[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Enable DC9 as lowest possible state during screen-off (rev6)
== Series Details == Series: drm/i915/icl: Enable DC9 as lowest possible state during screen-off (rev6) URL : https://patchwork.freedesktop.org/series/49447/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5052_full -> Patchwork_10638_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10638_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_schedule@pi-ringfull-bsd: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@gem_tiled_blits@interruptible: shard-apl: PASS -> INCOMPLETE (fdo#103927) igt@gem_userptr_blits@readonly-unsync: shard-skl: NOTRUN -> INCOMPLETE (fdo#108074) igt@kms_busy@extended-modeset-hang-newfb-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +1 igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: shard-snb: NOTRUN -> DMESG-WARN (fdo#107956) +1 igt@kms_chv_cursor_fail@pipe-c-128x128-top-edge: shard-skl: NOTRUN -> FAIL (fdo#104671) igt@kms_color@pipe-c-degamma: shard-apl: PASS -> FAIL (fdo#104782) igt@kms_cursor_crc@cursor-256x256-sliding: shard-glk: PASS -> FAIL (fdo#103232) +3 igt@kms_cursor_crc@cursor-256x85-onscreen: shard-apl: NOTRUN -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-256x85-random: shard-apl: PASS -> FAIL (fdo#103232) +1 igt@kms_flip@2x-wf_vblank-ts-check: shard-snb: SKIP -> INCOMPLETE (fdo#105411) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt: shard-glk: PASS -> FAIL (fdo#103167) +2 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: shard-apl: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-stridechange: shard-skl: NOTRUN -> FAIL (fdo#105683) igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc: shard-skl: NOTRUN -> FAIL (fdo#103167) +1 igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#108145, fdo#107815) igt@kms_plane_alpha_blend@pipe-c-alpha-7efc: shard-apl: NOTRUN -> FAIL (fdo#108145) igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: shard-skl: NOTRUN -> FAIL (fdo#108145) igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-apl: PASS -> FAIL (fdo#103166) +2 igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) shard-snb: NOTRUN -> FAIL (fdo#99912) igt@pm_rpm@gem-evict-pwrite: shard-skl: NOTRUN -> INCOMPLETE (fdo#107807) Possible fixes igt@gem_eio@in-flight-contexts-1us: shard-glk: FAIL (fdo#105957) -> PASS igt@kms_busy@extended-modeset-hang-newfb-render-c: shard-kbl: DMESG-WARN (fdo#107956) -> PASS igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: shard-hsw: DMESG-WARN (fdo#107956) -> PASS igt@kms_ccs@pipe-a-crc-sprite-planes-basic: shard-glk: FAIL (fdo#108145) -> PASS igt@kms_color@pipe-a-degamma: shard-apl: FAIL (fdo#108145, fdo#104782) -> PASS igt@kms_cursor_crc@cursor-128x128-suspend: shard-apl: FAIL (fdo#103191, fdo#103232) -> PASS igt@kms_cursor_crc@cursor-256x256-random: shard-glk: FAIL (fdo#103232) -> PASS igt@kms_cursor_crc@cursor-64x21-sliding: shard-apl: FAIL (fdo#103232) -> PASS +1 igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled: shard-glk: FAIL (fdo#103184) -> PASS +1 igt@kms_flip@plain-flip-fb-recreate: shard-skl: FAIL (fdo#100368) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-apl: FAIL (fdo#103167) -> PASS +2 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: shard-apl: INCOMPLETE (fdo#103927) -> PASS +1 igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS igt@kms_vblank@pipe-c-wait-busy: shard-kbl: DMESG-WARN (fdo#103558, fdo#105602) -> PASS +3 fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103232 https://bugs.freedesk
[Intel-gfx] [PATCH] drm/i915/gtt: Revert "Disable read-only support under GVT"
From: Hang Yuan This reverts commit c9e666880de5a1fed04dc412b046916d542b72dd. Checked GVT codes that guest PPGTT PTE flag bits are propagated to shadow PTE. Read/write bit is not changed. Further tested by i915 self-test case "igt_ctx_readonly". No error or GPU hang was detected. So enable read-only support under GVT. Signed-off-by: Hang Yuan --- drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 19b2d99..bdf9f9f 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1602,12 +1602,8 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915) 1ULL << 48 : 1ULL << 32; - /* -* From bdw, there is support for read-only pages in the PPGTT. -* -* XXX GVT is not honouring the lack of RW in the PTE bits. -*/ - ppgtt->vm.has_read_only = !intel_vgpu_active(i915); + /* From bdw, there is support for read-only pages in the PPGTT. */ + ppgtt->vm.has_read_only = true; i915_address_space_init(&ppgtt->vm, i915); -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftest: fix 64K alignment in igt_write_huge
Hi Matthew,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.19 next-20181029]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Matthew-Auld/drm-i915-selftest-fix-64K-alignment-in-igt_write_huge/20181030-034107
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All warnings (new ones prefixed by >>):
In file included from include/linux/list.h:9:0,
from include/linux/agp_backend.h:33,
from include/drm/drmP.h:35,
from drivers/gpu/drm/i915/i915_gem.c:28:
drivers/gpu/drm/i915/selftests/huge_pages.c: In function 'igt_write_huge':
include/linux/kernel.h:845:29: warning: comparison of distinct pointer types
lacks a cast
(!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
^
include/linux/kernel.h:859:4: note: in expansion of macro '__typecheck'
(__typecheck(x, y) && __no_side_effects(x, y))
^~~
include/linux/kernel.h:869:24: note: in expansion of macro '__safe_cmp'
__builtin_choose_expr(__safe_cmp(x, y), \
^~
include/linux/kernel.h:885:19: note: in expansion of macro '__careful_cmp'
#define max(x, y) __careful_cmp(x, y, >)
^
>> drivers/gpu/drm/i915/selftests/huge_pages.c:1132:15: note: in expansion of
>> macro 'max'
alignment = max(alignment, I915_GTT_PAGE_SIZE_2M);
^~~
vim +/max +1132 drivers/gpu/drm/i915/selftests/huge_pages.c
1106
1107 static int igt_write_huge(struct i915_gem_context *ctx,
1108struct drm_i915_gem_object *obj)
1109 {
1110 struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct i915_address_space *vm =
1112 ctx->ppgtt ? &ctx->ppgtt->vm : &i915->ggtt.vm;
1113 static struct intel_engine_cs *engines[I915_NUM_ENGINES];
1114 struct intel_engine_cs *engine;
1115 I915_RND_STATE(prng);
1116 IGT_TIMEOUT(end_time);
1117 unsigned int id;
1118 u64 alignment;
1119 u64 max;
1120 u64 num;
1121 u64 size;
1122 int *order;
1123 int i, n;
1124 int err = 0;
1125
1126 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
1127
1128 size = obj->base.size;
1129 alignment = rounddown_pow_of_two(obj->mm.page_sizes.sg);
1130 if (obj->mm.page_sizes.sg & I915_GTT_PAGE_SIZE_64K) {
1131 size = round_up(size, I915_GTT_PAGE_SIZE_2M);
> 1132 alignment = max(alignment, I915_GTT_PAGE_SIZE_2M);
1133 }
1134
1135 max = div_u64((vm->total - size), alignment);
1136
1137 n = 0;
1138 for_each_engine(engine, i915, id) {
1139 if (!intel_engine_can_store_dword(engine)) {
1140 pr_info("store-dword-imm not supported on
engine=%u\n",
1141 id);
1142 continue;
1143 }
1144 engines[n++] = engine;
1145 }
1146
1147 if (!n)
1148 return 0;
1149
1150 /*
1151 * To keep things interesting when alternating between engines
in our
1152 * randomized order, lets also make feeding to the same engine
a few
1153 * times in succession a possibility by enlarging the
permutation array.
1154 */
1155 order = i915_random_order(n * I915_NUM_ENGINES, &prng);
1156 if (!order)
1157 return -ENOMEM;
1158
1159 /*
1160 * Try various offsets in an ascending/descending fashion until
we
1161 * timeout -- we want to avoid issues hidden by effectively
always using
1162 * offset = 0.
1163 */
1164 i = 0;
1165 for_each_prime_number_from(num, 0, max) {
1166 u64 offset_low = num * alignment;
1167 u64 offset_high = (max - num) * alignment;
1168 u32 dword = offset_in_page(num) / 4;
1169
1170 engine = engines[order[i] % n];
1171 i = (i + 1) % (n * I915_NUM_ENGINES);
1172
1173 err = __igt_write_huge(ctx, engine, obj, size,
offset_low,
1174
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/gtt: Revert "Disable read-only support under GVT"
== Series Details == Series: drm/i915/gtt: Revert "Disable read-only support under GVT" URL : https://patchwork.freedesktop.org/series/51730/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/gtt: Revert "Disable read-only support under GVT" -drivers/gpu/drm/i915/i915_gem_gtt.c:348:14: warning: expression using sizeof(void) -drivers/gpu/drm/i915/i915_gem_gtt.c:348:14: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:348:14: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_gem_gtt.c:348:14: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
== Series Details == Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming URL : https://patchwork.freedesktop.org/series/51711/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5052_full -> Patchwork_10641_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10641_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10641_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10641_full: === IGT changes === Warnings igt@perf_pmu@rc6: shard-kbl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10641_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_basic@readonly-bsd1: shard-snb: SKIP -> INCOMPLETE (fdo#105411) igt@gem_exec_schedule@pi-ringfull-bsd: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@gem_userptr_blits@readonly-unsync: shard-skl: NOTRUN -> INCOMPLETE (fdo#108074) igt@kms_busy@extended-modeset-hang-newfb-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +1 igt@kms_busy@extended-modeset-hang-newfb-render-b: shard-snb: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_color@pipe-a-legacy-gamma: shard-apl: PASS -> FAIL (fdo#104782, fdo#108145) igt@kms_cursor_crc@cursor-256x85-onscreen: shard-apl: NOTRUN -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-256x85-random: shard-apl: PASS -> FAIL (fdo#103232) +5 igt@kms_flip@2x-flip-vs-modeset: shard-hsw: PASS -> DMESG-WARN (fdo#102614) igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-skl: PASS -> FAIL (fdo#105363) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff: shard-apl: PASS -> FAIL (fdo#103167) +1 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc: shard-skl: NOTRUN -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-stridechange: shard-skl: NOTRUN -> FAIL (fdo#105683) +1 igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: shard-skl: NOTRUN -> FAIL (fdo#108145) +1 igt@kms_plane_alpha_blend@pipe-c-alpha-7efc: shard-apl: NOTRUN -> FAIL (fdo#108145) igt@kms_plane_multiple@atomic-pipe-b-tiling-x: shard-apl: PASS -> FAIL (fdo#103166) igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) igt@kms_sysfs_edid_timing: shard-skl: NOTRUN -> FAIL (fdo#100047) igt@kms_vblank@pipe-a-wait-busy-hang: shard-apl: PASS -> DMESG-WARN (fdo#106107) Possible fixes igt@gem_eio@in-flight-contexts-1us: shard-glk: FAIL (fdo#105957) -> PASS igt@kms_atomic_transition@1x-modeset-transitions-fencing: shard-skl: FAIL (fdo#108470, fdo#107815) -> PASS igt@kms_color@pipe-a-degamma: shard-apl: FAIL (fdo#104782, fdo#108145) -> PASS igt@kms_cursor_crc@cursor-128x128-suspend: shard-apl: FAIL (fdo#103191, fdo#103232) -> PASS igt@kms_cursor_crc@cursor-64x21-sliding: shard-apl: FAIL (fdo#103232) -> PASS +1 igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS +1 igt@kms_draw_crc@draw-method-rgb565-pwrite-ytiled: shard-glk: FAIL (fdo#103184) -> PASS +2 igt@kms_flip@plain-flip-fb-recreate: shard-skl: FAIL (fdo#100368) -> PASS igt@kms_flip_tiling@flip-x-tiled: shard-skl: FAIL (fdo#108145) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-apl: FAIL (fdo#103167) -> PASS +1 igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff: shard-glk: DMESG-FAIL (fdo#103167, fdo#106538) -> PASS igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: shard-apl: INCOMPLETE (fdo#103927) -> PASS +1 igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS igt@kms_vblank@pipe-c-wait-busy: shard-kbl: DMESG-WARN (fdo#103558, fdo#105602) -> PASS +3 igt@pm_rpm@system-suspend: shard-skl: INCOMPLETE (fdo#107807, fdo#107773, fdo#104108) -> PASS fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047 fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103166 https://bugs.freedeskt
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gtt: Revert "Disable read-only support under GVT"
== Series Details == Series: drm/i915/gtt: Revert "Disable read-only support under GVT" URL : https://patchwork.freedesktop.org/series/51730/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5053 -> Patchwork_10644 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/51730/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_10644 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: fi-kbl-soraka: NOTRUN -> INCOMPLETE (fdo#107859, fdo#107556, fdo#107774) igt@kms_flip@basic-flip-vs-modeset: fi-hsw-4770r: PASS -> DMESG-WARN (fdo#105602) igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: PASS -> FAIL (fdo#103167) igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) Possible fixes igt@drv_getparams_basic@basic-eu-total: fi-kbl-7560u: INCOMPLETE (fdo#103665) -> PASS igt@drv_module_reload@basic-reload: fi-glk-j4005: DMESG-WARN (fdo#106725, fdo#106248) -> PASS igt@gem_exec_suspend@basic-s3: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: FAIL (fdo#100368) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-byt-clapper: FAIL (fdo#107362, fdo#103191) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248 fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774 fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859 == Participating hosts (47 -> 43) == Additional (1): fi-kbl-soraka Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5053 -> Patchwork_10644 CI_DRM_5053: fb5dde5f5303ed6eb6099f9435762ed70b3bfdb0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10644: cdbbe952e00992c1910756136b60be6341f14300 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == cdbbe952e009 drm/i915/gtt: Revert "Disable read-only support under GVT" == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10644/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915: Remove CNL from WA 827 (rev3)
== Series Details == Series: series starting with [1/5] drm/i915: Remove CNL from WA 827 (rev3) URL : https://patchwork.freedesktop.org/series/51713/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5052_full -> Patchwork_10642_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10642_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_schedule@pi-ringfull-bsd: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@kms_busy@extended-modeset-hang-newfb-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: shard-snb: NOTRUN -> DMESG-WARN (fdo#107956) +1 igt@kms_cursor_crc@cursor-128x42-offscreen: shard-skl: NOTRUN -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-256x256-random: shard-apl: PASS -> FAIL (fdo#103232) +1 igt@kms_cursor_crc@cursor-256x256-suspend: shard-skl: NOTRUN -> INCOMPLETE (fdo#104108) igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled: shard-skl: NOTRUN -> FAIL (fdo#103232, fdo#103184) igt@kms_flip_tiling@flip-to-x-tiled: shard-skl: NOTRUN -> FAIL (fdo#108134) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: shard-apl: PASS -> FAIL (fdo#103167) +1 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu: shard-skl: NOTRUN -> FAIL (fdo#105682) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc: shard-skl: NOTRUN -> FAIL (fdo#103167) +4 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: shard-glk: PASS -> FAIL (fdo#103167) igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#107815, fdo#108145) igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: shard-skl: NOTRUN -> FAIL (fdo#108145) igt@kms_plane_alpha_blend@pipe-c-alpha-7efc: shard-apl: NOTRUN -> FAIL (fdo#108145) igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-apl: PASS -> FAIL (fdo#103166) +1 igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) shard-snb: NOTRUN -> FAIL (fdo#99912) igt@kms_sysfs_edid_timing: shard-skl: NOTRUN -> FAIL (fdo#100047) igt@perf@blocking: shard-hsw: PASS -> FAIL (fdo#102252) Possible fixes igt@gem_eio@in-flight-contexts-1us: shard-glk: FAIL (fdo#105957) -> PASS igt@kms_color@pipe-a-degamma: shard-apl: FAIL (fdo#108145, fdo#104782) -> PASS igt@kms_cursor_crc@cursor-128x128-suspend: shard-apl: FAIL (fdo#103232, fdo#103191) -> PASS igt@kms_cursor_crc@cursor-64x64-dpms: shard-apl: FAIL (fdo#103232) -> PASS +1 igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled: shard-glk: FAIL (fdo#103184) -> PASS +1 igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt: shard-apl: FAIL (fdo#103167) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen: shard-glk: FAIL (fdo#103167) -> PASS +1 igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: shard-apl: INCOMPLETE (fdo#103927) -> PASS +1 igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: shard-skl: FAIL (fdo#107815) -> PASS igt@kms_plane_multiple@atomic-pipe-a-tiling-yf: shard-apl: FAIL (fdo#103166) -> PASS igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS +2 igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS igt@kms_vblank@pipe-c-wait-busy: shard-kbl: DMESG-WARN (fdo#103558, fdo#105602) -> PASS +3 igt@pm_rpm@system-suspend: shard-skl: INCOMPLETE (fdo#107773, fdo#107807, fdo#104108) -> PASS fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047 fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252 fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#104782
[Intel-gfx] [PATCH v3 4/4] drm/i915/icl: WaAllowUMDToModifySamplerMode
From: Oscar Mateo
Required for Bindless samplers.
Userspace consumer: mesa
V2: Rebase
V3: Update commit message
Cc: Anusha Srivatsa
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f76fa13a12a2..050fedb4fc81 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8648,6 +8648,8 @@ enum {
#define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
+#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
+
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD
Error Status 1 */
#define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 896874278852..d7176213e3ce 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1018,6 +1018,9 @@ static void icl_whitelist_build(struct whitelist *w)
{
/* WaAllowUMDToModifyHalfSliceChicken7:icl */
whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
+
+ /* WaAllowUMDToModifySamplerMode:icl */
+ whitelist_reg(w, GEN10_SAMPLER_MODE);
}
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
--
2.9.3
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[Intel-gfx] [PATCH v3 1/4] drm/i915/icl: Add WaEnable32PlaneMode
Gen11 Display suports 32 planes in total. Enable the new format in context
status to be used and expanded to 32 planes.
V2: Move the WA to display WA's(Chris)
Cc: Chris Wilson
Cc: Michel Thierry
Cc: James Ausmus
Reviewed-by: Anusha Srivatsa
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bcee91bcfba6..f76fa13a12a2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2537,6 +2537,7 @@ enum i915_power_well_id {
/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
+#define GEN11_ENABLE_32_PLANE_MODE (1 << 7)
/* WaClearTdlStateAckDirtyBits */
#define GEN8_STATE_ACK _MMIO(0x20F0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 82c82e233154..32d051fd45ee 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8865,6 +8865,10 @@ static void icl_init_clock_gating(struct
drm_i915_private *dev_priv)
/* This is not an Wa. Enable to reduce Sampler power */
I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
+
+ /* WaEnable32PlaneMode:icl */
+ I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
+ _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
}
static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
--
2.9.3
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[Intel-gfx] [PATCH v3 2/4] drm/i915/icl: Implement Display WA_1405510057
Display WA_1405510057 asks to not enable YUV 420 HDMI 10bpc when horizontal blank size mod 8 reminder is 2. V2: Rebase(r-b: Anusha) V3: crtc_state->s/ycbcr420/output_format/ Cc: Anusha Srivatsa Cc: Paulo Zanoni Cc: Rodrigo Vivi Cc: Ville Syrjälä Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/intel_hdmi.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 129b880bce64..6c6c4dd12fd5 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1595,6 +1595,8 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, struct drm_atomic_state *state = crtc_state->base.state; struct drm_connector_state *connector_state; struct drm_connector *connector; + const struct drm_display_mode *adjusted_mode = + &crtc_state->base.adjusted_mode; int i; if (HAS_GMCH_DISPLAY(dev_priv)) @@ -1643,7 +1645,14 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, /* Display WA #1139: glk */ if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && - crtc_state->base.adjusted_mode.htotal > 5460) + adjusted_mode->htotal > 5460) + return false; + + /* Display Wa_1405510057:icl */ + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && + bpc == 10 && IS_ICELAKE(dev_priv) && + (adjusted_mode->crtc_hblank_end - +adjusted_mode->crtc_hblank_start) % 8 == 2) return false; return true; -- 2.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 3/4] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
From: Oscar Mateo
Required to dinamically set 'Trilinear Filter Quality Mode'
Userpsace consumer is mesa.
V2: Rebase
V3: Update commit message
Cc: Mika Kuoppala
Cc: Anusha Srivatsa
Signed-off-by: Oscar Mateo
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_workarounds.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 01b9b7591c5d..896874278852 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1016,6 +1016,8 @@ static void cnl_whitelist_build(struct whitelist *w)
static void icl_whitelist_build(struct whitelist *w)
{
+ /* WaAllowUMDToModifyHalfSliceChicken7:icl */
+ whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
}
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
--
2.9.3
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Re: [Intel-gfx] [PATCH] RFC: Make igts for cross-driver stuff mandatory?
On Tue, Oct 30, 2018 at 12:17:30PM +1000, Dave Airlie wrote: > On Fri, 19 Oct 2018 at 18:51, Daniel Vetter wrote: > > > > Hi all, > > > > This is just to collect feedback on this idea, and see whether the > > overall dri-devel community stands on all this. I think the past few > > cross-vendor uapi extensions all came with igts attached, and > > personally I think there's lots of value in having them: A > > cross-vendor interface isn't useful if every driver implements it > > slightly differently. > > > > I think there's 2 questions here: > > > > - Do we want to make such testcases mandatory? > > Yes I think if at all practical it probably makes sense to have some > mandatory test cases for all cross-vendor features, or features that > might become cross vendor in the future. I've created a few patches to test that in gitlab CI. I think the only thing left now is CI'ing sysroot builds, but I don't know how to do that myself. > > - If yes, are we there yet, or is there something crucially missing > > still? > > I think the does igt build in all the places needed is the main one, > I've no idea what a baseline IGT test run looks like on non-intel hw, > how useful is it? We're in the process of moving i915 tests into a tests/i915/ subfolder. I think after that we could try to them on some hardware (my long term plan is to use vkms for that and put it into gitlab CI with qemu). We have accidentally run igts on amdgpu instead of i915 on KBL-G (and our CI found at least one bug in one of my refactor series), so stuff works :-) Coverage is a bit a mixed bag I think, but that's always the case when you retrofit a testsuite. -Daniel > > Acked-by: Dave Airlie -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/4] drm/dp_mst: Start tracking per-port VCPI allocations
On Mon, Oct 29, 2018 at 03:24:29PM +0100, Daniel Vetter wrote:
> On Fri, Oct 26, 2018 at 04:35:47PM -0400, Lyude Paul wrote:
> > There has been a TODO waiting for quite a long time in
> > drm_dp_mst_topology.c:
> >
> > /* We cannot rely on port->vcpi.num_slots to update
> > * topology_state->avail_slots as the port may not exist if the parent
> > * branch device was unplugged. This should be fixed by tracking
> > * per-port slot allocation in drm_dp_mst_topology_state instead of
> > * depending on the caller to tell us how many slots to release.
> > */
> >
> > That's not the only reason we should fix this: forcing the driver to
> > track the VCPI allocations throughout a state's atomic check is
> > error prone, because it means that extra care has to be taken with the
> > order that drm_dp_atomic_find_vcpi_slots() and
> > drm_dp_atomic_release_vcpi_slots() are called in in order to ensure
> > idempotency. Currently the only driver actually using these helpers,
> > i915, doesn't even do this correctly: multiple ->best_encoder() checks
> > with i915's current implementation would not be idempotent and would
> > over-allocate VCPI slots, something I learned trying to implement
> > fallback retraining in MST.
> >
> > So: simplify this whole mess, and teach drm_dp_atomic_find_vcpi_slots()
> > and drm_dp_atomic_release_vcpi_slots() to track the VCPI allocations for
> > each port. This allows us to ensure idempotency without having to rely
> > on the driver as much. Additionally: the driver doesn't need to do any
> > kind of VCPI slot tracking anymore if it doesn't need it for it's own
> > internal state.
> >
> > Additionally; this adds a new drm_dp_mst_atomic_check() helper which
> > must be used by atomic drivers to perform validity checks for the new
> > VCPI allocations incurred by a state.
> >
> > Also: update the documentation and make it more obvious that these
> > /must/ be called by /all/ atomic drivers supporting MST.
> >
> > Changes since v1:
> > - Don't use the now-removed ->atomic_check() for private objects hook,
> >just give drivers a function to call themselves
> >
> > Signed-off-by: Lyude Paul
> > Cc: Daniel Vetter
> > ---
> > drivers/gpu/drm/drm_dp_mst_topology.c | 190 +-
> > drivers/gpu/drm/i915/intel_display.c | 8 ++
> > drivers/gpu/drm/i915/intel_dp_mst.c | 31 +++--
> > include/drm/drm_dp_mst_helper.h | 11 +-
> > 4 files changed, 192 insertions(+), 48 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> > b/drivers/gpu/drm/drm_dp_mst_topology.c
> > index 8c3cfac437f4..dcfab7536914 100644
> > --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> > @@ -2614,21 +2614,33 @@ static int drm_dp_init_vcpi(struct
> > drm_dp_mst_topology_mgr *mgr,
> > }
> >
> > /**
> > - * drm_dp_atomic_find_vcpi_slots() - Find and add vcpi slots to the state
> > + * drm_dp_atomic_find_vcpi_slots() - Find and add VCPI slots to the state
> > * @state: global atomic state
> > * @mgr: MST topology manager for the port
> > * @port: port to find vcpi slots for
> > * @pbn: bandwidth required for the mode in PBN
> > *
> > + * Allocates VCPI slots to @port, replacing any previous VCPI allocations
> > it
> > + * may have had. Any atomic drivers which support MST must call this
> > function
> > + * in their atomic_check() handlers to change the current VCPI allocation
> > for
>
> Maybe do a nice kerneldoc reference to the right atomic_check here.
>
> > + * the new state. After the ->atomic_check() hooks of the driver and all
> > other
>
> This will upset the kerneldoc parser I think.
>
> > + * mode objects in the state have been called, DRM will check the final
> > VCPI
> > + * allocations to ensure that they will fit into the available bandwidth on
> > + * the topology.
> > + *
> > + * See also: drm_dp_atomic_release_vcpi_slots()
>
> Also need to reference drm_dp_mst_atomic_check() here and that drivers
> must call it or nothing happens.
> > + *
> > * RETURNS:
> > - * Total slots in the atomic state assigned for this port or error
> > + * Total slots in the atomic state assigned for this port, or a negative
> > error
> > + * code if the port no longer exists
> > */
> > int drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state,
> > struct drm_dp_mst_topology_mgr *mgr,
> > struct drm_dp_mst_port *port, int pbn)
> > {
> > struct drm_dp_mst_topology_state *topology_state;
> > - int req_slots;
> > + struct drm_dp_vcpi_allocation *pos, *vcpi = NULL;
> > + int prev_slots, req_slots, ret;
> >
> > topology_state = drm_atomic_get_mst_topology_state(state, mgr);
> > if (IS_ERR(topology_state))
> > @@ -2637,20 +2649,41 @@ int drm_dp_atomic_find_vcpi_slots(struct
> > drm_atomic_state *state,
> > port = drm_dp_get_validated_port_ref(mgr, port);
> > if (port == NULL)
> >
Re: [Intel-gfx] [PATCH v3 4/4] drm/i915/icl: WaAllowUMDToModifySamplerMode
Quoting Radhakrishna Sripada (2018-10-30 08:45:04)
> From: Oscar Mateo
>
> Required for Bindless samplers.
> Userspace consumer: mesa
>
> V2: Rebase
> V3: Update commit message
>
> Cc: Anusha Srivatsa
> Cc: Mika Kuoppala
> Signed-off-by: Oscar Mateo
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f76fa13a12a2..050fedb4fc81 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8648,6 +8648,8 @@ enum {
> #define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
> #define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
>
> +#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
> +
> /* IVYBRIDGE DPF */
> #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /*
> L3CD Error Status 1 */
> #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> b/drivers/gpu/drm/i915/intel_workarounds.c
> index 896874278852..d7176213e3ce 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -1018,6 +1018,9 @@ static void icl_whitelist_build(struct whitelist *w)
> {
> /* WaAllowUMDToModifyHalfSliceChicken7:icl */
> whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
> +
> + /* WaAllowUMDToModifySamplerMode:icl */
> + whitelist_reg(w, GEN10_SAMPLER_MODE);
Hmm, we need the basic subtests of gem_workarounds in BAT to have any
coverage of this code.
-Chris
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v3,1/4] drm/i915/icl: Add WaEnable32PlaneMode
== Series Details == Series: series starting with [v3,1/4] drm/i915/icl: Add WaEnable32PlaneMode URL : https://patchwork.freedesktop.org/series/51736/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5053 -> Patchwork_10645 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10645 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10645, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51736/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10645: === IGT changes === Possible regressions igt@drv_selftest@live_hangcheck: fi-skl-iommu: PASS -> INCOMPLETE Warnings igt@drv_selftest@live_guc: fi-skl-iommu: PASS -> SKIP +1 == Known issues == Here are the changes found in Patchwork_10645 that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s4-devices: fi-blb-e6850: NOTRUN -> INCOMPLETE (fdo#107718) igt@kms_pipe_crc_basic@hang-read-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) +1 Possible fixes igt@drv_getparams_basic@basic-eu-total: fi-kbl-7560u: INCOMPLETE (fdo#103665) -> PASS igt@drv_module_reload@basic-reload: fi-glk-j4005: DMESG-WARN (fdo#106725, fdo#106248) -> PASS igt@gem_exec_suspend@basic-s3: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: FAIL (fdo#100368) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248 fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 == Participating hosts (47 -> 41) == Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 == Build changes == * Linux: CI_DRM_5053 -> Patchwork_10645 CI_DRM_5053: fb5dde5f5303ed6eb6099f9435762ed70b3bfdb0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10645: e70001aa2cbf474303af8e09f96123b7be77d6e0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e70001aa2cbf drm/i915/icl: WaAllowUMDToModifySamplerMode 438b479a73ab drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7 d1a3aabde515 drm/i915/icl: Implement Display WA_1405510057 a1e4353acc17 drm/i915/icl: Add WaEnable32PlaneMode == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10645/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/icl: Implement Display WA_1405510057
Hi Radhakrishna,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.19 next-20181030]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Radhakrishna-Sripada/drm-i915-icl-Add-WaEnable32PlaneMode/20181030-164539
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x005-201843 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
drivers/gpu//drm/i915/intel_hdmi.c: In function 'hdmi_deep_color_possible':
>> drivers/gpu//drm/i915/intel_hdmi.c:1654:18: error: 'const struct
>> intel_crtc_state' has no member named 'output_format'; did you mean
>> 'output_types'?
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
^
output_types
>> drivers/gpu//drm/i915/intel_hdmi.c:1654:35: error:
>> 'INTEL_OUTPUT_FORMAT_YCBCR420' undeclared (first use in this function); did
>> you mean 'INTEL_OUTPUT_DP_MST'?
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
^~~~
INTEL_OUTPUT_DP_MST
drivers/gpu//drm/i915/intel_hdmi.c:1654:35: note: each undeclared identifier
is reported only once for each function it appears in
vim +1654 drivers/gpu//drm/i915/intel_hdmi.c
1591
1592 static bool hdmi_deep_color_possible(const struct intel_crtc_state
*crtc_state,
1593 int bpc)
1594 {
1595 struct drm_i915_private *dev_priv =
1596 to_i915(crtc_state->base.crtc->dev);
1597 struct drm_atomic_state *state = crtc_state->base.state;
1598 struct drm_connector_state *connector_state;
1599 struct drm_connector *connector;
1600 const struct drm_display_mode *adjusted_mode =
1601 &crtc_state->base.adjusted_mode;
1602 int i;
1603
1604 if (HAS_GMCH_DISPLAY(dev_priv))
1605 return false;
1606
1607 if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
1608 return false;
1609
1610 if (crtc_state->pipe_bpp <= 8*3)
1611 return false;
1612
1613 if (!crtc_state->has_hdmi_sink)
1614 return false;
1615
1616 /*
1617 * HDMI deep color affects the clocks, so it's only possible
1618 * when not cloning with other encoder types.
1619 */
1620 if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1621 return false;
1622
1623 for_each_new_connector_in_state(state, connector,
connector_state, i) {
1624 const struct drm_display_info *info =
&connector->display_info;
1625
1626 if (connector_state->crtc != crtc_state->base.crtc)
1627 continue;
1628
1629 if (crtc_state->ycbcr420) {
1630 const struct drm_hdmi_info *hdmi = &info->hdmi;
1631
1632 if (bpc == 12 && !(hdmi->y420_dc_modes &
1633 DRM_EDID_YCBCR420_DC_36))
1634 return false;
1635 else if (bpc == 10 && !(hdmi->y420_dc_modes &
1636
DRM_EDID_YCBCR420_DC_30))
1637 return false;
1638 } else {
1639 if (bpc == 12 && !(info->edid_hdmi_dc_modes &
1640 DRM_EDID_HDMI_DC_36))
1641 return false;
1642 else if (bpc == 10 &&
!(info->edid_hdmi_dc_modes &
1643 DRM_EDID_HDMI_DC_30))
1644 return false;
1645 }
1646 }
1647
1648 /* Display WA #1139: glk */
1649 if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1650 adjusted_mode->htotal > 5460)
1651 return false;
1652
1653 /* Display Wa_1405510057:icl */
> 1654 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1655 bpc == 10 && IS_ICELAKE(dev_priv) &
Re: [Intel-gfx] [PATCH v3 4/4] drm/i915/icl: WaAllowUMDToModifySamplerMode
Quoting Chris Wilson (2018-10-30 09:12:20)
> Quoting Radhakrishna Sripada (2018-10-30 08:45:04)
> > From: Oscar Mateo
> >
> > Required for Bindless samplers.
> > Userspace consumer: mesa
> >
> > V2: Rebase
> > V3: Update commit message
> >
> > Cc: Anusha Srivatsa
> > Cc: Mika Kuoppala
> > Signed-off-by: Oscar Mateo
> > Signed-off-by: Radhakrishna Sripada
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 2 ++
> > drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
> > 2 files changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index f76fa13a12a2..050fedb4fc81 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8648,6 +8648,8 @@ enum {
> > #define GAMW_ECO_DEV_RW_IA_REG _MMIO(0x4080)
> > #define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7)
> >
> > +#define GEN10_SAMPLER_MODE _MMIO(0xE18C)
> > +
> > /* IVYBRIDGE DPF */
> > #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /*
> > L3CD Error Status 1 */
> > #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
> > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> > b/drivers/gpu/drm/i915/intel_workarounds.c
> > index 896874278852..d7176213e3ce 100644
> > --- a/drivers/gpu/drm/i915/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> > @@ -1018,6 +1018,9 @@ static void icl_whitelist_build(struct whitelist *w)
> > {
> > /* WaAllowUMDToModifyHalfSliceChicken7:icl */
> > whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
> > +
> > + /* WaAllowUMDToModifySamplerMode:icl */
> > + whitelist_reg(w, GEN10_SAMPLER_MODE);
>
> Hmm, we need the basic subtests of gem_workarounds in BAT to have any
> coverage of this code.
Nah, we have live_reset_whitelist() to provide basic coverage in BAT.
-Chris
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Re: [Intel-gfx] [PATCH v3 2/4] drm/i915/icl: Implement Display WA_1405510057
Hi Radhakrishna,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.19 next-20181030]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Radhakrishna-Sripada/drm-i915-icl-Add-WaEnable32PlaneMode/20181030-164539
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x075-201843 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All warnings (new ones prefixed by >>):
In file included from include/linux/string.h:6:0,
from include/linux/uuid.h:20,
from include/linux/mod_devicetable.h:13,
from include/linux/i2c.h:29,
from drivers/gpu/drm/i915/intel_hdmi.c:29:
drivers/gpu/drm/i915/intel_hdmi.c: In function 'hdmi_deep_color_possible':
drivers/gpu/drm/i915/intel_hdmi.c:1654:18: error: 'const struct
intel_crtc_state' has no member named 'output_format'; did you mean
'output_types'?
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
^
include/linux/compiler.h:58:30: note: in definition of macro '__trace_if'
if (__builtin_constant_p(!!(cond)) ? !!(cond) : \
^~~~
>> drivers/gpu/drm/i915/intel_hdmi.c:1654:2: note: in expansion of macro 'if'
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
^~
drivers/gpu/drm/i915/intel_hdmi.c:1654:35: error:
'INTEL_OUTPUT_FORMAT_YCBCR420' undeclared (first use in this function); did you
mean 'INTEL_OUTPUT_DP_MST'?
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
^
include/linux/compiler.h:58:30: note: in definition of macro '__trace_if'
if (__builtin_constant_p(!!(cond)) ? !!(cond) : \
^~~~
>> drivers/gpu/drm/i915/intel_hdmi.c:1654:2: note: in expansion of macro 'if'
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
^~
drivers/gpu/drm/i915/intel_hdmi.c:1654:35: note: each undeclared identifier
is reported only once for each function it appears in
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
^
include/linux/compiler.h:58:30: note: in definition of macro '__trace_if'
if (__builtin_constant_p(!!(cond)) ? !!(cond) : \
^~~~
>> drivers/gpu/drm/i915/intel_hdmi.c:1654:2: note: in expansion of macro 'if'
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
^~
drivers/gpu/drm/i915/intel_hdmi.c:1654:18: error: 'const struct
intel_crtc_state' has no member named 'output_format'; did you mean
'output_types'?
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
^
include/linux/compiler.h:58:42: note: in definition of macro '__trace_if'
if (__builtin_constant_p(!!(cond)) ? !!(cond) : \
^~~~
>> drivers/gpu/drm/i915/intel_hdmi.c:1654:2: note: in expansion of macro 'if'
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
^~
drivers/gpu/drm/i915/intel_hdmi.c:1654:18: error: 'const struct
intel_crtc_state' has no member named 'output_format'; did you mean
'output_types'?
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
^
include/linux/compiler.h:69:16: note: in definition of macro '__trace_if'
__r = !!(cond); \
^~~~
>> drivers/gpu/drm/i915/intel_hdmi.c:1654:2: note: in expansion of macro 'if'
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
^~
vim +/if +1654 drivers/gpu/drm/i915/intel_hdmi.c
1591
1592 static bool hdmi_deep_color_possible(const struct intel_crtc_state
*crtc_state,
1593 int bpc)
1594 {
1595 struct drm_i915_private *dev_priv =
1596 to_i915(crtc_state->base.crtc->dev);
1597 struct drm_atomic_state *state = crtc_state->base.state;
1598 struct drm_connector_state *connector_state;
1599 struct drm_connector *connector;
1600 const struct drm_display_mode *adjusted_mode =
1601 &crtc_state->base.adjusted_mode;
1602 int i;
1603
1604 if (HAS_GMCH_DISPLA
Re: [Intel-gfx] [PATCH] drm/i915/execlists: Poison the CSB after use
Chris Wilson writes:
> After reading the event status from the CSB, write back 0 (an invalid
> value) so we can detect if the HW should signal a new event without
> writing the event in the future.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=108315
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 22b57b8926fc..126efe20d2d6 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -910,6 +910,9 @@ static void process_csb(struct intel_engine_cs *engine)
> execlists->active);
>
> status = buf[2 * head];
> + GEM_BUG_ON(!status);
Assuming we still have a timing issue in here, how about
we poll a little until status != 0 and then continue with warning?
We could recover by finding the 'bit late' status, instead of
oopsing out.
> + GEM_DEBUG_EXEC(WRITE_ONCE(*(u32 *)(buf + 2 * head), 0));
What I am afraid here is that we change the timing and cache dynamics
for our debug builds so that we bury the pesky thing.
Perhaps I am wandering too far but lets consider for the csb loop:
read head,tail;
rmb();
for_each_csb() {
64 bit read
64 bit write to zero it, unconditionally
act_on_it()
}
Too heavy?
Thanks,
Mika
> +
> if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE |
> GEN8_CTX_STATUS_PREEMPTED))
> execlists_set_active(execlists,
> --
> 2.19.1
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Re: [Intel-gfx] [PATCH v4 1/2] drm: Add drm_any_plane_has_format()
On Mon, Oct 29, 2018 at 04:00:04PM -0700, Eric Anholt wrote: > Ville Syrjala writes: > > > From: Ville Syrjälä > > > > Add a function to check whether there is at least one plane that > > supports a specific format and modifier combination. Drivers can > > use this to reject unsupported formats/modifiers in .fb_create(). > > > > v2: Accept anyformat if the driver doesn't do planes (Eric) > > s/planes_have_format/any_plane_has_format/ (Eric) > > Check the modifier as well since we already have a function > > that does both > > v3: Don't do the check in the core since we may not know the > > modifier yet, instead export the function and let drivers > > call it themselves > > > > Cc: Eric Anholt > > Cc: Dhinakaran Pandiyan > > Signed-off-by: Ville Syrjälä > > Reviewed-by: Dhinakaran Pandiyan > > I don't particularly see the point in having FB creation duplicate the > validation that atomic check will eventually do, and it means that FB > creation cost scales with plane count, but if i915's going to do this, > it seems reasonable for them. atomic_check checks for a given plane only, I do think it makes sense to make sure you can't create framebuffers that are impossible to use on a given driver at addfb time. In case the overhead is ever critical, we could compile a static map of this at driver load time, and then check that. Aside: Shouldn't we make this the default for atomic drivers? With atomic drivers we can assume that all planes have valid format lists (because atomic_check checks them already). Only with non-atomic drivers, how might have a faked primary plane is this not a valid assumption ... -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/execlists: Poison the CSB after use
Quoting Mika Kuoppala (2018-10-30 09:31:56)
> Chris Wilson writes:
>
> > After reading the event status from the CSB, write back 0 (an invalid
> > value) so we can detect if the HW should signal a new event without
> > writing the event in the future.
> >
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=108315
> > Signed-off-by: Chris Wilson
> > Cc: Mika Kuoppala
> > ---
> > drivers/gpu/drm/i915/intel_lrc.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> > b/drivers/gpu/drm/i915/intel_lrc.c
> > index 22b57b8926fc..126efe20d2d6 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -910,6 +910,9 @@ static void process_csb(struct intel_engine_cs *engine)
> > execlists->active);
> >
> > status = buf[2 * head];
> > + GEM_BUG_ON(!status);
>
> Assuming we still have a timing issue in here, how about
> we poll a little until status != 0 and then continue with warning?
If there's any race condition here, we definitely do not want to paper
over it.
> We could recover by finding the 'bit late' status, instead of
> oopsing out.
Oopsing out tells us where the problem is very concisely.
> > + GEM_DEBUG_EXEC(WRITE_ONCE(*(u32 *)(buf + 2 * head), 0));
>
> What I am afraid here is that we change the timing and cache dynamics
> for our debug builds so that we bury the pesky thing.
That too is a result.
> Perhaps I am wandering too far but lets consider for the csb loop:
>
> read head,tail;
> rmb();
>
> for_each_csb() {
> 64 bit read
> 64 bit write to zero it, unconditionally
> act_on_it()
> }
>
> Too heavy?
Too papery - shouts that we don't know what we or the hw is doing. We
want to pretend that we know what we are doing at least.
-Chris
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Re: [Intel-gfx] [RFC 1/4] drm/i915: Add Display Gen info.
On Mon, 29 Oct 2018, Rodrigo Vivi wrote: > Introduce Display Gen. The goal is to use this to minimize > the amount of platform codename checks we have nowdays on > display code. > > The introduction of a new platform should be just > gen >= current. So the patches 1-3 look nice for GLK. The thing that bugs me here is that this doesn't help VLV/CHV GMCH display at all. We'll still continue to have the more feature oriented HAS_GMCH_DISPLAY, HAS_DDI, and HAS_PCH_SPLIT. Haswell display is still better represented by HAS_DDI than gen because it's 7.5. Patch 4 means continued pedantic review about not mixing up IS_GEN and IS_DISPLAY_GEN. If we aren't strict about the separation, then what's the point? It's not immediately obvious that it's worth the hassle. Only time will tell. I'll want to hear more opinions before merging. One note inline below. BR, Jani. > > Just a gen++ without exposing any new feature or ip. > so this would minimize the amount of patches needed > for a bring-up specially holding them on internal branches. > > Cc: Jani Nikula > Cc: Lucas De Marchi > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/i915_drv.h | 28 ++-- > drivers/gpu/drm/i915/i915_pci.c | 5 - > drivers/gpu/drm/i915/intel_device_info.h | 2 ++ > 3 files changed, 32 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index c9e5bab6861b..3242229688e3 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2349,8 +2349,9 @@ intel_info(const struct drm_i915_private *dev_priv) > #define INTEL_INFO(dev_priv) intel_info((dev_priv)) > #define DRIVER_CAPS(dev_priv)(&(dev_priv)->caps) > > -#define INTEL_GEN(dev_priv) ((dev_priv)->info.gen) > -#define INTEL_DEVID(dev_priv)((dev_priv)->info.device_id) > +#define INTEL_GEN(dev_priv) ((dev_priv)->info.gen) > +#define INTEL_DISPLAY_GEN(dev_priv) ((dev_priv)->info.display_gen) > +#define INTEL_DEVID(dev_priv)((dev_priv)->info.device_id) > > #define REVID_FOREVER0xff > #define INTEL_REVID(dev_priv)((dev_priv)->drm.pdev->revision) > @@ -2363,6 +2364,8 @@ intel_info(const struct drm_i915_private *dev_priv) > /* Returns true if Gen is in inclusive range [Start, End] */ > #define IS_GEN(dev_priv, s, e) \ > (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e > +#define IS_DISPLAY_GEN(dev_priv, s, e) \ > + (!!((dev_priv)->info.display_gen_mask & INTEL_GEN_MASK((s), (e > > /* > * Return true if revision is in range [since,until] inclusive. > @@ -2532,6 +2535,27 @@ intel_info(const struct drm_i915_private *dev_priv) > #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9))) > #define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10))) > > +#define IS_DISPLAY_GEN2(dev_priv)(!!((dev_priv)->info.display_gen_mask \ > + & BIT(2))) > +#define IS_DISPLAY_GEN3(dev_priv)(!!((dev_priv)->info.display_gen_mask \ > + & BIT(3))) > +#define IS_DISPLAY_GEN4(dev_priv)(!!((dev_priv)->info.display_gen_mask \ > + & BIT(4))) > +#define IS_DISPLAY_GEN5(dev_priv)(!!((dev_priv)->info.display_gen_mask \ > + & BIT(5))) > +#define IS_DISPLAY_GEN6(dev_priv)(!!((dev_priv)->info.display_gen_mask \ > + & BIT(6))) > +#define IS_DISPLAY_GEN7(dev_priv)(!!((dev_priv)->info.display_gen_mask \ > + & BIT(7))) > +#define IS_DISPLAY_GEN8(dev_priv)(!!((dev_priv)->info.display_gen_mask \ > + & BIT(8))) > +#define IS_DISPLAY_GEN9(dev_priv)(!!((dev_priv)->info.display_gen_mask \ > + & BIT(9))) > +#define IS_DISPLAY_GEN10(dev_priv) (!!((dev_priv)->info.display_gen_mask \ > + & BIT(10))) > +#define IS_DISPLAY_GEN11(dev_priv) (!!((dev_priv)->info.display_gen_mask \ > + & BIT(11))) I know this is the same pattern as in IS_GEN above, but shouldn't the compiler end up with the same result if these were simply: #define IS_DISPLAY_GEN2(dev_priv) IS_DISPLAY_GEN(dev_priv, 2, 2) > + > #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) > #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv)) > #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index 44e745921ac1..fb8caf846c02 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -30,7 +30,10 @@ > #include "i915_selftest.h" > > #define PLATFORM(x) .platform = (x), .platform_mask = BIT(x) > -#define GEN(x) .gen = (x), .g
Re: [Intel-gfx] [PATCH] drm/i915/execlists: Poison the CSB after use
Chris Wilson writes:
> Quoting Mika Kuoppala (2018-10-30 09:31:56)
>> Chris Wilson writes:
>>
>> > After reading the event status from the CSB, write back 0 (an invalid
>> > value) so we can detect if the HW should signal a new event without
>> > writing the event in the future.
>> >
>> > References: https://bugs.freedesktop.org/show_bug.cgi?id=108315
>> > Signed-off-by: Chris Wilson
>> > Cc: Mika Kuoppala
>> > ---
>> > drivers/gpu/drm/i915/intel_lrc.c | 3 +++
>> > 1 file changed, 3 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c
>> > b/drivers/gpu/drm/i915/intel_lrc.c
>> > index 22b57b8926fc..126efe20d2d6 100644
>> > --- a/drivers/gpu/drm/i915/intel_lrc.c
>> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> > @@ -910,6 +910,9 @@ static void process_csb(struct intel_engine_cs *engine)
>> > execlists->active);
>> >
>> > status = buf[2 * head];
>> > + GEM_BUG_ON(!status);
>>
>> Assuming we still have a timing issue in here, how about
>> we poll a little until status != 0 and then continue with warning?
>
> If there's any race condition here, we definitely do not want to paper
> over it.
>
>> We could recover by finding the 'bit late' status, instead of
>> oopsing out.
>
> Oopsing out tells us where the problem is very concisely.
It would deliver the same information, so not papering over. Only
benefit is that with this signalling it wont be lost.
>
>> > + GEM_DEBUG_EXEC(WRITE_ONCE(*(u32 *)(buf + 2 * head), 0));
>>
>> What I am afraid here is that we change the timing and cache dynamics
>> for our debug builds so that we bury the pesky thing.
>
> That too is a result.
Agreed, so you want to observe behaviour with and without.
>> Perhaps I am wandering too far but lets consider for the csb loop:
>>
>> read head,tail;
>> rmb();
>>
>> for_each_csb() {
>> 64 bit read
>> 64 bit write to zero it, unconditionally
>> act_on_it()
>> }
>>
>> Too heavy?
>
> Too papery - shouts that we don't know what we or the hw is doing. We
> want to pretend that we know what we are doing at least.
Fair enough. Mainly the amount of reads with and without debugs, changes
inside the csb loop was my concern. But that view should be static to
cpu at this point regardless.
So lets try to find out what exactly how the hardware writes
the csb entries.
This patch does give us more details,
Reviewed-by: Mika Kuoppala
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Implement HDCP2.2: PART-I (rev2)
== Series Details == Series: Implement HDCP2.2: PART-I (rev2) URL : https://patchwork.freedesktop.org/series/51495/ State : failure == Summary == Applying: drm/i915: wrapping all hdcp var into intel_hdcp Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_debugfs.c M drivers/gpu/drm/i915/intel_display.c M drivers/gpu/drm/i915/intel_drv.h M drivers/gpu/drm/i915/intel_hdcp.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_hdcp.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_hdcp.c error: Failed to merge in the changes. Patch failed at 0001 drm/i915: wrapping all hdcp var into intel_hdcp Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10620/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/execlists: Poison the CSB after use
== Series Details == Series: drm/i915/execlists: Poison the CSB after use URL : https://patchwork.freedesktop.org/series/51703/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5054 -> Patchwork_10646 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10646 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10646, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51703/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10646: === IGT changes === Possible regressions igt@drv_selftest@live_gem: fi-bsw-kefka: PASS -> DMESG-WARN igt@prime_vgem@basic-fence-wait-default: fi-kbl-7560u: PASS -> INCOMPLETE == Known issues == Here are the changes found in Patchwork_10646 that come from known issues: === IGT changes === Issues hit igt@debugfs_test@read_all_entries: fi-icl-u2: PASS -> DMESG-WARN (fdo#108070) igt@gem_exec_suspend@basic-s3: fi-icl-u2: PASS -> DMESG-WARN (fdo#106612) igt@kms_flip@basic-flip-vs-modeset: fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998) Possible fixes igt@gem_ctx_create@basic-files: fi-icl-u2: DMESG-WARN (fdo#107724) -> PASS igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: FAIL (fdo#103167) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#106612 https://bugs.freedesktop.org/show_bug.cgi?id=106612 fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724 fdo#108070 https://bugs.freedesktop.org/show_bug.cgi?id=108070 == Participating hosts (46 -> 43) == Additional (2): fi-skl-iommu fi-pnv-d510 Missing(5): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan == Build changes == * Linux: CI_DRM_5054 -> Patchwork_10646 CI_DRM_5054: dfa9e5c2b4b958e77c1109477b94c5c8615e25cc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10646: e059833842b56e793dd9005a8976274280c4a668 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e059833842b5 drm/i915/execlists: Poison the CSB after use == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10646/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [CI 4/7] drm/dp: DRM DP helper/macros to get DP sink DSC parameters
Hi Manasi, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on v4.19 next-20181030] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Manasi-Navare/drm-i915-dsc-Add-slice_row_per_frame-in-DSC-PPS-programming/20181030-054654 base: git://anongit.freedesktop.org/drm-intel for-linux-next reproduce: make htmldocs All warnings (new ones prefixed by >>): include/net/mac80211.h:977: warning: Function parameter or member 'status.rates' not described in 'ieee80211_tx_info' include/net/mac80211.h:977: warning: Function parameter or member 'status.ack_signal' not described in 'ieee80211_tx_info' include/net/mac80211.h:977: warning: Function parameter or member 'status.ampdu_ack_len' not described in 'ieee80211_tx_info' include/net/mac80211.h:977: warning: Function parameter or member 'status.ampdu_len' not described in 'ieee80211_tx_info' include/net/mac80211.h:977: warning: Function parameter or member 'status.antenna' not described in 'ieee80211_tx_info' include/net/mac80211.h:977: warning: Function parameter or member 'status.tx_time' not described in 'ieee80211_tx_info' include/net/mac80211.h:977: warning: Function parameter or member 'status.is_valid_ack_signal' not described in 'ieee80211_tx_info' include/net/mac80211.h:977: warning: Function parameter or member 'status.status_driver_data' not described in 'ieee80211_tx_info' include/net/mac80211.h:977: warning: Function parameter or member 'driver_rates' not described in 'ieee80211_tx_info' include/net/mac80211.h:977: warning: Function parameter or member 'pad' not described in 'ieee80211_tx_info' include/net/mac80211.h:977: warning: Function parameter or member 'rate_driver_data' not described in 'ieee80211_tx_info' net/mac80211/sta_info.h:588: warning: Function parameter or member 'rx_stats_avg' not described in 'sta_info' net/mac80211/sta_info.h:588: warning: Function parameter or member 'rx_stats_avg.signal' not described in 'sta_info' net/mac80211/sta_info.h:588: warning: Function parameter or member 'rx_stats_avg.chain_signal' not described in 'sta_info' net/mac80211/sta_info.h:588: warning: Function parameter or member 'status_stats.filtered' not described in 'sta_info' net/mac80211/sta_info.h:588: warning: Function parameter or member 'status_stats.retry_failed' not described in 'sta_info' net/mac80211/sta_info.h:588: warning: Function parameter or member 'status_stats.retry_count' not described in 'sta_info' net/mac80211/sta_info.h:588: warning: Function parameter or member 'status_stats.lost_packets' not described in 'sta_info' net/mac80211/sta_info.h:588: warning: Function parameter or member 'status_stats.last_tdls_pkt_time' not described in 'sta_info' net/mac80211/sta_info.h:588: warning: Function parameter or member 'status_stats.msdu_retries' not described in 'sta_info' net/mac80211/sta_info.h:588: warning: Function parameter or member 'status_stats.msdu_failed' not described in 'sta_info' net/mac80211/sta_info.h:588: warning: Function parameter or member 'status_stats.last_ack' not described in 'sta_info' net/mac80211/sta_info.h:588: warning: Function parameter or member 'status_stats.last_ack_signal' not described in 'sta_info' net/mac80211/sta_info.h:588: warning: Function parameter or member 'status_stats.ack_signal_filled' not described in 'sta_info' net/mac80211/sta_info.h:588: warning: Function parameter or member 'status_stats.avg_ack_signal' not described in 'sta_info' net/mac80211/sta_info.h:588: warning: Function parameter or member 'tx_stats.packets' not described in 'sta_info' net/mac80211/sta_info.h:588: warning: Function parameter or member 'tx_stats.bytes' not described in 'sta_info' net/mac80211/sta_info.h:588: warning: Function parameter or member 'tx_stats.last_rate' not described in 'sta_info' net/mac80211/sta_info.h:588: warning: Function parameter or member 'tx_stats.msdu' not described in 'sta_info' include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.cb' not described in 'dma_buf' include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.poll' not described in
Re: [Intel-gfx] [v5 2/2] drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
Op 26-10-18 om 12:01 schreef Uma Shankar:
> Plane input CSC needs to be enabled to convert frambuffers from
> YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
> the planes have hardcoded conversion and taken care by the legacy
> code.
>
> This patch defines the co-efficient values for YUV to RGB conversion
> in BT709 and BT601 formats. It programs the coefficients and enables
> the plane input csc unit in hardware.
>
> Note: This is currently untested and floated to get an early feedback
> on the design and implementation for this feature. In parallel,
> I will test this on actual ICL hardware and confirm with planar
> formats.
>
> v2: Addressed Maarten's and Ville's review comments and added the
> coefficients in a 2D array instead of independent Macros.
>
> v3: Added individual coefficient matrix (9 values) instead of 6
> register values as per Maarten's comment. Also addresed a shift
> issue with B channel coefficient.
>
> v4: Added support for Limited Range Color Handling
>
> v5: Fixed Matt and Maarten's review comments.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/intel_color.c | 79
>
> drivers/gpu/drm/i915/intel_display.c | 23 ---
> drivers/gpu/drm/i915/intel_drv.h | 2 +
> 3 files changed, 98 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index 5127da2..681cd13 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -57,6 +57,15 @@
> #define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
> #define CSC_RGB_TO_YUV_BV 0x1e08
>
> +#define ROFF(x) (((x) & 0x) << 16)
> +#define GOFF(x) (((x) & 0x) << 0)
> +#define BOFF(x) (((x) & 0x) << 16)
> +
> +/* Preoffset values for YUV to RGB Conversion */
> +#define PREOFF_YUV_TO_RGB_HI 0x1800
> +#define PREOFF_YUV_TO_RGB_ME 0x1F00
> +#define PREOFF_YUV_TO_RGB_LO 0x1800
> +
> /*
> * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
> * format). This macro takes the coefficient we want transformed and the
> @@ -643,6 +652,76 @@ int intel_color_check(struct drm_crtc *crtc,
> return -EINVAL;
> }
>
> +void icl_program_input_csc_coeff(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + struct drm_i915_private *dev_priv =
> + to_i915(plane_state->base.plane->dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + enum pipe pipe = crtc->pipe;
> + struct intel_plane *intel_plane =
> + to_intel_plane(plane_state->base.plane);
> + enum plane_id plane = intel_plane->id;
> +
> + static const u16 input_csc_matrix[][9] = {
> + /* BT.601 full range YCbCr -> full range RGB */
> + [DRM_COLOR_YCBCR_BT601] = {
> + 0x7AF8, 0x7800, 0x0,
> + 0x8B28, 0x7800, 0x9AC0,
> + 0x0, 0x7800, 0x7DD8,
> + },
> + /* BT.709 full range YCbCr -> full range RGB */
> + [DRM_COLOR_YCBCR_BT709] = {
> + 0x7C98, 0x7800, 0x0,
> + 0x9EF8, 0x7800, 0xABF8,
> + 0x0, 0x7800, 0x7ED8,
> + },
> + };
> +
> + /* Matrix for Limited Range to Full Range Conversion */
> + static const u16 input_csc_matrix_lr[][9] = {
> + /* BT.601 Limted range YCbCr -> full range RGB */
> + [DRM_COLOR_YCBCR_BT601] = {
> + 0x7CC8, 0x7950, 0x0,
> + 0x8CB8, 0x7918, 0x9C40,
> + 0x0, 0x7918, 0x7FC8,
> + },
> + /* BT.709 Limited range YCbCr -> full range RGB */
> + [DRM_COLOR_YCBCR_BT709] = {
> + 0x7EA8, 0x7950, 0x0,
> + 0x, 0x7918, 0xADA8,
> + 0x0, 0x7918, 0x6870,
> + },
> + };
> + const u16 *csc;
> +
> + if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> + csc = input_csc_matrix[plane_state->base.color_encoding];
> + else
> + csc = input_csc_matrix_lr[plane_state->base.color_encoding];
> +
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 0), ROFF(csc[0]) |
> +GOFF(csc[1]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 1), BOFF(csc[2]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 2), ROFF(csc[3]) |
> +GOFF(csc[4]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 3), BOFF(csc[5]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 4), ROFF(csc[6]) |
> +GOFF(csc[7]));
> + I915_WRITE(PLANE_INPUT_CSC_COEFF(pipe, plane, 5), BOFF(csc[8]));
> +
> + I915_WRITE(PLANE_INPUT_CSC_PREOFF(pipe, plane, 0),
> +PREOFF_YUV_TO_RGB_HI);
> + I915_WRITE(PLANE_INPUT_
[Intel-gfx] [PATCH v2] drm/i915: Stop calling intel_opregion unregister/register in suspend/resume
If we reduce the suspend function for intel_opregion to do the minimum
required, the resume function can also do the simple task of notifier
the ACPI bios that we are back. This avoid some nasty restrictions on
the likes of register_acpi_notifier() that are not allowed during the
early phase of resume.
v2: Keep the order of acpi notify vs turning off ardy/drdy the same.
Signed-off-by: Chris Wilson
Cc: Imre Deak
Cc: Jani Nikula
Reviewed-by: Jani Nikula
Acked-by: Imre Deak
---
drivers/gpu/drm/i915/i915_drv.c | 9 +-
drivers/gpu/drm/i915/intel_opregion.c | 158 +++---
drivers/gpu/drm/i915/intel_opregion.h | 15 +++
3 files changed, 111 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1ad13da61d7a..f6416b1d3452 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1921,9 +1921,7 @@ static int i915_drm_suspend(struct drm_device *dev)
i915_save_state(dev_priv);
opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
- intel_opregion_notify_adapter(dev_priv, opregion_target_state);
-
- intel_opregion_unregister(dev_priv);
+ intel_opregion_suspend(dev_priv, opregion_target_state);
intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
@@ -2042,7 +2040,6 @@ static int i915_drm_resume(struct drm_device *dev)
i915_restore_state(dev_priv);
intel_pps_unlock_regs_wa(dev_priv);
- intel_opregion_setup(dev_priv);
intel_init_pch_refclk(dev_priv);
@@ -2084,12 +2081,10 @@ static int i915_drm_resume(struct drm_device *dev)
* */
intel_hpd_init(dev_priv);
- intel_opregion_register(dev_priv);
+ intel_opregion_resume(dev_priv);
intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
- intel_opregion_notify_adapter(dev_priv, PCI_D0);
-
intel_power_domains_enable(dev_priv);
enable_rpm_wakeref_asserts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opregion.c
index e034b4166d32..b8f106d9ecf8 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -773,70 +773,6 @@ static void intel_setup_cadls(struct drm_i915_private
*dev_priv)
opregion->acpi->cadl[i] = 0;
}
-void intel_opregion_register(struct drm_i915_private *dev_priv)
-{
- struct intel_opregion *opregion = &dev_priv->opregion;
-
- if (!opregion->header)
- return;
-
- if (opregion->acpi) {
- intel_didl_outputs(dev_priv);
- intel_setup_cadls(dev_priv);
-
- /* Notify BIOS we are ready to handle ACPI video ext notifs.
-* Right now, all the events are handled by the ACPI video
module.
-* We don't actually need to do anything with them. */
- opregion->acpi->csts = 0;
- opregion->acpi->drdy = 1;
-
- opregion->acpi_notifier.notifier_call =
intel_opregion_video_event;
- register_acpi_notifier(&opregion->acpi_notifier);
- }
-
- if (opregion->asle) {
- opregion->asle->tche = ASLE_TCHE_BLC_EN;
- opregion->asle->ardy = ASLE_ARDY_READY;
- }
-}
-
-void intel_opregion_unregister(struct drm_i915_private *dev_priv)
-{
- struct intel_opregion *opregion = &dev_priv->opregion;
-
- if (!opregion->header)
- return;
-
- if (opregion->asle)
- opregion->asle->ardy = ASLE_ARDY_NOT_READY;
-
- cancel_work_sync(&dev_priv->opregion.asle_work);
-
- if (opregion->acpi) {
- opregion->acpi->drdy = 0;
-
- unregister_acpi_notifier(&opregion->acpi_notifier);
- opregion->acpi_notifier.notifier_call = NULL;
- }
-
- /* just clear all opregion memory pointers now */
- memunmap(opregion->header);
- if (opregion->rvda) {
- memunmap(opregion->rvda);
- opregion->rvda = NULL;
- }
- if (opregion->vbt_firmware) {
- kfree(opregion->vbt_firmware);
- opregion->vbt_firmware = NULL;
- }
- opregion->header = NULL;
- opregion->acpi = NULL;
- opregion->swsci = NULL;
- opregion->asle = NULL;
- opregion->vbt = NULL;
- opregion->lid_state = NULL;
-}
-
static void swsci_setup(struct drm_i915_private *dev_priv)
{
struct intel_opregion *opregion = &dev_priv->opregion;
@@ -1115,3 +1051,97 @@ intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv)
return ret - 1;
}
+
+void intel_opregion_register(struct drm_i915_private *i915)
+{
+ struct intel_opregion *opregion = &i915->opregion;
+
+ if (!opregion->header)
+ return;
+
+ if (opregion->acpi) {
+ opregion->acpi_notifier.notifier_call =
+ intel_opregi
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/execlists: Poison the CSB after use
== Series Details == Series: drm/i915/execlists: Poison the CSB after use URL : https://patchwork.freedesktop.org/series/51703/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5054 -> Patchwork_10648 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10648 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10648, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51703/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10648: === IGT changes === Possible regressions igt@gem_ctx_switch@basic-default: fi-icl-u: PASS -> INCOMPLETE == Known issues == Here are the changes found in Patchwork_10648 that come from known issues: === IGT changes === Issues hit igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) +1 fi-cfl-8109u: PASS -> INCOMPLETE (fdo#106070, fdo#108126) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#108126 https://bugs.freedesktop.org/show_bug.cgi?id=108126 == Participating hosts (46 -> 43) == Additional (2): fi-skl-iommu fi-pnv-d510 Missing(5): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan == Build changes == * Linux: CI_DRM_5054 -> Patchwork_10648 CI_DRM_5054: dfa9e5c2b4b958e77c1109477b94c5c8615e25cc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10648: f055da085307e36a67bd590f0ba3d0a9bcc1dac6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f055da085307 drm/i915/execlists: Poison the CSB after use == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10648/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Stop calling intel_opregion unregister/register in suspend/resume (rev2)
== Series Details ==
Series: drm/i915: Stop calling intel_opregion unregister/register in
suspend/resume (rev2)
URL : https://patchwork.freedesktop.org/series/50630/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4e7c4e2dac56 drm/i915: Stop calling intel_opregion unregister/register in
suspend/resume
-:221: WARNING:NEEDLESS_IF: kfree(NULL) is safe and this check is probably not
required
#221: FILE: drivers/gpu/drm/i915/intel_opregion.c:1138:
+ if (opregion->vbt_firmware) {
+ kfree(opregion->vbt_firmware);
total: 0 errors, 1 warnings, 0 checks, 226 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 27/28] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable
On Mon, Oct 29, 2018 at 02:35:36PM -0700, Manasi Navare wrote:
> On Mon, Oct 29, 2018 at 10:39:21PM +0200, Ville Syrjälä wrote:
> > On Wed, Oct 24, 2018 at 03:28:39PM -0700, Manasi Navare wrote:
> > > DSC can be supported per DP connector. This patch adds a per connector
> > > debugfs node to expose DSC support capability by the kernel.
> > > The same node can be used from userspace to force DSC enable.
> >
> > Why is the force_dsc thing split between two patches so strangely?
>
> This patch just defines the force_dsc and sets it through the debugfs
> node. But how it configures DSC during atomic check is moved to a
> separate patch.
> Would you prefer having that integrated with this patch itself?
Either that or split it in into "read only debugfs status" +
"add dsc_force" patches.
>
> Manasi
>
> >
> > >
> > > v2:
> > > * Use kstrtobool_from_user to avoid explicit error checking (Lyude)
> > > * Rebase on drm-tip (Manasi)
> > >
> > > Cc: Rodrigo Vivi
> > > Cc: Ville Syrjala
> > > Cc: Anusha Srivatsa
> > > Cc: Lyude Paul
> > > Signed-off-by: Manasi Navare
> > > Reviewed-by: Lyude Paul
> > > ---
> > > drivers/gpu/drm/i915/i915_debugfs.c | 71 -
> > > drivers/gpu/drm/i915/intel_dp.c | 1 +
> > > drivers/gpu/drm/i915/intel_drv.h| 3 ++
> > > 3 files changed, 74 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index 5cadfcd03ea9..6e631f08dd4b 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -4999,6 +4999,72 @@ static int i915_hdcp_sink_capability_show(struct
> > > seq_file *m, void *data)
> > > }
> > > DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
> > >
> > > +static int i915_dsc_support_show(struct seq_file *m, void *data)
> > > +{
> > > + struct drm_connector *connector = m->private;
> > > + struct intel_encoder *encoder = intel_attached_encoder(connector);
> > > + struct intel_dp *intel_dp =
> > > + enc_to_intel_dp(&encoder->base);
> > > + struct intel_crtc *crtc;
> > > + struct intel_crtc_state *crtc_state;
> > > +
> > > + crtc = to_intel_crtc(encoder->base.crtc);
> > > + crtc_state = to_intel_crtc_state(crtc->base.state);
> > > + drm_modeset_lock(&crtc->base.mutex, NULL);
> > > + seq_printf(m, "Enabled: %s\n",
> > > +yesno(crtc_state->dsc_params.compression_enable));
> > > + seq_printf(m, "Supported: %s\n",
> > > +yesno(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
> > > + drm_modeset_unlock(&crtc->base.mutex);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static ssize_t i915_dsc_support_write(struct file *file,
> > > + const char __user *ubuf,
> > > + size_t len, loff_t *offp)
> > > +{
> > > + bool dsc_enable = false;
> > > + int ret;
> > > + struct drm_connector *connector =
> > > + ((struct seq_file *)file->private_data)->private;
> > > + struct intel_encoder *encoder = intel_attached_encoder(connector);
> > > + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> > > +
> > > + if (len == 0)
> > > + return 0;
> > > +
> > > + DRM_DEBUG_DRIVER("Copied %d bytes from user to force DSC\n",
> > > + (unsigned int)len);
> > > +
> > > + ret = kstrtobool_from_user(ubuf, len, &dsc_enable);
> > > + if (ret < 0)
> > > + return ret;
> > > +
> > > + DRM_DEBUG_DRIVER("Got %s for DSC Enable\n",
> > > + (dsc_enable) ? "true" : "false");
> > > + intel_dp->force_dsc_en = dsc_enable;
> > > +
> > > + *offp += len;
> > > + return len;
> > > +}
> > > +
> > > +static int i915_dsc_support_open(struct inode *inode,
> > > + struct file *file)
> > > +{
> > > + return single_open(file, i915_dsc_support_show,
> > > +inode->i_private);
> > > +}
> > > +
> > > +static const struct file_operations i915_dsc_support_fops = {
> > > + .owner = THIS_MODULE,
> > > + .open = i915_dsc_support_open,
> > > + .read = seq_read,
> > > + .llseek = seq_lseek,
> > > + .release = single_release,
> > > + .write = i915_dsc_support_write
> > > +};
> > > +
> > > /**
> > > * i915_debugfs_connector_add - add i915 specific connector debugfs files
> > > * @connector: pointer to a registered drm_connector
> > > @@ -5017,9 +5083,12 @@ int i915_debugfs_connector_add(struct
> > > drm_connector *connector)
> > > return -ENODEV;
> > >
> > > if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> > > - connector->connector_type == DRM_MODE_CONNECTOR_eDP)
> > > + connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
> > > debugfs_create_file("i915_dpcd", S_IRUGO, root,
> > > connector, &i915_dpcd_fops);
> > > + debugfs_create_file("i915_dsc_support", S_IRUGO, root,
> > > + connector, &i915_dsc_support_fops);
> > > + }
> > >
> > >
Re: [Intel-gfx] [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check
On Mon, Oct 29, 2018 at 03:12:51PM -0700, Manasi Navare wrote:
> On Mon, Oct 29, 2018 at 10:30:39PM +0200, Ville Syrjälä wrote:
> > On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> > > DSC params like the enable, compressed bpp, slice count and
> > > dsc_split are added to the intel_crtc_state. These parameters
> > > are set based on the requested mode and available link parameters
> > > during the pipe configuration in atomic check phase.
> > > These values are then later used to populate the remaining DSC
> > > and RC parameters before enbaling DSC in atomic commit.
> > >
> > > v9:
> > > * Rebase on top of drm-tip that now uses fast_narrow config
> > > for edp (Manasi)
> > > v8:
> > > * Check for DSC bpc not 0 (manasi)
> > >
> > > v7:
> > > * Fix indentation in compute_m_n (Manasi)
> > >
> > > v6 (From Gaurav):
> > > * Remove function call of intel_dp_compute_dsc_params() and
> > > invoke intel_dp_compute_dsc_params() in the patch where
> > > it is defined to fix compilation warning (Gaurav)
> > >
> > > v5:
> > > Add drm_dsc_cfg in intel_crtc_state (Manasi)
> > >
> > > v4:
> > > * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> > > * Add a comment why we need to check PSR while enabling DSC (Gaurav)
> > >
> > > v3:
> > > * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
> > >
> > > v2:
> > > * Add if-else for eDP/DP (Gaurav)
> > >
> > > Cc: Jani Nikula
> > > Cc: Ville Syrjala
> > > Cc: Anusha Srivatsa
> > > Cc: Gaurav K Singh
> > > Signed-off-by: Manasi Navare
> > > Reviewed-by: Anusha Srivatsa
> > > Acked-by: Jani Nikula
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 20 +++-
> > > drivers/gpu/drm/i915/intel_display.h | 3 +-
> > > drivers/gpu/drm/i915/intel_dp.c | 170 ++-
> > > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> > > 4 files changed, 155 insertions(+), 40 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index fe045abb6472..18737bd82b68 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -6434,7 +6434,7 @@ static int ironlake_fdi_compute_config(struct
> > > intel_crtc *intel_crtc,
> > >
> > > pipe_config->fdi_lanes = lane;
> > >
> > > - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> > > + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
> > > link_bw, &pipe_config->fdi_m_n, false);
> > >
> > > ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
> > > @@ -6671,17 +6671,25 @@ static void compute_m_n(unsigned int m, unsigned
> > > int n,
> > > }
> > >
> > > void
> > > -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> > > +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> > > +int nlanes,
> > > int pixel_clock, int link_clock,
> > > struct intel_link_m_n *m_n,
> > > bool constant_n)
> > > {
> > > m_n->tu = 64;
> > >
> > > - compute_m_n(bits_per_pixel * pixel_clock,
> > > - link_clock * nlanes * 8,
> > > - &m_n->gmch_m, &m_n->gmch_n,
> > > - constant_n);
> > > + /* For DSC, Data M/N calculation uses compressed BPP */
> > > + if (compressed_bpp)
> > > + compute_m_n(compressed_bpp * pixel_clock,
> > > + link_clock * nlanes * 8,
> > > + &m_n->gmch_m, &m_n->gmch_n,
> > > + constant_n);
> > > + else
> > > + compute_m_n(bits_per_pixel * pixel_clock,
> > > + link_clock * nlanes * 8,
> > > + &m_n->gmch_m, &m_n->gmch_n,
> > > + constant_n);
> > >
> > > compute_m_n(pixel_clock, link_clock,
> > > &m_n->link_m, &m_n->link_n,
> > > diff --git a/drivers/gpu/drm/i915/intel_display.h
> > > b/drivers/gpu/drm/i915/intel_display.h
> > > index 5d50decbcbb5..b0b23e1e9392 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.h
> > > +++ b/drivers/gpu/drm/i915/intel_display.h
> > > @@ -407,7 +407,8 @@ struct intel_link_m_n {
> > >(__i)++) \
> > > for_each_if(plane)
> > >
> > > -void intel_link_compute_m_n(int bpp, int nlanes,
> > > +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> > > + int nlanes,
> > > int pixel_clock, int link_clock,
> > > struct intel_link_m_n *m_n,
> > > bool constant_n);
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index 6f66a38ba0b2..a88f9371dd32 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -47,6 +47,8 @@
> > >
> > > /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
> > > #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> > > +#
Re: [Intel-gfx] [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check
On Mon, Oct 29, 2018 at 04:08:43PM -0700, Manasi Navare wrote:
> On Mon, Oct 29, 2018 at 10:34:58PM +0200, Ville Syrjälä wrote:
> > On Mon, Oct 29, 2018 at 10:30:39PM +0200, Ville Syrjälä wrote:
> > > On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> > > > DSC params like the enable, compressed bpp, slice count and
> > > > dsc_split are added to the intel_crtc_state. These parameters
> > > > are set based on the requested mode and available link parameters
> > > > during the pipe configuration in atomic check phase.
> > > > These values are then later used to populate the remaining DSC
> > > > and RC parameters before enbaling DSC in atomic commit.
> > > >
> > > > v9:
> > > > * Rebase on top of drm-tip that now uses fast_narrow config
> > > > for edp (Manasi)
> > > > v8:
> > > > * Check for DSC bpc not 0 (manasi)
> > > >
> > > > v7:
> > > > * Fix indentation in compute_m_n (Manasi)
> > > >
> > > > v6 (From Gaurav):
> > > > * Remove function call of intel_dp_compute_dsc_params() and
> > > > invoke intel_dp_compute_dsc_params() in the patch where
> > > > it is defined to fix compilation warning (Gaurav)
> > > >
> > > > v5:
> > > > Add drm_dsc_cfg in intel_crtc_state (Manasi)
> > > >
> > > > v4:
> > > > * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> > > > * Add a comment why we need to check PSR while enabling DSC (Gaurav)
> > > >
> > > > v3:
> > > > * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
> > > >
> > > > v2:
> > > > * Add if-else for eDP/DP (Gaurav)
> > > >
> > > > Cc: Jani Nikula
> > > > Cc: Ville Syrjala
> > > > Cc: Anusha Srivatsa
> > > > Cc: Gaurav K Singh
> > > > Signed-off-by: Manasi Navare
> > > > Reviewed-by: Anusha Srivatsa
> > > > Acked-by: Jani Nikula
> > > > ---
> > > > drivers/gpu/drm/i915/intel_display.c | 20 +++-
> > > > drivers/gpu/drm/i915/intel_display.h | 3 +-
> > > > drivers/gpu/drm/i915/intel_dp.c | 170 ++-
> > > > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> > > > 4 files changed, 155 insertions(+), 40 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > > b/drivers/gpu/drm/i915/intel_display.c
> > > > index fe045abb6472..18737bd82b68 100644
> > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > @@ -6434,7 +6434,7 @@ static int ironlake_fdi_compute_config(struct
> > > > intel_crtc *intel_crtc,
> > > >
> > > > pipe_config->fdi_lanes = lane;
> > > >
> > > > - intel_link_compute_m_n(pipe_config->pipe_bpp, lane,
> > > > fdi_dotclock,
> > > > + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane,
> > > > fdi_dotclock,
> > > >link_bw, &pipe_config->fdi_m_n, false);
> > > >
> > > > ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe,
> > > > pipe_config);
> > > > @@ -6671,17 +6671,25 @@ static void compute_m_n(unsigned int m,
> > > > unsigned int n,
> > > > }
> > > >
> > > > void
> > > > -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> > > > +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> > > > + int nlanes,
> > > >int pixel_clock, int link_clock,
> > > >struct intel_link_m_n *m_n,
> > > >bool constant_n)
> > > > {
> > > > m_n->tu = 64;
> > > >
> > > > - compute_m_n(bits_per_pixel * pixel_clock,
> > > > - link_clock * nlanes * 8,
> > > > - &m_n->gmch_m, &m_n->gmch_n,
> > > > - constant_n);
> > > > + /* For DSC, Data M/N calculation uses compressed BPP */
> > > > + if (compressed_bpp)
> > > > + compute_m_n(compressed_bpp * pixel_clock,
> > > > + link_clock * nlanes * 8,
> > > > + &m_n->gmch_m, &m_n->gmch_n,
> > > > + constant_n);
> > > > + else
> > > > + compute_m_n(bits_per_pixel * pixel_clock,
> > > > + link_clock * nlanes * 8,
> > > > + &m_n->gmch_m, &m_n->gmch_n,
> > > > + constant_n);
> > > >
> > > > compute_m_n(pixel_clock, link_clock,
> > > > &m_n->link_m, &m_n->link_n,
> > > > diff --git a/drivers/gpu/drm/i915/intel_display.h
> > > > b/drivers/gpu/drm/i915/intel_display.h
> > > > index 5d50decbcbb5..b0b23e1e9392 100644
> > > > --- a/drivers/gpu/drm/i915/intel_display.h
> > > > +++ b/drivers/gpu/drm/i915/intel_display.h
> > > > @@ -407,7 +407,8 @@ struct intel_link_m_n {
> > > > (__i)++) \
> > > > for_each_if(plane)
> > > >
> > > > -void intel_link_compute_m_n(int bpp, int nlanes,
> > > > +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> > > > + int nlanes,
> > > > int pixel_clock, int link_clock,
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Stop calling intel_opregion unregister/register in suspend/resume (rev2)
== Series Details == Series: drm/i915: Stop calling intel_opregion unregister/register in suspend/resume (rev2) URL : https://patchwork.freedesktop.org/series/50630/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5054 -> Patchwork_10649 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/50630/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_10649 that come from known issues: === IGT changes === Issues hit igt@debugfs_test@read_all_entries: fi-icl-u2: PASS -> DMESG-WARN (fdo#108070) igt@gem_exec_suspend@basic-s3: fi-icl-u2: PASS -> DMESG-WARN (fdo#106612) igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191) +1 fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) Possible fixes igt@gem_ctx_create@basic-files: fi-icl-u2: DMESG-WARN (fdo#107724) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#106612 https://bugs.freedesktop.org/show_bug.cgi?id=106612 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724 fdo#108070 https://bugs.freedesktop.org/show_bug.cgi?id=108070 == Participating hosts (46 -> 42) == Additional (2): fi-skl-iommu fi-pnv-d510 Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u == Build changes == * Linux: CI_DRM_5054 -> Patchwork_10649 CI_DRM_5054: dfa9e5c2b4b958e77c1109477b94c5c8615e25cc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10649: 4e7c4e2dac56bbf71c12e8c0bc0b21570c6bf99f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4e7c4e2dac56 drm/i915: Stop calling intel_opregion unregister/register in suspend/resume == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10649/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 00/38] drm/i915/icl: dsi enabling
Next version of [1]. Now includes all the patches I'm juggling, although I haven't gone through the patches toward the end of the series all that much. Still needs the DSI PLL stuff Vandita covers. Also available at icl-dsi-2018-10-30 branch of [2]. The patches that include my Reviewed-by I haven't changed. BR, Jani. [1] https://patchwork.freedesktop.org/series/51011/ [2] https://cgit.freedesktop.org/~jani/drm/ Anusha Srivatsa (1): drm/i915/icl: Add DSS_CTL Registers Jani Nikula (3): drm/i915/icl: Allocate DSI encoder/connector drm/i915/icl: Allocate hosts for DSI ports drm/i915/icl: Load DSI packet payload to queue Madhav Chauhan (34): drm/i915/icl: Move dsi host init code to common file drm/i915/dsi: move connector mode functions to common file drm/i915/icl: Set max return packet size for DSI panel drm/i915/icl: Power on DSI panel drm/i915/icl: Wait for header/payload credits release drm/i915/icl: Turn ON panel backlight drm/i915/icl: Turn OFF panel backlight drm/i915/icl: Disable DSI transcoders drm/i915/icl: Power down DSI panel drm/i915/icl: Put DSI link in ULPS drm/i915/icl: Disable DDI function drm/i915/icl: Disable portsync mode drm/i915/icl: Disable DSI ports drm/i915/icl: Disable DSI IO power drm/i915/icl: Define DSI timeout registers drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers drm/i915/icl: Find DSI presence for ICL drm/i915/icl: Add DSI packet payload/header registers drm/i915/icl: Fetch DSI pkt to be transferred drm/i915/icl: Add get config functionality for DSI drm/i915/icl: Get HW state for DSI encoder drm/i915/icl: Add DSI connector functions drm/i915/icl: Add DSI connector helper functions drm/i915/icl: Add DSI encoder remaining functions drm/i915/icl: Fill DSI ports info drm/i915/icl: Configure DSI Dual link mode drm/i915/icl: Define Panel power ctrl register drm/i915/icl: Define missing bitfield for shortplug reg drm/i915/icl: Define display GPIO pins for DSI drm/i915/icl: Add changes to program DSI panel GPIOs HACK: drm/i915/icl: Configure backlight functions for DSI drm/i915/icl: Don't wait for empty FIFO drm/i915/icl: Consider DSI for getting transcoder state drm/i915/icl: Get pipe timings for DSI drivers/gpu/drm/i915/i915_reg.h | 110 ++ drivers/gpu/drm/i915/icl_dsi.c | 716 ++- drivers/gpu/drm/i915/intel_bios.c| 12 +- drivers/gpu/drm/i915/intel_display.c | 33 +- drivers/gpu/drm/i915/intel_drv.h | 3 + drivers/gpu/drm/i915/intel_dsi.c | 81 drivers/gpu/drm/i915/intel_dsi.h | 7 + drivers/gpu/drm/i915/intel_dsi_vbt.c | 63 ++- drivers/gpu/drm/i915/intel_panel.c | 3 +- drivers/gpu/drm/i915/vlv_dsi.c | 84 +--- 10 files changed, 1008 insertions(+), 104 deletions(-) -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 01/38] drm/i915/icl: Move dsi host init code to common file
From: Madhav Chauhan
This patch moves intl_dsi_host_init() code to intel_dsi.c so that legacy
and gen11 DSI code can share this code.
v2 by Jani:
- Move the shared stuff to intel_dsi.c
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 34 ++
drivers/gpu/drm/i915/intel_dsi.h | 3 +++
drivers/gpu/drm/i915/vlv_dsi.c | 36 ++--
3 files changed, 39 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index a32cc1f4b384..97e04c272612 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -28,3 +28,37 @@ int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi)
return 200;
}
}
+
+struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
+ const struct mipi_dsi_host_ops
*funcs,
+ enum port port)
+{
+ struct intel_dsi_host *host;
+ struct mipi_dsi_device *device;
+
+ host = kzalloc(sizeof(*host), GFP_KERNEL);
+ if (!host)
+ return NULL;
+
+ host->base.ops = funcs;
+ host->intel_dsi = intel_dsi;
+ host->port = port;
+
+ /*
+* We should call mipi_dsi_host_register(&host->base) here, but we don't
+* have a host->dev, and we don't have OF stuff either. So just use the
+* dsi framework as a library and hope for the best. Create the dsi
+* devices by ourselves here too. Need to be careful though, because we
+* don't initialize any of the driver model devices here.
+*/
+ device = kzalloc(sizeof(*device), GFP_KERNEL);
+ if (!device) {
+ kfree(host);
+ return NULL;
+ }
+
+ device->host = &host->base;
+ host->device = device;
+
+ return host;
+}
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 14567929de9a..09f0fa9ccc7d 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -152,6 +152,9 @@ int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
/* vlv_dsi.c */
void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
+struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
+ const struct mipi_dsi_host_ops
*funcs,
+ enum port port);
/* vlv_dsi_pll.c */
int vlv_dsi_pll_compute(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index ee0cd5d0bf91..cbb935a9acf3 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -206,39 +206,6 @@ static const struct mipi_dsi_host_ops intel_dsi_host_ops =
{
.transfer = intel_dsi_host_transfer,
};
-static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
- enum port port)
-{
- struct intel_dsi_host *host;
- struct mipi_dsi_device *device;
-
- host = kzalloc(sizeof(*host), GFP_KERNEL);
- if (!host)
- return NULL;
-
- host->base.ops = &intel_dsi_host_ops;
- host->intel_dsi = intel_dsi;
- host->port = port;
-
- /*
-* We should call mipi_dsi_host_register(&host->base) here, but we don't
-* have a host->dev, and we don't have OF stuff either. So just use the
-* dsi framework as a library and hope for the best. Create the dsi
-* devices by ourselves here too. Need to be careful though, because we
-* don't initialize any of the driver model devices here.
-*/
- device = kzalloc(sizeof(*device), GFP_KERNEL);
- if (!device) {
- kfree(host);
- return NULL;
- }
-
- device->host = &host->base;
- host->device = device;
-
- return host;
-}
-
/*
* send a video mode command
*
@@ -1768,7 +1735,8 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
for_each_dsi_port(port, intel_dsi->ports) {
struct intel_dsi_host *host;
- host = intel_dsi_host_init(intel_dsi, port);
+ host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
+ port);
if (!host)
goto err;
--
2.11.0
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[Intel-gfx] [PATCH v8 05/38] drm/i915/icl: Wait for header/payload credits release
From: Madhav Chauhan
Driver needs payload/header credits for sending any command
and data over DSI link. These credits are released once command
or data sent to link. This patch adds functions to wait for releasing
of payload and header credits.
As per BSPEC, driver needs to ensure that all of commands/data
has been dispatched to panel before the transcoder is enabled.
This patch implement those steps i.e. sending NOP DCS command,
wait for header/payload credit to be released etc.
v2 by Jani:
- squash the credit wait helpers patch with the first user
- pass dev_priv to the credit wait helpers
- bikeshed credit helper names
- wait for *at least* the current maximum number of credits
- indentation fix
- add helpers for credits available
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 74 ++
1 file changed, 74 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index d9c91001f107..0f0447b6b1be 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -28,6 +28,36 @@
#include
#include "intel_dsi.h"
+static inline int header_credits_available(struct drm_i915_private *dev_priv,
+ enum transcoder dsi_trans)
+{
+ return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
+ >> FREE_HEADER_CREDIT_SHIFT;
+}
+
+static inline int payload_credits_available(struct drm_i915_private *dev_priv,
+ enum transcoder dsi_trans)
+{
+ return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
+ >> FREE_PLOAD_CREDIT_SHIFT;
+}
+
+static void wait_for_header_credits(struct drm_i915_private *dev_priv,
+ enum transcoder dsi_trans)
+{
+ if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
+ MAX_HEADER_CREDIT, 100))
+ DRM_ERROR("DSI header credits not released\n");
+}
+
+static void wait_for_payload_credits(struct drm_i915_private *dev_priv,
+enum transcoder dsi_trans)
+{
+ if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
+ MAX_PLOAD_CREDIT, 100))
+ DRM_ERROR("DSI payload credits not released\n");
+}
+
static enum transcoder dsi_port_to_transcoder(enum port port)
{
if (port == PORT_A)
@@ -36,6 +66,47 @@ static enum transcoder dsi_port_to_transcoder(enum port port)
return TRANSCODER_DSI_1;
}
+static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct mipi_dsi_device *dsi;
+ enum port port;
+ enum transcoder dsi_trans;
+ int ret;
+
+ /* wait for header/payload credits to be released */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ wait_for_header_credits(dev_priv, dsi_trans);
+ wait_for_payload_credits(dev_priv, dsi_trans);
+ }
+
+ /* send nop DCS command */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi = intel_dsi->dsi_hosts[port]->device;
+ dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+ dsi->channel = 0;
+ ret = mipi_dsi_dcs_nop(dsi);
+ if (ret < 0)
+ DRM_ERROR("error sending DCS NOP command\n");
+ }
+
+ /* wait for header credits to be released */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ wait_for_header_credits(dev_priv, dsi_trans);
+ }
+
+ /* wait for LP TX in progress bit to be cleared */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) &
+ LPTX_IN_PROGRESS), 20))
+ DRM_ERROR("LPTX bit not cleared\n");
+ }
+}
+
static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -671,6 +742,9 @@ static void gen11_dsi_powerup_panel(struct intel_encoder
*encoder)
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
+
+ /* ensure all panel commands dispatched before enabling transcoder */
+ wait_for_cmds_dispatched_to_panel(encoder);
}
static void __attribute__((unused))
--
2.11.0
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[Intel-gfx] [PATCH v8 08/38] drm/i915/icl: Disable DSI transcoders
From: Madhav Chauhan
This patch disables transcoders by writing to TRANS_CONF
registers for each DSI ports.
v2 by Jani:
- Wait for pipeconf active to go low
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index f7f48ff147d0..644ad7475920 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -777,6 +777,29 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
}
+static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ enum transcoder dsi_trans;
+ u32 tmp;
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+
+ /* disable transcoder */
+ tmp = I915_READ(PIPECONF(dsi_trans));
+ tmp &= ~PIPECONF_ENABLE;
+ I915_WRITE(PIPECONF(dsi_trans), tmp);
+
+ /* wait for transcoder to be disabled */
+ if (intel_wait_for_register(dev_priv, PIPECONF(dsi_trans),
+ I965_PIPECONF_ACTIVE, 0, 50))
+ DRM_ERROR("DSI trancoder not disabled\n");
+ }
+}
+
static void __attribute__((unused)) gen11_dsi_disable(
struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
@@ -787,4 +810,7 @@ static void __attribute__((unused)) gen11_dsi_disable(
/* step1: turn off backlight */
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
intel_panel_disable_backlight(old_conn_state);
+
+ /* step2d,e: disable transcoder and wait */
+ gen11_dsi_disable_transcoder(encoder);
}
--
2.11.0
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[Intel-gfx] [PATCH v8 11/38] drm/i915/icl: Disable DDI function
From: Madhav Chauhan
This patch disables DDI function by writing to
TRANS_DDI_FUNC_CTL registers of DSI ports as part
of DSI disable sequence.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 83c422d5976c..0041f57d3c0b 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -833,6 +833,14 @@ static void gen11_dsi_deconfigure_trancoder(struct
intel_encoder *encoder)
10))
DRM_ERROR("DSI link not in ULPS\n");
}
+
+ /* disable ddi function */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
+ tmp &= ~TRANS_DDI_FUNC_ENABLE;
+ I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
+ }
}
static void __attribute__((unused)) gen11_dsi_disable(
--
2.11.0
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[Intel-gfx] [PATCH v8 10/38] drm/i915/icl: Put DSI link in ULPS
From: Madhav Chauhan
As part of DSI disabling sequence, DSI link need to enter
in ULPS by writing into DSI_LP_MSG register. This patch
does the same using a wrapper function.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index a7b1a9eae04b..83c422d5976c 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -812,6 +812,29 @@ static void gen11_dsi_powerdown_panel(struct intel_encoder
*encoder)
wait_for_cmds_dispatched_to_panel(encoder);
}
+static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ enum transcoder dsi_trans;
+ u32 tmp;
+
+ /* put dsi link in ULPS */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ tmp = I915_READ(DSI_LP_MSG(dsi_trans));
+ tmp |= LINK_ENTER_ULPS;
+ tmp &= ~LINK_ULPS_TYPE_LP11;
+ I915_WRITE(DSI_LP_MSG(dsi_trans), tmp);
+
+ if (wait_for_us((I915_READ(DSI_LP_MSG(dsi_trans)) &
+ LINK_IN_ULPS),
+ 10))
+ DRM_ERROR("DSI link not in ULPS\n");
+ }
+}
+
static void __attribute__((unused)) gen11_dsi_disable(
struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
@@ -828,4 +851,7 @@ static void __attribute__((unused)) gen11_dsi_disable(
/* step2f,g: powerdown panel */
gen11_dsi_powerdown_panel(encoder);
+
+ /* step2h,i,j: deconfig trancoder */
+ gen11_dsi_deconfigure_trancoder(encoder);
}
--
2.11.0
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[Intel-gfx] [PATCH v8 13/38] drm/i915/icl: Disable DSI ports
From: Madhav Chauhan
This patch disables both DSI ports by writing to
DDI_BUF_CTL registers as part of DSI encoder disable
sequence.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 71092f116170..44696848ffd7 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -853,6 +853,26 @@ static void gen11_dsi_deconfigure_trancoder(struct
intel_encoder *encoder)
}
}
+static void gen11_dsi_disable_port(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ u32 tmp;
+ enum port port;
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(DDI_BUF_CTL(port));
+ tmp &= ~DDI_BUF_CTL_ENABLE;
+ I915_WRITE(DDI_BUF_CTL(port), tmp);
+
+ if (wait_for_us((I915_READ(DDI_BUF_CTL(port)) &
+DDI_BUF_IS_IDLE),
+8))
+ DRM_ERROR("DDI port:%c buffer not idle\n",
+ port_name(port));
+ }
+}
+
static void __attribute__((unused)) gen11_dsi_disable(
struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
@@ -872,4 +892,7 @@ static void __attribute__((unused)) gen11_dsi_disable(
/* step2h,i,j: deconfig trancoder */
gen11_dsi_deconfigure_trancoder(encoder);
+
+ /* step3: disable port */
+ gen11_dsi_disable_port(encoder);
}
--
2.11.0
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[Intel-gfx] [PATCH v8 12/38] drm/i915/icl: Disable portsync mode
From: Madhav Chauhan
This patch disables portsync mode if DSI link
is operating in dual link mode by writing to
TRANS_DDI_FUNC_CTL2 registers.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 0041f57d3c0b..71092f116170 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -841,6 +841,16 @@ static void gen11_dsi_deconfigure_trancoder(struct
intel_encoder *encoder)
tmp &= ~TRANS_DDI_FUNC_ENABLE;
I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
}
+
+ /* disable port sync mode if dual link */
+ if (intel_dsi->dual_link) {
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
+ tmp &= ~PORT_SYNC_MODE_ENABLE;
+ I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
+ }
+ }
}
static void __attribute__((unused)) gen11_dsi_disable(
--
2.11.0
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[Intel-gfx] [PATCH v8 03/38] drm/i915/icl: Set max return packet size for DSI panel
From: Madhav Chauhan
This patch programs maximum size of the payload transmitted
from peripheral back to the host processor using short packet
as a part of panel programming.
v2: Rebase
v3 by Jani:
- Add FIXME note.
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 216a1753d246..9c424adc8b75 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -25,6 +25,7 @@
* Jani Nikula
*/
+#include
#include "intel_dsi.h"
static enum transcoder dsi_port_to_transcoder(enum port port)
@@ -636,6 +637,35 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder
*encoder,
gen11_dsi_configure_transcoder(encoder, pipe_config);
}
+static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct mipi_dsi_device *dsi;
+ enum port port;
+ enum transcoder dsi_trans;
+ u32 tmp;
+ int ret;
+
+ /* set maximum return packet size */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+
+ /*
+* FIXME: This uses the number of DW's currently in the payload
+* receive queue. This is probably not what we want here.
+*/
+ tmp = I915_READ(DSI_CMD_RXCTL(dsi_trans));
+ tmp &= NUMBER_RX_PLOAD_DW_MASK;
+ /* multiply "Number Rx Payload DW" by 4 to get max value */
+ tmp = tmp * 4;
+ dsi = intel_dsi->dsi_hosts[port]->device;
+ ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
+ if (ret < 0)
+ DRM_ERROR("error setting max return pkt size%d\n", tmp);
+ }
+}
+
static void __attribute__((unused))
gen11_dsi_pre_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config,
@@ -650,6 +680,9 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
/* step4: enable DSI port and DPHY */
gen11_dsi_enable_port_and_phy(encoder, pipe_config);
+ /* step5: program and powerup panel */
+ gen11_dsi_powerup_panel(encoder);
+
/* step6c: configure transcoder timings */
gen11_dsi_set_transcoder_timings(encoder, pipe_config);
--
2.11.0
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[Intel-gfx] [PATCH v8 14/38] drm/i915/icl: Disable DSI IO power
From: Madhav Chauhan
This patch configures mode of combo phy as DDI and
disable IO power for DDI ports used by DSI.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 44696848ffd7..ac22c74ae146 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -873,6 +873,26 @@ static void gen11_dsi_disable_port(struct intel_encoder
*encoder)
}
}
+static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ u32 tmp;
+
+ intel_display_power_put(dev_priv, POWER_DOMAIN_PORT_DDI_A_IO);
+
+ if (intel_dsi->dual_link)
+ intel_display_power_put(dev_priv, POWER_DOMAIN_PORT_DDI_B_IO);
+
+ /* set mode to DDI */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
+ tmp &= ~COMBO_PHY_MODE_DSI;
+ I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);
+ }
+}
+
static void __attribute__((unused)) gen11_dsi_disable(
struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
@@ -895,4 +915,7 @@ static void __attribute__((unused)) gen11_dsi_disable(
/* step3: disable port */
gen11_dsi_disable_port(encoder);
+
+ /* step4: disable IO power */
+ gen11_dsi_disable_io_power(encoder);
}
--
2.11.0
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[Intel-gfx] [PATCH v8 06/38] drm/i915/icl: Turn ON panel backlight
From: Madhav Chauhan
This patch enables backlight of DSI panel by using VBT
BACKLIGHT_ON sequence and panel specific functions.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 0f0447b6b1be..bffbb40cc0bc 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -752,6 +752,8 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
{
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+
/* step2: enable IO power */
gen11_dsi_enable_io_power(encoder);
@@ -769,4 +771,8 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
/* step6d: enable dsi transcoder */
gen11_dsi_enable_transcoder(encoder);
+
+ /* step7: enable backlight */
+ intel_panel_enable_backlight(pipe_config, conn_state);
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
}
--
2.11.0
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[Intel-gfx] [PATCH v8 16/38] drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers
From: Madhav Chauhan
Program the timeout values (in escape clock) for HS TX, LP RX and TA
timeout.
HX TX: Ensure that host does not continuously transmit in the HS
state. If this timer expires, then host will gracefully end its HS
transmission and allow the link to enter into LP state.
LP RX: Monitor the length of LP receptions from Peripheral. If timeout
happens then host will drive the stop state onto all data lanes (only
Data Lane 0 should be receiving anything from the Peripheral). This
effectively takes back ownership of the bus transmit in the HS state.
TA timeout: Timeout valuefor monitoring Bus Turn-Around (BTA) sequence.
BTA sequence should complete within a bounded amount of time, with
peripheral acknowledging BTA by driving the stop state.
v2 by Jani:
- Rebase
- Use intel_dsi_bitrate() and intel_dsi_tlpx_ns(intel_dsi)
- Squash HX TX, LP RX and TA timeout into one patch
- Fix bspec mode set sequence reference
- Add FIXME about two timeouts
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 52
drivers/gpu/drm/i915/intel_dsi.h | 1 +
drivers/gpu/drm/i915/intel_dsi_vbt.c | 1 +
3 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index ac22c74ae146..fd82f349ced9 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -685,6 +685,55 @@ static void gen11_dsi_enable_transcoder(struct
intel_encoder *encoder)
}
}
+static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ enum transcoder dsi_trans;
+ u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
+
+ /*
+* escape clock count calculation:
+* BYTE_CLK_COUNT = TIME_NS/(8 * UI)
+* UI (nsec) = (10^6)/Bitrate
+* TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
+* ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
+*/
+ divisor = intel_dsi_tlpx_ns(intel_dsi) * intel_dsi_bitrate(intel_dsi) *
1000;
+ mul = 8 * 100;
+ hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
+divisor);
+ lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
+ ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+
+ /* program hst_tx_timeout */
+ tmp = I915_READ(DSI_HSTX_TO(dsi_trans));
+ tmp &= ~HSTX_TIMEOUT_VALUE_MASK;
+ tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout);
+ I915_WRITE(DSI_HSTX_TO(dsi_trans), tmp);
+
+ /* FIXME: DSI_CALIB_TO */
+
+ /* program lp_rx_host timeout */
+ tmp = I915_READ(DSI_LPRX_HOST_TO(dsi_trans));
+ tmp &= ~LPRX_TIMEOUT_VALUE_MASK;
+ tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout);
+ I915_WRITE(DSI_LPRX_HOST_TO(dsi_trans), tmp);
+
+ /* FIXME: DSI_PWAIT_TO */
+
+ /* program turn around timeout */
+ tmp = I915_READ(DSI_TA_TO(dsi_trans));
+ tmp &= ~TA_TIMEOUT_VALUE_MASK;
+ tmp |= TA_TIMEOUT_VALUE(ta_timeout);
+ I915_WRITE(DSI_TA_TO(dsi_trans), tmp);
+ }
+}
+
static void
gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
@@ -704,6 +753,9 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
/* setup D-PHY timings */
gen11_dsi_setup_dphy_timings(encoder);
+ /* step 4h: setup DSI protocol timeouts */
+ gen11_dsi_setup_timeouts(encoder);
+
/* Step (4h, 4i, 4j, 4k): Configure transcoder */
gen11_dsi_configure_transcoder(encoder, pipe_config);
}
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 10fd1582a8e2..f2a3ddedcc5d 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -95,6 +95,7 @@ struct intel_dsi {
u16 lp_byte_clk;
/* timeouts in byte clocks */
+ u16 hs_tx_timeout;
u16 lp_rx_timeout;
u16 turn_arnd_val;
u16 rst_timer_val;
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index cca071406c25..80bd56e96143 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -799,6 +799,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
panel_id)
intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
intel_dsi->lp_rx_timeout = mipi_config->lp_rx_t
[Intel-gfx] [PATCH v8 18/38] drm/i915/icl: Allocate DSI encoder/connector
This patch allocates memory for DSI encoder and connector
which will be used for various DSI encoder/connector operations
and attaching the same to DRM subsystem. This patch also extracts
DSI modes info from VBT and save the desired mode info to connector.
v2 by Jani:
- Drop GEN11 prefix from encoder name
- Drop extra parenthesis
- Drop extra local variable
- Squash encoder power domain here
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 96 ++
1 file changed, 88 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 01f422df8c23..a117ecc6c5a3 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -799,10 +799,9 @@ static void gen11_dsi_powerup_panel(struct intel_encoder
*encoder)
wait_for_cmds_dispatched_to_panel(encoder);
}
-static void __attribute__((unused))
-gen11_dsi_pre_enable(struct intel_encoder *encoder,
-const struct intel_crtc_state *pipe_config,
-const struct drm_connector_state *conn_state)
+static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
+const struct intel_crtc_state *pipe_config,
+const struct drm_connector_state *conn_state)
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -945,10 +944,9 @@ static void gen11_dsi_disable_io_power(struct
intel_encoder *encoder)
}
}
-static void __attribute__((unused)) gen11_dsi_disable(
- struct intel_encoder *encoder,
- const struct intel_crtc_state *old_crtc_state,
- const struct drm_connector_state *old_conn_state)
+static void gen11_dsi_disable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *old_crtc_state,
+ const struct drm_connector_state *old_conn_state)
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -972,10 +970,92 @@ static void __attribute__((unused)) gen11_dsi_disable(
gen11_dsi_disable_io_power(encoder);
}
+static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
+{
+ intel_encoder_destroy(encoder);
+}
+
+static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
+ .destroy = gen11_dsi_encoder_destroy,
+};
+
+static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
+};
+
void icl_dsi_init(struct drm_i915_private *dev_priv)
{
+ struct drm_device *dev = &dev_priv->drm;
+ struct intel_dsi *intel_dsi;
+ struct intel_encoder *encoder;
+ struct intel_connector *intel_connector;
+ struct drm_connector *connector;
+ struct drm_display_mode *scan, *fixed_mode = NULL;
enum port port;
if (!intel_bios_is_dsi_present(dev_priv, &port))
return;
+
+ intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
+ if (!intel_dsi)
+ return;
+
+ intel_connector = intel_connector_alloc();
+ if (!intel_connector) {
+ kfree(intel_dsi);
+ return;
+ }
+
+ encoder = &intel_dsi->base;
+ intel_dsi->attached_connector = intel_connector;
+ connector = &intel_connector->base;
+
+ /* register DSI encoder with DRM subsystem */
+ drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs,
+DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
+
+ encoder->pre_enable = gen11_dsi_pre_enable;
+ encoder->disable = gen11_dsi_disable;
+ encoder->port = port;
+ encoder->type = INTEL_OUTPUT_DSI;
+ encoder->cloneable = 0;
+ encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
+ encoder->power_domain = POWER_DOMAIN_PORT_DSI;
+
+ /* register DSI connector with DRM subsystem */
+ drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
+ DRM_MODE_CONNECTOR_DSI);
+ connector->display_info.subpixel_order = SubPixelHorizontalRGB;
+ connector->interlace_allowed = false;
+ connector->doublescan_allowed = false;
+
+ /* attach connector to encoder */
+ intel_connector_attach_encoder(intel_connector, encoder);
+
+ /* fill mode info from VBT */
+ mutex_lock(&dev->mode_config.mutex);
+ intel_dsi_vbt_get_modes(intel_dsi);
+ list_for_each_entry(scan, &connector->probed_modes, head) {
+ if (scan->type & DRM_MODE_TYPE_PREFERRED) {
+ fixed_mode = drm_mode_duplicate(dev, scan);
+ break;
+ }
+ }
+ mutex_unlock(&dev->mode_config.mutex);
+
+ if (!fixed_mode) {
+ DRM_ERROR("DSI fixed mode info missing\n");
+ goto err;
+ }
+
+ connector->display_info.width_mm = fixed_mode->width_m
[Intel-gfx] [PATCH v8 02/38] drm/i915/dsi: move connector mode functions to common file
From: Madhav Chauhan
Move DSI connector functions to intel_dsi.c and make them available to
both legacy and ICL DSI.
v2 by Jani:
- Move the functions to intel_dsi.c
- Don't reuse intel_dsi_connector_destroy()
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 47 +++
drivers/gpu/drm/i915/intel_dsi.h | 3 +++
drivers/gpu/drm/i915/vlv_dsi.c | 48
3 files changed, 50 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 97e04c272612..b9d5ef79015e 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -29,6 +29,53 @@ int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi)
}
}
+int intel_dsi_get_modes(struct drm_connector *connector)
+{
+ struct intel_connector *intel_connector = to_intel_connector(connector);
+ struct drm_display_mode *mode;
+
+ DRM_DEBUG_KMS("\n");
+
+ if (!intel_connector->panel.fixed_mode) {
+ DRM_DEBUG_KMS("no fixed mode\n");
+ return 0;
+ }
+
+ mode = drm_mode_duplicate(connector->dev,
+ intel_connector->panel.fixed_mode);
+ if (!mode) {
+ DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
+ return 0;
+ }
+
+ drm_mode_probed_add(connector, mode);
+ return 1;
+}
+
+enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ struct intel_connector *intel_connector = to_intel_connector(connector);
+ const struct drm_display_mode *fixed_mode =
intel_connector->panel.fixed_mode;
+ int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+
+ DRM_DEBUG_KMS("\n");
+
+ if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
+ return MODE_NO_DBLESCAN;
+
+ if (fixed_mode) {
+ if (mode->hdisplay > fixed_mode->hdisplay)
+ return MODE_PANEL;
+ if (mode->vdisplay > fixed_mode->vdisplay)
+ return MODE_PANEL;
+ if (fixed_mode->clock > max_dotclk)
+ return MODE_CLOCK_HIGH;
+ }
+
+ return MODE_OK;
+}
+
struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
const struct mipi_dsi_host_ops
*funcs,
enum port port)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 09f0fa9ccc7d..10fd1582a8e2 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -152,6 +152,9 @@ int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
/* vlv_dsi.c */
void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
+int intel_dsi_get_modes(struct drm_connector *connector);
+enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode);
struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
const struct mipi_dsi_host_ops
*funcs,
enum port port);
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index cbb935a9acf3..bab87b62bc2d 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -1212,31 +1212,6 @@ static void intel_dsi_get_config(struct intel_encoder
*encoder,
}
}
-static enum drm_mode_status
-intel_dsi_mode_valid(struct drm_connector *connector,
-struct drm_display_mode *mode)
-{
- struct intel_connector *intel_connector = to_intel_connector(connector);
- const struct drm_display_mode *fixed_mode =
intel_connector->panel.fixed_mode;
- int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
-
- DRM_DEBUG_KMS("\n");
-
- if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
- return MODE_NO_DBLESCAN;
-
- if (fixed_mode) {
- if (mode->hdisplay > fixed_mode->hdisplay)
- return MODE_PANEL;
- if (mode->vdisplay > fixed_mode->vdisplay)
- return MODE_PANEL;
- if (fixed_mode->clock > max_dotclk)
- return MODE_CLOCK_HIGH;
- }
-
- return MODE_OK;
-}
-
/* return txclkesc cycles in terms of divider and duration in us */
static u16 txclkesc(u32 divider, unsigned int us)
{
@@ -1559,29 +1534,6 @@ static void intel_dsi_unprepare(struct intel_encoder
*encoder)
}
}
-static int intel_dsi_get_modes(struct drm_connector *connector)
-{
- struct intel_connector *intel_connector = to_intel_connector(connector);
-
[Intel-gfx] [PATCH v8 04/38] drm/i915/icl: Power on DSI panel
From: Madhav Chauhan
This patch execute poweron, deassert reset, display on
VBT sequences and send TURN_ON DSI command to panel for
powering it up.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 9c424adc8b75..d9c91001f107 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -664,6 +664,13 @@ static void gen11_dsi_powerup_panel(struct intel_encoder
*encoder)
if (ret < 0)
DRM_ERROR("error setting max return pkt size%d\n", tmp);
}
+
+ /* panel power on related mipi dsi vbt sequences */
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
+ intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
}
static void __attribute__((unused))
--
2.11.0
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[Intel-gfx] [PATCH v8 07/38] drm/i915/icl: Turn OFF panel backlight
From: Madhav Chauhan
This patch disbles backlight of DSI panel by using VBT
BACKLIGHT_OFF sequence and panel specific disable functions.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index bffbb40cc0bc..f7f48ff147d0 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -776,3 +776,15 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
intel_panel_enable_backlight(pipe_config, conn_state);
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
}
+
+static void __attribute__((unused)) gen11_dsi_disable(
+ struct intel_encoder *encoder,
+ const struct intel_crtc_state *old_crtc_state,
+ const struct drm_connector_state *old_conn_state)
+{
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+
+ /* step1: turn off backlight */
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
+ intel_panel_disable_backlight(old_conn_state);
+}
--
2.11.0
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[Intel-gfx] [PATCH v8 19/38] drm/i915/icl: Allocate hosts for DSI ports
This patch allocates DSI host structure for each
DSI port available on gen11 and register them with
DSI fwk of DRM. Some of the DSI host operations are
also registered as part of this. This patch also fills
MIPI config block info from VBT to local structure.
v2 by Jani:
- indentation
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index a117ecc6c5a3..d0c60d402dfe 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -982,6 +982,23 @@ static const struct drm_encoder_funcs
gen11_dsi_encoder_funcs = {
static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
};
+static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
+struct mipi_dsi_device *dsi)
+{
+ return 0;
+}
+
+static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
+struct mipi_dsi_device *dsi)
+{
+ return 0;
+}
+
+static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
+ .attach = gen11_dsi_host_attach,
+ .detach = gen11_dsi_host_detach,
+};
+
void icl_dsi_init(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = &dev_priv->drm;
@@ -1052,6 +1069,21 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
intel_panel_setup_backlight(connector, INVALID_PIPE);
+ for_each_dsi_port(port, intel_dsi->ports) {
+ struct intel_dsi_host *host;
+
+ host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops,
port);
+ if (!host)
+ goto err;
+
+ intel_dsi->dsi_hosts[port] = host;
+ }
+
+ if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
+ DRM_DEBUG_KMS("no device found\n");
+ goto err;
+ }
+
return;
err:
--
2.11.0
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[Intel-gfx] [PATCH v8 15/38] drm/i915/icl: Define DSI timeout registers
From: Madhav Chauhan
This patch defines DSI_HTX_TO, DSI_LRX_H_TO, DSI_PWAIT_TO
and DSI_TA_TO registers for DSI transcoders '0' and '1'.
They are used for contention recovery on DPHY.
v2: Define SHIFT for bitfields.
v3 by Jani:
- Fix timeout bit definitions
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 43 +
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bcee91bcfba6..8d089ef848b2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10533,6 +10533,49 @@ enum skl_power_gate {
#define LINK_ULPS_TYPE_LP11 (1 << 8)
#define LINK_ENTER_ULPS (1 << 0)
+/* DSI timeout registers */
+#define _DSI_HSTX_TO_0 0x6b044
+#define _DSI_HSTX_TO_1 0x6b844
+#define DSI_HSTX_TO(tc)_MMIO_DSI(tc, \
+ _DSI_HSTX_TO_0,\
+ _DSI_HSTX_TO_1)
+#define HSTX_TIMEOUT_VALUE_MASK (0x << 16)
+#define HSTX_TIMEOUT_VALUE_SHIFT 16
+#define HSTX_TIMEOUT_VALUE(x) ((x) << 16)
+#define HSTX_TIMED_OUT(1 << 0)
+
+#define _DSI_LPRX_HOST_TO_00x6b048
+#define _DSI_LPRX_HOST_TO_10x6b848
+#define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \
+ _DSI_LPRX_HOST_TO_0,\
+ _DSI_LPRX_HOST_TO_1)
+#define LPRX_TIMED_OUT(1 << 16)
+#define LPRX_TIMEOUT_VALUE_MASK (0x << 0)
+#define LPRX_TIMEOUT_VALUE_SHIFT 0
+#define LPRX_TIMEOUT_VALUE(x) ((x) << 0)
+
+#define _DSI_PWAIT_TO_00x6b040
+#define _DSI_PWAIT_TO_10x6b840
+#define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \
+ _DSI_PWAIT_TO_0,\
+ _DSI_PWAIT_TO_1)
+#define PRESET_TIMEOUT_VALUE_MASK (0x << 16)
+#define PRESET_TIMEOUT_VALUE_SHIFT16
+#define PRESET_TIMEOUT_VALUE(x) ((x) << 16)
+#define PRESPONSE_TIMEOUT_VALUE_MASK (0x << 0)
+#define PRESPONSE_TIMEOUT_VALUE_SHIFT 0
+#define PRESPONSE_TIMEOUT_VALUE(x)((x) << 0)
+
+#define _DSI_TA_TO_0 0x6b04c
+#define _DSI_TA_TO_1 0x6b84c
+#define DSI_TA_TO(tc) _MMIO_DSI(tc, \
+ _DSI_TA_TO_0,\
+ _DSI_TA_TO_1)
+#define TA_TIMED_OUT (1 << 16)
+#define TA_TIMEOUT_VALUE_MASK (0x << 0)
+#define TA_TIMEOUT_VALUE_SHIFT0
+#define TA_TIMEOUT_VALUE(x) ((x) << 0)
+
/* bits 31:0 */
#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
--
2.11.0
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[Intel-gfx] [PATCH v8 09/38] drm/i915/icl: Power down DSI panel
From: Madhav Chauhan
This patch sends command and executes display off,
assert reset, power off VBT seqeuences to power
down DSI panel. Patch also adds high level function
to wrap all the panel sepcific programming during
DSI disabling.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 644ad7475920..a7b1a9eae04b 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -800,6 +800,18 @@ static void gen11_dsi_disable_transcoder(struct
intel_encoder *encoder)
}
}
+static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
+{
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
+
+ /* ensure cmds dispatched to panel */
+ wait_for_cmds_dispatched_to_panel(encoder);
+}
+
static void __attribute__((unused)) gen11_dsi_disable(
struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
@@ -813,4 +825,7 @@ static void __attribute__((unused)) gen11_dsi_disable(
/* step2d,e: disable transcoder and wait */
gen11_dsi_disable_transcoder(encoder);
+
+ /* step2f,g: powerdown panel */
+ gen11_dsi_powerdown_panel(encoder);
}
--
2.11.0
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[Intel-gfx] [PATCH v8 21/38] drm/i915/icl: Fetch DSI pkt to be transferred
From: Madhav Chauhan
This patch retrieves DSI pkt (from DSI msg) to be
sent over DSI link using DRM DSI exported functions.
A wrapper function is also added as "DSI host transfer"
for sending DSI data/cmd.
v2 by Jani:
- Use the new credit available helper
- Use int for free_credits
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 62 ++
1 file changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index d0c60d402dfe..c7b77cd81e45 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -107,6 +107,44 @@ static void wait_for_cmds_dispatched_to_panel(struct
intel_encoder *encoder)
}
}
+static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
+ struct mipi_dsi_packet pkt, bool enable_lpdt)
+{
+ struct intel_dsi *intel_dsi = host->intel_dsi;
+ struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+ enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
+ u32 tmp;
+ int free_credits;
+
+ /* check if header credit available */
+ free_credits = header_credits_available(dev_priv, dsi_trans);
+ if (free_credits < 1) {
+ DRM_ERROR("send pkt header failed, not enough hdr credits\n");
+ return -1;
+ }
+
+ tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans));
+
+ if (pkt.payload)
+ tmp |= PAYLOAD_PRESENT;
+ else
+ tmp &= ~PAYLOAD_PRESENT;
+
+ tmp &= ~VBLANK_FENCE;
+
+ if (enable_lpdt)
+ tmp |= LP_DATA_TRANSFER;
+
+ tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
+ tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT);
+ tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT);
+ tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT);
+ tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT);
+ I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp);
+
+ return 0;
+}
+
static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -994,9 +1032,33 @@ static int gen11_dsi_host_detach(struct mipi_dsi_host
*host,
return 0;
}
+static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
+ const struct mipi_dsi_msg *msg)
+{
+ struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
+ struct mipi_dsi_packet dsi_pkt;
+ ssize_t ret;
+ bool enable_lpdt = false;
+
+ ret = mipi_dsi_create_packet(&dsi_pkt, msg);
+ if (ret < 0)
+ return ret;
+
+ if (msg->flags & MIPI_DSI_MSG_USE_LPM)
+ enable_lpdt = true;
+
+ /* send packet header */
+ ret = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
+ if (ret < 0)
+ return ret;
+
+ return ret;
+}
+
static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
.attach = gen11_dsi_host_attach,
.detach = gen11_dsi_host_detach,
+ .transfer = gen11_dsi_host_transfer,
};
void icl_dsi_init(struct drm_i915_private *dev_priv)
--
2.11.0
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[Intel-gfx] [PATCH v8 25/38] drm/i915/icl: Add DSI connector functions
From: Madhav Chauhan
This patch assigns connector functions for DSI to
DRM connector structure.
v2 by Jani:
- use common connector destroy hook
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 0c1f84cca16e..5b33b7ac8e8f 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -26,6 +26,7 @@
*/
#include
+#include
#include "intel_dsi.h"
static inline int header_credits_available(struct drm_i915_private *dev_priv,
@@ -1117,6 +1118,14 @@ static const struct drm_encoder_funcs
gen11_dsi_encoder_funcs = {
};
static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
+ .late_register = intel_connector_register,
+ .early_unregister = intel_connector_unregister,
+ .destroy = intel_connector_destroy,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .atomic_get_property = intel_digital_connector_atomic_get_property,
+ .atomic_set_property = intel_digital_connector_atomic_set_property,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+ .atomic_duplicate_state = intel_digital_connector_duplicate_state,
};
static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
--
2.11.0
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[Intel-gfx] [PATCH v8 26/38] drm/i915/icl: Add DSI connector helper functions
From: Madhav Chauhan
This patch registers DSI connectors helper functions
with DRM driver.
v2 by Jani:
- Indentation change
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 5b33b7ac8e8f..c12c7d53bcff 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1128,6 +1128,12 @@ static const struct drm_connector_funcs
gen11_dsi_connector_funcs = {
.atomic_duplicate_state = intel_digital_connector_duplicate_state,
};
+static const struct drm_connector_helper_funcs
gen11_dsi_connector_helper_funcs = {
+ .get_modes = intel_dsi_get_modes,
+ .mode_valid = intel_dsi_mode_valid,
+ .atomic_check = intel_digital_connector_atomic_check,
+};
+
static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
struct mipi_dsi_device *dsi)
{
@@ -1224,6 +1230,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
/* register DSI connector with DRM subsystem */
drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
DRM_MODE_CONNECTOR_DSI);
+ drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
connector->display_info.subpixel_order = SubPixelHorizontalRGB;
connector->interlace_allowed = false;
connector->doublescan_allowed = false;
--
2.11.0
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[Intel-gfx] [PATCH v8 27/38] drm/i915/icl: Add DSI encoder remaining functions
From: Madhav Chauhan
This patch implements compute config and enable function
for Gen11 DSI encoder which is required at the time of
modeset. Enable function is empty as functionality is
implemented inside pre-enable function but still needed
otherwise null pointer dereference during modeset.
v2 by Jani:
- drop the enable nop hook
- fixed_mode is always true
- HAS_GMCH_DISPLAY() is always false
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index c12c7d53bcff..7a000a660c12 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1068,6 +1068,37 @@ static void gen11_dsi_get_config(struct intel_encoder
*encoder,
pipe_config->port_clock = pixel_clk;
}
+static bool gen11_dsi_compute_config(struct intel_encoder *encoder,
+struct intel_crtc_state *pipe_config,
+struct drm_connector_state *conn_state)
+{
+ struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
+ base);
+ struct intel_connector *intel_connector = intel_dsi->attached_connector;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+ const struct drm_display_mode *fixed_mode =
+ intel_connector->panel.fixed_mode;
+ struct drm_display_mode *adjusted_mode =
+ &pipe_config->base.adjusted_mode;
+
+ intel_fixed_panel_mode(fixed_mode, adjusted_mode);
+ intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode);
+
+ adjusted_mode->flags = 0;
+
+ /* Dual link goes to trancoder DSI'0' */
+ if (intel_dsi->ports == BIT(PORT_B))
+ pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
+ else
+ pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
+
+ pipe_config->clock_set = true;
+
+ //TODO: Add check if DSI PLL calculation is done
+
+ return true;
+}
+
static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe)
{
@@ -1221,6 +1252,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
encoder->disable = gen11_dsi_disable;
encoder->port = port;
encoder->get_config = gen11_dsi_get_config;
+ encoder->compute_config = gen11_dsi_compute_config;
encoder->get_hw_state = gen11_dsi_get_hw_state;
encoder->type = INTEL_OUTPUT_DSI;
encoder->cloneable = 0;
--
2.11.0
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[Intel-gfx] [PATCH v8 28/38] drm/i915/icl: Fill DSI ports info
From: Madhav Chauhan
This patch fills backlight, CABC and general port
info for Gen11 DSI.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 7a000a660c12..b2897281d42c 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1292,6 +1292,14 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
intel_panel_setup_backlight(connector, INVALID_PIPE);
+ if (dev_priv->vbt.dsi.config->dual_link)
+ intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
+ else
+ intel_dsi->ports = BIT(port);
+
+ intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
+ intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
+
for_each_dsi_port(port, intel_dsi->ports) {
struct intel_dsi_host *host;
--
2.11.0
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[Intel-gfx] [PATCH v8 24/38] drm/i915/icl: Get HW state for DSI encoder
From: Madhav Chauhan
This patch read out the current hw state for DSI and
return true if encoder is active.
v2 by Jani:
- Squash connector get hw state hook here
- Squash encode get hw state fix here
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 42 ++
1 file changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 83612c444eab..0c1f84cca16e 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1067,6 +1067,46 @@ static void gen11_dsi_get_config(struct intel_encoder
*encoder,
pipe_config->port_clock = pixel_clk;
}
+static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
+ enum pipe *pipe)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ u32 tmp;
+ enum port port;
+ enum transcoder dsi_trans;
+ bool ret = false;
+
+ if (!intel_display_power_get_if_enabled(dev_priv,
+ encoder->power_domain))
+ return false;
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
+ switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
+ case TRANS_DDI_EDP_INPUT_A_ON:
+ *pipe = PIPE_A;
+ break;
+ case TRANS_DDI_EDP_INPUT_B_ONOFF:
+ *pipe = PIPE_B;
+ break;
+ case TRANS_DDI_EDP_INPUT_C_ONOFF:
+ *pipe = PIPE_C;
+ break;
+ default:
+ DRM_ERROR("Invalid PIPE input\n");
+ goto out;
+ }
+
+ tmp = I915_READ(PIPECONF(dsi_trans));
+ ret = tmp & PIPECONF_ENABLE;
+ }
+out:
+ intel_display_power_put(dev_priv, encoder->power_domain);
+ return ret;
+}
+
static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
{
intel_encoder_destroy(encoder);
@@ -1166,6 +1206,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
encoder->disable = gen11_dsi_disable;
encoder->port = port;
encoder->get_config = gen11_dsi_get_config;
+ encoder->get_hw_state = gen11_dsi_get_hw_state;
encoder->type = INTEL_OUTPUT_DSI;
encoder->cloneable = 0;
encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
@@ -1177,6 +1218,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
connector->display_info.subpixel_order = SubPixelHorizontalRGB;
connector->interlace_allowed = false;
connector->doublescan_allowed = false;
+ intel_connector->get_hw_state = intel_connector_get_hw_state;
/* attach connector to encoder */
intel_connector_attach_encoder(intel_connector, encoder);
--
2.11.0
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[Intel-gfx] [PATCH v8 20/38] drm/i915/icl: Add DSI packet payload/header registers
From: Madhav Chauhan
This patch defines payload/header registers for each DSI
transcoder used for transmitting DSI packets.
v2 by Jani:
- Drop full register mask and shift for payload
- Use lower case for hex 0x
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8d089ef848b2..639667d0fb00 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10523,6 +10523,28 @@ enum skl_power_gate {
#define MAX_HEADER_CREDIT 0x10
#define MAX_PLOAD_CREDIT 0x40
+#define _DSI_CMD_TXHDR_0 0x6b100
+#define _DSI_CMD_TXHDR_1 0x6b900
+#define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \
+ _DSI_CMD_TXHDR_0,\
+ _DSI_CMD_TXHDR_1)
+#define PAYLOAD_PRESENT (1 << 31)
+#define LP_DATA_TRANSFER (1 << 30)
+#define VBLANK_FENCE (1 << 29)
+#define PARAM_WC_MASK (0x << 8)
+#define PARAM_WC_LOWER_SHIFT 8
+#define PARAM_WC_UPPER_SHIFT 16
+#define VC_MASK (0x3 << 6)
+#define VC_SHIFT 6
+#define DT_MASK (0x3f << 0)
+#define DT_SHIFT 0
+
+#define _DSI_CMD_TXPYLD_0 0x6b104
+#define _DSI_CMD_TXPYLD_1 0x6b904
+#define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \
+ _DSI_CMD_TXPYLD_0,\
+ _DSI_CMD_TXPYLD_1)
+
#define _DSI_LP_MSG_0 0x6b0d8
#define _DSI_LP_MSG_1 0x6b8d8
#define DSI_LP_MSG(tc) _MMIO_DSI(tc, \
--
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[Intel-gfx] [PATCH v8 17/38] drm/i915/icl: Find DSI presence for ICL
From: Madhav Chauhan
This patch detects DSI presence for ICL platform
by reading VBT. DSI detection is done while initializing
DSI using newly added function intel_gen11_dsi_init.
v2 by Jani:
- Preserve old behavour of intel_bios_is_dsi_present()
- s/intel_gen11_dsi_init/icl_dsi_init/g
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 8
drivers/gpu/drm/i915/intel_bios.c| 12 ++--
drivers/gpu/drm/i915/intel_display.c | 1 +
drivers/gpu/drm/i915/intel_drv.h | 3 +++
4 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index fd82f349ced9..01f422df8c23 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -971,3 +971,11 @@ static void __attribute__((unused)) gen11_dsi_disable(
/* step4: disable IO power */
gen11_dsi_disable_io_power(encoder);
}
+
+void icl_dsi_init(struct drm_i915_private *dev_priv)
+{
+ enum port port;
+
+ if (!intel_bios_is_dsi_present(dev_priv, &port))
+ return;
+}
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 1faa494e2bc9..5fa2133f801d 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -2039,17 +2039,17 @@ bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv,
dvo_port = child->dvo_port;
- switch (dvo_port) {
- case DVO_PORT_MIPIA:
- case DVO_PORT_MIPIC:
+ if (dvo_port == DVO_PORT_MIPIA ||
+ (dvo_port == DVO_PORT_MIPIB && IS_ICELAKE(dev_priv)) ||
+ (dvo_port == DVO_PORT_MIPIC && !IS_ICELAKE(dev_priv))) {
if (port)
*port = dvo_port - DVO_PORT_MIPIA;
return true;
- case DVO_PORT_MIPIB:
- case DVO_PORT_MIPID:
+ } else if (dvo_port == DVO_PORT_MIPIB ||
+ dvo_port == DVO_PORT_MIPIC ||
+ dvo_port == DVO_PORT_MIPID) {
DRM_DEBUG_KMS("VBT has unsupported DSI port %c\n",
port_name(dvo_port - DVO_PORT_MIPIA));
- break;
}
}
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c3cadc09f859..1d46f06ede37 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14128,6 +14128,7 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_ddi_init(dev_priv, PORT_D);
intel_ddi_init(dev_priv, PORT_E);
intel_ddi_init(dev_priv, PORT_F);
+ icl_dsi_init(dev_priv);
} else if (IS_GEN9_LP(dev_priv)) {
/*
* FIXME: Broxton doesn't support port detection via the
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 268afb6d2746..3081cca1a151 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1854,6 +1854,9 @@ void intel_dp_mst_encoder_cleanup(struct
intel_digital_port *intel_dig_port);
/* vlv_dsi.c */
void vlv_dsi_init(struct drm_i915_private *dev_priv);
+/* icl_dsi.c */
+void icl_dsi_init(struct drm_i915_private *dev_priv);
+
/* intel_dsi_dcs_backlight.c */
int intel_dsi_dcs_init_backlight_funcs(struct intel_connector
*intel_connector);
--
2.11.0
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[Intel-gfx] [PATCH v8 23/38] drm/i915/icl: Add get config functionality for DSI
From: Madhav Chauhan
This patch implements the functionality for getting PIPE
configuration to which DSI encoder is connected. Used during
the atomic modeset.
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 58774a1ac84b..83612c444eab 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1054,6 +1054,19 @@ static void gen11_dsi_disable(struct intel_encoder
*encoder,
gen11_dsi_disable_io_power(encoder);
}
+static void gen11_dsi_get_config(struct intel_encoder *encoder,
+struct intel_crtc_state *pipe_config)
+{
+ struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
+ base);
+ u32 pixel_clk;
+
+ //FIXME: Calculate pixel clock using PLL functions once implemented.
+ pixel_clk = intel_dsi->pclk;
+ pipe_config->base.adjusted_mode.crtc_clock = pixel_clk;
+ pipe_config->port_clock = pixel_clk;
+}
+
static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
{
intel_encoder_destroy(encoder);
@@ -1152,6 +1165,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
encoder->pre_enable = gen11_dsi_pre_enable;
encoder->disable = gen11_dsi_disable;
encoder->port = port;
+ encoder->get_config = gen11_dsi_get_config;
encoder->type = INTEL_OUTPUT_DSI;
encoder->cloneable = 0;
encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
--
2.11.0
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[Intel-gfx] [PATCH v8 22/38] drm/i915/icl: Load DSI packet payload to queue
This patch adds DSI packet payload to command payload
queue using credit based mechanism for *long* packets.
v2 by Jani:
- Add intel_dsi local variable for better code flow
- Use the new credit available helper
- Use int for free_credits, i, and j
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 57 ++
1 file changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index c7b77cd81e45..58774a1ac84b 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -107,6 +107,33 @@ static void wait_for_cmds_dispatched_to_panel(struct
intel_encoder *encoder)
}
}
+static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data,
+ u32 len)
+{
+ struct intel_dsi *intel_dsi = host->intel_dsi;
+ struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+ enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
+ int free_credits;
+ int i, j;
+
+ for (i = 0; i < len; i += 4) {
+ u32 tmp = 0;
+
+ free_credits = payload_credits_available(dev_priv, dsi_trans);
+ if (free_credits < 1) {
+ DRM_ERROR("Payload credit not available\n");
+ return false;
+ }
+
+ for (j = 0; j < min_t(u32, len - i, 4); j++)
+ tmp |= *data++ << 8 * j;
+
+ I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp);
+ }
+
+ return true;
+}
+
static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
struct mipi_dsi_packet pkt, bool enable_lpdt)
{
@@ -145,6 +172,25 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
return 0;
}
+static int dsi_send_pkt_payld(struct intel_dsi_host *host,
+ struct mipi_dsi_packet pkt)
+{
+ /* payload queue can accept *256 bytes*, check limit */
+ if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) {
+ DRM_ERROR("payload size exceeds max queue limit\n");
+ return -1;
+ }
+
+ /* load data into command payload queue */
+ if (!add_payld_to_queue(host, pkt.payload,
+ pkt.payload_length)) {
+ DRM_ERROR("adding payload to queue failed\n");
+ return -1;
+ }
+
+ return 0;
+}
+
static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -1052,6 +1098,17 @@ static ssize_t gen11_dsi_host_transfer(struct
mipi_dsi_host *host,
if (ret < 0)
return ret;
+ /* only long packet contains payload */
+ if (mipi_dsi_packet_format_is_long(msg->type)) {
+ ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt);
+ if (ret < 0)
+ return ret;
+ }
+
+ //TODO: add payload receive code if needed
+
+ ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
+
return ret;
}
--
2.11.0
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[Intel-gfx] [PATCH v8 31/38] drm/i915/icl: Define Panel power ctrl register
From: Madhav Chauhan
There are two panel power sequencers. Each register
has two addressable instances. This patch defines
both the instances of Panel power control register
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b9aaa71dabe2..5f51a258d87b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4592,6 +4592,17 @@ enum {
#define _PP_STATUS 0x61200
#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
#define PP_ON(1 << 31)
+
+#define _PP_CONTROL_1 0xc7204
+#define _PP_CONTROL_2 0xc7304
+#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
+ _PP_CONTROL_2)
+#define POWER_CYCLE_DELAY_MASK(0x1f << 4)
+#define POWER_CYCLE_DELAY_SHIFT 4
+#define VDD_OVERRIDE_FORCE(1 << 3)
+#define BACKLIGHT_ENABLE (1 << 2)
+#define PWR_DOWN_ON_RESET (1 << 1)
+#define PWR_STATE_TARGET (1 << 0)
/*
* Indicates that all dependencies of the panel are on:
*
--
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[Intel-gfx] [PATCH v8 29/38] drm/i915/icl: Add DSS_CTL Registers
From: Anusha Srivatsa
Add defines for DSS_CTL registers.
These registers specify the big joiner, splitter,
overlap pixels and info regarding
compression enabled on left or right branch.
v2:
- rebase. Remove overlapping defines(James Ausmus)
- Rename the register to ICL_DSS_CTL1/2_PIPE_ (manasi)
- take pixels as an argument for overlap.(Manasi)
v3:
- rebase. merge DSS_CTL1/2 introduced in Madhav's patch
to avoid confusion (madhav chauhan)
- Rename registers in accordance to BSpec (Madhav, Rodrigo)
- Add define to conditionally check the buffer target depth (James Ausmus)
v4:
- remove redundant definitions.(madhav)
v5:
- Add mask for overlap pixels.
- Code Style changes.(Madhav)
v6:
- Code style changes. (Madhav)
Suggested-by: Madhav Chauhan
Cc: Madhav Chauhan
cc: Rodrigo Vivi
Cc: James Ausmus
Cc: Gaurav Singh
Cc: Jani Nikula
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 33 +
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 639667d0fb00..b9aaa71dabe2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10033,6 +10033,39 @@ enum skl_power_gate {
_ICL_DSI_IO_MODECTL_1)
#define COMBO_PHY_MODE_DSI(1 << 0)
+/* Display Stream Splitter Control */
+#define DSS_CTL1 _MMIO(0x67400)
+#define SPLITTER_ENABLE (1 << 31)
+#define JOINER_ENABLE (1 << 30)
+#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
+#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
+#define OVERLAP_PIXELS_MASK (0xf << 16)
+#define OVERLAP_PIXELS(pixels)((pixels) << 16)
+#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
+#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
+#define MAX_DL_BUFFER_TARGET_DEPTH0x5A0
+
+#define DSS_CTL2 _MMIO(0x67404)
+#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
+#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
+#define RIGHT_DL_BUF_TARGET_DEPTH_MASK(0xfff << 0)
+#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
+
+#define _PIPE_DSS_CTL1_PB 0x78200
+#define _PIPE_DSS_CTL1_PC 0x78400
+#define PIPE_DSS_CTL1(pipe)_MMIO_PIPE((pipe) - PIPE_B, \
+ _PIPE_DSS_CTL1_PB, \
+ _PIPE_DSS_CTL1_PC)
+#define BIG_JOINER_ENABLE (1 << 29)
+#define MASTER_BIG_JOINER_ENABLE (1 << 28)
+#define VGA_CENTERING_ENABLE (1 << 27)
+
+#define _PIPE_DSS_CTL2_PB 0x78204
+#define _PIPE_DSS_CTL2_PC 0x78404
+#define PIPE_DSS_CTL2(pipe)_MMIO_PIPE((pipe) - PIPE_B, \
+ _PIPE_DSS_CTL2_PB, \
+ _PIPE_DSS_CTL2_PC)
+
#define BXT_P_DSI_REGULATOR_CFG_MMIO(0x160020)
#define STAP_SELECT (1 << 0)
--
2.11.0
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[Intel-gfx] [PATCH v8 34/38] drm/i915/icl: Add changes to program DSI panel GPIOs
From: Madhav Chauhan
For ICELAKE DSI, Display Pins are the only GPIOs
that need to be programmed. So DSI driver should have
its own implementation to toggle these pins based on
GPIO info coming from VBT sequences instead of using
platform specific GPIO driver.
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_vbt.c | 46 +++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 8177305b9c87..04423248bbd7 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -334,6 +334,48 @@ static void bxt_exec_gpio(struct drm_i915_private
*dev_priv,
gpiod_set_value(gpio_desc, value);
}
+static void icl_exec_gpio(struct drm_i915_private *dev_priv,
+ u8 gpio_source, u8 gpio_index, bool value)
+{
+ u32 val;
+
+ switch (gpio_index) {
+ case ICL_GPIO_DDSP_HPD_A:
+ val = I915_READ(SHOTPLUG_CTL_DDI);
+ val &= ~ICP_DDIA_HPD_ENABLE;
+ I915_WRITE(SHOTPLUG_CTL_DDI, val);
+ val = I915_READ(SHOTPLUG_CTL_DDI);
+
+ if (value)
+ val |= ICP_DDIA_HPD_OP_DRIVE_1;
+ else
+ val &= ~ICP_DDIA_HPD_OP_DRIVE_1;
+
+ I915_WRITE(SHOTPLUG_CTL_DDI, val);
+ break;
+ case ICL_GPIO_L_VDDEN_1:
+ val = I915_READ(ICP_PP_CONTROL(1));
+ if (value)
+ val |= PWR_STATE_TARGET;
+ else
+ val &= ~PWR_STATE_TARGET;
+ I915_WRITE(ICP_PP_CONTROL(1), val);
+ break;
+ case ICL_GPIO_L_BKLTEN_1:
+ val = I915_READ(ICP_PP_CONTROL(1));
+ if (value)
+ val |= BACKLIGHT_ENABLE;
+ else
+ val &= ~BACKLIGHT_ENABLE;
+ I915_WRITE(ICP_PP_CONTROL(1), val);
+ break;
+ default:
+ /* TODO: Add support for remaining GPIOs */
+ DRM_ERROR("Invalid GPIO no from VBT\n");
+ break;
+ }
+}
+
static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
{
struct drm_device *dev = intel_dsi->base.base.dev;
@@ -357,7 +399,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi
*intel_dsi, const u8 *data)
/* pull up/down */
value = *data++ & 1;
- if (IS_VALLEYVIEW(dev_priv))
+ if (IS_ICELAKE(dev_priv))
+ icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
+ else if (IS_VALLEYVIEW(dev_priv))
vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
else if (IS_CHERRYVIEW(dev_priv))
chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
--
2.11.0
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[Intel-gfx] [PATCH v8 37/38] drm/i915/icl: Consider DSI for getting transcoder state
From: Madhav Chauhan
For Gen11 DSI, we use similar registers like for eDP
to find if DSI encoder is connected or not to a pipe.
This patch refactors existing hsw_get_transcoder_state()
to handle this.
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 29 ++---
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 1d46f06ede37..1670646240ba 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9366,6 +9366,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc
*crtc,
struct drm_i915_private *dev_priv = to_i915(dev);
enum intel_display_power_domain power_domain;
u32 tmp;
+ bool is_dsi = false;
+ bool is_edp = false;
/*
* The pipe->transcoder mapping is fixed with the exception of the eDP
@@ -9378,26 +9380,39 @@ static bool hsw_get_transcoder_state(struct intel_crtc
*crtc,
* consistency and less surprising code; it's in always on power).
*/
tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
- if (tmp & TRANS_DDI_FUNC_ENABLE) {
- enum pipe trans_edp_pipe;
+ if (tmp & TRANS_DDI_FUNC_ENABLE)
+ is_edp = true;
+
+ if (IS_ICELAKE(dev_priv)) {
+ tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_DSI_0));
+ if (tmp & TRANS_DDI_FUNC_ENABLE)
+ is_dsi = true;
+ }
+
+ if (is_edp || is_dsi) {
+ enum pipe trans_pipe;
switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
default:
WARN(1, "unknown pipe linked to edp transcoder\n");
/* fall through */
case TRANS_DDI_EDP_INPUT_A_ONOFF:
case TRANS_DDI_EDP_INPUT_A_ON:
- trans_edp_pipe = PIPE_A;
+ trans_pipe = PIPE_A;
break;
case TRANS_DDI_EDP_INPUT_B_ONOFF:
- trans_edp_pipe = PIPE_B;
+ trans_pipe = PIPE_B;
break;
case TRANS_DDI_EDP_INPUT_C_ONOFF:
- trans_edp_pipe = PIPE_C;
+ trans_pipe = PIPE_C;
break;
}
- if (trans_edp_pipe == crtc->pipe)
- pipe_config->cpu_transcoder = TRANSCODER_EDP;
+ if (trans_pipe == crtc->pipe) {
+ if (is_edp)
+ pipe_config->cpu_transcoder = TRANSCODER_EDP;
+ else if (is_dsi)
+ pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
+ }
}
power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
--
2.11.0
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[Intel-gfx] [PATCH v8 30/38] drm/i915/icl: Configure DSI Dual link mode
From: Madhav Chauhan
This patch configures DSI video mode dual link by
programming DSS_CTL registers.
v2: Use new bitfield definitions from Anusha's patch
Correct register to be programmed and use max
depth buffer value (James)
v3 by Jani:
- checkpatch fixes
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 42 +-
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index b2897281d42c..f2609e36dd1d 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -257,6 +257,45 @@ static void dsi_program_swing_and_deemphasis(struct
intel_encoder *encoder)
}
}
+static void configure_dual_link_mode(struct intel_encoder *encoder,
+const struct intel_crtc_state *pipe_config)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ u32 dss_ctl1;
+
+ dss_ctl1 = I915_READ(DSS_CTL1);
+ dss_ctl1 |= SPLITTER_ENABLE;
+ dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
+ dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
+
+ if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
+ const struct drm_display_mode *adjusted_mode =
+ &pipe_config->base.adjusted_mode;
+ u32 dss_ctl2;
+ u16 hactive = adjusted_mode->crtc_hdisplay;
+ u16 dl_buffer_depth;
+
+ dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
+ dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
+
+ if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
+ DRM_ERROR("DL buffer depth exceed max value\n");
+
+ dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
+ dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
+ dss_ctl2 = I915_READ(DSS_CTL2);
+ dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK;
+ dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
+ I915_WRITE(DSS_CTL2, dss_ctl2);
+ } else {
+ /* Interleave */
+ dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
+ }
+
+ I915_WRITE(DSS_CTL1, dss_ctl1);
+}
+
static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -591,7 +630,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder
*encoder,
I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
}
- //TODO: configure DSS_CTL1
+ /* configure stream splitting */
+ configure_dual_link_mode(encoder, pipe_config);
}
for_each_dsi_port(port, intel_dsi->ports) {
--
2.11.0
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[Intel-gfx] [PATCH v8 38/38] drm/i915/icl: Get pipe timings for DSI
From: Madhav Chauhan
Transcoder timings for Gen11 DSI encoder
is available at pipe level unlike in older platform
where port specific registers need to be accessed.
v2 by Jani:
- get timings for (!dsi || icl) instead of (dsi && icl).
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 1670646240ba..126aa79b8746 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9547,7 +9547,8 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
if (!active)
goto out;
- if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
+ if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
+ IS_ICELAKE(dev_priv)) {
haswell_get_ddi_port_state(crtc, pipe_config);
intel_get_pipe_timings(crtc, pipe_config);
}
--
2.11.0
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[Intel-gfx] [PATCH v8 35/38] HACK: drm/i915/icl: Configure backlight functions for DSI
From: Madhav Chauhan Gen11 DSI doesn't use DCS commands based functionality for enabling/disabling backlight but uses PWM based functions similar to eDP. Note by Jani: This should be decided by VBT, not hard coded. DCS brightness control is still a thing. Signed-off-by: Madhav Chauhan Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_panel.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index ad88008f8dd0..60ccae68b27a 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -1835,7 +1835,8 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel) intel_dp_aux_init_backlight_funcs(connector) == 0) return; - if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI && + if (IS_GEN9_LP(dev_priv) && + connector->base.connector_type == DRM_MODE_CONNECTOR_DSI && intel_dsi_dcs_init_backlight_funcs(connector) == 0) return; -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 32/38] drm/i915/icl: Define missing bitfield for shortplug reg
From: Madhav Chauhan
This patch define missing bitfield for shortplug ctl ddi
register which will be used for ICL DSI GPIO programming.
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5f51a258d87b..8380fab06b97 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7693,6 +7693,7 @@ enum {
#define ICP_DDIB_HPD_LONG_DETECT (2 << 4)
#define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4)
#define ICP_DDIA_HPD_ENABLE (1 << 3)
+#define ICP_DDIA_HPD_OP_DRIVE_1 (1 << 2)
#define ICP_DDIA_HPD_STATUS_MASK (3 << 0)
#define ICP_DDIA_HPD_NO_DETECT (0 << 0)
#define ICP_DDIA_HPD_SHORT_DETECT(1 << 0)
--
2.11.0
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[Intel-gfx] [PATCH v8 36/38] drm/i915/icl: Don't wait for empty FIFO
From: Madhav Chauhan
For Gen11 DSI, we don't need to wait for getting
DSI FIFO empty after sending DCS commands.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_vbt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 04423248bbd7..e6686dbdf462 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -123,6 +123,7 @@ static inline enum port intel_dsi_seq_port_to_port(u8 port)
static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
const u8 *data)
{
+ struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
struct mipi_dsi_device *dsi_device;
u8 type, flags, seq_port;
u16 len;
@@ -193,7 +194,8 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi
*intel_dsi,
break;
}
- vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
+ if (!IS_ICELAKE(dev_priv))
+ vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
out:
data += len;
--
2.11.0
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[Intel-gfx] [PATCH v8 33/38] drm/i915/icl: Define display GPIO pins for DSI
From: Madhav Chauhan
Display Pins are the only GPIOs that need to be used by
driver for DSI panels. So driver should now have its own
implementation to toggle these pins based on GPIO info
received from VBT sequences.
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_vbt.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 80bd56e96143..8177305b9c87 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -103,6 +103,18 @@ static struct gpio_map vlv_gpio_table[] = {
#define CHV_GPIO_PAD_CFG1(f, i)(0x4400 + (f) * 0x400 + (i) * 8
+ 4)
#define CHV_GPIO_CFGLOCK (1 << 31)
+/* ICL DSI Display GPIO Pins */
+#define ICL_GPIO_DDSP_HPD_A 0
+#define ICL_GPIO_L_VDDEN_11
+#define ICL_GPIO_L_BKLTEN_1 2
+#define ICL_GPIO_DDPA_CTRLCLK_1 3
+#define ICL_GPIO_DDPA_CTRLDATA_1 4
+#define ICL_GPIO_DDSP_HPD_B 5
+#define ICL_GPIO_L_VDDEN_26
+#define ICL_GPIO_L_BKLTEN_2 7
+#define ICL_GPIO_DDPA_CTRLCLK_2 8
+#define ICL_GPIO_DDPA_CTRLDATA_2 9
+
static inline enum port intel_dsi_seq_port_to_port(u8 port)
{
return port ? PORT_C : PORT_A;
--
2.11.0
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: dsi enabling (rev3)
== Series Details ==
Series: drm/i915/icl: dsi enabling (rev3)
URL : https://patchwork.freedesktop.org/series/51011/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b251037fd588 drm/i915/icl: Move dsi host init code to common file
a43a103a8a44 drm/i915/dsi: move connector mode functions to common file
d122a34905d5 drm/i915/icl: Set max return packet size for DSI panel
3c73fd0e759d drm/i915/icl: Power on DSI panel
23539e8ed054 drm/i915/icl: Wait for header/payload credits release
8dd7cb7cd9f4 drm/i915/icl: Turn ON panel backlight
22cfa12e43d3 drm/i915/icl: Turn OFF panel backlight
-:22: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#22: FILE: drivers/gpu/drm/i915/icl_dsi.c:780:
+static void __attribute__((unused)) gen11_dsi_disable(
total: 0 errors, 0 warnings, 1 checks, 15 lines checked
e3b83d15858b drm/i915/icl: Disable DSI transcoders
496f9c431181 drm/i915/icl: Power down DSI panel
f92b349c0578 drm/i915/icl: Put DSI link in ULPS
32ebc3e760a5 drm/i915/icl: Disable DDI function
389528d1498d drm/i915/icl: Disable portsync mode
3dd8ac3bdc51 drm/i915/icl: Disable DSI ports
ffd539172104 drm/i915/icl: Disable DSI IO power
8f96cf43f453 drm/i915/icl: Define DSI timeout registers
71f90c5344a2 drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT
registers
f6c4ae07a154 drm/i915/icl: Find DSI presence for ICL
9447a71cdb6b drm/i915/icl: Allocate DSI encoder/connector
-:110: CHECK:CAMELCASE: Avoid CamelCase:
#110: FILE: drivers/gpu/drm/i915/icl_dsi.c:1027:
+ connector->display_info.subpixel_order = SubPixelHorizontalRGB;
total: 0 errors, 0 warnings, 1 checks, 118 lines checked
95614818e50b drm/i915/icl: Allocate hosts for DSI ports
6f27802c08aa drm/i915/icl: Add DSI packet payload/header registers
b28670b244e0 drm/i915/icl: Fetch DSI pkt to be transferred
e109cc511eb7 drm/i915/icl: Load DSI packet payload to queue
93032ef7347e drm/i915/icl: Add get config functionality for DSI
c90986451421 drm/i915/icl: Get HW state for DSI encoder
b70c25327649 drm/i915/icl: Add DSI connector functions
35cf407b3008 drm/i915/icl: Add DSI connector helper functions
2b52d7d72d09 drm/i915/icl: Add DSI encoder remaining functions
d4823e7ae09f drm/i915/icl: Fill DSI ports info
ac7d3b7155c4 drm/i915/icl: Add DSS_CTL Registers
89a7e3eca6a0 drm/i915/icl: Configure DSI Dual link mode
1c9fdd4762a5 drm/i915/icl: Define Panel power ctrl register
5a3ef42cc519 drm/i915/icl: Define missing bitfield for shortplug reg
67a18f5eec36 drm/i915/icl: Define display GPIO pins for DSI
6670c2df2ab4 drm/i915/icl: Add changes to program DSI panel GPIOs
bbfcade0770f HACK: drm/i915/icl: Configure backlight functions for DSI
ac08a6bf18b1 drm/i915/icl: Don't wait for empty FIFO
3e15da186132 drm/i915/icl: Consider DSI for getting transcoder state
5c1e98162a65 drm/i915/icl: Get pipe timings for DSI
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/icl: dsi enabling (rev3)
== Series Details == Series: drm/i915/icl: dsi enabling (rev3) URL : https://patchwork.freedesktop.org/series/51011/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/icl: Move dsi host init code to common file Okay! Commit: drm/i915/dsi: move connector mode functions to common file Okay! Commit: drm/i915/icl: Set max return packet size for DSI panel Okay! Commit: drm/i915/icl: Power on DSI panel Okay! Commit: drm/i915/icl: Wait for header/payload credits release Okay! Commit: drm/i915/icl: Turn ON panel backlight Okay! Commit: drm/i915/icl: Turn OFF panel backlight Okay! Commit: drm/i915/icl: Disable DSI transcoders Okay! Commit: drm/i915/icl: Power down DSI panel Okay! Commit: drm/i915/icl: Put DSI link in ULPS Okay! Commit: drm/i915/icl: Disable DDI function Okay! Commit: drm/i915/icl: Disable portsync mode Okay! Commit: drm/i915/icl: Disable DSI ports Okay! Commit: drm/i915/icl: Disable DSI IO power Okay! Commit: drm/i915/icl: Define DSI timeout registers Okay! Commit: drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers Okay! Commit: drm/i915/icl: Find DSI presence for ICL Okay! Commit: drm/i915/icl: Allocate DSI encoder/connector Okay! Commit: drm/i915/icl: Allocate hosts for DSI ports Okay! Commit: drm/i915/icl: Add DSI packet payload/header registers Okay! Commit: drm/i915/icl: Fetch DSI pkt to be transferred Okay! Commit: drm/i915/icl: Load DSI packet payload to queue +drivers/gpu/drm/i915/icl_dsi.c:128:33: warning: expression using sizeof(void) Commit: drm/i915/icl: Add get config functionality for DSI Okay! Commit: drm/i915/icl: Get HW state for DSI encoder Okay! Commit: drm/i915/icl: Add DSI connector functions Okay! Commit: drm/i915/icl: Add DSI connector helper functions Okay! Commit: drm/i915/icl: Add DSI encoder remaining functions Okay! Commit: drm/i915/icl: Fill DSI ports info Okay! Commit: drm/i915/icl: Add DSS_CTL Registers Okay! Commit: drm/i915/icl: Configure DSI Dual link mode Okay! Commit: drm/i915/icl: Define Panel power ctrl register Okay! Commit: drm/i915/icl: Define missing bitfield for shortplug reg Okay! Commit: drm/i915/icl: Define display GPIO pins for DSI Okay! Commit: drm/i915/icl: Add changes to program DSI panel GPIOs Okay! Commit: HACK: drm/i915/icl: Configure backlight functions for DSI Okay! Commit: drm/i915/icl: Don't wait for empty FIFO Okay! Commit: drm/i915/icl: Consider DSI for getting transcoder state Okay! Commit: drm/i915/icl: Get pipe timings for DSI Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/icl: dsi enabling (rev3)
== Series Details == Series: drm/i915/icl: dsi enabling (rev3) URL : https://patchwork.freedesktop.org/series/51011/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5054 -> Patchwork_10650 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10650 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10650, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51011/revisions/3/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10650: === IGT changes === Possible regressions igt@kms_flip@basic-flip-vs-wf_vblank: fi-icl-u: PASS -> DMESG-WARN +17 igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-icl-u2: PASS -> DMESG-WARN +17 == Known issues == Here are the changes found in Patchwork_10650 that come from known issues: === IGT changes === Issues hit igt@debugfs_test@read_all_entries: fi-icl-u2: PASS -> DMESG-WARN (fdo#108070) igt@gem_exec_suspend@basic-s3: fi-icl-u2: PASS -> DMESG-WARN (fdo#106612) igt@gem_mmap_gtt@basic-small-copy: fi-glk-dsi: PASS -> INCOMPLETE (fdo#103359, k.org#198133) igt@kms_flip@basic-flip-vs-dpms: fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998) igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: PASS -> DMESG-WARN (fdo#102614) Possible fixes igt@gem_ctx_create@basic-files: fi-icl-u2: DMESG-WARN (fdo#107724) -> PASS igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: FAIL (fdo#103167) -> PASS Warnings igt@drv_selftest@live_contexts: fi-icl-u: DMESG-FAIL (fdo#108569) -> INCOMPLETE (fdo#108535) fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998 fdo#106612 https://bugs.freedesktop.org/show_bug.cgi?id=106612 fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724 fdo#108070 https://bugs.freedesktop.org/show_bug.cgi?id=108070 fdo#108535 https://bugs.freedesktop.org/show_bug.cgi?id=108535 fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (46 -> 44) == Additional (2): fi-skl-iommu fi-pnv-d510 Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_5054 -> Patchwork_10650 CI_DRM_5054: dfa9e5c2b4b958e77c1109477b94c5c8615e25cc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10650: 5c1e98162a65f719a83eb7c087727a94b3b5ab6e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5c1e98162a65 drm/i915/icl: Get pipe timings for DSI 3e15da186132 drm/i915/icl: Consider DSI for getting transcoder state ac08a6bf18b1 drm/i915/icl: Don't wait for empty FIFO bbfcade0770f HACK: drm/i915/icl: Configure backlight functions for DSI 6670c2df2ab4 drm/i915/icl: Add changes to program DSI panel GPIOs 67a18f5eec36 drm/i915/icl: Define display GPIO pins for DSI 5a3ef42cc519 drm/i915/icl: Define missing bitfield for shortplug reg 1c9fdd4762a5 drm/i915/icl: Define Panel power ctrl register 89a7e3eca6a0 drm/i915/icl: Configure DSI Dual link mode ac7d3b7155c4 drm/i915/icl: Add DSS_CTL Registers d4823e7ae09f drm/i915/icl: Fill DSI ports info 2b52d7d72d09 drm/i915/icl: Add DSI encoder remaining functions 35cf407b3008 drm/i915/icl: Add DSI connector helper functions b70c25327649 drm/i915/icl: Add DSI connector functions c90986451421 drm/i915/icl: Get HW state for DSI encoder 93032ef7347e drm/i915/icl: Add get config functionality for DSI e109cc511eb7 drm/i915/icl: Load DSI packet payload to queue b28670b244e0 drm/i915/icl: Fetch DSI pkt to be transferred 6f27802c08aa drm/i915/icl: Add DSI packet payload/header registers 95614818e50b drm/i915/icl: Allocate hosts for DSI ports 9447a71cdb6b drm/i915/icl: Allocate DSI encoder/connector f6c4ae07a154 drm/i915/icl: Find DSI presence for ICL 71f90c5344a2 drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers 8f96cf43f453 drm/i915/icl: Define DSI timeout registers ffd539172104 drm/i915/icl: Disable DSI IO power 3dd8ac3bdc51 drm/i915/icl: Disable DSI ports 389528d1498d drm/i915/icl: Disable portsync mode 32ebc3e760a5 drm/i915/icl: Disable DDI function f92b349c0578 drm/i915/icl: Put DSI link in ULPS 496f9c431181 drm/i915/icl: Power down DSI panel e3b83d15858
Re: [Intel-gfx] [PATCH v8 00/38] drm/i915/icl: dsi enabling
On Tue, 30 Oct 2018, Jani Nikula wrote: > Jani Nikula (3): > drm/i915/icl: Allocate DSI encoder/connector > drm/i915/icl: Allocate hosts for DSI ports > drm/i915/icl: Load DSI packet payload to queue These are by Madhav, I accidentally took authorship while rebasing. Fixed locally. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftest: fix 64K alignment in igt_write_huge
Hi Matthew,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.19 next-20181030]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Matthew-Auld/drm-i915-selftest-fix-64K-alignment-in-igt_write_huge/20181030-034107
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-allyesconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All warnings (new ones prefixed by >>):
In file included from drivers/gpu/drm/i915/i915_gem.c:6238:0:
drivers/gpu/drm/i915/selftests/huge_pages.c: In function 'igt_write_huge':
>> drivers/gpu/drm/i915/selftests/huge_pages.c:1132:72: warning: comparison of
>> distinct pointer types lacks a cast
alignment = max(alignment, I915_GTT_PAGE_SIZE_2M);
^
vim +1132 drivers/gpu/drm/i915/selftests/huge_pages.c
1106
1107 static int igt_write_huge(struct i915_gem_context *ctx,
1108struct drm_i915_gem_object *obj)
1109 {
1110 struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct i915_address_space *vm =
1112 ctx->ppgtt ? &ctx->ppgtt->vm : &i915->ggtt.vm;
1113 static struct intel_engine_cs *engines[I915_NUM_ENGINES];
1114 struct intel_engine_cs *engine;
1115 I915_RND_STATE(prng);
1116 IGT_TIMEOUT(end_time);
1117 unsigned int id;
1118 u64 alignment;
1119 u64 max;
1120 u64 num;
1121 u64 size;
1122 int *order;
1123 int i, n;
1124 int err = 0;
1125
1126 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
1127
1128 size = obj->base.size;
1129 alignment = rounddown_pow_of_two(obj->mm.page_sizes.sg);
1130 if (obj->mm.page_sizes.sg & I915_GTT_PAGE_SIZE_64K) {
1131 size = round_up(size, I915_GTT_PAGE_SIZE_2M);
> 1132 alignment = max(alignment, I915_GTT_PAGE_SIZE_2M);
1133 }
1134
1135 max = div_u64((vm->total - size), alignment);
1136
1137 n = 0;
1138 for_each_engine(engine, i915, id) {
1139 if (!intel_engine_can_store_dword(engine)) {
1140 pr_info("store-dword-imm not supported on
engine=%u\n",
1141 id);
1142 continue;
1143 }
1144 engines[n++] = engine;
1145 }
1146
1147 if (!n)
1148 return 0;
1149
1150 /*
1151 * To keep things interesting when alternating between engines
in our
1152 * randomized order, lets also make feeding to the same engine
a few
1153 * times in succession a possibility by enlarging the
permutation array.
1154 */
1155 order = i915_random_order(n * I915_NUM_ENGINES, &prng);
1156 if (!order)
1157 return -ENOMEM;
1158
1159 /*
1160 * Try various offsets in an ascending/descending fashion until
we
1161 * timeout -- we want to avoid issues hidden by effectively
always using
1162 * offset = 0.
1163 */
1164 i = 0;
1165 for_each_prime_number_from(num, 0, max) {
1166 u64 offset_low = num * alignment;
1167 u64 offset_high = (max - num) * alignment;
1168 u32 dword = offset_in_page(num) / 4;
1169
1170 engine = engines[order[i] % n];
1171 i = (i + 1) % (n * I915_NUM_ENGINES);
1172
1173 err = __igt_write_huge(ctx, engine, obj, size,
offset_low,
1174 dword, num + 1);
1175 if (err)
1176 break;
1177
1178 err = __igt_write_huge(ctx, engine, obj, size,
offset_high,
1179 dword, num + 1);
1180 if (err)
1181 break;
1182
1183 if (igt_timeout(end_time,
1184 "%s timed out on engine=%u,
offset_low=%llx offset_high=%llx, max_page_size=%lx\n",
1185 __func__, engine->id, offset_low,
offset_high,
1186
rounddown_pow_of_two(obj->mm.page_sizes.sg)))
1187 break;
1188 }
1189
1190
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gtt: Revert "Disable read-only support under GVT"
== Series Details == Series: drm/i915/gtt: Revert "Disable read-only support under GVT" URL : https://patchwork.freedesktop.org/series/51730/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5053_full -> Patchwork_10644_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10644_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10644_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10644_full: === IGT changes === Warnings igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu: shard-snb: SKIP -> PASS +1 == Known issues == Here are the changes found in Patchwork_10644_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_reloc@basic-cpu-gtt: shard-apl: PASS -> DMESG-WARN (fdo#103558, fdo#105602) igt@gem_exec_schedule@pi-ringfull-bsd: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@gem_workarounds@suspend-resume-context: shard-skl: PASS -> INCOMPLETE (fdo#104108, fdo#107773) igt@kms_available_modes_crc@available_mode_test_crc: shard-apl: PASS -> FAIL (fdo#106641) igt@kms_busy@extended-modeset-hang-newfb-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: shard-kbl: PASS -> DMESG-WARN (fdo#107956) igt@kms_color@pipe-a-legacy-gamma: shard-apl: PASS -> FAIL (fdo#108145, fdo#104782) igt@kms_cursor_crc@cursor-256x256-random: shard-apl: PASS -> FAIL (fdo#103232) +4 igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: shard-glk: PASS -> DMESG-WARN (fdo#105763, fdo#106538) igt@kms_flip@flip-vs-expired-vblank: shard-skl: PASS -> FAIL (fdo#105363) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: shard-apl: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc: shard-glk: PASS -> INCOMPLETE (k.org#198133, fdo#103359) igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff: shard-glk: PASS -> FAIL (fdo#103167) +5 igt@kms_frontbuffer_tracking@psr-suspend: shard-skl: PASS -> INCOMPLETE (fdo#104108, fdo#106978, fdo#107773) igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: shard-skl: NOTRUN -> FAIL (fdo#108145) igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-apl: PASS -> FAIL (fdo#103166) +3 igt@kms_plane_multiple@atomic-pipe-c-tiling-x: shard-glk: PASS -> FAIL (fdo#103166) igt@kms_vblank@pipe-c-wait-busy: shard-apl: NOTRUN -> DMESG-WARN (fdo#103558, fdo#105602) +1 Possible fixes igt@gem_exec_whisper@normal: shard-skl: TIMEOUT (fdo#108592) -> PASS igt@gem_tiled_blits@interruptible: shard-apl: INCOMPLETE (fdo#103927) -> PASS igt@kms_color@pipe-c-degamma: shard-apl: FAIL (fdo#104782) -> PASS igt@kms_cursor_crc@cursor-128x42-offscreen: shard-skl: FAIL (fdo#103232) -> PASS igt@kms_cursor_crc@cursor-256x85-random: shard-apl: FAIL (fdo#103232) -> PASS +4 igt@kms_flip_tiling@flip-to-x-tiled: shard-skl: FAIL (fdo#108134) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt: shard-skl: FAIL (fdo#105682) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-apl: FAIL (fdo#103167) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-rte: shard-apl: FAIL (fdo#103167, fdo#105682) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt: shard-skl: FAIL (fdo#103167) -> PASS +1 igt@kms_plane_multiple@atomic-pipe-a-tiling-yf: shard-apl: FAIL (fdo#103166) -> PASS fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782 fdo#105363 https://
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] igt/gem_tiled_fence_blits: Remember to mark up fence blits
On Mon, Oct 29, 2018 at 08:49:58PM +, Chris Wilson wrote:
> Older platforms require fence registers to perform blits, and so
> userspace is expected to mark up the objects to request fences be
> assigned.
>
> Fixes: ff2db94acb53 ("igt/gem_tiled_fence_blits: Remove libdrm_intel
> dependence")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108591
> Signed-off-by: Chris Wilson
> ---
> tests/i915/gem_tiled_fence_blits.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/tests/i915/gem_tiled_fence_blits.c
> b/tests/i915/gem_tiled_fence_blits.c
> index 7560fa52..e40a7b43 100644
> --- a/tests/i915/gem_tiled_fence_blits.c
> +++ b/tests/i915/gem_tiled_fence_blits.c
> @@ -141,6 +141,8 @@ static void run_test(int fd, int count)
>
> memset(reloc, 0, sizeof(reloc));
> memset(obj, 0, sizeof(obj));
> + obj[0].flags = EXEC_OBJECT_NEEDS_FENCE;
> + obj[1].flags = EXEC_OBJECT_NEEDS_FENCE;
No harm in always asking for the fence I suppose.
Reviewed-by: Ville Syrjälä
> obj[2].handle = create_batch(fd, reloc);
> obj[2].relocs_ptr = to_user_pointer(reloc);
> obj[2].relocation_count = ARRAY_SIZE(reloc);
> --
> 2.19.1
>
> ___
> igt-dev mailing list
> igt-...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/fia: FIA registers offset implementation.
On Mon, 29 Oct 2018, Anusha Srivatsa wrote:
> The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
> from the base - which is the FLexi IO Adaptor. Lets follow the
> offset calculation while accessing these registers.
Why?
If I search the specs or i915_reg.h for, say, 0x1638c0 I'll find what
I'm looking for.
We generally don't follow this type of definitions for registers. We may
have some, but those are exceptions.
Please don't do this without some pretty good rationale written in the
commit message.
BR,
Jani.
>
> v2:
> - Follow spec for numbering - s/0/1(Lucas)
> - s/FIA_1/FIA1_BASE (Anusha)
>
> Cc: Lucas De Marchi
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/i915_reg.h | 15 +++
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bcee91bcfba6..dd74bc01c64e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2057,8 +2057,15 @@ enum i915_power_well_id {
> #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy),
> _PORT_CL2CM_DW6_BC)
> #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
>
> +/* FIA Offsets */
> +#define FIA1_BASE0x163000
> +#define PORT_TX_DFLEXDPMLE1_OFFSET 0x008C0
> +#define PORT_TX_DFLEXDPPMS_OFFSET0x00890
> +#define PORT_TX_DFLEXDPCSSS_OFFSET 0x00894
> +#define PORT_TX_DFLEXDPSP_OFFSET 0x008A0
> +
> /* ICL PHY DFLEX registers */
> -#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
> +#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE +
> PORT_TX_DFLEXDPMLE1_OFFSET)
> #define DFLEXDPMLE1_DPMLETC_MASK(n)(0xf << (4 * (n)))
> #define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
>
> @@ -10988,17 +10995,17 @@ enum skl_power_gate {
>
> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
>
> _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
>
> -#define PORT_TX_DFLEXDPSP_MMIO(0x1638A0)
> +#define PORT_TX_DFLEXDPSP_MMIO(FIA1_BASE +
> PORT_TX_DFLEXDPSP_OFFSET)
> #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
> #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
> #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
> #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
> #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
>
> -#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
> +#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE +
> PORT_TX_DFLEXDPPMS_OFFSET)
> #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))
>
> -#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
> +#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE +
> PORT_TX_DFLEXDPCSSS_OFFSET)
> #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
>
> #endif /* _I915_REG_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH v8 34/38] drm/i915/icl: Add changes to program DSI panel GPIOs
On Tue, Oct 30, 2018 at 01:56:40PM +0200, Jani Nikula wrote:
> From: Madhav Chauhan
>
> For ICELAKE DSI, Display Pins are the only GPIOs
> that need to be programmed. So DSI driver should have
> its own implementation to toggle these pins based on
> GPIO info coming from VBT sequences instead of using
> platform specific GPIO driver.
>
> Signed-off-by: Madhav Chauhan
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_dsi_vbt.c | 46
> +++-
> 1 file changed, 45 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index 8177305b9c87..04423248bbd7 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -334,6 +334,48 @@ static void bxt_exec_gpio(struct drm_i915_private
> *dev_priv,
> gpiod_set_value(gpio_desc, value);
> }
>
> +static void icl_exec_gpio(struct drm_i915_private *dev_priv,
> + u8 gpio_source, u8 gpio_index, bool value)
> +{
> + u32 val;
> +
> + switch (gpio_index) {
> + case ICL_GPIO_DDSP_HPD_A:
> + val = I915_READ(SHOTPLUG_CTL_DDI);
> + val &= ~ICP_DDIA_HPD_ENABLE;
> + I915_WRITE(SHOTPLUG_CTL_DDI, val);
> + val = I915_READ(SHOTPLUG_CTL_DDI);
> + if (value)
> + val |= ICP_DDIA_HPD_OP_DRIVE_1;
> + else
> + val &= ~ICP_DDIA_HPD_OP_DRIVE_1;
> +
> + I915_WRITE(SHOTPLUG_CTL_DDI, val);
How badly is this thing going to race with the hotplug irq handler?
> + break;
> + case ICL_GPIO_L_VDDEN_1:
> + val = I915_READ(ICP_PP_CONTROL(1));
> + if (value)
> + val |= PWR_STATE_TARGET;
> + else
> + val &= ~PWR_STATE_TARGET;
> + I915_WRITE(ICP_PP_CONTROL(1), val);
> + break;
> + case ICL_GPIO_L_BKLTEN_1:
> + val = I915_READ(ICP_PP_CONTROL(1));
> + if (value)
> + val |= BACKLIGHT_ENABLE;
> + else
> + val &= ~BACKLIGHT_ENABLE;
> + I915_WRITE(ICP_PP_CONTROL(1), val);
:( What a horror show. So basically we're trying to pretend the power
sequencer state machine doesn't even exist. Is there some bit somewhere
we can actually use to disable the state machine? If not I think this
thing needs much more care.
> + break;
> + default:
> + /* TODO: Add support for remaining GPIOs */
> + DRM_ERROR("Invalid GPIO no from VBT\n");
> + break;
> + }
> +}
> +
> static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> {
> struct drm_device *dev = intel_dsi->base.base.dev;
> @@ -357,7 +399,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi
> *intel_dsi, const u8 *data)
> /* pull up/down */
> value = *data++ & 1;
>
> - if (IS_VALLEYVIEW(dev_priv))
> + if (IS_ICELAKE(dev_priv))
> + icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
> + else if (IS_VALLEYVIEW(dev_priv))
> vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
> else if (IS_CHERRYVIEW(dev_priv))
> chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
> --
> 2.11.0
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v8 37/38] drm/i915/icl: Consider DSI for getting transcoder state
On Tue, Oct 30, 2018 at 01:56:43PM +0200, Jani Nikula wrote:
> From: Madhav Chauhan
>
> For Gen11 DSI, we use similar registers like for eDP
> to find if DSI encoder is connected or not to a pipe.
> This patch refactors existing hsw_get_transcoder_state()
> to handle this.
>
> Signed-off-by: Madhav Chauhan
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_display.c | 29 ++---
> 1 file changed, 22 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 1d46f06ede37..1670646240ba 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9366,6 +9366,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc
> *crtc,
> struct drm_i915_private *dev_priv = to_i915(dev);
> enum intel_display_power_domain power_domain;
> u32 tmp;
> + bool is_dsi = false;
> + bool is_edp = false;
>
> /*
>* The pipe->transcoder mapping is fixed with the exception of the eDP
> @@ -9378,26 +9380,39 @@ static bool hsw_get_transcoder_state(struct
> intel_crtc *crtc,
>* consistency and less surprising code; it's in always on power).
>*/
> tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
> - if (tmp & TRANS_DDI_FUNC_ENABLE) {
> - enum pipe trans_edp_pipe;
> + if (tmp & TRANS_DDI_FUNC_ENABLE)
> + is_edp = true;
> +
> + if (IS_ICELAKE(dev_priv)) {
> + tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_DSI_0));
> + if (tmp & TRANS_DDI_FUNC_ENABLE)
> + is_dsi = true;
> + }
> +
WARN_ON(is_edp && is_dsi) ?
> + if (is_edp || is_dsi) {
> + enum pipe trans_pipe;
> switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
> default:
> WARN(1, "unknown pipe linked to edp transcoder\n");
> /* fall through */
> case TRANS_DDI_EDP_INPUT_A_ONOFF:
> case TRANS_DDI_EDP_INPUT_A_ON:
> - trans_edp_pipe = PIPE_A;
> + trans_pipe = PIPE_A;
> break;
> case TRANS_DDI_EDP_INPUT_B_ONOFF:
> - trans_edp_pipe = PIPE_B;
> + trans_pipe = PIPE_B;
> break;
> case TRANS_DDI_EDP_INPUT_C_ONOFF:
> - trans_edp_pipe = PIPE_C;
> + trans_pipe = PIPE_C;
> break;
> }
>
> - if (trans_edp_pipe == crtc->pipe)
> - pipe_config->cpu_transcoder = TRANSCODER_EDP;
> + if (trans_pipe == crtc->pipe) {
> + if (is_edp)
> + pipe_config->cpu_transcoder = TRANSCODER_EDP;
> + else if (is_dsi)
> + pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
> + }
> }
>
> power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
> --
> 2.11.0
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v8 34/38] drm/i915/icl: Add changes to program DSI panel GPIOs
On Tue, 30 Oct 2018, Ville Syrjälä wrote:
> On Tue, Oct 30, 2018 at 01:56:40PM +0200, Jani Nikula wrote:
>> From: Madhav Chauhan
>>
>> For ICELAKE DSI, Display Pins are the only GPIOs
>> that need to be programmed. So DSI driver should have
>> its own implementation to toggle these pins based on
>> GPIO info coming from VBT sequences instead of using
>> platform specific GPIO driver.
>>
>> Signed-off-by: Madhav Chauhan
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/intel_dsi_vbt.c | 46
>> +++-
>> 1 file changed, 45 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> index 8177305b9c87..04423248bbd7 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> @@ -334,6 +334,48 @@ static void bxt_exec_gpio(struct drm_i915_private
>> *dev_priv,
>> gpiod_set_value(gpio_desc, value);
>> }
>>
>> +static void icl_exec_gpio(struct drm_i915_private *dev_priv,
>> + u8 gpio_source, u8 gpio_index, bool value)
>> +{
>> +u32 val;
>> +
>> +switch (gpio_index) {
>> +case ICL_GPIO_DDSP_HPD_A:
>> +val = I915_READ(SHOTPLUG_CTL_DDI);
>> +val &= ~ICP_DDIA_HPD_ENABLE;
>> +I915_WRITE(SHOTPLUG_CTL_DDI, val);
>> +val = I915_READ(SHOTPLUG_CTL_DDI);
>> +if (value)
>> +val |= ICP_DDIA_HPD_OP_DRIVE_1;
>> +else
>> +val &= ~ICP_DDIA_HPD_OP_DRIVE_1;
>> +
>> +I915_WRITE(SHOTPLUG_CTL_DDI, val);
>
> How badly is this thing going to race with the hotplug irq handler?
>
>> +break;
>> +case ICL_GPIO_L_VDDEN_1:
>> +val = I915_READ(ICP_PP_CONTROL(1));
>> +if (value)
>> +val |= PWR_STATE_TARGET;
>> +else
>> +val &= ~PWR_STATE_TARGET;
>> +I915_WRITE(ICP_PP_CONTROL(1), val);
>> +break;
>> +case ICL_GPIO_L_BKLTEN_1:
>> +val = I915_READ(ICP_PP_CONTROL(1));
>> +if (value)
>> +val |= BACKLIGHT_ENABLE;
>> +else
>> +val &= ~BACKLIGHT_ENABLE;
>> +I915_WRITE(ICP_PP_CONTROL(1), val);
>
> :( What a horror show. So basically we're trying to pretend the power
> sequencer state machine doesn't even exist. Is there some bit somewhere
> we can actually use to disable the state machine? If not I think this
> thing needs much more care.
Frankly I didn't look at the patches towards the end of the series all
that much. Just included them all for completeness.
Agreed, looks pretty bad. :(
BR,
Jani.
>
>> +break;
>> +default:
>> +/* TODO: Add support for remaining GPIOs */
>> +DRM_ERROR("Invalid GPIO no from VBT\n");
>> +break;
>> +}
>> +}
>> +
>> static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>> {
>> struct drm_device *dev = intel_dsi->base.base.dev;
>> @@ -357,7 +399,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi
>> *intel_dsi, const u8 *data)
>> /* pull up/down */
>> value = *data++ & 1;
>>
>> -if (IS_VALLEYVIEW(dev_priv))
>> +if (IS_ICELAKE(dev_priv))
>> +icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
>> +else if (IS_VALLEYVIEW(dev_priv))
>> vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
>> else if (IS_CHERRYVIEW(dev_priv))
>> chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
>> --
>> 2.11.0
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH v4 1/2] drm: Add drm_any_plane_has_format()
On Tue, Oct 30, 2018 at 10:35:07AM +0100, Daniel Vetter wrote: > On Mon, Oct 29, 2018 at 04:00:04PM -0700, Eric Anholt wrote: > > Ville Syrjala writes: > > > > > From: Ville Syrjälä > > > > > > Add a function to check whether there is at least one plane that > > > supports a specific format and modifier combination. Drivers can > > > use this to reject unsupported formats/modifiers in .fb_create(). > > > > > > v2: Accept anyformat if the driver doesn't do planes (Eric) > > > s/planes_have_format/any_plane_has_format/ (Eric) > > > Check the modifier as well since we already have a function > > > that does both > > > v3: Don't do the check in the core since we may not know the > > > modifier yet, instead export the function and let drivers > > > call it themselves > > > > > > Cc: Eric Anholt > > > Cc: Dhinakaran Pandiyan > > > Signed-off-by: Ville Syrjälä > > > Reviewed-by: Dhinakaran Pandiyan > > > > I don't particularly see the point in having FB creation duplicate the > > validation that atomic check will eventually do, and it means that FB > > creation cost scales with plane count, but if i915's going to do this, > > it seems reasonable for them. > > atomic_check checks for a given plane only, I do think it makes sense to > make sure you can't create framebuffers that are impossible to use on a > given driver at addfb time. > > In case the overhead is ever critical, we could compile a static map of > this at driver load time, and then check that. > > Aside: Shouldn't we make this the default for atomic drivers? With > atomic drivers we can assume that all planes have valid format lists > (because atomic_check checks them already). Only with non-atomic drivers, > how might have a faked primary plane is this not a valid assumption ... The problem of making this automagic for everyone was the legacy tiling->modifier thing. https://patchwork.freedesktop.org/patch/210193/ + https://patchwork.freedesktop.org/patch/208070/ is the best I could really come up with when I tried to make this entirely automagic. I haven't bothered to revisit those because I wasn't entirely happy with needing the extra vfunc, and people didn't seem too excited about this idea. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/fia: FIA registers offset implementation.
On Tue, Oct 30, 2018 at 6:56 AM Jani Nikula wrote:
>
> On Mon, 29 Oct 2018, Anusha Srivatsa wrote:
> > The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
> > from the base - which is the FLexi IO Adaptor. Lets follow the
> > offset calculation while accessing these registers.
>
> Why?
>
> If I search the specs or i915_reg.h for, say, 0x1638c0 I'll find what
> I'm looking for.
>
> We generally don't follow this type of definitions for registers. We may
> have some, but those are exceptions.
Because spec 29550 treats those registers as a base + offset to be more
future proof regarding a change of the base. And yes, I think something
like that needs to be stated in the commit message. Is this enough?
Lucas De Marchi
>
> Please don't do this without some pretty good rationale written in the
> commit message.
>
> BR,
> Jani.
>
> >
> > v2:
> > - Follow spec for numbering - s/0/1(Lucas)
> > - s/FIA_1/FIA1_BASE (Anusha)
> >
> > Cc: Lucas De Marchi
> > Signed-off-by: Anusha Srivatsa
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 15 +++
> > 1 file changed, 11 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index bcee91bcfba6..dd74bc01c64e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -2057,8 +2057,15 @@ enum i915_power_well_id {
> > #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy),
> > _PORT_CL2CM_DW6_BC)
> > #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
> >
> > +/* FIA Offsets */
> > +#define FIA1_BASE0x163000
> > +#define PORT_TX_DFLEXDPMLE1_OFFSET 0x008C0
> > +#define PORT_TX_DFLEXDPPMS_OFFSET0x00890
> > +#define PORT_TX_DFLEXDPCSSS_OFFSET 0x00894
> > +#define PORT_TX_DFLEXDPSP_OFFSET 0x008A0
> > +
> > /* ICL PHY DFLEX registers */
> > -#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
> > +#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE +
> > PORT_TX_DFLEXDPMLE1_OFFSET)
> > #define DFLEXDPMLE1_DPMLETC_MASK(n)(0xf << (4 * (n)))
> > #define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
> >
> > @@ -10988,17 +10995,17 @@ enum skl_power_gate {
> >
> > _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
> >
> > _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
> >
> > -#define PORT_TX_DFLEXDPSP_MMIO(0x1638A0)
> > +#define PORT_TX_DFLEXDPSP_MMIO(FIA1_BASE +
> > PORT_TX_DFLEXDPSP_OFFSET)
> > #define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))
> > #define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))
> > #define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)
> > #define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))
> > #define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))
> >
> > -#define PORT_TX_DFLEXDPPMS _MMIO(0x163890)
> > +#define PORT_TX_DFLEXDPPMS _MMIO(FIA1_BASE +
> > PORT_TX_DFLEXDPPMS_OFFSET)
> > #define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 <<
> > (tc_port))
> >
> > -#define PORT_TX_DFLEXDPCSSS _MMIO(0x163894)
> > +#define PORT_TX_DFLEXDPCSSS _MMIO(FIA1_BASE +
> > PORT_TX_DFLEXDPCSSS_OFFSET)
> > #define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 <<
> > (tc_port))
> >
> > #endif /* _I915_REG_H_ */
>
> --
> Jani Nikula, Intel Open Source Graphics Center
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--
Lucas De Marchi
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Re: [Intel-gfx] [PATCH v4 1/2] drm: Add drm_any_plane_has_format()
On Tue, Oct 30, 2018 at 04:18:28PM +0200, Ville Syrjälä wrote: > On Tue, Oct 30, 2018 at 10:35:07AM +0100, Daniel Vetter wrote: > > On Mon, Oct 29, 2018 at 04:00:04PM -0700, Eric Anholt wrote: > > > Ville Syrjala writes: > > > > > > > From: Ville Syrjälä > > > > > > > > Add a function to check whether there is at least one plane that > > > > supports a specific format and modifier combination. Drivers can > > > > use this to reject unsupported formats/modifiers in .fb_create(). > > > > > > > > v2: Accept anyformat if the driver doesn't do planes (Eric) > > > > s/planes_have_format/any_plane_has_format/ (Eric) > > > > Check the modifier as well since we already have a function > > > > that does both > > > > v3: Don't do the check in the core since we may not know the > > > > modifier yet, instead export the function and let drivers > > > > call it themselves > > > > > > > > Cc: Eric Anholt > > > > Cc: Dhinakaran Pandiyan > > > > Signed-off-by: Ville Syrjälä > > > > Reviewed-by: Dhinakaran Pandiyan > > > > > > I don't particularly see the point in having FB creation duplicate the > > > validation that atomic check will eventually do, and it means that FB > > > creation cost scales with plane count, but if i915's going to do this, > > > it seems reasonable for them. > > > > atomic_check checks for a given plane only, I do think it makes sense to > > make sure you can't create framebuffers that are impossible to use on a > > given driver at addfb time. > > > > In case the overhead is ever critical, we could compile a static map of > > this at driver load time, and then check that. > > > > Aside: Shouldn't we make this the default for atomic drivers? With > > atomic drivers we can assume that all planes have valid format lists > > (because atomic_check checks them already). Only with non-atomic drivers, > > how might have a faked primary plane is this not a valid assumption ... > > The problem of making this automagic for everyone was the > legacy tiling->modifier thing. > > https://patchwork.freedesktop.org/patch/210193/ + > https://patchwork.freedesktop.org/patch/208070/ > is the best I could really come up with when I tried to make this > entirely automagic. I haven't bothered to revisit those because I > wasn't entirely happy with needing the extra vfunc, and people > didn't seem too excited about this idea. Hm yeah for full format+modifier checking we need a hook. For format-only checking we can get by with requiring atomic only I think. Anyway, kinda orthogonal to all this. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/8] drm/i915: Move aux_ch to intel_digital_port
From ICL onwards all DDI/TypeC ports - even working in HDMI mode - need
to know their corresponding AUX CH, so move the field to a common
struct.
No functional change.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c | 4 +++-
drivers/gpu/drm/i915/intel_dp.c | 35 +++
drivers/gpu/drm/i915/intel_drv.h | 2 +-
3 files changed, 27 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index e40a8c97d34b..32a080265d03 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2084,6 +2084,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
static inline enum intel_display_power_domain
intel_ddi_main_link_aux_domain(struct intel_dp *intel_dp)
{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+
/* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
* DC states enabled at the same time, while for driver initiated AUX
* transfers we need the same AUX IOs to be powered but with DC states
@@ -2096,7 +2098,7 @@ intel_ddi_main_link_aux_domain(struct intel_dp *intel_dp)
* Note that PSR is enabled only on Port A even though this function
* returns the correct domain for other ports too.
*/
- return intel_dp->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
+ return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
intel_dp->aux_power_domain;
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2445897b8f6c..5530c604c694 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1156,6 +1156,7 @@ static uint32_t g4x_get_aux_clock_divider(struct intel_dp
*intel_dp, int index)
static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
if (index)
return 0;
@@ -1165,7 +1166,7 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp, int index)
* like to run at 2MHz. So, take the cdclk or PCH rawclk value and
* divide by 2000 and use that
*/
- if (intel_dp->aux_ch == AUX_CH_A)
+ if (dig_port->aux_ch == AUX_CH_A)
return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
else
return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
@@ -1174,8 +1175,9 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp
*intel_dp, int index)
static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- if (intel_dp->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
+ if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
/* Workaround for non-ULT HSW */
switch (index) {
case 0: return 63;
@@ -1506,7 +1508,9 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct
drm_dp_aux_msg *msg)
static enum intel_display_power_domain
intel_aux_power_domain(struct intel_dp *intel_dp)
{
- switch (intel_dp->aux_ch) {
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+
+ switch (dig_port->aux_ch) {
case AUX_CH_A:
return POWER_DOMAIN_AUX_A;
case AUX_CH_B:
@@ -1520,7 +1524,7 @@ intel_aux_power_domain(struct intel_dp *intel_dp)
case AUX_CH_F:
return POWER_DOMAIN_AUX_F;
default:
- MISSING_CASE(intel_dp->aux_ch);
+ MISSING_CASE(dig_port->aux_ch);
return POWER_DOMAIN_AUX_A;
}
}
@@ -1528,7 +1532,8 @@ intel_aux_power_domain(struct intel_dp *intel_dp)
static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- enum aux_ch aux_ch = intel_dp->aux_ch;
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
switch (aux_ch) {
case AUX_CH_B:
@@ -1544,7 +1549,8 @@ static i915_reg_t g4x_aux_ctl_reg(struct intel_dp
*intel_dp)
static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- enum aux_ch aux_ch = intel_dp->aux_ch;
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
switch (aux_ch) {
case AUX_CH_B:
@@ -1560,7 +1566,8 @@ static i915_reg_t g4x_aux_data_reg(struct intel_dp
*intel_dp, int index)
static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
{
struct drm
[Intel-gfx] [PATCH 0/8] drm/i915/icl: Fix HDMI on TypeC static ports
ICL has repurposed some of the AUX HW signals/flags, so that we have to program these for HDMI too. In practice this means enabling the AUX power well for HDMI mode too. The last patch fixes an issue where BIOS leaves the PLL->port mapping enabled even though the corresponding encoder is disabled. This happens at least on ICL when booting with an HDMI output connected, where the PLL->port mapping will be enabled for eDP, while the eDP encoder is disabled. Cc: Paulo Zanoni Cc: Ville Syrjälä Imre Deak (8): drm/i915: Move intel_aux_ch() to intel_bios.c drm/i915: Move aux_ch to intel_digital_port drm/i915: Init aux_ch for HDMI ports too drm/i915: Use a helper to get the aux power domain drm/i915: Enable AUX power earlier drm/i915: Enable AUX power for HDMI DDI/TypeC main link too drm/i915: Configure AUX_CH_CTL when enabling the AUX power domain drm/i915/icl+: Sanitize port to PLL mapping drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/intel_bios.c | 45 ++ drivers/gpu/drm/i915/intel_ddi.c| 81 + drivers/gpu/drm/i915/intel_display.c| 28 ++ drivers/gpu/drm/i915/intel_dp.c | 148 +++- drivers/gpu/drm/i915/intel_drv.h| 6 +- drivers/gpu/drm/i915/intel_hdmi.c | 1 + drivers/gpu/drm/i915/intel_runtime_pm.c | 69 +-- 8 files changed, 257 insertions(+), 123 deletions(-) -- 2.13.2 *** BLURB HERE *** Imre Deak (8): drm/i915: Move intel_aux_ch() to intel_bios.c drm/i915: Move aux_ch to intel_digital_port drm/i915: Init aux_ch for HDMI ports too drm/i915: Use a helper to get the aux power domain drm/i915: Enable AUX power earlier drm/i915: Enable AUX power for HDMI DDI/TypeC main link too drm/i915: Configure AUX_CH_CTL when enabling the AUX power domain drm/i915/icl+: Sanitize port to PLL mapping drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/intel_bios.c | 45 ++ drivers/gpu/drm/i915/intel_ddi.c| 81 + drivers/gpu/drm/i915/intel_display.c| 28 ++ drivers/gpu/drm/i915/intel_dp.c | 148 +++- drivers/gpu/drm/i915/intel_drv.h| 6 +- drivers/gpu/drm/i915/intel_hdmi.c | 1 + drivers/gpu/drm/i915/intel_runtime_pm.c | 69 +-- 8 files changed, 257 insertions(+), 123 deletions(-) -- 2.13.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/8] drm/i915: Move intel_aux_ch() to intel_bios.c
From ICL onwards all the DDI/TypeC ports - even working in HDMI mode -
need to know their corresponding AUX channel, so move the corresponding
helper to a common place.
No functional change.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_bios.c | 45 +++
drivers/gpu/drm/i915/intel_dp.c | 50 +--
3 files changed, 47 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c9e5bab6861b..c57b701f72a7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3445,6 +3445,7 @@ bool intel_bios_is_port_hpd_inverted(struct
drm_i915_private *dev_priv,
enum port port);
bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
enum port port);
+enum aux_ch intel_aux_ch(struct drm_i915_private *dev_priv, enum port port);
/* intel_acpi.c */
#ifdef CONFIG_ACPI
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 1faa494e2bc9..c7682a470c6a 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -2159,3 +2159,48 @@ intel_bios_is_lspcon_present(struct drm_i915_private
*dev_priv,
return false;
}
+
+enum aux_ch intel_aux_ch(struct drm_i915_private *dev_priv, enum port port)
+{
+ const struct ddi_vbt_port_info *info =
+ &dev_priv->vbt.ddi_port_info[port];
+ enum aux_ch aux_ch;
+
+ if (!info->alternate_aux_channel) {
+ aux_ch = (enum aux_ch) port;
+
+ DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
+ aux_ch_name(aux_ch), port_name(port));
+ return aux_ch;
+ }
+
+ switch (info->alternate_aux_channel) {
+ case DP_AUX_A:
+ aux_ch = AUX_CH_A;
+ break;
+ case DP_AUX_B:
+ aux_ch = AUX_CH_B;
+ break;
+ case DP_AUX_C:
+ aux_ch = AUX_CH_C;
+ break;
+ case DP_AUX_D:
+ aux_ch = AUX_CH_D;
+ break;
+ case DP_AUX_E:
+ aux_ch = AUX_CH_E;
+ break;
+ case DP_AUX_F:
+ aux_ch = AUX_CH_F;
+ break;
+ default:
+ MISSING_CASE(info->alternate_aux_channel);
+ aux_ch = AUX_CH_A;
+ break;
+ }
+
+ DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
+ aux_ch_name(aux_ch), port_name(port));
+
+ return aux_ch;
+}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6b37d66194a3..2445897b8f6c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1503,54 +1503,6 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct
drm_dp_aux_msg *msg)
return ret;
}
-static enum aux_ch intel_aux_ch(struct intel_dp *intel_dp)
-{
- struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum port port = encoder->port;
- const struct ddi_vbt_port_info *info =
- &dev_priv->vbt.ddi_port_info[port];
- enum aux_ch aux_ch;
-
- if (!info->alternate_aux_channel) {
- aux_ch = (enum aux_ch) port;
-
- DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
- aux_ch_name(aux_ch), port_name(port));
- return aux_ch;
- }
-
- switch (info->alternate_aux_channel) {
- case DP_AUX_A:
- aux_ch = AUX_CH_A;
- break;
- case DP_AUX_B:
- aux_ch = AUX_CH_B;
- break;
- case DP_AUX_C:
- aux_ch = AUX_CH_C;
- break;
- case DP_AUX_D:
- aux_ch = AUX_CH_D;
- break;
- case DP_AUX_E:
- aux_ch = AUX_CH_E;
- break;
- case DP_AUX_F:
- aux_ch = AUX_CH_F;
- break;
- default:
- MISSING_CASE(info->alternate_aux_channel);
- aux_ch = AUX_CH_A;
- break;
- }
-
- DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
- aux_ch_name(aux_ch), port_name(port));
-
- return aux_ch;
-}
-
static enum intel_display_power_domain
intel_aux_power_domain(struct intel_dp *intel_dp)
{
@@ -1691,7 +1643,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
- intel_dp->aux_ch = intel_aux_ch(intel_dp);
+ intel_dp->aux_ch = intel_aux_ch(dev_priv, encoder->port);
intel_dp->aux_power_domain = intel_
[Intel-gfx] [PATCH 5/8] drm/i915: Enable AUX power earlier
For DDI/TypeC ports the AUX power domain needs to be enabled before the
port's PLL is enabled, so move the enabling earlier accordingly.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c | 46 +---
drivers/gpu/drm/i915/intel_display.c | 2 ++
2 files changed, 34 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 5bb459011a49..7731ca704862 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2082,10 +2082,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder
*encoder,
}
static inline enum intel_display_power_domain
-intel_ddi_main_link_aux_domain(struct intel_dp *intel_dp)
+intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
{
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-
/* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
* DC states enabled at the same time, while for driver initiated AUX
* transfers we need the same AUX IOs to be powered but with DC states
@@ -2120,11 +2118,8 @@ static u64 intel_ddi_get_power_domains(struct
intel_encoder *encoder,
domains = BIT_ULL(dig_port->ddi_io_power_domain);
/* AUX power is only needed for (e)DP mode, not for HDMI. */
- if (intel_crtc_has_dp_encoder(crtc_state)) {
- struct intel_dp *intel_dp = &dig_port->dp;
-
- domains |= BIT_ULL(intel_ddi_main_link_aux_domain(intel_dp));
- }
+ if (intel_crtc_has_dp_encoder(crtc_state))
+ domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
return domains;
}
@@ -2891,6 +2886,32 @@ static void intel_ddi_clk_disable(struct intel_encoder
*encoder)
}
}
+static void
+intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state,
+const struct drm_connector_state *conn_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+
+ if (intel_crtc_has_dp_encoder(crtc_state))
+ intel_display_power_get(dev_priv,
+
intel_ddi_main_link_aux_domain(dig_port));
+}
+
+static void
+intel_ddi_post_pll_disable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+
+ if (intel_crtc_has_dp_encoder(crtc_state))
+ intel_display_power_put(dev_priv,
+
intel_ddi_main_link_aux_domain(dig_port));
+}
+
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state)
@@ -2904,9 +2925,6 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder
*encoder,
WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
- intel_display_power_get(dev_priv,
- intel_ddi_main_link_aux_domain(intel_dp));
-
intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
crtc_state->lane_count, is_mst);
@@ -3071,9 +3089,6 @@ static void intel_ddi_post_disable_dp(struct
intel_encoder *encoder,
intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
intel_ddi_clk_disable(encoder);
-
- intel_display_power_put(dev_priv,
- intel_ddi_main_link_aux_domain(intel_dp));
}
static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
@@ -3830,6 +3845,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
intel_encoder->enable = intel_enable_ddi;
if (IS_GEN9_LP(dev_priv))
intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
+
+ intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
+ intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
intel_encoder->pre_enable = intel_ddi_pre_enable;
intel_encoder->disable = intel_disable_ddi;
intel_encoder->post_disable = intel_ddi_post_disable;
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 36710a30fb37..12ba2b923e6b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5876,6 +5876,8 @@ static void haswell_crtc_disable(struct intel_crtc_state
*old_crtc_state,
if (INTEL_GEN(dev_priv) >= 11)
icl_unmap_plls_to_ports(crtc, old_crtc_state, old_state);
+
+
[Intel-gfx] [PATCH 6/8] drm/i915: Enable AUX power for HDMI DDI/TypeC main link too
DDI/TypeC ports need the AUX power domain for main link functionality
even when they operate in HDMI static mode, so enable the power domain
for these ports too.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 7731ca704862..bf58816ed59c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2103,6 +2103,7 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port
*dig_port)
static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port;
u64 domains;
@@ -2117,8 +2118,12 @@ static u64 intel_ddi_get_power_domains(struct
intel_encoder *encoder,
dig_port = enc_to_dig_port(&encoder->base);
domains = BIT_ULL(dig_port->ddi_io_power_domain);
- /* AUX power is only needed for (e)DP mode, not for HDMI. */
- if (intel_crtc_has_dp_encoder(crtc_state))
+ /*
+* AUX power is only needed for (e)DP mode, and for HDMI mode on TC
+* ports.
+*/
+ if (intel_crtc_has_dp_encoder(crtc_state) ||
+ intel_port_is_tc(dev_priv, encoder->port))
domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
return domains;
@@ -2894,7 +2899,8 @@ intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
- if (intel_crtc_has_dp_encoder(crtc_state))
+ if (intel_crtc_has_dp_encoder(crtc_state) ||
+ intel_port_is_tc(dev_priv, encoder->port))
intel_display_power_get(dev_priv,
intel_ddi_main_link_aux_domain(dig_port));
}
@@ -2907,7 +2913,8 @@ intel_ddi_post_pll_disable(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
- if (intel_crtc_has_dp_encoder(crtc_state))
+ if (intel_crtc_has_dp_encoder(crtc_state) ||
+ intel_port_is_tc(dev_priv, encoder->port))
intel_display_power_put(dev_priv,
intel_ddi_main_link_aux_domain(dig_port));
}
--
2.13.2
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 8/8] drm/i915/icl+: Sanitize port to PLL mapping
BIOS can leave the PLL to port mapping enabled, even if the
corresponding encoder is disabled. Disable the port mapping in this
case.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c | 23 +++
drivers/gpu/drm/i915/intel_display.c | 4
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index bf58816ed59c..8b7289af7558 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2822,6 +2822,29 @@ void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
}
}
+void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ u32 val = I915_READ(DPCLKA_CFGCR0_ICL);
+ enum port port = encoder->port;
+ bool clk_enabled = !(val & icl_dpclka_cfgcr0_clk_off(dev_priv, port));
+
+ if (clk_enabled == !!encoder->base.crtc)
+ return;
+
+ /*
+* Punt on the case now where clock is disabled, but the encoder is
+* enabled, something else is really broken then.
+*/
+ if (WARN_ON(!clk_enabled))
+ return;
+
+ DRM_NOTE("Port %c is disabled but it has a mapped PLL, unmap it\n",
+port_name(port));
+ val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+ I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+}
+
static void intel_ddi_clk_select(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 12ba2b923e6b..2534263ebb41 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15368,6 +15368,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
static void intel_sanitize_encoder(struct intel_encoder *encoder)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_connector *connector;
/* We need to check both for a crtc link (meaning that the
@@ -15409,6 +15410,9 @@ static void intel_sanitize_encoder(struct intel_encoder
*encoder)
/* notify opregion of the sanitized encoder state */
intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
+
+ if (INTEL_GEN(dev_priv) >= 11)
+ icl_sanitize_encoder_pll_mapping(encoder);
}
void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a3d7b93ecddd..224edb1a95d5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1519,6 +1519,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
struct intel_crtc_state *crtc_state,
struct drm_atomic_state *old_state);
+void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
int color_plane, unsigned int height);
--
2.13.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/8] drm/i915: Init aux_ch for HDMI ports too
From ICL onwards DDI/TypeC ports - even in HDMI static mode - need to know
which AUX CH belongs to them, so initialize aux_ch for those ports too.
For consistency do this for all HDMI ports, not only for DDI/TypeC ones.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c | 1 +
drivers/gpu/drm/i915/intel_dp.c | 2 +-
drivers/gpu/drm/i915/intel_hdmi.c | 1 +
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 32a080265d03..3739ef003819 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3852,6 +3852,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
(DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
+ intel_dig_port->aux_ch = intel_aux_ch(dev_priv, port);
switch (port) {
case PORT_A:
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5530c604c694..6645c9faca9a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1654,7 +1654,6 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct intel_encoder *encoder = &dig_port->base;
- dig_port->aux_ch = intel_aux_ch(dev_priv, encoder->port);
intel_dp->aux_power_domain = intel_aux_power_domain(intel_dp);
if (INTEL_GEN(dev_priv) >= 9) {
@@ -6706,6 +6705,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
if (port != PORT_A)
intel_infoframe_init(intel_dig_port);
+ intel_dig_port->aux_ch = intel_aux_ch(dev_priv, port);
if (!intel_dp_init_connector(intel_dig_port, intel_connector))
goto err_init_connector;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 129b880bce64..b50c5497048a 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2506,5 +2506,6 @@ void intel_hdmi_init(struct drm_i915_private *dev_priv,
intel_infoframe_init(intel_dig_port);
+ intel_dig_port->aux_ch = intel_aux_ch(dev_priv, port);
intel_hdmi_init_connector(intel_dig_port, intel_connector);
}
--
2.13.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/8] drm/i915: Use a helper to get the aux power domain
From ICL onwards the AUX power domain may change dynamically based on
whether a DDI/TypeC port is in thunderbolt or non-thunderbolt mode, so
use a helper function instead of a static field to get the current
domain.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 22 +++
drivers/gpu/drm/i915/intel_dp.c | 73 +++-
drivers/gpu/drm/i915/intel_drv.h | 3 +-
4 files changed, 56 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 3739ef003819..5bb459011a49 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2099,7 +2099,7 @@ intel_ddi_main_link_aux_domain(struct intel_dp *intel_dp)
* returns the correct domain for other ports too.
*/
return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
- intel_dp->aux_power_domain;
+ intel_aux_power_domain(dig_port);
}
static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c3cadc09f859..36710a30fb37 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5949,6 +5949,28 @@ enum intel_display_power_domain
intel_port_to_power_domain(enum port port)
}
}
+enum intel_display_power_domain
+intel_aux_power_domain(struct intel_digital_port *dig_port)
+{
+ switch (dig_port->aux_ch) {
+ case AUX_CH_A:
+ return POWER_DOMAIN_AUX_A;
+ case AUX_CH_B:
+ return POWER_DOMAIN_AUX_B;
+ case AUX_CH_C:
+ return POWER_DOMAIN_AUX_C;
+ case AUX_CH_D:
+ return POWER_DOMAIN_AUX_D;
+ case AUX_CH_E:
+ return POWER_DOMAIN_AUX_E;
+ case AUX_CH_F:
+ return POWER_DOMAIN_AUX_F;
+ default:
+ MISSING_CASE(dig_port->aux_ch);
+ return POWER_DOMAIN_AUX_A;
+ }
+}
+
static u64 get_crtc_power_domains(struct drm_crtc *crtc,
struct intel_crtc_state *crtc_state)
{
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6645c9faca9a..e6f59ef59be6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -690,7 +690,8 @@ static void pps_lock(struct intel_dp *intel_dp)
* See intel_power_sequencer_reset() why we need
* a power domain reference here.
*/
- intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
+ intel_display_power_get(dev_priv,
+
intel_aux_power_domain(dp_to_dig_port(intel_dp)));
mutex_lock(&dev_priv->pps_mutex);
}
@@ -701,7 +702,8 @@ static void pps_unlock(struct intel_dp *intel_dp)
mutex_unlock(&dev_priv->pps_mutex);
- intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
+ intel_display_power_put(dev_priv,
+
intel_aux_power_domain(dp_to_dig_port(intel_dp)));
}
static void
@@ -1505,29 +1507,6 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct
drm_dp_aux_msg *msg)
return ret;
}
-static enum intel_display_power_domain
-intel_aux_power_domain(struct intel_dp *intel_dp)
-{
- struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-
- switch (dig_port->aux_ch) {
- case AUX_CH_A:
- return POWER_DOMAIN_AUX_A;
- case AUX_CH_B:
- return POWER_DOMAIN_AUX_B;
- case AUX_CH_C:
- return POWER_DOMAIN_AUX_C;
- case AUX_CH_D:
- return POWER_DOMAIN_AUX_D;
- case AUX_CH_E:
- return POWER_DOMAIN_AUX_E;
- case AUX_CH_F:
- return POWER_DOMAIN_AUX_F;
- default:
- MISSING_CASE(dig_port->aux_ch);
- return POWER_DOMAIN_AUX_A;
- }
-}
static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
{
@@ -1654,8 +1633,6 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct intel_encoder *encoder = &dig_port->base;
- intel_dp->aux_power_domain = intel_aux_power_domain(intel_dp);
-
if (INTEL_GEN(dev_priv) >= 9) {
intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
intel_dp->aux_ch_data_reg = skl_aux_data_reg;
@@ -2356,7 +2333,8 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
if (edp_have_panel_vdd(intel_dp))
return need_to_disable;
- intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
+ intel_display_power_get(dev_priv,
+ intel_aux_power_domain(intel_dig_port));
DRM_DEBUG_KMS("Tur
[Intel-gfx] [PATCH 7/8] drm/i915: Configure AUX_CH_CTL when enabling the AUX power domain
Most of the AUX_CH_CTL flags are concerned with DP AUX transfer
parameters. As opposed to this the flag specifying the thunderbolt vs.
non-thunderbolt mode of the port is not related to AUX transfers at all
(rather it's repurposed to enable either TBT or non-TBT PHY HW blocks).
The programming has to be done before enabling the corresponding AUX
power well, so make it part of the power well code.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108548
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 69 +
2 files changed, 62 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c57b701f72a7..dbf894835cb2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -921,6 +921,7 @@ struct i915_power_well_desc {
/* The pw is backing the VGA functionality */
bool has_vga:1;
bool has_fuses:1;
+ bool is_tc_tbt;
} hsw;
};
const struct i915_power_well_ops *ops;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 5f5416eb9644..eed17440a4a7 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -465,6 +465,44 @@ icl_combo_phy_aux_power_well_disable(struct
drm_i915_private *dev_priv,
hsw_wait_for_power_well_disable(dev_priv, power_well);
}
+#define ICL_AUX_PW_TO_CH(pw_idx) \
+ ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
+
+static void
+icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
+struct i915_power_well *power_well)
+{
+ const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ int pw_idx = power_well->desc->hsw.idx;
+ enum aux_ch aux_ch = ICL_AUX_PW_TO_CH(pw_idx);
+ u32 val;
+
+ val = I915_READ(DP_AUX_CH_CTL(aux_ch));
+ val &= ~DP_AUX_CH_CTL_TBT_IO;
+ if (power_well->desc->hsw.is_tc_tbt)
+ val |= DP_AUX_CH_CTL_TBT_IO;
+ I915_WRITE(DP_AUX_CH_CTL(aux_ch), val);
+
+ val = I915_READ(regs->driver);
+ I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
+
+ hsw_wait_for_power_well_enable(dev_priv, power_well);
+}
+
+static void
+icl_tc_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
+ int pw_idx = power_well->desc->hsw.idx;
+ u32 val;
+
+ val = I915_READ(regs->driver);
+ I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
+
+ hsw_wait_for_power_well_disable(dev_priv, power_well);
+}
+
/*
* We should only use the power well if we explicitly asked the hardware to
* enable it, so check if it's enabled and also check if we've requested it to
@@ -2725,6 +2763,13 @@ static const struct i915_power_well_ops
icl_combo_phy_aux_power_well_ops = {
.is_enabled = hsw_power_well_enabled,
};
+static const struct i915_power_well_ops icl_tc_phy_aux_power_well_ops = {
+ .sync_hw = hsw_power_well_sync_hw,
+ .enable = icl_tc_phy_aux_power_well_enable,
+ .disable = icl_tc_phy_aux_power_well_disable,
+ .is_enabled = hsw_power_well_enabled,
+};
+
static const struct i915_power_well_regs icl_aux_power_well_regs = {
.bios = ICL_PWR_WELL_CTL_AUX1,
.driver = ICL_PWR_WELL_CTL_AUX2,
@@ -2870,81 +2915,89 @@ static const struct i915_power_well_desc
icl_power_wells[] = {
{
.name = "AUX C",
.domains = ICL_AUX_C_IO_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
+ .hsw.is_tc_tbt = false,
},
},
{
.name = "AUX D",
.domains = ICL_AUX_D_IO_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_regs,
.hsw.idx = ICL_PW_CTL_IDX_AUX_D,
+ .hsw.is_tc_tbt = false,
},
},
{
.name = "AUX E",
.domains = ICL_AUX_E_IO_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
+ .ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
.hsw.regs = &icl_aux_power_well_reg
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Stop calling intel_opregion unregister/register in suspend/resume (rev2)
== Series Details == Series: drm/i915: Stop calling intel_opregion unregister/register in suspend/resume (rev2) URL : https://patchwork.freedesktop.org/series/50630/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5054_full -> Patchwork_10649_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_10649_full that come from known issues: === IGT changes === Issues hit igt@drv_suspend@sysfs-reader: shard-skl: PASS -> INCOMPLETE (fdo#104108, fdo#107773) +1 igt@gem_exec_nop@signal-all: shard-apl: PASS -> INCOMPLETE (fdo#103927) igt@gem_exec_schedule@pi-ringfull-blt: shard-skl: NOTRUN -> FAIL (fdo#103158) igt@kms_busy@extended-modeset-hang-newfb-render-b: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_cursor_crc@cursor-256x256-suspend: shard-kbl: PASS -> DMESG-WARN (fdo#103313) +1 igt@kms_cursor_crc@cursor-256x85-onscreen: shard-apl: PASS -> FAIL (fdo#103232) igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-skl: PASS -> FAIL (fdo#105363) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-glk: PASS -> FAIL (fdo#103167) +1 igt@kms_frontbuffer_tracking@psr-suspend: shard-skl: PASS -> INCOMPLETE (fdo#106978, fdo#104108, fdo#107773) igt@kms_plane_alpha_blend@pipe-b-alpha-7efc: shard-skl: NOTRUN -> FAIL (fdo#108145, fdo#107815) igt@kms_plane_multiple@atomic-pipe-b-tiling-y: shard-apl: PASS -> FAIL (fdo#103166) igt@kms_setmode@basic: shard-hsw: PASS -> FAIL (fdo#99912) shard-kbl: PASS -> FAIL (fdo#99912) igt@pm_rpm@system-suspend: shard-skl: PASS -> INCOMPLETE (fdo#107807, fdo#104108) Possible fixes igt@gem_eio@in-flight-contexts-1us: shard-glk: FAIL (fdo#105957) -> PASS igt@kms_atomic_transition@1x-modeset-transitions-fencing: shard-skl: FAIL (fdo#108470, fdo#107815) -> PASS igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-kbl: FAIL -> PASS igt@kms_color@pipe-c-degamma: shard-apl: FAIL (fdo#104782) -> PASS igt@kms_cursor_crc@cursor-256x85-random: shard-apl: FAIL (fdo#103232) -> PASS +2 igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: shard-glk: DMESG-WARN (fdo#105763, fdo#106538) -> PASS igt@kms_flip_tiling@flip-x-tiled: shard-skl: FAIL (fdo#108145) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max: shard-glk: FAIL (fdo#108145) -> PASS igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: shard-skl: FAIL (fdo#107815) -> PASS igt@kms_plane_multiple@atomic-pipe-b-tiling-x: shard-apl: FAIL (fdo#103166) -> PASS +1 igt@kms_plane_multiple@atomic-pipe-c-tiling-y: shard-glk: FAIL (fdo#103166) -> PASS igt@perf@oa-exponents: shard-glk: FAIL (fdo#105483) -> PASS fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105483 https://bugs.freedesktop.org/show_bug.cgi?id=105483 fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763 fdo#105957 https://bugs.freedesktop.org/show_bug.cgi?id=105957 fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538 fdo#106978 https://bugs.freedesktop.org/show_bug.cgi?id=106978 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815 fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956 fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145 fdo#108470 https://bugs.freedesktop.org/show_bug.cgi?id=108470 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (6 -> 6) == No changes in participating hosts == Build changes == * Linux: CI_DRM_5054 -> Patchwork_10649 CI_DRM_5054: dfa9e5c2b4b958e77c1109477b94c5c8615e25cc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://a
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/icl: dsi enabling (rev3)
== Series Details == Series: drm/i915/icl: dsi enabling (rev3) URL : https://patchwork.freedesktop.org/series/51011/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_5055 -> Patchwork_10651 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10651 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10651, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51011/revisions/3/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10651: === IGT changes === Possible regressions igt@kms_flip@basic-flip-vs-wf_vblank: fi-icl-u: NOTRUN -> DMESG-WARN +17 igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-icl-u2: PASS -> DMESG-WARN +17 == Known issues == Here are the changes found in Patchwork_10651 that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_contexts: fi-icl-u: NOTRUN -> DMESG-FAIL (fdo#108569) igt@gem_ctx_create@basic-files: fi-icl-u2: PASS -> DMESG-WARN (fdo#107724) igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: PASS -> DMESG-WARN (fdo#102614) fi-byt-clapper: PASS -> FAIL (fdo#103167) Possible fixes igt@debugfs_test@read_all_entries: fi-icl-u2: DMESG-WARN (fdo#108070) -> PASS igt@gem_ctx_switch@basic-default: fi-icl-u: INCOMPLETE (fdo#108315) -> PASS igt@gem_exec_suspend@basic-s3: fi-icl-u2: DMESG-WARN (fdo#106612) -> PASS fi-skl-6700k2: INCOMPLETE (k.org#199541, fdo#104108, fdo#107773, fdo#105524) -> PASS fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#105524 https://bugs.freedesktop.org/show_bug.cgi?id=105524 fdo#106612 https://bugs.freedesktop.org/show_bug.cgi?id=106612 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 fdo#108070 https://bugs.freedesktop.org/show_bug.cgi?id=108070 fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315 fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569 k.org#199541 https://bugzilla.kernel.org/show_bug.cgi?id=199541 == Participating hosts (48 -> 43) == Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u == Build changes == * Linux: CI_DRM_5055 -> Patchwork_10651 CI_DRM_5055: 9471771fb0a56bb6559279fcdbb445d270036af3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4700: b517f6533671552166c11748ee48019093ebd069 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10651: 87c8755de8fc26e7997599089806eed5a1b8d86d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 87c8755de8fc drm/i915/icl: Get pipe timings for DSI 4e19ec989821 drm/i915/icl: Consider DSI for getting transcoder state b4c783231fd1 drm/i915/icl: Don't wait for empty FIFO b3834b323e7d HACK: drm/i915/icl: Configure backlight functions for DSI cbd69ec4862c drm/i915/icl: Add changes to program DSI panel GPIOs 8092c3e0dd04 drm/i915/icl: Define display GPIO pins for DSI 01e453ac8a6a drm/i915/icl: Define missing bitfield for shortplug reg aaf6977b06cb drm/i915/icl: Define Panel power ctrl register 72501c3a8bba drm/i915/icl: Configure DSI Dual link mode 2f152a982bd2 drm/i915/icl: Add DSS_CTL Registers e26fb20cea2f drm/i915/icl: Fill DSI ports info e894b96c824e drm/i915/icl: Add DSI encoder remaining functions 72c28090b6a5 drm/i915/icl: Add DSI connector helper functions 4748427f0452 drm/i915/icl: Add DSI connector functions cd3d49a7257a drm/i915/icl: Get HW state for DSI encoder 7bc214009751 drm/i915/icl: Add get config functionality for DSI df317648ec35 drm/i915/icl: Load DSI packet payload to queue 85ce70db0e45 drm/i915/icl: Fetch DSI pkt to be transferred 992b03129f02 drm/i915/icl: Add DSI packet payload/header registers c69cff40f89b drm/i915/icl: Allocate hosts for DSI ports 83b3f57d6785 drm/i915/icl: Allocate DSI encoder/connector 0f3cc0b226a3 drm/i915/icl: Find DSI presence for ICL ad6fc7baabda drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers dfb7554669d3 drm/i915/icl: Define DSI timeout registers cbfe2668e9d7 drm/i915/icl: Disable DSI IO power 32d59c491aa9 drm/i915/icl: Disable DSI ports 6b60f18669ea drm/i915/icl: Disable portsync mode 8c3c2895d1d6 drm/i915/icl: Disable DDI function b6edabbc57fe drm/i915/icl: Put DSI link in ULPS
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: Fix HDMI on TypeC static ports
== Series Details == Series: drm/i915/icl: Fix HDMI on TypeC static ports URL : https://patchwork.freedesktop.org/series/51765/ State : warning == Summary == $ dim checkpatch origin/drm-tip 83eb4def4751 drm/i915: Move intel_aux_ch() to intel_bios.c -:47: CHECK:SPACING: No space is necessary after a cast #47: FILE: drivers/gpu/drm/i915/intel_bios.c:2170: + aux_ch = (enum aux_ch) port; total: 0 errors, 0 warnings, 1 checks, 117 lines checked 0b6dfef45914 drm/i915: Move aux_ch to intel_digital_port 53ffb8f38693 drm/i915: Init aux_ch for HDMI ports too 220df38c6c99 drm/i915: Use a helper to get the aux power domain f4b2a2abef1f drm/i915: Enable AUX power earlier de78682eb1be drm/i915: Enable AUX power for HDMI DDI/TypeC main link too 95c39a9a3a65 drm/i915: Configure AUX_CH_CTL when enabling the AUX power domain -:30: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384 #30: FILE: drivers/gpu/drm/i915/i915_drv.h:924: + bool is_tc_tbt; total: 0 errors, 0 warnings, 1 checks, 161 lines checked ef4031503b26 drm/i915/icl+: Sanitize port to PLL mapping ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/icl: Fix HDMI on TypeC static ports
== Series Details == Series: drm/i915/icl: Fix HDMI on TypeC static ports URL : https://patchwork.freedesktop.org/series/51765/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Move intel_aux_ch() to intel_bios.c -drivers/gpu/drm/i915/selftests/../i915_drv.h:3699:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3700:16: warning: expression using sizeof(void) Commit: drm/i915: Move aux_ch to intel_digital_port Okay! Commit: drm/i915: Init aux_ch for HDMI ports too Okay! Commit: drm/i915: Use a helper to get the aux power domain Okay! Commit: drm/i915: Enable AUX power earlier Okay! Commit: drm/i915: Enable AUX power for HDMI DDI/TypeC main link too Okay! Commit: drm/i915: Configure AUX_CH_CTL when enabling the AUX power domain -drivers/gpu/drm/i915/selftests/../i915_drv.h:3700:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3701:16: warning: expression using sizeof(void) Commit: drm/i915/icl+: Sanitize port to PLL mapping Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
