Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Add XYUV format support (rev6)

[Lisovskiy, Stanislav]

On Fri, 2018-09-07 at 18:21 +0300, Martin Peres wrote:
> 
> 
> 
> This is known issue: https://bugs.freedesktop.org/show_bug.cgi?id=106
> 701
> 
> That means your patch is a SUCCESS from a CI perspective. Sorry for
> the
> noise!
> 

Sounds just great! :)

> > 
> >  Warnings 
> > 
> > igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
> >   shard-hsw:  SKIP -> PASS
> > 
> > igt@kms_vblank@pipe-b-wait-forked:
> >   shard-snb:  PASS -> SKIP
> > 
> > igt@perf_pmu@rc6:
> >   shard-kbl:  PASS -> SKIP
> > 
> > 
> > == Known issues ==
> > 
> >   Here are the changes found in Patchwork_10123_full that come from
> > known issues:
> > 
> >   === IGT changes ===
> > 
> >  Issues hit 
> > 
> > igt@drv_suspend@shrink:
> >   shard-glk:  PASS -> FAIL (fdo#106886)
> > 
> > igt@gem_exec_big:
> >   shard-hsw:  PASS -> INCOMPLETE (fdo#103540)
> > 
> > 
> >  Possible fixes 
> > 
> > igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mma
> > p-gtt:
> >   shard-glk:  FAIL (fdo#103167) -> PASS
> > 
> > igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mma
> > p-wc:
> >   shard-apl:  FAIL (fdo#103167) -> PASS
> > 
> > 
> >   fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
> >   fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
> >   fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
> > 
> > 
> > == Participating hosts (5 -> 5) ==
> > 
> >   No changes in participating hosts
> > 
> > 
> > == Build changes ==
> > 
> > * Linux: CI_DRM_4786 -> Patchwork_10123
> > 
> >   CI_DRM_4786: d28dcb05a3c33df6fcb0828d81fa0bb6591a97be @
> > git://anongit.freedesktop.org/gfx-ci/linux
> >   IGT_4634: 7d89cc39dde3b4881d85ace45d504cc098fa3684 @
> > git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> >   Patchwork_10123: 43038ad4912e589e9c487d88f4901c064ea66af4 @
> > git://anongit.freedesktop.org/gfx-ci/linux
> >   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> > git://anongit.freedesktop.org/piglit
> > 
> > == Logs ==
> > 
> > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patc
> > hwork_10123/shards.html
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
-- 
Best Regards,

Lisovskiy Stanislav
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Re: [Intel-gfx] [v5, 02/13] drm/i915/icl: DSI vswing programming sequence

[Madhav Chauhan]

On 9/6/2018 7:31 PM, Kulkarni, Vandita wrote:




On 7/10/2018 3:10 PM, Madhav Chauhan wrote:

This patch setup voltage swing before enabling
combo PHY DDI (shared with DSI).
Note that DSI voltage swing programming is for
high speed data buffers. HW automatically handles
the voltage swing for the low power data buffers.

v2: Rebase

Signed-off-by: Madhav Chauhan
---
  drivers/gpu/drm/i915/icl_dsi.c | 114 +
  1 file changed, 114 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index a571339..dc16c1f 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -27,6 +27,65 @@
  
  #include "intel_dsi.h"
  
+static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)

+{
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+   enum port port;
+   u32 tmp;
+   int lane;
+
+   for_each_dsi_port(port, intel_dsi->ports) {
+
+   /* Bspec: set scaling mode to 0x6 */
+   tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+   tmp |= SCALING_MODE_SEL(6);
+   I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+   tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+   tmp |= SCALING_MODE_SEL(6);
+   I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+   tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+   tmp |= TAP2_DISABLE | TAP3_DISABLE;
+   I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+   tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+   tmp |= TAP2_DISABLE | TAP3_DISABLE;
+   I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+
+   /*
+* swing and scaling values are taken from DSI
+* table under vswing programming sequence for
+* combo phy ddi in BSPEC.
+* program swing values
+*/
+   tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
+   tmp |= SWING_SEL_UPPER(0x2);
+   tmp |= SWING_SEL_LOWER(0x2);
+   tmp |= RCOMP_SCALAR(0x98);
+   I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
+   tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
+   tmp |= SWING_SEL_UPPER(0x2);
+   tmp |= SWING_SEL_LOWER(0x2);
+   tmp |= RCOMP_SCALAR(0x98);
+   I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
+
+   /* program scaling values */
+   tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
+   tmp |= POST_CURSOR_1(0x0);
+   tmp |= POST_CURSOR_2(0x0);
+   tmp |= CURSOR_COEFF(0x18);
+   I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
+
+   for (lane = 0; lane <= 3; lane++) {
+   /* Bspec: must not use GRP register for write */
+   tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
+   tmp |= POST_CURSOR_1(0x0);
+   tmp |= POST_CURSOR_2(0x0);
+   tmp |= CURSOR_COEFF(0x18);
+   I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
+   }
+   }
+}
+
  static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
  {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -140,6 +199,58 @@ static void gen11_dsi_config_phy_lanes_sequence(struct 
intel_encoder *encoder)
}
  }
  


I see from the bspec that except for the Loadgen Select and Latency 
Optimization all other DDI buffer programming can be taken from the 
DDI Buffer section.


Can we use this function "icl_ddi_combo_vswing_program" function which 
is already there

patch for reference:
https://patchwork.freedesktop.org/patch/213515/



We can't directly use that implementation. Reasons:
1. For DSI we use AUX register as well to write which is not the case 
for DDI. We need to add multiple INTEL_OUTPUT_DSI

checks .
2. DSI specific icl_combo_phy_ddi_buf_trans not added in intel_ddi.c 
which will be used while doing vswing programming

3. intel_ddi_dp_level doesn't support "level" calculation for DSI.

Also in past we had similar discussion (with Jani N) to keep DSI 
specific entries/code in DSI encoder.


Jani N whats the suggestion here??

Regards,
Madhav



Thanks,
Vandita


+static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
+{
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+   u32 tmp;
+   enum port port;
+
+   /* Step C.1:clear common keeper enable bit */
+   for_each_dsi_port(port, intel_dsi->ports) {
+   tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
+   tmp &= ~COMMON_KEEPER_EN;
+   I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
+   tmp 

[Intel-gfx] [PATCH 0/3] add LG panel to dpcd quirk database

[Lee, Shawn C]

Only specific N value (0x8000) would be acceptable for LG
LP140WF6-SPM1 eDP panel which is running at asynchronous
clock mode. With the other N value, it will enter BITS mode
and display black screen. This patch series set constant N
value for specific sink/branch device that would cover
similar issue.

Cc: Jani Nikula 
Cc: Cooper Chiou 
Cc: Matt Atwood 
Cc: Maarten Lankhorst 
Cc: Dhinakaran Pandiyan 
Cc: Clint Taylor 

Lee, Shawn C (3):
  drm: Add support for device_id based detection.
  drm: Change limited M/N quirk to constant N quirk.
  drm: add LG eDP panel to quirk database

 drivers/gpu/drm/drm_dp_helper.c  | 17 -
 drivers/gpu/drm/i915/intel_display.c | 26 +++---
 drivers/gpu/drm/i915/intel_display.h |  2 +-
 drivers/gpu/drm/i915/intel_dp.c  |  8 
 drivers/gpu/drm/i915/intel_dp_mst.c  |  6 +++---
 include/drm/drm_dp_helper.h  |  6 +++---
 6 files changed, 38 insertions(+), 27 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH 3/3] drm: add LG eDP panel to quirk database

[Lee, Shawn C]

The N value was computed by kernel driver that based on synchronous clock
mode. But only specific N value (0x8000) would be acceptable for
LG LP140WF6-SPM1 eDP panel which is running at asynchronous clock mode.
With the other N value, Tcon will enter BITS mode and display black screen.
Add this panel into quirk database and give particular N value when
calculate M/N divider.

Cc: Jani Nikula 
Cc: Cooper Chiou 
Cc: Matt Atwood 
Cc: Maarten Lankhorst 
Cc: Dhinakaran Pandiyan 
Cc: Clint Taylor 
Signed-off-by: Lee, Shawn C 
---
 drivers/gpu/drm/drm_dp_helper.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index d0c1250975ab..0ef7c43a9025 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1270,6 +1270,8 @@ struct dpcd_quirk {
 static const struct dpcd_quirk dpcd_quirk_list[] = {
/* Analogix 7737 needs reduced M and N at HBR2 link rates */
{ OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, 
BIT(DP_DPCD_QUIRK_CONSTANT_N) },
+   /* LG LP140WF6-SPM1 eDP panel */
+   { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), 
false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
 };
 
 #undef OUI
-- 
2.7.4

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[Intel-gfx] [PATCH 2/3] drm: Change limited M/N quirk to constant N quirk.

[Lee, Shawn C]

Some DP dongles in particular seem to be fussy about too large
link M/N values. Set specific value for N divider can resolve
this issue per dongle vendor's comment. So configure N as
constant value (0x8000) to instead of reduce M/N formula when
specific DP dongle connected.

Cc: Jani Nikula 
Cc: Cooper Chiou 
Cc: Matt Atwood 
Cc: Maarten Lankhorst 
Cc: Dhinakaran Pandiyan 
Cc: Clint Taylor 
Signed-off-by: Lee, Shawn C 
---
 drivers/gpu/drm/drm_dp_helper.c  |  2 +-
 drivers/gpu/drm/i915/intel_display.c | 26 +++---
 drivers/gpu/drm/i915/intel_display.h |  2 +-
 drivers/gpu/drm/i915/intel_dp.c  |  8 
 drivers/gpu/drm/i915/intel_dp_mst.c  |  6 +++---
 include/drm/drm_dp_helper.h  |  6 +++---
 6 files changed, 23 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 22753928af41..d0c1250975ab 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1269,7 +1269,7 @@ struct dpcd_quirk {
 
 static const struct dpcd_quirk dpcd_quirk_list[] = {
/* Analogix 7737 needs reduced M and N at HBR2 link rates */
-   { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, 
BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
+   { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, 
BIT(DP_DPCD_QUIRK_CONSTANT_N) },
 };
 
 #undef OUI
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index ec3e24f07486..b26f4ae60810 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6680,22 +6680,18 @@ intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
 
 static void compute_m_n(unsigned int m, unsigned int n,
uint32_t *ret_m, uint32_t *ret_n,
-   bool reduce_m_n)
+   bool constant_n)
 {
/*
-* Reduce M/N as much as possible without loss in precision. Several DP
-* dongles in particular seem to be fussy about too large *link* M/N
-* values. The passed in values are more likely to have the least
-* significant bits zero than M after rounding below, so do this first.
+* Several DP dongles in particular seem to be fussy about
+* too large *link* M/N * values. Give N value as 0x8000
+* that should be acceptable by specific devices.
 */
-   if (reduce_m_n) {
-   while ((m & 1) == 0 && (n & 1) == 0) {
-   m >>= 1;
-   n >>= 1;
-   }
-   }
+   if (constant_n)
+   *ret_n = 0x8000;
+   else
+   *ret_n = min_t(unsigned int, roundup_pow_of_two(n), 
DATA_LINK_N_MAX);
 
-   *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
*ret_m = div_u64((uint64_t) m * *ret_n, n);
intel_reduce_m_n_ratio(ret_m, ret_n);
 }
@@ -6704,18 +6700,18 @@ void
 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
   int pixel_clock, int link_clock,
   struct intel_link_m_n *m_n,
-  bool reduce_m_n)
+  bool constant_n)
 {
m_n->tu = 64;
 
compute_m_n(bits_per_pixel * pixel_clock,
link_clock * nlanes * 8,
&m_n->gmch_m, &m_n->gmch_n,
-   reduce_m_n);
+   constant_n);
 
compute_m_n(pixel_clock, link_clock,
&m_n->link_m, &m_n->link_n,
-   reduce_m_n);
+   constant_n);
 }
 
 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_display.h 
b/drivers/gpu/drm/i915/intel_display.h
index 43f080c6538d..8e8bd5eed2c2 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -379,7 +379,7 @@ struct intel_link_m_n {
 void intel_link_compute_m_n(int bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
-   bool reduce_m_n);
+   bool constant_n);
 
 bool is_ccs_modifier(u64 modifier);
 #endif
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 436c22de33b6..fce4be57ccc9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1998,8 +1998,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_connector *intel_connector = intel_dp->attached_connector;
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(conn_state);
-   bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
-  DP_DPCD_QUIRK_LIMITED_M_N);
+   bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
+  DP_DPCD_QUIRK_CONSTANT_N);
 
if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) &

[Intel-gfx] [PATCH 1/3] drm: Add support for device_id based detection.

[Lee, Shawn C]

DP quirk list just compare sink or branch device's OUI so far.
That means particular vendor's products will be applied specific
change. This change would confirm device_id the same or not.
Then driver can implement some changes for branch/sink device
that really need additional WA.

Cc: Jani Nikula 
Cc: Cooper Chiou 
Cc: Matt Atwood 
Cc: Maarten Lankhorst 
Cc: Dhinakaran Pandiyan 
Cc: Clint Taylor 
Signed-off-by: Lee, Shawn C 
---
 drivers/gpu/drm/drm_dp_helper.c | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 0cccbcb2d03e..22753928af41 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1256,15 +1256,20 @@ EXPORT_SYMBOL(drm_dp_stop_crc);
 
 struct dpcd_quirk {
u8 oui[3];
+   u8 device_id[6];
bool is_branch;
u32 quirks;
 };
 
 #define OUI(first, second, third) { (first), (second), (third) }
+#define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
+   { (first), (second), (third), (fourth), (fifth), (sixth) }
+
+#define DEVICE_ID_ANY  DEVICE_ID(0, 0, 0, 0, 0, 0)
 
 static const struct dpcd_quirk dpcd_quirk_list[] = {
/* Analogix 7737 needs reduced M and N at HBR2 link rates */
-   { OUI(0x00, 0x22, 0xb9), true, BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
+   { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, 
BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
 };
 
 #undef OUI
@@ -1283,6 +1288,7 @@ drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, 
bool is_branch)
const struct dpcd_quirk *quirk;
u32 quirks = 0;
int i;
+   u8 any_device[6] = DEVICE_ID_ANY;
 
for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
quirk = &dpcd_quirk_list[i];
@@ -1293,12 +1299,19 @@ drm_dp_get_quirks(const struct drm_dp_dpcd_ident 
*ident, bool is_branch)
if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
continue;
 
+   if (memcmp(quirk->device_id, any_device, 6) != 0 &&
+   memcmp(quirk->device_id, ident->device_id, 6) != 0)
+   continue;
+
quirks |= quirk->quirks;
}
 
return quirks;
 }
 
+#undef DEVICE_ID_ANY
+#undef DEVICE_ID
+
 /**
  * drm_dp_read_desc - read sink/branch descriptor from DPCD
  * @aux: DisplayPort AUX channel
-- 
2.7.4

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Make i915 check for panel orient quirks on eDP and add one such quirk

[Patchwork]

== Series Details ==

Series: drm: Make i915 check for panel orient quirks on eDP and add one such 
quirk
URL   : https://patchwork.freedesktop.org/series/49389/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
c514c6c8ea38 drm/i915: Check for panel orientation quirks on eDP panels
-:33: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#33: FILE: drivers/gpu/drm/i915/intel_dp.c:6494:
+   drm_connector_init_panel_orientation_property(

-:38: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch 
author 'Hans de Goede '

total: 0 errors, 1 warnings, 1 checks, 10 lines checked
0efa0ba71ccd drm: panel-orientation-quirks: Add quirk for GPD win2
-:49: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch 
author 'Hans de Goede '

total: 0 errors, 1 warnings, 0 checks, 28 lines checked

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Make i915 check for panel orient quirks on eDP and add one such quirk

[Patchwork]

== Series Details ==

Series: drm: Make i915 check for panel orient quirks on eDP and add one such 
quirk
URL   : https://patchwork.freedesktop.org/series/49389/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4788 -> Patchwork_10131 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/49389/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10131 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_exec_suspend@basic-s4-devices:
  fi-blb-e6850:   PASS -> INCOMPLETE (fdo#107718)

igt@kms_frontbuffer_tracking@basic:
  fi-byt-clapper: PASS -> FAIL (fdo#103167)

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
  fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191)


 Possible fixes 

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
  fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS

igt@kms_psr@primary_page_flip:
  fi-cnl-psr: FAIL (fdo#107336) -> PASS


  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718


== Participating hosts (51 -> 47) ==

  Missing(4): fi-ctg-p8600 fi-ilk-m540 fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4788 -> Patchwork_10131

  CI_DRM_4788: 79cc335f1963668a20a974b9641be97d44b286ea @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4636: 40de31df52ffed5e392d607a83e3aea4efb150e6 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10131: 0efa0ba71ccdd028e3104c2fbac2a24f4c64678a @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

0efa0ba71ccd drm: panel-orientation-quirks: Add quirk for GPD win2
c514c6c8ea38 drm/i915: Check for panel orientation quirks on eDP panels

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10131/issues.html
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Re: [Intel-gfx] [PATCH v2] drm/i915: use for_each_pipe loop to assign crtc_mask

[Jani Nikula]

On Fri, 07 Sep 2018, Ville Syrjälä  wrote:
> On Fri, Sep 07, 2018 at 04:04:03PM +0300, Jani Nikula wrote:
>> On Fri, 07 Sep 2018, Mahesh Kumar  wrote:
>> > This cleanup patch makes changes to use for_each_pipe loop
>> > during bit-mask assignment of allowed crtc with encoder.
>> >
>> > changes:
>> >  - use BIT(i) macro instead of (1 << i) (Chris)
>> >
>> > Cc: Jani Nikula 
>> > Cc: Rodrigo Vivi 
>> > Signed-off-by: Mahesh Kumar 
>> > ---
>> >  drivers/gpu/drm/i915/intel_ddi.c  | 4 +++-
>> >  drivers/gpu/drm/i915/intel_dp.c   | 5 -
>> >  drivers/gpu/drm/i915/intel_hdmi.c | 5 -
>> >  3 files changed, 11 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
>> > b/drivers/gpu/drm/i915/intel_ddi.c
>> > index cd01a09c5e0f..88dfca245099 100644
>> > --- a/drivers/gpu/drm/i915/intel_ddi.c
>> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> > @@ -3751,6 +3751,7 @@ void intel_ddi_init(struct drm_i915_private 
>> > *dev_priv, enum port port)
>> >struct intel_encoder *intel_encoder;
>> >struct drm_encoder *encoder;
>> >bool init_hdmi, init_dp, init_lspcon = false;
>> > +  u8 i;
>> 
>> Please use int instead of u8 throughout. u8 only makes sense when you
>> actually need the specific size, or need to be concerned about the size.
>
> Actually please use 'enum pipe pipe'.

D'oh, of course.

BR,
Jani.


>
>> 
>> BR,
>> Jani.
>> 
>> >  
>> >  
>> >init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
>> > @@ -3801,8 +3802,9 @@ void intel_ddi_init(struct drm_i915_private 
>> > *dev_priv, enum port port)
>> >intel_encoder->type = INTEL_OUTPUT_DDI;
>> >intel_encoder->power_domain = intel_port_to_power_domain(port);
>> >intel_encoder->port = port;
>> > -  intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
>> >intel_encoder->cloneable = 0;
>> > +  for_each_pipe(dev_priv, i)
>> > +  intel_encoder->crtc_mask |= BIT(i);
>> >  
>> >if (INTEL_GEN(dev_priv) >= 11)
>> >intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
>> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
>> > b/drivers/gpu/drm/i915/intel_dp.c
>> > index 436c22de33b6..1f954debdc55 100644
>> > --- a/drivers/gpu/drm/i915/intel_dp.c
>> > +++ b/drivers/gpu/drm/i915/intel_dp.c
>> > @@ -6709,7 +6709,10 @@ bool intel_dp_init(struct drm_i915_private 
>> > *dev_priv,
>> >else
>> >intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
>> >} else {
>> > -  intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
>> > +  u8 i;
>> > +
>> > +  for_each_pipe(dev_priv, i)
>> > +  intel_encoder->crtc_mask |= BIT(i);
>> >}
>> >intel_encoder->cloneable = 0;
>> >intel_encoder->port = port;
>> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
>> > b/drivers/gpu/drm/i915/intel_hdmi.c
>> > index a2dab0b6bde6..647e38de7980 100644
>> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
>> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
>> > @@ -2468,7 +2468,10 @@ void intel_hdmi_init(struct drm_i915_private 
>> > *dev_priv,
>> >else
>> >intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
>> >} else {
>> > -  intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
>> > +  u8 i;
>> > +
>> > +  for_each_pipe(dev_priv, i)
>> > +  intel_encoder->crtc_mask |= BIT(i);
>> >}
>> >intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
>> >/*
>> 
>> -- 
>> Jani Nikula, Intel Open Source Graphics Center
>> ___
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Getting rid of GUP and use HMM for user ptr features.

[Patchwork]

== Series Details ==

Series: Getting rid of GUP and use HMM for user ptr features.
URL   : https://patchwork.freedesktop.org/series/49395/
State : failure

== Summary ==

CALLscripts/checksyscalls.sh
  DESCEND  objtool
  CHK include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/i915_gem_userptr.o
drivers/gpu/drm/i915/i915_gem_userptr.c:51:20: error: field ‘mirror’ has 
incomplete type
  struct hmm_mirror mirror;
^~
drivers/gpu/drm/i915/i915_gem_userptr.c:116:22: error: ‘struct hmm_update’ 
declared inside parameter list will not be visible outside of this definition 
or declaration [-Werror]
 const struct hmm_update *update)
  ^~
In file included from ./include/linux/export.h:45:0,
 from ./include/linux/linkage.h:7,
 from ./include/linux/kernel.h:7,
 from ./include/linux/list.h:9,
 from ./include/linux/agp_backend.h:33,
 from ./include/drm/drmP.h:35,
 from drivers/gpu/drm/i915/i915_gem_userptr.c:25:
drivers/gpu/drm/i915/i915_gem_userptr.c: In function 
‘i915_sync_cpu_device_pagetables’:
./include/linux/kernel.h:997:32: error: dereferencing pointer to incomplete 
type ‘struct hmm_mirror’
  BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
^~
./include/linux/compiler.h:335:18: note: in definition of macro 
‘__compiletime_assert’
   int __cond = !(condition);\
  ^
./include/linux/compiler.h:358:2: note: in expansion of macro 
‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
  ^~~
./include/linux/build_bug.h:45:37: note: in expansion of macro 
‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
 ^~
./include/linux/kernel.h:997:2: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
  BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
  ^~~~
./include/linux/kernel.h:997:20: note: in expansion of macro ‘__same_type’
  BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
^~~
drivers/gpu/drm/i915/i915_gem_userptr.c:119:3: note: in expansion of macro 
‘container_of’
   container_of(_mirror, struct i915_mirror, mirror);
   ^~~~
drivers/gpu/drm/i915/i915_gem_userptr.c:121:28: error: dereferencing pointer to 
incomplete type ‘const struct hmm_update’
  unsigned long end = update->end - 1;
^~
drivers/gpu/drm/i915/i915_gem_userptr.c: At top level:
drivers/gpu/drm/i915/i915_gem_userptr.c:167:21: error: variable 
‘i915_mirror_ops’ has initializer but incomplete type
 static const struct hmm_mirror_ops i915_mirror_ops = {
 ^~
drivers/gpu/drm/i915/i915_gem_userptr.c:168:3: error: ‘const struct 
hmm_mirror_ops’ has no member named ‘sync_cpu_device_pagetables’
  .sync_cpu_device_pagetables = &i915_sync_cpu_device_pagetables,
   ^~
drivers/gpu/drm/i915/i915_gem_userptr.c:168:32: error: excess elements in 
struct initializer [-Werror]
  .sync_cpu_device_pagetables = &i915_sync_cpu_device_pagetables,
^
drivers/gpu/drm/i915/i915_gem_userptr.c:168:32: note: (near initialization for 
‘i915_mirror_ops’)
drivers/gpu/drm/i915/i915_gem_userptr.c:169:3: error: ‘const struct 
hmm_mirror_ops’ has no member named ‘release’
  .release = &i915_mirror_release,
   ^~~
drivers/gpu/drm/i915/i915_gem_userptr.c:169:13: error: excess elements in 
struct initializer [-Werror]
  .release = &i915_mirror_release,
 ^
drivers/gpu/drm/i915/i915_gem_userptr.c:169:13: note: (near initialization for 
‘i915_mirror_ops’)
drivers/gpu/drm/i915/i915_gem_userptr.c: In function ‘i915_mirror_find’:
drivers/gpu/drm/i915/i915_gem_userptr.c:230:9: error: implicit declaration of 
function ‘hmm_mirror_register’; did you mean ‘rc_map_register’? 
[-Werror=implicit-function-declaration]
   err = hmm_mirror_register(&mirror->mirror, mm->mm);
 ^~~
 rc_map_register
drivers/gpu/drm/i915/i915_gem_userptr.c: In function ‘i915_mirror_free’:
drivers/gpu/drm/i915/i915_gem_userptr.c:290:2: error: implicit declaration of 
function ‘hmm_mirror_unregister’; did you mean ‘rc_map_unregister’? 
[-Werror=implicit-function-declaration]
  hmm_mirror_unregister(&mirror->mirror);
  ^
  rc_map_unregister
drivers/gpu/drm/i915/i915_gem_userptr.c: At top level:
drivers/gpu/drm/i915/i915_gem_userptr.c:467:17: error: ‘struct hmm_range’ 
declared inside parameter list will not be visible outside of this definition 
or declaration [-Werror]
  struct hmm_range *range)
 ^
drivers/gpu/drm/i915/i915_gem_userptr.c: In function 
‘__i915_gem_userptr_set_active’:
drivers/gpu/drm/i915/i915_gem_userptr.c:490:8: error: implicit declaration of 
f

[Intel-gfx] ✗ Fi.CI.BAT: failure for add LG panel to dpcd quirk database

[Patchwork]

== Series Details ==

Series: add LG panel to dpcd quirk database
URL   : https://patchwork.freedesktop.org/series/49413/
State : failure

== Summary ==

CALLscripts/checksyscalls.sh
  DESCEND  objtool
  CHK include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/intel_dp.o
drivers/gpu/drm/i915/intel_dp.c: In function ‘intel_dp_compute_config’:
drivers/gpu/drm/i915/intel_dp.c:2077:13: error: ‘costant_n’ undeclared (first 
use in this function); did you mean ‘constant_n’?
 costant_n);
 ^
 constant_n
drivers/gpu/drm/i915/intel_dp.c:2077:13: note: each undeclared identifier is 
reported only once for each function it appears in
scripts/Makefile.build:305: recipe for target 'drivers/gpu/drm/i915/intel_dp.o' 
failed
make[4]: *** [drivers/gpu/drm/i915/intel_dp.o] Error 1
scripts/Makefile.build:546: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:546: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:546: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1060: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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[Intel-gfx] [PULL] gvt-fixes for 4.19-rc4

[Zhenyu Wang]

Hi,

Here's more gvt-fixes for 4.19. Most critical one is to fix
KVM's mm reference when we access guest memory, issue was raised
by Linus in 
https://lists.freedesktop.org/archives/intel-gvt-dev/2018-August/004130.html.
Another one with virtual opregion fix.

Thanks
--
The following changes since commit 54ff01fd0d44b9681615f77c15fe9ea6dfadb501:

  drm/i915/gvt: Give new born vGPU higher scheduling chance (2018-09-03 
14:28:23 +0800)

are available in the Git repository at:

  https://github.com/intel/gvt-linux.git tags/gvt-fixes-2018-09-10

for you to fetch changes up to 792fab2c0d45758ad3d187bd252570d2bb627fa9:

  drm/i915/gvt: Fix the incorrect length of child_device_config issue 
(2018-09-06 11:17:38 +0800)


gvt-fixes-2018-09-10

- KVM mm access reference fix (Zhenyu)
- Fix child device config length for virtual opregion (Weinan)


Weinan Li (1):
  drm/i915/gvt: Fix the incorrect length of child_device_config issue

Zhenyu Wang (1):
  drm/i915/gvt: Fix life cycle reference on KVM mm

 drivers/gpu/drm/i915/gvt/kvmgt.c| 10 --
 drivers/gpu/drm/i915/gvt/opregion.c | 20 +---
 2 files changed, 17 insertions(+), 13 deletions(-)

-- 
Open Source Technology Center, Intel ltd.

$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827


signature.asc
Description: PGP signature
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Re: [Intel-gfx] [PATCH i-g-t] igt/gem_exec_capture: Fix command emission for gen3

[Chris Wilson]

Quoting Chris Wilson (2018-09-09 13:43:08)
> A missing no-op causing us to emit the wrong address when relocation was
> required for BB_START.
 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106078
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106028

> Signed-off-by: Chris Wilson 
> ---
>  tests/gem_exec_capture.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/tests/gem_exec_capture.c b/tests/gem_exec_capture.c
> index 2dc06ce43..9c26e12c9 100644
> --- a/tests/gem_exec_capture.c
> +++ b/tests/gem_exec_capture.c
> @@ -117,7 +117,7 @@ static void __capture(int fd, int dir, unsigned ring, 
> uint32_t target)
> batch[++i] = 0;
> }
> batch[++i] = 0xc0ffee;
> -   if (gen < 3)
> +   if (gen <= 3)
> batch[++i] = MI_NOOP;
>  
> batch[++i] = MI_BATCH_BUFFER_START; /* not crashed? try again! */
> @@ -144,10 +144,12 @@ static void __capture(int fd, int dir, unsigned ring, 
> uint32_t target)
> execbuf.flags = ring;
> if (gen > 3 && gen < 6)
> execbuf.flags |= I915_EXEC_SECURE;
> +
> +   igt_assert(!READ_ONCE(*seqno));
> gem_execbuf(fd, &execbuf);
>  
> /* Wait for the request to start */
> -   while (*(volatile uint32_t *)seqno != 0xc0ffee)
> +   while (READ_ONCE(*seqno) != 0xc0ffee)
> igt_assert(gem_bo_busy(fd, obj[SCRATCH].handle));
> munmap(seqno, 4096);
>  
> -- 
> 2.19.0.rc2
> 
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm: Make i915 check for panel orient quirks on eDP and add one such quirk

[Patchwork]

== Series Details ==

Series: drm: Make i915 check for panel orient quirks on eDP and add one such 
quirk
URL   : https://patchwork.freedesktop.org/series/49389/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4788_full -> Patchwork_10131_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10131_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10131_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_10131_full:

  === IGT changes ===

 Warnings 

igt@pm_rc6_residency@rc6-accuracy:
  shard-snb:  PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_10131_full that come from known 
issues:

  === IGT changes ===

 Issues hit 

igt@drv_suspend@shrink:
  shard-hsw:  PASS -> INCOMPLETE (fdo#106886, fdo#103540)

igt@kms_cursor_legacy@cursor-vs-flip-toggle:
  shard-kbl:  PASS -> FAIL (fdo#103355)

igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
  shard-glk:  PASS -> FAIL (fdo#105363)

igt@kms_setmode@basic:
  shard-kbl:  PASS -> FAIL (fdo#99912)


 Possible fixes 

igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
  shard-apl:  DMESG-WARN (fdo#103558, fdo#105602) -> PASS +15


  fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4788 -> Patchwork_10131

  CI_DRM_4788: 79cc335f1963668a20a974b9641be97d44b286ea @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4636: 40de31df52ffed5e392d607a83e3aea4efb150e6 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10131: 0efa0ba71ccdd028e3104c2fbac2a24f4c64678a @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10131/shards.html
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[Intel-gfx] [CI v2 1/2] drm/i915/guc: Update GuC power domain states

[Michal Wajdeczko]

We should update GuC power domain states also when GuC submission
is disabled, otherwise GuC might complain or ignore our requests.
This seems to be required for all currently released GuC firmwares.

v2: it is only needed by pre-Gen11 firmwares

Signed-off-by: Michal Wajdeczko 
Cc: John Spotswood 
Cc: Anusha Srivatsa 
Cc: Tomasz Lis 
Cc: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/intel_uc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 7c95697..b1b3e81 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -401,6 +401,10 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
ret = intel_guc_submission_enable(guc);
if (ret)
goto err_communication;
+   } else if (INTEL_GEN(i915) < 11) {
+   ret = intel_guc_sample_forcewake(guc);
+   if (ret)
+   goto err_communication;
}
 
dev_info(i915->drm.dev, "GuC firmware version %u.%u\n",
-- 
1.9.1

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[Intel-gfx] [CI v2 2/2] HAX Switch off GuC submission even if explicitly enabled

[Michal Wajdeczko]

Signed-off-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/intel_uc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index b1b3e81..ad659c1 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -157,6 +157,9 @@ static void sanitize_options_early(struct drm_i915_private 
*i915)
 
yesno(GUC_LOG_LEVEL_IS_VERBOSE(i915_modparams.guc_log_level)),
 
GUC_LOG_LEVEL_TO_VERBOSITY(i915_modparams.guc_log_level));
 
+   /* HAX: Never allow GuC submission */
+   i915_modparams.enable_guc &= ~ENABLE_GUC_SUBMISSION;
+
/* Make sure that sanitization was done */
GEM_BUG_ON(i915_modparams.enable_guc < 0);
GEM_BUG_ON(i915_modparams.guc_log_level < 0);
-- 
1.9.1

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Re: [Intel-gfx] [PATCH 1/3] drm: Add support for device_id based detection.

[Jani Nikula]

On Mon, 10 Sep 2018, "Lee, Shawn C"  wrote:
> DP quirk list just compare sink or branch device's OUI so far.
> That means particular vendor's products will be applied specific
> change. This change would confirm device_id the same or not.
> Then driver can implement some changes for branch/sink device
> that really need additional WA.
>
> Cc: Jani Nikula 
> Cc: Cooper Chiou 
> Cc: Matt Atwood 
> Cc: Maarten Lankhorst 
> Cc: Dhinakaran Pandiyan 
> Cc: Clint Taylor 
> Signed-off-by: Lee, Shawn C 
> ---
>  drivers/gpu/drm/drm_dp_helper.c | 15 ++-
>  1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 0cccbcb2d03e..22753928af41 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1256,15 +1256,20 @@ EXPORT_SYMBOL(drm_dp_stop_crc);
>  
>  struct dpcd_quirk {
>   u8 oui[3];
> + u8 device_id[6];
>   bool is_branch;
>   u32 quirks;
>  };
>  
>  #define OUI(first, second, third) { (first), (second), (third) }
> +#define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
> + { (first), (second), (third), (fourth), (fifth), (sixth) }
> +
> +#define DEVICE_ID_ANYDEVICE_ID(0, 0, 0, 0, 0, 0)
>  
>  static const struct dpcd_quirk dpcd_quirk_list[] = {
>   /* Analogix 7737 needs reduced M and N at HBR2 link rates */
> - { OUI(0x00, 0x22, 0xb9), true, BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
> + { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, 
> BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
>  };
>  
>  #undef OUI
> @@ -1283,6 +1288,7 @@ drm_dp_get_quirks(const struct drm_dp_dpcd_ident 
> *ident, bool is_branch)
>   const struct dpcd_quirk *quirk;
>   u32 quirks = 0;
>   int i;
> + u8 any_device[6] = DEVICE_ID_ANY;

Please make that any_device[] without the size.

>  
>   for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
>   quirk = &dpcd_quirk_list[i];
> @@ -1293,12 +1299,19 @@ drm_dp_get_quirks(const struct drm_dp_dpcd_ident 
> *ident, bool is_branch)
>   if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
>   continue;
>  
> + if (memcmp(quirk->device_id, any_device, 6) != 0 &&
> + memcmp(quirk->device_id, ident->device_id, 6) != 0)

Please use sizeof instead of hard coded 6.

With those changes,

Reviewed-by: Jani Nikula 



> + continue;
> +
>   quirks |= quirk->quirks;
>   }
>  
>   return quirks;
>  }
>  
> +#undef DEVICE_ID_ANY
> +#undef DEVICE_ID
> +
>  /**
>   * drm_dp_read_desc - read sink/branch descriptor from DPCD
>   * @aux: DisplayPort AUX channel

-- 
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Re: [Intel-gfx] [PATCH 2/3] drm: Change limited M/N quirk to constant N quirk.

[Jani Nikula]

On Mon, 10 Sep 2018, "Lee, Shawn C"  wrote:
> Some DP dongles in particular seem to be fussy about too large
> link M/N values. Set specific value for N divider can resolve
> this issue per dongle vendor's comment. So configure N as
> constant value (0x8000) to instead of reduce M/N formula when
> specific DP dongle connected.
>
> Cc: Jani Nikula 
> Cc: Cooper Chiou 
> Cc: Matt Atwood 
> Cc: Maarten Lankhorst 
> Cc: Dhinakaran Pandiyan 
> Cc: Clint Taylor 
> Signed-off-by: Lee, Shawn C 
> ---
>  drivers/gpu/drm/drm_dp_helper.c  |  2 +-
>  drivers/gpu/drm/i915/intel_display.c | 26 +++---
>  drivers/gpu/drm/i915/intel_display.h |  2 +-
>  drivers/gpu/drm/i915/intel_dp.c  |  8 
>  drivers/gpu/drm/i915/intel_dp_mst.c  |  6 +++---
>  include/drm/drm_dp_helper.h  |  6 +++---
>  6 files changed, 23 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 22753928af41..d0c1250975ab 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1269,7 +1269,7 @@ struct dpcd_quirk {
>  
>  static const struct dpcd_quirk dpcd_quirk_list[] = {
>   /* Analogix 7737 needs reduced M and N at HBR2 link rates */
> - { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, 
> BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
> + { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, 
> BIT(DP_DPCD_QUIRK_CONSTANT_N) },
>  };
>  
>  #undef OUI
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index ec3e24f07486..b26f4ae60810 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6680,22 +6680,18 @@ intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
>  
>  static void compute_m_n(unsigned int m, unsigned int n,
>   uint32_t *ret_m, uint32_t *ret_n,
> - bool reduce_m_n)
> + bool constant_n)
>  {
>   /*
> -  * Reduce M/N as much as possible without loss in precision. Several DP
> -  * dongles in particular seem to be fussy about too large *link* M/N
> -  * values. The passed in values are more likely to have the least
> -  * significant bits zero than M after rounding below, so do this first.
> +  * Several DP dongles in particular seem to be fussy about
> +  * too large *link* M/N * values. Give N value as 0x8000
^
Extra *.

> +  * that should be acceptable by specific devices.

Please also add something like:

0x8000 is the specified fixed N value for asynchronous clock
mode, which the devices expect also in synchronous clock mode.


>*/
> - if (reduce_m_n) {
> - while ((m & 1) == 0 && (n & 1) == 0) {
> - m >>= 1;
> - n >>= 1;
> - }
> - }
> + if (constant_n)
> + *ret_n = 0x8000;
> + else
> + *ret_n = min_t(unsigned int, roundup_pow_of_two(n), 
> DATA_LINK_N_MAX);
>  
> - *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
>   *ret_m = div_u64((uint64_t) m * *ret_n, n);
>   intel_reduce_m_n_ratio(ret_m, ret_n);
>  }
> @@ -6704,18 +6700,18 @@ void
>  intel_link_compute_m_n(int bits_per_pixel, int nlanes,
>  int pixel_clock, int link_clock,
>  struct intel_link_m_n *m_n,
> -bool reduce_m_n)
> +bool constant_n)
>  {
>   m_n->tu = 64;
>  
>   compute_m_n(bits_per_pixel * pixel_clock,
>   link_clock * nlanes * 8,
>   &m_n->gmch_m, &m_n->gmch_n,
> - reduce_m_n);
> + constant_n);
>  
>   compute_m_n(pixel_clock, link_clock,
>   &m_n->link_m, &m_n->link_n,
> - reduce_m_n);
> + constant_n);
>  }
>  
>  static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_display.h 
> b/drivers/gpu/drm/i915/intel_display.h
> index 43f080c6538d..8e8bd5eed2c2 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -379,7 +379,7 @@ struct intel_link_m_n {
>  void intel_link_compute_m_n(int bpp, int nlanes,
>   int pixel_clock, int link_clock,
>   struct intel_link_m_n *m_n,
> - bool reduce_m_n);
> + bool constant_n);
>  
>  bool is_ccs_modifier(u64 modifier);
>  #endif
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 436c22de33b6..fce4be57ccc9 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1998,8 +1998,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>   struct intel_connector *intel_connector = intel_dp->attached_connector;
>   struct intel_digital_connector_state *int

Re: [Intel-gfx] [PATCH 3/3] drm: add LG eDP panel to quirk database

[Jani Nikula]

On Mon, 10 Sep 2018, "Lee, Shawn C"  wrote:
> The N value was computed by kernel driver that based on synchronous clock
> mode. But only specific N value (0x8000) would be acceptable for
> LG LP140WF6-SPM1 eDP panel which is running at asynchronous clock mode.
> With the other N value, Tcon will enter BITS mode and display black screen.
> Add this panel into quirk database and give particular N value when
> calculate M/N divider.
>
> Cc: Jani Nikula 
> Cc: Cooper Chiou 
> Cc: Matt Atwood 
> Cc: Maarten Lankhorst 
> Cc: Dhinakaran Pandiyan 
> Cc: Clint Taylor 
> Signed-off-by: Lee, Shawn C 

No access to the panel or its details, so instead of review,

Acked-by: Jani Nikula 

> ---
>  drivers/gpu/drm/drm_dp_helper.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index d0c1250975ab..0ef7c43a9025 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1270,6 +1270,8 @@ struct dpcd_quirk {
>  static const struct dpcd_quirk dpcd_quirk_list[] = {
>   /* Analogix 7737 needs reduced M and N at HBR2 link rates */
>   { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, 
> BIT(DP_DPCD_QUIRK_CONSTANT_N) },
> + /* LG LP140WF6-SPM1 eDP panel */
> + { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), 
> false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
>  };
>  
>  #undef OUI

-- 
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Re: [Intel-gfx] [PATCH i-g-t] igt/gem_exec_capture: Fix command emission for gen3

[Joonas Lahtinen]

Quoting Chris Wilson (2018-09-09 15:43:08)
> A missing no-op causing us to emit the wrong address when relocation was
> required for BB_START.
> 
> Signed-off-by: Chris Wilson 
> ---
>  tests/gem_exec_capture.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/tests/gem_exec_capture.c b/tests/gem_exec_capture.c
> index 2dc06ce43..9c26e12c9 100644
> --- a/tests/gem_exec_capture.c
> +++ b/tests/gem_exec_capture.c
> @@ -117,7 +117,7 @@ static void __capture(int fd, int dir, unsigned ring, 
> uint32_t target)
> batch[++i] = 0;
> }
> batch[++i] = 0xc0ffee;
> -   if (gen < 3)
> +   if (gen <= 3)

"gen < 4" would be more consistent with the usual checks. One would
assume the evolution of the code to be that this if was added during
development of Gen4 when it's not needed anymore.

Reviewed-by: Joonas Lahtinen 

Regards, Joonas

> batch[++i] = MI_NOOP;
>  
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Re: [Intel-gfx] [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter

[Lisovskiy, Stanislav]

On Tue, 2018-07-10 at 15:10 +0530, Madhav Chauhan wrote:
> This patch set the loadgen select and latency optimization for
> aux and transmit lanes of combo phy transmitters. It will be
> used for MIPI DSI HS operations.
> 
> v2: Rebase
> 
> Signed-off-by: Madhav Chauhan 
> ---
>  drivers/gpu/drm/i915/icl_dsi.c | 38
> ++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c
> b/drivers/gpu/drm/i915/icl_dsi.c
> index 13830e4..a571339 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -105,10 +105,48 @@ static void gen11_dsi_power_up_lanes(struct
> intel_encoder *encoder)
>   }
>  }
>  
> +static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder
> *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder-
> >base);
> + enum port port;
> + u32 tmp;
> + int lane;
> +
> + /* Step 4b(i) set loadgen select for transmit and aux lanes
> */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
> + tmp &= ~LOADGEN_SELECT;
> + I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
> + for (lane = 0; lane <= 3; lane++) {
> + tmp = I915_READ(ICL_PORT_TX_DW4_LN(port,
> lane));
> + tmp &= ~LOADGEN_SELECT;
> + if (lane != 2)
> + tmp |= LOADGEN_SELECT;
> + I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane),
> tmp);
> + }
> + }
> +
> + /* Step 4b(ii) set latency optimization for transmit and aux
> lanes */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
> + tmp &= ~FRC_LATENCY_OPTIM_MASK;
> + tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> + I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
> + tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> + tmp &= ~FRC_LATENCY_OPTIM_MASK;
> + tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> + I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
> + }
> +}
> 

I think bspec states that latency optimization should be set only for
Transmit lanes 0, 1, 3. Is it fine to use a group access(i.e
ICL_PORT_TX_DW2_GRP) here? I think it states also that no latency
optimization is needed for the clock lane.

-- 
Best Regards,

Lisovskiy Stanislav
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Re: [Intel-gfx] [PATCH i-g-t] igt/gem_exec_capture: Fix command emission for gen3

[Ville Syrjälä]

On Sun, Sep 09, 2018 at 01:43:08PM +0100, Chris Wilson wrote:
> A missing no-op causing us to emit the wrong address when relocation was
> required for BB_START.
> 
> Signed-off-by: Chris Wilson 
> ---
>  tests/gem_exec_capture.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/tests/gem_exec_capture.c b/tests/gem_exec_capture.c
> index 2dc06ce43..9c26e12c9 100644
> --- a/tests/gem_exec_capture.c
> +++ b/tests/gem_exec_capture.c
> @@ -117,7 +117,7 @@ static void __capture(int fd, int dir, unsigned ring, 
> uint32_t target)
>   batch[++i] = 0;
>   }
>   batch[++i] = 0xc0ffee;
> - if (gen < 3)
> + if (gen <= 3)
>   batch[++i] = MI_NOOP;

This code is rather well obfuscated. Removing the length from
MI_STORE_DWORD_IMM and just setting it correctly in each branch
would go a long way towards making things more obvious.

>  
>   batch[++i] = MI_BATCH_BUFFER_START; /* not crashed? try again! */
> @@ -144,10 +144,12 @@ static void __capture(int fd, int dir, unsigned ring, 
> uint32_t target)
>   execbuf.flags = ring;
>   if (gen > 3 && gen < 6)
>   execbuf.flags |= I915_EXEC_SECURE;
> +
> + igt_assert(!READ_ONCE(*seqno));
>   gem_execbuf(fd, &execbuf);
>  
>   /* Wait for the request to start */
> - while (*(volatile uint32_t *)seqno != 0xc0ffee)
> + while (READ_ONCE(*seqno) != 0xc0ffee)
>   igt_assert(gem_bo_busy(fd, obj[SCRATCH].handle));
>   munmap(seqno, 4096);
>  
> -- 
> 2.19.0.rc2
> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 1/4] fbdev: Drop FBINFO_CAN_FORCE_OUTPUT flag

[Bartlomiej Zolnierkiewicz]

On 08/22/2018 10:54 AM, Daniel Vetter wrote:
> This was only added for the drm's fbdev emulation support, so that it
> would try harder to show the Oops.
> 
> Unfortunately this never really worked reliably, and in practice ended
> up pushing the real Oops off the screen due to plentyfull locking,
> sleep-while-atomic and other issues. So we removed all that support
> from the fbdev emulation a while back. Aside: We've also removed the
> kgdb support, for similar reasons.
> 
> Since it's such a small patch I figured I don't split this up into the
> usual 3-phase removal.
> 
> Cc: Ben Skeggs 
> Cc: Bartlomiej Zolnierkiewicz 
> Cc: Greg Kroah-Hartman 
> Cc: Hans de Goede 
> Cc: Daniel Vetter 
> Cc: Alexander Kapshuk 
> Cc: Kees Cook 
> Cc: Thierry Reding 
> Cc: David Lechner 
> Cc: nouv...@lists.freedesktop.org
> Cc: linux-fb...@vger.kernel.org
> Signed-off-by: Daniel Vetter 

Acked-by: Bartlomiej Zolnierkiewicz 

Best regards,
--
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Re: [Intel-gfx] [PATCH 3/4] fbdev: Add FBINFO_HIDE_SMEM_START flag

[Bartlomiej Zolnierkiewicz]

On 08/22/2018 10:54 AM, Daniel Vetter wrote:
> DRM drivers really, really, really don't want random userspace to
> share buffer behind it's back, bypassing the dma-buf buffer sharing
> machanism. For that reason we've ruthlessly rejected any IOCTL
> exposing the physical address of any graphics buffer.
> 
> Unfortunately fbdev comes with that built-in. We could just set
> smem_start to 0, but that means we'd have to hand-roll our own fb_mmap
> implementation. For good reasons many drivers do that, but
> smem_start/length is still super convenient.
> 
> Hence instead just stop the leak in the ioctl, to keep fb mmap working
> as-is. A second patch will set this flag for all drm drivers.
> 
> Cc: Bartlomiej Zolnierkiewicz 
> Cc: Kees Cook 
> Cc: Daniel Vetter 
> Cc: linux-fb...@vger.kernel.org
> Signed-off-by: Daniel Vetter 

Acked-by: Bartlomiej Zolnierkiewicz 

Best regards,
--
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[Intel-gfx] [PATCH] drm/i915/ringbuffer: Reload PDs harder on byt/bcs

[Chris Wilson]

Baytrail takes a little more convincing that it needs to actually reload
its Page Directoy (ppGTT) before the context switch, so repeat it until
it gets the message. Once again the arbitrary values here are
empirically derived.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107861
Testcase: igt/gem_exec_parallel/fds
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 23 ---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 472939f5c18f..d0ef50bf930a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1677,9 +1677,26 @@ static int switch_context(struct i915_request *rq)
GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
 
if (ppgtt) {
-   ret = load_pd_dir(rq, ppgtt);
-   if (ret)
-   goto err;
+   int loops;
+
+   /*
+* Baytail takes a little more convincing that it really needs
+* to reload the PD between contexts. It is not just a little
+* longer, as adding more stalls after the load_pd_dir (i.e.
+* adding a long loop around flush_pd_dir) is not as effective
+* as reloading the PD umpteen times. 32 is derived from
+* experimentation (gem_exec_parallel/fds) and has no good
+* explanation.
+*/
+   loops = 1;
+   if (engine->id == BCS && IS_VALLEYVIEW(engine->i915))
+   loops = 32;
+
+   do {
+   ret = load_pd_dir(rq, ppgtt);
+   if (ret)
+   goto err;
+   } while (--loops);
 
if (intel_engine_flag(engine) & ppgtt->pd_dirty_rings) {
unwind_mm = intel_engine_flag(engine);
-- 
2.19.0.rc2

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[Intel-gfx] [PATCH] drm/i915/chv: Update csc coefficient matrix during modeset

[raviraj . p . sitaram]

From: P Raviraj Sitaram 

During modeset, previously configured csc coefficient matrix,if any, will
not persist. This can result in blank screen as csc mode will be programmed
while loading LUT but csc coefficient matrix remains unprogrammed.

Signed-off-by: P Raviraj Sitaram 
---
 drivers/gpu/drm/i915/intel_display.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index b2bab57cd113..5029c0daa994 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6014,6 +6014,9 @@ static void valleyview_crtc_enable(struct 
intel_crtc_state *pipe_config,
 
i9xx_set_pipeconf(intel_crtc);
 
+   if (IS_CHERRYVIEW(dev_priv))
+   intel_color_set_csc(&pipe_config->base);
+
intel_crtc->active = true;
 
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
-- 
2.7.4

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Re: [Intel-gfx] [PATCH 3/6] drm/i915: Limit number of capture objects

[Mika Kuoppala]

Chris Wilson  writes:

> If we fail to allocate an array for a large number of user requested
> capture objects, reduce the array size and try to grab at least some of
> the objects!
>
> Signed-off-by: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/i915_gpu_error.c | 20 +---
>  1 file changed, 13 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index f7f2aa71d8d9..2835cacd0d08 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1365,15 +1365,20 @@ static void request_record_user_bo(struct 
> i915_request *request,
>  {
>   struct i915_capture_list *c;
>   struct drm_i915_error_object **bo;
> - long count;
> + long count, max;
>  
> - count = 0;
> + max = 0;
>   for (c = request->capture_list; c; c = c->next)
> - count++;
> + max++;
> + if (!max)
> + return;
>  
> - bo = NULL;
> - if (count)
> - bo = kcalloc(count, sizeof(*bo), GFP_ATOMIC);
> + bo = kmalloc_array(max, sizeof(*bo), GFP_ATOMIC);

There seems to be no need to zero the array.

> + if (!bo) {
> + /* If we can't capture everything, try to capture something. */
> + max = min_t(long, max, PAGE_SIZE / sizeof(*bo));

Perhaps there is some bookkeeping in slab so this would spill to 2
pages eventually?

Reviewed-by: Mika Kuoppala 

> + bo = kmalloc_array(max, sizeof(*bo), GFP_ATOMIC);
> + }
>   if (!bo)
>   return;
>  
> @@ -1382,7 +1387,8 @@ static void request_record_user_bo(struct i915_request 
> *request,
>   bo[count] = i915_error_object_create(request->i915, c->vma);
>   if (!bo[count])
>   break;
> - count++;
> + if (++count == max)
> + break;
>   }
>  
>   ee->user_bo = bo;
> -- 
> 2.19.0.rc2
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Re: [Intel-gfx] [PATCH 3/6] drm/i915: Limit number of capture objects

[Chris Wilson]

Quoting Mika Kuoppala (2018-09-10 14:14:56)
> Chris Wilson  writes:
> 
> > If we fail to allocate an array for a large number of user requested
> > capture objects, reduce the array size and try to grab at least some of
> > the objects!
> >
> > Signed-off-by: Chris Wilson 
> > ---
> >  drivers/gpu/drm/i915/i915_gpu_error.c | 20 +---
> >  1 file changed, 13 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
> > b/drivers/gpu/drm/i915/i915_gpu_error.c
> > index f7f2aa71d8d9..2835cacd0d08 100644
> > --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> > @@ -1365,15 +1365,20 @@ static void request_record_user_bo(struct 
> > i915_request *request,
> >  {
> >   struct i915_capture_list *c;
> >   struct drm_i915_error_object **bo;
> > - long count;
> > + long count, max;
> >  
> > - count = 0;
> > + max = 0;
> >   for (c = request->capture_list; c; c = c->next)
> > - count++;
> > + max++;
> > + if (!max)
> > + return;
> >  
> > - bo = NULL;
> > - if (count)
> > - bo = kcalloc(count, sizeof(*bo), GFP_ATOMIC);
> > + bo = kmalloc_array(max, sizeof(*bo), GFP_ATOMIC);
> 
> There seems to be no need to zero the array.
> 
> > + if (!bo) {
> > + /* If we can't capture everything, try to capture something. 
> > */
> > + max = min_t(long, max, PAGE_SIZE / sizeof(*bo));
> 
> Perhaps there is some bookkeeping in slab so this would spill to 2
> pages eventually?

Perhaps, my understanding is that kmalloc < 8192 is efficient. It was
more about defining an arbitrary number to try in case the user is
asking for several million captures like the igt did.

We could say halve the number until it allocates, but then we'll
probably just fail latter in capturing pages.

So a page worth of pointers seemed like as good a number as any to use.
We could just capture 1 user buffer, so long as it was the right one ;)
0 just meant the test was a flop (didn't actually test anything other
than the capture malloc failure). What we really need on top of this is
to record when we didn't capture everything :(
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/chv: Update csc coefficient matrix during modeset

[Ville Syrjälä]

On Mon, Sep 10, 2018 at 06:31:22PM +0530, raviraj.p.sita...@intel.com wrote:
> From: P Raviraj Sitaram 
> 
> During modeset, previously configured csc coefficient matrix,if any, will
> not persist. This can result in blank screen as csc mode will be programmed
> while loading LUT but csc coefficient matrix remains unprogrammed.
> 
> Signed-off-by: P Raviraj Sitaram 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index b2bab57cd113..5029c0daa994 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6014,6 +6014,9 @@ static void valleyview_crtc_enable(struct 
> intel_crtc_state *pipe_config,
>  
>   i9xx_set_pipeconf(intel_crtc);
>  
> + if (IS_CHERRYVIEW(dev_priv))
> + intel_color_set_csc(&pipe_config->base);
> +

No need for the platform check.

>   intel_crtc->active = true;
>  
>   intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> -- 
> 2.7.4
> 
> ___
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Re: [Intel-gfx] [PATCH 4/7] drm/i915/perf: lock powergating configuration to default when active

[Tvrtko Ursulin]

On 07/09/2018 10:55, Lionel Landwerlin wrote:

On 07/09/2018 10:39, Tvrtko Ursulin wrote:


On 07/09/2018 10:23, Lionel Landwerlin wrote:

On 07/09/2018 09:26, Tvrtko Ursulin wrote:


On 06/09/2018 11:36, Lionel Landwerlin wrote:

On 06/09/2018 11:22, Chris Wilson wrote:

Quoting Lionel Landwerlin (2018-09-06 11:18:01)

On 06/09/2018 11:10, Chris Wilson wrote:

Quoting Lionel Landwerlin (2018-09-06 10:57:47)

On 05/09/2018 15:22, Tvrtko Ursulin wrote:

From: Lionel Landwerlin 

If some of the contexts submitting workloads to the GPU have been
configured to shutdown slices/subslices, we might loose the NOA
configurations written in the NOA muxes.

One possible solution to this problem is to reprogram the NOA 
muxes

when we switch to a new context. We initially tried this in the
workaround batchbuffer but some concerns where raised about 
the cost
of reprogramming at every context switch. This solution is 
also not
without consequences from the userspace point of view. 
Reprogramming
of the muxes can only happen once the powergating 
configuration has
changed (which happens after context switch). This means for a 
window
of time during the recording, counters recorded by the OA unit 
might
be invalid. This requires userspace dealing with OA reports to 
discard

the invalid values.

Minimizing the reprogramming could be implemented by tracking 
of the
last programmed configuration somewhere in GGTT and use 
MI_PREDICATE
to discard some of the programming commands, but the command 
streamer

would still have to parse all the MI_LRI instructions in the
workaround batchbuffer.

Another solution, which this change implements, is to simply 
disregard
the user requested configuration for the period of time when 
i915/perf
is active. There is no known issue with this apart from a 
performance

penality for some media workloads that benefit from running on a
partially powergated GPU. We already prevent RC6 from 
affecting the
programming so it doesn't sound completely unreasonable to 
hold on

powergating for the same reason.

v2: Leave RPCS programming in intel_lrc.c (Lionel)

v3: Update for s/union intel_sseu/struct intel_sseu/ (Lionel)
   More to_intel_context() (Tvrtko)
   s/dev_priv/i915/ (Tvrtko)

Tvrtko Ursulin:

v4:
    * Rebase for make_rpcs changes.

v5:
    * Apply OA restriction from make_rpcs directly.

v6:
    * Rebase for context image setup changes.

Signed-off-by: Lionel Landwerlin 
Signed-off-by: Tvrtko Ursulin 
---
    drivers/gpu/drm/i915/i915_perf.c |  5 +
    drivers/gpu/drm/i915/intel_lrc.c | 30 
--

    drivers/gpu/drm/i915/intel_lrc.h |  3 +++
    3 files changed, 28 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c 
b/drivers/gpu/drm/i915/i915_perf.c

index ccb20230df2c..dd65b72bddd4 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1677,6 +1677,11 @@ static void 
gen8_update_reg_state_unlocked(struct i915_gem_context *ctx,
    CTX_REG(reg_state, state_offset, flex_regs[i], 
value);

    }
+
+ CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, 
GEN8_R_PWR_CLK_STATE,

+ gen8_make_rpcs(dev_priv,
+ &to_intel_context(ctx,
+ dev_priv->engine[RCS])->sseu));
I think there is one issue I missed on the previous iterations 
of this

patch.

This gen8_update_reg_state_unlocked() is called when the GPU is 
parked

on the kernel context.

It's supposed to update all contexts, but I think we might not 
be able

to update the kernel context image while the GPU is using it.

The kernel context is only ever taken in extremis (you are either
parking or stalling userspace) so I don't care.


The patch exposing the RPCS configuration to userspace will make 
use of
the kernel context while OA/perf is enabled. Even if it 
reprograms the
locked value that will break the power configuration stability on 
Gen11

(because the locked configuration will be different from the kernel
context configuration).

Sure, but as you point out that's only on changing configuration.

What's missing in the patch is that we only bail early if the new 
sseu

matches the ce->sseu, but that doesn't necessarily match whats in the
context due to OA. (Or maybe I missed the conversion to rpcs value 
and

checking.)
-Chris



Yep, because the gen8_make_rpcs() post processes the values store 
at the gem context level, we risk rerunning the kernel context to 
write the exiting value.

Sorry this is all so messy :(


Lets see if I managed to follow here.

The current code indeed bails out at the set ctx param level if the 
requested state matches the ce->state. My thinking was that 
ce->state is the master state and whatever happens in "post 
processing" via gen8_make_rpcs should be hidden from it since the 
design is that the i915_perf.c will re-configure all contexts when 
the OA active status changes (to either direction).


So I don't see a problem in those two interactions.



Let's say you have contextA with 

Re: [Intel-gfx] [PATCH v10 0/8] YCBCR 4:2:0/4:4:4 output support for LSPCON

[Vania Toperich]

tested-by: Vania Toperich 
mailto:va...@bergehenegouwen.com>>


This patch series does the following:
- Adds concept of CRTC output format, which indicates if a CRTC is
  driving RGB/YCBCR4:4:4/YCBCR4:2:0 or other outputs.
- Sets RGB as default output for all displays.
- Enables YCBCR4:4:4/4:2:0 outputs for LSPCON displays
- Drives these outputs on LSPCON using this CRTC output framework.

Sharma, Shashank (2):
  drm/i915: Check LSPCON vendor OUI
  drm/i915: Write AVI infoframes for MCA LSPCON

Shashank Sharma (6):
  drm/i915: Introduce CRTC output format
  drm/i915: Add CRTC output format YCBCR 4:2:0
  drm/i915: Add CRTC output format YCBCR 4:4:4
  drm/i915: Add AVI infoframe support for LSPCON
  drm/i915: Write AVI infoframes for Parade LSPCON
  drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON

 drivers/gpu/drm/i915/i915_reg.h  |   2 +
 drivers/gpu/drm/i915/intel_color.c   |   3 +-
 drivers/gpu/drm/i915/intel_crt.c |   3 +
 drivers/gpu/drm/i915/intel_ddi.c |  28 ++-
 drivers/gpu/drm/i915/intel_display.c | 104 ---
 drivers/gpu/drm/i915/intel_dp.c  |   5 +
 drivers/gpu/drm/i915/intel_dp_mst.c  |   1 +
 drivers/gpu/drm/i915/intel_drv.h |  39 +++-
 drivers/gpu/drm/i915/intel_dvo.c |   1 +
 drivers/gpu/drm/i915/intel_hdmi.c|  24 ++-
 drivers/gpu/drm/i915/intel_lspcon.c  | 348 +--
 drivers/gpu/drm/i915/intel_lvds.c|   2 +
 drivers/gpu/drm/i915/intel_panel.c   |   2 +-
 drivers/gpu/drm/i915/intel_sdvo.c|   1 +
 drivers/gpu/drm/i915/intel_tv.c  |   1 +
 drivers/gpu/drm/i915/vlv_dsi.c   |   1 +
 16 files changed, 507 insertions(+), 58 deletions(-)

--
2.7.4

Vania Toperich
IT Specialist



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T:  , M: +31 6 15097042
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[Intel-gfx] [PATCH v1] drm/i915/chv: Update csc coefficient matrix during modeset

[raviraj . p . sitaram]

From: P Raviraj Sitaram 

During modeset, previously configured csc coefficient matrix,if any, will
not persist. This can result in blank screen as csc mode will be programmed
while loading LUT but csc coefficient matrix remains unprogrammed.

Changes since V1:
- Removed platform check

Signed-off-by: P Raviraj Sitaram 
---
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index b2bab57cd113..2b77d9350a3a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6014,6 +6014,8 @@ static void valleyview_crtc_enable(struct 
intel_crtc_state *pipe_config,
 
i9xx_set_pipeconf(intel_crtc);
 
+   intel_color_set_csc(&pipe_config->base);
+
intel_crtc->active = true;
 
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
-- 
2.7.4

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v2,1/2] drm/i915/guc: Update GuC power domain states

[Patchwork]

== Series Details ==

Series: series starting with [CI,v2,1/2] drm/i915/guc: Update GuC power domain 
states
URL   : https://patchwork.freedesktop.org/series/49423/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d0f85704c2c0 drm/i915/guc: Update GuC power domain states
1ad52148da5f HAX Switch off GuC submission even if explicitly enabled
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

total: 0 errors, 1 warnings, 0 checks, 9 lines checked

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Re: [Intel-gfx] [PATCH v5 01/13] drm/i915/icl: Configure lane sequencing of combo phy transmitter

[Madhav Chauhan]

On 9/10/2018 5:50 PM, Lisovskiy, Stanislav wrote:

On Tue, 2018-07-10 at 15:10 +0530, Madhav Chauhan wrote:

This patch set the loadgen select and latency optimization for
aux and transmit lanes of combo phy transmitters. It will be
used for MIPI DSI HS operations.

v2: Rebase

Signed-off-by: Madhav Chauhan 
---
  drivers/gpu/drm/i915/icl_dsi.c | 38
++
  1 file changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c
b/drivers/gpu/drm/i915/icl_dsi.c
index 13830e4..a571339 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -105,10 +105,48 @@ static void gen11_dsi_power_up_lanes(struct
intel_encoder *encoder)
}
  }
  
+static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder

*encoder)
+{
+   struct drm_i915_private *dev_priv = to_i915(encoder-

base.dev);

+   struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder-

base);

+   enum port port;
+   u32 tmp;
+   int lane;
+
+   /* Step 4b(i) set loadgen select for transmit and aux lanes
*/
+   for_each_dsi_port(port, intel_dsi->ports) {
+   tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
+   tmp &= ~LOADGEN_SELECT;
+   I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
+   for (lane = 0; lane <= 3; lane++) {
+   tmp = I915_READ(ICL_PORT_TX_DW4_LN(port,
lane));
+   tmp &= ~LOADGEN_SELECT;
+   if (lane != 2)
+   tmp |= LOADGEN_SELECT;
+   I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane),
tmp);
+   }
+   }
+
+   /* Step 4b(ii) set latency optimization for transmit and aux
lanes */
+   for_each_dsi_port(port, intel_dsi->ports) {
+   tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
+   tmp &= ~FRC_LATENCY_OPTIM_MASK;
+   tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
+   I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
+   tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
+   tmp &= ~FRC_LATENCY_OPTIM_MASK;
+   tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
+   I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
+   }
+}


I think bspec states that latency optimization should be set only for
Transmit lanes 0, 1, 3. Is it fine to use a group access(i.e
ICL_PORT_TX_DW2_GRP) here? I think it states also that no latency
optimization is needed for the clock lane.


There is a separate comment added in BSPEC :
"The Latency Optimization of the Clock Lane can be either left at it's 
default value ('h0)
or programmed to the same value as the other lanes. If programmed with 
the same
value as the other lanes,  then the Group access can be used for 
PORT_TX_DW2 programming"


Regards,
Madhav





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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,v2,1/2] drm/i915/guc: Update GuC power domain states

[Patchwork]

== Series Details ==

Series: series starting with [CI,v2,1/2] drm/i915/guc: Update GuC power domain 
states
URL   : https://patchwork.freedesktop.org/series/49423/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4792 -> Patchwork_10134 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10134 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10134, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/49423/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10134:

  === IGT changes ===

 Possible regressions 

igt@drv_selftest@live_contexts:
  fi-bsw-n3050:   PASS -> DMESG-WARN


== Known issues ==

  Here are the changes found in Patchwork_10134 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
  fi-skl-guc: PASS -> FAIL (fdo#103191)

igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
  fi-byt-clapper: PASS -> FAIL (fdo#107362)

igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
  fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191)

igt@kms_psr@primary_page_flip:
  fi-cnl-psr: PASS -> FAIL (fdo#107336)


 Possible fixes 

igt@drv_selftest@live_guc:
  fi-skl-guc: DMESG-WARN (fdo#107258) -> PASS
  fi-kbl-guc: DMESG-WARN (fdo#107258) -> PASS

igt@drv_selftest@live_hangcheck:
  fi-skl-guc: FAIL (fdo#107837) -> PASS

igt@kms_frontbuffer_tracking@basic:
  fi-byt-clapper: FAIL (fdo#103167) -> PASS

igt@prime_vgem@basic-fence-flip:
  fi-ilk-650: FAIL (fdo#104008) -> PASS


  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107837 https://bugs.freedesktop.org/show_bug.cgi?id=107837


== Participating hosts (52 -> 47) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4792 -> Patchwork_10134

  CI_DRM_4792: e1d007eb6fbfa346237b7b3a62625e50b3070c71 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4637: 57e3d826dee154cb8664667db7660d854a707fc6 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10134: 1ad52148da5f720ebb994660f92f72850196d8df @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

1ad52148da5f HAX Switch off GuC submission even if explicitly enabled
d0f85704c2c0 drm/i915/guc: Update GuC power domain states

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10134/issues.html
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Re: [Intel-gfx] [CI v2 1/2] drm/i915/guc: Update GuC power domain states

[Chris Wilson]

Quoting Michal Wajdeczko (2018-09-10 11:41:49)
> We should update GuC power domain states also when GuC submission
> is disabled, otherwise GuC might complain or ignore our requests.
> This seems to be required for all currently released GuC firmwares.

Was it expected to fix the live_guc selftest? Might be worth mentioning
Testcase: igt/drv_selftest/live_guc
in that case.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ringbuffer: Reload PDs harder on byt/bcs

[Patchwork]

== Series Details ==

Series: drm/i915/ringbuffer: Reload PDs harder on byt/bcs
URL   : https://patchwork.freedesktop.org/series/49429/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4792 -> Patchwork_10135 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/49429/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10135 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@live_guc:
  fi-cfl-guc: PASS -> DMESG-WARN (fdo#107258)

igt@kms_pipe_crc_basic@read-crc-pipe-b:
  fi-byt-clapper: PASS -> FAIL (fdo#107362)

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927)


 Possible fixes 

igt@drv_selftest@live_hangcheck:
  fi-skl-guc: FAIL (fdo#107837) -> PASS

igt@gem_exec_suspend@basic-s3:
  fi-blb-e6850:   INCOMPLETE (fdo#107718) -> PASS


  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  fdo#107837 https://bugs.freedesktop.org/show_bug.cgi?id=107837


== Participating hosts (52 -> 46) ==

  Missing(6): fi-hsw-4770r fi-ilk-m540 fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-ctg-p8600 


== Build changes ==

* Linux: CI_DRM_4792 -> Patchwork_10135

  CI_DRM_4792: e1d007eb6fbfa346237b7b3a62625e50b3070c71 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4637: 57e3d826dee154cb8664667db7660d854a707fc6 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10135: 3fbcc7f73ddc58e486af5211d4ea6be18aacf9c3 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3fbcc7f73ddc drm/i915/ringbuffer: Reload PDs harder on byt/bcs

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10135/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/chv: Update csc coefficient matrix during modeset (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/chv: Update csc coefficient matrix during modeset (rev2)
URL   : https://patchwork.freedesktop.org/series/49430/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4792 -> Patchwork_10136 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/49430/revisions/2/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10136 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@live_guc:
  fi-cfl-guc: PASS -> DMESG-WARN (fdo#107258)

igt@gem_exec_suspend@basic-s4-devices:
  fi-blb-e6850:   NOTRUN -> INCOMPLETE (fdo#107718)

igt@kms_psr@primary_page_flip:
  fi-cnl-psr: PASS -> FAIL (fdo#107336)


 Possible fixes 

igt@drv_selftest@live_hangcheck:
  fi-skl-guc: FAIL (fdo#107837) -> PASS

igt@gem_exec_suspend@basic-s3:
  fi-blb-e6850:   INCOMPLETE (fdo#107718) -> PASS

igt@prime_vgem@basic-fence-flip:
  fi-ilk-650: FAIL (fdo#104008) -> PASS


  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  fdo#107837 https://bugs.freedesktop.org/show_bug.cgi?id=107837


== Participating hosts (52 -> 47) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4792 -> Patchwork_10136

  CI_DRM_4792: e1d007eb6fbfa346237b7b3a62625e50b3070c71 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4637: 57e3d826dee154cb8664667db7660d854a707fc6 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10136: b424875cce453b5ed6f689942cd123b080c190c7 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

b424875cce45 drm/i915/chv: Update csc coefficient matrix during modeset

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10136/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [CI v2 1/2] drm/i915/guc: Update GuC power domain states

[Srivatsa, Anusha]

>-Original Message-
>From: Wajdeczko, Michal
>Sent: Monday, September 10, 2018 3:42 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Wajdeczko, Michal ; Spotswood, John A
>; Srivatsa, Anusha ;
>Lis, Tomasz ; Ceraolo Spurio, Daniele
>
>Subject: [CI v2 1/2] drm/i915/guc: Update GuC power domain states
>
>We should update GuC power domain states also when GuC submission is
>disabled, otherwise GuC might complain or ignore our requests.
>This seems to be required for all currently released GuC firmwares.
>
>v2: it is only needed by pre-Gen11 firmwares
>
>Signed-off-by: Michal Wajdeczko 
>Cc: John Spotswood 
>Cc: Anusha Srivatsa 
>Cc: Tomasz Lis 
>Cc: Daniele Ceraolo Spurio 
Reviewed-by: Anusha Srivatsa 
>---
> drivers/gpu/drm/i915/intel_uc.c | 4 
> 1 file changed, 4 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
>index 7c95697..b1b3e81 100644
>--- a/drivers/gpu/drm/i915/intel_uc.c
>+++ b/drivers/gpu/drm/i915/intel_uc.c
>@@ -401,6 +401,10 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
>   ret = intel_guc_submission_enable(guc);
>   if (ret)
>   goto err_communication;
>+  } else if (INTEL_GEN(i915) < 11) {
>+  ret = intel_guc_sample_forcewake(guc);
>+  if (ret)
>+  goto err_communication;
>   }
>
>   dev_info(i915->drm.dev, "GuC firmware version %u.%u\n",
>--
>1.9.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/ringbuffer: Reload PDs harder on byt/bcs

[Patchwork]

== Series Details ==

Series: drm/i915/ringbuffer: Reload PDs harder on byt/bcs
URL   : https://patchwork.freedesktop.org/series/49429/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4792_full -> Patchwork_10135_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10135_full that come from known 
issues:

  === IGT changes ===

 Issues hit 

igt@gem_exec_big:
  shard-hsw:  PASS -> INCOMPLETE (fdo#103540)

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-glk:  PASS -> FAIL (fdo#105363)

igt@kms_setmode@basic:
  shard-kbl:  PASS -> FAIL (fdo#99912)


 Possible fixes 

igt@perf@blocking:
  shard-hsw:  FAIL -> PASS


  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4792 -> Patchwork_10135

  CI_DRM_4792: e1d007eb6fbfa346237b7b3a62625e50b3070c71 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4637: 57e3d826dee154cb8664667db7660d854a707fc6 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10135: 3fbcc7f73ddc58e486af5211d4ea6be18aacf9c3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10135/shards.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,v2,1/2] drm/i915/guc: Update GuC power domain states

[Patchwork]

== Series Details ==

Series: series starting with [CI,v2,1/2] drm/i915/guc: Update GuC power domain 
states
URL   : https://patchwork.freedesktop.org/series/49423/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4792 -> Patchwork_10137 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/49423/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10137 that come from known issues:

  === IGT changes ===

 Possible fixes 

igt@drv_selftest@live_guc:
  fi-skl-guc: DMESG-WARN (fdo#107258) -> PASS
  fi-kbl-guc: DMESG-WARN (fdo#107258) -> PASS

igt@drv_selftest@live_hangcheck:
  fi-skl-guc: FAIL (fdo#107837) -> PASS

igt@gem_exec_suspend@basic-s3:
  fi-blb-e6850:   INCOMPLETE (fdo#107718) -> PASS

igt@kms_frontbuffer_tracking@basic:
  fi-byt-clapper: FAIL (fdo#103167) -> PASS

igt@prime_vgem@basic-fence-flip:
  fi-ilk-650: FAIL (fdo#104008) -> PASS


  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  fdo#107837 https://bugs.freedesktop.org/show_bug.cgi?id=107837


== Participating hosts (52 -> 47) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4792 -> Patchwork_10137

  CI_DRM_4792: e1d007eb6fbfa346237b7b3a62625e50b3070c71 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4637: 57e3d826dee154cb8664667db7660d854a707fc6 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10137: aeefdf21ff2a38b6b958b267513dbbf8325dc1da @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

aeefdf21ff2a HAX Switch off GuC submission even if explicitly enabled
d32a07cfbc60 drm/i915/guc: Update GuC power domain states

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10137/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v3)

[Bob Paauwe]

48 bit ppgtt device configuration is really just extended address
range full ppgtt and may actually be something other than 48 bits.

Change USES_FULL_48BIT_PPGTT() to USES_FULL_4LVL_PPGTT() to better
describe that a 4 level walk table extended range PPGTT is being
used. Add a new device info field that specifies the number of
bits to prepare for cases where the range is not 32 or 48 bits.

v2: keep USES_FULL_PPGTT() unchanged (Chris)
v3: Simplify condition in gen8_ppgtt_create() (Chris)
Remove unecessary line coninuations (Bob)
Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)

Signed-off-by: Bob Paauwe 
CC: Rodrigo Vivi 
CC: Michel Thierry 
CC: Chris Wilson 

Additional work to rename 48bit to 4 level

Signed-off-by: Bob Paauwe 
---
 drivers/gpu/drm/i915/gvt/vgpu.c  |  2 +-
 drivers/gpu/drm/i915/i915_drv.h  |  2 +-
 drivers/gpu/drm/i915/i915_gem_context.c  |  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c  | 24 
 drivers/gpu/drm/i915/i915_gem_gtt.h  |  4 ++--
 drivers/gpu/drm/i915/i915_pci.c  |  7 +--
 drivers/gpu/drm/i915/i915_pvinfo.h   |  2 +-
 drivers/gpu/drm/i915/i915_vgpu.c |  4 ++--
 drivers/gpu/drm/i915/i915_vgpu.h |  2 +-
 drivers/gpu/drm/i915/intel_device_info.h |  4 +++-
 drivers/gpu/drm/i915/intel_lrc.c |  8 
 drivers/gpu/drm/i915/selftests/huge_pages.c  |  8 
 drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
 13 files changed, 39 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index a4e8e3cf74fd..52bebd67173a 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
 
-   vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
+   vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_4LVL_PPGTT;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5a4da5b723fd..a367686fd735 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2569,7 +2569,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define USES_PPGTT(dev_priv)   (i915_modparams.enable_ppgtt)
 #define USES_FULL_PPGTT(dev_priv)  (i915_modparams.enable_ppgtt >= 2)
-#define USES_FULL_48BIT_PPGTT(dev_priv)(i915_modparams.enable_ppgtt == 
3)
+#define USES_FULL_4LVL_PPGTT(dev_priv) ((dev_priv)->info.full_ppgtt_bits > 32)
 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
GEM_BUG_ON((sizes) == 0); \
((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index f15a039772db..1add339ca6be 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -249,7 +249,7 @@ static u32 default_desc_template(const struct 
drm_i915_private *i915,
desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
 
address_mode = INTEL_LEGACY_32B_CONTEXT;
-   if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
+   if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
address_mode = INTEL_LEGACY_64B_CONTEXT;
desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index eb0e446d6482..c66bbf409791 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -137,18 +137,18 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private 
*dev_priv,
int enable_ppgtt)
 {
bool has_full_ppgtt;
-   bool has_full_48bit_ppgtt;
+   bool has_full_4lvl_ppgtt;
 
if (!dev_priv->info.has_aliasing_ppgtt)
return 0;
 
has_full_ppgtt = dev_priv->info.has_full_ppgtt;
-   has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
+   has_full_4lvl_ppgtt = USES_FULL_4LVL_PPGTT(dev_priv);
 
if (intel_vgpu_active(dev_priv)) {
/* GVT-g has no support for 32bit ppgtt */
has_full_ppgtt = false;
-   has_full_48bit_ppgtt = 
intel_vgpu_has_full_48bit_ppgtt(dev_priv);
+   has_full_4lvl_ppgtt = intel_vgpu_has_full_4lvl_ppgtt(dev_priv);
}
 
/*
@@ -164,7 +164,7 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private 
*dev_priv,
if (enable_ppgtt == 2 && has_full_ppgtt)
return 2;
 
-   if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
+   if (enable_ppgtt == 3 && has_full_4lvl_ppgtt)
 

Re: [Intel-gfx] [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v3)

[Rodrigo Vivi]

On Mon, Sep 10, 2018 at 10:12:25AM -0700, Bob Paauwe wrote:
1;5202;0c> 48 bit ppgtt device configuration is really just extended address
> range full ppgtt and may actually be something other than 48 bits.
> 
> Change USES_FULL_48BIT_PPGTT() to USES_FULL_4LVL_PPGTT() to better
> describe that a 4 level walk table extended range PPGTT is being
> used. Add a new device info field that specifies the number of
> bits to prepare for cases where the range is not 32 or 48 bits.
> 
> v2: keep USES_FULL_PPGTT() unchanged (Chris)
> v3: Simplify condition in gen8_ppgtt_create() (Chris)
> Remove unecessary line coninuations (Bob)
> Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
> 
> Signed-off-by: Bob Paauwe 
> CC: Rodrigo Vivi 
> CC: Michel Thierry 
> CC: Chris Wilson 
> 
> Additional work to rename 48bit to 4 level

Thanks for the additional work.
Bikeshed on this comment here: Shouldn't this be mentioned on the
"v3" portion directly instead of the middle of tags' block?

> 
> Signed-off-by: Bob Paauwe 
> ---
>  drivers/gpu/drm/i915/gvt/vgpu.c  |  2 +-
>  drivers/gpu/drm/i915/i915_drv.h  |  2 +-
>  drivers/gpu/drm/i915/i915_gem_context.c  |  2 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c  | 24 
> 
>  drivers/gpu/drm/i915/i915_gem_gtt.h  |  4 ++--
>  drivers/gpu/drm/i915/i915_pci.c  |  7 +--
>  drivers/gpu/drm/i915/i915_pvinfo.h   |  2 +-
>  drivers/gpu/drm/i915/i915_vgpu.c |  4 ++--
>  drivers/gpu/drm/i915/i915_vgpu.h |  2 +-
>  drivers/gpu/drm/i915/intel_device_info.h |  4 +++-
>  drivers/gpu/drm/i915/intel_lrc.c |  8 
>  drivers/gpu/drm/i915/selftests/huge_pages.c  |  8 
>  drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
>  13 files changed, 39 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
> index a4e8e3cf74fd..52bebd67173a 100644
> --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> @@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
>   vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
>   vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
>  
> - vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
> + vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_4LVL_PPGTT;
>   vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
>   vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5a4da5b723fd..a367686fd735 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2569,7 +2569,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>  
>  #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt)
>  #define USES_FULL_PPGTT(dev_priv)(i915_modparams.enable_ppgtt >= 2)
> -#define USES_FULL_48BIT_PPGTT(dev_priv)  (i915_modparams.enable_ppgtt == 
> 3)
> +#define USES_FULL_4LVL_PPGTT(dev_priv)   
> ((dev_priv)->info.full_ppgtt_bits > 32)

another bikeshed: FULL_4LVL_PPGTT or just 4LVL_PPGTT?

>  #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
>   GEM_BUG_ON((sizes) == 0); \
>   ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index f15a039772db..1add339ca6be 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -249,7 +249,7 @@ static u32 default_desc_template(const struct 
> drm_i915_private *i915,
>   desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
>  
>   address_mode = INTEL_LEGACY_32B_CONTEXT;
> - if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
> + if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
>   address_mode = INTEL_LEGACY_64B_CONTEXT;
>   desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index eb0e446d6482..c66bbf409791 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -137,18 +137,18 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private 
> *dev_priv,
>   int enable_ppgtt)
>  {
>   bool has_full_ppgtt;
> - bool has_full_48bit_ppgtt;
> + bool has_full_4lvl_ppgtt;
>  
>   if (!dev_priv->info.has_aliasing_ppgtt)
>   return 0;
>  
>   has_full_ppgtt = dev_priv->info.has_full_ppgtt;
> - has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
> + has_full_4lvl_ppgtt = USES_FULL_4LVL_PPGTT(dev_priv);
>  
>   if (intel_vgpu_active(dev_priv)) {
>   /* GVT-g has no support for 32bit ppgtt */
>   has_full_ppgtt = false;
> - has_full_48bit

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/chv: Update csc coefficient matrix during modeset (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/chv: Update csc coefficient matrix during modeset (rev2)
URL   : https://patchwork.freedesktop.org/series/49430/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4792_full -> Patchwork_10136_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10136_full that come from known 
issues:

  === IGT changes ===

 Issues hit 

igt@gem_ctx_isolation@bcs0-s3:
  shard-kbl:  PASS -> INCOMPLETE (fdo#103665)

igt@kms_setmode@basic:
  shard-apl:  PASS -> FAIL (fdo#99912)
  shard-kbl:  PASS -> FAIL (fdo#99912)


 Possible fixes 

igt@gem_exec_flush@basic-uc-pro-default:
  shard-snb:  INCOMPLETE (fdo#105411) -> PASS

igt@perf@blocking:
  shard-hsw:  FAIL -> PASS


  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4792 -> Patchwork_10136

  CI_DRM_4792: e1d007eb6fbfa346237b7b3a62625e50b3070c71 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4637: 57e3d826dee154cb8664667db7660d854a707fc6 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10136: b424875cce453b5ed6f689942cd123b080c190c7 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10136/shards.html
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Rename full ppgtt configuration to be more generic (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic (rev3)
URL   : https://patchwork.freedesktop.org/series/49021/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
4c677e951cdc drm/i915: Make 48bit full ppgtt configuration generic (v3)
-:16: WARNING:TYPO_SPELLING: 'unecessary' may be misspelled - perhaps 
'unnecessary'?
#16: 
Remove unecessary line coninuations (Bob)

-:26: WARNING:BAD_SIGN_OFF: Duplicate signature
#26: 
Signed-off-by: Bob Paauwe 

total: 0 errors, 2 warnings, 0 checks, 255 lines checked

___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Rename full ppgtt configuration to be more generic (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic (rev3)
URL   : https://patchwork.freedesktop.org/series/49021/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: Make 48bit full ppgtt configuration generic (v3)
+drivers/gpu/drm/i915/i915_gem_gtt.c:1652:35: warning: expression using 
sizeof(void)

___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Rename full ppgtt configuration to be more generic (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Rename full ppgtt configuration to be more generic (rev3)
URL   : https://patchwork.freedesktop.org/series/49021/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4793 -> Patchwork_10138 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10138 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10138, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/49021/revisions/3/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10138:

  === IGT changes ===

 Possible regressions 

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  fi-icl-u:   PASS -> INCOMPLETE


 Warnings 

igt@pm_rpm@module-reload:
  fi-hsw-4770r:   PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_10138 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_module_reload@basic-reload-inject:
  fi-hsw-4770r:   PASS -> DMESG-WARN (fdo#107425)

igt@drv_selftest@live_guc:
  fi-skl-guc: NOTRUN -> DMESG-WARN (fdo#107258)

igt@gem_exec_suspend@basic-s4-devices:
  fi-blb-e6850:   PASS -> INCOMPLETE (fdo#107718)


 Possible fixes 

igt@kms_psr@primary_page_flip:
  fi-whl-u:   FAIL (fdo#107336) -> PASS


  fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
  fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718


== Participating hosts (51 -> 46) ==

  Additional (1): fi-skl-guc 
  Missing(6): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-ctg-p8600 


== Build changes ==

* Linux: CI_DRM_4793 -> Patchwork_10138

  CI_DRM_4793: 8c3078ff800467d16aea5622b2fa325826d167c2 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4637: 57e3d826dee154cb8664667db7660d854a707fc6 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10138: 4c677e951cdc744cbc43b7c1fbbc32561c53bab3 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4c677e951cdc drm/i915: Make 48bit full ppgtt configuration generic (v3)

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10138/issues.html
___
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Re: [Intel-gfx] [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v3)

[Bob Paauwe]

On Mon, 10 Sep 2018 10:32:42 -0700
Rodrigo Vivi  wrote:

> On Mon, Sep 10, 2018 at 10:12:25AM -0700, Bob Paauwe wrote:
> 1;5202;0c> 48 bit ppgtt device configuration is really just extended address
> > range full ppgtt and may actually be something other than 48 bits.
> > 
> > Change USES_FULL_48BIT_PPGTT() to USES_FULL_4LVL_PPGTT() to better
> > describe that a 4 level walk table extended range PPGTT is being
> > used. Add a new device info field that specifies the number of
> > bits to prepare for cases where the range is not 32 or 48 bits.
> > 
> > v2: keep USES_FULL_PPGTT() unchanged (Chris)
> > v3: Simplify condition in gen8_ppgtt_create() (Chris)
> > Remove unecessary line coninuations (Bob)
> > Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
> > 
> > Signed-off-by: Bob Paauwe 
> > CC: Rodrigo Vivi 
> > CC: Michel Thierry 
> > CC: Chris Wilson 
> > 
> > Additional work to rename 48bit to 4 level  
> 
> Thanks for the additional work.
> Bikeshed on this comment here: Shouldn't this be mentioned on the
> "v3" portion directly instead of the middle of tags' block?

Oops, that was just a rebase squash failure on my part and shouldn't be
there at all. 

> 
> > 
> > Signed-off-by: Bob Paauwe 
> > ---
> >  drivers/gpu/drm/i915/gvt/vgpu.c  |  2 +-
> >  drivers/gpu/drm/i915/i915_drv.h  |  2 +-
> >  drivers/gpu/drm/i915/i915_gem_context.c  |  2 +-
> >  drivers/gpu/drm/i915/i915_gem_gtt.c  | 24 
> > 
> >  drivers/gpu/drm/i915/i915_gem_gtt.h  |  4 ++--
> >  drivers/gpu/drm/i915/i915_pci.c  |  7 +--
> >  drivers/gpu/drm/i915/i915_pvinfo.h   |  2 +-
> >  drivers/gpu/drm/i915/i915_vgpu.c |  4 ++--
> >  drivers/gpu/drm/i915/i915_vgpu.h |  2 +-
> >  drivers/gpu/drm/i915/intel_device_info.h |  4 +++-
> >  drivers/gpu/drm/i915/intel_lrc.c |  8 
> >  drivers/gpu/drm/i915/selftests/huge_pages.c  |  8 
> >  drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
> >  13 files changed, 39 insertions(+), 32 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c 
> > b/drivers/gpu/drm/i915/gvt/vgpu.c
> > index a4e8e3cf74fd..52bebd67173a 100644
> > --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> > +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> > @@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
> > vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
> > vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
> >  
> > -   vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
> > +   vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_4LVL_PPGTT;
> > vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
> > vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 5a4da5b723fd..a367686fd735 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2569,7 +2569,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> >  
> >  #define USES_PPGTT(dev_priv)   (i915_modparams.enable_ppgtt)
> >  #define USES_FULL_PPGTT(dev_priv)  (i915_modparams.enable_ppgtt >= 2)
> > -#define USES_FULL_48BIT_PPGTT(dev_priv)(i915_modparams.enable_ppgtt == 
> > 3)
> > +#define USES_FULL_4LVL_PPGTT(dev_priv) 
> > ((dev_priv)->info.full_ppgtt_bits > 32)  
> 
> another bikeshed: FULL_4LVL_PPGTT or just 4LVL_PPGTT?

I don't have any strong opinion here but can see that "FULL" is a bit
redundant when thinking of this an option/enhancement to FULL_PPGTT.

> 
> >  #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
> > GEM_BUG_ON((sizes) == 0); \
> > ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
> > b/drivers/gpu/drm/i915/i915_gem_context.c
> > index f15a039772db..1add339ca6be 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > @@ -249,7 +249,7 @@ static u32 default_desc_template(const struct 
> > drm_i915_private *i915,
> > desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
> >  
> > address_mode = INTEL_LEGACY_32B_CONTEXT;
> > -   if (ppgtt && i915_vm_is_48bit(&ppgtt->vm))
> > +   if (ppgtt && i915_vm_is_4lvl(&ppgtt->vm))
> > address_mode = INTEL_LEGACY_64B_CONTEXT;
> > desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> > b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index eb0e446d6482..c66bbf409791 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -137,18 +137,18 @@ int intel_sanitize_enable_ppgtt(struct 
> > drm_i915_private *dev_priv,
> > int enable_ppgtt)
> >  {
> > bool has_full_ppgtt;
> > -   bool has_full_48bit_ppgtt;
> > +   b

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,v2,1/2] drm/i915/guc: Update GuC power domain states

[Patchwork]

== Series Details ==

Series: series starting with [CI,v2,1/2] drm/i915/guc: Update GuC power domain 
states
URL   : https://patchwork.freedesktop.org/series/49423/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4792_full -> Patchwork_10137_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10137_full that come from known 
issues:

  === IGT changes ===

 Issues hit 

igt@gem_ctx_isolation@bcs0-s3:
  shard-kbl:  PASS -> INCOMPLETE (fdo#103665)

igt@kms_flip@2x-flip-vs-expired-vblank:
  shard-glk:  PASS -> FAIL (fdo#105363)

igt@kms_setmode@basic:
  shard-kbl:  PASS -> FAIL (fdo#99912)


 Possible fixes 

igt@perf@blocking:
  shard-hsw:  FAIL -> PASS


  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4792 -> Patchwork_10137

  CI_DRM_4792: e1d007eb6fbfa346237b7b3a62625e50b3070c71 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4637: 57e3d826dee154cb8664667db7660d854a707fc6 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10137: aeefdf21ff2a38b6b958b267513dbbf8325dc1da @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10137/shards.html
___
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[Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

[Anusha Srivatsa]

From: Animesh Manna 

ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
DC5/6 when appropriate.

v2: (James Ausmus)
 - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
   i915_drm_suspend_early
 - Add DC9 to gen9_dc_mask for ICL
 - Re-order GEN checks for newest platform first
 - Use INTEL_GEN instead of INTEL_INFO->gen
 - Use INTEL_GEN >= 11 instead of IS_ICELAKE
 - Consolidate GEN checks

v3: (James Ausmus)
 - Also allow DC6 for ICL (Imre, Art)
 - Simplify !(GEN >= 11) to GEN < 11 (Imre)

v4: (James Ausmus)
 - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
   PPS regs are Always On
 - Rebase against upstream changes

v5: (Anusha Srivatsa)
- rebased against the latest upstream changes.

Cc: Imre Deak 
Cc: Rodrigo Vivi 
Signed-off-by: Animesh Manna 
Signed-off-by: James Ausmus 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/i915_drv.c | 20 +++---
 drivers/gpu/drm/i915/intel_drv.h|  3 +++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 27 +++--
 3 files changed, 36 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5dd7fc582e6f..2b1c1b9e0077 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1855,7 +1855,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
 
intel_uncore_resume_early(dev_priv);
 
-   if (IS_GEN9_LP(dev_priv)) {
+   if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
gen9_sanitize_dc_state(dev_priv);
bxt_disable_dc9(dev_priv);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -2622,7 +2622,10 @@ static int intel_runtime_suspend(struct device *kdev)
intel_uncore_suspend(dev_priv);
 
ret = 0;
-   if (IS_GEN9_LP(dev_priv)) {
+   if (IS_ICELAKE(dev_priv)) {
+   icl_display_core_uninit(dev_priv);
+   bxt_enable_dc9(dev_priv);
+   } else if (IS_GEN9_LP(dev_priv)) {
bxt_display_core_uninit(dev_priv);
bxt_enable_dc9(dev_priv);
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
@@ -2707,7 +2710,18 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
-   if (IS_GEN9_LP(dev_priv)) {
+   if (IS_ICELAKE(dev_priv)) {
+   bxt_disable_dc9(dev_priv);
+   icl_display_core_init(dev_priv, true);
+   if (dev_priv->csr.dmc_payload) {
+   if (dev_priv->csr.allowed_dc_mask &
+   DC_STATE_EN_UPTO_DC6)
+   skl_enable_dc6(dev_priv);
+   else if (dev_priv->csr.allowed_dc_mask &
+DC_STATE_EN_UPTO_DC5)
+gen9_enable_dc5(dev_priv);
+   }
+   } else if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
if (dev_priv->csr.dmc_payload &&
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f5731215210a..3a06f58a3459 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1625,6 +1625,7 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv);
 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
 unsigned int skl_cdclk_get_vco(unsigned int freq);
+void skl_enable_dc6(struct drm_i915_private *dev_priv);
 void intel_dp_get_m_n(struct intel_crtc *crtc,
  struct intel_crtc_state *pipe_config);
 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
@@ -1962,6 +1963,8 @@ int intel_power_domains_init(struct drm_i915_private *);
 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
resume);
 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
+void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
+void icl_display_core_uninit(struct drm_i915_private *dev_priv);
 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 480dadb1047b..33ad0b751576 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -551,7 +551,9 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
u32 mask;
 
mask = DC_STATE_EN_UPTO_DC5;
-   if (IS_GEN9_LP(dev_priv))
+   if (INTEL_GEN(dev_priv) >= 11)
+   mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
+   else if (IS_GEN9_LP(dev_priv))
   

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: Enable DC9 as lowest possible state during screen-off

[Patchwork]

== Series Details ==

Series: drm/i915/icl: Enable DC9 as lowest possible state during screen-off
URL   : https://patchwork.freedesktop.org/series/49447/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
aeb4804d1d5b drm/i915/icl: Enable DC9 as lowest possible state during screen-off
-:70: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional 
statements (8, 24)
#70: FILE: drivers/gpu/drm/i915/i915_drv.c:2716:
+   if (dev_priv->csr.dmc_payload) {
+   if (dev_priv->csr.allowed_dc_mask &

-:74: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional 
statements (24, 33)
#74: FILE: drivers/gpu/drm/i915/i915_drv.c:2720:
+   else if (dev_priv->csr.allowed_dc_mask &
[...]
+gen9_enable_dc5(dev_priv);

-:170: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#170: FILE: drivers/gpu/drm/i915/intel_runtime_pm.c:3522:
+void icl_display_core_init(struct drm_i915_private *dev_priv,
  bool resume)

total: 0 errors, 2 warnings, 1 checks, 122 lines checked

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Re: [Intel-gfx] [CI v2 1/2] drm/i915/guc: Update GuC power domain states

[Chris Wilson]

Quoting Srivatsa, Anusha (2018-09-10 17:39:30)
> 
> 
> >-Original Message-
> >From: Wajdeczko, Michal
> >Sent: Monday, September 10, 2018 3:42 AM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Wajdeczko, Michal ; Spotswood, John A
> >; Srivatsa, Anusha ;
> >Lis, Tomasz ; Ceraolo Spurio, Daniele
> >
> >Subject: [CI v2 1/2] drm/i915/guc: Update GuC power domain states
> >
> >We should update GuC power domain states also when GuC submission is
> >disabled, otherwise GuC might complain or ignore our requests.
> >This seems to be required for all currently released GuC firmwares.
> >
> >v2: it is only needed by pre-Gen11 firmwares
> >
> >Signed-off-by: Michal Wajdeczko 
> >Cc: John Spotswood 
> >Cc: Anusha Srivatsa 
> >Cc: Tomasz Lis 
> >Cc: Daniele Ceraolo Spurio 
> Reviewed-by: Anusha Srivatsa 

And pushed. Thanks for the patch and review,
-Chris
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Re: [Intel-gfx] [PATCH v2 09/23] drm/dsc: Define Rate Control values that do not change over configurations

[Manasi Navare]

On Tue, Jul 31, 2018 at 02:07:05PM -0700, Manasi Navare wrote:
> From: "Srivatsa, Anusha" 
> 
> DSC has some Rate Control values that remain constant
> across all configurations. These are as per the DSC
> standard.
> 
> v3:
> * Define them in drm_dsc.h as they are
> DSC constants (Manasi)
> v2:
> * Add DP_DSC_ prefix (Jani Nikula)
> 
> Cc: dri-de...@lists.freedesktop.org
> Cc: Manasi Navare 
> Cc: Jani Nikula 
> Cc: Ville Syrjala 
> Cc: Gaurav K Singh 
> Cc: Harry Wentland 
> Signed-off-by: Anusha Srivatsa 

Tested and double checked the values with DSC spec so
Reviewed-by: Manasi Navare 

> ---
>  include/drm/drm_dsc.h | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
> index eda323d..ebd99d7 100644
> --- a/include/drm/drm_dsc.h
> +++ b/include/drm/drm_dsc.h
> @@ -33,6 +33,12 @@
>  #define DSC_MUX_WORD_SIZE_8_10_BPC   48
>  #define DSC_MUX_WORD_SIZE_12_BPC 64
>  
> +/* DSC Rate Control Constants */
> +#define DSC_RC_MODEL_SIZE_CONST  8192
> +#define DSC_RC_EDGE_FACTOR_CONST 6
> +#define DSC_RC_TGT_OFFSET_HI_CONST   3
> +#define DSC_RC_TGT_OFFSET_LO_CONST   3
> +
>  /* Configuration for a single Rate Control model range */
>  struct dsc_rc_range_parameters {
>   /* Min Quantization Parameters allowed for this range */
> -- 
> 2.7.4
> 
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Re: [Intel-gfx] [PULL] gvt-fixes for 4.19-rc4

[Rodrigo Vivi]

Pulled, thanks!

On Mon, Sep 10, 2018 at 05:22:12PM +0800, Zhenyu Wang wrote:
> 
> Hi,
> 
> Here's more gvt-fixes for 4.19. Most critical one is to fix
> KVM's mm reference when we access guest memory, issue was raised
> by Linus in 
> https://lists.freedesktop.org/archives/intel-gvt-dev/2018-August/004130.html.
> Another one with virtual opregion fix.
> 
> Thanks
> --
> The following changes since commit 54ff01fd0d44b9681615f77c15fe9ea6dfadb501:
> 
>   drm/i915/gvt: Give new born vGPU higher scheduling chance (2018-09-03 
> 14:28:23 +0800)
> 
> are available in the Git repository at:
> 
>   https://github.com/intel/gvt-linux.git tags/gvt-fixes-2018-09-10
> 
> for you to fetch changes up to 792fab2c0d45758ad3d187bd252570d2bb627fa9:
> 
>   drm/i915/gvt: Fix the incorrect length of child_device_config issue 
> (2018-09-06 11:17:38 +0800)
> 
> 
> gvt-fixes-2018-09-10
> 
> - KVM mm access reference fix (Zhenyu)
> - Fix child device config length for virtual opregion (Weinan)
> 
> 
> Weinan Li (1):
>   drm/i915/gvt: Fix the incorrect length of child_device_config issue
> 
> Zhenyu Wang (1):
>   drm/i915/gvt: Fix life cycle reference on KVM mm
> 
>  drivers/gpu/drm/i915/gvt/kvmgt.c| 10 --
>  drivers/gpu/drm/i915/gvt/opregion.c | 20 +---
>  2 files changed, 17 insertions(+), 13 deletions(-)
> 
> -- 
> Open Source Technology Center, Intel ltd.
> 
> $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827


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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/icl: Enable DC9 as lowest possible state during screen-off

[Patchwork]

== Series Details ==

Series: drm/i915/icl: Enable DC9 as lowest possible state during screen-off
URL   : https://patchwork.freedesktop.org/series/49447/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4793 -> Patchwork_10139 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10139 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10139, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/49447/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10139:

  === IGT changes ===

 Possible regressions 

igt@pm_rpm@module-reload:
  fi-skl-6600u:   PASS -> INCOMPLETE


== Known issues ==

  Here are the changes found in Patchwork_10139 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_selftest@live_coherency:
  fi-gdg-551: PASS -> DMESG-FAIL (fdo#107164)

igt@drv_selftest@live_guc:
  fi-skl-guc: NOTRUN -> DMESG-WARN (fdo#107258)

igt@kms_psr@primary_page_flip:
  fi-kbl-7560u:   PASS -> FAIL (fdo#107336)


 Possible fixes 

igt@kms_psr@primary_page_flip:
  fi-whl-u:   FAIL (fdo#107336) -> PASS


  fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164
  fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336


== Participating hosts (51 -> 47) ==

  Additional (1): fi-skl-guc 
  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4793 -> Patchwork_10139

  CI_DRM_4793: 8c3078ff800467d16aea5622b2fa325826d167c2 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4637: 57e3d826dee154cb8664667db7660d854a707fc6 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10139: aeb4804d1d5b7f8d32ba8053086eab944b850415 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

aeb4804d1d5b drm/i915/icl: Enable DC9 as lowest possible state during screen-off

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10139/issues.html
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Re: [Intel-gfx] [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v3)

[Chris Wilson]

Quoting Bob Paauwe (2018-09-10 18:12:25)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d6f7b9fe1d26..e0619952ff52 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -299,6 +299,7 @@ static const struct intel_device_info 
> intel_sandybridge_m_gt2_info = {
> .has_rc6p = 1, \
> .has_aliasing_ppgtt = 1, \
> .has_full_ppgtt = 1, \
> +   .full_ppgtt_bits = 32, \
> GEN_DEFAULT_PIPEOFFSETS, \
> GEN_DEFAULT_PAGE_SIZES, \
> IVB_CURSOR_OFFSETS
> @@ -353,6 +354,7 @@ static const struct intel_device_info 
> intel_valleyview_info = {
> .has_hotplug = 1,
> .has_aliasing_ppgtt = 1,
> .has_full_ppgtt = 1,
> +   .full_ppgtt_bits = 32,
> .has_snoop = true,
> .has_coherent_ggtt = false,
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING,

To be pedant, .bits = 31 for gen6/7.
-Chris
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Re: [Intel-gfx] [PATCH 2/3] drm/i915/dp: Restrict link retrain workaround to external monitors

[Dhinakaran Pandiyan]

On Fri, 2018-09-07 at 22:18 +0300, Ville Syrjälä wrote:
> On Fri, Sep 07, 2018 at 11:31:15AM -0700, Dhinakaran Pandiyan wrote:
> > On Fri, 2018-09-07 at 09:25 -0700, Manasi Navare wrote:
> > > On Fri, Sep 07, 2018 at 05:34:23PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Sep 06, 2018 at 11:21:34PM -0700, Dhinakaran Pandiyan
> > > > wrote:
> > > > > commit '3cf71bc9904d ("drm/i915: Re-apply "Perform link
> > > > > quality
> > > > > check,
> > > > > unconditionally during long pulse"")' applies a work around
> > > > > for
> > > > > monitors
> > > > > that don't signal link loss. Apply this only for external
> > > > > displays as
> > > > > eDP features like PSR when active will have the link turned
> > > > > off
> > > > > and the
> > > > > driver ends up retraining the link seeeing that link is not
> > > > > synchronized.
> > > > > 
> > > > > Cc: Lyude Paul 
> > > > > Cc: Jan-Marek Glogowski 
> > > > > Cc: Ville Syrjälä 
> > > > > Cc: Rodrigo Vivi 
> > > > > References: 3cf71bc9904d ("drm/i915: Re-apply "Perform link
> > > > > quality check, unconditionally during long pulse"")
> > > > > Signed-off-by: Dhinakaran Pandiyan  > > > > .com
> > > > > > 
> > > > > 
> > > > > ---
> > > > >  drivers/gpu/drm/i915/intel_dp.c | 4 +++-
> > > > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > > > b/drivers/gpu/drm/i915/intel_dp.c
> > > > > index befdaa076d8c..c59b2f78f41a 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > > @@ -5072,7 +5072,9 @@ intel_dp_full_detect(struct
> > > > > intel_connector
> > > > > *connector,
> > > > >*/
> > > > >   status = connector_status_disconnected;
> > > > >   goto out;
> > > > > - } else {
> > > > > + }
> > > > > +
> > > > > + if (!intel_dp_is_edp(intel_dp)) {
> > > 
> > > Also what happens when the PSR is not active? We would still need
> > > to
> > > retrain
> > > even on eDP.
> > > eDP tends to get fixed a lot of times during link retraining.
> > > 
> > > Manasi
> > > 
> > > > 
> > > > Hmm. How do things work if we get a short hpd from the sink
> > > > while
> > > > it's
> > > > in PSR link off mode? Won't we try to retrain in that case as
> > > > well?
> > > > 
> > 
> > Looks like short pulse defers retraining to ->detect(), so with
> > this
> > change we end up not retraining.
> 
> Except the ->hotplug() hook will still do the retraining I guess?
> It's a
> bit of a mess now with this getting handled in two places.
> 
Yeah, we'll have to fix shortpulse handling in a separate patch. Link
standby v/s link off also determines how we should handle short pulse
from the sink. A retrain is required if PSR put link in standby and
then it went out of sync.


> > But, we do want to retrain when we get
> > a short pulse for a bad link and the link is expected to be
> > synchronized.
> > 
> > > > >   /*
> > > > >* Check link status in case the link went
> > > > > out
> > > > > of
> > > > >* synchronization and the sink did not tell
> > > > > us.
> > > > > -- 
> > > > > 2.17.1
> > > > 
> > > > -- 
> > > > Ville Syrjälä
> > > > Intel
> > > > ___
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > 
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> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
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Re: [Intel-gfx] [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v3)

[Bob Paauwe]

On Mon, 10 Sep 2018 20:56:51 +0100
Chris Wilson  wrote:

> Quoting Bob Paauwe (2018-09-10 18:12:25)
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c 
> > b/drivers/gpu/drm/i915/i915_pci.c
> > index d6f7b9fe1d26..e0619952ff52 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -299,6 +299,7 @@ static const struct intel_device_info 
> > intel_sandybridge_m_gt2_info = {
> > .has_rc6p = 1, \
> > .has_aliasing_ppgtt = 1, \
> > .has_full_ppgtt = 1, \
> > +   .full_ppgtt_bits = 32, \
> > GEN_DEFAULT_PIPEOFFSETS, \
> > GEN_DEFAULT_PAGE_SIZES, \
> > IVB_CURSOR_OFFSETS
> > @@ -353,6 +354,7 @@ static const struct intel_device_info 
> > intel_valleyview_info = {
> > .has_hotplug = 1,
> > .has_aliasing_ppgtt = 1,
> > .has_full_ppgtt = 1,
> > +   .full_ppgtt_bits = 32,
> > .has_snoop = true,
> > .has_coherent_ggtt = false,
> > .ring_mask = RENDER_RING | BSD_RING | BLT_RING,  
> 
> To be pedant, .bits = 31 for gen6/7.
> -Chris

If I'm reading the code right, these use a different method of setting
the vm.total so won't use the .full_ppgtt_bits.

I don't know enough about this, but would it make sense to modify
gen6_ppgtt_create() to use .full_ppgtt_bits (with it set correctly to
31) or maybe just not set .full_ppgtt_bits for those platforms or set
the value correctly and ignore it for now?

Bob

-- 
--
Bob Paauwe  
bob.j.paa...@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193

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Re: [Intel-gfx] [PATCH] drm/i915: Make 48bit full ppgtt configuration generic (v3)

[Chris Wilson]

Quoting Bob Paauwe (2018-09-10 21:34:00)
> On Mon, 10 Sep 2018 20:56:51 +0100
> Chris Wilson  wrote:
> 
> > Quoting Bob Paauwe (2018-09-10 18:12:25)
> > > diff --git a/drivers/gpu/drm/i915/i915_pci.c 
> > > b/drivers/gpu/drm/i915/i915_pci.c
> > > index d6f7b9fe1d26..e0619952ff52 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -299,6 +299,7 @@ static const struct intel_device_info 
> > > intel_sandybridge_m_gt2_info = {
> > > .has_rc6p = 1, \
> > > .has_aliasing_ppgtt = 1, \
> > > .has_full_ppgtt = 1, \
> > > +   .full_ppgtt_bits = 32, \
> > > GEN_DEFAULT_PIPEOFFSETS, \
> > > GEN_DEFAULT_PAGE_SIZES, \
> > > IVB_CURSOR_OFFSETS
> > > @@ -353,6 +354,7 @@ static const struct intel_device_info 
> > > intel_valleyview_info = {
> > > .has_hotplug = 1,
> > > .has_aliasing_ppgtt = 1,
> > > .has_full_ppgtt = 1,
> > > +   .full_ppgtt_bits = 32,
> > > .has_snoop = true,
> > > .has_coherent_ggtt = false,
> > > .ring_mask = RENDER_RING | BSD_RING | BLT_RING,  
> > 
> > To be pedant, .bits = 31 for gen6/7.
> > -Chris
> 
> If I'm reading the code right, these use a different method of setting
> the vm.total so won't use the .full_ppgtt_bits.
> 
> I don't know enough about this, but would it make sense to modify
> gen6_ppgtt_create() to use .full_ppgtt_bits (with it set correctly to
> 31) or maybe just not set .full_ppgtt_bits for those platforms or set
> the value correctly and ignore it for now?

One of our goals is to remove the differences where none exist...
-Chris
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