Re: [Intel-gfx] [PATCH 08/10] drm/sun4i: Use drm_crtc_mask()
On Tue, Jun 26, 2018 at 10:47:14PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Use drm_crtc_mask() where appropriate. > > Cc: Maxime Ripard > Signed-off-by: Ville Syrjälä Acked-by: Maxime Ripard Maxime -- Maxime Ripard, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC PATCH] mm, oom: distinguish blockable mode for mmu notifiers
This is the v2 of RFC based on the feedback I've received so far. The code even compiles as a bonus ;) I haven't runtime tested it yet, mostly because I have no idea how. Any further feedback is highly appreciated of course. --- From ec9a7241bf422b908532c4c33953b0da2655ad05 Mon Sep 17 00:00:00 2001 From: Michal Hocko Date: Wed, 20 Jun 2018 15:03:20 +0200 Subject: [PATCH] mm, oom: distinguish blockable mode for mmu notifiers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are several blockable mmu notifiers which might sleep in mmu_notifier_invalidate_range_start and that is a problem for the oom_reaper because it needs to guarantee a forward progress so it cannot depend on any sleepable locks. Currently we simply back off and mark an oom victim with blockable mmu notifiers as done after a short sleep. That can result in selecting a new oom victim prematurely because the previous one still hasn't torn its memory down yet. We can do much better though. Even if mmu notifiers use sleepable locks there is no reason to automatically assume those locks are held. Moreover majority of notifiers only care about a portion of the address space and there is absolutely zero reason to fail when we are unmapping an unrelated range. Many notifiers do really block and wait for HW which is harder to handle and we have to bail out though. This patch handles the low hanging fruid. __mmu_notifier_invalidate_range_start gets a blockable flag and callbacks are not allowed to sleep if the flag is set to false. This is achieved by using trylock instead of the sleepable lock for most callbacks and continue as long as we do not block down the call chain. I think we can improve that even further because there is a common pattern to do a range lookup first and then do something about that. The first part can be done without a sleeping lock in most cases AFAICS. The oom_reaper end then simply retries if there is at least one notifier which couldn't make any progress in !blockable mode. A retry loop is already implemented to wait for the mmap_sem and this is basically the same thing. Changes since rfc v1 - gpu notifiers can sleep while waiting for HW (evict_process_queues_cpsch on a lock and amdgpu_mn_invalidate_node on unbound timeout) make sure we bail out when we have an intersecting range for starter - note that a notifier failed to the log for easier debugging - back off early in ib_umem_notifier_invalidate_range_start if the callback is called - mn_invl_range_start waits for completion down the unmap_grant_pages path so we have to back off early on overlapping ranges Cc: "David (ChunMing) Zhou" Cc: Paolo Bonzini Cc: "Radim Krčmář" Cc: Alex Deucher Cc: "Christian König" Cc: David Airlie Cc: Jani Nikula Cc: Joonas Lahtinen Cc: Rodrigo Vivi Cc: Doug Ledford Cc: Jason Gunthorpe Cc: Mike Marciniszyn Cc: Dennis Dalessandro Cc: Sudeep Dutt Cc: Ashutosh Dixit Cc: Dimitri Sivanich Cc: Boris Ostrovsky Cc: Juergen Gross Cc: "Jérôme Glisse" Cc: Andrea Arcangeli Cc: Felix Kuehling Cc: k...@vger.kernel.org (open list:KERNEL VIRTUAL MACHINE FOR X86 (KVM/x86)) Cc: linux-ker...@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)) Cc: amd-...@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS) Cc: dri-de...@lists.freedesktop.org (open list:DRM DRIVERS) Cc: intel-gfx@lists.freedesktop.org (open list:INTEL DRM DRIVERS (excluding Poulsbo, Moorestow...) Cc: linux-r...@vger.kernel.org (open list:INFINIBAND SUBSYSTEM) Cc: xen-de...@lists.xenproject.org (moderated list:XEN HYPERVISOR INTERFACE) Cc: linux...@kvack.org (open list:HMM - Heterogeneous Memory Management) Reported-by: David Rientjes Signed-off-by: Michal Hocko --- arch/x86/kvm/x86.c | 7 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 43 +++- drivers/gpu/drm/i915/i915_gem_userptr.c | 13 ++-- drivers/gpu/drm/radeon/radeon_mn.c | 22 +++-- drivers/infiniband/core/umem_odp.c | 33 +++ drivers/infiniband/hw/hfi1/mmu_rb.c | 11 --- drivers/infiniband/hw/mlx5/odp.c| 2 +- drivers/misc/mic/scif/scif_dma.c| 7 ++-- drivers/misc/sgi-gru/grutlbpurge.c | 7 ++-- drivers/xen/gntdev.c| 44 - include/linux/kvm_host.h| 4 +-- include/linux/mmu_notifier.h| 35 +++- include/linux/oom.h | 2 +- include/rdma/ib_umem_odp.h | 3 +- mm/hmm.c| 7 ++-- mm/mmap.c | 2 +- mm/mmu_notifier.c | 19 --- mm/oom_kill.c | 29 virt/kvm/kvm_main.c | 15 ++--- 19 files changed, 225 insertions(+), 80 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 6bcecc325e7e..ac08f5d711be 100644 --- a/arch/x86/kvm/x86
Re: [Intel-gfx] [PATCH 06/10] drm/imx: Use drm_plane_mask()
On Tue, 2018-06-26 at 22:47 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use drm_plane_mask() where appropriate.
>
> Cc: Philipp Zabel
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/imx/ipuv3-crtc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c
> b/drivers/gpu/drm/imx/ipuv3-crtc.c
> index e83af0f2be86..21d002859ae0 100644
> --- a/drivers/gpu/drm/imx/ipuv3-crtc.c
> +++ b/drivers/gpu/drm/imx/ipuv3-crtc.c
> @@ -213,7 +213,7 @@ static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
> static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
>struct drm_crtc_state *state)
> {
> - u32 primary_plane_mask = 1 << drm_plane_index(crtc->primary);
> + u32 primary_plane_mask = drm_plane_mask(crtc->primary);
>
> if (state->active && (primary_plane_mask & state->plane_mask) == 0)
> return -EINVAL;
Acked-by: Philipp Zabel
regards
Philipp
___
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[Intel-gfx] [PATCH] drm/i915/psr: Add psr1 live status
From: Vathsala Nagaraju
Prints live state of psr1.Extending the existing
PSR2 live state function to cover psr1.
Tested on KBL with psr2 and psr1 panel.
v2: rebase
v3: DK
Rename psr2_live_status to psr_source_status.
v4: DK
Move EDP_PSR_STATUS_STATE_SHIFT below EDP_PSR_STATUS_STATE_MASK.
Pass seq to psr_source_status, handle source status prints in
psr_source_status.
v5: Fixed CI warning messages
v6:
Remove extra space in the title before the colon.(DK)
Rebase. (Jani)
v7: Use tabs for indenting the values.(Jani)
v8: Addressed dk's review comments.
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: Vathsala Nagaraju
---
drivers/gpu/drm/i915/i915_debugfs.c | 72 -
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 49 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index c400f42..14e4d6c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2597,27 +2597,55 @@ static int i915_guc_log_relay_release(struct inode
*inode, struct file *file)
.release = i915_guc_log_relay_release,
};
-static const char *psr2_live_status(u32 val)
-{
- static const char * const live_status[] = {
- "IDLE",
- "CAPTURE",
- "CAPTURE_FS",
- "SLEEP",
- "BUFON_FW",
- "ML_UP",
- "SU_STANDBY",
- "FAST_SLEEP",
- "DEEP_SLEEP",
- "BUF_ON",
- "TG_ON"
- };
+static void
+psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m)
+{
+ u32 val, psr_status;
- val = (val & EDP_PSR2_STATUS_STATE_MASK) >> EDP_PSR2_STATUS_STATE_SHIFT;
- if (val < ARRAY_SIZE(live_status))
- return live_status[val];
+ if (dev_priv->psr.psr2_enabled) {
+ static const char * const live_status[] = {
+ "IDLE",
+ "CAPTURE",
+ "CAPTURE_FS",
+ "SLEEP",
+ "BUFON_FW",
+ "ML_UP",
+ "SU_STANDBY",
+ "FAST_SLEEP",
+ "DEEP_SLEEP",
+ "BUF_ON",
+ "TG_ON"
+ };
+ psr_status = I915_READ(EDP_PSR2_STATUS);
+ val = (psr_status & EDP_PSR2_STATUS_STATE_MASK) >>
+ EDP_PSR2_STATUS_STATE_SHIFT;
+ if (val < ARRAY_SIZE(live_status)) {
+ seq_printf(m, "Source PSR status: 0x%x [%s]\n",
+ psr_status, live_status[val]);
+ return;
+ }
+ } else {
+ static const char * const live_status[] = {
+ "IDLE",
+ "SRDONACK",
+ "SRDENT",
+ "BUFOFF",
+ "BUFON",
+ "AUXACK",
+ "SRDOFFACK",
+ "SRDENT_ON",
+ };
+ psr_status = I915_READ(EDP_PSR_STATUS);
+ val = (psr_status & EDP_PSR_STATUS_STATE_MASK) >>
+ EDP_PSR_STATUS_STATE_SHIFT;
+ if (val < ARRAY_SIZE(live_status)) {
+ seq_printf(m, "Source PSR status: 0x%x [%s]\n",
+ psr_status, live_status[val]);
+ return;
+ }
+ }
- return "unknown";
+ seq_printf(m, "Source PSR status: 0x%x [%s]\n", psr_status, "unknown");
}
static const char *psr_sink_status(u8 val)
@@ -2681,12 +2709,8 @@ static int i915_edp_psr_status(struct seq_file *m, void
*data)
seq_printf(m, "Performance_Counter: %u\n", psrperf);
}
- if (dev_priv->psr.psr2_enabled) {
- u32 psr2 = I915_READ(EDP_PSR2_STATUS);
- seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
- psr2, psr2_live_status(psr2));
- }
+ psr_source_status(dev_priv, m);
if (dev_priv->psr.enabled) {
struct drm_dp_aux *aux = &dev_priv->psr.enabled->aux;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 43db91c..f35df07 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4073,6 +4073,7 @@ enum {
#define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base +
0x40)
#define EDP_PSR_STATUS_STATE_MASK(7 << 29)
+#define EDP_PSR_STATUS_STATE_SHIFT 29
#define EDP_PSR_STATUS_STATE_IDLE(0 << 29)
#define EDP_PSR_STATUS_STATE_SRDONACK(1 << 29)
#define EDP_PSR_STATUS_STATE_SRDENT (2 << 29)
--
1.9.1
__
[Intel-gfx] [PATCH v5 00/40] drm/i915: Implement HDCP2.2
The sequence for HDCP2.2 authentication and encryption is implemented in I915. Encoder specific implementations are moved into hdcp_shim. Intel HWs supports HDCP2.2 through ME FW. Hence this series introduces a client driver for mei bus, so that for HDCP2.2 authentication, HDCP2.2 stack in I915 can avail the services from ME FW. DRM_I915 selects INTEL_MEI_HDCP, which selects INTEL_MEI_ME and INTEL_MEI. If we are interested in disabling the MEI_HDCP and MEI Bus then we need an option to disable the HDCP2.2 in I915 (like DRM_I915_HDCP2.2!?). Till then they are binded. Userspace interface remains unchanged as version agnostic. When userspace request for HDCP enable, Kernel will detect the HDCP source and sink's HDCP version(1.4/2.2)capability and enable the best capable version for that combination. This series enables the HDCP2.2 for Type0 content streams. Thanks a lot for Daniel vetter for reviewing v4. Major Changes in v5: - Component is used for I915-MEI HDCP interface [Daniel]. - Patches are restructured for bisecting. - Lookup tables are used for DP and HDMI HDCP2.2 messages [Daniel]. GMBus changes are added here for completeness of the series. They are in review at https://patchwork.freedesktop.org/series/41632/ also. Complete series is hosted at https://github.com/ramalingampc2008/drm-tip.git hdcp2_2_v5 Ramalingam C (39): drm: hdcp2.2 authentication msg definitions drm: HDMI and DP specific HDCP2.2 defines linux/mei: Header for mei_hdcp driver interface drm/i915: wrapping all hdcp var into intel_hdcp drm/i915: Define HDCP2.2 related variables drm/i915: Define Intel HDCP2.2 registers drm/i915: Initialize HDCP2.2 and its MEI interface drm/i915: Schedule hdcp_check_link in _intel_hdcp_enable drm/i915: Pullout the bksv read and validation drm/i915: Enable superior HDCP ver that is capable drm/i915: Enable HDCP1.4 incase of HDCP2.2 failure drm/i915: Implement HDCP2.2 Enable and Disable drm/i915: Enable and Disable HDCP2.2 port encryption drm/i915: Implement HDCP2.2 receiver authentication drm/i915: Implement HDCP2.2 repeater authentication drm/i915: Implement HDCP2.2 link integrity check drm/i915: Handle HDCP2.2 downstream topology change drm/i915: hdcp_check_link only on CP_IRQ drm/i915: Check HDCP 1.4 and 2.2 link on CP_IRQ drm/i915/gmbus: Increase the Bytes per Rd/Wr Op drm/i915/gmbus: Enable burst read drm/i915: Implement the HDCP2.2 support for DP drm/i915: Implement the HDCP2.2 support for HDMI drm/i915: Add HDCP2.2 support for DP connectors drm/i915: Add HDCP2.2 support for HDMI connectors misc/mei/hdcp: Client driver for HDCP application misc/mei/hdcp: Component framework for I915 Interface misc/mei/hdcp: Define ME FW interface for HDCP2.2 misc/mei/hdcp: Initiate Wired HDCP2.2 Tx Session misc/mei/hdcp: Verify Receiver Cert and prepare km misc/mei/hdcp: Verify H_prime misc/mei/hdcp: Store the HDCP Pairing info misc/mei/hdcp: Initiate Locality check misc/mei/hdcp: Verify L_prime misc/mei/hdcp: Prepare Session Key misc/mei/hdcp: Repeater topology verification and ack misc/mei/hdcp: Verify M_prime misc/mei/hdcp: Enabling the HDCP authentication misc/mei/hdcp: Closing wired HDCP2.2 Tx Session Tomas Winkler (1): mei: bus: whitelist hdcp client drivers/gpu/drm/i915/Kconfig |1 + drivers/gpu/drm/i915/i915_drv.h |5 + drivers/gpu/drm/i915/i915_reg.h | 34 + drivers/gpu/drm/i915/intel_display.c |7 +- drivers/gpu/drm/i915/intel_dp.c | 345 - drivers/gpu/drm/i915/intel_drv.h | 88 ++- drivers/gpu/drm/i915/intel_hdcp.c| 1289 -- drivers/gpu/drm/i915/intel_hdmi.c| 190 - drivers/gpu/drm/i915/intel_i2c.c | 71 +- drivers/misc/mei/Kconfig |7 + drivers/misc/mei/Makefile|2 + drivers/misc/mei/bus-fixup.c | 16 + drivers/misc/mei/hdcp/Makefile |6 + drivers/misc/mei/hdcp/mei_hdcp.c | 862 +++ drivers/misc/mei/hdcp/mei_hdcp.h | 408 +++ include/drm/drm_dp_helper.h | 51 ++ include/drm/drm_hdcp.h | 232 ++ include/drm/i915_component.h | 88 +++ include/linux/mei_hdcp.h | 100 +++ 19 files changed, 3710 insertions(+), 92 deletions(-) create mode 100644 drivers/misc/mei/hdcp/Makefile create mode 100644 drivers/misc/mei/hdcp/mei_hdcp.c create mode 100644 drivers/misc/mei/hdcp/mei_hdcp.h create mode 100644 include/linux/mei_hdcp.h -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 02/40] drm: HDMI and DP specific HDCP2.2 defines
This patch adds HDCP register definitions for HDMI and DP HDCP
adaptations.
HDMI specific HDCP2.2 register definitions are added into drm_hdcp.h,
where as HDCP2.2 register offsets in DPCD offsets are defined at
drm_dp_helper.h.
v2:
bit_field definitions are replaced by macros. [Tomas and Jani]
v3:
No Changes.
v4:
Comments style and typos are fixed [Uma]
v5:
Fix for macros.
Signed-off-by: Ramalingam C
---
include/drm/drm_dp_helper.h | 51 +
include/drm/drm_hdcp.h | 30 ++
2 files changed, 81 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index c01564991a9f..17e0889d6aaa 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -904,6 +904,57 @@
#define DP_AUX_HDCP_KSV_FIFO 0x6802C
#define DP_AUX_HDCP_AINFO 0x6803B
+/* DP HDCP2.2 parameter offsets in DPCD address space */
+#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
+#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
+#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
+#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
+#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
+#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET0x69220
+#define DP_HDCP_2_2_REG_EKH_KM_OFFSET 0x692A0
+#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
+#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
+#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
+#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
+#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
+#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET0x69318
+#defineDP_HDCP_2_2_REG_RIV_OFFSET 0x69328
+#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
+#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
+#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
+#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET0x69345
+#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
+#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
+#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
+#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
+#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
+#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET0x69493
+#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
+#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
+
+/* DP HDCP message start offsets in DPCD address space */
+#define DP_HDCP_2_2_AKE_INIT_OFFSETDP_HDCP_2_2_REG_RTX_OFFSET
+#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET
+#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSETDP_HDCP_2_2_REG_EKPUB_KM_OFFSET
+#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_OFFSET
+#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET
+#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
+ DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
+#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET
+#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET
+#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET
DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
+#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET
DP_HDCP_2_2_REG_RXINFO_OFFSET
+#define DP_HDCP_2_2_REP_SEND_ACK_OFFSETDP_HDCP_2_2_REG_V_OFFSET
+#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
+#define DP_HDCP_2_2_REP_STREAM_READY_OFFSETDP_HDCP_2_2_REG_MPRIME_OFFSET
+
+#define HDCP_2_2_DP_RXSTATUS_LEN 1
+#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
+#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x)((x) & BIT(1))
+#define HDCP_2_2_DP_RXSTATUS_PAIRING(x)((x) & BIT(2))
+#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
+#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x)((x) & BIT(4))
+
/* DP 1.2 Sideband message defines */
/* peer device type - DP 1.2a Table 2-92 */
#define DP_PEER_DEVICE_NONE0x0
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index 3e963c5d04b2..2fc6311dc060 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -217,4 +217,34 @@ struct hdcp2_dp_errata_stream_type {
uint8_t stream_type;
} __packed;
+/* HDCP2.2 TIMEOUTs in mSec */
+#define HDCP_2_2_CERT_TIMEOUT 100
+#define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT 1000
+#define HDCP_2_2_HPRIME_PAIRED_TIMEOUT 200
+#define HDCP_2_2_PAIRING_TIMEOUT 200
+#defineHDCP_2_2_HDMI_LPRIME_TIMEOUT20
+#define HDCP_2_2_DP_LPRIME_TIMEOUT 7
+#define HDCP_2_2_RECVID_LIST_TIMEOUT 3000
+#define HDCP_2_2_STREAM_READY_TIMEOUT 100
+
+/* HDMI HDCP2.2 Register Offsets */
+#define HDCP_2_2_HDMI_REG_VER_OFFSET 0x50
+#define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET0x60
+#define
[Intel-gfx] [PATCH v5 01/40] drm: hdcp2.2 authentication msg definitions
This patch defines the hdcp2.2 protocol messages for authentication.
v2:
bit_fields are removed. Instead bitmasking used. [Tomas and Jani]
prefix HDCP_2_2_ is added to the macros. [Tomas]
v3:
No Changes.
v4:
Style and spellings are fixed [Uma]
v5:
Fix for macros.
Signed-off-by: Ramalingam C
---
include/drm/drm_hdcp.h | 179 +
1 file changed, 179 insertions(+)
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index 98e63d870139..3e963c5d04b2 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -38,4 +38,183 @@
#define DRM_HDCP_DDC_BSTATUS 0x41
#define DRM_HDCP_DDC_KSV_FIFO 0x43
+#define DRM_HDCP_1_4_SRM_ID0x8
+#define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3
+#define DRM_HDCP_1_4_DCP_SIG_SIZE 40
+
+/* Protocol message definition for HDCP2.2 specification */
+#define HDCP_STREAM_TYPE0 0x00
+#define HDCP_STREAM_TYPE1 0x01
+
+/* HDCP2.2 Msg IDs */
+#define HDCP_2_2_NULL_MSG 1
+#define HDCP_2_2_AKE_INIT 2
+#define HDCP_2_2_AKE_SEND_CERT 3
+#define HDCP_2_2_AKE_NO_STORED_KM 4
+#define HDCP_2_2_AKE_STORED_KM 5
+#define HDCP_2_2_AKE_SEND_HPRIME 7
+#define HDCP_2_2_AKE_SEND_PAIRING_INFO 8
+#define HDCP_2_2_LC_INIT 9
+#define HDCP_2_2_LC_SEND_LPRIME10
+#define HDCP_2_2_SKE_SEND_EKS 11
+#define HDCP_2_2_REP_SEND_RECVID_LIST 12
+#define HDCP_2_2_REP_SEND_ACK 15
+#define HDCP_2_2_REP_STREAM_MANAGE 16
+#define HDCP_2_2_REP_STREAM_READY 17
+#define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50
+
+#define HDCP_2_2_RTX_LEN 8
+#define HDCP_2_2_RRX_LEN 8
+
+#define HDCP_2_2_K_PUB_RX_MOD_N_LEN128
+#define HDCP_2_2_K_PUB_RX_EXP_E_LEN3
+#define HDCP_2_2_K_PUB_RX_LEN (HDCP_2_2_K_PUB_RX_MOD_N_LEN + \
+HDCP_2_2_K_PUB_RX_EXP_E_LEN)
+
+#define HDCP_2_2_DCP_LLC_SIG_LEN 384
+
+#define HDCP_2_2_E_KPUB_KM_LEN 128
+#define HDCP_2_2_E_KH_KM_M_LEN (16 + 16)
+#define HDCP_2_2_H_PRIME_LEN 32
+#define HDCP_2_2_E_KH_KM_LEN 16
+#define HDCP_2_2_RN_LEN8
+#define HDCP_2_2_L_PRIME_LEN 32
+#define HDCP_2_2_E_DKEY_KS_LEN 16
+#define HDCP_2_2_RIV_LEN 8
+#define HDCP_2_2_SEQ_NUM_LEN 3
+#define HDCP_2_2_LPRIME_HALF_LEN (HDCP_2_2_L_PRIME_LEN / 2)
+#define HDCP_2_2_RECEIVER_ID_LEN DRM_HDCP_KSV_LEN
+#define HDCP_2_2_MAX_DEVICE_COUNT 31
+#define HDCP_2_2_RECEIVER_IDS_MAX_LEN (HDCP_2_2_RECEIVER_ID_LEN * \
+HDCP_2_2_MAX_DEVICE_COUNT)
+#define HDCP_2_2_MPRIME_LEN32
+
+/* Following Macros take a byte at a time for bit(s) masking */
+/*
+ * TODO: This has to be changed for DP MST, as multiple stream on
+ * same port is possible.
+ * For HDCP2.2 on HDMI and DP SST this value is always 1.
+ */
+#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
+#define HDCP_2_2_TXCAP_MASK_LEN2
+#define HDCP_2_2_RXCAPS_LEN3
+#define HDCP_2_2_RX_REPEATER(x)((x) & BIT(0))
+#define HDCP_2_2_DP_HDCP_CAPABLE(x)((x) & BIT(1))
+#define HDCP_2_2_RXINFO_LEN2
+
+/* HDCP1.x compliant device in downstream */
+#define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x) ((x) & BIT(0))
+
+/* HDCP2.0 Compliant repeater in downstream */
+#define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x) ((x) & BIT(1))
+#define HDCP_2_2_MAX_CASCADE_EXCEEDED(x) ((x) & BIT(2))
+#define HDCP_2_2_MAX_DEVS_EXCEEDED(x) ((x) & BIT(3))
+#define HDCP_2_2_DEV_COUNT_LO(x) (((x) & (0xF << 4)) >> 4)
+#define HDCP_2_2_DEV_COUNT_HI(x) ((x) & BIT(0))
+#define HDCP_2_2_DEPTH(x) (((x) & (0x7 << 1)) >> 1)
+
+struct hdcp2_cert_rx {
+ uint8_t receiver_id[HDCP_2_2_RECEIVER_ID_LEN];
+ uint8_t kpub_rx[HDCP_2_2_K_PUB_RX_LEN];
+ uint8_t reserved[2];
+ uint8_t dcp_signature[HDCP_2_2_DCP_LLC_SIG_LEN];
+} __packed;
+
+struct hdcp2_streamid_type {
+ uint8_t stream_id;
+ uint8_t stream_type;
+} __packed;
+
+/*
+ * The TxCaps field specified in the HDCP HDMI, DP specs
+ * This field is big endian as specified in the errata.
+ */
+struct hdcp2_tx_caps {
+ /* Transmitter must set this to 0x2 */
+ uint8_t version;
+
+ /* Reserved for HDCP and DP Spec. Read as Zero */
+ uint8_t tx_cap_mask[HDCP_2_2_TXCAP_MASK_LEN];
+} __packed;
+
+/* Main structures for HDCP2.2 protocol c
[Intel-gfx] [PATCH v5 04/40] linux/mei: Header for mei_hdcp driver interface
Data structures and Enum for the I915-MEI_HDCP interface are defined
at
v2:
Rebased.
v3:
mei_cl_device is removed from mei_hdcp_data [Tomas]
v4:
Comment style and typo fixed [Uma]
v5:
Rebased.
Signed-off-by: Ramalingam C
---
include/linux/mei_hdcp.h | 100 +++
1 file changed, 100 insertions(+)
create mode 100644 include/linux/mei_hdcp.h
diff --git a/include/linux/mei_hdcp.h b/include/linux/mei_hdcp.h
new file mode 100644
index ..f993e389d7cf
--- /dev/null
+++ b/include/linux/mei_hdcp.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright © 2017-2018 Intel Corporation
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission. The copyright holders make no representations
+ * about the suitability of this software for any purpose. It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ *
+ * Authors:
+ * Ramalingam C
+ */
+
+#ifndef _LINUX_MEI_HDCP_H
+#define _LINUX_MEI_HDCP_H
+
+#include
+
+/*
+ * Enumeration of the physical DDI available on the platform
+ */
+enum hdcp_physical_port {
+ INVALID_PORT = 0x00,/* Not a valid port */
+
+ DDI_RANGE_BEGIN = 0x01, /* Beginning of the valid DDI port range */
+ DDI_B = 0x01, /* Port DDI B */
+ DDI_C = 0x02, /* Port DDI C */
+ DDI_D = 0x03, /* Port DDI D */
+ DDI_E = 0x04, /* Port DDI E */
+ DDI_F = 0x05, /* Port DDI F */
+ DDI_A = 0x07, /* Port DDI A */
+ DDI_RANGE_END = DDI_A,/* End of the valid DDI port range */
+};
+
+/* The types of HDCP 2.2 ports supported */
+enum hdcp_integrated_port_type {
+ HDCP_INVALID_TYPE = 0x00,
+
+ /* HDCP 2.x ports that are integrated into Intel HW */
+ INTEGRATED = 0x01,
+
+ /* HDCP2.2 discrete wired Tx port with LSPCON (HDMI 2.0) solution */
+ LSPCON = 0x02,
+
+ /* HDCP2.2 discrete wired Tx port using the CPDP (DP 1.3) solution */
+ CPDP= 0x03,
+};
+
+/*
+ * wired_protocol: Supported integrated wired HDCP protocol.
+ * Based on this value, Minor difference needed between wired specifications
+ * are handled.
+ */
+enum hdcp_protocol {
+ HDCP_PROTOCOL_INVALID,
+ HDCP_PROTOCOL_HDMI,
+ HDCP_PROTOCOL_DP
+};
+
+/*
+ * mei_hdcp_data: Input data to the mei_hdcp APIs.
+ */
+struct mei_hdcp_data {
+ enum hdcp_physical_port port;
+ enum hdcp_integrated_port_type port_type;
+ enum hdcp_protocol protocol;
+
+ /*
+* No of streams transmitted on a port.
+* In case of HDMI & DP SST, single stream will be
+* transmitted on a port.
+*/
+ uint16_t k;
+
+ /*
+* Count of RepeaterAuth_Stream_Manage msg propagated.
+* Initialized to 0 on AKE_INIT. Incremented after every successful
+* transmission of RepeaterAuth_Stream_Manage message. When it rolls
+* over re-Auth has to be triggered.
+*/
+ uint32_t seq_num_m;
+
+ /* k(No of Streams per port) x structure of wired_streamid_type */
+ struct hdcp2_streamid_type *streams;
+};
+
+#endif /* defined (_LINUX_MEI_HDCP_H) */
--
2.7.4
___
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[Intel-gfx] [PATCH v5 06/40] drm/i915: Define HDCP2.2 related variables
For upcoming implementation of HDCP2.2 in I915, important variable
required for HDCP2.2 are defined.
HDCP_shim is extended to support encoder specific HDCP2.2 flows.
v2:
1.4 shim is extended to support hdcp2.2. [Sean Paul]
platform's/panel's hdcp ver capability is removed. [Sean Paul]
mei references in i915_private are moved to later patches. [Chris Wilson]
v3:
mei_cl_device ref is moved into intel_hdcp
v4:
Extra * in comment is removed [Uma]
v5:
No Change.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_drv.h | 61
1 file changed, 61 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index eb480574a92e..b615ea4a44c3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include
#include "i915_drv.h"
#include
@@ -375,6 +376,32 @@ struct intel_hdcp_shim {
/* Detects panel's hdcp capability. This is optional for HDMI. */
int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
bool *hdcp_capable);
+
+ /* Write HDCP2.2 messages */
+ int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port,
+void *buf, size_t size);
+
+ /* Read HDCP2.2 messages */
+ int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port,
+ uint8_t msg_id, void *buf, size_t size);
+
+ /*
+* Implementation of DP HDCP2.2 Errata for the communication of stream
+* type to Receivers. In DP HDCP2.2 Stream type is one of the input to
+* the HDCP2.2 Chiper for En/De-Cryption. Not applicable for HDMI.
+*/
+ int (*config_stream_type)(struct intel_digital_port *intel_dig_port,
+ void *buf, size_t size);
+
+ /* HDCP2.2 Link Integrity Check */
+ int (*check_2_2_link)(struct intel_digital_port *intel_dig_port);
+
+ /* Detects whether Panel is HDCP2.2 capable */
+ int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port,
+ bool *capable);
+
+ /* Detects the HDCP protocol(DP/HDMI) required on the port */
+ enum hdcp_protocol (*hdcp_protocol)(void);
};
struct intel_hdcp {
@@ -384,6 +411,40 @@ struct intel_hdcp {
uint64_t hdcp_value;
struct delayed_work hdcp_check_work;
struct work_struct hdcp_prop_work;
+
+ /* HDCP2.2 related definitions */
+ bool hdcp2_supported;
+
+ /*
+* Content Stream Type defined by content owner. TYPE0(0x0) content can
+* flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
+* content can flow only through a link protected by HDCP2.2.
+*/
+ u8 content_type;
+
+ bool is_paired;
+ bool is_repeater;
+
+ /*
+* Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
+* Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
+* When it rolls over re-auth has to be triggered.
+*/
+ uint32_t seq_num_v;
+
+ /*
+* Count of RepeaterAuth_Stream_Manage msg propagated.
+* Initialized to 0 on AKE_INIT. Incremented after every successful
+* transmission of RepeaterAuth_Stream_Manage message. When it rolls
+* over re-Auth has to be triggered.
+*/
+ uint32_t seq_num_m;
+
+ /* mei interface related information */
+ struct mei_cl_device *cldev;
+ struct mei_hdcp_data mei_data;
+
+ struct delayed_work hdcp2_check_work;
};
struct intel_connector {
--
2.7.4
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for ALSA: hda - Handle pm failure during hotplug
== Series Details ==
Series: ALSA: hda - Handle pm failure during hotplug
URL : https://patchwork.freedesktop.org/series/45463/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c8ac3d11b058 ALSA: hda - Handle pm failure during hotplug
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#13:
References: 222bde03881c ("ALSA: hda - Fix mutex deadlock at HDMI/DP hotplug")
-:13: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 222bde03881c ("ALSA: hda - Fix
mutex deadlock at HDMI/DP hotplug")'
#13:
References: 222bde03881c ("ALSA: hda - Fix mutex deadlock at HDMI/DP hotplug")
total: 1 errors, 1 warnings, 0 checks, 10 lines checked
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[Intel-gfx] [PATCH v5 07/40] drm/i915: Define Intel HDCP2.2 registers
Intel HDCP2.2 registers are defined with addr offsets and bit details.
v2:
Replaced the arith calc with _PICK [Sean Paul]
v3:
No changes.
v4:
%s/HDCP2_CTR_DDI/HDCP2_CTL_DDI [Uma]
v5:
Added parentheses for the parameters of macro.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_reg.h | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index caad19f5f557..822fee56931e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8697,6 +8697,38 @@ enum skl_power_gate {
#define HDCP_STATUS_CIPHERBIT(16)
#define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff)
+/* HDCP2.2 Registers */
+#define _PORTA_HDCP2_BASE 0x66800
+#define _PORTB_HDCP2_BASE 0x66500
+#define _PORTC_HDCP2_BASE 0x66600
+#define _PORTD_HDCP2_BASE 0x66700
+#define _PORTE_HDCP2_BASE 0x66A00
+#define _PORTF_HDCP2_BASE 0x66900
+#define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \
+ _PORTA_HDCP2_BASE, \
+ _PORTB_HDCP2_BASE, \
+ _PORTC_HDCP2_BASE, \
+ _PORTD_HDCP2_BASE, \
+ _PORTE_HDCP2_BASE, \
+ _PORTF_HDCP2_BASE) + (x))
+
+#define HDCP2_AUTH_DDI(port) _PORT_HDCP2_BASE(port, 0x98)
+#define AUTH_LINK_AUTHENTICATED BIT(31)
+#define AUTH_LINK_TYPE BIT(30)
+#define AUTH_FORCE_CLR_INPUTCTR BIT(19)
+#define AUTH_CLR_KEYSBIT(18)
+
+#define HDCP2_CTL_DDI(port)_PORT_HDCP2_BASE(port, 0xB0)
+#define CTL_LINK_ENCRYPTION_REQ BIT(31)
+
+#define HDCP2_STATUS_DDI(port) _PORT_HDCP2_BASE(port, 0xB4)
+#define STREAM_ENCRYPTION_STATUS_A BIT(31)
+#define STREAM_ENCRYPTION_STATUS_B BIT(30)
+#define STREAM_ENCRYPTION_STATUS_C BIT(29)
+#define LINK_TYPE_STATUS BIT(22)
+#define LINK_AUTH_STATUS BIT(21)
+#define LINK_ENCRYPTION_STATUS BIT(20)
+
/* Per-pipe DDI Function Control */
#define _TRANS_DDI_FUNC_CTL_A 0x60400
#define _TRANS_DDI_FUNC_CTL_B 0x61400
--
2.7.4
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[Intel-gfx] [PATCH v5 03/40] mei: bus: whitelist hdcp client
From: Tomas Winkler
Whitelist HDCP client for in kernel drm use
v2:
Rebased.
v3:
No changes.
v4:
No changes.
v5:
No changes.
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/bus-fixup.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 0208c4b027c5..3df2a69fddfb 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -41,6 +41,9 @@ static const uuid_le mei_nfc_info_guid = MEI_UUID_NFC_INFO;
#define MEI_UUID_MKHIF_FIX UUID_LE(0x55213584, 0x9a29, 0x4916, \
0xba, 0xdf, 0xf, 0xb7, 0xed, 0x68, 0x2a, 0xeb)
+#define MEI_UUID_HDCP UUID_LE(0xB638AB7E, 0x94E2, 0x4EA2, \
+ 0xA5, 0x52, 0xD1, 0xC5, 0x4B, 0x62, 0x7F, 0x04)
+
#define MEI_UUID_ANY NULL_UUID_LE
/**
@@ -72,6 +75,18 @@ static void blacklist(struct mei_cl_device *cldev)
cldev->do_match = 0;
}
+/**
+ * whitelist - forcefully whitelist client
+ *
+ * @cldev: me clients device
+ */
+static void whitelist(struct mei_cl_device *cldev)
+{
+ dev_dbg(&cldev->dev, "running hook %s\n", __func__);
+
+ cldev->do_match = 1;
+}
+
#define OSTYPE_LINUX2
struct mei_os_ver {
__le16 build;
@@ -399,6 +414,7 @@ static struct mei_fixup {
MEI_FIXUP(MEI_UUID_NFC_HCI, mei_nfc),
MEI_FIXUP(MEI_UUID_WD, mei_wd),
MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix),
+ MEI_FIXUP(MEI_UUID_HDCP, whitelist),
};
/**
--
2.7.4
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[Intel-gfx] [PATCH v5 08/40] drm/i915: Initialize HDCP2.2 and its MEI interface
Initialize HDCP2.2 support. This includes the mei interface
initialization along with required component registration.
v2:
mei interface handle is protected with mutex. [Chris Wilson]
v3:
Notifiers are used for the mei interface state.
v4:
Poll for mei client device state
Error msg for out of mem [Uma]
Inline req for init function removed [Uma]
v5:
Rebase as Part of reordering.
Component is used for the I915 and MEI_HDCP interface [Daniel]
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_dp.c | 3 +-
drivers/gpu/drm/i915/intel_drv.h | 5 +-
drivers/gpu/drm/i915/intel_hdcp.c | 204 +-
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
include/drm/i915_component.h | 88
6 files changed, 298 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6f08ab310118..0e6fe140dc63 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2142,6 +2142,8 @@ struct drm_i915_private {
struct i915_pmu pmu;
+ struct i915_hdcp_component *hdcp_comp;
+
/*
* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
* will be rejected. Instead look for a better place.
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c1b2f00f324b..6bcc52766ea3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -6404,7 +6404,8 @@ intel_dp_init_connector(struct intel_digital_port
*intel_dig_port,
intel_dp_add_properties(intel_dp, connector);
if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
- int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
+ int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim,
+ false);
if (ret)
DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b615ea4a44c3..2eeb82b04953 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -441,9 +441,7 @@ struct intel_hdcp {
uint32_t seq_num_m;
/* mei interface related information */
- struct mei_cl_device *cldev;
struct mei_hdcp_data mei_data;
-
struct delayed_work hdcp2_check_work;
};
@@ -1962,7 +1960,8 @@ void intel_hdcp_atomic_check(struct drm_connector
*connector,
struct drm_connector_state *old_state,
struct drm_connector_state *new_state);
int intel_hdcp_init(struct intel_connector *connector,
- const struct intel_hdcp_shim *hdcp_shim);
+ const struct intel_hdcp_shim *hdcp_shim,
+ bool hdcp2_supported);
int intel_hdcp_enable(struct intel_connector *connector);
int intel_hdcp_disable(struct intel_connector *connector);
int intel_hdcp_check_link(struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index 65bbe5874eee..769560591aa8 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -8,13 +8,19 @@
#include
#include
+#include
#include
#include
+#include
#include "intel_drv.h"
#include "i915_reg.h"
#define KEY_LOAD_TRIES 5
+#define GET_MEI_DDI_INDEX(port)(((port) == PORT_A) ? DDI_A : \
+(enum hdcp_physical_port)(port))
+
+static int intel_hdcp2_init(struct intel_connector *connector);
static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
const struct intel_hdcp_shim *shim)
@@ -743,11 +749,15 @@ bool is_hdcp_supported(struct drm_i915_private *dev_priv,
enum port port)
}
int intel_hdcp_init(struct intel_connector *connector,
- const struct intel_hdcp_shim *hdcp_shim)
+ const struct intel_hdcp_shim *hdcp_shim,
+ bool hdcp2_supported)
{
struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
+ if (!hdcp_shim)
+ return -EINVAL;
+
ret = drm_connector_attach_content_protection_property(
&connector->base);
if (ret)
@@ -757,6 +767,10 @@ int intel_hdcp_init(struct intel_connector *connector,
mutex_init(&hdcp->hdcp_mutex);
INIT_DELAYED_WORK(&hdcp->hdcp_check_work, intel_hdcp_check_work);
INIT_WORK(&hdcp->hdcp_prop_work, intel_hdcp_prop_work);
+
+ if (hdcp2_supported)
+ intel_hdcp2_init(connector);
+
return 0;
}
@@ -896,3 +910,191 @@ int intel_hdcp_check_link(struct intel_connector
*connector)
mutex_unlock(&hdcp->hdcp_mutex);
return ret;
}
+
+static int i915_hdcp_compo
[Intel-gfx] [PATCH v5 09/40] drm/i915: Schedule hdcp_check_link in _intel_hdcp_enable
As a preparation for making the intel_hdcp_enable as common function
for both HDCP1.4 and HDCP2.2, HDCP1.4 check_link scheduling is moved
into _intel_hdcp_enable() function.
v3:
No Changes.
v4:
Style fix.
v5:
No Change.
Signed-off-by: Ramalingam C
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_hdcp.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index 769560591aa8..4bff74b3bed0 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -688,7 +688,7 @@ static int _intel_hdcp_enable(struct intel_connector
*connector)
ret = intel_hdcp_auth(conn_to_dig_port(connector),
hdcp->hdcp_shim);
if (!ret)
- return 0;
+ break;
DRM_DEBUG_KMS("HDCP Auth failure (%d)\n", ret);
@@ -696,7 +696,13 @@ static int _intel_hdcp_enable(struct intel_connector
*connector)
_intel_hdcp_disable(connector);
}
- DRM_ERROR("HDCP authentication failed (%d tries/%d)\n", tries, ret);
+ if (i != tries)
+ schedule_delayed_work(&hdcp->hdcp_check_work,
+ DRM_HDCP_CHECK_PERIOD_MS);
+ else
+ DRM_ERROR("HDCP authentication failed (%d tries/%d)\n",
+ tries, ret);
+
return ret;
}
@@ -790,8 +796,6 @@ int intel_hdcp_enable(struct intel_connector *connector)
hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
schedule_work(&hdcp->hdcp_prop_work);
- schedule_delayed_work(&hdcp->hdcp_check_work,
- DRM_HDCP_CHECK_PERIOD_MS);
out:
mutex_unlock(&hdcp->hdcp_mutex);
return ret;
--
2.7.4
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[Intel-gfx] [PATCH v5 05/40] drm/i915: wrapping all hdcp var into intel_hdcp
Considering significant number of HDCP specific variables, it will
be clean to have separate struct for HDCP.
New structure called intel_hdcp is added within intel_connector.
v2:
struct hdcp statically allocated. [Sean Paul]
enable and disable function parameters are retained.[Sean Paul]
v3:
No Changes.
v4:
Commit msg is rephrased [Uma]
v5:
Comment for mutex definition.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_display.c | 7 +--
drivers/gpu/drm/i915/intel_drv.h | 15 --
drivers/gpu/drm/i915/intel_hdcp.c| 94
3 files changed, 67 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3d849ec17f5c..ef09bb89d2ca 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15856,9 +15856,10 @@ static void intel_hpd_poll_fini(struct drm_device *dev)
for_each_intel_connector_iter(connector, &conn_iter) {
if (connector->modeset_retry_work.func)
cancel_work_sync(&connector->modeset_retry_work);
- if (connector->hdcp_shim) {
- cancel_delayed_work_sync(&connector->hdcp_check_work);
- cancel_work_sync(&connector->hdcp_prop_work);
+ if (connector->hdcp.hdcp_shim) {
+ cancel_delayed_work_sync(
+ &connector->hdcp.hdcp_check_work);
+ cancel_work_sync(&connector->hdcp.hdcp_prop_work);
}
}
drm_connector_list_iter_end(&conn_iter);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 578346b8d7e2..eb480574a92e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -377,6 +377,15 @@ struct intel_hdcp_shim {
bool *hdcp_capable);
};
+struct intel_hdcp {
+ const struct intel_hdcp_shim *hdcp_shim;
+ /* Mutex for hdcp state of the connector */
+ struct mutex hdcp_mutex;
+ uint64_t hdcp_value;
+ struct delayed_work hdcp_check_work;
+ struct work_struct hdcp_prop_work;
+};
+
struct intel_connector {
struct drm_connector base;
/*
@@ -409,11 +418,7 @@ struct intel_connector {
/* Work struct to schedule a uevent on link train failure */
struct work_struct modeset_retry_work;
- const struct intel_hdcp_shim *hdcp_shim;
- struct mutex hdcp_mutex;
- uint64_t hdcp_value; /* protected by hdcp_mutex */
- struct delayed_work hdcp_check_work;
- struct work_struct hdcp_prop_work;
+ struct intel_hdcp hdcp;
};
struct intel_digital_connector_state {
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index 0cc6a861bcf8..65bbe5874eee 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -626,6 +626,7 @@ struct intel_digital_port *conn_to_dig_port(struct
intel_connector *connector)
static int _intel_hdcp_disable(struct intel_connector *connector)
{
+ struct intel_hdcp *hdcp = &connector->hdcp;
struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
enum port port = intel_dig_port->base.port;
@@ -641,7 +642,7 @@ static int _intel_hdcp_disable(struct intel_connector
*connector)
return -ETIMEDOUT;
}
- ret = connector->hdcp_shim->toggle_signalling(intel_dig_port, false);
+ ret = hdcp->hdcp_shim->toggle_signalling(intel_dig_port, false);
if (ret) {
DRM_ERROR("Failed to disable HDCP signalling\n");
return ret;
@@ -653,6 +654,7 @@ static int _intel_hdcp_disable(struct intel_connector
*connector)
static int _intel_hdcp_enable(struct intel_connector *connector)
{
+ struct intel_hdcp *hdcp = &connector->hdcp;
struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
int i, ret, tries = 3;
@@ -678,7 +680,7 @@ static int _intel_hdcp_enable(struct intel_connector
*connector)
/* Incase of authentication failures, HDCP spec expects reauth. */
for (i = 0; i < tries; i++) {
ret = intel_hdcp_auth(conn_to_dig_port(connector),
- connector->hdcp_shim);
+ hdcp->hdcp_shim);
if (!ret)
return 0;
@@ -694,36 +696,42 @@ static int _intel_hdcp_enable(struct intel_connector
*connector)
static void intel_hdcp_check_work(struct work_struct *work)
{
- struct intel_connector *connector = container_of(to_delayed_work(work),
+ struct intel_hdcp *hdcp = container_of(to_delayed_work(work),
+ struct intel_hdcp,
+
[Intel-gfx] [PATCH v5 10/40] drm/i915: Pullout the bksv read and validation
For reusability purpose, this patch implements the hdcp1.4 bksv's
read and validation as a functions.
For detecting the HDMI panel's HDCP capability this fucntions will be
used.
v2:
Rebased.
v3:
No Changes.
v4:
inline tag is removed with modified error msg.
v5:
No Changes.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 37 +
1 file changed, 25 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index 4bff74b3bed0..32a1a3f39b65 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -400,6 +400,28 @@ int intel_hdcp_validate_v_prime(struct intel_digital_port
*intel_dig_port,
return 0;
}
+static
+int intel_hdcp_read_valid_bksv(struct intel_digital_port *intel_dig_port,
+ const struct intel_hdcp_shim *shim, u8 *bksv)
+{
+ int ret, i, tries = 2;
+
+ /* HDCP spec states that we must retry the bksv if it is invalid */
+ for (i = 0; i < tries; i++) {
+ ret = shim->read_bksv(intel_dig_port, bksv);
+ if (ret)
+ return ret;
+ if (intel_hdcp_is_ksv_valid(bksv))
+ break;
+ }
+ if (i == tries) {
+ DRM_ERROR("Bksv is invalid\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
/* Implements Part 2 of the HDCP authorization procedure */
static
int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
@@ -533,18 +555,9 @@ static int intel_hdcp_auth(struct intel_digital_port
*intel_dig_port,
memset(&bksv, 0, sizeof(bksv));
- /* HDCP spec states that we must retry the bksv if it is invalid */
- for (i = 0; i < tries; i++) {
- ret = shim->read_bksv(intel_dig_port, bksv.shim);
- if (ret)
- return ret;
- if (intel_hdcp_is_ksv_valid(bksv.shim))
- break;
- }
- if (i == tries) {
- DRM_ERROR("HDCP failed, Bksv is invalid\n");
- return -ENODEV;
- }
+ ret = intel_hdcp_read_valid_bksv(intel_dig_port, shim, bksv.shim);
+ if (ret < 0)
+ return ret;
I915_WRITE(PORT_HDCP_BKSVLO(port), bksv.reg[0]);
I915_WRITE(PORT_HDCP_BKSVHI(port), bksv.reg[1]);
--
2.7.4
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[Intel-gfx] [PATCH v5 12/40] drm/i915: Enable HDCP1.4 incase of HDCP2.2 failure
When HDCP2.2 enabling fails and HDCP1.4 is supported, HDCP1.4 is
enabled.
v2:
Rebased.
v3:
No Changes.
v4:
Reviewed-by is collected.
v5:
No Change.
Signed-off-by: Ramalingam C
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_hdcp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index b34e3b1587d6..34bafc2025f7 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -863,7 +863,9 @@ int intel_hdcp_enable(struct intel_connector *connector)
*/
if (intel_hdcp2_capable(connector))
ret = _intel_hdcp2_enable(connector);
- else if (intel_hdcp_capable(connector))
+
+ /* When HDCP2.2 fails, HDCP1.4 will be attempted */
+ if (ret && intel_hdcp_capable(connector))
ret = _intel_hdcp_enable(connector);
if (!ret) {
--
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[Intel-gfx] [PATCH v5 11/40] drm/i915: Enable superior HDCP ver that is capable
Considering that HDCP2.2 is more secure than HDCP1.4, When a setup
supports HDCP2.2 and HDCP1.4, HDCP2.2 will be enabled.
v2:
Included few optimization suggestions [Chris Wilson]
Commit message is updated as per the rebased version.
v3:
No changes.
v4:
Extra comment added and Style issue fixed [Uma]
v5:
Rebased as part of patch reordering.
Flag is added for tracking hdcp2.2 encryption status.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_hdcp.c | 90 +++
2 files changed, 83 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 2eeb82b04953..7624388eecd5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -414,6 +414,7 @@ struct intel_hdcp {
/* HDCP2.2 related definitions */
bool hdcp2_supported;
+ bool hdcp2_in_use;
/*
* Content Stream Type defined by content owner. TYPE0(0x0) content can
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index 32a1a3f39b65..b34e3b1587d6 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -21,6 +21,60 @@
(enum hdcp_physical_port)(port))
static int intel_hdcp2_init(struct intel_connector *connector);
+static int _intel_hdcp2_enable(struct intel_connector *connector);
+static int _intel_hdcp2_disable(struct intel_connector *connector);
+static
+int intel_hdcp_read_valid_bksv(struct intel_digital_port *intel_dig_port,
+ const struct intel_hdcp_shim *shim, u8 *bksv);
+static
+struct intel_digital_port *conn_to_dig_port(struct intel_connector *connector);
+
+static bool panel_supports_hdcp(struct intel_connector *connector)
+{
+ struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
+ struct intel_hdcp *hdcp = &connector->hdcp;
+ bool capable = false;
+ u8 bksv[5];
+
+ if (hdcp->hdcp_shim) {
+ if (hdcp->hdcp_shim->hdcp_capable) {
+ hdcp->hdcp_shim->hdcp_capable(intel_dig_port, &capable);
+ } else {
+ if (!intel_hdcp_read_valid_bksv(intel_dig_port,
+ hdcp->hdcp_shim, bksv))
+ capable = true;
+ }
+ }
+
+ return capable;
+}
+
+static inline
+bool panel_supports_hdcp2(struct intel_connector *connector)
+{
+ struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
+ struct intel_hdcp *hdcp = &connector->hdcp;
+ bool capable = false;
+
+ /* Check the panel's hdcp2.2 compliance if platform supports it. */
+ if (hdcp->hdcp2_supported)
+ hdcp->hdcp_shim->hdcp_2_2_capable(intel_dig_port, &capable);
+
+ return capable;
+}
+
+/* Is HDCP1.4 capable on Platform and Panel */
+static inline bool intel_hdcp_capable(struct intel_connector *connector)
+{
+ return (connector->hdcp.hdcp_shim && panel_supports_hdcp(connector));
+}
+
+/* Is HDCP2.2 capable on Platform and Panel */
+static inline bool intel_hdcp2_capable(struct intel_connector *connector)
+{
+ return (connector->hdcp.hdcp2_supported &&
+ panel_supports_hdcp2(connector));
+}
static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
const struct intel_hdcp_shim *shim)
@@ -796,20 +850,27 @@ int intel_hdcp_init(struct intel_connector *connector,
int intel_hdcp_enable(struct intel_connector *connector)
{
struct intel_hdcp *hdcp = &connector->hdcp;
- int ret;
+ int ret = -EINVAL;
if (!hdcp->hdcp_shim)
return -ENOENT;
mutex_lock(&hdcp->hdcp_mutex);
- ret = _intel_hdcp_enable(connector);
- if (ret)
- goto out;
+ /*
+* Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
+* is capable of HDCP2.2, it is preferred to use HDCP2.2.
+*/
+ if (intel_hdcp2_capable(connector))
+ ret = _intel_hdcp2_enable(connector);
+ else if (intel_hdcp_capable(connector))
+ ret = _intel_hdcp_enable(connector);
+
+ if (!ret) {
+ hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
+ schedule_work(&hdcp->hdcp_prop_work);
+ }
- hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
- schedule_work(&hdcp->hdcp_prop_work);
-out:
mutex_unlock(&hdcp->hdcp_mutex);
return ret;
}
@@ -826,7 +887,10 @@ int intel_hdcp_disable(struct intel_connector *connector)
if (hdcp->hdcp_value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
- ret = _intel_hdcp_disable(connector);
+ if
[Intel-gfx] [PATCH v5 13/40] drm/i915: Implement HDCP2.2 Enable and Disable
Implements a sequence of enabling and disabling the HDCP2.2
(auth and encryption).
v2:
Rebased.
v3:
No Changes.
v4:
No Changes.
v5:
Rebased as part of the patch reordering.
HDCP2 encryption status is tracked.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 105 +-
1 file changed, 104 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index 34bafc2025f7..f72684488bc7 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -994,14 +994,117 @@ int intel_hdcp_check_link(struct intel_connector
*connector)
return ret;
}
+static int hdcp2_close_mei_session(struct intel_connector *connector)
+{
+ struct mei_hdcp_data *data = &connector->hdcp.mei_data;
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct i915_hdcp_component *comp = dev_priv->hdcp_comp;
+ int ret;
+
+ if (!comp)
+ return -EINVAL;
+
+ mutex_lock(&comp->mutex);
+ if (!comp->ops || !comp->mei_cldev || data->port == INVALID_PORT) {
+ mutex_unlock(&comp->mutex);
+ return -EINVAL;
+ }
+ ret = comp->ops->close_hdcp_session(comp->mei_cldev, data);
+ mutex_unlock(&comp->mutex);
+
+ return ret;
+}
+
+static int hdcp2_deauthenticate_port(struct intel_connector *connector)
+{
+ return hdcp2_close_mei_session(connector);
+}
+
+static int hdcp2_authenticate_sink(struct intel_connector *connector)
+{
+ return 0;
+}
+
+static int hdcp2_enable_encryption(struct intel_connector *connector)
+{
+ return 0;
+}
+
+static int hdcp2_disable_encryption(struct intel_connector *connector)
+{
+ return 0;
+}
+
+static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
+{
+ int ret, i, tries = 3;
+
+ for (i = 0; i < tries; i++) {
+ ret = hdcp2_authenticate_sink(connector);
+ if (!ret)
+ break;
+
+ /* Clearing the mei hdcp session */
+ hdcp2_deauthenticate_port(connector);
+ DRM_DEBUG_KMS("HDCP2.2 Auth %d of %d Failed.(%d)\n",
+ i + 1, tries, ret);
+ }
+
+ if (i != tries) {
+ /*
+* Ensuring the required 200mSec min time interval between
+* Session Key Exchange and encryption.
+*/
+ msleep(HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN);
+ ret = hdcp2_enable_encryption(connector);
+ if (ret < 0) {
+ DRM_DEBUG_KMS("Encryption Enable Failed.(%d)\n", ret);
+ hdcp2_deauthenticate_port(connector);
+ }
+ }
+
+ return ret;
+}
+
static int _intel_hdcp2_enable(struct intel_connector *connector)
{
+ struct intel_hdcp *hdcp = &connector->hdcp;
+ int ret;
+
+ DRM_DEBUG_KMS("[%s:%d] HDCP2.2 is being enabled. Type: %d\n",
+ connector->base.name, connector->base.base.id,
+ hdcp->content_type);
+
+ ret = hdcp2_authenticate_and_encrypt(connector);
+ if (ret) {
+ DRM_ERROR("HDCP2 Type%d Enabling Failed. (%d)\n",
+ hdcp->content_type, ret);
+ return ret;
+ }
+
+ DRM_DEBUG_KMS("[%s:%d] HDCP2.2 is enabled. Type %d\n",
+ connector->base.name, connector->base.base.id,
+ hdcp->content_type);
+
+ hdcp->hdcp2_in_use = true;
+ hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
+ schedule_work(&hdcp->hdcp_prop_work);
return 0;
}
static int _intel_hdcp2_disable(struct intel_connector *connector)
{
- return 0;
+ int ret;
+
+ DRM_DEBUG_KMS("[%s:%d] HDCP2.2 is being Disabled\n",
+ connector->base.name, connector->base.base.id);
+
+ ret = hdcp2_disable_encryption(connector);
+
+ hdcp2_deauthenticate_port(connector);
+ connector->hdcp.hdcp2_in_use = false;
+
+ return ret;
}
static int i915_hdcp_component_master_bind(struct device *dev)
--
2.7.4
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[Intel-gfx] [PATCH v5 19/40] drm/i915: hdcp_check_link only on CP_IRQ
HDCP check link is invoked only on CP_IRQ detection, instead of all
short pulses.
v3:
No Changes.
v4:
Added sean in cc and collected the reviewed-by received.
v5:
No Change.
Signed-off-by: Ramalingam C
cc: Sean Paul
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dp.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6bcc52766ea3..7467e7b3f2df 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4483,8 +4483,10 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
intel_dp_handle_test_request(intel_dp);
- if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
- DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
+ if (sink_irq_vector & DP_CP_IRQ)
+ intel_hdcp_check_link(intel_dp->attached_connector);
+ if (sink_irq_vector & DP_SINK_SPECIFIC_IRQ)
+ DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
}
/* defer to the hotplug work for link retraining if needed */
@@ -5454,9 +5456,6 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
handled = intel_dp_short_pulse(intel_dp);
- /* Short pulse can signify loss of hdcp authentication */
- intel_hdcp_check_link(intel_dp->attached_connector);
-
if (!handled) {
intel_dp->detect_done = false;
goto put_power;
--
2.7.4
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[Intel-gfx] [PATCH v5 14/40] drm/i915: Enable and Disable HDCP2.2 port encryption
Implements the enable and disable functions for HDCP2.2 encryption
of the PORT.
v2:
intel_wait_for_register is used instead of wait_for. [Chris Wilson]
v3:
No Changes.
v4:
Debug msg is added for timeout at Disable of Encryption [Uma]
%s/HDCP2_CTL/HDCP2_CTL
v5:
Rebased as part of patch reordering.
HW state check is moved into WARN_ON [Daniel]
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 48 +--
1 file changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index f72684488bc7..1e75b4fc978a 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -17,6 +17,7 @@
#include "i915_reg.h"
#define KEY_LOAD_TRIES 5
+#define TIME_FOR_ENCRYPT_STATUS_CHANGE 32
#define GET_MEI_DDI_INDEX(port)(((port) == PORT_A) ? DDI_A : \
(enum hdcp_physical_port)(port))
@@ -1027,12 +1028,55 @@ static int hdcp2_authenticate_sink(struct
intel_connector *connector)
static int hdcp2_enable_encryption(struct intel_connector *connector)
{
- return 0;
+ struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct intel_hdcp *hdcp = &connector->hdcp;
+ enum port port = connector->encoder->port;
+ int ret;
+
+ WARN_ON(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS);
+
+ if (hdcp->hdcp_shim->toggle_signalling)
+ hdcp->hdcp_shim->toggle_signalling(intel_dig_port, true);
+
+ if (I915_READ(HDCP2_STATUS_DDI(port)) & LINK_AUTH_STATUS) {
+ /* Link is Authenticated. Now set for Encryption */
+ I915_WRITE(HDCP2_CTL_DDI(port),
+ I915_READ(HDCP2_CTL_DDI(port)) |
+ CTL_LINK_ENCRYPTION_REQ);
+ }
+
+ ret = intel_wait_for_register(dev_priv, HDCP2_STATUS_DDI(port),
+ LINK_ENCRYPTION_STATUS,
+ LINK_ENCRYPTION_STATUS,
+ TIME_FOR_ENCRYPT_STATUS_CHANGE);
+
+ return ret;
}
static int hdcp2_disable_encryption(struct intel_connector *connector)
{
- return 0;
+ struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct intel_hdcp *hdcp = &connector->hdcp;
+ enum port port = connector->encoder->port;
+ int ret;
+
+ WARN_ON(!(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS));
+
+ I915_WRITE(HDCP2_CTL_DDI(port),
+ I915_READ(HDCP2_CTL_DDI(port)) & ~CTL_LINK_ENCRYPTION_REQ);
+
+ ret = intel_wait_for_register(dev_priv, HDCP2_STATUS_DDI(port),
+ LINK_ENCRYPTION_STATUS, 0x0,
+ TIME_FOR_ENCRYPT_STATUS_CHANGE);
+ if (ret == -ETIMEDOUT)
+ DRM_DEBUG_KMS("Disable Encryption Timedout");
+
+ if (hdcp->hdcp_shim->toggle_signalling)
+ hdcp->hdcp_shim->toggle_signalling(intel_dig_port, false);
+
+ return ret;
}
static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
--
2.7.4
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[Intel-gfx] [PATCH v5 17/40] drm/i915: Implement HDCP2.2 link integrity check
Implements the link integrity check once in 500mSec.
Once encryption is enabled, an ongoing Link Integrity Check is
performed by the HDCP Receiver to check that cipher synchronization
is maintained between the HDCP Transmitter and the HDCP Receiver.
On the detection of synchronization lost, the HDCP Receiver must assert
the corresponding bits of the RxStatus register. The Transmitter polls
the RxStatus register and it may initiate re-authentication.
v2:
Rebased.
v3:
No Changes.
v4:
enum check_link_response is used check the link status [Uma]
v5:
Rebased as part of patch reordering.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 82 +++
include/drm/drm_hdcp.h| 8
2 files changed, 90 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index cf1c5f20b62e..ec840c1178bb 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -25,6 +25,8 @@
static int intel_hdcp2_init(struct intel_connector *connector);
static int _intel_hdcp2_enable(struct intel_connector *connector);
static int _intel_hdcp2_disable(struct intel_connector *connector);
+static void intel_hdcp2_check_work(struct work_struct *work);
+static int intel_hdcp2_check_link(struct intel_connector *connector);
static
int intel_hdcp_read_valid_bksv(struct intel_digital_port *intel_dig_port,
const struct intel_hdcp_shim *shim, u8 *bksv);
@@ -841,6 +843,7 @@ int intel_hdcp_init(struct intel_connector *connector,
hdcp->hdcp_shim = hdcp_shim;
mutex_init(&hdcp->hdcp_mutex);
INIT_DELAYED_WORK(&hdcp->hdcp_check_work, intel_hdcp_check_work);
+ INIT_DELAYED_WORK(&hdcp->hdcp2_check_work, intel_hdcp2_check_work);
INIT_WORK(&hdcp->hdcp_prop_work, intel_hdcp_prop_work);
if (hdcp2_supported)
@@ -1709,6 +1712,8 @@ static int _intel_hdcp2_enable(struct intel_connector
*connector)
hdcp->hdcp2_in_use = true;
hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
schedule_work(&hdcp->hdcp_prop_work);
+ schedule_delayed_work(&hdcp->hdcp2_check_work,
+ DRM_HDCP2_CHECK_PERIOD_MS);
return 0;
}
@@ -1914,3 +1919,80 @@ static int intel_hdcp2_init(struct intel_connector
*connector)
exit:
return ret;
}
+
+static int intel_hdcp2_check_link(struct intel_connector *connector)
+{
+ struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct intel_hdcp *hdcp = &connector->hdcp;
+ enum port port = connector->encoder->port;
+ int ret = 0;
+
+ if (!hdcp->hdcp_shim)
+ return -ENOENT;
+
+ mutex_lock(&hdcp->hdcp_mutex);
+
+ if (hdcp->hdcp_value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
+ goto out;
+
+ if (!(I915_READ(HDCP2_STATUS_DDI(port)) & LINK_ENCRYPTION_STATUS)) {
+ DRM_ERROR("HDCP check failed: link is not encrypted, %x\n",
+ I915_READ(HDCP2_STATUS_DDI(port)));
+ ret = -ENXIO;
+ hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+ schedule_work(&hdcp->hdcp_prop_work);
+ goto out;
+ }
+
+ ret = hdcp->hdcp_shim->check_2_2_link(intel_dig_port);
+ if (ret == DRM_HDCP_LINK_PROTECTED) {
+ if (hdcp->hdcp_value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
+ hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
+ schedule_work(&hdcp->hdcp_prop_work);
+ }
+ goto out;
+ }
+
+ DRM_ERROR("[%s:%d] HDCP2.2 link failed, retrying auth\n",
+ connector->base.name, connector->base.base.id);
+
+ ret = _intel_hdcp2_disable(connector);
+ if (ret) {
+ DRM_ERROR("[%s:%d] Failed to disable hdcp2.2 (%d)\n",
+ connector->base.name, connector->base.base.id, ret);
+
+ hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+ schedule_work(&hdcp->hdcp_prop_work);
+ goto out;
+ }
+
+ ret = _intel_hdcp2_enable(connector);
+ if (ret) {
+ DRM_ERROR("[%s:%d] Failed to enable hdcp2.2 (%d)\n",
+ connector->base.name, connector->base.base.id, ret);
+
+ hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+ schedule_work(&hdcp->hdcp_prop_work);
+ goto out;
+ }
+
+out:
+ mutex_unlock(&hdcp->hdcp_mutex);
+
+ return ret;
+}
+
+static void intel_hdcp2_check_work(struct work_struct *work)
+{
+ struct intel_hdcp *hdcp = container_of(to_delayed_work(work),
+ struct intel_hdcp,
+ hdcp2_check_work);
+
[Intel-gfx] [PATCH v5 15/40] drm/i915: Implement HDCP2.2 receiver authentication
Implements HDCP2.2 authentication for hdcp2.2 receivers, with
following steps:
Authentication and Key exchange (AKE).
Locality Check (LC).
Session Key Exchange(SKE).
DP Errata for stream type configuration for receivers.
At AKE, the HDCP Receiver’s public key certificate is verified by the
HDCP Transmitter. A Master Key k m is exchanged.
At LC, the HDCP Transmitter enforces locality on the content by
requiring that the Round Trip Time (RTT) between a pair of messages
is not more than 20 ms.
At SKE, The HDCP Transmitter exchanges Session Key ks with
the HDCP Receiver.
In DP HDCP2.2 encryption and decryption logics use the stream type as
one of the parameter. So Before enabling the Encryption DP HDCP2.2
receiver needs to be communicated with stream type. This is added to
spec as ERRATA.
This generic implementation is complete only with the hdcp2_shim
defined.
v2:
Rebased.
v3:
No Changes.
v4:
%s/PARING/PAIRING
Coding style fixing [Uma]
v5:
Rebased as part of patch reordering.
Defined the functions for mei services. [Daniel]
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 400 +-
1 file changed, 399 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index 1e75b4fc978a..bb6e72807060 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -18,6 +18,7 @@
#define KEY_LOAD_TRIES 5
#define TIME_FOR_ENCRYPT_STATUS_CHANGE 32
+#define HDCP2_LC_RETRY_CNT 3
#define GET_MEI_DDI_INDEX(port)(((port) == PORT_A) ? DDI_A : \
(enum hdcp_physical_port)(port))
@@ -995,6 +996,222 @@ int intel_hdcp_check_link(struct intel_connector
*connector)
return ret;
}
+static int
+hdcp2_prepare_ake_init(struct intel_connector *connector,
+ struct hdcp2_ake_init *ake_data)
+{
+ struct mei_hdcp_data *data = &connector->hdcp.mei_data;
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct i915_hdcp_component *comp = dev_priv->hdcp_comp;
+ int ret;
+
+ if (!comp)
+ return -EINVAL;
+
+ mutex_lock(&comp->mutex);
+ if (!comp->ops || !comp->mei_cldev) {
+ mutex_unlock(&comp->mutex);
+ return -EINVAL;
+ }
+
+ if (data->port == INVALID_PORT && connector->encoder)
+ data->port = GET_MEI_DDI_INDEX(connector->encoder->port);
+
+ /* Clear ME FW instance for the port, just incase */
+ comp->ops->close_hdcp_session(comp->mei_cldev, data);
+
+ ret = comp->ops->initiate_hdcp2_session(comp->mei_cldev,
+ data, ake_data);
+ mutex_unlock(&comp->mutex);
+
+ return ret;
+}
+
+static int
+hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector,
+ struct hdcp2_ake_send_cert *rx_cert,
+ bool *paired,
+ struct hdcp2_ake_no_stored_km *ek_pub_km,
+ size_t *msg_sz)
+{
+ struct mei_hdcp_data *data = &connector->hdcp.mei_data;
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct i915_hdcp_component *comp = dev_priv->hdcp_comp;
+ int ret;
+
+ if (!comp)
+ return -EINVAL;
+
+ mutex_lock(&comp->mutex);
+ if (!comp->ops || !comp->mei_cldev || data->port == INVALID_PORT) {
+ mutex_unlock(&comp->mutex);
+ return -EINVAL;
+ }
+
+ ret = comp->ops->verify_receiver_cert_prepare_km(comp->mei_cldev, data,
+rx_cert, paired,
+ek_pub_km, msg_sz);
+ if (ret < 0)
+ comp->ops->close_hdcp_session(comp->mei_cldev, data);
+
+ mutex_unlock(&comp->mutex);
+ return ret;
+}
+
+static int hdcp2_verify_hprime(struct intel_connector *connector,
+ struct hdcp2_ake_send_hprime *rx_hprime)
+{
+ struct mei_hdcp_data *data = &connector->hdcp.mei_data;
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct i915_hdcp_component *comp = dev_priv->hdcp_comp;
+ int ret;
+
+ if (!comp)
+ return -EINVAL;
+
+ mutex_lock(&comp->mutex);
+ if (!comp->ops || !comp->mei_cldev || data->port == INVALID_PORT) {
+ mutex_unlock(&comp->mutex);
+ return -EINVAL;
+ }
+
+ ret = comp->ops->verify_hprime(comp->mei_cldev, data, rx_hprime);
+ if (ret < 0)
+ comp->ops->close_hdcp_session(comp->mei_cldev, data);
+
+ mutex_unlock(&comp->mutex);
+ return ret;
+}
+
+static int
+hdcp2_store_pairing_info(struct intel_connector *connector,
+st
[Intel-gfx] [PATCH v5 21/40] drm/i915/gmbus: Increase the Bytes per Rd/Wr Op
GMBUS HW supports 511Bytes as Max Bytes per single RD/WR op. Instead of
enabling the 511Bytes per RD/WR cycle on legacy platforms for no
absolute ROIs, this change allows the max bytes per op upto 511Bytes
from Gen9 onwards.
v2:
No Change.
v3:
Inline function for max_xfer_size and renaming of the macro.[Jani]
v4:
Extra brackets removed [ville]
Commit msg is modified.
v5:
Adding the Reviewed-By received.
v6:
No Change.
Cc: Jani Nikula
Cc: Chris Wilson
Signed-off-by: Ramalingam C
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_i2c.c | 11 +--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 822fee56931e..91d42b3e39ad 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3049,6 +3049,7 @@ enum i915_power_well_id {
#define GMBUS_CYCLE_STOP (4 << 25)
#define GMBUS_BYTE_COUNT_SHIFT 16
#define GMBUS_BYTE_COUNT_MAX 256U
+#define GEN9_GMBUS_BYTE_COUNT_MAX 511U
#define GMBUS_SLAVE_INDEX_SHIFT 8
#define GMBUS_SLAVE_ADDR_SHIFT 1
#define GMBUS_SLAVE_READ (1 << 0)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 97606c1be70d..82bb9c33ab1c 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -361,6 +361,13 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
return ret;
}
+static inline
+unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
+{
+ return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
+ GMBUS_BYTE_COUNT_MAX;
+}
+
static int
gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
unsigned short addr, u8 *buf, unsigned int len,
@@ -400,7 +407,7 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct
i2c_msg *msg,
int ret;
do {
- len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
+ len = min(rx_size, gmbus_max_xfer_size(dev_priv));
ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
buf, len, gmbus1_index);
@@ -462,7 +469,7 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct
i2c_msg *msg,
int ret;
do {
- len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
+ len = min(tx_size, gmbus_max_xfer_size(dev_priv));
ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
gmbus1_index);
--
2.7.4
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[Intel-gfx] [PATCH v5 23/40] drm/i915: Implement the HDCP2.2 support for DP
Implements the DP adaptation specific HDCP2.2 functions.
These functions perform the DPCD read and write for communicating the
HDCP2.2 auth message back and forth.
Note: Chris Wilson suggested alternate method for waiting for CP_IRQ,
than completions concept. WIP to understand and implement that,
if needed. Just to unblock the review of other changes, v2 still
continues with completions.
v2:
wait for cp_irq is merged with this patch. Rebased.
v3:
wait_queue is used for wait for cp_irq [Chris Wilson]
v4:
Style fixed.
%s/PARING/PAIRING
Few style fixes [Uma]
v5:
Lookup table for DP HDCP2.2 msg details [Daniel].
Extra lines are removed.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_dp.c | 333 ++
drivers/gpu/drm/i915/intel_drv.h | 7 +
drivers/gpu/drm/i915/intel_hdcp.c | 5 +
3 files changed, 345 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a6ba27ef20ae..c8974a7d2d37 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -31,6 +31,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -5086,6 +5087,27 @@ void intel_dp_encoder_suspend(struct intel_encoder
*intel_encoder)
pps_unlock(intel_dp);
}
+static int intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp,
+int timeout)
+{
+ long ret;
+
+ /* Reinit */
+ atomic_set(&hdcp->cp_irq_recved, 0);
+
+#define C (atomic_read(&hdcp->cp_irq_recved) > 0)
+ ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
+ msecs_to_jiffies(timeout));
+
+ if (ret > 0) {
+ atomic_set(&hdcp->cp_irq_recved, 0);
+ return 0;
+ } else if (!ret) {
+ return -ETIMEDOUT;
+ }
+ return (int)ret;
+}
+
static
int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
u8 *an)
@@ -5304,6 +5326,311 @@ int intel_dp_hdcp_capable(struct intel_digital_port
*intel_dig_port,
return 0;
}
+static struct hdcp2_dp_msg_data {
+ uint8_t msg_id;
+ uint32_t offset;
+ bool msg_detectable;
+ uint32_t timeout;
+ uint32_t timeout2; /* Added for non_paired situation */
+ } hdcp2_msg_data[] = {
+ {HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0},
+ {HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
+ false, HDCP_2_2_CERT_TIMEOUT, 0},
+ {HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
+ false, 0, 0},
+ {HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
+ false, 0, 0},
+ {HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
+ true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT,
+ HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT},
+ {HDCP_2_2_AKE_SEND_PAIRING_INFO,
+ DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
+ HDCP_2_2_PAIRING_TIMEOUT, 0},
+ {HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0},
+ {HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
+ false, HDCP_2_2_DP_LPRIME_TIMEOUT, 0},
+ {HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
+ 0, 0},
+ {HDCP_2_2_REP_SEND_RECVID_LIST,
+ DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
+ HDCP_2_2_RECVID_LIST_TIMEOUT, 0},
+ {HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
+ 0, 0},
+ {HDCP_2_2_REP_STREAM_MANAGE,
+ DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
+ 0, 0},
+ {HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
+ false, HDCP_2_2_STREAM_READY_TIMEOUT, 0},
+ {HDCP_2_2_ERRATA_DP_STREAM_TYPE,
+ DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
+ 0, 0},
+ };
+
+static inline
+int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
+ uint8_t *rx_status)
+{
+ ssize_t ret;
+
+ ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
+ DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
+ HDCP_2_2_DP_RXSTATUS_LEN);
+ if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
+ DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
+ return ret >= 0 ? -EIO : ret;
+ }
+
+ return 0;
+}
+
+s
[Intel-gfx] [PATCH v5 18/40] drm/i915: Handle HDCP2.2 downstream topology change
When repeater notifies a downstream topology change, this patch
reauthenticate the repeater alone without disabling the hdcp
encryption. If that fails then complete reauthentication is executed.
v2:
Rebased.
v3:
No Changes.
v4:
Typo in commit msg is fixed [Uma]
v5:
Rebased as part of patch reordering.
Minor style fixes.
Signed-off-by: Ramalingam C
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_hdcp.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index ec840c1178bb..790f4a9f4793 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -1954,8 +1954,23 @@ static int intel_hdcp2_check_link(struct intel_connector
*connector)
goto out;
}
- DRM_ERROR("[%s:%d] HDCP2.2 link failed, retrying auth\n",
- connector->base.name, connector->base.base.id);
+ if (ret == DRM_HDCP_TOPOLOGY_CHANGE) {
+ if (hdcp->hdcp_value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
+ goto out;
+
+ DRM_DEBUG_KMS("HDCP2.2 Downstream topology change\n");
+ ret = hdcp2_authenticate_repeater_topology(connector);
+ if (!ret) {
+ hdcp->hdcp_value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
+ schedule_work(&hdcp->hdcp_prop_work);
+ goto out;
+ }
+ DRM_ERROR("[%s:%d] Repeater topology auth failed.(%d)\n",
+ connector->base.name, connector->base.base.id, ret);
+ } else {
+ DRM_ERROR("[%s:%d] HDCP2.2 link failed, retrying auth\n",
+ connector->base.name, connector->base.base.id);
+ }
ret = _intel_hdcp2_disable(connector);
if (ret) {
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 22/40] drm/i915/gmbus: Enable burst read
Support for Burst read in HW is added for HDCP2.2 compliance
requirement.
This patch enables the burst read for all the gmbus read of more than
511Bytes, on capable platforms.
v2:
Extra line is removed.
v3:
Macro is added for detecting the BURST_READ Support [Jani]
Runtime detection of the need for burst_read [Jani]
Calculation enhancement.
v4:
GMBUS0 reg val is passed from caller [ville]
Removed a extra var [ville]
Extra brackets are removed [ville]
Implemented the handling of 512Bytes Burst Read.
v5:
Burst read max length is fixed at 767Bytes [Ville]
v6:
No Change.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_i2c.c | 62 +---
3 files changed, 56 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0e6fe140dc63..65323f61e590 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2584,6 +2584,9 @@ intel_info(const struct drm_i915_private *dev_priv)
IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
+#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
+ IS_GEMINILAKE(dev_priv) || \
+ IS_KABYLAKE(dev_priv))
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
* rows, which changed the alignment requirements and fence programming.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 91d42b3e39ad..1386356bcfc4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3020,6 +3020,7 @@ enum i915_power_well_id {
#define GMBUS_RATE_400KHZ(2 << 8) /* reserved on Pineview */
#define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */
#define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */
+#define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
#define GMBUS_PIN_DISABLED 0
#define GMBUS_PIN_SSC1
#define GMBUS_PIN_VGADDC 2
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 82bb9c33ab1c..3957988e46d1 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -371,12 +371,30 @@ unsigned int gmbus_max_xfer_size(struct drm_i915_private
*dev_priv)
static int
gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
unsigned short addr, u8 *buf, unsigned int len,
- u32 gmbus1_index)
+ u32 gmbus0_reg, u32 gmbus1_index)
{
+ unsigned int size = len;
+ bool burst_read = len > gmbus_max_xfer_size(dev_priv);
+ bool extra_byte_added = false;
+
+ if (burst_read) {
+
+ /*
+* As per HW Spec, for 512Bytes need to read extra Byte and
+* Ignore the extra byte read.
+*/
+ if (len == 512) {
+ extra_byte_added = true;
+ len++;
+ }
+ size = len % 256 + 256;
+ I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
+ }
+
I915_WRITE_FW(GMBUS1,
gmbus1_index |
GMBUS_CYCLE_WAIT |
- (len << GMBUS_BYTE_COUNT_SHIFT) |
+ (size << GMBUS_BYTE_COUNT_SHIFT) |
(addr << GMBUS_SLAVE_ADDR_SHIFT) |
GMBUS_SLAVE_READ | GMBUS_SW_RDY);
while (len) {
@@ -389,17 +407,34 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
val = I915_READ_FW(GMBUS3);
do {
+ if (extra_byte_added && len == 1)
+ break;
+
*buf++ = val & 0xff;
val >>= 8;
} while (--len && ++loop < 4);
+
+ if (burst_read && len == size - 4)
+ /* Reset the override bit */
+ I915_WRITE_FW(GMBUS0, gmbus0_reg);
}
return 0;
}
+/*
+ * HW spec says that 512Bytes in Burst read need special treatment.
+ * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
+ * an I2C slave, which supports such a lengthy burst read too for experiments.
+ *
+ * So until things get clarified on HW support, to avoid the burst read length
+ * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
+ */
+#define INTEL_GMBUS_BURST_READ_MAX_LEN 767U
+
static int
gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
- u32 gmbus1_index)
+ u32 gmbus0_reg, u32 gmbus1_index)
{
u8 *buf = msg->buf;
unsigned int rx_size = msg->len;
@@ -407,10 +442,13 @@ gmbus_xfer_read(struct drm_i915_p
[Intel-gfx] [PATCH v5 24/40] drm/i915: Implement the HDCP2.2 support for HDMI
Implements the HDMI adaptation specific HDCP2.2 operations.
Basically these are DDC read and write for authenticating through
HDCP2.2 messages.
v2:
Rebased.
v3:
No Changes.
v4:
No more special handling of Gmbus burst read for AKE_SEND_CERT.
Style fixed with few naming. [Uma]
%s/PARING/PAIRING
v5:
msg_sz is initialized at definition.
Lookup table is defined for HDMI HDCP2.2 msgs [Daniel].
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdmi.c | 187 ++
1 file changed, 187 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 7988f958d835..f3672e192be6 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1116,6 +1117,187 @@ bool intel_hdmi_hdcp_check_link(struct
intel_digital_port *intel_dig_port)
return true;
}
+static struct hdcp2_hdmi_msg_data {
+ uint8_t msg_id;
+ uint32_t timeout;
+ uint32_t timeout2;
+ } hdcp2_msg_data[] = {
+ {HDCP_2_2_AKE_INIT, 0, 0},
+ {HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT, 0},
+ {HDCP_2_2_AKE_NO_STORED_KM, 0, 0},
+ {HDCP_2_2_AKE_STORED_KM, 0, 0},
+ {HDCP_2_2_AKE_SEND_HPRIME, HDCP_2_2_HPRIME_PAIRED_TIMEOUT,
+ HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT},
+ {HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT, 0},
+ {HDCP_2_2_LC_INIT, 0, 0},
+ {HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT, 0},
+ {HDCP_2_2_SKE_SEND_EKS, 0, 0},
+ {HDCP_2_2_REP_SEND_RECVID_LIST,
+ HDCP_2_2_RECVID_LIST_TIMEOUT, 0},
+ {HDCP_2_2_REP_SEND_ACK, 0, 0},
+ {HDCP_2_2_REP_STREAM_MANAGE, 0, 0},
+ {HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT, 0},
+ };
+
+static
+int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
+ uint8_t *rx_status)
+{
+ return intel_hdmi_hdcp_read(intel_dig_port,
+ HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
+ rx_status,
+ HDCP_2_2_HDMI_RXSTATUS_LEN);
+}
+
+static int get_hdcp2_msg_timeout(uint8_t msg_id, bool is_paired)
+{
+ int i;
+
+ for (i = 0; i < sizeof(hdcp2_msg_data); i++)
+ if (hdcp2_msg_data[i].msg_id == msg_id &&
+ (msg_id != HDCP_2_2_AKE_SEND_HPRIME || is_paired))
+ return hdcp2_msg_data[i].timeout;
+ else if (hdcp2_msg_data[i].msg_id == msg_id)
+ return hdcp2_msg_data[i].timeout2;
+
+ return -EINVAL;
+}
+
+static inline
+int hdcp2_detect_msg_availability(struct intel_digital_port
*intel_digital_port,
+ uint8_t msg_id, bool *msg_ready,
+ ssize_t *msg_sz)
+{
+ uint8_t rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
+ int ret;
+
+ ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status);
+ if (ret < 0) {
+ DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret);
+ return ret;
+ }
+
+ *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
+ rx_status[0]);
+
+ if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
+ *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
+*msg_sz);
+ else
+ *msg_ready = *msg_sz;
+
+ return 0;
+}
+
+static ssize_t
+intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
+ uint8_t msg_id, bool paired)
+{
+ bool msg_ready = false;
+ int timeout, ret;
+ ssize_t msg_sz = 0;
+
+ timeout = get_hdcp2_msg_timeout(msg_id, paired);
+ if (timeout < 0)
+ return timeout;
+
+ ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port,
+msg_id, &msg_ready, &msg_sz),
+!ret && msg_ready && msg_sz, timeout * 1000,
+1000, 5 * 1000);
+ if (ret)
+ DRM_ERROR("msg_id: %d, ret: %d, timeout: %d\n",
+ msg_id, ret, timeout);
+
+ return ret ? ret : msg_sz;
+}
+
+static
+int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
+ void *buf, size_t size)
+{
+ unsigned int offset;
+
+ offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
+ return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size);
+}
+
+static
+int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
+ uint8_t msg_id, void *buf, size_t size)
+{
+ struct intel
[Intel-gfx] [PATCH v5 26/40] drm/i915: Add HDCP2.2 support for HDMI connectors
On HDMI connector init, intel_hdcp_init is passed with a flag for hdcp2.2
support based on the platform capability.
v2:
Rebased.
v3:
No Changes.
v4:
Collected the reviewed-by received.
v5:
No change.
Signed-off-by: Ramalingam C
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_hdmi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index f3672e192be6..05fa1f8da681 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2553,7 +2553,8 @@ void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port,
if (is_hdcp_supported(dev_priv, port)) {
int ret = intel_hdcp_init(intel_connector,
- &intel_hdmi_hdcp_shim, false);
+&intel_hdmi_hdcp_shim,
+is_hdcp2_supported(dev_priv));
if (ret)
DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
}
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 25/40] drm/i915: Add HDCP2.2 support for DP connectors
On DP connector init, intel_hdcp_init is passed with a flag for hdcp2.2
support based on the platform capability.
v2:
Rebased.
v3:
No Changes.
v4:
Collected the reviewed-by received.
v5:
No change.
Signed-off-by: Ramalingam C
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c8974a7d2d37..f5486f080951 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -6737,7 +6737,7 @@ intel_dp_init_connector(struct intel_digital_port
*intel_dig_port,
if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim,
- false);
+ is_hdcp2_supported(dev_priv));
if (ret)
DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 074dc5b53488..2ef3606a1810 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1974,6 +1974,7 @@ int intel_hdcp_enable(struct intel_connector *connector);
int intel_hdcp_disable(struct intel_connector *connector);
bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
void intel_hdcp_handle_cp_irq(struct intel_connector *connector);
+bool is_hdcp2_supported(struct drm_i915_private *dev_priv);
/* intel_psr.c */
#define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 16/40] drm/i915: Implement HDCP2.2 repeater authentication
Implements the HDCP2.2 repeaters authentication steps such as verifying
the downstream topology and sending stream management information.
v2:
Rebased.
v3:
No Changes.
v4:
-EINVAL is returned for topology error and rollover scenario.
Endianness conversion func from drm_hdcp.h is used [Uma]
v5:
Rebased as part of patches reordering.
Defined the mei service functions [Daniel]
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 178 ++
include/drm/drm_hdcp.h| 15
2 files changed, 193 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index bb6e72807060..cf1c5f20b62e 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -1188,6 +1188,63 @@ static int hdcp2_prepare_skey(struct intel_connector
*connector,
return ret;
}
+static int
+hdcp2_verify_rep_topology_prepare_ack(
+ struct intel_connector *connector,
+ struct hdcp2_rep_send_receiverid_list *rep_topology,
+ struct hdcp2_rep_send_ack *rep_send_ack)
+{
+ struct mei_hdcp_data *data = &connector->hdcp.mei_data;
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct i915_hdcp_component *comp = dev_priv->hdcp_comp;
+ int ret;
+
+ if (!comp)
+ return -EINVAL;
+
+ mutex_lock(&comp->mutex);
+ if (!comp->ops || !comp->mei_cldev || data->port == INVALID_PORT) {
+ mutex_unlock(&comp->mutex);
+ return -EINVAL;
+ }
+
+ ret = comp->ops->repeater_check_flow_prepare_ack(comp->mei_cldev, data,
+ rep_topology, rep_send_ack);
+ if (ret < 0)
+ comp->ops->close_hdcp_session(comp->mei_cldev, data);
+
+ mutex_unlock(&comp->mutex);
+
+ return ret;
+}
+
+static int
+hdcp2_verify_mprime(struct intel_connector *connector,
+ struct hdcp2_rep_stream_ready *stream_ready)
+{
+ struct mei_hdcp_data *data = &connector->hdcp.mei_data;
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct i915_hdcp_component *comp = dev_priv->hdcp_comp;
+ int ret;
+
+ if (!comp)
+ return -EINVAL;
+
+ mutex_lock(&comp->mutex);
+ if (!comp->ops || !comp->mei_cldev || data->port == INVALID_PORT) {
+ mutex_unlock(&comp->mutex);
+ return -EINVAL;
+ }
+
+ ret = comp->ops->verify_mprime(comp->mei_cldev, data, stream_ready);
+ if (ret < 0)
+ comp->ops->close_hdcp_session(comp->mei_cldev, data);
+
+ mutex_unlock(&comp->mutex);
+
+ return ret;
+}
+
static int hdcp2_authenticate_port(struct intel_connector *connector)
{
struct mei_hdcp_data *data = &connector->hdcp.mei_data;
@@ -1373,6 +1430,121 @@ static int hdcp2_session_key_exchange(struct
intel_connector *connector)
return 0;
}
+static
+int hdcp2_propagate_stream_management_info(struct intel_connector *connector)
+{
+ struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
+ struct intel_hdcp *hdcp = &connector->hdcp;
+ union {
+ struct hdcp2_rep_stream_manage stream_manage;
+ struct hdcp2_rep_stream_ready stream_ready;
+ } msgs;
+ const struct intel_hdcp_shim *shim = hdcp->hdcp_shim;
+ int ret;
+
+ /* Prepare RepeaterAuth_Stream_Manage msg */
+ msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE;
+ reverse_endianness(msgs.stream_manage.seq_num_m, HDCP_2_2_SEQ_NUM_LEN,
+ (u8 *)&hdcp->seq_num_m);
+
+ /* K no of streams is fixed as 1. Stored as big-endian. */
+ msgs.stream_manage.k = __swab16(1);
+
+ /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
+ msgs.stream_manage.streams[0].stream_id = 0;
+ msgs.stream_manage.streams[0].stream_type = hdcp->content_type;
+
+ /* Send it to Repeater */
+ ret = shim->write_2_2_msg(intel_dig_port, &msgs.stream_manage,
+ sizeof(msgs.stream_manage));
+ if (ret < 0)
+ return ret;
+
+ ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_REP_STREAM_READY,
+&msgs.stream_ready, sizeof(msgs.stream_ready));
+ if (ret < 0)
+ return ret;
+
+ hdcp->mei_data.seq_num_m = hdcp->seq_num_m;
+ hdcp->mei_data.streams[0].stream_type = hdcp->content_type;
+
+ ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
+ if (ret < 0)
+ return ret;
+
+ hdcp->seq_num_m++;
+
+ if (hdcp->seq_num_m > HDCP_2_2_SEQ_NUM_MAX) {
+ DRM_DEBUG_KMS("seq_num_m roll over.\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+static
+int hdcp2_authenticate_repeater_topology(struct
[Intel-gfx] [PATCH v5 30/40] misc/mei/hdcp: Initiate Wired HDCP2.2 Tx Session
Request ME FW to start the HDCP2.2 session for an intel port.
Prepares payloads for command WIRED_INITIATE_HDCP2_SESSION and sends
to ME FW.
On Success, ME FW will start a HDCP2.2 session for the port and
provides the content for HDCP2.2 AKE_Init message.
v2:
Rebased.
v3:
cldev is add as a separate parameter [Tomas]
Redundant comment and typecast are removed [Tomas]
v4:
%zd is used for size [Alexander]
%s/return -1/return -EIO [Alexander]
Spellings in commit msg is fixed [Uma]
v5:
Rebased.
Signed-off-by: Ramalingam C
---
drivers/misc/mei/hdcp/mei_hdcp.c | 70 +++-
1 file changed, 69 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index ba7550215b7f..7311e3095e94 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -32,14 +32,82 @@
#include
#include
#include
+#include
#include
+#include
+
+#include "mei_hdcp.h"
bool mei_hdcp_component_registered;
static struct mei_cl_device *mei_cldev;
+/*
+ * mei_initiate_hdcp2_session:
+ * Function to start a Wired HDCP2.2 Tx Session with ME FW
+ *
+ * cldev : Pointer for mei client device
+ * data: Intel HW specific Data
+ * ake_data: ptr to store AKE_Init
+ *
+ * Returns 0 on Success, <0 on Failure.
+ */
+static int mei_initiate_hdcp2_session(struct mei_cl_device *cldev,
+ struct mei_hdcp_data *data,
+ struct hdcp2_ake_init *ake_data)
+{
+ struct wired_cmd_initiate_hdcp2_session_in session_init_in = { { 0 } };
+ struct wired_cmd_initiate_hdcp2_session_out
+ session_init_out = { { 0 } };
+ struct device *dev;
+ ssize_t byte;
+
+ if (!data || !ake_data)
+ return -EINVAL;
+
+ dev = &cldev->dev;
+
+ session_init_in.header.api_version = HDCP_API_VERSION;
+ session_init_in.header.command_id = WIRED_INITIATE_HDCP2_SESSION;
+ session_init_in.header.status = ME_HDCP_STATUS_SUCCESS;
+ session_init_in.header.buffer_len =
+ WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN;
+
+ session_init_in.port.integrated_port_type = data->port_type;
+ session_init_in.port.physical_port = data->port;
+ session_init_in.protocol = (uint8_t)data->protocol;
+
+ byte = mei_cldev_send(cldev, (u8 *)&session_init_in,
+ sizeof(session_init_in));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ byte = mei_cldev_recv(cldev, (u8 *)&session_init_out,
+ sizeof(session_init_out));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ if (session_init_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+ dev_dbg(dev, "ME cmd 0x%08X Failed. Status: 0x%X\n",
+ WIRED_INITIATE_HDCP2_SESSION,
+ session_init_out.header.status);
+ return -EIO;
+ }
+
+ ake_data->msg_id = HDCP_2_2_AKE_INIT;
+ ake_data->tx_caps = session_init_out.tx_caps;
+ memcpy(ake_data->r_tx, session_init_out.r_tx,
+ sizeof(session_init_out.r_tx));
+
+ return 0;
+}
+
struct i915_hdcp_component_ops mei_hdcp_component_ops = {
.owner = THIS_MODULE,
- .initiate_hdcp2_session = NULL,
+ .initiate_hdcp2_session = mei_initiate_hdcp2_session,
.verify_receiver_cert_prepare_km= NULL,
.verify_hprime = NULL,
.store_pairing_info = NULL,
--
2.7.4
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[Intel-gfx] [PATCH v5 28/40] misc/mei/hdcp: Component framework for I915 Interface
Mei hdcp driver is designed as component slave for the I915 component
master.
v2:
Rebased.
v3:
Notifier chain is adopted for cldev state update [Tomas]
v4:
Made static dummy functions as inline in mei_hdcp.h
API for polling client device status
IS_ENABLED used in header, for config status for mei_hdcp.
v5:
Replacing the notifier with component framework. [Daniel]
Signed-off-by: Ramalingam C
---
drivers/misc/mei/hdcp/mei_hdcp.c | 94 +++-
1 file changed, 92 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 4cd6fdd01181..ba7550215b7f 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -31,6 +31,83 @@
#include
#include
#include
+#include
+#include
+
+bool mei_hdcp_component_registered;
+static struct mei_cl_device *mei_cldev;
+
+struct i915_hdcp_component_ops mei_hdcp_component_ops = {
+ .owner = THIS_MODULE,
+ .initiate_hdcp2_session = NULL,
+ .verify_receiver_cert_prepare_km= NULL,
+ .verify_hprime = NULL,
+ .store_pairing_info = NULL,
+ .initiate_locality_check= NULL,
+ .verify_lprime = NULL,
+ .get_session_key= NULL,
+ .repeater_check_flow_prepare_ack= NULL,
+ .verify_mprime = NULL,
+ .enable_hdcp_authentication = NULL,
+ .close_hdcp_session = NULL,
+};
+
+static int mei_hdcp_component_bind(struct device *mei_kdev,
+ struct device *i915_kdev, void *data)
+{
+ struct i915_hdcp_component *comp = data;
+
+ WARN_ON(!mutex_is_locked(&comp->mutex));
+ if (WARN_ON(comp->ops || comp->dev))
+ return -EEXIST;
+
+ dev_info(mei_kdev, "MEI HDCP comp bind\n");
+ comp->ops = &mei_hdcp_component_ops;
+ comp->i915_kdev = i915_kdev;
+ comp->mei_cldev = mei_cldev;
+ mei_cldev_set_drvdata(mei_cldev, (void *)comp);
+
+ return 0;
+}
+
+static void mei_hdcp_component_unbind(struct device *mei_kdev,
+ struct device *i915_kdev, void *data)
+{
+ struct i915_hdcp_component *comp = data;
+
+ WARN_ON(!mutex_is_locked(&comp->mutex));
+ dev_info(mei_kdev, "MEI HDCP comp unbind\n");
+ comp->ops = NULL;
+ comp->dev = NULL;
+ comp->mei_cldev = NULL;
+}
+
+static const struct component_ops mei_hdcp_component_bind_ops = {
+ .bind = mei_hdcp_component_bind,
+ .unbind = mei_hdcp_component_unbind,
+};
+
+void mei_hdcp_component_init(struct device *dev)
+{
+ int ret;
+
+ ret = component_add(dev, &mei_hdcp_component_bind_ops);
+ if (ret < 0) {
+ dev_err(dev, "Failed to add MEI HDCP comp (%d)\n", ret);
+ return;
+ }
+
+ mei_hdcp_component_registered = true;
+}
+
+void mei_hdcp_component_cleanup(struct device *dev)
+{
+ if (!mei_hdcp_component_registered)
+ return;
+
+ component_del(dev, &mei_hdcp_component_bind_ops);
+ mei_hdcp_component_registered = false;
+}
static int mei_hdcp_probe(struct mei_cl_device *cldev,
const struct mei_cl_device_id *id)
@@ -38,15 +115,28 @@ static int mei_hdcp_probe(struct mei_cl_device *cldev,
int ret;
ret = mei_cldev_enable(cldev);
- if (ret < 0)
+ if (ret < 0) {
dev_err(&cldev->dev, "mei_cldev_enable Failed. %d\n", ret);
+ return ret;
+ }
- return ret;
+ mei_cldev = cldev;
+ mei_hdcp_component_init(&cldev->dev);
+ return 0;
}
static int mei_hdcp_remove(struct mei_cl_device *cldev)
{
+ struct i915_hdcp_component *comp;
+
+ comp = mei_cldev_get_drvdata(cldev);
+ if (comp && comp->master_ops && comp->master_ops->pull_down_interface)
+ comp->master_ops->pull_down_interface(comp->i915_kdev);
+
+ mei_cldev = NULL;
mei_cldev_set_drvdata(cldev, NULL);
+ mei_hdcp_component_cleanup(&cldev->dev);
+
return mei_cldev_disable(cldev);
}
--
2.7.4
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[Intel-gfx] [PATCH v5 27/40] misc/mei/hdcp: Client driver for HDCP application
ME FW is contributes a vital role in HDCP2.2 authentication. HDCP2.2 driver needs to communicate to ME FW for each step of the HDCP2.2 authentication. ME FW prepare and HDCP2.2 authentication parameters and encrypt them as per spec. With such parameter Driver prepares HDCP2.2 auth messages and communicate with HDCP2.2 sink. Similarly HDCP2. sink's response is shared with ME FW for decrypt and verification. Once All the steps of HDCP2.2 authentications are complete on driver's request ME FW will configure the port as authenticated and supply the HDCP keys to the Gen HW for encryption. Only after this stage HDCP2.2 driver can start the HDCP2.2 encryption for a port. ME FW is interfaced to kernel through MEI Bus Driver. To obtain the HDCP2.2 services from the ME FW through MEI Bus driver MEI Client Driver is developed. With this change MEI_HDCP drivers selected by I915 by default. In case if we want to exclude the mei_hdcp compilation, we need to introduce a new config called HDCP2.2. Using such CONFIG var we could control the compilation of the HDCP2.2 code in I915 and also the compilation of the MEI_HDCP. v2: hdcp files are moved to drivers/misc/mei/hdcp/ [Tomas] v3: Squashed the Kbuild support [Tomas] UUID renamed and Module License is modified [Tomas] drv_data is set to null at remove [Tomas] v4: Module name is changed to "MEI HDCP" I915 Selects the MEI_HDCP v5: No Change. Signed-off-by: Ramalingam C Signed-off-by: Tomas Winkler --- drivers/gpu/drm/i915/Kconfig | 1 + drivers/misc/mei/Kconfig | 7 drivers/misc/mei/Makefile| 2 ++ drivers/misc/mei/hdcp/Makefile | 6 drivers/misc/mei/hdcp/mei_hdcp.c | 74 5 files changed, 90 insertions(+) create mode 100644 drivers/misc/mei/hdcp/Makefile create mode 100644 drivers/misc/mei/hdcp/mei_hdcp.c diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index dfd95889f4b7..bfa8f987910b 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -23,6 +23,7 @@ config DRM_I915 select SYNC_FILE select IOSF_MBI select CRC32 + select INTEL_MEI_HDCP help Choose this option if you have a system that has "Intel Graphics Media Accelerator" or "HD Graphics" integrated graphics, diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig index c49e1d2269af..9c518b7f0011 100644 --- a/drivers/misc/mei/Kconfig +++ b/drivers/misc/mei/Kconfig @@ -43,3 +43,10 @@ config INTEL_MEI_TXE Supported SoCs: Intel Bay Trail + +config INTEL_MEI_HDCP + tristate "Intel HDCP2.2 services of ME Interface" + select INTEL_MEI_ME + depends on DRM_I915 + help + MEI Support for HDCP2.2 Services on Intel SoCs. diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile index cd6825afa8e1..e64d1212fb85 100644 --- a/drivers/misc/mei/Makefile +++ b/drivers/misc/mei/Makefile @@ -23,3 +23,5 @@ mei-txe-objs += hw-txe.o mei-$(CONFIG_EVENT_TRACING) += mei-trace.o CFLAGS_mei-trace.o = -I$(src) + +obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/ diff --git a/drivers/misc/mei/hdcp/Makefile b/drivers/misc/mei/hdcp/Makefile new file mode 100644 index ..75ac50203223 --- /dev/null +++ b/drivers/misc/mei/hdcp/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile - HDCP client driver for Intel MEI Bus Driver. +# Copyright (c) 2010-2014, Intel Corporation. +# +obj-$(CONFIG_INTEL_MEI_HDCP) += mei_hdcp.o diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c new file mode 100644 index ..4cd6fdd01181 --- /dev/null +++ b/drivers/misc/mei/hdcp/mei_hdcp.c @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright © 2017-2018 Intel Corporation + * + * Mei_hdcp.c: HDCP client driver for mei bus + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
[Intel-gfx] [PATCH v5 20/40] drm/i915: Check HDCP 1.4 and 2.2 link on CP_IRQ
On DP HDCP1.4 and 2.2, when CP_IRQ is received, start the link
integrity check for the HDCP version that is enabled.
v2:
Rebased. Function name is changed.
v3:
No Changes.
v4:
No Changes.
v5:
No Changes.
Signed-off-by: Ramalingam C
cc: Sean Paul
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_hdcp.c | 31 ++-
3 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7467e7b3f2df..a6ba27ef20ae 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4484,7 +4484,7 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
intel_dp_handle_test_request(intel_dp);
if (sink_irq_vector & DP_CP_IRQ)
- intel_hdcp_check_link(intel_dp->attached_connector);
+ intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
if (sink_irq_vector & DP_SINK_SPECIFIC_IRQ)
DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7624388eecd5..875657fd7d3c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1965,8 +1965,8 @@ int intel_hdcp_init(struct intel_connector *connector,
bool hdcp2_supported);
int intel_hdcp_enable(struct intel_connector *connector);
int intel_hdcp_disable(struct intel_connector *connector);
-int intel_hdcp_check_link(struct intel_connector *connector);
bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
+void intel_hdcp_handle_cp_irq(struct intel_connector *connector);
/* intel_psr.c */
#define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index 790f4a9f4793..b035274785c8 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -32,6 +32,7 @@ int intel_hdcp_read_valid_bksv(struct intel_digital_port
*intel_dig_port,
const struct intel_hdcp_shim *shim, u8 *bksv);
static
struct intel_digital_port *conn_to_dig_port(struct intel_connector *connector);
+static int intel_hdcp_check_link(struct intel_connector *connector);
static bool panel_supports_hdcp(struct intel_connector *connector)
{
@@ -80,6 +81,26 @@ static inline bool intel_hdcp2_capable(struct
intel_connector *connector)
panel_supports_hdcp2(connector));
}
+static inline bool intel_hdcp_in_force(struct intel_connector *connector)
+{
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ enum port port = connector->encoder->port;
+ u32 reg;
+
+ reg = I915_READ(PORT_HDCP_STATUS(port));
+ return reg & (HDCP_STATUS_AUTH | HDCP_STATUS_ENC);
+}
+
+static inline bool intel_hdcp2_in_force(struct intel_connector *connector)
+{
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ enum port port = connector->encoder->port;
+ u32 reg;
+
+ reg = I915_READ(HDCP2_STATUS_DDI(port));
+ return reg & (LINK_ENCRYPTION_STATUS | LINK_AUTH_STATUS);
+}
+
static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
const struct intel_hdcp_shim *shim)
{
@@ -939,7 +960,7 @@ void intel_hdcp_atomic_check(struct drm_connector
*connector,
}
/* Implements Part 3 of the HDCP authorization procedure */
-int intel_hdcp_check_link(struct intel_connector *connector)
+static int intel_hdcp_check_link(struct intel_connector *connector)
{
struct intel_hdcp *hdcp = &connector->hdcp;
struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
@@ -2011,3 +2032,11 @@ static void intel_hdcp2_check_work(struct work_struct
*work)
schedule_delayed_work(&hdcp->hdcp2_check_work,
DRM_HDCP2_CHECK_PERIOD_MS);
}
+
+void intel_hdcp_handle_cp_irq(struct intel_connector *connector)
+{
+ if (intel_hdcp_in_force(connector))
+ intel_hdcp_check_link(connector);
+ else if (intel_hdcp2_in_force(connector))
+ intel_hdcp2_check_link(connector);
+}
--
2.7.4
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[Intel-gfx] [PATCH v5 29/40] misc/mei/hdcp: Define ME FW interface for HDCP2.2
Defines the HDCP specific ME FW interfaces such as Request CMDs,
payload structure for CMDs and their response status codes.
This patch defines payload size(Excluding the Header)for each WIRED
HDCP2.2 CMDs.
v2:
Rebased.
v3:
Extra comments are removed.
v4:
%s/\/\*\*/\/\*
v5:
Extra lines are removed.
Signed-off-by: Ramalingam C
---
drivers/misc/mei/hdcp/mei_hdcp.h | 408 +++
1 file changed, 408 insertions(+)
create mode 100644 drivers/misc/mei/hdcp/mei_hdcp.h
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.h b/drivers/misc/mei/hdcp/mei_hdcp.h
new file mode 100644
index ..b201cd1ffda4
--- /dev/null
+++ b/drivers/misc/mei/hdcp/mei_hdcp.h
@@ -0,0 +1,408 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright © 2017-2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Ramalingam C
+ */
+
+#ifndef __MEI_HDCP_H__
+#define __MEI_HDCP_H__
+
+#include
+
+/*
+ * me_hdcp_status: Enumeration of all HDCP Status Codes
+ */
+enum me_hdcp_status {
+ ME_HDCP_STATUS_SUCCESS = 0x,
+
+ /* WiDi Generic Status Codes */
+ ME_HDCP_STATUS_INTERNAL_ERROR = 0x1000,
+ ME_HDCP_STATUS_UNKNOWN_ERROR= 0x1001,
+ ME_HDCP_STATUS_INCORRECT_API_VERSION= 0x1002,
+ ME_HDCP_STATUS_INVALID_FUNCTION = 0x1003,
+ ME_HDCP_STATUS_INVALID_BUFFER_LENGTH= 0x1004,
+ ME_HDCP_STATUS_INVALID_PARAMS = 0x1005,
+ ME_HDCP_STATUS_AUTHENTICATION_FAILED= 0x1006,
+
+ /* WiDi Status Codes */
+ ME_HDCP_INVALID_SESSION_STATE = 0x6000,
+ ME_HDCP_SRM_FRAGMENT_UNEXPECTED = 0x6001,
+ ME_HDCP_SRM_INVALID_LENGTH = 0x6002,
+ ME_HDCP_SRM_FRAGMENT_OFFSET_INVALID = 0x6003,
+ ME_HDCP_SRM_VERIFICATION_FAILED = 0x6004,
+ ME_HDCP_SRM_VERSION_TOO_OLD = 0x6005,
+ ME_HDCP_RX_CERT_VERIFICATION_FAILED = 0x6006,
+ ME_HDCP_RX_REVOKED = 0x6007,
+ ME_HDCP_H_VERIFICATION_FAILED = 0x6008,
+ ME_HDCP_REPEATER_CHECK_UNEXPECTED = 0x6009,
+ ME_HDCP_TOPOLOGY_MAX_EXCEEDED = 0x600A,
+ ME_HDCP_V_VERIFICATION_FAILED = 0x600B,
+ ME_HDCP_L_VERIFICATION_FAILED = 0x600C,
+ ME_HDCP_STREAM_KEY_ALLOC_FAILED = 0x600D,
+ ME_HDCP_BASE_KEY_RESET_FAILED = 0x600E,
+ ME_HDCP_NONCE_GENERATION_FAILED = 0x600F,
+ ME_HDCP_STATUS_INVALID_E_KEY_STATE = 0x6010,
+ ME_HDCP_STATUS_INVALID_CS_ICV = 0x6011,
+ ME_HDCP_STATUS_INVALID_KB_KEY_STATE = 0x6012,
+ ME_HDCP_STATUS_INVALID_PAVP_MODE_ICV= 0x6013,
+ ME_HDCP_STATUS_INVALID_PAVP_MODE= 0x6014,
+ ME_HDCP_STATUS_LC_MAX_ATTEMPTS = 0x6015,
+
+ /* New status for HDCP 2.1 */
+ ME_HDCP_STATUS_MISMATCH_IN_M= 0x6016,
+
+ /* New status code for HDCP 2.2 Rx */
+ ME_HDCP_STATUS_RX_PROV_NOT_ALLOWED = 0x6017,
+ ME_HDCP_STATUS_RX_PROV_WRONG_SUBJECT= 0x6018,
+ ME_HDCP_RX_NEEDS_PROVISIONING = 0x6019,
+ ME_HDCP_BKSV_ICV_AUTH_FAILED= 0x6020,
+ ME_HDCP_STATUS_INVALID_STREAM_ID= 0x6021,
+ ME_HDCP_STATUS_CHAIN_NOT_INITIALIZED= 0x6022,
+ ME_HDCP_FAIL_NOT_EXPECTED = 0x6023,
+ ME_HDCP_FAIL_HDCP_OFF = 0x6024,
+ ME_HDCP_FAIL_INVALID_PAVP_MEMORY_MODE = 0x6025,
+ ME_HDCP_FAIL_AES_ECB_FAILURE= 0x6026,
+ ME_HDCP_FEATURE_NOT_SUPPORTED = 0x6027,
+ ME_HDCP_DMA_READ_ERROR = 0x6028,
+ ME_HDCP_DMA_WRITE_ERROR = 0x6029,
+ ME_HDCP_FAIL_INVALID_PACKET_SIZE= 0x6030,
+ ME_HDCP_H264_PARSING_ERROR = 0x6031,
+ ME_HDC
[Intel-gfx] [PATCH v5 32/40] misc/mei/hdcp: Verify H_prime
Requests for the verification of AKE_Send_H_prime.
ME will calculate the H and comparing it with received H_Prime.
The result will be returned as status.
Here AKE_Send_H_prime is a HDCP2.2 Authentication msg.
v2:
Rebased.
v3:
cldev is passed as first parameter [Tomas]
Redundant comments and cast are removed [Tomas]
v4:
%zd for ssize_t [Alexander]
%s/return -1/return -EIO [Alexander]
Styles and typos fixed [Uma]
v5:
Rebased.
Signed-off-by: Ramalingam C
---
drivers/misc/mei/hdcp/mei_hdcp.c | 61 +++-
1 file changed, 60 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index fb717a7ff249..fb8b7ed889f5 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -187,12 +187,71 @@ mei_verify_receiver_cert_prepare_km(struct mei_cl_device
*cldev,
return 0;
}
+/*
+ * mei_verify_hprime:
+ * Function to verify AKE_Send_H_prime received, through ME FW.
+ *
+ * cldev : Pointer for mei client device
+ * data: Intel HW specific Data
+ * rx_hprime : Pointer for AKE_Send_H_prime
+ * hprime_sz : Input buffer size
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+static int mei_verify_hprime(struct mei_cl_device *cldev,
+struct mei_hdcp_data *data,
+struct hdcp2_ake_send_hprime *rx_hprime)
+{
+ struct wired_cmd_ake_send_hprime_in send_hprime_in = { { 0 } };
+ struct wired_cmd_ake_send_hprime_out send_hprime_out = { { 0 } };
+ struct device *dev;
+ ssize_t byte;
+
+ if (!data || !rx_hprime)
+ return -EINVAL;
+
+ dev = &cldev->dev;
+
+ send_hprime_in.header.api_version = HDCP_API_VERSION;
+ send_hprime_in.header.command_id = WIRED_AKE_SEND_HPRIME;
+ send_hprime_in.header.status = ME_HDCP_STATUS_SUCCESS;
+ send_hprime_in.header.buffer_len = WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_IN;
+
+ send_hprime_in.port.integrated_port_type = data->port_type;
+ send_hprime_in.port.physical_port = data->port;
+
+ memcpy(send_hprime_in.h_prime, rx_hprime->h_prime,
+ sizeof(rx_hprime->h_prime));
+
+ byte = mei_cldev_send(cldev, (u8 *)&send_hprime_in,
+ sizeof(send_hprime_in));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ byte = mei_cldev_recv(cldev, (u8 *)&send_hprime_out,
+ sizeof(send_hprime_out));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ if (send_hprime_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+ dev_dbg(dev, "ME cmd 0x%08X Failed. Status: 0x%X\n",
+ WIRED_AKE_SEND_HPRIME, send_hprime_out.header.status);
+ return -EIO;
+ }
+
+ return 0;
+}
+
struct i915_hdcp_component_ops mei_hdcp_component_ops = {
.owner = THIS_MODULE,
.initiate_hdcp2_session = mei_initiate_hdcp2_session,
.verify_receiver_cert_prepare_km=
mei_verify_receiver_cert_prepare_km,
- .verify_hprime = NULL,
+ .verify_hprime = mei_verify_hprime,
.store_pairing_info = NULL,
.initiate_locality_check= NULL,
.verify_lprime = NULL,
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 31/40] misc/mei/hdcp: Verify Receiver Cert and prepare km
Requests for verification for receiver certification and also the
preparation for next AKE auth message with km.
On Success ME FW validate the HDCP2.2 receivers certificate and do the
revocation check on the receiver ID. AKE_Stored_Km will be prepared if
the receiver is already paired, else AKE_No_Stored_Km will be prepared.
Here AKE_Stored_Km and AKE_No_Stored_Km are HDCP2.2 protocol msgs.
v2:
Rebased.
v3:
cldev is passed as first parameter [Tomas]
Redundant comments and cast are removed [Tomas]
v4:
%zd is used for ssize_t [Alexander]
%s/return -1/return -EIO [Alexander]
v5:
Rebased.
Signed-off-by: Ramalingam C
---
drivers/misc/mei/hdcp/mei_hdcp.c | 85 +++-
1 file changed, 84 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 7311e3095e94..fb717a7ff249 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -105,10 +105,93 @@ static int mei_initiate_hdcp2_session(struct
mei_cl_device *cldev,
return 0;
}
+/*
+ * mei_verify_receiver_cert_prepare_km:
+ * Function to verify the Receiver Certificate AKE_Send_Cert
+ * and prepare AKE_Stored_Km or AKE_No_Stored_Km
+ *
+ * cldev : Pointer for mei client device
+ * data: Intel HW specific Data
+ * rx_cert : Pointer for AKE_Send_Cert
+ * km_stored : Pointer for pairing status flag
+ * ek_pub_km : Pointer for output msg
+ * msg_sz : Pointer for size of AKE_X_Km
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+static int
+mei_verify_receiver_cert_prepare_km(struct mei_cl_device *cldev,
+ struct mei_hdcp_data *data,
+ struct hdcp2_ake_send_cert *rx_cert,
+ bool *km_stored,
+ struct hdcp2_ake_no_stored_km *ek_pub_km,
+ size_t *msg_sz)
+{
+ struct wired_cmd_verify_receiver_cert_in verify_rxcert_in = { { 0 } };
+ struct wired_cmd_verify_receiver_cert_out verify_rxcert_out = { { 0 } };
+ struct device *dev;
+ ssize_t byte;
+
+ if (!data || !rx_cert || !km_stored || !ek_pub_km || !msg_sz)
+ return -EINVAL;
+
+ dev = &cldev->dev;
+
+ verify_rxcert_in.header.api_version = HDCP_API_VERSION;
+ verify_rxcert_in.header.command_id = WIRED_VERIFY_RECEIVER_CERT;
+ verify_rxcert_in.header.status = ME_HDCP_STATUS_SUCCESS;
+ verify_rxcert_in.header.buffer_len =
+ WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_IN;
+
+ verify_rxcert_in.port.integrated_port_type = data->port_type;
+ verify_rxcert_in.port.physical_port = data->port;
+
+ memcpy(&verify_rxcert_in.cert_rx, &rx_cert->cert_rx,
+ sizeof(rx_cert->cert_rx));
+ memcpy(verify_rxcert_in.r_rx, &rx_cert->r_rx, sizeof(rx_cert->r_rx));
+ memcpy(verify_rxcert_in.rx_caps, rx_cert->rx_caps, HDCP_2_2_RXCAPS_LEN);
+
+ byte = mei_cldev_send(cldev, (u8 *)&verify_rxcert_in,
+ sizeof(verify_rxcert_in));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed: %zd\n", byte);
+ return byte;
+ }
+
+ byte = mei_cldev_recv(cldev, (u8 *)&verify_rxcert_out,
+ sizeof(verify_rxcert_out));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed: %zd\n", byte);
+ return byte;
+ }
+
+ if (verify_rxcert_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+ dev_dbg(dev, "ME cmd 0x%08X Failed. Status: 0x%X\n",
+ WIRED_VERIFY_RECEIVER_CERT,
+ verify_rxcert_out.header.status);
+ return -EIO;
+ }
+
+ *km_stored = verify_rxcert_out.km_stored;
+ if (verify_rxcert_out.km_stored) {
+ ek_pub_km->msg_id = HDCP_2_2_AKE_STORED_KM;
+ *msg_sz = sizeof(struct hdcp2_ake_stored_km);
+ } else {
+ ek_pub_km->msg_id = HDCP_2_2_AKE_NO_STORED_KM;
+ *msg_sz = sizeof(struct hdcp2_ake_no_stored_km);
+ }
+
+ memcpy(ek_pub_km->e_kpub_km, &verify_rxcert_out.ekm_buff,
+ sizeof(verify_rxcert_out.ekm_buff));
+
+ return 0;
+}
+
struct i915_hdcp_component_ops mei_hdcp_component_ops = {
.owner = THIS_MODULE,
.initiate_hdcp2_session = mei_initiate_hdcp2_session,
- .verify_receiver_cert_prepare_km= NULL,
+ .verify_receiver_cert_prepare_km=
+ mei_verify_receiver_cert_prepare_km,
.verify_hprime = NULL,
.store_pairing_info = NULL,
.initiate_locality_check= NULL,
--
2.7.4
___
[Intel-gfx] [PATCH v5 33/40] misc/mei/hdcp: Store the HDCP Pairing info
Provides Pairing info to ME to store.
Pairing is a process to fast track the subsequent authentication
with the same HDCP sink.
On Success, received HDCP pairing info is stored in non-volatile
memory of ME.
v2:
Rebased.
v3:
cldev is passed as first parameter [Tomas]
Redundant comments and cast are removed [Tomas]
v4:
%zd for ssize_t [Alexander]
%s/return -1/return -EIO [Alexander]
Style fixed [Uma]
v5:
Rebased.
Signed-off-by: Ramalingam C
---
drivers/misc/mei/hdcp/mei_hdcp.c | 63 +++-
1 file changed, 62 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index fb8b7ed889f5..7c833378bc60 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -246,13 +246,74 @@ static int mei_verify_hprime(struct mei_cl_device *cldev,
return 0;
}
+/*
+ * mei_store_pairing_info:
+ * Function to store pairing info received from panel
+ *
+ * cldev : Pointer for mei client device
+ * data: Intel HW specific Data
+ * pairing_info: Pointer for AKE_Send_Pairing_Info
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+static int
+mei_store_pairing_info(struct mei_cl_device *cldev,
+ struct mei_hdcp_data *data,
+ struct hdcp2_ake_send_pairing_info *pairing_info)
+{
+ struct wired_cmd_ake_send_pairing_info_in pairing_info_in = { { 0 } };
+ struct wired_cmd_ake_send_pairing_info_out pairing_info_out = { { 0 } };
+ struct device *dev;
+ ssize_t byte;
+
+ if (!data || !pairing_info)
+ return -EINVAL;
+
+ dev = &cldev->dev;
+
+ pairing_info_in.header.api_version = HDCP_API_VERSION;
+ pairing_info_in.header.command_id = WIRED_AKE_SEND_PAIRING_INFO;
+ pairing_info_in.header.status = ME_HDCP_STATUS_SUCCESS;
+ pairing_info_in.header.buffer_len =
+ WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_IN;
+
+ pairing_info_in.port.integrated_port_type = data->port_type;
+ pairing_info_in.port.physical_port = data->port;
+
+ memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km,
+ sizeof(pairing_info_in.e_kh_km));
+
+ byte = mei_cldev_send(cldev, (u8 *)&pairing_info_in,
+ sizeof(pairing_info_in));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ byte = mei_cldev_recv(cldev, (u8 *)&pairing_info_out,
+ sizeof(pairing_info_out));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ if (pairing_info_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+ dev_dbg(dev, "ME cmd 0x%08X failed. Status: 0x%X\n",
+ WIRED_AKE_SEND_PAIRING_INFO,
+ pairing_info_out.header.status);
+ return -EIO;
+ }
+
+ return 0;
+}
+
struct i915_hdcp_component_ops mei_hdcp_component_ops = {
.owner = THIS_MODULE,
.initiate_hdcp2_session = mei_initiate_hdcp2_session,
.verify_receiver_cert_prepare_km=
mei_verify_receiver_cert_prepare_km,
.verify_hprime = mei_verify_hprime,
- .store_pairing_info = NULL,
+ .store_pairing_info = mei_store_pairing_info,
.initiate_locality_check= NULL,
.verify_lprime = NULL,
.get_session_key= NULL,
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 37/40] misc/mei/hdcp: Repeater topology verification and ack
Request ME to verify the downstream topology information received.
ME FW will validate the Repeaters receiver id list and
downstream topology.
On Success ME FW will provide the Least Significant
128bits of VPrime, which forms the repeater ack.
v2:
Rebased.
v3:
cldev is passed as first parameter [Tomas]
Redundant comments and cast are removed [Tomas]
v4:
%zd for ssize_t [Alexander]
%s/return -1/return -EIO [Alexander]
Style and typos fixed [Uma]
v5:
Rebased.
Signed-off-by: Ramalingam C
---
drivers/misc/mei/hdcp/mei_hdcp.c | 77 +++-
1 file changed, 76 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 8a065f17d6c9..1fa668a5f437 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -482,6 +482,80 @@ static int mei_get_session_key(struct mei_cl_device *cldev,
return 0;
}
+/*
+ * mei_repeater_check_flow_prepare_ack:
+ * Function to validate the Downstream topology and prepare rep_ack.
+ *
+ * cldev : Pointer for mei client device
+ * data: Intel HW specific Data
+ * rep_topology: Pointer for Receiver Id List to be validated.
+ * rep_send_ack: Pointer for repeater ack
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+static int
+mei_repeater_check_flow_prepare_ack(struct mei_cl_device *cldev,
+ struct mei_hdcp_data *data,
+ struct hdcp2_rep_send_receiverid_list
+ *rep_topology,
+ struct hdcp2_rep_send_ack *rep_send_ack)
+{
+ struct wired_cmd_verify_repeater_in verify_repeater_in = { { 0 } };
+ struct wired_cmd_verify_repeater_out verify_repeater_out = { { 0 } };
+ struct device *dev;
+ ssize_t byte;
+
+ if (!rep_topology || !rep_send_ack || !data)
+ return -EINVAL;
+
+ dev = &cldev->dev;
+
+ verify_repeater_in.header.api_version = HDCP_API_VERSION;
+ verify_repeater_in.header.command_id = WIRED_VERIFY_REPEATER;
+ verify_repeater_in.header.status = ME_HDCP_STATUS_SUCCESS;
+ verify_repeater_in.header.buffer_len =
+ WIRED_CMD_BUF_LEN_VERIFY_REPEATER_IN;
+
+ verify_repeater_in.port.integrated_port_type = data->port_type;
+ verify_repeater_in.port.physical_port = data->port;
+
+ memcpy(verify_repeater_in.rx_info, rep_topology->rx_info,
+ HDCP_2_2_RXINFO_LEN);
+ memcpy(verify_repeater_in.seq_num_v, rep_topology->seq_num_v,
+ HDCP_2_2_SEQ_NUM_LEN);
+ memcpy(verify_repeater_in.v_prime, rep_topology->v_prime,
+ HDCP_2_2_LPRIME_HALF_LEN);
+ memcpy(verify_repeater_in.receiver_ids, rep_topology->receiver_ids,
+ HDCP_2_2_RECEIVER_IDS_MAX_LEN);
+
+ byte = mei_cldev_send(cldev, (u8 *)&verify_repeater_in,
+ sizeof(verify_repeater_in));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ byte = mei_cldev_recv(cldev, (u8 *)&verify_repeater_out,
+ sizeof(verify_repeater_out));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ if (verify_repeater_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+ dev_dbg(dev, "ME cmd 0x%08X failed. status: 0x%X\n",
+ WIRED_VERIFY_REPEATER,
+ verify_repeater_out.header.status);
+ return -EIO;
+ }
+
+ memcpy(rep_send_ack->v, verify_repeater_out.v,
+ HDCP_2_2_LPRIME_HALF_LEN);
+ rep_send_ack->msg_id = HDCP_2_2_REP_SEND_ACK;
+
+ return 0;
+}
+
struct i915_hdcp_component_ops mei_hdcp_component_ops = {
.owner = THIS_MODULE,
.initiate_hdcp2_session = mei_initiate_hdcp2_session,
@@ -492,7 +566,8 @@ struct i915_hdcp_component_ops mei_hdcp_component_ops = {
.initiate_locality_check= mei_initiate_locality_check,
.verify_lprime = mei_verify_lprime,
.get_session_key= mei_get_session_key,
- .repeater_check_flow_prepare_ack= NULL,
+ .repeater_check_flow_prepare_ack=
+ mei_repeater_check_flow_prepare_ack,
.verify_mprime = NULL,
.enable_hdcp_authentication = NULL,
.close_hdcp_session = NULL,
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 36/40] misc/mei/hdcp: Prepare Session Key
Request to ME to prepare the encrypted session key.
On Success, ME provides Encrypted session key. Function populates
the HDCP2.2 authentication msg SKE_Send_Eks.
v2:
Rebased.
v3:
cldev is passed as first parameter [Tomas]
Redundant comments and cast are removed [Tomas]
v4:
%zd for ssize_t [Alexander]
%s/return -1/return -EIO [Alexander]
Style fixed [Uma]
v5:
Rebased.
Signed-off-by: Ramalingam C
---
drivers/misc/mei/hdcp/mei_hdcp.c | 62 ++--
1 file changed, 60 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index de8ffb589ca4..8a065f17d6c9 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -423,6 +423,65 @@ static int mei_verify_lprime(struct mei_cl_device *cldev,
return 0;
}
+/*
+ * mei_get_session_key:
+ * Function to prepare SKE_Send_Eks.
+ *
+ * cldev : Pointer for mei client device
+ * data: Intel HW specific Data
+ * ske_data: Pointer for SKE_Send_Eks.
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+static int mei_get_session_key(struct mei_cl_device *cldev,
+ struct mei_hdcp_data *data,
+ struct hdcp2_ske_send_eks *ske_data)
+{
+ struct wired_cmd_get_session_key_in get_skey_in = { { 0 } };
+ struct wired_cmd_get_session_key_out get_skey_out = { { 0 } };
+ struct device *dev;
+ ssize_t byte;
+
+ if (!data || !ske_data)
+ return -EINVAL;
+
+ dev = &cldev->dev;
+
+ get_skey_in.header.api_version = HDCP_API_VERSION;
+ get_skey_in.header.command_id = WIRED_GET_SESSION_KEY;
+ get_skey_in.header.status = ME_HDCP_STATUS_SUCCESS;
+ get_skey_in.header.buffer_len = WIRED_CMD_BUF_LEN_GET_SESSION_KEY_IN;
+
+ get_skey_in.port.integrated_port_type = data->port_type;
+ get_skey_in.port.physical_port = data->port;
+
+ byte = mei_cldev_send(cldev, (u8 *)&get_skey_in, sizeof(get_skey_in));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ byte = mei_cldev_recv(cldev, (u8 *)&get_skey_out, sizeof(get_skey_out));
+
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ if (get_skey_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+ dev_dbg(dev, "ME cmd 0x%08X failed. status: 0x%X\n",
+ WIRED_GET_SESSION_KEY, get_skey_out.header.status);
+ return -EIO;
+ }
+
+ ske_data->msg_id = HDCP_2_2_SKE_SEND_EKS;
+ memcpy(ske_data->e_dkey_ks, get_skey_out.e_dkey_ks,
+ HDCP_2_2_E_DKEY_KS_LEN);
+ memcpy(ske_data->riv, get_skey_out.r_iv, HDCP_2_2_RIV_LEN);
+
+ return 0;
+}
+
struct i915_hdcp_component_ops mei_hdcp_component_ops = {
.owner = THIS_MODULE,
.initiate_hdcp2_session = mei_initiate_hdcp2_session,
@@ -432,7 +491,7 @@ struct i915_hdcp_component_ops mei_hdcp_component_ops = {
.store_pairing_info = mei_store_pairing_info,
.initiate_locality_check= mei_initiate_locality_check,
.verify_lprime = mei_verify_lprime,
- .get_session_key= NULL,
+ .get_session_key= mei_get_session_key,
.repeater_check_flow_prepare_ack= NULL,
.verify_mprime = NULL,
.enable_hdcp_authentication = NULL,
@@ -441,7 +500,6 @@ struct i915_hdcp_component_ops mei_hdcp_component_ops = {
static int mei_hdcp_component_bind(struct device *mei_kdev,
struct device *i915_kdev, void *data)
-
{
struct i915_hdcp_component *comp = data;
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 35/40] misc/mei/hdcp: Verify L_prime
Request to ME to verify the LPrime received from HDCP sink.
On Success, ME FW will verify the received Lprime by calculating and
comparing with L.
This represents the completion of Locality Check.
v2:
Rebased.
v3:
cldev is passed as first parameter [Tomas]
Redundant comments and cast are removed [Tomas]
v4:
%zd for ssize_t [Alexander]
%s/return -1/return -EIO [Alexander]
Style fixed [Uma]
v5:
Rebased.
Signed-off-by: Ramalingam C
---
drivers/misc/mei/hdcp/mei_hdcp.c | 63 +++-
1 file changed, 62 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 2a0369f46326..de8ffb589ca4 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -363,6 +363,66 @@ static int mei_initiate_locality_check(struct
mei_cl_device *cldev,
return 0;
}
+/*
+ * mei_verify_lprime:
+ * Function to verify lprime.
+ *
+ * cldev : Pointer for mei client device
+ * data: Intel HW specific Data
+ * rx_lprime : Pointer for LC_Send_L_prime
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+static int mei_verify_lprime(struct mei_cl_device *cldev,
+struct mei_hdcp_data *data,
+struct hdcp2_lc_send_lprime *rx_lprime)
+{
+ struct wired_cmd_validate_locality_in verify_lprime_in = { { 0 } };
+ struct wired_cmd_validate_locality_out verify_lprime_out = { { 0 } };
+ struct device *dev;
+ ssize_t byte;
+
+ if (!data || !rx_lprime)
+ return -EINVAL;
+
+ dev = &cldev->dev;
+
+ verify_lprime_in.header.api_version = HDCP_API_VERSION;
+ verify_lprime_in.header.command_id = WIRED_VALIDATE_LOCALITY;
+ verify_lprime_in.header.status = ME_HDCP_STATUS_SUCCESS;
+ verify_lprime_in.header.buffer_len =
+ WIRED_CMD_BUF_LEN_VALIDATE_LOCALITY_IN;
+
+ verify_lprime_in.port.integrated_port_type = data->port_type;
+ verify_lprime_in.port.physical_port = data->port;
+
+ memcpy(verify_lprime_in.l_prime, rx_lprime->l_prime,
+ sizeof(rx_lprime->l_prime));
+
+ byte = mei_cldev_send(cldev, (u8 *)&verify_lprime_in,
+ sizeof(verify_lprime_in));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ byte = mei_cldev_recv(cldev, (u8 *)&verify_lprime_out,
+ sizeof(verify_lprime_out));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ if (verify_lprime_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+ dev_dbg(dev, "ME cmd 0x%08X failed. status: 0x%X\n",
+ WIRED_VALIDATE_LOCALITY,
+ verify_lprime_out.header.status);
+ return -EIO;
+ }
+
+ return 0;
+}
+
struct i915_hdcp_component_ops mei_hdcp_component_ops = {
.owner = THIS_MODULE,
.initiate_hdcp2_session = mei_initiate_hdcp2_session,
@@ -371,7 +431,7 @@ struct i915_hdcp_component_ops mei_hdcp_component_ops = {
.verify_hprime = mei_verify_hprime,
.store_pairing_info = mei_store_pairing_info,
.initiate_locality_check= mei_initiate_locality_check,
- .verify_lprime = NULL,
+ .verify_lprime = mei_verify_lprime,
.get_session_key= NULL,
.repeater_check_flow_prepare_ack= NULL,
.verify_mprime = NULL,
@@ -381,6 +441,7 @@ struct i915_hdcp_component_ops mei_hdcp_component_ops = {
static int mei_hdcp_component_bind(struct device *mei_kdev,
struct device *i915_kdev, void *data)
+
{
struct i915_hdcp_component *comp = data;
--
2.7.4
___
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[Intel-gfx] [PATCH v5 39/40] misc/mei/hdcp: Enabling the HDCP authentication
Request to ME to configure a port as authenticated.
On Success, ME FW will mark the port as authenticated and provides
HDCP cipher with the encryption keys.
Enabling the Authentication can be requested once all stages of
HDCP2.2 authentication is completed by interacting with ME FW.
Only after this stage, driver can enable the HDCP encryption for
the port, through HW registers.
v2:
Rebased.
v3:
cldev is passed as first parameter [Tomas]
Redundant comments and cast are removed [Tomas]
v4:
%zd for ssize_t [Alexander]
%s/return -1/return -EIO [Alexander]
Style and typos fixed [Uma]
v5:
Rebased.
Signed-off-by: Ramalingam C
---
drivers/misc/mei/hdcp/mei_hdcp.c | 57 +++-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 3ff4de75ff21..c3d97a848c67 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -624,6 +624,60 @@ static int mei_verify_mprime(struct mei_cl_device *cldev,
return 0;
}
+/*
+ * mei_enable_hdcp_authentication:
+ * Function to request ME FW to mark a port as authenticated.
+ *
+ * cldev : Pointer for mei client device
+ * data: Intel HW specific Data
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+static int mei_enable_hdcp_authentication(struct mei_cl_device *cldev,
+ struct mei_hdcp_data *data)
+{
+ struct wired_cmd_enable_auth_in enable_auth_in = { { 0 } };
+ struct wired_cmd_enable_auth_out enable_auth_out = { { 0 } };
+ struct device *dev;
+ ssize_t byte;
+
+ if (!data)
+ return -EINVAL;
+
+ dev = &cldev->dev;
+
+ enable_auth_in.header.api_version = HDCP_API_VERSION;
+ enable_auth_in.header.command_id = WIRED_ENABLE_AUTH;
+ enable_auth_in.header.status = ME_HDCP_STATUS_SUCCESS;
+ enable_auth_in.header.buffer_len = WIRED_CMD_BUF_LEN_ENABLE_AUTH_IN;
+
+ enable_auth_in.port.integrated_port_type = data->port_type;
+ enable_auth_in.port.physical_port = data->port;
+ enable_auth_in.stream_type = data->streams[0].stream_type;
+
+ byte = mei_cldev_send(cldev, (u8 *)&enable_auth_in,
+ sizeof(enable_auth_in));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ byte = mei_cldev_recv(cldev, (u8 *)&enable_auth_out,
+ sizeof(enable_auth_out));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ if (enable_auth_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+ dev_dbg(dev, "ME cmd 0x%08X failed. status: 0x%X\n",
+ WIRED_ENABLE_AUTH, enable_auth_out.header.status);
+ return -EIO;
+ }
+
+ return 0;
+}
+
struct i915_hdcp_component_ops mei_hdcp_component_ops = {
.owner = THIS_MODULE,
.initiate_hdcp2_session = mei_initiate_hdcp2_session,
@@ -637,7 +691,8 @@ struct i915_hdcp_component_ops mei_hdcp_component_ops = {
.repeater_check_flow_prepare_ack=
mei_repeater_check_flow_prepare_ack,
.verify_mprime = mei_verify_mprime,
- .enable_hdcp_authentication = NULL,
+ .enable_hdcp_authentication =
+ mei_enable_hdcp_authentication,
.close_hdcp_session = NULL,
};
--
2.7.4
___
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[Intel-gfx] [PATCH v5 38/40] misc/mei/hdcp: Verify M_prime
Request to ME to verify the M_Prime received from the HDCP sink.
ME FW will calculate the M and compare with M_prime received
as part of RepeaterAuth_Stream_Ready, which is HDCP2.2 protocol msg.
On successful completion of this stage, downstream propagation of
the stream management info is completed.
v2:
Rebased.
v3:
cldev is passed as first parameter [Tomas]
Redundant comments and cast are removed [Tomas]
v4:
%zd for ssize_t [Alexander]
%s/return -1/return -EIO [Alexander]
endianness conversion func is moved to drm_hdcp.h [Uma]
v5:
Rebased.
Signed-off-by: Ramalingam C
---
drivers/misc/mei/hdcp/mei_hdcp.c | 70 +++-
1 file changed, 69 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 1fa668a5f437..3ff4de75ff21 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -556,6 +556,74 @@ mei_repeater_check_flow_prepare_ack(struct mei_cl_device
*cldev,
return 0;
}
+/*
+ * mei_verify_mprime:
+ * Function to verify mprime.
+ *
+ * cldev : Pointer for mei client device
+ * data: Intel HW specific Data
+ * stream_ready: pointer for RepeaterAuth_Stream_Ready message.
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+static int mei_verify_mprime(struct mei_cl_device *cldev,
+struct mei_hdcp_data *data,
+struct hdcp2_rep_stream_ready *stream_ready)
+{
+ struct wired_cmd_repeater_auth_stream_req_in
+ verify_mprime_in = { { 0 } };
+ struct wired_cmd_repeater_auth_stream_req_out
+ verify_mprime_out = { { 0 } };
+ struct device *dev;
+ ssize_t byte;
+
+ if (!stream_ready || !data)
+ return -EINVAL;
+
+ dev = &cldev->dev;
+
+ verify_mprime_in.header.api_version = HDCP_API_VERSION;
+ verify_mprime_in.header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ;
+ verify_mprime_in.header.status = ME_HDCP_STATUS_SUCCESS;
+ verify_mprime_in.header.buffer_len =
+ WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN;
+
+ verify_mprime_in.port.integrated_port_type = data->port_type;
+ verify_mprime_in.port.physical_port = data->port;
+
+ memcpy(verify_mprime_in.m_prime, stream_ready->m_prime,
+ HDCP_2_2_MPRIME_LEN);
+ reverse_endianness((u8 *)&verify_mprime_in.seq_num_m,
+ HDCP_2_2_SEQ_NUM_LEN, (u8 *)&data->seq_num_m);
+ memcpy(verify_mprime_in.streams, data->streams,
+ (data->k * sizeof(struct hdcp2_streamid_type)));
+
+ verify_mprime_in.k = __swab16(data->k);
+
+ byte = mei_cldev_send(cldev, (u8 *)&verify_mprime_in,
+ sizeof(verify_mprime_in));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ byte = mei_cldev_recv(cldev, (u8 *)&verify_mprime_out,
+ sizeof(verify_mprime_out));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ if (verify_mprime_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+ dev_dbg(dev, "ME cmd 0x%08X failed. status: 0x%X\n",
+ WIRED_REPEATER_AUTH_STREAM_REQ,
+ verify_mprime_out.header.status);
+ return -EIO;
+ }
+
+ return 0;
+}
+
struct i915_hdcp_component_ops mei_hdcp_component_ops = {
.owner = THIS_MODULE,
.initiate_hdcp2_session = mei_initiate_hdcp2_session,
@@ -568,7 +636,7 @@ struct i915_hdcp_component_ops mei_hdcp_component_ops = {
.get_session_key= mei_get_session_key,
.repeater_check_flow_prepare_ack=
mei_repeater_check_flow_prepare_ack,
- .verify_mprime = NULL,
+ .verify_mprime = mei_verify_mprime,
.enable_hdcp_authentication = NULL,
.close_hdcp_session = NULL,
};
--
2.7.4
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[Intel-gfx] [PATCH v5 34/40] misc/mei/hdcp: Initiate Locality check
Requests ME to start the second stage of HDCP2.2 authentication,
called Locality Check.
On Success, ME FW will provide LC_Init message to send to hdcp sink.
v2:
Rebased.
v3:
cldev is passed as first parameter [Tomas]
Redundant comments and cast are removed [Tomas]
v4:
%zd used for ssize_t [Alexander]
%s/return -1/return -EIO [Alexander]
Style fixed [Uma]
v5:
Rebased.
Signed-off-by: Ramalingam C
---
drivers/misc/mei/hdcp/mei_hdcp.c | 58 +++-
1 file changed, 57 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 7c833378bc60..2a0369f46326 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -307,6 +307,62 @@ mei_store_pairing_info(struct mei_cl_device *cldev,
return 0;
}
+/*
+ * mei_initiate_locality_check:
+ * Function to prepare LC_Init.
+ *
+ * cldev : Pointer for mei client device
+ * data: Intel HW specific Data
+ * hdcp2_lc_init : Pointer for storing LC_Init
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+static int mei_initiate_locality_check(struct mei_cl_device *cldev,
+ struct mei_hdcp_data *data,
+ struct hdcp2_lc_init *lc_init_data)
+{
+ struct wired_cmd_init_locality_check_in lc_init_in = { { 0 } };
+ struct wired_cmd_init_locality_check_out lc_init_out = { { 0 } };
+ struct device *dev;
+ ssize_t byte;
+
+ if (!data || !lc_init_data)
+ return -EINVAL;
+
+ dev = &cldev->dev;
+
+ lc_init_in.header.api_version = HDCP_API_VERSION;
+ lc_init_in.header.command_id = WIRED_INIT_LOCALITY_CHECK;
+ lc_init_in.header.status = ME_HDCP_STATUS_SUCCESS;
+ lc_init_in.header.buffer_len = WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_IN;
+
+ lc_init_in.port.integrated_port_type = data->port_type;
+ lc_init_in.port.physical_port = data->port;
+
+ byte = mei_cldev_send(cldev, (u8 *)&lc_init_in, sizeof(lc_init_in));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ byte = mei_cldev_recv(cldev, (u8 *)&lc_init_out, sizeof(lc_init_out));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ if (lc_init_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+ dev_dbg(dev, "ME cmd 0x%08X Failed. status: 0x%X\n",
+ WIRED_INIT_LOCALITY_CHECK, lc_init_out.header.status);
+ return -EIO;
+ }
+
+ lc_init_data->msg_id = HDCP_2_2_LC_INIT;
+ memcpy(lc_init_data->r_n, lc_init_out.r_n, HDCP_2_2_RN_LEN);
+
+ return 0;
+}
+
struct i915_hdcp_component_ops mei_hdcp_component_ops = {
.owner = THIS_MODULE,
.initiate_hdcp2_session = mei_initiate_hdcp2_session,
@@ -314,7 +370,7 @@ struct i915_hdcp_component_ops mei_hdcp_component_ops = {
mei_verify_receiver_cert_prepare_km,
.verify_hprime = mei_verify_hprime,
.store_pairing_info = mei_store_pairing_info,
- .initiate_locality_check= NULL,
+ .initiate_locality_check= mei_initiate_locality_check,
.verify_lprime = NULL,
.get_session_key= NULL,
.repeater_check_flow_prepare_ack= NULL,
--
2.7.4
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[Intel-gfx] [PATCH v5 40/40] misc/mei/hdcp: Closing wired HDCP2.2 Tx Session
Request the ME to terminate the HDCP2.2 session for a port.
On Success, ME FW will mark the intel port as Deauthenticated and
terminate the wired HDCP2.2 Tx session started due to the cmd
WIRED_INITIATE_HDCP2_SESSION.
v2:
Rebased.
v3:
cldev is passed as first parameter [Tomas]
Redundant comments and cast are removed [Tomas]
v4:
%zd for ssize_t [Alexander]
%s/return -1/return -EIO [Alexander]
Style and typos fixed [Uma]
v5:
Extra line is removed.
Signed-off-by: Ramalingam C
---
drivers/misc/mei/hdcp/mei_hdcp.c | 56 +++-
1 file changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index c3d97a848c67..8f5797e2eb51 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -678,6 +678,60 @@ static int mei_enable_hdcp_authentication(struct
mei_cl_device *cldev,
return 0;
}
+/*
+ * mei_close_hdcp_session:
+ * Function to close the Wired HDCP Tx session of ME FW.
+ * This also disables the authenticated state of the port.
+ *
+ * data: Intel HW specific Data
+ *
+ * Returns 0 on Success, <0 on Failure
+ */
+static int mei_close_hdcp_session(struct mei_cl_device *cldev,
+ struct mei_hdcp_data *data)
+{
+ struct wired_cmd_close_session_in session_close_in = { { 0 } };
+ struct wired_cmd_close_session_out session_close_out = { { 0 } };
+ struct device *dev;
+ ssize_t byte;
+
+ if (!data)
+ return -EINVAL;
+
+ dev = &cldev->dev;
+
+ session_close_in.header.api_version = HDCP_API_VERSION;
+ session_close_in.header.command_id = WIRED_CLOSE_SESSION;
+ session_close_in.header.status = ME_HDCP_STATUS_SUCCESS;
+ session_close_in.header.buffer_len =
+ WIRED_CMD_BUF_LEN_CLOSE_SESSION_IN;
+
+ session_close_in.port.integrated_port_type = data->port_type;
+ session_close_in.port.physical_port = data->port;
+
+ byte = mei_cldev_send(cldev, (u8 *)&session_close_in,
+ sizeof(session_close_in));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ byte = mei_cldev_recv(cldev, (u8 *)&session_close_out,
+ sizeof(session_close_out));
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ if (session_close_out.header.status != ME_HDCP_STATUS_SUCCESS) {
+ dev_dbg(dev, "Session Close Failed. status: 0x%X\n",
+ session_close_out.header.status);
+ return -EIO;
+ }
+
+ return 0;
+}
+
struct i915_hdcp_component_ops mei_hdcp_component_ops = {
.owner = THIS_MODULE,
.initiate_hdcp2_session = mei_initiate_hdcp2_session,
@@ -693,7 +747,7 @@ struct i915_hdcp_component_ops mei_hdcp_component_ops = {
.verify_mprime = mei_verify_mprime,
.enable_hdcp_authentication =
mei_enable_hdcp_authentication,
- .close_hdcp_session = NULL,
+ .close_hdcp_session = mei_close_hdcp_session,
};
static int mei_hdcp_component_bind(struct device *mei_kdev,
--
2.7.4
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Re: [Intel-gfx] [PATCH] drm/atomic-helper: Use old/new state in drm_atomic_helper_commit_planes_on_crtc()
On Tue, Jun 26, 2018 at 11:41:44PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Update drm_atomic_helper_commit_planes_on_crtc() to use explicit old/new
> states instead of relying on obj->state.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/drm_atomic_helper.c | 15 ++-
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> b/drivers/gpu/drm/drm_atomic_helper.c
> index e022cacdae34..8008a7de2e10 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -2342,11 +2342,13 @@ drm_atomic_helper_commit_planes_on_crtc(struct
> drm_crtc_state *old_crtc_state)
> const struct drm_crtc_helper_funcs *crtc_funcs;
> struct drm_crtc *crtc = old_crtc_state->crtc;
> struct drm_atomic_state *old_state = old_crtc_state->state;
> + struct drm_crtc_state *new_crtc_state =
> + drm_atomic_get_new_crtc_state(old_state, crtc);
> struct drm_plane *plane;
> unsigned plane_mask;
>
> plane_mask = old_crtc_state->plane_mask;
> - plane_mask |= crtc->state->plane_mask;
> + plane_mask |= new_crtc_state->plane_mask;
>
> crtc_funcs = crtc->helper_private;
> if (crtc_funcs && crtc_funcs->atomic_begin)
> @@ -2355,6 +2357,8 @@ drm_atomic_helper_commit_planes_on_crtc(struct
> drm_crtc_state *old_crtc_state)
> drm_for_each_plane_mask(plane, crtc->dev, plane_mask) {
> struct drm_plane_state *old_plane_state =
> drm_atomic_get_old_plane_state(old_state, plane);
> + struct drm_plane_state *new_plane_state =
> + drm_atomic_get_new_plane_state(old_state, plane);
> const struct drm_plane_helper_funcs *plane_funcs;
>
> plane_funcs = plane->helper_private;
> @@ -2362,13 +2366,14 @@ drm_atomic_helper_commit_planes_on_crtc(struct
> drm_crtc_state *old_crtc_state)
> if (!old_plane_state || !plane_funcs)
> continue;
>
> - WARN_ON(plane->state->crtc && plane->state->crtc != crtc);
> + WARN_ON(new_plane_state->crtc &&
> + new_plane_state->crtc != crtc);
>
> - if (drm_atomic_plane_disabling(old_plane_state, plane->state) &&
> + if (drm_atomic_plane_disabling(old_plane_state,
> new_plane_state) &&
> plane_funcs->atomic_disable)
> plane_funcs->atomic_disable(plane, old_plane_state);
> - else if (plane->state->crtc ||
> - drm_atomic_plane_disabling(old_plane_state,
> plane->state))
> + else if (new_plane_state->crtc ||
> + drm_atomic_plane_disabling(old_plane_state,
> new_plane_state))
> plane_funcs->atomic_update(plane, old_plane_state);
> }
>
> --
> 2.16.4
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 1/8] drm/fb-helper: Eliminate the .best_encoder() usage
On Tue, Jun 26, 2018 at 08:47:07PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Instead of using the .best_encoder() hook to figure out whether a given
> connector+crtc combo will work, let's instead do what userspace does and
> just iterate over all the encoders for the connector, and then check
> each crtc against each encoder's possible_crtcs bitmask.
>
> Cc: Dhinakaran Pandiyan
> Cc: Harry Wentland
> Cc: Daniel Vetter
> Acked-by: Daniel Vetter
> Suggested-by: Daniel Vetter
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_fb_helper.c | 36 +++-
> 1 file changed, 19 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
> index cab14f253384..61c39cd75a27 100644
> --- a/drivers/gpu/drm/drm_fb_helper.c
> +++ b/drivers/gpu/drm/drm_fb_helper.c
> @@ -2323,6 +2323,23 @@ static bool drm_target_preferred(struct drm_fb_helper
> *fb_helper,
> return true;
> }
>
> +static bool connector_crtc_ok(struct drm_connector *connector,
> + struct drm_crtc *crtc)
> +{
> + int i;
> +
> + for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
> + struct drm_encoder *encoder =
> + drm_encoder_find(connector->dev, NULL,
> + connector->encoder_ids[i]);
> +
Shouldn't we also check for encoder != NULL here? Just for the case where
a connector does not work on the given crtc, where we do expect to
actually run off the end of the valid entries in the array.
With that fixed:
Reviewed-by: Daniel Vetter
> + if (encoder->possible_crtcs & drm_crtc_mask(crtc))
> + return true;
> + }
> +
> + return false;
> +}
> +
> static int drm_pick_crtcs(struct drm_fb_helper *fb_helper,
> struct drm_fb_helper_crtc **best_crtcs,
> struct drm_display_mode **modes,
> @@ -2331,7 +2348,6 @@ static int drm_pick_crtcs(struct drm_fb_helper
> *fb_helper,
> int c, o;
> struct drm_connector *connector;
> const struct drm_connector_helper_funcs *connector_funcs;
> - struct drm_encoder *encoder;
> int my_score, best_score, score;
> struct drm_fb_helper_crtc **crtcs, *crtc;
> struct drm_fb_helper_connector *fb_helper_conn;
> @@ -2362,20 +2378,6 @@ static int drm_pick_crtcs(struct drm_fb_helper
> *fb_helper,
>
> connector_funcs = connector->helper_private;
>
> - /*
> - * If the DRM device implements atomic hooks and ->best_encoder() is
> - * NULL we fallback to the default drm_atomic_helper_best_encoder()
> - * helper.
> - */
> - if (drm_drv_uses_atomic_modeset(fb_helper->dev) &&
> - !connector_funcs->best_encoder)
> - encoder = drm_atomic_helper_best_encoder(connector);
> - else
> - encoder = connector_funcs->best_encoder(connector);
> -
> - if (!encoder)
> - goto out;
> -
> /*
>* select a crtc for this connector and then attempt to configure
>* remaining connectors
> @@ -2383,7 +2385,7 @@ static int drm_pick_crtcs(struct drm_fb_helper
> *fb_helper,
> for (c = 0; c < fb_helper->crtc_count; c++) {
> crtc = &fb_helper->crtc_info[c];
>
> - if ((encoder->possible_crtcs & (1 << c)) == 0)
> + if (!connector_crtc_ok(connector, crtc->mode_set.crtc))
> continue;
>
> for (o = 0; o < n; o++)
> @@ -2410,7 +2412,7 @@ static int drm_pick_crtcs(struct drm_fb_helper
> *fb_helper,
> sizeof(struct drm_fb_helper_crtc *));
> }
> }
> -out:
> +
> kfree(crtcs);
> return best_score;
> }
> --
> 2.16.4
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 2/8] drm/i915: Nuke intel_mst_best_encoder()
On Tue, Jun 26, 2018 at 08:47:08PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> With the fb-helper no longer relying on the non-atomic .best_encoder()
> we can eliminate the hook from the MST encoder.
>
> Cc: Dhinakaran Pandiyan
> Signed-off-by: Ville Syrjälä
Yay!
Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/intel_dp_mst.c | 10 --
> 1 file changed, 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 5890500a3a8b..0f012fbe34eb 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -403,20 +403,10 @@ static struct drm_encoder
> *intel_mst_atomic_best_encoder(struct drm_connector *c
> return &intel_dp->mst_encoders[crtc->pipe]->base.base;
> }
>
> -static struct drm_encoder *intel_mst_best_encoder(struct drm_connector
> *connector)
> -{
> - struct intel_connector *intel_connector = to_intel_connector(connector);
> - struct intel_dp *intel_dp = intel_connector->mst_port;
> - if (!intel_dp)
> - return NULL;
> - return &intel_dp->mst_encoders[0]->base.base;
> -}
> -
> static const struct drm_connector_helper_funcs
> intel_dp_mst_connector_helper_funcs = {
> .get_modes = intel_dp_mst_get_modes,
> .mode_valid = intel_dp_mst_mode_valid,
> .atomic_best_encoder = intel_mst_atomic_best_encoder,
> - .best_encoder = intel_mst_best_encoder,
> .atomic_check = intel_dp_mst_atomic_check,
> };
>
> --
> 2.16.4
>
> ___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for mm, oom: distinguish blockable mode for mmu notifiers (rev5)
== Series Details == Series: mm, oom: distinguish blockable mode for mmu notifiers (rev5) URL : https://patchwork.freedesktop.org/series/45263/ State : failure == Summary == Applying: mm, oom: distinguish blockable mode for mmu notifiers Using index info to reconstruct a base tree... M arch/x86/kvm/x86.c M drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c M mm/oom_kill.c M virt/kvm/kvm_main.c Falling back to patching base and 3-way merge... Auto-merging virt/kvm/kvm_main.c Auto-merging mm/oom_kill.c Auto-merging drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c CONFLICT (content): Merge conflict in drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c Auto-merging arch/x86/kvm/x86.c error: Failed to merge in the changes. Patch failed at 0001 mm, oom: distinguish blockable mode for mmu notifiers Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for ALSA: hda - Handle pm failure during hotplug
== Series Details == Series: ALSA: hda - Handle pm failure during hotplug URL : https://patchwork.freedesktop.org/series/45463/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4383 -> Patchwork_9435 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/45463/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_9435 that come from known issues: === IGT changes === Issues hit igt@drv_module_reload@basic-no-display: fi-cnl-psr: NOTRUN -> DMESG-WARN (fdo#105395) +2 fdo#105395 https://bugs.freedesktop.org/show_bug.cgi?id=105395 == Participating hosts (44 -> 40) == Additional (1): fi-cnl-psr Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4383 -> Patchwork_9435 CI_DRM_4383: bdbdbb788dc43f68c57cd3b793f123901358c331 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9435: c8ac3d11b0583503f74781fcede9f58fc3bafc51 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c8ac3d11b058 ALSA: hda - Handle pm failure during hotplug == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9435/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/8] drm: Add drm_for_each_connector_encoder_ids()
On Tue, Jun 26, 2018 at 08:47:09PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Add a convenience macro for iterating connector->encoder_ids[].
> Isolates the users from the implementation details.
>
> Also use ARRAY_SIZE() when populating the array to avoid spreading
> knowledge about the array size all over.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_connector.c| 22 ++
> drivers/gpu/drm/drm_fb_helper.c| 6 +++---
> drivers/gpu/drm/drm_probe_helper.c | 9 +
> include/drm/drm_connector.h| 11 +++
> 4 files changed, 29 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index 2f9ebddd178e..c43646cb8145 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -321,7 +321,7 @@ int drm_mode_connector_attach_encoder(struct
> drm_connector *connector,
> if (WARN_ON(connector->encoder))
> return -EINVAL;
>
> - for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
> + for (i = 0; i < ARRAY_SIZE(connector->encoder_ids); i++) {
> if (connector->encoder_ids[i] == 0) {
> connector->encoder_ids[i] = encoder->base.id;
> return 0;
> @@ -1693,6 +1693,7 @@ int drm_mode_getconnector(struct drm_device *dev, void
> *data,
> int encoders_count = 0;
> int ret = 0;
> int copied = 0;
> + u32 encoder_id;
> int i;
> struct drm_mode_modeinfo u_mode;
> struct drm_mode_modeinfo __user *mode_ptr;
> @@ -1708,22 +1709,19 @@ int drm_mode_getconnector(struct drm_device *dev,
> void *data,
> if (!connector)
> return -ENOENT;
>
> - for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++)
> - if (connector->encoder_ids[i] != 0)
> - encoders_count++;
> + drm_for_each_connector_encoder_ids(connector, encoder_id, i)
> + encoders_count++;
>
> if ((out_resp->count_encoders >= encoders_count) && encoders_count) {
> copied = 0;
> encoder_ptr = (uint32_t __user *)(unsigned
> long)(out_resp->encoders_ptr);
> - for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
> - if (connector->encoder_ids[i] != 0) {
> - if (put_user(connector->encoder_ids[i],
> - encoder_ptr + copied)) {
> - ret = -EFAULT;
> - goto out;
> - }
> - copied++;
> +
> + drm_for_each_connector_encoder_ids(connector, encoder_id, i) {
> + if (put_user(encoder_id, encoder_ptr + copied)) {
> + ret = -EFAULT;
> + goto out;
> }
> + copied++;
> }
> }
> out_resp->count_encoders = encoders_count;
> diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
> index 61c39cd75a27..e086b08748f4 100644
> --- a/drivers/gpu/drm/drm_fb_helper.c
> +++ b/drivers/gpu/drm/drm_fb_helper.c
> @@ -2326,12 +2326,12 @@ static bool drm_target_preferred(struct drm_fb_helper
> *fb_helper,
> static bool connector_crtc_ok(struct drm_connector *connector,
> struct drm_crtc *crtc)
> {
> + u32 encoder_id;
> int i;
>
> - for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
> + drm_for_each_connector_encoder_ids(connector, encoder_id, i) {
> struct drm_encoder *encoder =
> - drm_encoder_find(connector->dev, NULL,
> - connector->encoder_ids[i]);
> + drm_encoder_find(connector->dev, NULL, encoder_id);
>
> if (encoder->possible_crtcs & drm_crtc_mask(crtc))
> return true;
> diff --git a/drivers/gpu/drm/drm_probe_helper.c
> b/drivers/gpu/drm/drm_probe_helper.c
> index 527743394150..0239f76c52fb 100644
> --- a/drivers/gpu/drm/drm_probe_helper.c
> +++ b/drivers/gpu/drm/drm_probe_helper.c
> @@ -88,9 +88,9 @@ drm_mode_validate_pipeline(struct drm_display_mode *mode,
> struct drm_connector *connector)
> {
> struct drm_device *dev = connector->dev;
> - uint32_t *ids = connector->encoder_ids;
> enum drm_mode_status ret = MODE_OK;
> - unsigned int i;
> + u32 encoder_id;
> + int i;
>
> /* Step 1: Validate against connector */
> ret = drm_connector_mode_valid(connector, mode);
> @@ -98,8 +98,9 @@ drm_mode_validate_pipeline(struct drm_display_mode *mode,
> return ret;
>
> /* Step 2: Validate against encoders and crtcs */
> - for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
> - struct drm_encoder *encoder = drm_encoder_find(dev, NULL,
> ids[i]);
> + dr
Re: [Intel-gfx] [PATCH 3/8] drm: Add drm_for_each_connector_encoder_ids()
On Wed, Jun 27, 2018 at 11:08:48AM +0200, Daniel Vetter wrote:
> On Tue, Jun 26, 2018 at 08:47:09PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Add a convenience macro for iterating connector->encoder_ids[].
> > Isolates the users from the implementation details.
> >
> > Also use ARRAY_SIZE() when populating the array to avoid spreading
> > knowledge about the array size all over.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/drm_connector.c| 22 ++
> > drivers/gpu/drm/drm_fb_helper.c| 6 +++---
> > drivers/gpu/drm/drm_probe_helper.c | 9 +
> > include/drm/drm_connector.h| 11 +++
> > 4 files changed, 29 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_connector.c
> > b/drivers/gpu/drm/drm_connector.c
> > index 2f9ebddd178e..c43646cb8145 100644
> > --- a/drivers/gpu/drm/drm_connector.c
> > +++ b/drivers/gpu/drm/drm_connector.c
> > @@ -321,7 +321,7 @@ int drm_mode_connector_attach_encoder(struct
> > drm_connector *connector,
> > if (WARN_ON(connector->encoder))
> > return -EINVAL;
> >
> > - for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
> > + for (i = 0; i < ARRAY_SIZE(connector->encoder_ids); i++) {
> > if (connector->encoder_ids[i] == 0) {
> > connector->encoder_ids[i] = encoder->base.id;
> > return 0;
> > @@ -1693,6 +1693,7 @@ int drm_mode_getconnector(struct drm_device *dev,
> > void *data,
> > int encoders_count = 0;
> > int ret = 0;
> > int copied = 0;
> > + u32 encoder_id;
> > int i;
> > struct drm_mode_modeinfo u_mode;
> > struct drm_mode_modeinfo __user *mode_ptr;
> > @@ -1708,22 +1709,19 @@ int drm_mode_getconnector(struct drm_device *dev,
> > void *data,
> > if (!connector)
> > return -ENOENT;
> >
> > - for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++)
> > - if (connector->encoder_ids[i] != 0)
> > - encoders_count++;
> > + drm_for_each_connector_encoder_ids(connector, encoder_id, i)
> > + encoders_count++;
> >
> > if ((out_resp->count_encoders >= encoders_count) && encoders_count) {
> > copied = 0;
> > encoder_ptr = (uint32_t __user *)(unsigned
> > long)(out_resp->encoders_ptr);
> > - for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
> > - if (connector->encoder_ids[i] != 0) {
> > - if (put_user(connector->encoder_ids[i],
> > -encoder_ptr + copied)) {
> > - ret = -EFAULT;
> > - goto out;
> > - }
> > - copied++;
> > +
> > + drm_for_each_connector_encoder_ids(connector, encoder_id, i) {
> > + if (put_user(encoder_id, encoder_ptr + copied)) {
> > + ret = -EFAULT;
> > + goto out;
> > }
> > + copied++;
> > }
> > }
> > out_resp->count_encoders = encoders_count;
> > diff --git a/drivers/gpu/drm/drm_fb_helper.c
> > b/drivers/gpu/drm/drm_fb_helper.c
> > index 61c39cd75a27..e086b08748f4 100644
> > --- a/drivers/gpu/drm/drm_fb_helper.c
> > +++ b/drivers/gpu/drm/drm_fb_helper.c
> > @@ -2326,12 +2326,12 @@ static bool drm_target_preferred(struct
> > drm_fb_helper *fb_helper,
> > static bool connector_crtc_ok(struct drm_connector *connector,
> > struct drm_crtc *crtc)
> > {
> > + u32 encoder_id;
> > int i;
> >
> > - for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
> > + drm_for_each_connector_encoder_ids(connector, encoder_id, i) {
> > struct drm_encoder *encoder =
> > - drm_encoder_find(connector->dev, NULL,
> > -connector->encoder_ids[i]);
> > + drm_encoder_find(connector->dev, NULL, encoder_id);
> >
> > if (encoder->possible_crtcs & drm_crtc_mask(crtc))
> > return true;
> > diff --git a/drivers/gpu/drm/drm_probe_helper.c
> > b/drivers/gpu/drm/drm_probe_helper.c
> > index 527743394150..0239f76c52fb 100644
> > --- a/drivers/gpu/drm/drm_probe_helper.c
> > +++ b/drivers/gpu/drm/drm_probe_helper.c
> > @@ -88,9 +88,9 @@ drm_mode_validate_pipeline(struct drm_display_mode *mode,
> > struct drm_connector *connector)
> > {
> > struct drm_device *dev = connector->dev;
> > - uint32_t *ids = connector->encoder_ids;
> > enum drm_mode_status ret = MODE_OK;
> > - unsigned int i;
> > + u32 encoder_id;
> > + int i;
> >
> > /* Step 1: Validate against connector */
> > ret = drm_connector_mode_valid(connector, mode);
> > @@ -98,8 +98,9 @@ drm_mode_validate_pipeline(struct drm_display_mode *mode,
> > return ret;
> >
> > /* Step 2: Validate against
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Add psr1 live status (rev3)
== Series Details == Series: drm/i915/psr: Add psr1 live status (rev3) URL : https://patchwork.freedesktop.org/series/45143/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4383 -> Patchwork_9437 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/45143/revisions/3/mbox/ == Known issues == Here are the changes found in Patchwork_9437 that come from known issues: === IGT changes === Issues hit igt@drv_module_reload@basic-no-display: fi-cnl-psr: NOTRUN -> DMESG-WARN (fdo#105395) +2 igt@prime_vgem@basic-fence-flip: fi-ilk-650: PASS -> FAIL (fdo#104008) fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#105395 https://bugs.freedesktop.org/show_bug.cgi?id=105395 == Participating hosts (44 -> 40) == Additional (1): fi-cnl-psr Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4383 -> Patchwork_9437 CI_DRM_4383: bdbdbb788dc43f68c57cd3b793f123901358c331 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9437: 149469ec93e01783a7eba674442b545ffd1197f8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 149469ec93e0 drm/i915/psr: Add psr1 live status == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9437/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: mark expected switch fall-through
On Tue, 26 Jun 2018, "Gustavo A. R. Silva" wrote:
> Hi Jani,
>
> On 06/21/2018 03:03 AM, Jani Nikula wrote:
>> On Wed, 20 Jun 2018, "Gustavo A. R. Silva" wrote:
>>> On 06/20/2018 02:06 PM, Rodrigo Vivi wrote:
On Wed, Jun 20, 2018 at 08:31:00AM -0500, Gustavo A. R. Silva wrote:
> In preparation to enabling -Wimplicit-fallthrough, mark switch cases
> where we are expecting to fall through.
>
> Addresses-Coverity-ID: 1470102 ("Missing break in switch")
Any other advantage besides coverity?
Can't we address it by marking as "Intentional" on the tool?
>>>
>>> Yes. The advantage of this is that it will eventually allows to enable
>>> -Wimplicit-fallthrough, hence, enabling the compiler to trigger a
>>> warning, which will force us to double check if we are actually missing
>>> a break before committing the code.
>>
>> I applaud the efforts. Since you're doing the comment changes, do you
>> have an idea what -Wimplicit-fallthrough=N level is being considered for
>> kernel?
>>
>
> Currently, we are trying level 2.
>
I'm afraid there will be so many more places to add fallthrough
marks
>>>
>>> Oh yeah, there are around 1000 similar places in the whole codebase.
>>> There is an ongoing effort to review each case. Months ago, it used to
>>> be around 1500 of these cases.
>>
>> We use our own MISSING_CASE() to indicate stuff that's not supposed to
>> happen, or to be implemented, etc. and in many cases the fallthrough is
>> normal. I wonder if we could embed __attribute__ ((fallthrough)) in
>> there to tackle all of these without a comment.
>>
>
> I've tried this:
>
> diff --git a/drivers/gpu/drm/i915/i915_utils.h
> b/drivers/gpu/drm/i915/i915_utils.h
> index 00165ad..829572c 100644
> --- a/drivers/gpu/drm/i915/i915_utils.h
> +++ b/drivers/gpu/drm/i915/i915_utils.h
> @@ -40,8 +40,10 @@
> #undef WARN_ON_ONCE
> #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x)
> ")")
>
> -#define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
> -__stringify(x), (long)(x))
> +#define MISSING_CASE(x) ({ \
> + WARN(1, "Missing case (%s == %ld)\n", __stringify(x), (long)(x)); \
> + __attribute__ ((fallthrough)); \
> +})
>
> #if GCC_VERSION >= 7
> #define add_overflows(A, B) \
>
> and I get the following warnings as a consequence:
Right. That's because we've used MISSING_CASE() also in if-ladders in
addition to the switch default case. From our POV the usage is similar.
*shrug*
I guess I like /* fall through */ annotations next to MISSING_CASE()
better than having two different macros depending on where they're being
used.
Thanks for trying it out anyway.
BR,
Jani.
>
> drivers/gpu/drm/i915/intel_pm.c: In function ‘intel_init_clock_gating_hooks’:
> drivers/gpu/drm/i915/i915_utils.h:48:2: error: invalid use of attribute
> ‘fallthrough’
> __attribute__ ((fallthrough)); \
> ^
> drivers/gpu/drm/i915/intel_pm.c:9240:3: note: in expansion of macro
> ‘MISSING_CASE’
>MISSING_CASE(INTEL_DEVID(dev_priv));
>^~~~
> drivers/gpu/drm/i915/intel_pm.c: In function ‘intel_read_wm_latency’:
> drivers/gpu/drm/i915/i915_utils.h:48:2: error: invalid use of attribute
> ‘fallthrough’
> __attribute__ ((fallthrough)); \
> ^
> drivers/gpu/drm/i915/intel_pm.c:2902:3: note: in expansion of macro
> ‘MISSING_CASE’
>MISSING_CASE(INTEL_DEVID(dev_priv));
>^~~~
>
> Thanks
> --
> Gustavo
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH v4] drm/i915/execlists: Pull CSB reset under the timeline.lock
On 26/06/2018 12:50, Chris Wilson wrote:
In the following patch, we will process the CSB events under the
timeline.lock and not serialised by the tasklet. This also means that we
will need to protect access to common variables such as
execlists->csb_head with the timeline.lock during reset.
v2: Move sync_irq to avoid deadlocks between taking timeline.lock from
our interrupt handler.
v3: Kill off the synchronize_hardirq as it raises more questions than
answered; now we use the timeline.lock entirely for CSB serialisation
between the irq and elsewhere, we don't need to be so heavy handed with
flushing
v4: Treat request cancellation (wedging after failed reset) similarly
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 009db92b67d7..4b31e8f42aeb 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -871,7 +871,6 @@ static void reset_irq(struct intel_engine_cs *engine)
{
/* Mark all CS interrupts as complete */
smp_store_mb(engine->execlists.active, 0);
- synchronize_hardirq(engine->i915->drm.irq);
clear_gtiir(engine);
@@ -908,14 +907,12 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine)
* submission's irq state, we also wish to remind ourselves that
* it is irq state.)
*/
- local_irq_save(flags);
+ spin_lock_irqsave(&engine->timeline.lock, flags);
/* Cancel the requests on the HW and clear the ELSP tracker. */
execlists_cancel_port_requests(execlists);
reset_irq(engine);
- spin_lock(&engine->timeline.lock);
-
/* Mark all executing requests as skipped. */
list_for_each_entry(rq, &engine->timeline.requests, link) {
GEM_BUG_ON(!rq->global_seqno);
@@ -949,9 +946,7 @@ static void execlists_cancel_requests(struct
intel_engine_cs *engine)
execlists->first = NULL;
GEM_BUG_ON(port_isset(execlists->port));
- spin_unlock(&engine->timeline.lock);
-
- local_irq_restore(flags);
+ spin_unlock_irqrestore(&engine->timeline.lock, flags);
}
static void process_csb(struct intel_engine_cs *engine)
@@ -1969,8 +1964,7 @@ static void execlists_reset(struct intel_engine_cs
*engine,
engine->name, request ? request->global_seqno : 0,
intel_engine_get_seqno(engine));
- /* See execlists_cancel_requests() for the irq/spinlock split. */
- local_irq_save(flags);
+ spin_lock_irqsave(&engine->timeline.lock, flags);
/*
* Catch up with any missed context-switch interrupts.
@@ -1985,14 +1979,12 @@ static void execlists_reset(struct intel_engine_cs
*engine,
reset_irq(engine);
/* Push back any incomplete requests for replay after the reset. */
- spin_lock(&engine->timeline.lock);
__unwind_incomplete_requests(engine);
- spin_unlock(&engine->timeline.lock);
/* Following the reset, we need to reload the CSB read/write pointers */
engine->execlists.csb_head = GEN8_CSB_ENTRIES - 1;
- local_irq_restore(flags);
+ spin_unlock_irqrestore(&engine->timeline.lock, flags);
/*
* If the request was innocent, we leave the request in the ELSP
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
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Re: [Intel-gfx] [PATCH 05/31] drm/i915/execlists: Process one CSB update at a time
On 25/06/2018 10:48, Chris Wilson wrote:
In the next patch, we will process the CSB events directly from the
submission path, rather than only after a CS interrupt. Hence, we will
no longer have the need for a loop until the has-interrupt bit is clear,
and in the meantime can remove that small optimisation.
So strictly speaking this patch would need to go after the one which
removes the need to loop.
Unfortunately there is "Unify CSB access pointers" in between which
touches the same code heavily so I think that would really ruin your day.
So lets turn a blind eye.. just remember not to merge this series
half-way through.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 278 +++
1 file changed, 137 insertions(+), 141 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 2cbb293fb409..8911c4ccbdad 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -960,166 +960,162 @@ static void process_csb(struct intel_engine_cs *engine)
struct intel_engine_execlists * const execlists = &engine->execlists;
struct execlist_port *port = execlists->port;
struct drm_i915_private *i915 = engine->i915;
+
+ /* The HWSP contains a (cacheable) mirror of the CSB */
+ const u32 *buf =
+ &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
+ unsigned int head, tail;
bool fw = false;
- do {
- /* The HWSP contains a (cacheable) mirror of the CSB */
- const u32 *buf =
- &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
- unsigned int head, tail;
-
- /* Clear before reading to catch new interrupts */
- clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
- smp_mb__after_atomic();
-
- if (unlikely(execlists->csb_use_mmio)) {
- if (!fw) {
- intel_uncore_forcewake_get(i915,
execlists->fw_domains);
- fw = true;
- }
+ /* Clear before reading to catch new interrupts */
+ clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
+ smp_mb__after_atomic();
- buf = (u32 * __force)
- (i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
+ if (unlikely(execlists->csb_use_mmio)) {
+ intel_uncore_forcewake_get(i915, execlists->fw_domains);
+ fw = true;
- head = readl(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
- tail = GEN8_CSB_WRITE_PTR(head);
- head = GEN8_CSB_READ_PTR(head);
- execlists->csb_head = head;
- } else {
- const int write_idx =
- intel_hws_csb_write_index(i915) -
- I915_HWS_CSB_BUF0_INDEX;
+ buf = (u32 * __force)
+ (i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
- head = execlists->csb_head;
- tail = READ_ONCE(buf[write_idx]);
- rmb(); /* Hopefully paired with a wmb() in HW */
- }
- GEM_TRACE("%s cs-irq head=%d [%d%s], tail=%d [%d%s]\n",
- engine->name,
- head, GEN8_CSB_READ_PTR(readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?",
- tail, GEN8_CSB_WRITE_PTR(readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?");
+ head = readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
+ tail = GEN8_CSB_WRITE_PTR(head);
+ head = GEN8_CSB_READ_PTR(head);
+ execlists->csb_head = head;
+ } else {
+ const int write_idx =
+ intel_hws_csb_write_index(i915) -
+ I915_HWS_CSB_BUF0_INDEX;
- while (head != tail) {
- struct i915_request *rq;
- unsigned int status;
- unsigned int count;
+ head = execlists->csb_head;
+ tail = READ_ONCE(buf[write_idx]);
+ rmb(); /* Hopefully paired with a wmb() in HW */
+ }
+ GEM_TRACE("%s cs-irq head=%d [%d%s], tail=%d [%d%s]\n",
+ engine->name,
+ head, GEN8_CSB_READ_PTR(readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?",
+ tail, GEN8_CSB_WRITE_PTR(readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?");
- if (++head == GEN8_CSB_ENTRIES)
- head = 0;
+ while (head != tail) {
+
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Implement HDCP2.2 (rev6)
== Series Details ==
Series: drm/i915: Implement HDCP2.2 (rev6)
URL : https://patchwork.freedesktop.org/series/38254/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5492406c5fd4 drm: hdcp2.2 authentication msg definitions
141f5ef87658 drm: HDMI and DP specific HDCP2.2 defines
c2631180e88c mei: bus: whitelist hdcp client
3076f17d9d6f linux/mei: Header for mei_hdcp driver interface
-:21: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#21:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 100 lines checked
b0085b67f0d4 drm/i915: wrapping all hdcp var into intel_hdcp
-:35: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#35: FILE: drivers/gpu/drm/i915/intel_display.c:15886:
+ cancel_delayed_work_sync(
total: 0 errors, 0 warnings, 1 checks, 266 lines checked
cdd72314a661 drm/i915: Define HDCP2.2 related variables
b5070b3df185 drm/i915: Define Intel HDCP2.2 registers
d9cad9943e32 drm/i915: Initialize HDCP2.2 and its MEI interface
-:91: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible
side-effects?
#91: FILE: drivers/gpu/drm/i915/intel_hdcp.c:20:
+#define GET_MEI_DDI_INDEX(port)(((port) == PORT_A) ? DDI_A : \
+(enum hdcp_physical_port)(port))
total: 0 errors, 0 warnings, 1 checks, 377 lines checked
0320f25fee34 drm/i915: Schedule hdcp_check_link in _intel_hdcp_enable
6f3bfe958148 drm/i915: Pullout the bksv read and validation
f8a3b01256ba drm/i915: Enable superior HDCP ver that is capable
ec29346c6922 drm/i915: Enable HDCP1.4 incase of HDCP2.2 failure
64da60e913c1 drm/i915: Implement HDCP2.2 Enable and Disable
9b54b98284ab drm/i915: Enable and Disable HDCP2.2 port encryption
e53953d473e5 drm/i915: Implement HDCP2.2 receiver authentication
b25ef7a2fffe drm/i915: Implement HDCP2.2 repeater authentication
-:31: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#31: FILE: drivers/gpu/drm/i915/intel_hdcp.c:1192:
+hdcp2_verify_rep_topology_prepare_ack(
total: 0 errors, 0 warnings, 1 checks, 215 lines checked
87738908c17a drm/i915: Implement HDCP2.2 link integrity check
c8857e092400 drm/i915: Handle HDCP2.2 downstream topology change
c51f890739b3 drm/i915: hdcp_check_link only on CP_IRQ
4af972f5695a drm/i915: Check HDCP 1.4 and 2.2 link on CP_IRQ
6bf99667b493 drm/i915/gmbus: Increase the Bytes per Rd/Wr Op
82267d3ab33e drm/i915/gmbus: Enable burst read
-:38: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible
side-effects?
#38: FILE: drivers/gpu/drm/i915/i915_drv.h:2579:
+#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
+ IS_GEMINILAKE(dev_priv) || \
+ IS_KABYLAKE(dev_priv))
-:72: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#72: FILE: drivers/gpu/drm/i915/intel_i2c.c:381:
+ if (burst_read) {
+
total: 0 errors, 0 warnings, 2 checks, 131 lines checked
c6a7aff5b081 drm/i915: Implement the HDCP2.2 support for DP
2483edd05e87 drm/i915: Implement the HDCP2.2 support for HDMI
-:126: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#126: FILE: drivers/gpu/drm/i915/intel_hdmi.c:1205:
+ ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port,
+msg_id, &msg_ready, &msg_sz),
total: 0 errors, 0 warnings, 1 checks, 205 lines checked
2c24ad5e9eac drm/i915: Add HDCP2.2 support for DP connectors
e8411d9b58c4 drm/i915: Add HDCP2.2 support for HDMI connectors
5fbf18f87d30 misc/mei/hdcp: Client driver for HDCP application
-:87: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#87:
new file mode 100644
-:104: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#104: FILE: drivers/misc/mei/hdcp/mei_hdcp.c:1:
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
total: 0 errors, 2 warnings, 0 checks, 102 lines checked
708216f2ee32 misc/mei/hdcp: Component framework for I915 Interface
ec1d8f5d766d misc/mei/hdcp: Define ME FW interface for HDCP2.2
-:24: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#24:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 408 lines checked
08702087a8da misc/mei/hdcp: Initiate Wired HDCP2.2 Tx Session
89c8dd646a8b misc/mei/hdcp: Verify Receiver Cert and prepare km
43869e147bbf misc/mei/hdcp: Verify H_prime
29dc95904d40 misc/mei/hdcp: Store the HDCP Pairing info
e98ec660d02f misc/mei/hdcp: Initiate Locality check
a5a038d5ca07 misc/mei/hdcp: Verify L_prime
f351f07d3bdf misc/mei/hdcp: Prepare Session Key
da152ecb2ae1 misc/mei/hdcp: Repeater topology verification and ack
91bf6b0aeac5 misc/mei/hdcp: Verify M_prime
e9a556103422 misc/mei/hdcp: Enabling the HDCP authentication
51addd6109ff misc/mei/hdcp: Closing wired HDCP2.2 Tx Session
___
Intel-gfx mai
Re: [Intel-gfx] [PATCH 06/31] drm/i915/execlists: Unify CSB access pointers
On 25/06/2018 10:48, Chris Wilson wrote:
Following the removal of the last workarounds, the only CSB mmio access
is for the old vGPU interface. The mmio registers presented by vGPU do
not require forcewake and can be treated as ordinary volatile memory,
i.e. they behave just like the HWSP access just at a different location.
We can reduce the CSB access to a set of read/write/buffer pointers and
treat the various paths identically and not worry about forcewake.
(Forcewake is nightmare for worstcase latency, and we want to process
this all with irqsoff -- no latency allowed!)
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_engine_cs.c | 12 ---
drivers/gpu/drm/i915/intel_lrc.c| 116 ++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 23 +++--
3 files changed, 65 insertions(+), 86 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index d3264bd6e9dc..7209c22798e6 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -25,7 +25,6 @@
#include
#include "i915_drv.h"
-#include "i915_vgpu.h"
#include "intel_ringbuffer.h"
#include "intel_lrc.h"
@@ -456,21 +455,10 @@ static void intel_engine_init_batch_pool(struct intel_engine_cs *engine)
i915_gem_batch_pool_init(&engine->batch_pool, engine);
}
-static bool csb_force_mmio(struct drm_i915_private *i915)
-{
- /* Older GVT emulation depends upon intercepting CSB mmio */
- if (intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915))
- return true;
-
- return false;
-}
-
static void intel_engine_init_execlist(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
- execlists->csb_use_mmio = csb_force_mmio(engine->i915);
-
execlists->port_mask = 1;
BUILD_BUG_ON_NOT_POWER_OF_2(execlists_num_ports(execlists));
GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 8911c4ccbdad..5a12b8fc9d8f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -137,6 +137,7 @@
#include
#include "i915_drv.h"
#include "i915_gem_render_state.h"
+#include "i915_vgpu.h"
#include "intel_lrc_reg.h"
#include "intel_mocs.h"
#include "intel_workarounds.h"
@@ -959,44 +960,23 @@ static void process_csb(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
struct execlist_port *port = execlists->port;
- struct drm_i915_private *i915 = engine->i915;
-
- /* The HWSP contains a (cacheable) mirror of the CSB */
- const u32 *buf =
- &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
- unsigned int head, tail;
- bool fw = false;
+ const u32 * const buf = execlists->csb_status;
+ u8 head, tail;
/* Clear before reading to catch new interrupts */
clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
smp_mb__after_atomic();
- if (unlikely(execlists->csb_use_mmio)) {
- intel_uncore_forcewake_get(i915, execlists->fw_domains);
- fw = true;
-
- buf = (u32 * __force)
- (i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
+ /* Note that csb_write, csb_status may be either in HWSP or mmio */
+ head = execlists->csb_head;
+ tail = READ_ONCE(*execlists->csb_write);
+ GEM_TRACE("%s cs-irq head=%d, tail=%d\n", engine->name, head, tail);
+ if (unlikely(head == tail))
+ return;
- head = readl(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
- tail = GEN8_CSB_WRITE_PTR(head);
- head = GEN8_CSB_READ_PTR(head);
- execlists->csb_head = head;
- } else {
- const int write_idx =
- intel_hws_csb_write_index(i915) -
- I915_HWS_CSB_BUF0_INDEX;
+ rmb(); /* Hopefully paired with a wmb() in HW */
- head = execlists->csb_head;
- tail = READ_ONCE(buf[write_idx]);
- rmb(); /* Hopefully paired with a wmb() in HW */
- }
- GEM_TRACE("%s cs-irq head=%d [%d%s], tail=%d [%d%s]\n",
- engine->name,
- head, GEN8_CSB_READ_PTR(readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?",
- tail, GEN8_CSB_WRITE_PTR(readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?");
-
- while (head != tail) {
+ do {
struct i915_request *rq;
unsigned int status;
unsigned int count;
@@ -1022,12 +1002,12 @@ static void process_csb(struct intel_engine_cs *engine)
* status not
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Implement HDCP2.2 (rev6)
== Series Details == Series: drm/i915: Implement HDCP2.2 (rev6) URL : https://patchwork.freedesktop.org/series/38254/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm: hdcp2.2 authentication msg definitions Okay! Commit: drm: HDMI and DP specific HDCP2.2 defines Okay! Commit: mei: bus: whitelist hdcp client Okay! Commit: linux/mei: Header for mei_hdcp driver interface Okay! Commit: drm/i915: wrapping all hdcp var into intel_hdcp Okay! Commit: drm/i915: Define HDCP2.2 related variables Okay! Commit: drm/i915: Define Intel HDCP2.2 registers Okay! Commit: drm/i915: Initialize HDCP2.2 and its MEI interface +drivers/gpu/drm/i915/intel_hdcp.c:1074:6: warning: symbol 'is_hdcp2_supported' was not declared. Should it be static? +drivers/gpu/drm/i915/intel_hdcp.c:999:39: warning: symbol 'master_ops' was not declared. Should it be static? -drivers/gpu/drm/i915/selftests/../i915_drv.h:3672:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3674:16: warning: expression using sizeof(void) +./include/linux/slab.h:631:13: error: not a function Commit: drm/i915: Schedule hdcp_check_link in _intel_hdcp_enable -drivers/gpu/drm/i915/intel_hdcp.c:1078:6: warning: symbol 'is_hdcp2_supported' was not declared. Should it be static? +drivers/gpu/drm/i915/intel_hdcp.c:1078:6: warning: symbol 'is_hdcp2_supported' was not declared. Should it be static? Commit: drm/i915: Pullout the bksv read and validation Okay! Commit: drm/i915: Enable superior HDCP ver that is capable Okay! Commit: drm/i915: Enable HDCP1.4 incase of HDCP2.2 failure Okay! Commit: drm/i915: Implement HDCP2.2 Enable and Disable Okay! Commit: drm/i915: Enable and Disable HDCP2.2 port encryption Okay! Commit: drm/i915: Implement HDCP2.2 receiver authentication Okay! Commit: drm/i915: Implement HDCP2.2 repeater authentication +drivers/gpu/drm/i915/intel_hdcp.c:1451:30:expected restricted __be16 [assigned] [usertype] k +drivers/gpu/drm/i915/intel_hdcp.c:1451:30:got int +drivers/gpu/drm/i915/intel_hdcp.c:1451:30: warning: incorrect type in assignment (different base types) Commit: drm/i915: Implement HDCP2.2 link integrity check Okay! Commit: drm/i915: Handle HDCP2.2 downstream topology change Okay! Commit: drm/i915: hdcp_check_link only on CP_IRQ Okay! Commit: drm/i915: Check HDCP 1.4 and 2.2 link on CP_IRQ Okay! Commit: drm/i915/gmbus: Increase the Bytes per Rd/Wr Op -O:drivers/gpu/drm/i915/intel_i2c.c:403:23: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_i2c.c:465:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_i2c.c:410:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_i2c.c:410:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_i2c.c:472:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_i2c.c:472:23: warning: expression using sizeof(void) Commit: drm/i915/gmbus: Enable burst read -O:drivers/gpu/drm/i915/intel_i2c.c:410:23: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_i2c.c:410:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_i2c.c:446:31: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_i2c.c:448:31: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_i2c.c:448:31: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/../i915_drv.h:3674:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3677:16: warning: expression using sizeof(void) Commit: drm/i915: Implement the HDCP2.2 support for DP Okay! Commit: drm/i915: Implement the HDCP2.2 support for HDMI Okay! Commit: drm/i915: Add HDCP2.2 support for DP connectors -drivers/gpu/drm/i915/intel_hdcp.c:1918:6: warning: symbol 'is_hdcp2_supported' was not declared. Should it be static? Commit: drm/i915: Add HDCP2.2 support for HDMI connectors Okay! Commit: misc/mei/hdcp: Client driver for HDCP application Okay! Commit: misc/mei/hdcp: Component framework for I915 Interface Okay! Commit: misc/mei/hdcp: Define ME FW interface for HDCP2.2 Okay! Commit: misc/mei/hdcp: Initiate Wired HDCP2.2 Tx Session Okay! Commit: misc/mei/hdcp: Verify Receiver Cert and prepare km Okay! Commit: misc/mei/hdcp: Verify H_prime Okay! Commit: misc/mei/hdcp: Store the HDCP Pairing info Okay! Commit: misc/mei/hdcp: Initiate Locality check Okay! Commit: misc/mei/hdcp: Verify L_prime Okay! Commit: misc/mei/hdcp: Prepare Session Key Okay! Commit: misc/mei/hdcp: Repeater topology verification and ack Okay! Commit: misc/mei/hdcp: Verify M_prime Okay! Commit: misc/mei/hdcp: Enabling the HDCP authentication Okay! Commit: misc/mei/hdcp: Closing wired HDCP2.2 Tx Session Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Implement HDCP2.2 (rev6)
== Series Details ==
Series: drm/i915: Implement HDCP2.2 (rev6)
URL : https://patchwork.freedesktop.org/series/38254/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4383 -> Patchwork_9438 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_9438 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9438, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/38254/revisions/6/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9438:
=== IGT changes ===
Possible regressions
igt@drv_module_reload@basic-no-display:
fi-glk-j4005: PASS -> DMESG-FAIL
fi-kbl-r: PASS -> DMESG-FAIL
fi-kbl-guc: PASS -> DMESG-FAIL
fi-glk-dsi: PASS -> DMESG-FAIL
{fi-kbl-x1275}: PASS -> FAIL
igt@drv_module_reload@basic-reload:
{fi-kbl-x1275}: PASS -> DMESG-FAIL
igt@drv_module_reload@basic-reload-inject:
fi-kbl-7560u: PASS -> DMESG-FAIL
fi-kbl-r: PASS -> INCOMPLETE
fi-kbl-7500u: PASS -> DMESG-FAIL
fi-cnl-psr: NOTRUN -> DMESG-FAIL
fi-glk-dsi: PASS -> INCOMPLETE
{fi-kbl-x1275}: PASS -> INCOMPLETE
igt@gem_exec_suspend@basic-s3:
fi-kbl-r: PASS -> DMESG-WARN +1
fi-glk-j4005: PASS -> DMESG-WARN
fi-glk-dsi: PASS -> DMESG-WARN
fi-kbl-7500u: PASS -> DMESG-WARN +1
fi-kbl-guc: PASS -> DMESG-WARN +1
fi-cnl-psr: NOTRUN -> DMESG-WARN
fi-kbl-7560u: PASS -> DMESG-WARN +1
== Known issues ==
Here are the changes found in Patchwork_9438 that come from known issues:
=== IGT changes ===
Issues hit
igt@drv_module_reload@basic-no-display:
fi-cnl-psr: NOTRUN -> DMESG-WARN (fdo#105395) +1
igt@drv_module_reload@basic-reload-inject:
fi-kbl-guc: PASS -> INCOMPLETE (fdo#106693)
fi-glk-j4005: PASS -> INCOMPLETE (k.org#198133, fdo#103359)
igt@gem_exec_suspend@basic-s3:
fi-kbl-7567u: PASS -> INCOMPLETE (fdo#103665)
igt@kms_chamelium@hdmi-hpd-fast:
fi-kbl-7500u: SKIP -> FAIL (fdo#102672, fdo#103841)
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-glk-j4005: PASS -> FAIL (fdo#100368)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#105395 https://bugs.freedesktop.org/show_bug.cgi?id=105395
fdo#106693 https://bugs.freedesktop.org/show_bug.cgi?id=106693
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (44 -> 39) ==
Additional (1): fi-cnl-psr
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_4383 -> Patchwork_9438
CI_DRM_4383: bdbdbb788dc43f68c57cd3b793f123901358c331 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9438: 51addd6109ffb47c4808337be8b4f45bbe82a752 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
51addd6109ff misc/mei/hdcp: Closing wired HDCP2.2 Tx Session
e9a556103422 misc/mei/hdcp: Enabling the HDCP authentication
91bf6b0aeac5 misc/mei/hdcp: Verify M_prime
da152ecb2ae1 misc/mei/hdcp: Repeater topology verification and ack
f351f07d3bdf misc/mei/hdcp: Prepare Session Key
a5a038d5ca07 misc/mei/hdcp: Verify L_prime
e98ec660d02f misc/mei/hdcp: Initiate Locality check
29dc95904d40 misc/mei/hdcp: Store the HDCP Pairing info
43869e147bbf misc/mei/hdcp: Verify H_prime
89c8dd646a8b misc/mei/hdcp: Verify Receiver Cert and prepare km
08702087a8da misc/mei/hdcp: Initiate Wired HDCP2.2 Tx Session
ec1d8f5d766d misc/mei/hdcp: Define ME FW interface for HDCP2.2
708216f2ee32 misc/mei/hdcp: Component framework for I915 Interface
5fbf18f87d30 misc/mei/hdcp: Client driver for HDCP application
e8411d9b58c4 drm/i915: Add HDCP2.2 support for HDMI connectors
2c24ad5e9eac drm/i915: Add HDCP2.2 support for DP connectors
2483edd05e87 drm/i915: Implement the HDCP2.2 support for HDMI
c6a7aff5
[Intel-gfx] ✓ Fi.CI.IGT: success for ALSA: hda - Handle pm failure during hotplug
== Series Details == Series: ALSA: hda - Handle pm failure during hotplug URL : https://patchwork.freedesktop.org/series/45463/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4383_full -> Patchwork_9435_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9435_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9435_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9435_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-bsd2: shard-kbl: PASS -> SKIP +2 igt@gem_mocs_settings@mocs-rc6-blt: shard-kbl: SKIP -> PASS +1 == Known issues == Here are the changes found in Patchwork_9435_full that come from known issues: === IGT changes === Issues hit igt@kms_available_modes_crc@available_mode_test_crc: shard-kbl: NOTRUN -> FAIL (fdo#106641) igt@kms_flip_tiling@flip-to-y-tiled: shard-glk: PASS -> FAIL (fdo#104724, fdo#103822) +2 Possible fixes igt@gem_exec_big: shard-hsw: INCOMPLETE (fdo#103540) -> PASS igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: FAIL (fdo#105703) -> PASS igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic: shard-glk: FAIL (fdo#105454, fdo#106509) -> PASS igt@kms_flip@flip-vs-expired-vblank: shard-glk: FAIL (fdo#105363) -> PASS igt@kms_flip_tiling@flip-x-tiled: shard-glk: FAIL (fdo#104724) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt: shard-glk: FAIL (fdo#104724, fdo#103167) -> PASS igt@kms_rotation_crc@sprite-rotation-180: shard-hsw: FAIL (fdo#104724, fdo#103925) -> PASS fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641 == Participating hosts (6 -> 5) == Missing(1): pig-skl-6260u == Build changes == * Linux: CI_DRM_4383 -> Patchwork_9435 CI_DRM_4383: bdbdbb788dc43f68c57cd3b793f123901358c331 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9435: c8ac3d11b0583503f74781fcede9f58fc3bafc51 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9435/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/31] drm/i915/execlists: Process one CSB update at a time
Quoting Tvrtko Ursulin (2018-06-27 10:46:37)
>
> On 25/06/2018 10:48, Chris Wilson wrote:
> > In the next patch, we will process the CSB events directly from the
> > submission path, rather than only after a CS interrupt. Hence, we will
> > no longer have the need for a loop until the has-interrupt bit is clear,
> > and in the meantime can remove that small optimisation.
>
> So strictly speaking this patch would need to go after the one which
> removes the need to loop.
Hmm. We can just remove the test_and_set_bit here so the tasklet is
unconditionally called, that should resolve the doubt.
> > + /*
> > + * We are flying near dragons again.
> > + *
> > + * We hold a reference to the request in execlist_port[]
> > + * but no more than that. We are operating in softirq
> > + * context and so cannot hold any mutex or sleep. That
> > + * prevents us stopping the requests we are processing
> > + * in port[] from being retired simultaneously (the
> > + * breadcrumb will be complete before we see the
> > + * context-switch). As we only hold the reference to the
> > + * request, any pointer chasing underneath the request
> > + * is subject to a potential use-after-free. Thus we
> > + * store all of the bookkeeping within port[] as
> > + * required, and avoid using unguarded pointers beneath
> > + * request itself. The same applies to the atomic
> > + * status notifier.
> > + */
>
> I need a reformat-comment-to-wrap plugin for my editor. Just noticing
> that some width has been freed up so number of lines could be reduced.
> But don't waste time on it.
>
> >
> > - /* We should never get a COMPLETED | IDLE_ACTIVE! */
> > - GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE);
> > + status = READ_ONCE(buf[2 * head]); /* maybe mmio! */
> > + GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x, active=0x%x\n",
> > + engine->name, head,
> > + status, buf[2*head + 1],
> > + execlists->active);
> > +
> > + if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE |
> > + GEN8_CTX_STATUS_PREEMPTED))
> > + execlists_set_active(execlists,
> > + EXECLISTS_ACTIVE_HWACK);
> > + if (status & GEN8_CTX_STATUS_ACTIVE_IDLE)
> > + execlists_clear_active(execlists,
> > +EXECLISTS_ACTIVE_HWACK);
> > +
> > + if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
> > + continue;
> >
> > - if (status & GEN8_CTX_STATUS_COMPLETE &&
> > - buf[2*head + 1] ==
> > execlists->preempt_complete_status) {
> > - GEM_TRACE("%s preempt-idle\n", engine->name);
> > - complete_preempt_context(execlists);
> > - continue;
> > - }
> > + /* We should never get a COMPLETED | IDLE_ACTIVE! */
> > + GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE);
> >
> > - if (status & GEN8_CTX_STATUS_PREEMPTED &&
> > - execlists_is_active(execlists,
> > - EXECLISTS_ACTIVE_PREEMPT))
> > - continue;
> > + if (status & GEN8_CTX_STATUS_COMPLETE &&
> > + buf[2*head + 1] == execlists->preempt_complete_status) {
> > + GEM_TRACE("%s preempt-idle\n", engine->name);
> > + complete_preempt_context(execlists);
> > + continue;
> > + }
> >
> > - GEM_BUG_ON(!execlists_is_active(execlists,
> > -
> > EXECLISTS_ACTIVE_USER));
> > + if (status & GEN8_CTX_STATUS_PREEMPTED &&
> > + execlists_is_active(execlists,
> > + EXECLISTS_ACTIVE_PREEMPT))
>
> But reformatting actual code would have probably been a good idea. Don't
> do it now, or I'll have to re-read it all!
! I was trying to be good and just have the re-indent as separate patch
:)
> Nothing seems lost or added, so:
>
> Reviewed-by: Tvrtko Ursulin
>
Imagine with the i915_irq.c change?
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 06/31] drm/i915/execlists: Unify CSB access pointers
Quoting Tvrtko Ursulin (2018-06-27 10:52:45)
>
> On 25/06/2018 10:48, Chris Wilson wrote:
> > @@ -1109,16 +1089,11 @@ static void process_csb(struct intel_engine_cs
> > *engine)
> > } else {
> > port_set(port, port_pack(rq, count));
> > }
> > - }
> > + } while (head != tail);
> >
> > - if (head != execlists->csb_head) {
> > - execlists->csb_head = head;
> > - writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8),
> > -i915->regs +
> > i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
> > - }
> > -
> > - if (unlikely(fw))
> > - intel_uncore_forcewake_put(i915, execlists->fw_domains);
> > + writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8),
> > +execlists->csb_read);
>
> Continuing from the last round - so what to do with this one? It does
> need forcewake. So I think it needs to go if we are claiming there is no
> mmio any longer.
From last round, we decided it didn't, or at least concluded the
(from the lack of) evidence that it does not, because we are not using
forcewake right now...
-Chris
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 07/31] drm/i915/execlists: Direct submission of new requests (avoid tasklet/ksoftirqd)
On 25/06/2018 10:48, Chris Wilson wrote:
Back in commit 27af5eea54d1 ("drm/i915: Move execlists irq handler to a
bottom half"), we came to the conclusion that running our CSB processing
and ELSP submission from inside the irq handler was a bad idea. A really
bad idea as we could impose nearly 1s latency on other users of the
system, on average! Deferring our work to a tasklet allowed us to do the
processing with irqs enabled, reducing the impact to an average of about
50us.
We have since eradicated the use of forcewaked mmio from inside the CSB
processing and ELSP submission, bringing the impact down to around 5us
(on Kabylake); an order of magnitude better than our measurements 2
years ago on Broadwell and only about 2x worse on average than the
gem_syslatency on an unladen system.
In this iteration of the tasklet-vs-direct submission debate, we seek a
compromise where by we submit new requests immediately to the HW but
defer processing the CS interrupt onto a tasklet. We gain the advantage
of low-latency and ksoftirqd avoidance when waking up the HW, while
avoiding the system-wide starvation of our CS irq-storms.
Comparing the impact on the maximum latency observed (that is the time
stolen from an RT process) over a 120s interval, repeated several times
(using gem_syslatency, similar to RT's cyclictest) while the system is
fully laden with i915 nops, we see that direct submission an actually
improve the worse case.
Maximum latency in microseconds of a third party RT thread
(gem_syslatency -t 120 -f 2)
x Always using tasklets (a couple of >1000us outliers removed)
+ Only using tasklets from CS irq, direct submission of requests
++
| + |
| + |
| + |
| + + |
| + + + |
| + + + + x x x |
| +++ + + + x x x x x x |
| +++ + ++ + + *x x x x x x |
| +++ + ++ + * *x x * x x x |
|+ +++ + ++ * * +*xxx * x x xx |
|* +++ + * *x+**xx+ * x x x |
| **x*++**+*x*xx+ * +x xx x x|
|x* **+***++*+***xx* xx*x xxx +x+|
| |__MA___| |
| |__M__A| |
++
N Min MaxMedian AvgStddev
x 11891 186 124 125.28814 16.279137
+ 12092 187 109 112.00833 13.458617
Difference at 95.0% confidence
-13.2798 +/- 3.79219
-10.5994% +/- 3.02677%
(Student's t, pooled s = 14.9237)
However the mean latency is adversely affected:
Mean latency in microseconds of a third party RT thread
(gem_syslatency -t 120 -f 1)
x Always using tasklets
+ Only using tasklets from CS irq, direct submission of requests
++
| xx+ ++ |
| xx+ ++ |
| xx + +++ ++ |
| xxx + ++ |
| xxx + ++ |
| xxx + +++|
| xxx + ++ |
| ++ ++ |
| ++ ++ |
| xx+++ |
| xxxx +++ |
|x x x ++ ++ +|
| |__A__| |
| |A___||
++
N Min MaxMedian AvgStddev
x 120 3.506 3.727 3.631 3.63214170.02773109
+ 120 3.834 4.149 4.039 4.0375167 0.041221676
Difference at 95.0% confidence
[Intel-gfx] [PATCH v2] drm/i915/execlists: Process one CSB update at a time
In the next patch, we will process the CSB events directly from the
submission path, rather than only after a CS interrupt. Hence, we will
no longer have the need for a loop until the has-interrupt bit is clear,
and in the meantime can remove that small optimisation.
v2: Tvrtko pointed out it was safer to unconditionally kick the tasklet
after each irq, when assuming that the tasklet is called for each irq.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin #v1
---
drivers/gpu/drm/i915/i915_irq.c | 7 +-
drivers/gpu/drm/i915/intel_lrc.c | 278 +++
2 files changed, 141 insertions(+), 144 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 46aaef5c1851..d02f30591c0b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1473,9 +1473,10 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32
iir)
bool tasklet = false;
if (iir & GT_CONTEXT_SWITCH_INTERRUPT) {
- if (READ_ONCE(engine->execlists.active))
- tasklet = !test_and_set_bit(ENGINE_IRQ_EXECLIST,
- &engine->irq_posted);
+ if (READ_ONCE(engine->execlists.active)) {
+ set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
+ tasklet = true;
+ }
}
if (iir & GT_RENDER_USER_INTERRUPT) {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4b31e8f42aeb..91656eb2f2db 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -954,166 +954,162 @@ static void process_csb(struct intel_engine_cs *engine)
struct intel_engine_execlists * const execlists = &engine->execlists;
struct execlist_port *port = execlists->port;
struct drm_i915_private *i915 = engine->i915;
+
+ /* The HWSP contains a (cacheable) mirror of the CSB */
+ const u32 *buf =
+ &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
+ unsigned int head, tail;
bool fw = false;
- do {
- /* The HWSP contains a (cacheable) mirror of the CSB */
- const u32 *buf =
- &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
- unsigned int head, tail;
-
- /* Clear before reading to catch new interrupts */
- clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
- smp_mb__after_atomic();
-
- if (unlikely(execlists->csb_use_mmio)) {
- if (!fw) {
- intel_uncore_forcewake_get(i915,
execlists->fw_domains);
- fw = true;
- }
+ /* Clear before reading to catch new interrupts */
+ clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
+ smp_mb__after_atomic();
- buf = (u32 * __force)
- (i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
+ if (unlikely(execlists->csb_use_mmio)) {
+ intel_uncore_forcewake_get(i915, execlists->fw_domains);
+ fw = true;
- head = readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
- tail = GEN8_CSB_WRITE_PTR(head);
- head = GEN8_CSB_READ_PTR(head);
- execlists->csb_head = head;
- } else {
- const int write_idx =
- intel_hws_csb_write_index(i915) -
- I915_HWS_CSB_BUF0_INDEX;
+ buf = (u32 * __force)
+ (i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
- head = execlists->csb_head;
- tail = READ_ONCE(buf[write_idx]);
- rmb(); /* Hopefully paired with a wmb() in HW */
- }
- GEM_TRACE("%s cs-irq head=%d [%d%s], tail=%d [%d%s]\n",
- engine->name,
- head, GEN8_CSB_READ_PTR(readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?",
- tail, GEN8_CSB_WRITE_PTR(readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?");
+ head = readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
+ tail = GEN8_CSB_WRITE_PTR(head);
+ head = GEN8_CSB_READ_PTR(head);
+ execlists->csb_head = head;
+ } else {
+ const int write_idx =
+ intel_hws_csb_write_index(i915) -
+ I915_HWS_CSB_BUF0_INDEX;
- while (head != tail) {
- struct i915_request *r
Re: [Intel-gfx] [PATCH 08/31] drm/i915: Move rate-limiting request retire to after submission
On 25/06/2018 10:48, Chris Wilson wrote:
Our long standing defense against a single client from flooding the
system with requests (causing mempressure and stalls across the whole
system) is to retire the old request on every allocation. (By retiring
the oldest, we try to keep returning requests back to the system in a
steady flow.) This adds an extra step into the submission path that we
can reduce simply by moving it to after the submission itself.
We already do try to clean up a stale request list after submission, so
always retiring all completed requests fits in as a natural extension.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 26 ++
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index e1dbb544046f..e6e5eea87629 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -694,12 +694,6 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
if (ret)
goto err_unreserve;
- /* Move our oldest request to the slab-cache (if not in use!) */
- rq = list_first_entry(&ce->ring->request_list, typeof(*rq), ring_link);
- if (!list_is_last(&rq->ring_link, &ce->ring->request_list) &&
- i915_request_completed(rq))
- i915_request_retire(rq);
-
/*
* Beware: Dragons be flying overhead.
*
@@ -1110,6 +1104,8 @@ void i915_request_add(struct i915_request *request)
local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
/*
+* Move our oldest requests to the slab-cache (if not in use!)
+*
* In typical scenarios, we do not expect the previous request on
* the timeline to be still tracked by timeline->last_request if it
* has been completed. If the completed request is still here, that
@@ -1126,8 +1122,22 @@ void i915_request_add(struct i915_request *request)
* work on behalf of others -- but instead we should benefit from
* improved resource management. (Well, that's the theory at least.)
*/
- if (prev && i915_request_completed(prev))
- i915_request_retire_upto(prev);
+ do {
+ prev = list_first_entry(&ring->request_list,
+ typeof(*prev), ring_link);
+
+ /*
+* Keep the current request, the caller may not be
+* expecting it to be retired (and freed!) immediately,
+* and preserving one request from the client allows us to
+* carry forward frequently reused state onto the next
+* submission.
+*/
+ if (prev == request || !i915_request_completed(prev))
+ break;
+
+ i915_request_retire(prev);
+ } while (1);
Maybe new helper i915_request_try_retire_upto(prev)?
}
static unsigned long local_clock_us(unsigned int *cpu)
Cost benefit? Is it really so interesting to keep tweaking this? I feel
like I can stamp an r-b with the "yeah whatever" approach.. but the
commit doesn't say what we gain to explain why it is useful to spend
time reviewing it.
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 07/31] drm/i915/execlists: Direct submission of new requests (avoid tasklet/ksoftirqd)
Quoting Tvrtko Ursulin (2018-06-27 11:40:32)
>
> On 25/06/2018 10:48, Chris Wilson wrote:
> > Back in commit 27af5eea54d1 ("drm/i915: Move execlists irq handler to a
> > bottom half"), we came to the conclusion that running our CSB processing
> > and ELSP submission from inside the irq handler was a bad idea. A really
> > bad idea as we could impose nearly 1s latency on other users of the
> > system, on average! Deferring our work to a tasklet allowed us to do the
> > processing with irqs enabled, reducing the impact to an average of about
> > 50us.
> >
> > We have since eradicated the use of forcewaked mmio from inside the CSB
> > processing and ELSP submission, bringing the impact down to around 5us
> > (on Kabylake); an order of magnitude better than our measurements 2
> > years ago on Broadwell and only about 2x worse on average than the
> > gem_syslatency on an unladen system.
> >
> > In this iteration of the tasklet-vs-direct submission debate, we seek a
> > compromise where by we submit new requests immediately to the HW but
> > defer processing the CS interrupt onto a tasklet. We gain the advantage
> > of low-latency and ksoftirqd avoidance when waking up the HW, while
> > avoiding the system-wide starvation of our CS irq-storms.
> >
> > Comparing the impact on the maximum latency observed (that is the time
> > stolen from an RT process) over a 120s interval, repeated several times
> > (using gem_syslatency, similar to RT's cyclictest) while the system is
> > fully laden with i915 nops, we see that direct submission an actually
> > improve the worse case.
> >
> > Maximum latency in microseconds of a third party RT thread
> > (gem_syslatency -t 120 -f 2)
> >x Always using tasklets (a couple of >1000us outliers removed)
> >+ Only using tasklets from CS irq, direct submission of requests
> > ++
> > | + |
> > | + |
> > | + |
> > | + + |
> > | + + + |
> > | + + + + x x x |
> > | +++ + + + x x x x x x |
> > | +++ + ++ + + *x x x x x x |
> > | +++ + ++ + * *x x * x x x |
> > |+ +++ + ++ * * +*xxx * x x xx |
> > |* +++ + * *x+**xx+ * x x x |
> > | **x*++**+*x*xx+ * +x xx x x|
> > |x* **+***++*+***xx* xx*x xxx +x+|
> > | |__MA___| |
> > | |__M__A| |
> > ++
> > N Min MaxMedian AvgStddev
> > x 11891 186 124 125.28814 16.279137
> > + 12092 187 109 112.00833 13.458617
> > Difference at 95.0% confidence
> > -13.2798 +/- 3.79219
> > -10.5994% +/- 3.02677%
> > (Student's t, pooled s = 14.9237)
> >
> > However the mean latency is adversely affected:
> >
> > Mean latency in microseconds of a third party RT thread
> > (gem_syslatency -t 120 -f 1)
> >x Always using tasklets
> >+ Only using tasklets from CS irq, direct submission of requests
> > ++
> > | xx+ ++ |
> > | xx+ ++ |
> > | xx + +++ ++ |
> > | xxx + ++ |
> > | xxx + ++ |
> > | xxx + +++|
> > | xxx + ++ |
> > | ++ ++ |
> > | ++ ++ |
> > | xx+++ |
> > | xxxx +++ |
> > |x x x ++ ++ +|
> > | |__A__| |
> > | |A___|
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/31] drm/i915: Defer modeset cleanup to a secondary task (rev3)
== Series Details == Series: series starting with [01/31] drm/i915: Defer modeset cleanup to a secondary task (rev3) URL : https://patchwork.freedesktop.org/series/45325/ State : failure == Summary == Applying: drm/i915: Defer modeset cleanup to a secondary task Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/intel_display.c Falling back to patching base and 3-way merge... No changes -- Patch already applied. Applying: drm/i915/execlists: Check for ce->state before destroy Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/intel_lrc.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_lrc.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_lrc.c error: Failed to merge in the changes. Patch failed at 0002 drm/i915/execlists: Check for ce->state before destroy Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/psr: Add psr1 live status (rev3)
== Series Details == Series: drm/i915/psr: Add psr1 live status (rev3) URL : https://patchwork.freedesktop.org/series/45143/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4383_full -> Patchwork_9437_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9437_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9437_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9437_full: === IGT changes === Warnings igt@gem_mocs_settings@mocs-rc6-bsd2: shard-kbl: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9437_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_gtt: shard-kbl: PASS -> FAIL (fdo#105347) shard-glk: PASS -> FAIL (fdo#105347) igt@drv_selftest@live_hugepages: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@drv_suspend@shrink: shard-snb: PASS -> FAIL (fdo#106886) igt@gem_softpin@noreloc-s3: shard-kbl: NOTRUN -> INCOMPLETE (fdo#103665) igt@kms_flip@dpms-vs-vblank-race: shard-apl: PASS -> FAIL (fdo#103060) igt@kms_flip_tiling@flip-to-y-tiled: shard-glk: PASS -> FAIL (fdo#103822, fdo#104724) +1 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt: shard-glk: PASS -> FAIL (fdo#103167, fdo#104724) Possible fixes igt@gem_exec_big: shard-hsw: INCOMPLETE (fdo#103540) -> PASS igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: FAIL (fdo#105703) -> PASS igt@kms_flip@flip-vs-expired-vblank: shard-glk: FAIL (fdo#105363) -> PASS igt@kms_flip_tiling@flip-x-tiled: shard-glk: FAIL (fdo#104724) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt: shard-glk: FAIL (fdo#103167, fdo#104724) -> PASS igt@kms_rotation_crc@sprite-rotation-180: shard-hsw: FAIL (fdo#103925, fdo#104724) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (6 -> 5) == Missing(1): pig-skl-6260u == Build changes == * Linux: CI_DRM_4383 -> Patchwork_9437 CI_DRM_4383: bdbdbb788dc43f68c57cd3b793f123901358c331 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9437: 149469ec93e01783a7eba674442b545ffd1197f8 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9437/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/31] drm/i915: Move rate-limiting request retire to after submission
Quoting Tvrtko Ursulin (2018-06-27 11:57:39)
>
> On 25/06/2018 10:48, Chris Wilson wrote:
> > Our long standing defense against a single client from flooding the
> > system with requests (causing mempressure and stalls across the whole
> > system) is to retire the old request on every allocation. (By retiring
> > the oldest, we try to keep returning requests back to the system in a
> > steady flow.) This adds an extra step into the submission path that we
> > can reduce simply by moving it to after the submission itself.
> >
> > We already do try to clean up a stale request list after submission, so
> > always retiring all completed requests fits in as a natural extension.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Tvrtko Ursulin
> > ---
> > drivers/gpu/drm/i915/i915_request.c | 26 ++
> > 1 file changed, 18 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_request.c
> > b/drivers/gpu/drm/i915/i915_request.c
> > index e1dbb544046f..e6e5eea87629 100644
> > --- a/drivers/gpu/drm/i915/i915_request.c
> > +++ b/drivers/gpu/drm/i915/i915_request.c
> > @@ -694,12 +694,6 @@ i915_request_alloc(struct intel_engine_cs *engine,
> > struct i915_gem_context *ctx)
> > if (ret)
> > goto err_unreserve;
> >
> > - /* Move our oldest request to the slab-cache (if not in use!) */
> > - rq = list_first_entry(&ce->ring->request_list, typeof(*rq),
> > ring_link);
> > - if (!list_is_last(&rq->ring_link, &ce->ring->request_list) &&
> > - i915_request_completed(rq))
> > - i915_request_retire(rq);
> > -
> > /*
> >* Beware: Dragons be flying overhead.
> >*
> > @@ -1110,6 +1104,8 @@ void i915_request_add(struct i915_request *request)
> > local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
> >
> > /*
> > + * Move our oldest requests to the slab-cache (if not in use!)
> > + *
> >* In typical scenarios, we do not expect the previous request on
> >* the timeline to be still tracked by timeline->last_request if it
> >* has been completed. If the completed request is still here, that
> > @@ -1126,8 +1122,22 @@ void i915_request_add(struct i915_request *request)
> >* work on behalf of others -- but instead we should benefit from
> >* improved resource management. (Well, that's the theory at least.)
> >*/
> > - if (prev && i915_request_completed(prev))
> > - i915_request_retire_upto(prev);
> > + do {
> > + prev = list_first_entry(&ring->request_list,
> > + typeof(*prev), ring_link);
> > +
> > + /*
> > + * Keep the current request, the caller may not be
> > + * expecting it to be retired (and freed!) immediately,
> > + * and preserving one request from the client allows us to
> > + * carry forward frequently reused state onto the next
> > + * submission.
> > + */
> > + if (prev == request || !i915_request_completed(prev))
> > + break;
> > +
> > + i915_request_retire(prev);
> > + } while (1);
>
> Maybe new helper i915_request_try_retire_upto(prev)?
try_retire_before() I'm just feeling confusion in the name. Not yet
sold, and certainly don't want to invite more users :)
> > static unsigned long local_clock_us(unsigned int *cpu)
> >
>
> Cost benefit? Is it really so interesting to keep tweaking this? I feel
> like I can stamp an r-b with the "yeah whatever" approach.. but the
> commit doesn't say what we gain to explain why it is useful to spend
> time reviewing it.
The true cost was the contention the earlier retirement was causing with
the still inflight ELSP. The cost of that contention is less with the
current series, but the implication was made.
-Chris
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[Intel-gfx] [PATCH] horror
---
drivers/gpu/drm/i915/i915_drv.c | 8
drivers/gpu/drm/i915/i915_drv.h | 12
drivers/gpu/drm/i915/i915_request.c | 7 +--
3 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5ba785387c2b..3c2625b50448 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1479,6 +1479,14 @@ static void i915_driver_release(struct drm_device *dev)
kfree(dev_priv);
}
+void i915_release(struct kref *kref)
+{
+ struct drm_i915_private *i915 =
+ container_of(kref, struct drm_i915_private, drm.ref);
+
+ i915_driver_release(&i915->drm);
+}
+
static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 397e587a8688..052e4952e370 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3552,4 +3552,16 @@ static inline int intel_hws_csb_write_index(struct
drm_i915_private *i915)
return I915_HWS_CSB_WRITE_INDEX;
}
+static inline struct drm_i915_private *i915_get(struct drm_i915_private *i915)
+{
+ kref_get(&i915->drm.ref);
+ return i915;
+}
+
+void i915_release(struct kref *kref);
+static inline void i915_put(struct drm_i915_private *i915)
+{
+ kref_put(&i915->drm.ref, i915_release);
+}
+
#endif
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index e808087928f7..6753fe8e6400 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -74,6 +74,7 @@ static signed long i915_fence_wait(struct dma_fence *fence,
static void i915_fence_release(struct dma_fence *fence)
{
struct i915_request *rq = to_request(fence);
+ struct drm_i915_private *i915 = rq->i915;
/*
* The request is put onto a RCU freelist (i.e. the address
@@ -84,7 +85,8 @@ static void i915_fence_release(struct dma_fence *fence)
*/
i915_sw_fence_fini(&rq->submit);
- kmem_cache_free(rq->i915->requests, rq);
+ kmem_cache_free(i915->requests, rq);
+ i915_put(i915);
}
const struct dma_fence_ops i915_fence_ops = {
@@ -717,7 +719,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
}
INIT_LIST_HEAD(&rq->active_list);
- rq->i915 = i915;
+ rq->i915 = i915_get(i915);
rq->engine = engine;
rq->gem_context = ctx;
rq->hw_context = ce;
@@ -795,6 +797,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
kmem_cache_free(i915->requests, rq);
+ i915_put(i915);
err_unreserve:
unreserve_gt(i915);
err_unpin:
--
2.18.0
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[Intel-gfx] [PATCH] drm/i915/execlists: Reset CSB write pointer after reset
On HW reset, the HW clears the write pointer (to 0). But since it also
writes its first CSB entry to slot 0, we need to reset the write pointer
back to the element before (so the first entry we read is 0).
This is required for the next patch, where we trust the CSB completely!
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 368a8c74d11d..8b111a268697 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -884,6 +884,21 @@ static void reset_irq(struct intel_engine_cs *engine)
clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
}
+static void reset_csb_pointers(struct intel_engine_execlists *execlists)
+{
+ /*
+* After a reset, the HW starts writing into CSB entry [0]. We
+* therefore have to set our HEAD pointer back one entry so that
+* the *first* entry we check is entry 0. To complicate this further,
+* as we don't wait for the first interrupt after reset, we have to
+* fake the HW write to point back to the last entry so that our
+* inline comparison of our cached head position against the last HW
+* write works even before the first interrupt.
+*/
+ execlists->csb_head = GEN8_CSB_ENTRIES - 1;
+ WRITE_ONCE(*execlists->csb_write, (GEN8_CSB_ENTRIES - 1) | 0xff << 16);
+}
+
static void execlists_cancel_requests(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
@@ -1953,7 +1968,7 @@ static void execlists_reset(struct intel_engine_cs
*engine,
__unwind_incomplete_requests(engine);
/* Following the reset, we need to reload the CSB read/write pointers */
- engine->execlists.csb_head = GEN8_CSB_ENTRIES - 1;
+ reset_csb_pointers(&engine->execlists);
spin_unlock_irqrestore(&engine->timeline.lock, flags);
@@ -2452,7 +2467,6 @@ static int logical_ring_init(struct intel_engine_cs
*engine)
upper_32_bits(ce->lrc_desc);
}
- execlists->csb_head = GEN8_CSB_ENTRIES - 1;
execlists->csb_read =
i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
if (csb_force_mmio(i915)) {
@@ -2467,6 +2481,7 @@ static int logical_ring_init(struct intel_engine_cs
*engine)
execlists->csb_write =
&engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
}
+ reset_csb_pointers(execlists);
return 0;
--
2.18.0
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Re: [Intel-gfx] [PATCH] horror
I really must remember to proof read git send-email. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 09/31] drm/i915: Wait for engines to idle before retiring
On 25/06/2018 10:48, Chris Wilson wrote:
In the next patch, we will start to defer retiring the request from the
engine list if it is still active on the submission backend. To preserve
the semantics that after wait-for-idle completes the system is idle and
fully retired, we need to therefore wait for the backends to idle before
calling i915_retire_requests().
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 858d188dd33b..5a9cae604e2b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3810,10 +3810,13 @@ int i915_gem_wait_for_idle(struct drm_i915_private
*i915, unsigned int flags)
if (err)
return err;
}
+
+ err = wait_for_engines(i915);
+ if (err)
+ return err;
+
i915_retire_requests(i915);
GEM_BUG_ON(i915->gt.active_requests);
-
- return wait_for_engines(i915);
} else {
struct intel_engine_cs *engine;
enum intel_engine_id id;
@@ -3824,9 +3827,9 @@ int i915_gem_wait_for_idle(struct drm_i915_private *i915,
unsigned int flags)
if (err)
return err;
}
-
- return 0;
}
+
+ return 0;
}
static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj)
To me this order makes more sense in general.
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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[Intel-gfx] [PATCH 3/6] drm/i915/execlists: Process one CSB update at a time
In the next patch, we will process the CSB events directly from the
submission path, rather than only after a CS interrupt. Hence, we will
no longer have the need for a loop until the has-interrupt bit is clear,
and in the meantime can remove that small optimisation.
v2: Tvrtko pointed out it was safer to unconditionally kick the tasklet
after each irq, when assuming that the tasklet is called for each irq.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin #v1
---
drivers/gpu/drm/i915/i915_irq.c | 7 +-
drivers/gpu/drm/i915/intel_lrc.c | 278 +++
2 files changed, 141 insertions(+), 144 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 46aaef5c1851..d02f30591c0b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1473,9 +1473,10 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32
iir)
bool tasklet = false;
if (iir & GT_CONTEXT_SWITCH_INTERRUPT) {
- if (READ_ONCE(engine->execlists.active))
- tasklet = !test_and_set_bit(ENGINE_IRQ_EXECLIST,
- &engine->irq_posted);
+ if (READ_ONCE(engine->execlists.active)) {
+ set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
+ tasklet = true;
+ }
}
if (iir & GT_RENDER_USER_INTERRUPT) {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4b31e8f42aeb..91656eb2f2db 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -954,166 +954,162 @@ static void process_csb(struct intel_engine_cs *engine)
struct intel_engine_execlists * const execlists = &engine->execlists;
struct execlist_port *port = execlists->port;
struct drm_i915_private *i915 = engine->i915;
+
+ /* The HWSP contains a (cacheable) mirror of the CSB */
+ const u32 *buf =
+ &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
+ unsigned int head, tail;
bool fw = false;
- do {
- /* The HWSP contains a (cacheable) mirror of the CSB */
- const u32 *buf =
- &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
- unsigned int head, tail;
-
- /* Clear before reading to catch new interrupts */
- clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
- smp_mb__after_atomic();
-
- if (unlikely(execlists->csb_use_mmio)) {
- if (!fw) {
- intel_uncore_forcewake_get(i915,
execlists->fw_domains);
- fw = true;
- }
+ /* Clear before reading to catch new interrupts */
+ clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
+ smp_mb__after_atomic();
- buf = (u32 * __force)
- (i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
+ if (unlikely(execlists->csb_use_mmio)) {
+ intel_uncore_forcewake_get(i915, execlists->fw_domains);
+ fw = true;
- head = readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
- tail = GEN8_CSB_WRITE_PTR(head);
- head = GEN8_CSB_READ_PTR(head);
- execlists->csb_head = head;
- } else {
- const int write_idx =
- intel_hws_csb_write_index(i915) -
- I915_HWS_CSB_BUF0_INDEX;
+ buf = (u32 * __force)
+ (i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
- head = execlists->csb_head;
- tail = READ_ONCE(buf[write_idx]);
- rmb(); /* Hopefully paired with a wmb() in HW */
- }
- GEM_TRACE("%s cs-irq head=%d [%d%s], tail=%d [%d%s]\n",
- engine->name,
- head, GEN8_CSB_READ_PTR(readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?",
- tail, GEN8_CSB_WRITE_PTR(readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?");
+ head = readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
+ tail = GEN8_CSB_WRITE_PTR(head);
+ head = GEN8_CSB_READ_PTR(head);
+ execlists->csb_head = head;
+ } else {
+ const int write_idx =
+ intel_hws_csb_write_index(i915) -
+ I915_HWS_CSB_BUF0_INDEX;
- while (head != tail) {
- struct i915_request *r
[Intel-gfx] [PATCH 4/6] drm/i915/execlists: Unify CSB access pointers
Following the removal of the last workarounds, the only CSB mmio access
is for the old vGPU interface. The mmio registers presented by vGPU do
not require forcewake and can be treated as ordinary volatile memory,
i.e. they behave just like the HWSP access just at a different location.
We can reduce the CSB access to a set of read/write/buffer pointers and
treat the various paths identically and not worry about forcewake.
(Forcewake is nightmare for worstcase latency, and we want to process
this all with irqsoff -- no latency allowed!)
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_engine_cs.c | 12 ---
drivers/gpu/drm/i915/intel_lrc.c| 116 ++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 23 +++--
3 files changed, 65 insertions(+), 86 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index d3264bd6e9dc..7209c22798e6 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -25,7 +25,6 @@
#include
#include "i915_drv.h"
-#include "i915_vgpu.h"
#include "intel_ringbuffer.h"
#include "intel_lrc.h"
@@ -456,21 +455,10 @@ static void intel_engine_init_batch_pool(struct
intel_engine_cs *engine)
i915_gem_batch_pool_init(&engine->batch_pool, engine);
}
-static bool csb_force_mmio(struct drm_i915_private *i915)
-{
- /* Older GVT emulation depends upon intercepting CSB mmio */
- if (intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915))
- return true;
-
- return false;
-}
-
static void intel_engine_init_execlist(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
- execlists->csb_use_mmio = csb_force_mmio(engine->i915);
-
execlists->port_mask = 1;
BUILD_BUG_ON_NOT_POWER_OF_2(execlists_num_ports(execlists));
GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 91656eb2f2db..368a8c74d11d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -137,6 +137,7 @@
#include
#include "i915_drv.h"
#include "i915_gem_render_state.h"
+#include "i915_vgpu.h"
#include "intel_lrc_reg.h"
#include "intel_mocs.h"
#include "intel_workarounds.h"
@@ -953,44 +954,23 @@ static void process_csb(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
struct execlist_port *port = execlists->port;
- struct drm_i915_private *i915 = engine->i915;
-
- /* The HWSP contains a (cacheable) mirror of the CSB */
- const u32 *buf =
- &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
- unsigned int head, tail;
- bool fw = false;
+ const u32 * const buf = execlists->csb_status;
+ u8 head, tail;
/* Clear before reading to catch new interrupts */
clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
smp_mb__after_atomic();
- if (unlikely(execlists->csb_use_mmio)) {
- intel_uncore_forcewake_get(i915, execlists->fw_domains);
- fw = true;
-
- buf = (u32 * __force)
- (i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
+ /* Note that csb_write, csb_status may be either in HWSP or mmio */
+ head = execlists->csb_head;
+ tail = READ_ONCE(*execlists->csb_write);
+ GEM_TRACE("%s cs-irq head=%d, tail=%d\n", engine->name, head, tail);
+ if (unlikely(head == tail))
+ return;
- head = readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
- tail = GEN8_CSB_WRITE_PTR(head);
- head = GEN8_CSB_READ_PTR(head);
- execlists->csb_head = head;
- } else {
- const int write_idx =
- intel_hws_csb_write_index(i915) -
- I915_HWS_CSB_BUF0_INDEX;
+ rmb(); /* Hopefully paired with a wmb() in HW */
- head = execlists->csb_head;
- tail = READ_ONCE(buf[write_idx]);
- rmb(); /* Hopefully paired with a wmb() in HW */
- }
- GEM_TRACE("%s cs-irq head=%d [%d%s], tail=%d [%d%s]\n",
- engine->name,
- head, GEN8_CSB_READ_PTR(readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?",
- tail, GEN8_CSB_WRITE_PTR(readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?");
-
- while (head != tail) {
+ do {
struct i915_request *rq;
unsigned int status;
unsigned int count;
@@ -1016,12 +996,12 @@ static void process_csb(struct intel_engine_cs *engine)
* status notifier.
*/
-
[Intel-gfx] [PATCH 6/6] drm/i915/execlists: Direct submission of new requests (avoid tasklet/ksoftirqd)
Back in commit 27af5eea54d1 ("drm/i915: Move execlists irq handler to a
bottom half"), we came to the conclusion that running our CSB processing
and ELSP submission from inside the irq handler was a bad idea. A really
bad idea as we could impose nearly 1s latency on other users of the
system, on average! Deferring our work to a tasklet allowed us to do the
processing with irqs enabled, reducing the impact to an average of about
50us.
We have since eradicated the use of forcewaked mmio from inside the CSB
processing and ELSP submission, bringing the impact down to around 5us
(on Kabylake); an order of magnitude better than our measurements 2
years ago on Broadwell and only about 2x worse on average than the
gem_syslatency on an unladen system.
In this iteration of the tasklet-vs-direct submission debate, we seek a
compromise where by we submit new requests immediately to the HW but
defer processing the CS interrupt onto a tasklet. We gain the advantage
of low-latency and ksoftirqd avoidance when waking up the HW, while
avoiding the system-wide starvation of our CS irq-storms.
Comparing the impact on the maximum latency observed (that is the time
stolen from an RT process) over a 120s interval, repeated several times
(using gem_syslatency, similar to RT's cyclictest) while the system is
fully laden with i915 nops, we see that direct submission an actually
improve the worse case.
Maximum latency in microseconds of a third party RT thread
(gem_syslatency -t 120 -f 2)
x Always using tasklets (a couple of >1000us outliers removed)
+ Only using tasklets from CS irq, direct submission of requests
++
| + |
| + |
| + |
| + + |
| + + + |
| + + + + x x x |
| +++ + + + x x x x x x |
| +++ + ++ + + *x x x x x x |
| +++ + ++ + * *x x * x x x |
|+ +++ + ++ * * +*xxx * x x xx |
|* +++ + * *x+**xx+ * x x x |
| **x*++**+*x*xx+ * +x xx x x|
|x* **+***++*+***xx* xx*x xxx +x+|
| |__MA___| |
| |__M__A| |
++
N Min MaxMedian AvgStddev
x 11891 186 124 125.28814 16.279137
+ 12092 187 109 112.00833 13.458617
Difference at 95.0% confidence
-13.2798 +/- 3.79219
-10.5994% +/- 3.02677%
(Student's t, pooled s = 14.9237)
However the mean latency is adversely affected:
Mean latency in microseconds of a third party RT thread
(gem_syslatency -t 120 -f 1)
x Always using tasklets
+ Only using tasklets from CS irq, direct submission of requests
++
| xx+ ++ |
| xx+ ++ |
| xx + +++ ++ |
| xxx + ++ |
| xxx + ++ |
| xxx + +++|
| xxx + ++ |
| ++ ++ |
| ++ ++ |
| xx+++ |
| xxxx +++ |
|x x x ++ ++ +|
| |__A__| |
| |A___||
++
N Min MaxMedian AvgStddev
x 120 3.506 3.727 3.631 3.63214170.02773109
+ 120 3.834 4.149 4.039 4.0375167 0.041221676
Difference at 95.0% confidence
0.405375 +/- 0.00888913
11.1608% +/-
[Intel-gfx] [PATCH 2/6] drm/i915/execlists: Pull CSB reset under the timeline.lock
In the following patch, we will process the CSB events under the
timeline.lock and not serialised by the tasklet. This also means that we
will need to protect access to common variables such as
execlists->csb_head with the timeline.lock during reset.
v2: Move sync_irq to avoid deadlocks between taking timeline.lock from
our interrupt handler.
v3: Kill off the synchronize_hardirq as it raises more questions than
answered; now we use the timeline.lock entirely for CSB serialisation
between the irq and elsewhere, we don't need to be so heavy handed with
flushing
v4: Treat request cancellation (wedging after failed reset) similarly
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 009db92b67d7..4b31e8f42aeb 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -871,7 +871,6 @@ static void reset_irq(struct intel_engine_cs *engine)
{
/* Mark all CS interrupts as complete */
smp_store_mb(engine->execlists.active, 0);
- synchronize_hardirq(engine->i915->drm.irq);
clear_gtiir(engine);
@@ -908,14 +907,12 @@ static void execlists_cancel_requests(struct
intel_engine_cs *engine)
* submission's irq state, we also wish to remind ourselves that
* it is irq state.)
*/
- local_irq_save(flags);
+ spin_lock_irqsave(&engine->timeline.lock, flags);
/* Cancel the requests on the HW and clear the ELSP tracker. */
execlists_cancel_port_requests(execlists);
reset_irq(engine);
- spin_lock(&engine->timeline.lock);
-
/* Mark all executing requests as skipped. */
list_for_each_entry(rq, &engine->timeline.requests, link) {
GEM_BUG_ON(!rq->global_seqno);
@@ -949,9 +946,7 @@ static void execlists_cancel_requests(struct
intel_engine_cs *engine)
execlists->first = NULL;
GEM_BUG_ON(port_isset(execlists->port));
- spin_unlock(&engine->timeline.lock);
-
- local_irq_restore(flags);
+ spin_unlock_irqrestore(&engine->timeline.lock, flags);
}
static void process_csb(struct intel_engine_cs *engine)
@@ -1969,8 +1964,7 @@ static void execlists_reset(struct intel_engine_cs
*engine,
engine->name, request ? request->global_seqno : 0,
intel_engine_get_seqno(engine));
- /* See execlists_cancel_requests() for the irq/spinlock split. */
- local_irq_save(flags);
+ spin_lock_irqsave(&engine->timeline.lock, flags);
/*
* Catch up with any missed context-switch interrupts.
@@ -1985,14 +1979,12 @@ static void execlists_reset(struct intel_engine_cs
*engine,
reset_irq(engine);
/* Push back any incomplete requests for replay after the reset. */
- spin_lock(&engine->timeline.lock);
__unwind_incomplete_requests(engine);
- spin_unlock(&engine->timeline.lock);
/* Following the reset, we need to reload the CSB read/write pointers */
engine->execlists.csb_head = GEN8_CSB_ENTRIES - 1;
- local_irq_restore(flags);
+ spin_unlock_irqrestore(&engine->timeline.lock, flags);
/*
* If the request was innocent, we leave the request in the ELSP
--
2.18.0
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[Intel-gfx] [PATCH 1/6] drm/i915/execlists: Pull submit after dequeue under timeline lock
In the next patch, we will begin processing the CSB from inside the
submission path (underneath an irqsoff section, and even from inside
interrupt handlers). This means that updating the execlists->port[] will
no longer be serialised by the tasklet but needs to be locked by the
engine->timeline.lock instead. Pull dequeue and submit under the same
lock for protection. (An alternate future plan is to keep the in/out
arrays separate for concurrent processing and reduced lock coverage.)
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 32
1 file changed, 12 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 2b21a6596360..009db92b67d7 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -567,7 +567,7 @@ static void complete_preempt_context(struct
intel_engine_execlists *execlists)
execlists_clear_active(execlists, EXECLISTS_ACTIVE_PREEMPT);
}
-static bool __execlists_dequeue(struct intel_engine_cs *engine)
+static void __execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
struct execlist_port *port = execlists->port;
@@ -622,11 +622,11 @@ static bool __execlists_dequeue(struct intel_engine_cs
*engine)
* the HW to indicate that it has had a chance to respond.
*/
if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK))
- return false;
+ return;
if (need_preempt(engine, last, execlists->queue_priority)) {
inject_preempt_context(engine);
- return false;
+ return;
}
/*
@@ -651,7 +651,7 @@ static bool __execlists_dequeue(struct intel_engine_cs
*engine)
* priorities of the ports haven't been switch.
*/
if (port_count(&port[1]))
- return false;
+ return;
/*
* WaIdleLiteRestore:bdw,skl
@@ -751,8 +751,10 @@ static bool __execlists_dequeue(struct intel_engine_cs
*engine)
port != execlists->port ? rq_prio(last) : INT_MIN;
execlists->first = rb;
- if (submit)
+ if (submit) {
port_assign(port, last);
+ execlists_submit_ports(engine);
+ }
/* We must always keep the beast fed if we have work piled up */
GEM_BUG_ON(execlists->first && !port_isset(execlists->port));
@@ -761,24 +763,19 @@ static bool __execlists_dequeue(struct intel_engine_cs
*engine)
if (last)
execlists_user_begin(execlists, execlists->port);
- return submit;
+ /* If the engine is now idle, so should be the flag; and vice versa. */
+ GEM_BUG_ON(execlists_is_active(&engine->execlists,
+ EXECLISTS_ACTIVE_USER) ==
+ !port_isset(engine->execlists.port));
}
static void execlists_dequeue(struct intel_engine_cs *engine)
{
- struct intel_engine_execlists * const execlists = &engine->execlists;
unsigned long flags;
- bool submit;
spin_lock_irqsave(&engine->timeline.lock, flags);
- submit = __execlists_dequeue(engine);
+ __execlists_dequeue(engine);
spin_unlock_irqrestore(&engine->timeline.lock, flags);
-
- if (submit)
- execlists_submit_ports(engine);
-
- GEM_BUG_ON(port_isset(execlists->port) &&
- !execlists_is_active(execlists, EXECLISTS_ACTIVE_USER));
}
void
@@ -1161,11 +1158,6 @@ static void execlists_submission_tasklet(unsigned long
data)
if (!execlists_is_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT))
execlists_dequeue(engine);
-
- /* If the engine is now idle, so should be the flag; and vice versa. */
- GEM_BUG_ON(execlists_is_active(&engine->execlists,
- EXECLISTS_ACTIVE_USER) ==
- !port_isset(engine->execlists.port));
}
static void queue_request(struct intel_engine_cs *engine,
--
2.18.0
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[Intel-gfx] [PATCH 5/6] drm/i915/execlists: Reset CSB write pointer after reset
On HW reset, the HW clears the write pointer (to 0). But since it also
writes its first CSB entry to slot 0, we need to reset the write pointer
back to the element before (so the first entry we read is 0).
This is required for the next patch, where we trust the CSB completely!
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 368a8c74d11d..8b111a268697 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -884,6 +884,21 @@ static void reset_irq(struct intel_engine_cs *engine)
clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
}
+static void reset_csb_pointers(struct intel_engine_execlists *execlists)
+{
+ /*
+* After a reset, the HW starts writing into CSB entry [0]. We
+* therefore have to set our HEAD pointer back one entry so that
+* the *first* entry we check is entry 0. To complicate this further,
+* as we don't wait for the first interrupt after reset, we have to
+* fake the HW write to point back to the last entry so that our
+* inline comparison of our cached head position against the last HW
+* write works even before the first interrupt.
+*/
+ execlists->csb_head = GEN8_CSB_ENTRIES - 1;
+ WRITE_ONCE(*execlists->csb_write, (GEN8_CSB_ENTRIES - 1) | 0xff << 16);
+}
+
static void execlists_cancel_requests(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
@@ -1953,7 +1968,7 @@ static void execlists_reset(struct intel_engine_cs
*engine,
__unwind_incomplete_requests(engine);
/* Following the reset, we need to reload the CSB read/write pointers */
- engine->execlists.csb_head = GEN8_CSB_ENTRIES - 1;
+ reset_csb_pointers(&engine->execlists);
spin_unlock_irqrestore(&engine->timeline.lock, flags);
@@ -2452,7 +2467,6 @@ static int logical_ring_init(struct intel_engine_cs
*engine)
upper_32_bits(ce->lrc_desc);
}
- execlists->csb_head = GEN8_CSB_ENTRIES - 1;
execlists->csb_read =
i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
if (csb_force_mmio(i915)) {
@@ -2467,6 +2481,7 @@ static int logical_ring_init(struct intel_engine_cs
*engine)
execlists->csb_write =
&engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
}
+ reset_csb_pointers(execlists);
return 0;
--
2.18.0
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Re: [Intel-gfx] [PATCH 09/31] drm/i915: Wait for engines to idle before retiring
Quoting Tvrtko Ursulin (2018-06-27 12:32:35) > > To me this order makes more sense in general. Apart from the cries of struct_mutex, no! I feel a chill go up my spline for every i915_retire_requests(). (How on earth are we going to dig ourselves out of this one? One hopes the globals can be constrained...) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Remove delayed FBC activation.
Op 26-06-18 om 19:59 schreef Ville Syrjälä:
> On Mon, Jun 25, 2018 at 06:37:58PM +0200, Maarten Lankhorst wrote:
>> The only time we should start FBC is when we have waited a vblank
>> after the atomic update.
> What about front buffer tracking? Is this going to leave FBC permanently
> disabled unless there are flips/plane updates?
No, see intel_fbc_flush. If there's a race with frontbuffer tracking and page
flip,
we will not enable FBC in intel_fbc_flush(), but in that case we would enable
it from
intel_fbc_post_update().
Or the other way around, intel_fbc_post_update won't enable FBC if the fb is
dirty, but
intel_fbc_flush() afterwards will.
> I think there are a few cases we need to consider:
> 1. plane update which doesn't need fbc disable
> 2. plane update which needs to disable fbc but can re-enable it after the flip
>has happended (eg. need to reallocate the cfb due to plane size/format
> change)
> 3. plane update which needs to disable fbc and can't re-enable it (eg. the new
>plane state no longer fbc compatible)
> 4. front buffer invalidate + flush
>
> HW nuke will handle case 1. Case 2 could do the fbc re-enable after the
> post-flip vblank wait. Case 3 would ideally let us move FBC to another
> plane (thinking of pre-HSW hardware here). And case 4 must re-enable fbc
> after the flush has happened.
I don't see how this code will break any case. :)
~Maarten
>> We've already forced a vblank wait by doing
>> wait_for_flip_done before intel_post_plane_update(), so we don't need
>> to wait a second time before enabling.
>>
>> Removing the worker simplifies the code and removes possible race
>> conditions, like happening in 103167.
>>
>> Cc: Paulo Zanoni
>> Cc: Rodrigo Vivi
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103167
>> Signed-off-by: Maarten Lankhorst
>> ---
>> drivers/gpu/drm/i915/i915_debugfs.c | 5 --
>> drivers/gpu/drm/i915/i915_drv.h | 6 --
>> drivers/gpu/drm/i915/intel_fbc.c| 96 +
>> 3 files changed, 1 insertion(+), 106 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>> b/drivers/gpu/drm/i915/i915_debugfs.c
>> index c400f42a54ec..48a57c0636bf 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -1659,11 +1659,6 @@ static int i915_fbc_status(struct seq_file *m, void
>> *unused)
>> else
>> seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
>>
>> -if (fbc->work.scheduled)
>> -seq_printf(m, "FBC worker scheduled on vblank %llu, now %llu\n",
>> - fbc->work.scheduled_vblank,
>> - drm_crtc_vblank_count(&fbc->crtc->base));
>> -
>> if (intel_fbc_is_active(dev_priv)) {
>> u32 mask;
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 328d4312c438..9645dcb30454 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -580,12 +580,6 @@ struct intel_fbc {
>> unsigned int gen9_wa_cfb_stride;
>> } params;
>>
>> -struct intel_fbc_work {
>> -bool scheduled;
>> -u64 scheduled_vblank;
>> -struct work_struct work;
>> -} work;
>> -
>> const char *no_fbc_reason;
>> };
>>
>> diff --git a/drivers/gpu/drm/i915/intel_fbc.c
>> b/drivers/gpu/drm/i915/intel_fbc.c
>> index 9f9ea0b5452f..01d1d2088f04 100644
>> --- a/drivers/gpu/drm/i915/intel_fbc.c
>> +++ b/drivers/gpu/drm/i915/intel_fbc.c
>> @@ -399,89 +399,6 @@ bool intel_fbc_is_active(struct drm_i915_private
>> *dev_priv)
>> return dev_priv->fbc.active;
>> }
>>
>> -static void intel_fbc_work_fn(struct work_struct *__work)
>> -{
>> -struct drm_i915_private *dev_priv =
>> -container_of(__work, struct drm_i915_private, fbc.work.work);
>> -struct intel_fbc *fbc = &dev_priv->fbc;
>> -struct intel_fbc_work *work = &fbc->work;
>> -struct intel_crtc *crtc = fbc->crtc;
>> -struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[crtc->pipe];
>> -
>> -if (drm_crtc_vblank_get(&crtc->base)) {
>> -/* CRTC is now off, leave FBC deactivated */
>> -mutex_lock(&fbc->lock);
>> -work->scheduled = false;
>> -mutex_unlock(&fbc->lock);
>> -return;
>> -}
>> -
>> -retry:
>> -/* Delay the actual enabling to let pageflipping cease and the
>> - * display to settle before starting the compression. Note that
>> - * this delay also serves a second purpose: it allows for a
>> - * vblank to pass after disabling the FBC before we attempt
>> - * to modify the control registers.
>> - *
>> - * WaFbcWaitForVBlankBeforeEnable:ilk,snb
>> - *
>> - * It is also worth mentioning that since work->scheduled_vblank can be
>> - * updated multiple times by the other threads, hitting the timeout is
>> - * not an error condition. We'll just end up hitting the "goto r
Re: [Intel-gfx] [PATCH] drm/i915/crt: make intel_crt_reset() static again
On Thu, 21 Jun 2018, Ville Syrjälä wrote:
> On Thu, Jun 21, 2018 at 04:03:30PM +0300, Jani Nikula wrote:
>> Commit 9504a8924759 ("drm/i915/vlv: Reset the ADPA in
>> vlv_display_power_well_init()") started calling intel_crt_reset()
>> directly, while we could just as well use the hooks and keep the
>> function static.
>>
>> Cc: Lyude
>> Cc: Ville Syrjälä
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/intel_crt.c| 2 +-
>> drivers/gpu/drm/i915/intel_drv.h| 1 -
>> drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
>> 3 files changed, 2 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_crt.c
>> b/drivers/gpu/drm/i915/intel_crt.c
>> index 0c6bf82bb059..c2cb3b7a255b 100644
>> --- a/drivers/gpu/drm/i915/intel_crt.c
>> +++ b/drivers/gpu/drm/i915/intel_crt.c
>> @@ -881,7 +881,7 @@ static int intel_crt_get_modes(struct drm_connector
>> *connector)
>> return ret;
>> }
>>
>> -void intel_crt_reset(struct drm_encoder *encoder)
>> +static void intel_crt_reset(struct drm_encoder *encoder)
>> {
>> struct drm_i915_private *dev_priv = to_i915(encoder->dev);
>> struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index 0c3ac0eafde0..b2002fee1b58 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -1373,7 +1373,6 @@ void gen9_disable_guc_interrupts(struct
>> drm_i915_private *dev_priv);
>> bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
>> i915_reg_t adpa_reg, enum pipe *pipe);
>> void intel_crt_init(struct drm_i915_private *dev_priv);
>> -void intel_crt_reset(struct drm_encoder *encoder);
>>
>> /* intel_ddi.c */
>> void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
>> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
>> b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> index de3a81034f77..0b3da5818383 100644
>> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> @@ -972,7 +972,7 @@ static void vlv_display_power_well_init(struct
>> drm_i915_private *dev_priv)
>> /* Re-enable the ADPA, if we have one */
>> for_each_intel_encoder(&dev_priv->drm, encoder) {
>> if (encoder->type == INTEL_OUTPUT_ANALOG)
>> -intel_crt_reset(&encoder->base);
>> +encoder->base.funcs->reset(&encoder->base);
>
> I have a feeling I requested the direct call to make it less annoying to
> figure out what it's actually calling. But if people prefer the function
> pointer version I can live with that too.
True that, but I thought the direct call was a layering violation.
To push, or not to push, that is the question.
BR,
Jani.
>
> Reviewed-by: Ville Syrjälä
>
>> }
>>
>> i915_redisable_vga_power_on(dev_priv);
>> --
>> 2.11.0
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] [CI] drm/i915: Wait for engines to idle before retiring
In the next^W forthcoming patch, we will start to defer retiring the
request from the engine list if it is still active on the submission
backend. To preserve the semantics that after wait-for-idle completes
the system is idle and fully retired, we need to therefore wait for the
backends to idle before calling i915_retire_requests().
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 858d188dd33b..5a9cae604e2b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3810,10 +3810,13 @@ int i915_gem_wait_for_idle(struct drm_i915_private
*i915, unsigned int flags)
if (err)
return err;
}
+
+ err = wait_for_engines(i915);
+ if (err)
+ return err;
+
i915_retire_requests(i915);
GEM_BUG_ON(i915->gt.active_requests);
-
- return wait_for_engines(i915);
} else {
struct intel_engine_cs *engine;
enum intel_engine_id id;
@@ -3824,9 +3827,9 @@ int i915_gem_wait_for_idle(struct drm_i915_private *i915,
unsigned int flags)
if (err)
return err;
}
-
- return 0;
}
+
+ return 0;
}
static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object
*obj)
--
2.18.0
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Re: [Intel-gfx] [PATCH] drm/i915/icl: Add power well support
On Tue, Jun 26, 2018 at 05:28:06PM -0700, Paulo Zanoni wrote:
> Em Ter, 2018-06-26 às 17:22 +0300, Imre Deak escreveu:
> > Add the definition for ICL power wells and their mapping to power
> > domains. On ICL there are 3 power well control registers, we'll
> > select
> > the correct one based on higher bits of the power well ID. The offset
> > for the control and status flags within this register is based on the
> > lower bits of the ID as on older platforms.
> >
> > As the DC state programming is also the same as on old platforms we
> > can
> > reuse the corresponding helpers. For this we mark here the DC-off
> > power
> > well as shared among multiple platforms.
> >
> > Other than the above the delta between old platforms and ICL:
> > - Pipe C has its own power well, so we can save some additional power
> > in the
> > pipe A+B and (non-eDP) pipe A configurations.
> > - Power wells for port E/F DDI/AUX IO and Thunderbolt 1-4 AUX IO
> >
> > v2:
> > - Rebase on drm-tip after prep patch for this was merged there as
> > requested by Paulo.
> > - Actually add the new AUX and DDI power well control regs (Rakshmi)
> >
> > v3:
> > - Fix power well register names in code comments
> > - Add TBT AUX->power well 3 dependency
> >
> > v4:
> > - Rebase
> >
> > v5:
> > - Detach AUX power wells from the INIT power domain. These power
> > wells
> > can only be enabled in a TC/TBT connected state and otherwise not
> > needed during driver initialization.
> >
> > Cc: Animesh Manna
> > Cc: Rakshmi Bhatia
> > Cc: Paulo Zanoni
> > Signed-off-by: Imre Deak
> > Reviewed-by: Animesh Manna (v1)
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 78 +++-
> > drivers/gpu/drm/i915/intel_display.h| 4 +
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 329
> > +++-
> > 3 files changed, 395 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index caad19f5f557..865b05ce8d76 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1045,13 +1045,13 @@ enum i915_power_well_id {
> >
> > /*
> > * HSW/BDW
> > -* - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit:
> > id*2+1)
> > +* - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit:
> > id*2+1)
> > */
> > HSW_DISP_PW_GLOBAL = 15,
> >
> > /*
> > * GEN9+
> > -* - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit:
> > id*2+1)
> > +* - _HSW_PWR_WELL_CTL1-4 (status bit: id*2, req bit:
> > id*2+1)
> > */
> > SKL_DISP_PW_MISC_IO = 0,
> > SKL_DISP_PW_DDI_A_E,
> > @@ -1075,17 +1075,54 @@ enum i915_power_well_id {
> > SKL_DISP_PW_2,
> >
> > /* - custom power wells */
> > - SKL_DISP_PW_DC_OFF,
> > BXT_DPIO_CMN_A,
> > BXT_DPIO_CMN_BC,
> > - GLK_DPIO_CMN_C, /* 19 */
> > + GLK_DPIO_CMN_C, /* 18 */
> > +
> > + /*
> > +* GEN11+
> > +* - _HSW_PWR_WELL_CTL1-4
> > +*(status bit: (id&15)*2, req bit:(id&15)*2+1)
> > +*/
> > + ICL_DISP_PW_1 = 0,
> > + ICL_DISP_PW_2,
> > + ICL_DISP_PW_3,
> > + ICL_DISP_PW_4,
> > +
> > + /*
> > +* - _HSW_PWR_WELL_CTL_AUX1/2/4
> > +*(status bit: (id&15)*2, req bit:(id&15)*2+1)
> > +*/
> > + ICL_DISP_PW_AUX_A = 16,
> > + ICL_DISP_PW_AUX_B,
> > + ICL_DISP_PW_AUX_C,
> > + ICL_DISP_PW_AUX_D,
> > + ICL_DISP_PW_AUX_E,
> > + ICL_DISP_PW_AUX_F,
> > +
> > + ICL_DISP_PW_AUX_TBT1 = 24,
> > + ICL_DISP_PW_AUX_TBT2,
> > + ICL_DISP_PW_AUX_TBT3,
> > + ICL_DISP_PW_AUX_TBT4,
> > +
> > + /*
> > +* - _HSW_PWR_WELL_CTL_DDI1/2/4
> > +*(status bit: (id&15)*2, req bit:(id&15)*2+1)
> > +*/
> > + ICL_DISP_PW_DDI_A = 32,
> > + ICL_DISP_PW_DDI_B,
> > + ICL_DISP_PW_DDI_C,
> > + ICL_DISP_PW_DDI_D,
> > + ICL_DISP_PW_DDI_E,
> > + ICL_DISP_PW_DDI_F, /* 37 */
> >
> > /*
> > * Multiple platforms.
> > * Must start following the highest ID of any platform.
> > * - custom power wells
> > */
> > - I915_DISP_PW_ALWAYS_ON = 20,
> > + SKL_DISP_PW_DC_OFF = 38,
> > + I915_DISP_PW_ALWAYS_ON,
> > };
> >
> > #define PUNIT_REG_PWRGT_CTRL 0x60
> > @@ -1679,6 +1716,13 @@ enum i915_power_well_id {
> > #define IREF1RC_OFFSET_MASK (0xFF <<
> > IREF1RC_OFFSET_SHIFT)
> > #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy),
> > _PORT_CL1CM_DW10_BC)
> >
> > +#define _ICL_PORT_CL_DW12_A0x162030
> > +#define _ICL_PORT_CL_DW12_B0x6C030
> > +#define ICL_LANE_ENABLE_AUX (1 << 0)
> > +#define ICL_PORT_CL_DW12(port) _MMIO(_PICK((port),
>
> You can get away with _PIPE instead of _PICK here, which is supposed to
> be a little more efficient.
There's a third instance of the register with a different offset, but
yes we can use _PIPE until that is taken into use. Will change that
along with the chec
Re: [Intel-gfx] [PATCH 04/10] drm/rockchip/crc: Implement verify_crc_source callback
On Tue, 26 Jun 2018, Mahesh Kumar wrote:
> This patch implements "verify_crc_source" callback function for
> rockchip drm driver.
>
> Signed-off-by: Mahesh Kumar
> Cc: dri-de...@lists.freedesktop.org
> ---
> drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 21 +
> 1 file changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> index c9222119767d..ea4884ac4cb0 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> @@ -1138,12 +1138,32 @@ static int vop_crtc_set_crc_source(struct drm_crtc
> *crtc,
>
> return ret;
> }
> +
> +static int
> +vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
> +size_t *values_cnt)
> +{
> + if ((source_name && strcmp(source_name, "auto") == 0) || !source_name) {
Drive-by review:
IOW,
if (!source_name || strcmp(source_name, "auto") == 0)
Better yet, reverse the logic,
if (source_name && strcmp(source_name, "auto") != 0)
return -EINVAL;
*values_cnt = 3;
return 0;
BR,
Jani.
> + *values_cnt = 3;
> + return 0;
> + }
> +
> + return -EINVAL;
> +}
> +
> #else
> static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
> const char *source_name, size_t *values_cnt)
> {
> return -ENODEV;
> }
> +
> +static int
> +vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
> +size_t *values_cnt)
> +{
> + return -ENODEV;
> +}
> #endif
>
> static const struct drm_crtc_funcs vop_crtc_funcs = {
> @@ -1156,6 +1176,7 @@ static const struct drm_crtc_funcs vop_crtc_funcs = {
> .enable_vblank = vop_crtc_enable_vblank,
> .disable_vblank = vop_crtc_disable_vblank,
> .set_crc_source = vop_crtc_set_crc_source,
> + .verify_crc_source = vop_crtc_verify_crc_source,
> };
>
> static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] [REGRESSION] 4.18-rc2: X61s thinkpad display unusable after xlock & lid close
Hello, Beginning with 4.18, when I lock my X server using the `xlock` command, and close the lid, upon reopening the lid I am not presented with the xlock UI. The system is not hung. If I blindly enter the password, I get an intact and functional pointer but none of the desktop is displayed. I can move the pointer, and cycling window focus generates some random noise occasionally, but it's all nonsensical. No windows are discernable, it's just blackness with ephemeral noise on window cycles, and a movable pointer. The system does not suspend on lid close, with "HandleLidSwitch=ignore" in logind.conf. So this is a bit odd, since I don't observe this when I just run `xlock` but don't close/open the lid before unlocking. This is on Debian 9.4 amd64, the hardware is a 1.8Ghz X61s ThinkPad, kernel config attached. I'm using the modesetting Xorg driver on i915 KMS. Regards, Vito Caputo ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/8] drm/fb-helper: Eliminate the .best_encoder() usage
On Wed, Jun 27, 2018 at 11:03:31AM +0200, Daniel Vetter wrote:
> On Tue, Jun 26, 2018 at 08:47:07PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Instead of using the .best_encoder() hook to figure out whether a given
> > connector+crtc combo will work, let's instead do what userspace does and
> > just iterate over all the encoders for the connector, and then check
> > each crtc against each encoder's possible_crtcs bitmask.
> >
> > Cc: Dhinakaran Pandiyan
> > Cc: Harry Wentland
> > Cc: Daniel Vetter
> > Acked-by: Daniel Vetter
> > Suggested-by: Daniel Vetter
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/drm_fb_helper.c | 36 +++-
> > 1 file changed, 19 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_fb_helper.c
> > b/drivers/gpu/drm/drm_fb_helper.c
> > index cab14f253384..61c39cd75a27 100644
> > --- a/drivers/gpu/drm/drm_fb_helper.c
> > +++ b/drivers/gpu/drm/drm_fb_helper.c
> > @@ -2323,6 +2323,23 @@ static bool drm_target_preferred(struct
> > drm_fb_helper *fb_helper,
> > return true;
> > }
> >
> > +static bool connector_crtc_ok(struct drm_connector *connector,
> > + struct drm_crtc *crtc)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
> > + struct drm_encoder *encoder =
> > + drm_encoder_find(connector->dev, NULL,
> > +connector->encoder_ids[i]);
> > +
>
> Shouldn't we also check for encoder != NULL here? Just for the case where
> a connector does not work on the given crtc, where we do expect to
> actually run off the end of the valid entries in the array.
Yeah. This one is obviously crap. Originally I had it after the
for_each_encoder_ids() thing so didn't need any checks, but then
thought I should move it before just in case people don't like
that particular macro. And apparently forgot to think when doing
that.
>
> With that fixed:
>
> Reviewed-by: Daniel Vetter
>
> > + if (encoder->possible_crtcs & drm_crtc_mask(crtc))
> > + return true;
> > + }
> > +
> > + return false;
> > +}
> > +
> > static int drm_pick_crtcs(struct drm_fb_helper *fb_helper,
> > struct drm_fb_helper_crtc **best_crtcs,
> > struct drm_display_mode **modes,
> > @@ -2331,7 +2348,6 @@ static int drm_pick_crtcs(struct drm_fb_helper
> > *fb_helper,
> > int c, o;
> > struct drm_connector *connector;
> > const struct drm_connector_helper_funcs *connector_funcs;
> > - struct drm_encoder *encoder;
> > int my_score, best_score, score;
> > struct drm_fb_helper_crtc **crtcs, *crtc;
> > struct drm_fb_helper_connector *fb_helper_conn;
> > @@ -2362,20 +2378,6 @@ static int drm_pick_crtcs(struct drm_fb_helper
> > *fb_helper,
> >
> > connector_funcs = connector->helper_private;
> >
> > - /*
> > -* If the DRM device implements atomic hooks and ->best_encoder() is
> > -* NULL we fallback to the default drm_atomic_helper_best_encoder()
> > -* helper.
> > -*/
> > - if (drm_drv_uses_atomic_modeset(fb_helper->dev) &&
> > - !connector_funcs->best_encoder)
> > - encoder = drm_atomic_helper_best_encoder(connector);
> > - else
> > - encoder = connector_funcs->best_encoder(connector);
> > -
> > - if (!encoder)
> > - goto out;
> > -
> > /*
> > * select a crtc for this connector and then attempt to configure
> > * remaining connectors
> > @@ -2383,7 +2385,7 @@ static int drm_pick_crtcs(struct drm_fb_helper
> > *fb_helper,
> > for (c = 0; c < fb_helper->crtc_count; c++) {
> > crtc = &fb_helper->crtc_info[c];
> >
> > - if ((encoder->possible_crtcs & (1 << c)) == 0)
> > + if (!connector_crtc_ok(connector, crtc->mode_set.crtc))
> > continue;
> >
> > for (o = 0; o < n; o++)
> > @@ -2410,7 +2412,7 @@ static int drm_pick_crtcs(struct drm_fb_helper
> > *fb_helper,
> >sizeof(struct drm_fb_helper_crtc *));
> > }
> > }
> > -out:
> > +
> > kfree(crtcs);
> > return best_score;
> > }
> > --
> > 2.16.4
> >
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Ville Syrjälä
Intel
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for horror
== Series Details == Series: horror URL : https://patchwork.freedesktop.org/series/45480/ State : warning == Summary == $ dim checkpatch origin/drm-tip c0c89f80325f horror -:17: ERROR:TRAILING_WHITESPACE: trailing whitespace #17: FILE: drivers/gpu/drm/i915/i915_drv.c:1473: +^Istruct drm_i915_private *i915 = $ -:85: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s) total: 2 errors, 0 warnings, 0 checks, 61 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for horror
== Series Details == Series: horror URL : https://patchwork.freedesktop.org/series/45480/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4383 -> Patchwork_9440 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_9440 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9440, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/45480/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9440: === IGT changes === Possible regressions igt@gem_mmap@basic-small-bo: fi-glk-dsi: PASS -> INCOMPLETE == Known issues == Here are the changes found in Patchwork_9440 that come from known issues: === IGT changes === Issues hit igt@drv_module_reload@basic-no-display: fi-cnl-psr: NOTRUN -> DMESG-WARN (fdo#105395) +2 igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927) fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#105395 https://bugs.freedesktop.org/show_bug.cgi?id=105395 == Participating hosts (44 -> 40) == Additional (1): fi-cnl-psr Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4383 -> Patchwork_9440 CI_DRM_4383: bdbdbb788dc43f68c57cd3b793f123901358c331 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9440: c0c89f80325f48aa97090292117f63cb5c031bb0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c0c89f80325f horror == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9440/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/31] drm/i915: Defer modeset cleanup to a secondary task (rev4)
== Series Details == Series: series starting with [01/31] drm/i915: Defer modeset cleanup to a secondary task (rev4) URL : https://patchwork.freedesktop.org/series/45325/ State : failure == Summary == Applying: drm/i915: Defer modeset cleanup to a secondary task Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/intel_display.c Falling back to patching base and 3-way merge... No changes -- Patch already applied. Applying: drm/i915/execlists: Check for ce->state before destroy Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/intel_lrc.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_lrc.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_lrc.c error: Failed to merge in the changes. Patch failed at 0002 drm/i915/execlists: Check for ce->state before destroy Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [REGRESSION] 4.18-rc2: X61s thinkpad display unusable after xlock & lid close
On Tue, 26 Jun 2018, Vito Caputo wrote: > Beginning with 4.18, when I lock my X server using the `xlock` command, > and close the lid, upon reopening the lid I am not presented with the > xlock UI. Please file a bug report at [1]. Please include Xorg.0.log and dmesg with drm.debug=14 reproducing the problem. For fastest results, please git bisect. BR, Jani. [1] https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=DRM/Intel -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915/execlists: Pull submit after dequeue under timeline lock
== Series Details ==
Series: series starting with [1/6] drm/i915/execlists: Pull submit after
dequeue under timeline lock
URL : https://patchwork.freedesktop.org/series/45482/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2f29c7874491 drm/i915/execlists: Pull submit after dequeue under timeline lock
384a361612d3 drm/i915/execlists: Pull CSB reset under the timeline.lock
9856695d1f7d drm/i915/execlists: Process one CSB update at a time
-:68: WARNING:MEMORY_BARRIER: memory barrier without comment
#68: FILE: drivers/gpu/drm/i915/intel_lrc.c:966:
+ smp_mb__after_atomic();
-:114: WARNING:LONG_LINE: line over 100 characters
#114: FILE: drivers/gpu/drm/i915/intel_lrc.c:990:
+ head, GEN8_CSB_READ_PTR(readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?",
-:115: WARNING:LONG_LINE: line over 100 characters
#115: FILE: drivers/gpu/drm/i915/intel_lrc.c:991:
+ tail, GEN8_CSB_WRITE_PTR(readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?");
-:183: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#183: FILE: drivers/gpu/drm/i915/intel_lrc.c:1022:
+ status, buf[2*head + 1],
^
-:211: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#211: FILE: drivers/gpu/drm/i915/intel_lrc.c:1040:
+ buf[2*head + 1] == execlists->preempt_complete_status) {
^
total: 0 errors, 3 warnings, 2 checks, 316 lines checked
85e5b9862d79 drm/i915/execlists: Unify CSB access pointers
abf1c8fb921b drm/i915/execlists: Reset CSB write pointer after reset
12a239a0de57 drm/i915/execlists: Direct submission of new requests (avoid
tasklet/ksoftirqd)
-:104: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#104:
References: 27af5eea54d1 ("drm/i915: Move execlists irq handler to a bottom
half")
-:104: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit
<12+ chars of sha1> ("")' - ie: 'commit 27af5eea54d1 ("drm/i915:
Move execlists irq handler to a bottom half")'
#104:
References: 27af5eea54d1 ("drm/i915: Move execlists irq handler to a bottom
half")
total: 1 errors, 1 warnings, 0 checks, 325 lines checked
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Re: [Intel-gfx] [PATCH] horror
On Wed, 27 Jun 2018, Chris Wilson wrote: > I really must remember to proof read git send-email. I did like the subsequent "warning for horror" and "failure for horror" messages from CI though. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915/execlists: Pull submit after dequeue under timeline lock
== Series Details == Series: series starting with [1/6] drm/i915/execlists: Pull submit after dequeue under timeline lock URL : https://patchwork.freedesktop.org/series/45482/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4383 -> Patchwork_9442 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_9442 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9442, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/45482/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9442: === IGT changes === Possible regressions igt@gem_mmap@basic-small-bo: fi-glk-dsi: PASS -> INCOMPLETE == Known issues == Here are the changes found in Patchwork_9442 that come from known issues: === IGT changes === Issues hit igt@drv_module_reload@basic-no-display: fi-cnl-psr: NOTRUN -> DMESG-WARN (fdo#105395) +2 igt@gem_exec_gttfill@basic: fi-byt-n2820: PASS -> FAIL (fdo#106744) fdo#105395 https://bugs.freedesktop.org/show_bug.cgi?id=105395 fdo#106744 https://bugs.freedesktop.org/show_bug.cgi?id=106744 == Participating hosts (44 -> 40) == Additional (1): fi-cnl-psr Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4383 -> Patchwork_9442 CI_DRM_4383: bdbdbb788dc43f68c57cd3b793f123901358c331 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4530: 0e98bf69f146eb72fe3a7c3b19a049b5786f0ca3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9442: 12a239a0de57b50f1a27ca5beaa884e4710c0092 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 12a239a0de57 drm/i915/execlists: Direct submission of new requests (avoid tasklet/ksoftirqd) abf1c8fb921b drm/i915/execlists: Reset CSB write pointer after reset 85e5b9862d79 drm/i915/execlists: Unify CSB access pointers 9856695d1f7d drm/i915/execlists: Process one CSB update at a time 384a361612d3 drm/i915/execlists: Pull CSB reset under the timeline.lock 2f29c7874491 drm/i915/execlists: Pull submit after dequeue under timeline lock == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9442/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/6] drm/i915/execlists: Process one CSB update at a time
On 27/06/2018 12:38, Chris Wilson wrote:
In the next patch, we will process the CSB events directly from the
submission path, rather than only after a CS interrupt. Hence, we will
no longer have the need for a loop until the has-interrupt bit is clear,
and in the meantime can remove that small optimisation.
v2: Tvrtko pointed out it was safer to unconditionally kick the tasklet
after each irq, when assuming that the tasklet is called for each irq.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin #v1
Okay I can swallow it.
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_irq.c | 7 +-
drivers/gpu/drm/i915/intel_lrc.c | 278 +++
2 files changed, 141 insertions(+), 144 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 46aaef5c1851..d02f30591c0b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1473,9 +1473,10 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32
iir)
bool tasklet = false;
if (iir & GT_CONTEXT_SWITCH_INTERRUPT) {
- if (READ_ONCE(engine->execlists.active))
- tasklet = !test_and_set_bit(ENGINE_IRQ_EXECLIST,
- &engine->irq_posted);
+ if (READ_ONCE(engine->execlists.active)) {
+ set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
+ tasklet = true;
+ }
}
if (iir & GT_RENDER_USER_INTERRUPT) {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4b31e8f42aeb..91656eb2f2db 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -954,166 +954,162 @@ static void process_csb(struct intel_engine_cs *engine)
struct intel_engine_execlists * const execlists = &engine->execlists;
struct execlist_port *port = execlists->port;
struct drm_i915_private *i915 = engine->i915;
+
+ /* The HWSP contains a (cacheable) mirror of the CSB */
+ const u32 *buf =
+ &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
+ unsigned int head, tail;
bool fw = false;
- do {
- /* The HWSP contains a (cacheable) mirror of the CSB */
- const u32 *buf =
- &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
- unsigned int head, tail;
-
- /* Clear before reading to catch new interrupts */
- clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
- smp_mb__after_atomic();
-
- if (unlikely(execlists->csb_use_mmio)) {
- if (!fw) {
- intel_uncore_forcewake_get(i915,
execlists->fw_domains);
- fw = true;
- }
+ /* Clear before reading to catch new interrupts */
+ clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
+ smp_mb__after_atomic();
- buf = (u32 * __force)
- (i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
+ if (unlikely(execlists->csb_use_mmio)) {
+ intel_uncore_forcewake_get(i915, execlists->fw_domains);
+ fw = true;
- head = readl(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
- tail = GEN8_CSB_WRITE_PTR(head);
- head = GEN8_CSB_READ_PTR(head);
- execlists->csb_head = head;
- } else {
- const int write_idx =
- intel_hws_csb_write_index(i915) -
- I915_HWS_CSB_BUF0_INDEX;
+ buf = (u32 * __force)
+ (i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
- head = execlists->csb_head;
- tail = READ_ONCE(buf[write_idx]);
- rmb(); /* Hopefully paired with a wmb() in HW */
- }
- GEM_TRACE("%s cs-irq head=%d [%d%s], tail=%d [%d%s]\n",
- engine->name,
- head, GEN8_CSB_READ_PTR(readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?",
- tail, GEN8_CSB_WRITE_PTR(readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine, fw ? "" : "?");
+ head = readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
+ tail = GEN8_CSB_WRITE_PTR(head);
+ head = GEN8_CSB_READ_PTR(head);
+ execlists->csb_head = head;
+ } else {
+ const int write_idx =
+ intel_hws_csb_write_index(i915) -
+ I915_HWS_CSB_BUF0_INDEX;
- while (head != tail) {
-
Re: [Intel-gfx] [PATCH 06/31] drm/i915/execlists: Unify CSB access pointers
On 27/06/2018 11:35, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-06-27 10:52:45)
On 25/06/2018 10:48, Chris Wilson wrote:
@@ -1109,16 +1089,11 @@ static void process_csb(struct intel_engine_cs *engine)
} else {
port_set(port, port_pack(rq, count));
}
- }
+ } while (head != tail);
- if (head != execlists->csb_head) {
- execlists->csb_head = head;
- writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8),
-i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
- }
-
- if (unlikely(fw))
- intel_uncore_forcewake_put(i915, execlists->fw_domains);
+ writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8),
+execlists->csb_read);
Continuing from the last round - so what to do with this one? It does
need forcewake. So I think it needs to go if we are claiming there is no
mmio any longer.
From last round, we decided it didn't, or at least concluded the
(from the lack of) evidence that it does not, because we are not using
forcewake right now...
But we are not sure if our writes stick 100% of the time due using the
HWSP path. And we are wasting time on MMIO for nothing. Put an "if
(execlists->csb_use_mmio)" on it?
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 12/31] drm/i915: Reduce spinlock hold time during notify_ring() interrupt
Chris Wilson writes:
> By taking advantage of the RCU protection of the task struct, we can find
> the appropriate signaler under the spinlock and then release the spinlock
> before waking the task and signaling the fence.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_irq.c | 33 ++---
> 1 file changed, 22 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 316d0b08d40f..53dad48f92ce 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1145,21 +1145,23 @@ static void ironlake_rps_change_irq_handler(struct
> drm_i915_private *dev_priv)
>
> static void notify_ring(struct intel_engine_cs *engine)
> {
> + const u32 seqno = intel_engine_get_seqno(engine);
> struct i915_request *rq = NULL;
> + struct task_struct *tsk = NULL;
> struct intel_wait *wait;
>
> - if (!engine->breadcrumbs.irq_armed)
> + if (unlikely(!engine->breadcrumbs.irq_armed))
> return;
>
Ok, so due to unlikeliness, you get the seqno early.
> atomic_inc(&engine->irq_count);
> - set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
> +
> + rcu_read_lock();
As I understand from irc discussion, we have our own const
or stable copy of task struct from now on.
>
> spin_lock(&engine->breadcrumbs.irq_lock);
> wait = engine->breadcrumbs.irq_wait;
> if (wait) {
> - bool wakeup = engine->irq_seqno_barrier;
> -
> - /* We use a callback from the dma-fence to submit
> + /*
> + * We use a callback from the dma-fence to submit
>* requests after waiting on our own requests. To
>* ensure minimum delay in queuing the next request to
>* hardware, signal the fence now rather than wait for
> @@ -1170,19 +1172,23 @@ static void notify_ring(struct intel_engine_cs
> *engine)
>* and to handle coalescing of multiple seqno updates
>* and many waiters.
>*/
> - if (i915_seqno_passed(intel_engine_get_seqno(engine),
> - wait->seqno)) {
> + if (i915_seqno_passed(seqno, wait->seqno)) {
> struct i915_request *waiter = wait->request;
>
> - wakeup = true;
> if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
> &waiter->fence.flags) &&
> intel_wait_check_request(wait, waiter))
> rq = i915_request_get(waiter);
> - }
>
> - if (wakeup)
> - wake_up_process(wait->tsk);
> + tsk = wait->tsk;
> + } else {
> + if (engine->irq_seqno_barrier &&
> + i915_seqno_passed(seqno, wait->seqno - 1)) {
> + set_bit(ENGINE_IRQ_BREADCRUMB,
> + &engine->irq_posted);
> + tsk = wait->tsk;
Hmm, you are optimistic that the latency of wakeup will be on par
or greater than the next request completion?
And wait side notices too that we are close and spins,
instead of going back to sleep?
> + }
> + }
> } else {
> if (engine->breadcrumbs.irq_armed)
> __intel_engine_disarm_breadcrumbs(engine);
> @@ -1195,6 +1201,11 @@ static void notify_ring(struct intel_engine_cs *engine)
> i915_request_put(rq);
> }
>
> + if (tsk && tsk->state & TASK_NORMAL)
> + wake_up_process(tsk);
> +
Why the TASK_NORMAL check?
-Mika
> + rcu_read_unlock();
> +
> trace_intel_engine_notify(engine, wait);
> }
>
> --
> 2.18.0
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[Intel-gfx] [PATCH v3 3/9] drm/pl111: Set .gem_prime_vmap and .gem_prime_mmap
These are needed for pl111 to use the generic fbdev emulation.
Cc: Eric Anholt
Signed-off-by: Noralf Trønnes
Reviewed-by: Eric Anholt
---
drivers/gpu/drm/pl111/pl111_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/pl111/pl111_drv.c
b/drivers/gpu/drm/pl111/pl111_drv.c
index 454ff0804642..78854b52676c 100644
--- a/drivers/gpu/drm/pl111/pl111_drv.c
+++ b/drivers/gpu/drm/pl111/pl111_drv.c
@@ -249,6 +249,8 @@ static struct drm_driver pl111_drm_driver = {
.gem_prime_import_sg_table = pl111_gem_import_sg_table,
.gem_prime_export = drm_gem_prime_export,
.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
+ .gem_prime_mmap = drm_gem_cma_prime_mmap,
+ .gem_prime_vmap = drm_gem_cma_prime_vmap,
#if defined(CONFIG_DEBUG_FS)
.debugfs_init = pl111_debugfs_init,
--
2.15.1
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