Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Enable provoking vertex fix on Gen9+ systems.
Quoting Patchwork (2018-06-14 23:53:30)
> == Series Details ==
>
> Series: drm/i915: Enable provoking vertex fix on Gen9+ systems.
> URL : https://patchwork.freedesktop.org/series/44781/
> State : failure
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_4322 -> Patchwork_9312 =
>
> == Summary - FAILURE ==
>
> Serious unknown changes coming with Patchwork_9312 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_9312, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL:
> https://patchwork.freedesktop.org/api/1.0/series/44781/revisions/1/mbox/
>
> == Possible new issues ==
>
> Here are the unknown changes that may have been introduced in
> Patchwork_9312:
>
> === IGT changes ===
>
> Possible regressions
>
> igt@gem_workarounds@basic-read:
> fi-skl-6260u: PASS -> FAIL
> fi-cfl-s3: PASS -> FAIL
> fi-skl-6700k2: PASS -> FAIL
> fi-skl-6770hq: PASS -> FAIL
> fi-kbl-7560u: PASS -> FAIL
> fi-skl-6600u: PASS -> FAIL
> fi-bxt-dsi: PASS -> FAIL
> fi-kbl-guc: PASS -> FAIL
> fi-kbl-7500u: PASS -> FAIL
> fi-skl-6700hq: PASS -> FAIL
> fi-bxt-j4205: PASS -> FAIL
> fi-skl-gvtdvm: PASS -> FAIL
> fi-cfl-guc: PASS -> FAIL
> {fi-whl-u}: PASS -> FAIL
> fi-cfl-8700k: PASS -> FAIL
> fi-glk-j4005: PASS -> FAIL
> fi-skl-guc: PASS -> FAIL
> fi-kbl-7567u: PASS -> FAIL
> fi-kbl-r: PASS -> FAIL
(gem_workarounds:3828) DEBUG: Address val maskread
result
(gem_workarounds:3828) DEBUG: 0x07014 0x20002000 0x2000
0x2000 OK
(gem_workarounds:3828) DEBUG: 0x0E194 0x01000100 0x0100
0x0114 OK
(gem_workarounds:3828) DEBUG: 0x0E4F0 0x81008100 0x8100
0x8120 OK
(gem_workarounds:3828) DEBUG: 0x0E184 0x00200020 0x0020
0x0022 OK
(gem_workarounds:3828) DEBUG: 0x0E194 0x00140014 0x0014
0x0114 OK
(gem_workarounds:3828) DEBUG: 0x07004 0x00420042 0x0042
0x29C2 OK
(gem_workarounds:3828) DEBUG: 0x0E188 0x0008 0x0008
0x8030 OK
(gem_workarounds:3828) DEBUG: 0x07300 0x80208020 0x8020
0x8830 OK
(gem_workarounds:3828) DEBUG: 0x07300 0x00100010 0x0010
0x8830 OK
(gem_workarounds:3828) DEBUG: 0x0E184 0x00020002 0x0002
0x0022 OK
(gem_workarounds:3828) DEBUG: 0x0E180 0x20002000 0x2000
0x2000 OK
(gem_workarounds:3828) DEBUG: 0x02580 0x0001 0x0001
0x0004 OK
(gem_workarounds:3828) DEBUG: 0x02580 0x00060004 0x0006
0x0004 OK
(gem_workarounds:3828) WARNING: 0x02088 0x00020002 0x0002
0x FAIL
(gem_workarounds:3828) WARNING: 0x02090 0x10001000 0x1000
0x FAIL
The 2 writes didn't stick. Not context saved? Or something even more
peculiar?
(Look at all those repeated register writes, no wonder we ran out of
space.)
-Chris
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/whl: Introducing Whiskey Lake platform
== Series Details == Series: series starting with [1/2] drm/i915/whl: Introducing Whiskey Lake platform URL : https://patchwork.freedesktop.org/series/44782/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4322_full -> Patchwork_9313_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9313_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9313_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9313_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-render: shard-kbl: SKIP -> PASS igt@gem_mocs_settings@mocs-rc6-ctx-render: shard-kbl: PASS -> SKIP igt@pm_rc6_residency@rc6-accuracy: shard-snb: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_9313_full that come from known issues: === IGT changes === Issues hit igt@gem_exec_suspend@basic-s3: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@gem_ppgtt@blt-vs-render-ctx0: shard-kbl: PASS -> INCOMPLETE (fdo#106023, fdo#103665) igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy: shard-hsw: PASS -> FAIL (fdo#102670) igt@kms_flip@2x-modeset-vs-vblank-race: shard-glk: PASS -> FAIL (fdo#103060) igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-hsw: PASS -> FAIL (fdo#105189) igt@kms_flip_tiling@flip-to-x-tiled: shard-glk: PASS -> FAIL (fdo#104724) igt@perf_pmu@other-init-2: shard-snb: PASS -> INCOMPLETE (fdo#105411) Possible fixes igt@drv_selftest@live_gtt: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: shard-hsw: FAIL (fdo#100368) -> PASS shard-glk: FAIL (fdo#100368) -> PASS +1 igt@kms_flip@plain-flip-ts-check: shard-hsw: FAIL (fdo#103928) -> PASS igt@kms_flip_tiling@flip-y-tiled: shard-glk: FAIL (fdo#103822, fdo#104724) -> PASS igt@kms_setmode@basic: shard-kbl: FAIL (fdo#99912) -> PASS igt@testdisplay: shard-kbl: WARN -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4322 -> Patchwork_9313 CI_DRM_4322: 485f975b0c64f2a3c9b0bf116a63adc3c6389b1f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4519: 3381a56be31defb3b5c23a4fbc19ac26a000c35b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9313: 0a4e7fa1669fb3e63e2576a835cb77c84d99c361 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9313/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Keep the ctx workarounds tightly packed
For each platform, we have a few registers that rewritten with multiple
values -- they are not part of a sequence, just different parts of a
masked register set at different times (e.g. platform and gen
workarounds). Consolidate these into a single register write to keep the
table compact.
While adjusting the construction of the wa table, make it non fatal so
that the driver still loads but keeping the warning and extra details
for inspection.
Signed-off-by: Chris Wilson
Cc: Oscar Mateo
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c | 25 ++
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_workarounds.c | 63 +---
3 files changed, 52 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 99d3272d82d8..c400f42a54ec 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3378,28 +3378,13 @@ static int i915_shared_dplls_info(struct seq_file *m,
void *unused)
static int i915_wa_registers(struct seq_file *m, void *unused)
{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct i915_workarounds *workarounds = &dev_priv->workarounds;
+ struct i915_workarounds *wa = &node_to_i915(m->private)->workarounds;
int i;
- intel_runtime_pm_get(dev_priv);
-
- seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
- for (i = 0; i < workarounds->count; ++i) {
- i915_reg_t addr;
- u32 mask, value, read;
- bool ok;
-
- addr = workarounds->reg[i].addr;
- mask = workarounds->reg[i].mask;
- value = workarounds->reg[i].value;
- read = I915_READ(addr);
- ok = (value & mask) == (read & mask);
- seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x,
status: %s\n",
- i915_mmio_reg_offset(addr), value, mask, read, ok ?
"OK" : "FAIL");
- }
-
- intel_runtime_pm_put(dev_priv);
+ seq_printf(m, "Workarounds applied: %d\n", wa->count);
+ for (i = 0; i < wa->count; ++i)
+ seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
+ wa->reg[i].addr, wa->reg[i].value, wa->reg[i].mask);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 74dd88d8563e..ea389771f917 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1305,7 +1305,7 @@ struct i915_frontbuffer_tracking {
};
struct i915_wa_reg {
- i915_reg_t addr;
+ u32 addr;
u32 value;
/* bitmask representing WA bits */
u32 mask;
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 24b929ce3341..f8bb32e974f6 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -48,29 +48,58 @@
* - Public functions to init or apply the given workaround type.
*/
-static int wa_add(struct drm_i915_private *dev_priv,
- i915_reg_t addr,
- const u32 mask, const u32 val)
+static void wa_add(struct drm_i915_private *i915,
+ i915_reg_t reg, const u32 mask, const u32 val)
{
- const unsigned int idx = dev_priv->workarounds.count;
+ struct i915_workarounds *wa = &i915->workarounds;
+ unsigned int start = 0, end = wa->count;
+ unsigned int addr = i915_mmio_reg_offset(reg);
+ struct i915_wa_reg *r;
+
+ while (start < end) {
+ unsigned int mid = start + (end - start) / 2;
+
+ if (wa->reg[mid].addr < addr) {
+ start = mid + 1;
+ } else if (wa->reg[mid].addr > addr) {
+ end = mid;
+ } else {
+ r = &wa->reg[mid];
+
+ if ((mask & ~r->mask) == 0) {
+ DRM_ERROR("Discarding overwritten w/a for reg
%04x (mask: %08x, value: %08x)\n",
+ addr, r->mask, r->value);
+
+ r->value &= ~mask;
+ }
+
+ r->value |= val;
+ r->mask |= mask;
+ return;
+ }
+ }
- if (WARN_ON(idx >= I915_MAX_WA_REGS))
- return -ENOSPC;
+ if (WARN_ON_ONCE(wa->count >= I915_MAX_WA_REGS)) {
+ DRM_ERROR("Dropping w/a for reg %04x (mask: %08x, value:
%08x)\n",
+ addr, mask, val);
+ return;
+ }
- dev_priv->workarounds.reg[idx].addr = addr;
- dev_priv->workarounds.reg[idx].value = val;
- dev_priv->workarounds.reg[idx].mask = mask;
+ r = &wa->reg[wa->count++];
+ r->addr = addr;
+ r->value = val;
+ r->mas
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Enable provoking vertex fix on Gen9+ systems.
Quoting Chris Wilson (2018-06-15 08:16:01)
> Quoting Patchwork (2018-06-14 23:53:30)
> > == Series Details ==
> >
> > Series: drm/i915: Enable provoking vertex fix on Gen9+ systems.
> > URL : https://patchwork.freedesktop.org/series/44781/
> > State : failure
> >
> > == Summary ==
> >
> > = CI Bug Log - changes from CI_DRM_4322 -> Patchwork_9312 =
> >
> > == Summary - FAILURE ==
> >
> > Serious unknown changes coming with Patchwork_9312 absolutely need to be
> > verified manually.
> >
> > If you think the reported changes have nothing to do with the changes
> > introduced in Patchwork_9312, please notify your bug team to allow them
> > to document this new failure mode, which will reduce false positives in
> > CI.
> >
> > External URL:
> > https://patchwork.freedesktop.org/api/1.0/series/44781/revisions/1/mbox/
> >
> > == Possible new issues ==
> >
> > Here are the unknown changes that may have been introduced in
> > Patchwork_9312:
> >
> > === IGT changes ===
> >
> > Possible regressions
> >
> > igt@gem_workarounds@basic-read:
> > fi-skl-6260u: PASS -> FAIL
> > fi-cfl-s3: PASS -> FAIL
> > fi-skl-6700k2: PASS -> FAIL
> > fi-skl-6770hq: PASS -> FAIL
> > fi-kbl-7560u: PASS -> FAIL
> > fi-skl-6600u: PASS -> FAIL
> > fi-bxt-dsi: PASS -> FAIL
> > fi-kbl-guc: PASS -> FAIL
> > fi-kbl-7500u: PASS -> FAIL
> > fi-skl-6700hq: PASS -> FAIL
> > fi-bxt-j4205: PASS -> FAIL
> > fi-skl-gvtdvm: PASS -> FAIL
> > fi-cfl-guc: PASS -> FAIL
> > {fi-whl-u}: PASS -> FAIL
> > fi-cfl-8700k: PASS -> FAIL
> > fi-glk-j4005: PASS -> FAIL
> > fi-skl-guc: PASS -> FAIL
> > fi-kbl-7567u: PASS -> FAIL
> > fi-kbl-r: PASS -> FAIL
>
> (gem_workarounds:3828) DEBUG: Address val maskread
> result
> (gem_workarounds:3828) DEBUG: 0x07014 0x20002000 0x2000
> 0x2000 OK
> (gem_workarounds:3828) DEBUG: 0x0E194 0x01000100 0x0100
> 0x0114 OK
> (gem_workarounds:3828) DEBUG: 0x0E4F0 0x81008100 0x8100
> 0x8120 OK
> (gem_workarounds:3828) DEBUG: 0x0E184 0x00200020 0x0020
> 0x0022 OK
> (gem_workarounds:3828) DEBUG: 0x0E194 0x00140014 0x0014
> 0x0114 OK
> (gem_workarounds:3828) DEBUG: 0x07004 0x00420042 0x0042
> 0x29C2 OK
> (gem_workarounds:3828) DEBUG: 0x0E188 0x0008 0x0008
> 0x8030 OK
> (gem_workarounds:3828) DEBUG: 0x07300 0x80208020 0x8020
> 0x8830 OK
> (gem_workarounds:3828) DEBUG: 0x07300 0x00100010 0x0010
> 0x8830 OK
> (gem_workarounds:3828) DEBUG: 0x0E184 0x00020002 0x0002
> 0x0022 OK
> (gem_workarounds:3828) DEBUG: 0x0E180 0x20002000 0x2000
> 0x2000 OK
> (gem_workarounds:3828) DEBUG: 0x02580 0x0001 0x0001
> 0x0004 OK
> (gem_workarounds:3828) DEBUG: 0x02580 0x00060004 0x0006
> 0x0004 OK
> (gem_workarounds:3828) WARNING: 0x02088 0x00020002 0x0002
> 0x FAIL
> (gem_workarounds:3828) WARNING: 0x02090 0x10001000 0x1000
> 0x FAIL
>
> The 2 writes didn't stick. Not context saved? Or something even more
> peculiar?
More sinister. The LRI never expected so many registers!
-Chris
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[Intel-gfx] [PATCH 1/2] drm/i915: Keep the ctx workarounds tightly packed
For each platform, we have a few registers that rewritten with multiple
values -- they are not part of a sequence, just different parts of a
masked register set at different times (e.g. platform and gen
workarounds). Consolidate these into a single register write to keep the
table compact.
While adjusting the construction of the wa table, make it non fatal so
that the driver still loads but keeping the warning and extra details
for inspection.
Signed-off-by: Chris Wilson
Cc: Oscar Mateo
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c | 25 ++
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_workarounds.c | 63 +---
3 files changed, 52 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index c600279d3db5..f78895ffab9b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3378,28 +3378,13 @@ static int i915_shared_dplls_info(struct seq_file *m,
void *unused)
static int i915_wa_registers(struct seq_file *m, void *unused)
{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct i915_workarounds *workarounds = &dev_priv->workarounds;
+ struct i915_workarounds *wa = &node_to_i915(m->private)->workarounds;
int i;
- intel_runtime_pm_get(dev_priv);
-
- seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
- for (i = 0; i < workarounds->count; ++i) {
- i915_reg_t addr;
- u32 mask, value, read;
- bool ok;
-
- addr = workarounds->reg[i].addr;
- mask = workarounds->reg[i].mask;
- value = workarounds->reg[i].value;
- read = I915_READ(addr);
- ok = (value & mask) == (read & mask);
- seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x,
status: %s\n",
- i915_mmio_reg_offset(addr), value, mask, read, ok ?
"OK" : "FAIL");
- }
-
- intel_runtime_pm_put(dev_priv);
+ seq_printf(m, "Workarounds applied: %d\n", wa->count);
+ for (i = 0; i < wa->count; ++i)
+ seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
+ wa->reg[i].addr, wa->reg[i].value, wa->reg[i].mask);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2c12de678e32..91c389622217 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1308,7 +1308,7 @@ struct i915_frontbuffer_tracking {
};
struct i915_wa_reg {
- i915_reg_t addr;
+ u32 addr;
u32 value;
/* bitmask representing WA bits */
u32 mask;
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 24b929ce3341..f8bb32e974f6 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -48,29 +48,58 @@
* - Public functions to init or apply the given workaround type.
*/
-static int wa_add(struct drm_i915_private *dev_priv,
- i915_reg_t addr,
- const u32 mask, const u32 val)
+static void wa_add(struct drm_i915_private *i915,
+ i915_reg_t reg, const u32 mask, const u32 val)
{
- const unsigned int idx = dev_priv->workarounds.count;
+ struct i915_workarounds *wa = &i915->workarounds;
+ unsigned int start = 0, end = wa->count;
+ unsigned int addr = i915_mmio_reg_offset(reg);
+ struct i915_wa_reg *r;
+
+ while (start < end) {
+ unsigned int mid = start + (end - start) / 2;
+
+ if (wa->reg[mid].addr < addr) {
+ start = mid + 1;
+ } else if (wa->reg[mid].addr > addr) {
+ end = mid;
+ } else {
+ r = &wa->reg[mid];
+
+ if ((mask & ~r->mask) == 0) {
+ DRM_ERROR("Discarding overwritten w/a for reg
%04x (mask: %08x, value: %08x)\n",
+ addr, r->mask, r->value);
+
+ r->value &= ~mask;
+ }
+
+ r->value |= val;
+ r->mask |= mask;
+ return;
+ }
+ }
- if (WARN_ON(idx >= I915_MAX_WA_REGS))
- return -ENOSPC;
+ if (WARN_ON_ONCE(wa->count >= I915_MAX_WA_REGS)) {
+ DRM_ERROR("Dropping w/a for reg %04x (mask: %08x, value:
%08x)\n",
+ addr, mask, val);
+ return;
+ }
- dev_priv->workarounds.reg[idx].addr = addr;
- dev_priv->workarounds.reg[idx].value = val;
- dev_priv->workarounds.reg[idx].mask = mask;
+ r = &wa->reg[wa->count++];
+ r->addr = addr;
+ r->value = val;
+ r->mas
[Intel-gfx] [PATCH] drm/i915: Break workaround register emission into batches of 15
We are restricted to the number of registers we can rewrite into a
single command by the packet length. If we have more registers than can
be fitted into a single packet, we therefore need to split the writes
into multiple packets.
Reported-by: Kenneth Graunke
Signed-off-by: Chris Wilson
Cc: Oscar Mateo
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Cc: Kenneth Graunke
---
drivers/gpu/drm/i915/intel_workarounds.c | 31
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index f8bb32e974f6..d82e08af6a60 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -553,6 +553,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private
*dev_priv)
int intel_ctx_workarounds_emit(struct i915_request *rq)
{
struct i915_workarounds *w = &rq->i915->workarounds;
+ struct i915_wa_reg *reg = w->reg;
+ unsigned int remain;
u32 *cs;
int ret, i;
@@ -563,18 +565,27 @@ int intel_ctx_workarounds_emit(struct i915_request *rq)
if (ret)
return ret;
- cs = intel_ring_begin(rq, (w->count * 2 + 2));
- if (IS_ERR(cs))
- return PTR_ERR(cs);
+ remain = w->count;
+ do {
+ unsigned int count;
- *cs++ = MI_LOAD_REGISTER_IMM(w->count);
- for (i = 0; i < w->count; i++) {
- *cs++ = w->reg[i].addr;
- *cs++ = w->reg[i].value;
- }
- *cs++ = MI_NOOP;
+ count = min(remain, 15u);
+ remain -= count;
+
+ cs = intel_ring_begin(rq, 2 * count + 2);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ *cs++ = MI_LOAD_REGISTER_IMM(count);
+ for (i = 0; i < count; i++) {
+ *cs++ = reg->addr;
+ *cs++ = reg->value;
+ reg++;
+ }
+ *cs++ = MI_NOOP;
- intel_ring_advance(rq, cs);
+ intel_ring_advance(rq, cs);
+ } while (remain);
ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
if (ret)
--
2.17.1
___
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[Intel-gfx] [PATCH 2/2] drm/i915: Break workaround register emission into batches of 15
We are restricted to the number of registers we can rewrite into a
single command by the packet length. If we have more registers than can
be fitted into a single packet, we therefore need to split the writes
into multiple packets.
Reported-by: Kenneth Graunke
Signed-off-by: Chris Wilson
Cc: Oscar Mateo
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Cc: Kenneth Graunke
---
drivers/gpu/drm/i915/intel_workarounds.c | 31
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index f8bb32e974f6..d82e08af6a60 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -553,6 +553,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private
*dev_priv)
int intel_ctx_workarounds_emit(struct i915_request *rq)
{
struct i915_workarounds *w = &rq->i915->workarounds;
+ struct i915_wa_reg *reg = w->reg;
+ unsigned int remain;
u32 *cs;
int ret, i;
@@ -563,18 +565,27 @@ int intel_ctx_workarounds_emit(struct i915_request *rq)
if (ret)
return ret;
- cs = intel_ring_begin(rq, (w->count * 2 + 2));
- if (IS_ERR(cs))
- return PTR_ERR(cs);
+ remain = w->count;
+ do {
+ unsigned int count;
- *cs++ = MI_LOAD_REGISTER_IMM(w->count);
- for (i = 0; i < w->count; i++) {
- *cs++ = w->reg[i].addr;
- *cs++ = w->reg[i].value;
- }
- *cs++ = MI_NOOP;
+ count = min(remain, 15u);
+ remain -= count;
+
+ cs = intel_ring_begin(rq, 2 * count + 2);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ *cs++ = MI_LOAD_REGISTER_IMM(count);
+ for (i = 0; i < count; i++) {
+ *cs++ = reg->addr;
+ *cs++ = reg->value;
+ reg++;
+ }
+ *cs++ = MI_NOOP;
- intel_ring_advance(rq, cs);
+ intel_ring_advance(rq, cs);
+ } while (remain);
ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
if (ret)
--
2.17.1
___
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Re: [Intel-gfx] [PATCH 2/5] drm/i915/gtt: Read-only pages for insert_entries on bdw+
Quoting Chris Wilson (2018-06-14 22:24:01)
> From: Jon Bloomfield
>
> Hook up the flags to allow read-only ppGTT mappings for gen8+
>
> v2: Include a selftest to check that writes to a readonly PTE are
> dropped
>
> Signed-off-by: Jon Bloomfield
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matthew Auld
> Reviewed-by: Joonas Lahtinen #v1
> Reviewed-by: Matthew Auld #v1
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> @@ -23,6 +23,7 @@
> */
>
> #include "../i915_selftest.h"
> +#include "i915_random.h"
> #include "igt_flush_test.h"
>
> #include "mock_drm.h"
> @@ -266,6 +267,41 @@ static int cpu_check(struct drm_i915_gem_object *obj,
> unsigned int max)
> return err;
> }
>
> +static int ro_check(struct drm_i915_gem_object *obj, unsigned int max)
> +{
> + unsigned int n, m, needs_flush;
> + int err;
> +
> + err = i915_gem_obj_prepare_shmem_read(obj, &needs_flush);
> + if (err)
> + return err;
> +
> + for (n = 0; n < real_page_count(obj); n++) {
> + u32 *map;
> +
> + map = kmap_atomic(i915_gem_object_get_page(obj, n));
> + if (needs_flush & CLFLUSH_BEFORE)
> + drm_clflush_virt_range(map, PAGE_SIZE);
> +
> + for (m = 0; m < DW_PER_PAGE; m++) {
> + if (map[m] != 0xdeadbeef) {
One could have #define MAGIC 0xdeadbeef
> + pr_err("Invalid value (overwritten) at page
> %d, offset %d: found %08x expected %08x\n",
> + n, m, map[m], 0xdeadbeef);
> + err = -EINVAL;
> + goto out_unmap;
> + }
> + }
> +
> +out_unmap:
> + kunmap_atomic(map);
> + if (err)
> + break;
> + }
> +
> + i915_gem_obj_finish_shmem_access(obj);
> + return err;
> +}
> +static int igt_ctx_readonly(void *arg)
> +{
> + struct drm_i915_private *i915 = arg;
> + struct drm_i915_gem_object *obj = NULL;
> + struct drm_file *file;
> + I915_RND_STATE(prng);
> + IGT_TIMEOUT(end_time);
> + LIST_HEAD(objects);
> + struct i915_gem_context *ctx;
> + struct i915_hw_ppgtt *ppgtt;
> + unsigned long ndwords, dw;
> + int err = -ENODEV;
> +
> + /* Create a few different contexts (with different mm) and write
As noted by Matt.
Reviewed-by: Joonas Lahtinen
Regards, Joonas
___
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Re: [Intel-gfx] [PATCH 3/5] drm/i915: Prevent writing into a read-only object via a GGTT mmap
Quoting Chris Wilson (2018-06-14 22:24:02)
> If the user has created a read-only object, they should not be allowed
> to circumvent the write protection by using a GGTT mmapping. Deny it.
>
> Also most machines do not support read-only GGTT PTEs, so again we have
> to reject attempted writes. Fortunately, this is known a priori, so we
> can at least reject in the call to create the mmap (with a sanity check
> in the fault handler).
>
> v2: Check the vma->vm_flags during mmap() to allow readonly access.
>
> Signed-off-by: Chris Wilson
> Cc: Jon Bloomfield
> Cc: Joonas Lahtinen
> Cc: Matthew Auld
> Cc: David Herrmann
> Reviewed-by: Joonas Lahtinen #v1
> Reviewed-by: Matthew Auld #v1
> Reviewed-by: Jon Bloomfield
> +++ b/drivers/gpu/drm/drm_gem.c
> @@ -1036,6 +1036,11 @@ int drm_gem_mmap(struct file *filp, struct
> vm_area_struct *vma)
> return -EACCES;
> }
>
> + if (vma->vm_flags & VM_WRITE && node->readonly) {
> + drm_gem_object_put_unlocked(obj);
> + return -EINVAL;
> + }
> +
Pretty sure you want to split this patch and Cc: dri-devel. With that,
both are:
Reviewed-by: Joonas Lahtinen
Regards, Joonas
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Re: [Intel-gfx] [PATCH] drm/i915/psr: Adds psrwake options for all platforms
On Thu, 14 Jun 2018, Dhinakaran Pandiyan wrote:
> On Thu, 2018-06-14 at 16:56 +, Nagaraju, Vathsala wrote:
>> + Ashutosh(VBT team) + maulik
>>
>> 209 is confirmed version on kbl both by vbt team (Maulik) and google,
>> so we had used it.
>>
>> DK's suggestion is
>> if ((bdb->version >= 203 && IS_GEN9_BC(dev_priv)) ||
>> IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
>> /* new mapping */
>>
>> As per Ashutosh, 203 Is not the right version, 205 is fine , but user
>> can still provide decimal value for SKL.
>
> I am confused, why does the commit message mention 203 then?
Whatever the version, I want that to be required always. i.e.
if (version >= N && (bunch of other conditions))
*not*
if (version >= N || (bunch of other conditions))
BR,
Jani.
>
>
>> Jani/Rodrigo, should we use 205 for SKL or drop SKL from the new
>> mapping?
>>
>> -Original Message-
>> From: Pandiyan, Dhinakaran
>> Sent: Thursday, June 14, 2018 9:30 PM
>> To: Vivi, Rodrigo ; Nikula, Jani > @intel.com>; Nagaraju, Vathsala
>> Cc: put...@chromium.org; intel-gfx@lists.freedesktop.org
>> Subject: Re: [PATCH] drm/i915/psr: Adds psrwake options for all
>> platforms
>>
>> On Thu, 2018-06-14 at 11:59 +0530, Nagaraju, Vathsala wrote:
>> >
>> >
>> > On 6/13/2018 11:10 PM, Dhinakaran Pandiyan wrote:
>> > >
>> > >
>> > > On Wed, 2018-06-13 at 10:32 -0700, Dhinakaran Pandiyan wrote:
>> > > >
>> > > >
>> > > > On Wed, 2018-06-13 at 09:41 +0300, Jani Nikula wrote:
>> > > > >
>> > > > >
>> > > > > On Wed, 13 Jun 2018, "Nagaraju, Vathsala" > > > > > in
>> > > > > tel.
>> > > > > co
>> > > > > m> wrote:
>> > > > > >
>> > > > > >
>> > > > > >
>> > > > > > On 6/12/2018 2:30 PM, Jani Nikula wrote:
>> > > > > > >
>> > > > > > >
>> > > > > > >
>> > > > > > > On Tue, 12 Jun 2018, vathsala nagaraju > > > > > > > @i
>> > > > > > > ntel .c
>> > > > > > > om> wrote:
>> > > > > > > >
>> > > > > > > >
>> > > > > > > >
>> > > > > > > > From: Vathsala Nagaraju
>> > > > > > > >
>> > > > > > > > Adds new psrwake options defined in the below table.
>> > > > > > > > Platform PSR wake options vbt version
>> > > > > > > > KBL/CFL/WHLAll
>> > > > > > > > SKLAll PV releases (Check for 203+
>> > > > > > > > might
>> > > > > > > > help
>> > > > > > > > but cannot be foolproof)
>> > > > > > > > BXTUses old interpretation.
>> > > > > > > > CNL/ICL+ All
>> > > > > > > > GLKAll
>> > > > > > > >
>> > > > > > > > For SKL, we will continue to use older interpretation
>> > > > > > > > for
>> > > > > > > > the above reason.
>> > > > > > > >
>> > > > > > > > Cc: Jani Nikula
>> > > > > > > > Cc: Rodrigo Vivi
>> > > > > > > > Cc: Puthikorn Voravootivat
>> > > > > > > > Cc: Dhinakaran Pandiyan
>> > > > > > > >
>> > > > > > > > Signed-off-by: Vathsala Nagaraju > > > > > > > > el
>> > > > > > > > .com
>> > > > > > > > ---
>> > > > > > > > drivers/gpu/drm/i915/intel_bios.c | 3 ++-
>> > > > > > > > 1 file changed, 2 insertions(+), 1 deletion(-)
>> > > > > > > >
>> > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_bios.c
>> > > > > > > > b/drivers/gpu/drm/i915/intel_bios.c
>> > > > > > > > index 465dff4..010ff68 100644
>> > > > > > > > --- a/drivers/gpu/drm/i915/intel_bios.c
>> > > > > > > > +++ b/drivers/gpu/drm/i915/intel_bios.c
>> > > > > > > > @@ -710,7 +710,8 @@ static int
>> > > > > > > > intel_bios_ssc_frequency(struct drm_i915_private
>> > > > > > > > *dev_priv,
>> > > > > > > > * New psr options 0=500us, 1=100us,
>> > > > > > > > 2=2500us, 3=0us
>> > > > > > > > * Old decimal value is wake up time in
>> > > > > > > > multiples of
>> > > > > > > > 100 us.
>> > > > > > > > */
>> > > > > > > > - if (bdb->version >= 209 &&
>> > > > > > > > IS_GEN9_BC(dev_priv))
>> > > > > > > > {
>> > > > > > > > + if ((INTEL_GEN(dev_priv) >= 10) ||
>> > > > > > > > + (IS_GEN9_BC(dev_priv) &&
>> > > > > > > > !IS_SKYLAKE(dev_priv)))
>> > > > > > > > {
>> > > > > > > Please keep the version check.
>> > > > > > Sure. For SKL , shall we use older interpretation for all
>> > > > > > bdb
>> > > > > > version as vbt team cannot confirm bdb version for SKL?
>> > > > > I guess.
>> > > > >
>> > > > Why not change the version check to >= 203, if that's what PV
>> > > > releases
>> > > > had as per your commit message? With the current code, Linux
>> > > > and
>> > > > Windows set 500 us and 2.5 ms respectively on my laptop.
>> > > Said laptop is a SKL with bdb version 205.
>> > + ashutosh(VBT team)
>> > Since VBT team cannot confirm version for SKL ,so skipped for
>> > skylake.
>> > I did a copy paste of the table provided by vbt team, will edit for
>> > skylake.
>> >
>> We are not going to get this right for all combinations, the best we
>> can do is make sure things work in most cases. I prefer to err on the
>> side of using the new mapping because when translated incorrectly, 3
>> out of 4 values lead to >= intended training
[Intel-gfx] [PULL] drm-misc-next-fixes
drm-misc-next-fixes-2018-06-15: - Fix possible race conditions while unplugging DRM device. The following changes since commit fbecef131676c1d18e8e6b42c04e10dc49725e96: drm/v3d: add CONFIG_MMU dependency (2018-05-30 12:15:18 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-fixes-2018-06-15 for you to fetch changes up to 069035c5db3459b9b5f12caf3bffed9a863fa5c4: drm: Fix possible race conditions while unplugging DRM device (2018-05-31 10:36:28 +0300) Single fix for v4.18: - Fix possible race conditions while unplugging DRM device. Oleksandr Andrushchenko (1): drm: Fix possible race conditions while unplugging DRM device drivers/gpu/drm/drm_drv.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915/icl: implement DVFS for ICL
== Series Details == Series: series starting with [CI,1/2] drm/i915/icl: implement DVFS for ICL URL : https://patchwork.freedesktop.org/series/44784/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4322_full -> Patchwork_9314_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9314_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9314_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9314_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-render: shard-kbl: SKIP -> PASS igt@gem_mocs_settings@mocs-rc6-vebox: shard-kbl: PASS -> SKIP +2 == Known issues == Here are the changes found in Patchwork_9314_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_gtt: shard-glk: PASS -> INCOMPLETE (k.org#198133, fdo#103359) igt@drv_suspend@shrink: shard-snb: PASS -> FAIL (fdo#106886) shard-hsw: PASS -> INCOMPLETE (fdo#103540) igt@gem_exec_suspend@basic-s3: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@gem_ppgtt@blt-vs-render-ctx0: shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106023) igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#105189) igt@kms_flip@modeset-vs-vblank-race-interruptible: shard-hsw: PASS -> FAIL (fdo#103060) igt@kms_flip_tiling@flip-to-x-tiled: shard-glk: PASS -> FAIL (fdo#104724) igt@kms_flip_tiling@flip-to-y-tiled: shard-glk: PASS -> FAIL (fdo#104724, fdo#103822) igt@perf_pmu@other-init-2: shard-snb: PASS -> INCOMPLETE (fdo#105411) Possible fixes igt@drv_selftest@live_gtt: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@gem_exec_big: shard-hsw: INCOMPLETE (fdo#103540) -> PASS igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: shard-hsw: FAIL (fdo#100368) -> PASS igt@kms_flip_tiling@flip-y-tiled: shard-glk: FAIL (fdo#104724, fdo#103822) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS shard-hsw: FAIL (fdo#99912) -> PASS igt@testdisplay: shard-kbl: WARN (fdo#106354) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#106354 https://bugs.freedesktop.org/show_bug.cgi?id=106354 fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4322 -> Patchwork_9314 CI_DRM_4322: 485f975b0c64f2a3c9b0bf116a63adc3c6389b1f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4519: 3381a56be31defb3b5c23a4fbc19ac26a000c35b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9314: d5c29a8723e6c00c6509ab2d3a37fe522a37cb20 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9314/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Break workaround register emission into batches of 15
== Series Details == Series: drm/i915: Break workaround register emission into batches of 15 URL : https://patchwork.freedesktop.org/series/44808/ State : failure == Summary == Applying: drm/i915: Break workaround register emission into batches of 15 Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/intel_workarounds.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/intel_workarounds.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_workarounds.c error: Failed to merge in the changes. Patch failed at 0001 drm/i915: Break workaround register emission into batches of 15 Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Keep the ctx workarounds tightly packed
== Series Details == Series: drm/i915: Keep the ctx workarounds tightly packed URL : https://patchwork.freedesktop.org/series/44807/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4323 -> Patchwork_9316 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/44807/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_9316 that come from known issues: === IGT changes === Issues hit igt@debugfs_test@read_all_entries: fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713) igt@kms_flip@basic-flip-vs-wf_vblank: fi-cfl-s3: PASS -> FAIL (fdo#100368, fdo#103928) igt@prime_vgem@basic-fence-flip: fi-ilk-650: PASS -> FAIL (fdo#104008) fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 == Participating hosts (43 -> 38) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4323 -> Patchwork_9316 CI_DRM_4323: 25d3805133071406ffae77c994f464dbbb3bb34e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4519: 3381a56be31defb3b5c23a4fbc19ac26a000c35b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9316: fa1c64fa7e2045edc633d8b6babd4320be4b7341 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == fa1c64fa7e20 drm/i915: Keep the ctx workarounds tightly packed == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9316/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: Keep the ctx workarounds tightly packed
== Series Details == Series: series starting with [1/2] drm/i915: Keep the ctx workarounds tightly packed URL : https://patchwork.freedesktop.org/series/44809/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Keep the ctx workarounds tightly packed Okay! Commit: drm/i915: Break workaround register emission into batches of 15 - +drivers/gpu/drm/i915/intel_workarounds.c:572:25: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4] drm/i915/gtt: Read-only pages for insert_entries on bdw+
From: Jon Bloomfield
Hook up the flags to allow read-only ppGTT mappings for gen8+
v2: Include a selftest to check that writes to a readonly PTE are
dropped
v3: Don't duplicate cpu_check() as we can just reuse it, and even worse
don't wholesale copy the theory-of-operation comment from igt_ctx_exec
without changing it to explain the intention behind the new test!
v4: Joonas really likes magic mystery values
Signed-off-by: Jon Bloomfield
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matthew Auld
Reviewed-by: Joonas Lahtinen
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 45 ---
drivers/gpu/drm/i915/i915_gem_gtt.h | 7 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 11 +-
.../gpu/drm/i915/selftests/i915_gem_context.c | 112 +-
4 files changed, 153 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 705cf1c04bba..deddf15db24a 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -196,7 +196,7 @@ static int ppgtt_bind_vma(struct i915_vma *vma,
return err;
}
- /* Currently applicable only to VLV */
+ /* Applicable to VLV, and gen8+ */
pte_flags = 0;
if (vma->obj->gt_ro)
pte_flags |= PTE_READ_ONLY;
@@ -952,10 +952,11 @@ gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt,
struct i915_page_directory_pointer *pdp,
struct sgt_dma *iter,
struct gen8_insert_pte *idx,
- enum i915_cache_level cache_level)
+ enum i915_cache_level cache_level,
+ u32 flags)
{
struct i915_page_directory *pd;
- const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, 0);
+ const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
gen8_pte_t *vaddr;
bool ret;
@@ -1006,14 +1007,14 @@ gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt
*ppgtt,
static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm,
struct i915_vma *vma,
enum i915_cache_level cache_level,
- u32 unused)
+ u32 flags)
{
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
struct sgt_dma iter = sgt_dma(vma);
struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
gen8_ppgtt_insert_pte_entries(ppgtt, &ppgtt->pdp, &iter, &idx,
- cache_level);
+ cache_level, flags);
vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
}
@@ -1021,9 +1022,10 @@ static void gen8_ppgtt_insert_3lvl(struct
i915_address_space *vm,
static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma,
struct i915_page_directory_pointer
**pdps,
struct sgt_dma *iter,
- enum i915_cache_level cache_level)
+ enum i915_cache_level cache_level,
+ u32 flags)
{
- const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, 0);
+ const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
u64 start = vma->node.start;
dma_addr_t rem = iter->sg->length;
@@ -1139,19 +1141,21 @@ static void gen8_ppgtt_insert_huge_entries(struct
i915_vma *vma,
static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
struct i915_vma *vma,
enum i915_cache_level cache_level,
- u32 unused)
+ u32 flags)
{
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
struct sgt_dma iter = sgt_dma(vma);
struct i915_page_directory_pointer **pdps = ppgtt->pml4.pdps;
if (vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
- gen8_ppgtt_insert_huge_entries(vma, pdps, &iter, cache_level);
+ gen8_ppgtt_insert_huge_entries(vma, pdps, &iter, cache_level,
+ flags);
} else {
struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++],
-&iter, &idx, cache_level))
+&iter, &idx, cache_level,
+flags))
GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
@@ -1564,6 +1568,9 @@ static struct i915_
Re: [Intel-gfx] [PATCH 3/5] drm/i915: Prevent writing into a read-only object via a GGTT mmap
Quoting Joonas Lahtinen (2018-06-15 09:08:54)
> Quoting Chris Wilson (2018-06-14 22:24:02)
> > If the user has created a read-only object, they should not be allowed
> > to circumvent the write protection by using a GGTT mmapping. Deny it.
> >
> > Also most machines do not support read-only GGTT PTEs, so again we have
> > to reject attempted writes. Fortunately, this is known a priori, so we
> > can at least reject in the call to create the mmap (with a sanity check
> > in the fault handler).
> >
> > v2: Check the vma->vm_flags during mmap() to allow readonly access.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Jon Bloomfield
> > Cc: Joonas Lahtinen
> > Cc: Matthew Auld
> > Cc: David Herrmann
> > Reviewed-by: Joonas Lahtinen #v1
> > Reviewed-by: Matthew Auld #v1
> > Reviewed-by: Jon Bloomfield
>
>
>
> > +++ b/drivers/gpu/drm/drm_gem.c
> > @@ -1036,6 +1036,11 @@ int drm_gem_mmap(struct file *filp, struct
> > vm_area_struct *vma)
> > return -EACCES;
> > }
> >
> > + if (vma->vm_flags & VM_WRITE && node->readonly) {
> > + drm_gem_object_put_unlocked(obj);
> > + return -EINVAL;
> > + }
> > +
>
> Pretty sure you want to split this patch and Cc: dri-devel. With that,
> both are:
I thought I cc'ed dri-devel on the previous sending. (At least I thought
about it.) Besides until ttm differentiates between read/write access,
it's a moot point.
-Chris
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915/gtt: Add read only pages to gen8_pte_encode (rev2)
== Series Details == Series: series starting with [1/5] drm/i915/gtt: Add read only pages to gen8_pte_encode (rev2) URL : https://patchwork.freedesktop.org/series/44776/ State : failure == Summary == Applying: drm/i915/gtt: Add read only pages to gen8_pte_encode Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_gem_gtt.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_gem_gtt.c Applying: drm/i915/gtt: Read-only pages for insert_entries on bdw+ Applying: drm/i915: Prevent writing into a read-only object via a GGTT mmap Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_gem_gtt.c M drivers/gpu/drm/i915/selftests/i915_gem_context.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/selftests/i915_gem_context.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/selftests/i915_gem_context.c Auto-merging drivers/gpu/drm/i915/i915_gem_gtt.c error: Failed to merge in the changes. Patch failed at 0003 drm/i915: Prevent writing into a read-only object via a GGTT mmap Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Keep the ctx workarounds tightly packed
== Series Details == Series: series starting with [1/2] drm/i915: Keep the ctx workarounds tightly packed URL : https://patchwork.freedesktop.org/series/44809/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4323 -> Patchwork_9318 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/44809/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_9318 that come from known issues: === IGT changes === Issues hit igt@gem_exec_gttfill@basic: fi-byt-n2820: PASS -> FAIL (fdo#106744) igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000, fdo#106097) igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106238) igt@vgem_basic@second-client: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106745) Possible fixes igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: FAIL (fdo#100368) -> PASS igt@kms_flip@basic-plain-flip: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#106238 https://bugs.freedesktop.org/show_bug.cgi?id=106238 fdo#106744 https://bugs.freedesktop.org/show_bug.cgi?id=106744 fdo#106745 https://bugs.freedesktop.org/show_bug.cgi?id=106745 == Participating hosts (43 -> 38) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4323 -> Patchwork_9318 CI_DRM_4323: 25d3805133071406ffae77c994f464dbbb3bb34e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4519: 3381a56be31defb3b5c23a4fbc19ac26a000c35b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9318: 5917a776ca11e12245c16146f7f54012f91c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5917a776ca11 drm/i915: Break workaround register emission into batches of 15 1735e8c05885 drm/i915: Keep the ctx workarounds tightly packed == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9318/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915: Enable provoking vertex fix on Gen9+ systems.
From: Kenneth Graunke
The SF and clipper units mishandle the provoking vertex in some cases,
which can cause misrendering with shaders that use flat shaded inputs.
There are chicken bits in 3D_CHICKEN3 (for SF) and FF_SLICE_CHICKEN
(for the clipper) that work around the issue. These registers are
unfortunately not part of the logical context (even the power context).
This patch sets both bits, and bumps the number of allowed workaround
registers to avoid running out of space (thanks to Chris Wilson for
helping debug that issue).
I am not aware of any workaround names or numbers assigned for these
issues, they're simply recommended in the documentation for each of
the registers.
Bugzilla: https://bugs.freedesktop.org/103047
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 140f6a27d696..35d8c2be85be 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2432,12 +2432,17 @@ enum i915_power_well_id {
#define _3D_CHICKEN_MMIO(0x2084)
#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
#define _3D_CHICKEN2 _MMIO(0x208c)
+
+#define FF_SLICE_CHICKEN _MMIO(0x2088)
+#define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1)
+
/* Disables pipelining of read flushes past the SF-WIZ interface.
* Required on all Ironlake steppings according to the B-Spec, but the
* particular danger of not doing so is not specified.
*/
# define _3D_CHICKEN2_WM_READ_PIPELINED(1 << 14)
#define _3D_CHICKEN3 _MMIO(0x2090)
+#define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12)
#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL(1 << 10)
#define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5)
#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index d82e08af6a60..ca74b4b3f206 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -303,6 +303,12 @@ static int gen9_ctx_workarounds_init(struct
drm_i915_private *dev_priv)
if (IS_GEN9_LP(dev_priv))
WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
+ /* BSpec: 11391 */
+ WA_SET_BIT_MASKED(FF_SLICE_CHICKEN,
+ FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX);
+ /* BSpec: 11299 */
+ WA_SET_BIT_MASKED(_3D_CHICKEN3, _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX);
+
return 0;
}
--
2.17.1
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[Intel-gfx] [PATCH 1/3] drm/i915: Keep the ctx workarounds tightly packed
For each platform, we have a few registers that rewritten with multiple
values -- they are not part of a sequence, just different parts of a
masked register set at different times (e.g. platform and gen
workarounds). Consolidate these into a single register write to keep the
table compact.
While adjusting the construction of the wa table, make it non fatal so
that the driver still loads but keeping the warning and extra details
for inspection.
Signed-off-by: Chris Wilson
Cc: Oscar Mateo
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c | 25 ++
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_workarounds.c | 63 +---
3 files changed, 52 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index c600279d3db5..f78895ffab9b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3378,28 +3378,13 @@ static int i915_shared_dplls_info(struct seq_file *m,
void *unused)
static int i915_wa_registers(struct seq_file *m, void *unused)
{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct i915_workarounds *workarounds = &dev_priv->workarounds;
+ struct i915_workarounds *wa = &node_to_i915(m->private)->workarounds;
int i;
- intel_runtime_pm_get(dev_priv);
-
- seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
- for (i = 0; i < workarounds->count; ++i) {
- i915_reg_t addr;
- u32 mask, value, read;
- bool ok;
-
- addr = workarounds->reg[i].addr;
- mask = workarounds->reg[i].mask;
- value = workarounds->reg[i].value;
- read = I915_READ(addr);
- ok = (value & mask) == (read & mask);
- seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x,
status: %s\n",
- i915_mmio_reg_offset(addr), value, mask, read, ok ?
"OK" : "FAIL");
- }
-
- intel_runtime_pm_put(dev_priv);
+ seq_printf(m, "Workarounds applied: %d\n", wa->count);
+ for (i = 0; i < wa->count; ++i)
+ seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
+ wa->reg[i].addr, wa->reg[i].value, wa->reg[i].mask);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2c12de678e32..91c389622217 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1308,7 +1308,7 @@ struct i915_frontbuffer_tracking {
};
struct i915_wa_reg {
- i915_reg_t addr;
+ u32 addr;
u32 value;
/* bitmask representing WA bits */
u32 mask;
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 24b929ce3341..f8bb32e974f6 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -48,29 +48,58 @@
* - Public functions to init or apply the given workaround type.
*/
-static int wa_add(struct drm_i915_private *dev_priv,
- i915_reg_t addr,
- const u32 mask, const u32 val)
+static void wa_add(struct drm_i915_private *i915,
+ i915_reg_t reg, const u32 mask, const u32 val)
{
- const unsigned int idx = dev_priv->workarounds.count;
+ struct i915_workarounds *wa = &i915->workarounds;
+ unsigned int start = 0, end = wa->count;
+ unsigned int addr = i915_mmio_reg_offset(reg);
+ struct i915_wa_reg *r;
+
+ while (start < end) {
+ unsigned int mid = start + (end - start) / 2;
+
+ if (wa->reg[mid].addr < addr) {
+ start = mid + 1;
+ } else if (wa->reg[mid].addr > addr) {
+ end = mid;
+ } else {
+ r = &wa->reg[mid];
+
+ if ((mask & ~r->mask) == 0) {
+ DRM_ERROR("Discarding overwritten w/a for reg
%04x (mask: %08x, value: %08x)\n",
+ addr, r->mask, r->value);
+
+ r->value &= ~mask;
+ }
+
+ r->value |= val;
+ r->mask |= mask;
+ return;
+ }
+ }
- if (WARN_ON(idx >= I915_MAX_WA_REGS))
- return -ENOSPC;
+ if (WARN_ON_ONCE(wa->count >= I915_MAX_WA_REGS)) {
+ DRM_ERROR("Dropping w/a for reg %04x (mask: %08x, value:
%08x)\n",
+ addr, mask, val);
+ return;
+ }
- dev_priv->workarounds.reg[idx].addr = addr;
- dev_priv->workarounds.reg[idx].value = val;
- dev_priv->workarounds.reg[idx].mask = mask;
+ r = &wa->reg[wa->count++];
+ r->addr = addr;
+ r->value = val;
+ r->mas
[Intel-gfx] [PATCH 2/3] drm/i915: Break workaround register emission into batches of 15
We are restricted to the number of registers we can write with a
single command by the packet length. If we have more registers than can
be fitted into a single packet, we therefore need to split the writes
into multiple packets.
Reported-by: Kenneth Graunke
Signed-off-by: Chris Wilson
Cc: Oscar Mateo
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Cc: Kenneth Graunke
---
drivers/gpu/drm/i915/intel_workarounds.c | 31
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index f8bb32e974f6..d82e08af6a60 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -553,6 +553,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private
*dev_priv)
int intel_ctx_workarounds_emit(struct i915_request *rq)
{
struct i915_workarounds *w = &rq->i915->workarounds;
+ struct i915_wa_reg *reg = w->reg;
+ unsigned int remain;
u32 *cs;
int ret, i;
@@ -563,18 +565,27 @@ int intel_ctx_workarounds_emit(struct i915_request *rq)
if (ret)
return ret;
- cs = intel_ring_begin(rq, (w->count * 2 + 2));
- if (IS_ERR(cs))
- return PTR_ERR(cs);
+ remain = w->count;
+ do {
+ unsigned int count;
- *cs++ = MI_LOAD_REGISTER_IMM(w->count);
- for (i = 0; i < w->count; i++) {
- *cs++ = w->reg[i].addr;
- *cs++ = w->reg[i].value;
- }
- *cs++ = MI_NOOP;
+ count = min(remain, 15u);
+ remain -= count;
+
+ cs = intel_ring_begin(rq, 2 * count + 2);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ *cs++ = MI_LOAD_REGISTER_IMM(count);
+ for (i = 0; i < count; i++) {
+ *cs++ = reg->addr;
+ *cs++ = reg->value;
+ reg++;
+ }
+ *cs++ = MI_NOOP;
- intel_ring_advance(rq, cs);
+ intel_ring_advance(rq, cs);
+ } while (remain);
ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
if (ret)
--
2.17.1
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/2] drm/i915/whl: Introducing Whiskey Lake platform
== Series Details == Series: series starting with [v2,1/2] drm/i915/whl: Introducing Whiskey Lake platform URL : https://patchwork.freedesktop.org/series/44787/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4322_full -> Patchwork_9315_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9315_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9315_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9315_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-vebox: shard-kbl: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_9315_full that come from known issues: === IGT changes === Issues hit igt@drv_hangman@error-state-capture-render: shard-snb: PASS -> FAIL (fdo#106847) igt@gem_exec_suspend@basic-s3: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@gem_ppgtt@blt-vs-render-ctx0: shard-kbl: PASS -> INCOMPLETE (fdo#103665, fdo#106023) igt@kms_flip_tiling@flip-x-tiled: shard-glk: PASS -> FAIL (fdo#103822, fdo#104724) +1 Possible fixes igt@drv_selftest@live_gtt: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@gem_exec_big: shard-hsw: INCOMPLETE (fdo#103540) -> PASS igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: shard-hsw: FAIL (fdo#100368) -> PASS shard-glk: FAIL (fdo#100368) -> PASS +1 igt@kms_flip@plain-flip-ts-check: shard-hsw: FAIL (fdo#103928) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS igt@prime_busy@wait-after-bsd: shard-snb: INCOMPLETE (fdo#105411) -> SKIP igt@testdisplay: shard-kbl: WARN (fdo#106354) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#106354 https://bugs.freedesktop.org/show_bug.cgi?id=106354 fdo#106847 https://bugs.freedesktop.org/show_bug.cgi?id=106847 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4322 -> Patchwork_9315 CI_DRM_4322: 485f975b0c64f2a3c9b0bf116a63adc3c6389b1f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4519: 3381a56be31defb3b5c23a4fbc19ac26a000c35b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9315: 06a369a6e01a43eb549615bf08acd2651756b06d @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9315/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/7] drm/i915: move towards kernel types
On Thu, 14 Jun 2018, Rodrigo Vivi wrote: > On Wed, Jun 13, 2018 at 09:55:38AM +0300, Jani Nikula wrote: >> On Tue, 12 Jun 2018, Lucas De Marchi wrote: >> > On Tue, Jun 12, 2018 at 3:15 AM Jani Nikula wrote: >> >> >> >> On Tue, 12 Jun 2018, Tvrtko Ursulin >> >> wrote: >> >> > On 12/06/2018 10:19, Jani Nikula wrote: >> >> >> Semi-RFC. Do we want to do this? Here's a batch of conversions that >> >> >> shouldn't >> >> >> conflict much with in-flight patches. >> >> >> >> >> >> The trouble with mixed use is that it's inconsistent, and any >> >> >> remaining C99 >> >> >> types will encourage their use. We could at least do the low hanging >> >> >> fruit? >> >> > >> >> > Ack from me. Doesn't seem so big to cause much pain. >> >> > >> >> > When you say low-hanging fruit, that implies you only dealt with a >> >> > particular class of occurrences? >> >> >> >> I meant the files which don't have massive amounts of C99 types and >> >> aren't under active development right now. I just wanted to avoid >> >> trouble for starters. ;) >> > >> > If using kernel types is where we want to go (which I agree with), >> > maybe it would be better to have a single conversion rather than >> > several small ones as we are doing with dev_priv -> i915? This allows >> > in-flight-but-not-yet-sent patches to easily keep up with the changes >> > rather than conflicting every other rebase. >> >> I'm thinking we can do a lot of changes without conflicting anything or >> very little. At least for starters before the sudden ripping off the >> band-aid. > > I'm with Lucas. I'd prefer one single massive move than many small ones. > Easier for the internal maintenance. We fix it only once and not one per > day for months and months like dev_priv/i915 case. For everything else, I believe smaller patches are easier. For example, who is going to review the massive change? Halt everything until it's reviewed and merged? For merge conflicts I think git can do a better job of managing the rerere with piecemeal changes. Internal is not the only consideration. BR, Jani. > >> >> BR, >> Jani. >> >> > >> > Lucas De Marchi >> > >> >> >> >> > Also going forward we have to make sure we will be able to stop them >> >> > creeping back in. Is checkpatch perhaps covering this? Or we could put >> >> > something in dim? >> >> >> >> We can stop ignoring PREFER_KERNEL_TYPES in checkpatch (the ignores are >> >> in dim). We don't even have to change everything for that, we just need >> >> to change enough to make the S/N better. People tend to use the types >> >> near the places they change. >> >> >> >> BR, >> >> Jani. >> >> >> >> >> >> > >> >> > Regards, >> >> > >> >> > Tvrtko >> >> > >> >> >> $ git grep "uint\(8\|16\|32\|64\)_t" -- drivers/gpu/drm/i915/ | sed >> >> >> 's/:.*//' | sort | uniq -c | sort -n >> >> >> >> >> >> BR, >> >> >> Jani. >> >> >> >> >> >> >> >> >> Jani Nikula (7): >> >> >>drm/i915/vbt: switch to kernel unsigned int types >> >> >>drm/i915/hdmi: switch to kernel unsigned int types >> >> >>drm/i915/uncore: switch to kernel unsigned int types >> >> >>drm/i915/dvo: switch to kernel unsigned int types >> >> >>drm/i915/backlight: switch to kernel unsigned int types >> >> >>drm/i915/audio: switch to kernel unsigned int types >> >> >>drm/i915/lspcon: switch to kernel unsigned int types >> >> >> >> >> >> drivers/gpu/drm/i915/dvo_ch7017.c | 20 ++-- >> >> >> drivers/gpu/drm/i915/dvo_ch7xxx.c | 22 +++--- >> >> >> drivers/gpu/drm/i915/dvo_ivch.c | 26 >> >> >> drivers/gpu/drm/i915/dvo_ns2501.c | 44 >> >> >> +-- >> >> >> drivers/gpu/drm/i915/dvo_sil164.c | 10 +++--- >> >> >> drivers/gpu/drm/i915/dvo_tfp410.c | 16 +- >> >> >> drivers/gpu/drm/i915/intel_audio.c| 36 >> >> >> +++--- >> >> >> drivers/gpu/drm/i915/intel_bios.c | 4 +-- >> >> >> drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 12 >> >> >> drivers/gpu/drm/i915/intel_dvo.c | 2 +- >> >> >> drivers/gpu/drm/i915/intel_hdmi.c | 14 - >> >> >> drivers/gpu/drm/i915/intel_lspcon.c | 2 +- >> >> >> drivers/gpu/drm/i915/intel_panel.c| 8 ++--- >> >> >> drivers/gpu/drm/i915/intel_uncore.h | 22 +++--- >> >> >> drivers/gpu/drm/i915/intel_vbt_defs.h | 2 +- >> >> >> 15 files changed, 120 insertions(+), 120 deletions(-) >> >> >> >> >> >> >> -- >> >> Jani Nikula, Intel Open Source Graphics Center >> >> ___ >> >> Intel-gfx mailing list >> >> Intel-gfx@lists.freedesktop.org >> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx >> >> -- >> Jani Nikula, Intel Open Source Graphics Center >> ___ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mai
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Keep the ctx workarounds tightly packed
== Series Details == Series: series starting with [1/3] drm/i915: Keep the ctx workarounds tightly packed URL : https://patchwork.freedesktop.org/series/44811/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7aec116d9abf drm/i915: Keep the ctx workarounds tightly packed 6deece3deb40 drm/i915: Break workaround register emission into batches of 15 ae25fb82a171 drm/i915: Enable provoking vertex fix on Gen9+ systems. -:61: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s) total: 1 errors, 0 warnings, 0 checks, 29 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915: Keep the ctx workarounds tightly packed
== Series Details == Series: series starting with [1/3] drm/i915: Keep the ctx workarounds tightly packed URL : https://patchwork.freedesktop.org/series/44811/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Keep the ctx workarounds tightly packed Okay! Commit: drm/i915: Break workaround register emission into batches of 15 - +drivers/gpu/drm/i915/intel_workarounds.c:572:25: warning: expression using sizeof(void) Commit: drm/i915: Enable provoking vertex fix on Gen9+ systems. Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915: Be irqsafe inside reset
As we want to be able to call i915_reset_engine and co from a softirq or
timer context, we need to be irqsafe at all times. So we have to forgo
the simple spin_lock_irq for the full spin_lock_irqsave.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8dd4d35655af..7fe951ad2a8b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3144,15 +3144,17 @@ i915_gem_reset_request(struct intel_engine_cs *engine,
*/
request = i915_gem_find_active_request(engine);
if (request) {
+ unsigned long flags;
+
i915_gem_context_mark_innocent(request->gem_context);
dma_fence_set_error(&request->fence, -EAGAIN);
/* Rewind the engine to replay the incomplete rq */
- spin_lock_irq(&engine->timeline.lock);
+ spin_lock_irqsave(&engine->timeline.lock, flags);
request = list_prev_entry(request, link);
if (&request->link == &engine->timeline.requests)
request = NULL;
- spin_unlock_irq(&engine->timeline.lock);
+ spin_unlock_irqrestore(&engine->timeline.lock, flags);
}
}
--
2.17.1
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[Intel-gfx] [CI 2/2] drm/i915/execlists: Reset the CSB head tracking on reset/sanitization
We can avoid the mmio read of the CSB pointers after reset based on the
knowledge that the HW always start writing at entry 0 in the CSB buffer.
We need to reset our CSB head tracking after GPU reset (and on
sanitization after resume) so that we are expecting to read from entry
0, hence we reset our head tracking back to the entry before (the last
entry in the ring).
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 839cb1fc6a01..340c82efed4a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -970,22 +970,19 @@ static void process_csb(struct intel_engine_cs *engine)
&engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
unsigned int head, tail;
- if (unlikely(execlists->csb_use_mmio)) {
- buf = (u32 * __force)
- (i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
- execlists->csb_head = -1; /* force mmio read of CSB */
- }
-
/* Clear before reading to catch new interrupts */
clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
smp_mb__after_atomic();
- if (unlikely(execlists->csb_head == -1)) { /* after a reset */
+ if (unlikely(execlists->csb_use_mmio)) {
if (!fw) {
intel_uncore_forcewake_get(i915,
execlists->fw_domains);
fw = true;
}
+ buf = (u32 * __force)
+ (i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
+
head = readl(i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
tail = GEN8_CSB_WRITE_PTR(head);
head = GEN8_CSB_READ_PTR(head);
@@ -1960,7 +1957,7 @@ static void execlists_reset(struct intel_engine_cs
*engine,
spin_unlock(&engine->timeline.lock);
/* Following the reset, we need to reload the CSB read/write pointers */
- engine->execlists.csb_head = -1;
+ engine->execlists.csb_head = GEN8_CSB_ENTRIES - 1;
local_irq_restore(flags);
@@ -2468,7 +2465,7 @@ static int logical_ring_init(struct intel_engine_cs
*engine)
upper_32_bits(ce->lrc_desc);
}
- engine->execlists.csb_head = -1;
+ engine->execlists.csb_head = GEN8_CSB_ENTRIES - 1;
return 0;
--
2.17.1
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[Intel-gfx] [CI 1/2] drm/i915: Be irqsafe inside reset
As we want to be able to call i915_reset_engine and co from a softirq or
timer context, we need to be irqsafe at all times. So we have to forgo
the simple spin_lock_irq for the full spin_lock_irqsave.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8dd4d35655af..7fe951ad2a8b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3144,15 +3144,17 @@ i915_gem_reset_request(struct intel_engine_cs *engine,
*/
request = i915_gem_find_active_request(engine);
if (request) {
+ unsigned long flags;
+
i915_gem_context_mark_innocent(request->gem_context);
dma_fence_set_error(&request->fence, -EAGAIN);
/* Rewind the engine to replay the incomplete rq */
- spin_lock_irq(&engine->timeline.lock);
+ spin_lock_irqsave(&engine->timeline.lock, flags);
request = list_prev_entry(request, link);
if (&request->link == &engine->timeline.requests)
request = NULL;
- spin_unlock_irq(&engine->timeline.lock);
+ spin_unlock_irqrestore(&engine->timeline.lock, flags);
}
}
--
2.17.1
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Keep the ctx workarounds tightly packed
== Series Details ==
Series: series starting with [1/3] drm/i915: Keep the ctx workarounds tightly
packed
URL : https://patchwork.freedesktop.org/series/44811/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4323 -> Patchwork_9320 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_9320 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9320, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/44811/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9320:
=== IGT changes ===
Possible regressions
igt@gem_workarounds@basic-read:
fi-skl-6260u: PASS -> FAIL
fi-cfl-s3: PASS -> FAIL
fi-skl-6700k2: PASS -> FAIL
fi-skl-6770hq: PASS -> FAIL
fi-kbl-7560u: PASS -> FAIL
fi-skl-6600u: PASS -> FAIL
fi-kbl-guc: PASS -> FAIL
fi-kbl-7500u: PASS -> FAIL
fi-skl-6700hq: PASS -> FAIL
fi-bxt-j4205: PASS -> FAIL
fi-skl-gvtdvm: PASS -> FAIL
fi-cfl-guc: PASS -> FAIL
{fi-whl-u}: PASS -> FAIL
fi-cfl-8700k: PASS -> FAIL
fi-glk-j4005: PASS -> FAIL
fi-skl-guc: PASS -> FAIL
fi-kbl-7567u: PASS -> FAIL
fi-kbl-r: PASS -> FAIL
Warnings
igt@gem_exec_gttfill@basic:
fi-pnv-d510:PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_9320 that come from known issues:
=== IGT changes ===
Issues hit
igt@gem_ctx_create@basic-files:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719)
igt@kms_flip@basic-flip-vs-modeset:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000, fdo#106097)
Possible fixes
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-glk-j4005: FAIL (fdo#100368) -> PASS
igt@kms_flip@basic-plain-flip:
fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719
fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000
fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097
== Participating hosts (43 -> 37) ==
Missing(6): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_4323 -> Patchwork_9320
CI_DRM_4323: 25d3805133071406ffae77c994f464dbbb3bb34e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4519: 3381a56be31defb3b5c23a4fbc19ac26a000c35b @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9320: ae25fb82a17111ccb9dc2edf3b72ab92074d5270 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ae25fb82a171 drm/i915: Enable provoking vertex fix on Gen9+ systems.
6deece3deb40 drm/i915: Break workaround register emission into batches of 15
7aec116d9abf drm/i915: Keep the ctx workarounds tightly packed
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9320/issues.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Be irqsafe inside reset
== Series Details == Series: drm/i915: Be irqsafe inside reset URL : https://patchwork.freedesktop.org/series/44814/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4323 -> Patchwork_9321 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/44814/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_9321 that come from known issues: === IGT changes === Issues hit igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) +1 igt@kms_flip@basic-flip-vs-wf_vblank: fi-cnl-psr: PASS -> FAIL (fdo#103928, fdo#100368) igt@kms_flip@basic-plain-flip: fi-cnl-y3: NOTRUN -> DMESG-WARN (fdo#104951) igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: PASS -> DMESG-FAIL (fdo#106103, fdo#102614) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927) Possible fixes igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: FAIL (fdo#100368) -> PASS igt@kms_flip@basic-plain-flip: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928 fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103 == Participating hosts (43 -> 39) == Additional (1): fi-cnl-y3 Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4323 -> Patchwork_9321 CI_DRM_4323: 25d3805133071406ffae77c994f464dbbb3bb34e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4519: 3381a56be31defb3b5c23a4fbc19ac26a000c35b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9321: bd825aa461c85924212bd5614820e3b25903463b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == bd825aa461c8 drm/i915: Be irqsafe inside reset == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9321/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915: Be irqsafe inside reset
== Series Details == Series: series starting with [CI,1/2] drm/i915: Be irqsafe inside reset URL : https://patchwork.freedesktop.org/series/44815/ State : warning == Summary == $ dim checkpatch origin/drm-tip 88cc0c1c5c51 drm/i915: Be irqsafe inside reset 73a559896046 drm/i915/execlists: Reset the CSB head tracking on reset/sanitization -:43: WARNING:LONG_LINE: line over 100 characters #43: FILE: drivers/gpu/drm/i915/intel_lrc.c:984: + (i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0))); total: 0 errors, 1 warnings, 0 checks, 42 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915: Be irqsafe inside reset
== Series Details == Series: series starting with [CI,1/2] drm/i915: Be irqsafe inside reset URL : https://patchwork.freedesktop.org/series/44815/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4323 -> Patchwork_9322 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/44815/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_9322 that come from known issues: === IGT changes === Issues hit igt@kms_frontbuffer_tracking@basic: fi-hsw-peppy: PASS -> DMESG-FAIL (fdo#106103, fdo#102614) igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b: fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719) igt@prime_vgem@basic-fence-flip: fi-ilk-650: PASS -> FAIL (fdo#104008) Possible fixes igt@kms_flip@basic-plain-flip: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103 == Participating hosts (43 -> 38) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4323 -> Patchwork_9322 CI_DRM_4323: 25d3805133071406ffae77c994f464dbbb3bb34e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4519: 3381a56be31defb3b5c23a4fbc19ac26a000c35b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9322: 73a55989604679b9f39075543079091a4751fec6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 73a559896046 drm/i915/execlists: Reset the CSB head tracking on reset/sanitization 88cc0c1c5c51 drm/i915: Be irqsafe inside reset == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9322/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Fix context ban and hang accounting for client
If client is smart or lucky enough to create a new context
after each hang, our context banning mechanism will never
catch up, and as a result of that it will be saved from
client banning. This can result in a never ending streak of
gpu hangs caused by bad or malicious client, preventing
access from other legit gpu clients.
Fix this by always incrementing per client ban score if
it hangs in short successions regardless of context ban
scoring. The exception are non bannable contexts. They remain
detached from client ban scoring mechanism.
v2: xchg timestamp, tidyup (Chris)
Fixes: b083a0870c79 ("drm/i915: Add per client max context ban limit")
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h | 20 ++---
drivers/gpu/drm/i915/i915_gem.c | 57 +
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
3 files changed, 54 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 74dd88d8563e..93aa8e7dfaba 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -352,14 +352,20 @@ struct drm_i915_file_private {
unsigned int bsd_engine;
-/* Client can have a maximum of 3 contexts banned before
- * it is denied of creating new contexts. As one context
- * ban needs 4 consecutive hangs, and more if there is
- * progress in between, this is a last resort stop gap measure
- * to limit the badly behaving clients access to gpu.
+/* Every context ban increments per client ban score. Also
+ * hangs in short succession increments ban score. If client suffers 3
+ * context bans, 9 hangs in quick succession or combination of those,
+ * it is banned and submitting more work will fail. This is a stop gap
+ * measure to limit the badly behaving clients access to gpu.
+ * Note that unbannable contexts never increment the client ban score.
*/
-#define I915_MAX_CLIENT_CONTEXT_BANS 3
- atomic_t context_bans;
+#define I915_CLIENT_SCORE_HANG_FAST1
+#define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
+#define I915_CLIENT_SCORE_CONTEXT_BAN 3
+#define I915_CLIENT_SCORE_BANNED 9
+ /** ban_score: Accumulated score of all ctx bans and fast hangs. */
+ atomic_t ban_score;
+ unsigned long hang_timestamp;
};
/* Interface history:
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8dd4d35655af..f06fe1c636e5 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2941,32 +2941,54 @@ i915_gem_object_pwrite_gtt(struct drm_i915_gem_object
*obj,
return 0;
}
+static void i915_gem_client_mark_guilty(struct drm_i915_file_private
*file_priv,
+ const struct i915_gem_context *ctx)
+{
+ unsigned int score;
+ unsigned long prev_hang;
+
+ if (i915_gem_context_is_banned(ctx))
+ score = I915_CLIENT_SCORE_CONTEXT_BAN;
+ else
+ score = 0;
+
+ prev_hang = xchg(&file_priv->hang_timestamp, jiffies);
+ if (time_before(jiffies, prev_hang + I915_CLIENT_FAST_HANG_JIFFIES))
+ score += I915_CLIENT_SCORE_HANG_FAST;
+
+ if (score) {
+ atomic_add(score, &file_priv->ban_score);
+
+ DRM_DEBUG_DRIVER("client %s: gained %u ban score, now %u\n",
+ctx->name, score,
+atomic_read(&file_priv->ban_score));
+ }
+}
+
static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx)
{
- bool banned;
+ unsigned int score;
+ bool banned, bannable;
atomic_inc(&ctx->guilty_count);
- banned = false;
- if (i915_gem_context_is_bannable(ctx)) {
- unsigned int score;
+ bannable = i915_gem_context_is_bannable(ctx);
+ score = atomic_add_return(CONTEXT_SCORE_GUILTY, &ctx->ban_score);
+ banned = score >= CONTEXT_SCORE_BAN_THRESHOLD;
- score = atomic_add_return(CONTEXT_SCORE_GUILTY,
- &ctx->ban_score);
- banned = score >= CONTEXT_SCORE_BAN_THRESHOLD;
+ DRM_DEBUG_DRIVER("context %s: guilty %d, score %u, ban %s:%s\n",
+ctx->name, atomic_read(&ctx->guilty_count),
+score, yesno(bannable), yesno(banned));
- DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned?
%s\n",
-ctx->name, score, yesno(banned));
- }
- if (!banned)
+ /* Cool contexts don't accumulate client ban score */
+ if (!bannable)
return;
- i915_gem_context_set_banned(ctx);
- if (!IS_ERR_OR_NULL(ctx->file_priv)) {
- atomic_inc(&ctx->file_priv->context_bans);
- DRM_DEBUG_DRIVER("client %s has had %d context banned\n",
-ctx->name,
atomic_read(&ctx->file_priv->context_bans)
Re: [Intel-gfx] [PATCH] drm/i915: Fix context ban and hang accounting for client
Quoting Mika Kuoppala (2018-06-15 11:18:28)
> If client is smart or lucky enough to create a new context
> after each hang, our context banning mechanism will never
> catch up, and as a result of that it will be saved from
> client banning. This can result in a never ending streak of
> gpu hangs caused by bad or malicious client, preventing
> access from other legit gpu clients.
>
> Fix this by always incrementing per client ban score if
> it hangs in short successions regardless of context ban
> scoring. The exception are non bannable contexts. They remain
> detached from client ban scoring mechanism.
>
> v2: xchg timestamp, tidyup (Chris)
>
> Fixes: b083a0870c79 ("drm/i915: Add per client max context ban limit")
> Cc: Chris Wilson
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_drv.h | 20 ++---
> drivers/gpu/drm/i915/i915_gem.c | 57 +
> drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
> 3 files changed, 54 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 74dd88d8563e..93aa8e7dfaba 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -352,14 +352,20 @@ struct drm_i915_file_private {
>
> unsigned int bsd_engine;
>
> -/* Client can have a maximum of 3 contexts banned before
> - * it is denied of creating new contexts. As one context
> - * ban needs 4 consecutive hangs, and more if there is
> - * progress in between, this is a last resort stop gap measure
> - * to limit the badly behaving clients access to gpu.
> +/* Every context ban increments per client ban score. Also
/*
* Every
One day we'll have rewritten every line of code, and every comment.
> + * hangs in short succession increments ban score. If client suffers 3
> + * context bans, 9 hangs in quick succession or combination of those,
Leave out the numbers if possible, just explain the rationale of the
multilevel system.
> + * it is banned and submitting more work will fail. This is a stop gap
> + * measure to limit the badly behaving clients access to gpu.
> + * Note that unbannable contexts never increment the client ban score.
> */
> -#define I915_MAX_CLIENT_CONTEXT_BANS 3
> - atomic_t context_bans;
> +#define I915_CLIENT_SCORE_HANG_FAST1
> +#define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
> +#define I915_CLIENT_SCORE_CONTEXT_BAN 3
> +#define I915_CLIENT_SCORE_BANNED 9
> + /** ban_score: Accumulated score of all ctx bans and fast hangs. */
> + atomic_t ban_score;
> + unsigned long hang_timestamp;
> };
>
> /* Interface history:
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 8dd4d35655af..f06fe1c636e5 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2941,32 +2941,54 @@ i915_gem_object_pwrite_gtt(struct drm_i915_gem_object
> *obj,
> return 0;
> }
>
> +static void i915_gem_client_mark_guilty(struct drm_i915_file_private
> *file_priv,
> + const struct i915_gem_context *ctx)
> +{
> + unsigned int score;
> + unsigned long prev_hang;
> +
> + if (i915_gem_context_is_banned(ctx))
> + score = I915_CLIENT_SCORE_CONTEXT_BAN;
> + else
> + score = 0;
> +
> + prev_hang = xchg(&file_priv->hang_timestamp, jiffies);
> + if (time_before(jiffies, prev_hang + I915_CLIENT_FAST_HANG_JIFFIES))
> + score += I915_CLIENT_SCORE_HANG_FAST;
> +
> + if (score) {
> + atomic_add(score, &file_priv->ban_score);
> +
> + DRM_DEBUG_DRIVER("client %s: gained %u ban score, now %u\n",
> +ctx->name, score,
> +atomic_read(&file_priv->ban_score));
> + }
> +}
> +
> static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx)
> {
> - bool banned;
> + unsigned int score;
> + bool banned, bannable;
>
> atomic_inc(&ctx->guilty_count);
>
> - banned = false;
> - if (i915_gem_context_is_bannable(ctx)) {
> - unsigned int score;
> + bannable = i915_gem_context_is_bannable(ctx);
> + score = atomic_add_return(CONTEXT_SCORE_GUILTY, &ctx->ban_score);
> + banned = score >= CONTEXT_SCORE_BAN_THRESHOLD;
>
> - score = atomic_add_return(CONTEXT_SCORE_GUILTY,
> - &ctx->ban_score);
> - banned = score >= CONTEXT_SCORE_BAN_THRESHOLD;
> + DRM_DEBUG_DRIVER("context %s: guilty %d, score %u, ban %s:%s\n",
> +ctx->name, atomic_read(&ctx->guilty_count),
> +score, yesno(bannable), yesno(banned));
ban: no:yes
Wut? Maybe just yesno(banned && bannable) as even debug messages
shouldn't strive to confuse us further.
Reviewed-by: Chris Wilson
-Chris
___
[Intel-gfx] [PATCH 02/20] drm/i915/icl: Program DSI Escape clock Divider
Escape Clock is used for LP communication across the DSI
Link. To achieve the constant frequency of the escape clock
from the variable DPLL frequency output, a variable divider(M)
is needed. This patch programs the same.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_dsi_new.c | 65
3 files changed, 67 insertions(+)
create mode 100644 drivers/gpu/drm/i915/intel_dsi_new.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 4c6adae..a5f60c8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -142,6 +142,7 @@ i915-y += dvo_ch7017.o \
intel_dp_mst.o \
intel_dp.o \
intel_dsi.o \
+ intel_dsi_new.o \
intel_dsi_dcs_backlight.o \
intel_dsi_pll.o \
intel_dsi_vbt.o \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf2d3e4..55ef57d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9350,6 +9350,7 @@ enum skl_power_gate {
_ICL_DPHY_ESC_CLK_DIV0, \
_ICL_DPHY_ESC_CLK_DIV1)
#define ICL_ESC_CLK_DIV_MASK 0x1ff
+#define DSI_MAX_ESC_CLK2 /* in KHz */
/* Gen4+ Timestamp and Pipe Frame time stamp registers */
#define GEN4_TIMESTAMP _MMIO(0x2358)
diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c
b/drivers/gpu/drm/i915/intel_dsi_new.c
new file mode 100644
index 000..0d325ca
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Madhav Chauhan
+ * Jani Nikula
+ */
+
+#include "intel_dsi.h"
+
+static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ u32 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+ u32 afe_clk_khz; /* 8X Clock */
+ u32 esc_clk_div_m;
+
+ afe_clk_khz = DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp,
+ intel_dsi->lane_count);
+
+ esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ I915_WRITE(ICL_DSI_ESC_CLK_DIV(port),
+ esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
+ POSTING_READ(ICL_DSI_ESC_CLK_DIV(port));
+ }
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port),
+ esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
+ POSTING_READ(ICL_DPHY_ESC_CLK_DIV(port));
+ }
+}
+
+static void __attribute__((unused)) gen11_dsi_pre_enable(
+ struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config,
+ const struct drm_connector_state *conn_state)
+{
+ /* step3: enable DSI PLL */
+ gen11_dsi_program_esc_clk_div(encoder);
+}
--
2.7.4
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/20] drm/i915/icl: Enable DSI IO power
This patch configures mode of operation for DSI
and enable DDI IO power by configuring power well.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c
b/drivers/gpu/drm/i915/intel_dsi_new.c
index 0d325ca..5ec4016 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -55,11 +55,33 @@ static void gen11_dsi_program_esc_clk_div(struct
intel_encoder *encoder)
}
}
+static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ u32 tmp;
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
+ tmp |= COMBO_PHY_MODE_DSI;
+ I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);
+ }
+
+ intel_display_power_get(dev_priv, POWER_DOMAIN_PORT_DDI_A_IO);
+
+ if (intel_dsi->dual_link)
+ intel_display_power_get(dev_priv, POWER_DOMAIN_PORT_DDI_B_IO);
+}
+
static void __attribute__((unused)) gen11_dsi_pre_enable(
struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
{
+ /* step2: enable IO power */
+ gen11_dsi_enable_io_power(encoder);
+
/* step3: enable DSI PLL */
gen11_dsi_program_esc_clk_div(encoder);
}
--
2.7.4
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 00/20] ICELAKE DSI DRIVER
From ICELAKE platform onwards, new MIPI DSI IP controller is integrated to GPU/Display Engine and same could be extended for future Intel platforms as well. DSI IP controller supports MIPI DSI 1.3 and DPHY 1.2 specification. So, a new DSI driver has been added inside I915. Given below patches are the part of new DSI driver which implements BSPEC sequence till transcoder configuration. Rest of the patches (~45) will be published to GITHUB by mid next week and will share the GITHUB link here so that complete implementation can be looked at by reviewers. Madhav Chauhan (20): drm/i915/icl: Define register for DSI PLL drm/i915/icl: Program DSI Escape clock Divider drm/i915/icl: Define DSI mode ctl register drm/i915/icl: Enable DSI IO power drm/i915/icl: Define PORT_CL_DW_10 register drm/i915/icl: Power down unused DSI lanes drm/i915/icl: Define AUX lane registers for Port A/B drm/i915/icl: Configure lane sequencing of combo phy transmitter drm/i915/icl: DSI vswing programming sequence drm/i915/icl: Enable DDI Buffer drm/i915/icl: Define T_INIT_MASTER registers drm/i915/icl: Program T_INIT_MASTER registers drm/i915/icl: Define data/clock lanes dphy timing registers drm/i915/icl: Program DSI clock and data lane timing params drm/i915/icl: Define TA_TIMING_PARAM registers drm/i915/icl: Program TA_TIMING_PARAM registers drm/i915/icl: Get DSI transcoder for a given port drm/i915/icl: Add macros for MMIO of DSI transcoder registers drm/i915/icl: Define TRANS_DSI_FUNC_CONF register drm/i915/icl: Configure DSI transcoders drivers/gpu/drm/i915/Makefile| 1 + drivers/gpu/drm/i915/i915_reg.h | 174 ++ drivers/gpu/drm/i915/intel_display.h | 6 +- drivers/gpu/drm/i915/intel_dsi.h | 7 + drivers/gpu/drm/i915/intel_dsi_new.c | 455 +++ drivers/gpu/drm/i915/intel_dsi_vbt.c | 202 +++- 6 files changed, 787 insertions(+), 58 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_dsi_new.c -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/20] drm/i915/icl: Define PORT_CL_DW_10 register
This register used to power down individual lanes for
DDI/DSI ports. Bitfields to power up/down various
combinations of lanes are also added in this patch.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0d268d1..1b91e73 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1666,6 +1666,25 @@ enum i915_power_well_id {
#define ICL_PORT_CL_DW5(port) _MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
_ICL_PORT_CL_DW5_B)
+#define _CNL_PORT_CL_DW10_A0x162028
+#define _ICL_PORT_CL_DW10_B0x6c028
+#define ICL_PORT_CL_DW10(port) _MMIO_PORT(port,\
+ _CNL_PORT_CL_DW10_A, \
+ _ICL_PORT_CL_DW10_B)
+#define PG_SEQ_DELAY_OVRRIDE (3 << 25)
+#define PG_SEQ_DELAY_OVRRIDE_ENABLE (1 << 24)
+#define PWR_UP_ALL_LANES 0x0
+#define PWR_DOWN_LN_3_2_1 0xe
+#define PWR_DOWN_LN_3_2 0xc
+#define PWR_DOWN_LN_3 0x8
+#define PWR_DOWN_LN_2_1_0 0x7
+#define PWR_DOWN_LN_1_0 0x3
+#define PWR_DOWN_LN_1 0x2
+#define PWR_DOWN_LN_3_1 0xa
+#define PWR_DOWN_LN_3_1_0 0xb
+#define PWR_DOWN_LN_MASK 0xf0
+#define PWR_DOWN_LN_SHIFT 4
+
#define _PORT_CL1CM_DW9_A 0x162024
#define _PORT_CL1CM_DW9_BC 0x6C024
#define IREF0RC_OFFSET_SHIFT 8
--
2.7.4
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[Intel-gfx] [PATCH 06/20] drm/i915/icl: Power down unused DSI lanes
To save power, unused lanes should be powered
down using the bitfield of PORT_CL_DW10.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.c | 44
1 file changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c
b/drivers/gpu/drm/i915/intel_dsi_new.c
index 5ec4016..baaf46d 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -74,6 +74,47 @@ static void gen11_dsi_enable_io_power(struct intel_encoder
*encoder)
intel_display_power_get(dev_priv, POWER_DOMAIN_PORT_DDI_B_IO);
}
+static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ u32 tmp;
+ u32 lane_mask;
+
+ switch (intel_dsi->lane_count) {
+ case 1:
+ lane_mask = PWR_DOWN_LN_3_1_0;
+ break;
+ case 2:
+ lane_mask = PWR_DOWN_LN_3_1;
+ break;
+ case 3:
+ lane_mask = PWR_DOWN_LN_3;
+ break;
+ case 4:
+ lane_mask = PWR_UP_ALL_LANES;
+ break;
+ default:
+ lane_mask = PWR_UP_ALL_LANES;
+ break;
+ }
+
+ lane_mask = lane_mask << PWR_DOWN_LN_SHIFT;
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(ICL_PORT_CL_DW10(port));
+ tmp &= ~PWR_DOWN_LN_MASK;
+ I915_WRITE(ICL_PORT_CL_DW10(port), tmp | lane_mask);
+ }
+}
+
+static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
+{
+ /* step 4a: power up all lanes of the DDI used by DSI */
+ gen11_dsi_power_up_lanes(encoder);
+}
+
static void __attribute__((unused)) gen11_dsi_pre_enable(
struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config,
@@ -84,4 +125,7 @@ static void __attribute__((unused)) gen11_dsi_pre_enable(
/* step3: enable DSI PLL */
gen11_dsi_program_esc_clk_div(encoder);
+
+ /* step4: enable DSI port and DPHY */
+ gen11_dsi_enable_port_and_phy(encoder);
}
--
2.7.4
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[Intel-gfx] [PATCH 07/20] drm/i915/icl: Define AUX lane registers for Port A/B
This patch defines AUX lane registers for PORT_PCS_DW1,
PORT_TX_DW2, PORT_TX_DW4, PORT_TX_DW5 used during
dsi enabling.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1b91e73..ae00999 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1734,16 +1734,21 @@ enum i915_power_well_id {
_CNL_PORT_PCS_DW1_LN0_D, \
_CNL_PORT_PCS_DW1_LN0_AE, \
_CNL_PORT_PCS_DW1_LN0_F))
+
#define _ICL_PORT_PCS_DW1_GRP_A0x162604
#define _ICL_PORT_PCS_DW1_GRP_B0x6C604
#define _ICL_PORT_PCS_DW1_LN0_A0x162804
#define _ICL_PORT_PCS_DW1_LN0_B0x6C804
+#define _ICL_PORT_PCS_DW1_AUX_B0x6c304
#define ICL_PORT_PCS_DW1_GRP(port) _MMIO_PORT(port,\
_ICL_PORT_PCS_DW1_GRP_A, \
_ICL_PORT_PCS_DW1_GRP_B)
#define ICL_PORT_PCS_DW1_LN0(port) _MMIO_PORT(port, \
_ICL_PORT_PCS_DW1_LN0_A, \
_ICL_PORT_PCS_DW1_LN0_B)
+#define ICL_PORT_PCS_DW1_AUX(port) _MMIO_PORT(port, \
+ _CNL_PORT_PCS_DW1_GRP_AE, \
+ _ICL_PORT_PCS_DW1_AUX_B)
#define COMMON_KEEPER_EN (1 << 26)
/* CNL Port TX registers */
@@ -1780,16 +1785,23 @@ enum i915_power_well_id {
#define _ICL_PORT_TX_DW2_GRP_B 0x6C688
#define _ICL_PORT_TX_DW2_LN0_A 0x162888
#define _ICL_PORT_TX_DW2_LN0_B 0x6C888
+#define _ICL_PORT_TX_DW2_AUX_A 0x162388
+#define _ICL_PORT_TX_DW2_AUX_B 0x6c388
#define ICL_PORT_TX_DW2_GRP(port) _MMIO_PORT(port, \
_ICL_PORT_TX_DW2_GRP_A, \
_ICL_PORT_TX_DW2_GRP_B)
#define ICL_PORT_TX_DW2_LN0(port) _MMIO_PORT(port, \
_ICL_PORT_TX_DW2_LN0_A, \
_ICL_PORT_TX_DW2_LN0_B)
+#define ICL_PORT_TX_DW2_AUX(port) _MMIO_PORT(port, \
+ _ICL_PORT_TX_DW2_AUX_A, \
+ _ICL_PORT_TX_DW2_AUX_B)
#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
#define SWING_SEL_UPPER_MASK (1 << 15)
#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
#define SWING_SEL_LOWER_MASK (0x7 << 11)
+#define FRC_LATENCY_OPTIM_MASK(0x7 << 8)
+#define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8)
#define RCOMP_SCALAR(x) ((x) << 0)
#define RCOMP_SCALAR_MASK(0xFF << 0)
@@ -1805,6 +1817,8 @@ enum i915_power_well_id {
#define _ICL_PORT_TX_DW4_LN0_A 0x162890
#define _ICL_PORT_TX_DW4_LN1_A 0x162990
#define _ICL_PORT_TX_DW4_LN0_B 0x6C890
+#define _ICL_PORT_TX_DW4_AUX_A 0x162390
+#define _ICL_PORT_TX_DW4_AUX_B 0x6c390
#define ICL_PORT_TX_DW4_GRP(port) _MMIO_PORT(port, \
_ICL_PORT_TX_DW4_GRP_A, \
_ICL_PORT_TX_DW4_GRP_B)
@@ -1813,6 +1827,9 @@ enum i915_power_well_id {
_ICL_PORT_TX_DW4_LN0_B) + \
(ln * (_ICL_PORT_TX_DW4_LN1_A - \
_ICL_PORT_TX_DW4_LN0_A)))
+#define ICL_PORT_TX_DW4_AUX(port) _MMIO_PORT(port, \
+ _ICL_PORT_TX_DW4_AUX_A, \
+ _ICL_PORT_TX_DW4_AUX_B)
#define LOADGEN_SELECT (1 << 31)
#define POST_CURSOR_1(x) ((x) << 12)
#define POST_CURSOR_1_MASK (0x3F << 12)
@@ -1827,12 +1844,17 @@ enum i915_power_well_id {
#define _ICL_PORT_TX_DW5_GRP_B 0x6C694
#define _ICL_PORT_TX_DW5_LN0_A 0x162894
#define _ICL_PORT_TX_DW5_LN0_B 0x6C894
+#define _ICL_PORT_TX_DW5_AUX_A 0x162394
+#define _ICL_PORT_TX_DW5_AUX_B 0x6c394
#define ICL_PORT_TX_DW5_GRP(port) _MMIO_PORT(port, \
_ICL_PORT_TX_DW5_GRP_A, \
_ICL_PORT_TX_DW5_GRP_B)
#define ICL_PORT_TX_DW5_LN0(port) _MMIO_PORT(port, \
_ICL_PORT_TX_DW5_LN0_A, \
_ICL_PORT_TX_DW5_LN0_B)
+#define ICL_PORT_TX_DW5_AUX(port) _MMIO_PORT
[Intel-gfx] [PATCH 03/20] drm/i915/icl: Define DSI mode ctl register
This patch defines DSI IO mode control register and it's bits
used while enabling IO power for DSI.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 55ef57d..0d268d1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9486,6 +9486,14 @@ enum skl_power_gate {
#define _BXT_MIPIC_PORT_CTRL 0x6B8C0
#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL,
_BXT_MIPIC_PORT_CTRL)
+/* ICL DSI MODE control */
+#define _ICL_DSI_IO_MODECTL_0 0x6B094
+#define _ICL_DSI_IO_MODECTL_1 0x6B894
+#define ICL_DSI_IO_MODECTL(port) _MMIO_PORT(port,\
+ _ICL_DSI_IO_MODECTL_0, \
+ _ICL_DSI_IO_MODECTL_1)
+#define COMBO_PHY_MODE_DSI(1 << 0)
+
#define BXT_P_DSI_REGULATOR_CFG_MMIO(0x160020)
#define STAP_SELECT (1 << 0)
--
2.7.4
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[Intel-gfx] [PATCH 08/20] drm/i915/icl: Configure lane sequencing of combo phy transmitter
This patch set the loadgen select and latency optimization for
aux and transmit lanes of combo phy transmitters. It will be
used for MIPI DSI HS operations.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.c | 38
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c
b/drivers/gpu/drm/i915/intel_dsi_new.c
index baaf46d..cf52160 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -109,10 +109,48 @@ static void gen11_dsi_power_up_lanes(struct intel_encoder
*encoder)
}
}
+static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ u32 tmp;
+ int lane;
+
+ /* Step 4b(i) set loadgen select for transmit and aux lanes */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
+ tmp &= ~LOADGEN_SELECT;
+ I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
+ for (lane = 0; lane <= 3; lane++) {
+ tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
+ tmp &= ~LOADGEN_SELECT;
+ if (lane != 2)
+ tmp |= LOADGEN_SELECT;
+ I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
+ }
+ }
+
+ /* Step 4b(ii) set latency optimization for transmit and aux lanes */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
+ tmp &= ~FRC_LATENCY_OPTIM_MASK;
+ tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
+ I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
+ tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
+ tmp &= ~FRC_LATENCY_OPTIM_MASK;
+ tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
+ I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
+ }
+}
+
static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
{
/* step 4a: power up all lanes of the DDI used by DSI */
gen11_dsi_power_up_lanes(encoder);
+
+ /* step 4b: configure lane sequencing of the Combo-PHY transmitters */
+ gen11_dsi_config_phy_lanes_sequence(encoder);
}
static void __attribute__((unused)) gen11_dsi_pre_enable(
--
2.7.4
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[Intel-gfx] [PATCH 01/20] drm/i915/icl: Define register for DSI PLL
This patch adds the new registers and corresponding bit definitions
which will be used for programming/enable DSI PLL.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f0317bde..bf2d3e4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9339,6 +9339,18 @@ enum skl_power_gate {
#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
#define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
+#define _ICL_DSI_ESC_CLK_DIV0 0x6b090
+#define _ICL_DSI_ESC_CLK_DIV1 0x6b890
+#define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \
+ _ICL_DSI_ESC_CLK_DIV0, \
+ _ICL_DSI_ESC_CLK_DIV1)
+#define _ICL_DPHY_ESC_CLK_DIV0 0x162190
+#define _ICL_DPHY_ESC_CLK_DIV1 0x6C190
+#define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \
+ _ICL_DPHY_ESC_CLK_DIV0, \
+ _ICL_DPHY_ESC_CLK_DIV1)
+#define ICL_ESC_CLK_DIV_MASK 0x1ff
+
/* Gen4+ Timestamp and Pipe Frame time stamp registers */
#define GEN4_TIMESTAMP _MMIO(0x2358)
#define ILK_TIMESTAMP_HI _MMIO(0x70070)
--
2.7.4
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[Intel-gfx] [PATCH 09/20] drm/i915/icl: DSI vswing programming sequence
This patch setup voltage swing before enabling
combo PHY DDI (shared with DSI).
Note that DSI voltage swing programming is for
high speed data buffers. HW automatically handles
the voltage swing for the low power data buffers.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.c | 114 +++
1 file changed, 114 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c
b/drivers/gpu/drm/i915/intel_dsi_new.c
index cf52160..252af06 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -28,6 +28,65 @@
#include "intel_dsi.h"
+static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ u32 tmp;
+ int lane;
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+
+ /* Bspec: set scaling mode to 0x6 */
+ tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+ tmp |= SCALING_MODE_SEL(6);
+ I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+ tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+ tmp |= SCALING_MODE_SEL(6);
+ I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+ tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+ tmp |= TAP2_DISABLE | TAP3_DISABLE;
+ I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+ tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+ tmp |= TAP2_DISABLE | TAP3_DISABLE;
+ I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+
+ /*
+* swing and scaling values are taken from DSI
+* table under vswing programming sequence for
+* combo phy ddi in BSPEC.
+* program swing values
+*/
+ tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
+ tmp |= SWING_SEL_UPPER(0x2);
+ tmp |= SWING_SEL_LOWER(0x2);
+ tmp |= RCOMP_SCALAR(0x98);
+ I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
+ tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
+ tmp |= SWING_SEL_UPPER(0x2);
+ tmp |= SWING_SEL_LOWER(0x2);
+ tmp |= RCOMP_SCALAR(0x98);
+ I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
+
+ /* program scaling values */
+ tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
+ tmp |= POST_CURSOR_1(0x0);
+ tmp |= POST_CURSOR_2(0x0);
+ tmp |= CURSOR_COEFF(0x18);
+ I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
+
+ for (lane = 0; lane <= 3; lane++) {
+ /* Bspec: must not use GRP register for write */
+ tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane));
+ tmp |= POST_CURSOR_1(0x0);
+ tmp |= POST_CURSOR_2(0x0);
+ tmp |= CURSOR_COEFF(0x18);
+ I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp);
+ }
+ }
+}
+
static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -144,6 +203,58 @@ static void gen11_dsi_config_phy_lanes_sequence(struct
intel_encoder *encoder)
}
}
+static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ u32 tmp;
+ enum port port;
+
+ /* Step C.1:clear common keeper enable bit */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
+ tmp &= ~COMMON_KEEPER_EN;
+ I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
+ tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
+ tmp &= ~COMMON_KEEPER_EN;
+ I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
+ }
+
+ /*
+* Step C.3: Set SUS Clock Config bitfield to 11b
+* Note: Step C.2 (loadgen select program) is done
+* as part of lane phy sequence configuration
+*/
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(ICL_PORT_CL_DW5(port));
+ tmp |= SUS_CLOCK_CONFIG;
+ I915_WRITE(ICL_PORT_CL_DW5(port), tmp);
+ }
+
+ /* Step C.4: Clear training enable to change swing values */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+ tmp &= ~TX_TRAINING_EN;
+ I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+ tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+ tmp &= ~TX_TRAINING_EN;
+ I91
[Intel-gfx] [PATCH 11/20] drm/i915/icl: Define T_INIT_MASTER registers
This patch defines DSI_T_INIT_MASTER register for DSI ports
0/1 which will be used in dphy programming.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ae00999..ef8c1b3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9865,6 +9865,12 @@ enum skl_power_gate {
#define PREPARE_COUNT_SHIFT 0
#define PREPARE_COUNT_MASK(0x3f << 0)
+#define _ICL_DSI_T_INIT_MASTER_0 0x6b088
+#define _ICL_DSI_T_INIT_MASTER_1 0x6b888
+#define ICL_DSI_T_INIT_MASTER(port)_MMIO_PORT(port,\
+ _ICL_DSI_T_INIT_MASTER_0,\
+ _ICL_DSI_T_INIT_MASTER_1)
+
/* bits 31:0 */
#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
--
2.7.4
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[Intel-gfx] [PATCH 14/20] drm/i915/icl: Program DSI clock and data lane timing params
This patch programs D-PHY timing parameters for the
clock and data lane (in escape clocks) of DSI
controller (DSI port 0 and 1).
These programmed timings would be used by DSI Controller
to calculate link transition latencies of the data and
clock lanes.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi.h | 3 +
drivers/gpu/drm/i915/intel_dsi_new.c | 18
drivers/gpu/drm/i915/intel_dsi_vbt.c | 200 +--
3 files changed, 165 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 7afeb95..12a8154 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -85,6 +85,9 @@ struct intel_dsi {
u32 port_bits;
u32 bw_timer;
u32 dphy_reg;
+
+ /* data lanes dphy timing */
+ u32 dphy_data_lane_reg;
u32 video_frmt_cfg_bits;
u16 lp_byte_clk;
diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c
b/drivers/gpu/drm/i915/intel_dsi_new.c
index 369f075..5594252 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -288,6 +288,24 @@ static void gen11_dsi_setup_dphy_timings(struct
intel_encoder *encoder)
tmp |= intel_dsi->init_count;
I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
}
+
+ /* Program DPHY clock lanes timings */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ I915_WRITE(DPHY_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
+
+ /* shadow register inside display core */
+ I915_WRITE(DSI_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg);
+ }
+
+ /* Program DPHY data lanes timings */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ I915_WRITE(DPHY_DATA_TIMING_PARAM(port),
+ intel_dsi->dphy_data_lane_reg);
+
+ /* shadow register inside display core */
+ I915_WRITE(DSI_DATA_TIMING_PARAM(port),
+ intel_dsi->dphy_data_lane_reg);
+ }
}
static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 4d6ffa7..5cc3dd0 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -509,7 +509,9 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
panel_id)
u32 bpp;
u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
u32 ui_num, ui_den;
- u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
+ u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt, hs_zero_cnt;
+ u32 tclk_pre_cnt, tclk_post_cnt;
+ u32 tclk_pre_ns, tclk_post_ns;
u32 ths_prepare_ns, tclk_trail_ns;
u32 tclk_prepare_clkzero, ths_prepare_hszero;
u32 lp_to_hs_switch, hs_to_lp_switch;
@@ -624,76 +626,157 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
panel_id)
tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
ths_prepare_hszero = mipi_config->ths_prepare_hszero;
-
+ tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
+ ths_prepare_ns = max(mipi_config->ths_prepare,
+ mipi_config->tclk_prepare);
/*
* B060
* LP byte clock = TLPX/ (8UI)
*/
intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
- /* DDR clock period = 2 * UI
-* UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
-* UI(nsec) = 10^6 / bitrate
-* DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
-* DDR clock count = ns_value / DDR clock period
-*
+ /*
* For GEMINILAKE dphy_param_reg will be programmed in terms of
* HS byte clock count for other platform in HS ddr clock count
*/
mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
- ths_prepare_ns = max(mipi_config->ths_prepare,
-mipi_config->tclk_prepare);
- /* prepare count */
- prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
+ if (IS_ICELAKE(dev_priv)) {
+ /*
+* prepare cnt in escape clocks
+* this field represents a hexadecimal value with a precision
+* of 1.2 – i.e. the most significant bit is the integer
+* and the least significant 2 bits are fraction bits.
+* so, the field can represent a range of 0.25 to 1.75
+*/
+ prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
+
+ /* clk zero count in escape clocks */
+ clk_zero_cnt = DIV_ROUND_UP(
+ (tclk_prepare_clkzero - ths_prepare_ns),
+ tlpx_ns);
+
+ /* trail cnt in escape clocks*/
+ trail_cnt
[Intel-gfx] [PATCH 10/20] drm/i915/icl: Enable DDI Buffer
This patch enables DDI buffer by writing to DDI_BUF_CTL
register and wait for DDI status to be *not idle* for a
port.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c
b/drivers/gpu/drm/i915/intel_dsi_new.c
index 252af06..c625bca 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -255,6 +255,25 @@ static void gen11_dsi_voltage_swing_program_seq(struct
intel_encoder *encoder)
}
}
+static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ u32 tmp;
+ enum port port;
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(DDI_BUF_CTL(port));
+ tmp |= DDI_BUF_CTL_ENABLE;
+ I915_WRITE(DDI_BUF_CTL(port), tmp);
+
+ if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) &
+ DDI_BUF_IS_IDLE),
+ 500))
+ DRM_ERROR("DDI port:%c buffer idle\n", port_name(port));
+ }
+}
+
static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
{
/* step 4a: power up all lanes of the DDI used by DSI */
@@ -265,6 +284,9 @@ static void gen11_dsi_enable_port_and_phy(struct
intel_encoder *encoder)
/* step 4c: configure voltage swing and skew */
gen11_dsi_voltage_swing_program_seq(encoder);
+
+ /* step 4d: enable DDI buffer */
+ gen11_dsi_enable_ddi_buffer(encoder);
}
static void __attribute__((unused)) gen11_dsi_pre_enable(
--
2.7.4
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[Intel-gfx] [PATCH 13/20] drm/i915/icl: Define data/clock lanes dphy timing registers
This patch defines DSI_CLK_TIMING_PARAM, DPHY_CLK_TIMING_PARAM,
DSI_DATA_TIMING_PARAM, DPHY_DATA_TIMING_PARAM register used in
dphy programming.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 40
1 file changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ef8c1b3..200fd63 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9871,6 +9871,46 @@ enum skl_power_gate {
_ICL_DSI_T_INIT_MASTER_0,\
_ICL_DSI_T_INIT_MASTER_1)
+#define _DPHY_CLK_TIMING_PARAM_0 0x162180
+#define _DPHY_CLK_TIMING_PARAM_1 0x6c180
+#define DPHY_CLK_TIMING_PARAM(port)_MMIO_PORT(port,\
+ _DPHY_CLK_TIMING_PARAM_0,\
+ _DPHY_CLK_TIMING_PARAM_1)
+#define _DSI_CLK_TIMING_PARAM_00x6b080
+#define _DSI_CLK_TIMING_PARAM_10x6b880
+#define DSI_CLK_TIMING_PARAM(port) _MMIO_PORT(port,\
+ _DSI_CLK_TIMING_PARAM_0,\
+ _DSI_CLK_TIMING_PARAM_1)
+#define CLK_PREP_OVERRIDE (1 << 31)
+#define CLK_PREP_TIME(x) (x << 28)
+#define CLK_ZERO_OVERRIDE (1 << 27)
+#define CLK_ZERO_TIME(x) (x << 20)
+#define CLK_PRE_OVERRIDE (1 << 19)
+#define CLK_PRE_TIME(x) (x << 16)
+#define CLK_POST_OVERRIDE (1 << 15)
+#define CLK_POST_TIME(x) (x << 8)
+#define CLK_TRAIL_OVERRIDE(1 << 7)
+#define CLK_TRAIL_TIME(x) (x << 0)
+
+#define _DPHY_DATA_TIMING_PARAM_0 0x162184
+#define _DPHY_DATA_TIMING_PARAM_1 0x6c184
+#define DPHY_DATA_TIMING_PARAM(port) _MMIO_PORT(port,\
+ _DPHY_DATA_TIMING_PARAM_0,\
+ _DPHY_DATA_TIMING_PARAM_1)
+#define _DSI_DATA_TIMING_PARAM_0 0x6B084
+#define _DSI_DATA_TIMING_PARAM_1 0x6B884
+#define DSI_DATA_TIMING_PARAM(port)_MMIO_PORT(port,\
+ _DSI_DATA_TIMING_PARAM_0,\
+ _DSI_DATA_TIMING_PARAM_1)
+#define HS_PREP_OVERRIDE (1 << 31)
+#define HS_PREP_TIME(x) (x << 24)
+#define HS_ZERO_OVERRIDE (1 << 23)
+#define HS_ZERO_TIME(x) (x << 16)
+#define HS_TRAIL_OVERRIDE (1 << 15)
+#define HS_TRAIL_TIME(x) (x << 8)
+#define HS_EXIT_OVERRIDE (1 << 7)
+#define HS_EXIT_TIME(x) (x << 0)
+
/* bits 31:0 */
#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
--
2.7.4
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[Intel-gfx] [PATCH 17/20] drm/i915/icl: Get DSI transcoder for a given port
This patch adds a helper function to retrieve DSI
transcoder for a given DSI port using newly defined
enum names for DSI transcoders.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_display.h | 6 --
drivers/gpu/drm/i915/intel_dsi_new.c | 9 +
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index c88185e..c47d053 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -43,8 +43,10 @@ enum transcoder {
TRANSCODER_B,
TRANSCODER_C,
TRANSCODER_EDP,
- TRANSCODER_DSI_A,
- TRANSCODER_DSI_C,
+ TRANSCODER_DSI_0,
+ TRANSCODER_DSI_1,
+ TRANSCODER_DSI_A = TRANSCODER_DSI_0,/* legacy DSI */
+ TRANSCODER_DSI_C = TRANSCODER_DSI_1,/* legacy DSI */
I915_MAX_TRANSCODERS
};
diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c
b/drivers/gpu/drm/i915/intel_dsi_new.c
index ada075f..dd2f186 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -28,6 +28,15 @@
#include "intel_dsi.h"
+static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(
+ enum port port)
+{
+ if (port == PORT_A)
+ return TRANSCODER_DSI_0;
+ else
+ return TRANSCODER_DSI_1;
+}
+
static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
--
2.7.4
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[Intel-gfx] [PATCH 15/20] drm/i915/icl: Define TA_TIMING_PARAM registers
This patch defines DSI_TA_TIMING_PARAM and
DPHY_TA_TIMING_PARAM registers used in
dphy programming.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 200fd63..289acf2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9911,6 +9911,20 @@ enum skl_power_gate {
#define HS_EXIT_OVERRIDE (1 << 7)
#define HS_EXIT_TIME(x) (x << 0)
+#define _DPHY_TA_TIMING_PARAM_00x162188
+#define _DPHY_TA_TIMING_PARAM_10x6c188
+#define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port,\
+ _DPHY_TA_TIMING_PARAM_0,\
+ _DPHY_TA_TIMING_PARAM_1)
+#define _DSI_TA_TIMING_PARAM_0 0x6b098
+#define _DSI_TA_TIMING_PARAM_1 0x6b898
+#define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port,\
+ _DSI_TA_TIMING_PARAM_0,\
+ _DSI_TA_TIMING_PARAM_1)
+#define TA_SURE_OVERRIDE (1 << 31)
+#define TA_SURE_TIME(x) (x << 16)
+#define TA_SURE_TIME_MASK (0x1f << 16)
+
/* bits 31:0 */
#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
--
2.7.4
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[Intel-gfx] [PATCH 18/20] drm/i915/icl: Add macros for MMIO of DSI transcoder registers
This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing
DSI transcoder registers.
Credits-to: Jani N
Cc: Jani Nikula
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 289acf2..62aa8a6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9375,6 +9375,11 @@ enum skl_power_gate {
#define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c)/* ports A and
C only */
#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
+/* gen11 DSI */
+#define _DSI_TRANS(tc, dsi0, dsi1) (((tc) == TRANSCODER_DSI_0) ? \
+(dsi0) : (dsi1))
+#define _MMIO_DSI(tc, dsi0, dsi1) _MMIO(_DSI_TRANS(tc, dsi0, dsi1))
+
#define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
#define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF
#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
--
2.7.4
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[Intel-gfx] [PATCH 12/20] drm/i915/icl: Program T_INIT_MASTER registers
This patch programs the time (in escape clocks) to drive
the link in the initialization (i.e. LP-11) state.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c
b/drivers/gpu/drm/i915/intel_dsi_new.c
index c625bca..369f075 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -274,6 +274,22 @@ static void gen11_dsi_enable_ddi_buffer(struct
intel_encoder *encoder)
}
}
+static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ u32 tmp;
+ enum port port;
+
+ /* Program T-INIT master registers */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(ICL_DSI_T_INIT_MASTER(port));
+ tmp &= ~MASTER_INIT_TIMER_MASK;
+ tmp |= intel_dsi->init_count;
+ I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
+ }
+}
+
static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
{
/* step 4a: power up all lanes of the DDI used by DSI */
@@ -287,6 +303,9 @@ static void gen11_dsi_enable_port_and_phy(struct
intel_encoder *encoder)
/* step 4d: enable DDI buffer */
gen11_dsi_enable_ddi_buffer(encoder);
+
+ /* step 4e: setup D-PHY timings */
+ gen11_dsi_setup_dphy_timings(encoder);
}
static void __attribute__((unused)) gen11_dsi_pre_enable(
--
2.7.4
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[Intel-gfx] [PATCH 20/20] drm/i915/icl: Configure DSI transcoders
This patch programs DSI operation mode, pixel format,
BGR info, link calibration etc for the DSI transcoder.
This patch also extract BGR info of the DSI panel from
VBT and save it inside struct intel_dsi which used for
configuring DSI transcoder.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi.h | 3 ++
drivers/gpu/drm/i915/intel_dsi_new.c | 87 +++-
drivers/gpu/drm/i915/intel_dsi_vbt.c | 1 +
3 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 16964c2..fdde724 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -81,6 +81,9 @@ struct intel_dsi {
u16 dcs_backlight_ports;
u16 dcs_cabc_ports;
+ /* RGB or BGR */
+ unsigned int bgr_enabled;
+
u8 pixel_overlap;
u32 port_bits;
u32 bw_timer;
diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c
b/drivers/gpu/drm/i915/intel_dsi_new.c
index dd2f186..21fd1b7 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -28,8 +28,7 @@
#include "intel_dsi.h"
-static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(
- enum port port)
+static enum transcoder dsi_port_to_transcoder(enum port port)
{
if (port == PORT_A)
return TRANSCODER_DSI_0;
@@ -338,6 +337,87 @@ static void gen11_dsi_setup_dphy_timings(struct
intel_encoder *encoder)
}
}
+static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ u32 tmp;
+ enum port port;
+ enum transcoder dsi_trans;
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
+
+ if (intel_dsi->eotp_pkt == 0)
+ tmp |= EOTP_DISABLED;
+ else
+ tmp &= ~EOTP_DISABLED;
+
+ /* enable link calibration if freq > 1.5Gbps */
+ if (intel_dsi->bitrate_khz >= (1500 * 1000)) {
+ tmp &= ~LINK_CALIBRATION_MASK;
+ tmp |= LINK_CALIBRATION(
+ CALIBRATION_ENABLED_INITIAL_ONLY);
+ }
+
+ /* configure continuous clock */
+ tmp &= ~CONTINUOUS_CLK_MASK;
+ if (intel_dsi->clock_stop)
+ tmp |= CONTINUOUS_CLK(CLK_ENTER_LP_AFTER_DATA);
+ else
+ tmp |= CONTINUOUS_CLK(CLK_HS_CONTINUOUS);
+
+ /* configure buffer threshold limit to minimum */
+ tmp &= ~PIX_BUF_THRESHOLD_MASK;
+ tmp |= PIX_BUF_THRESHOLD(PIX_BUF_THRESHOLD_1_4);
+
+ /* set virtual channel to '0' */
+ tmp &= ~PIX_VIRT_CHAN_MASK;
+ tmp |= PIX_VIRT_CHAN(0x0);
+
+ /* program BGR transmission */
+ if (intel_dsi->bgr_enabled)
+ tmp |= BGR_TRANSMISSION;
+
+ /* select pixel format */
+ tmp &= ~PIX_FMT_MASK;
+
+ switch (intel_dsi->pixel_format) {
+ case MIPI_DSI_FMT_RGB888:
+ tmp |= PIX_FMT(PIX_FMT_RGB888);
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ tmp |= PIX_FMT(PIX_FMT_RGB666_LOOSE);
+ break;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ tmp |= PIX_FMT(PIX_FMT_RGB666_PACKED);
+ break;
+ case MIPI_DSI_FMT_RGB565:
+ tmp |= PIX_FMT(PIX_FMT_RGB565);
+ break;
+ default:
+ DRM_ERROR("DSI pixel format unsupported\n");
+ }
+
+ /* program DSI operation mode */
+ if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
+ tmp &= ~OP_MODE_MASK;
+ if (intel_dsi->video_mode_format ==
+ VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
+ tmp |= OP_MODE(VIDEO_MODE_SYNC_PULSE);
+ } else if (intel_dsi->video_mode_format ==
+ VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS) {
+ tmp |= OP_MODE(VIDEO_MODE_SYNC_EVENT);
+ } else {
+ DRM_ERROR("DSI Video Mode unsupported\n");
+ }
+ }
+
+ I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
+ }
+}
+
static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
{
[Intel-gfx] [PATCH 16/20] drm/i915/icl: Program TA_TIMING_PARAM registers
This patch programs D-PHY timing parameters for the
bus turn around flow(in escape clocks) only if dsi link
frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
identical register DSI_TA_TIMING_PARAM (inside DSI
Controller within the Display Core).
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi.h | 1 +
drivers/gpu/drm/i915/intel_dsi_new.c | 21 +
drivers/gpu/drm/i915/intel_dsi_vbt.c | 1 +
3 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 12a8154..16964c2 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -101,6 +101,7 @@ struct intel_dsi {
u16 init_count;
u32 pclk;
+ u32 bitrate_khz;
u16 burst_mode_ratio;
/* all delays in ms */
diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c
b/drivers/gpu/drm/i915/intel_dsi_new.c
index 5594252..ada075f 100644
--- a/drivers/gpu/drm/i915/intel_dsi_new.c
+++ b/drivers/gpu/drm/i915/intel_dsi_new.c
@@ -306,6 +306,27 @@ static void gen11_dsi_setup_dphy_timings(struct
intel_encoder *encoder)
I915_WRITE(DSI_DATA_TIMING_PARAM(port),
intel_dsi->dphy_data_lane_reg);
}
+
+ /*
+* If DSI link operating at or below an 800 MHz,
+* TA_SURE should be override and programmed to
+* a value '0' inside TA_PARAM_REGISTERS otherwise
+* leave all fields at HW default values.
+*/
+ if (intel_dsi->bitrate_khz <= KHz(800)) {
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
+ tmp &= ~TA_SURE_TIME_MASK;
+ tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
+ I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp);
+
+ /* shadow register inside display core */
+ tmp = I915_READ(DSI_TA_TIMING_PARAM(port));
+ tmp &= ~TA_SURE_TIME_MASK;
+ tmp |= (TA_SURE_OVERRIDE | TA_SURE_TIME(0));
+ I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
+ }
+ }
}
static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 5cc3dd0..a3d71fb 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -589,6 +589,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
panel_id)
intel_dsi->pclk = pclk;
bitrate = (pclk * bpp) / intel_dsi->lane_count;
+ intel_dsi->bitrate_khz = bitrate;
switch (intel_dsi->escape_clk_div) {
case 0:
--
2.7.4
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[Intel-gfx] [PATCH 19/20] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
This patch defines transcoder function configuration
registers and its bitfields for both DSI ports.
Used while programming/enabling DSI transcoder.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 47 +
1 file changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 62aa8a6..3df9c22 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9930,6 +9930,53 @@ enum skl_power_gate {
#define TA_SURE_TIME(x) (x << 16)
#define TA_SURE_TIME_MASK (0x1f << 16)
+/* DSI transcoder configuration */
+#define _DSI_TRANS_FUNC_CONF_0 0x6b030
+#define _DSI_TRANS_FUNC_CONF_1 0x6b830
+#define DSI_TRANS_FUNC_CONF(tc)_MMIO_DSI(tc, \
+ _DSI_TRANS_FUNC_CONF_0,\
+ _DSI_TRANS_FUNC_CONF_1)
+#define OP_MODE(x)(x << 28)
+#define OP_MODE_MASK (0x3 << 28)
+#define CMD_MODE_NO_GATE 0x0
+#define CMD_MODE_TE_GATE 0x1
+#define VIDEO_MODE_SYNC_EVENT 0x2
+#define VIDEO_MODE_SYNC_PULSE 0x3
+#define LINK_READY(1 << 20)
+#define PIX_FMT(x)(x << 16)
+#define PIX_FMT_MASK (0x3 << 16)
+#define PIX_FMT_RGB5650x0
+#define PIX_FMT_RGB666_PACKED 0x1
+#define PIX_FMT_RGB666_LOOSE 0x2
+#define PIX_FMT_RGB8880x3
+#define PIX_FMT_RGB101010 0x4
+#define PIX_FMT_RGB121212 0x5
+#define PIX_FMT_COMPRESSED0x6
+#define BGR_TRANSMISSION (1 << 15)
+#define PIX_VIRT_CHAN(x) (x << 12)
+#define PIX_VIRT_CHAN_MASK(0x3 << 12)
+#define PIX_BUF_THRESHOLD(x) ((x & 0x3) << 10)
+#define PIX_BUF_THRESHOLD_MASK(0x3 << 10)
+#define PIX_BUF_THRESHOLD_1_4 0x0
+#define PIX_BUF_THRESHOLD_1_2 0x1
+#define PIX_BUF_THRESHOLD_3_4 0x2
+#define PIX_BUF_THRESHOLD_FULL0x3
+#define CONTINUOUS_CLK(x) (x << 8)
+#define CONTINUOUS_CLK_MASK (0x3 << 8)
+#define CLK_ENTER_LP_AFTER_DATA 0x0
+#define CLK_HS_OR_LP 0x2
+#define CLK_HS_CONTINUOUS 0x3
+#define LINK_CALIBRATION(x) (x << 4)
+#define LINK_CALIBRATION_MASK (0x3 << 4)
+#define CALIBRATION_DISABLED 0x0
+#define CALIBRATION_ENABLED_INITIAL_ONLY 0x2
+#define CALIBRATION_ENABLED_INITIAL_PERIODIC 0x3
+#define S3D_ORIENTATION(x)(x << 1)
+#define S3D_ORIENTATION_MASK (0x1 << 1)
+#define S3D_ORIENTATION_PORTRAIT 0x0
+#define S3D_ORIENTATION_LANDSCAPE 0x1
+#define EOTP_DISABLED (1 << 0)
+
/* bits 31:0 */
#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
--
2.7.4
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix context ban and hang accounting for client
== Series Details == Series: drm/i915: Fix context ban and hang accounting for client URL : https://patchwork.freedesktop.org/series/44820/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Fix context ban and hang accounting for client -drivers/gpu/drm/i915/selftests/../i915_drv.h:3683:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3689:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Fix context ban and hang accounting for client
If client is smart or lucky enough to create a new context
after each hang, our context banning mechanism will never
catch up, and as a result of that it will be saved from
client banning. This can result in a never ending streak of
gpu hangs caused by bad or malicious client, preventing
access from other legit gpu clients.
Fix this by always incrementing per client ban score if
it hangs in short successions regardless of context ban
scoring. The exception are non bannable contexts. They remain
detached from client ban scoring mechanism.
v2: xchg timestamp, tidyup (Chris)
v3: comment, bannable & banned together (Chris)
Fixes: b083a0870c79 ("drm/i915: Add per client max context ban limit")
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 21 ++---
drivers/gpu/drm/i915/i915_gem.c | 57 +
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
3 files changed, 55 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 74dd88d8563e..082e84ff0881 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -352,14 +352,21 @@ struct drm_i915_file_private {
unsigned int bsd_engine;
-/* Client can have a maximum of 3 contexts banned before
- * it is denied of creating new contexts. As one context
- * ban needs 4 consecutive hangs, and more if there is
- * progress in between, this is a last resort stop gap measure
- * to limit the badly behaving clients access to gpu.
+/*
+ * Every context ban increments per client ban score. Also
+ * hangs in short succession increments ban score. If ban threshold
+ * is reached, client is considered banned and submitting more work
+ * will fail. This is a stop gap measure to limit the badly behaving
+ * clients access to gpu. Note that unbannable contexts never increment
+ * the client ban score.
*/
-#define I915_MAX_CLIENT_CONTEXT_BANS 3
- atomic_t context_bans;
+#define I915_CLIENT_SCORE_HANG_FAST1
+#define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
+#define I915_CLIENT_SCORE_CONTEXT_BAN 3
+#define I915_CLIENT_SCORE_BANNED 9
+ /** ban_score: Accumulated score of all ctx bans and fast hangs. */
+ atomic_t ban_score;
+ unsigned long hang_timestamp;
};
/* Interface history:
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8dd4d35655af..977982a987c8 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2941,32 +2941,54 @@ i915_gem_object_pwrite_gtt(struct drm_i915_gem_object
*obj,
return 0;
}
+static void i915_gem_client_mark_guilty(struct drm_i915_file_private
*file_priv,
+ const struct i915_gem_context *ctx)
+{
+ unsigned int score;
+ unsigned long prev_hang;
+
+ if (i915_gem_context_is_banned(ctx))
+ score = I915_CLIENT_SCORE_CONTEXT_BAN;
+ else
+ score = 0;
+
+ prev_hang = xchg(&file_priv->hang_timestamp, jiffies);
+ if (time_before(jiffies, prev_hang + I915_CLIENT_FAST_HANG_JIFFIES))
+ score += I915_CLIENT_SCORE_HANG_FAST;
+
+ if (score) {
+ atomic_add(score, &file_priv->ban_score);
+
+ DRM_DEBUG_DRIVER("client %s: gained %u ban score, now %u\n",
+ctx->name, score,
+atomic_read(&file_priv->ban_score));
+ }
+}
+
static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx)
{
- bool banned;
+ unsigned int score;
+ bool banned, bannable;
atomic_inc(&ctx->guilty_count);
- banned = false;
- if (i915_gem_context_is_bannable(ctx)) {
- unsigned int score;
+ bannable = i915_gem_context_is_bannable(ctx);
+ score = atomic_add_return(CONTEXT_SCORE_GUILTY, &ctx->ban_score);
+ banned = score >= CONTEXT_SCORE_BAN_THRESHOLD;
- score = atomic_add_return(CONTEXT_SCORE_GUILTY,
- &ctx->ban_score);
- banned = score >= CONTEXT_SCORE_BAN_THRESHOLD;
+ DRM_DEBUG_DRIVER("context %s: guilty %d, score %u, ban %s\n",
+ctx->name, atomic_read(&ctx->guilty_count),
+score, yesno(banned && bannable));
- DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned?
%s\n",
-ctx->name, score, yesno(banned));
- }
- if (!banned)
+ /* Cool contexts don't accumulate client ban score */
+ if (!bannable)
return;
- i915_gem_context_set_banned(ctx);
- if (!IS_ERR_OR_NULL(ctx->file_priv)) {
- atomic_inc(&ctx->file_priv->context_bans);
- DRM_DEBUG_DRIVER("client %s has had %d context banned\n",
-ctx->name,
atomic_read(&c
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix context ban and hang accounting for client
== Series Details == Series: drm/i915: Fix context ban and hang accounting for client URL : https://patchwork.freedesktop.org/series/44820/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4323 -> Patchwork_9323 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9323 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9323, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44820/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9323: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:PASS -> SKIP == Known issues == Here are the changes found in Patchwork_9323 that come from known issues: === IGT changes === Issues hit igt@gem_exec_gttfill@basic: fi-byt-n2820: PASS -> FAIL (fdo#106744) igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097) Possible fixes igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: FAIL (fdo#100368) -> PASS igt@kms_flip@basic-plain-flip: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#106744 https://bugs.freedesktop.org/show_bug.cgi?id=106744 == Participating hosts (43 -> 38) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4323 -> Patchwork_9323 CI_DRM_4323: 25d3805133071406ffae77c994f464dbbb3bb34e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4519: 3381a56be31defb3b5c23a4fbc19ac26a000c35b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9323: e9aa4424223e3105de81fe8274087163cc809619 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e9aa4424223e drm/i915: Fix context ban and hang accounting for client == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9323/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER
== Series Details ==
Series: ICELAKE DSI DRIVER
URL : https://patchwork.freedesktop.org/series/44823/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c891c2690e61 drm/i915/icl: Define register for DSI PLL
034415bf480c drm/i915/icl: Program DSI Escape clock Divider
-:38: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#38:
new file mode 100644
-:89: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#89: FILE: drivers/gpu/drm/i915/intel_dsi_new.c:47:
+ I915_WRITE(ICL_DSI_ESC_CLK_DIV(port),
+ esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
-:95: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#95: FILE: drivers/gpu/drm/i915/intel_dsi_new.c:53:
+ I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port),
+ esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
-:100: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#100: FILE: drivers/gpu/drm/i915/intel_dsi_new.c:58:
+static void __attribute__((unused)) gen11_dsi_pre_enable(
total: 0 errors, 1 warnings, 3 checks, 79 lines checked
377567cee3fb drm/i915/icl: Define DSI mode ctl register
0c9ae5501a9c drm/i915/icl: Enable DSI IO power
cb9ea5efade8 drm/i915/icl: Define PORT_CL_DW_10 register
159663d4b051 drm/i915/icl: Power down unused DSI lanes
ead6060f69a5 drm/i915/icl: Define AUX lane registers for Port A/B
873188f7da58 drm/i915/icl: Configure lane sequencing of combo phy transmitter
60ff8f5c139f drm/i915/icl: DSI vswing programming sequence
-:31: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#31: FILE: drivers/gpu/drm/i915/intel_dsi_new.c:40:
+ for_each_dsi_port(port, intel_dsi->ports) {
+
total: 0 errors, 0 warnings, 1 checks, 132 lines checked
cb25fce515b5 drm/i915/icl: Enable DDI Buffer
1c8e8d05b24e drm/i915/icl: Define T_INIT_MASTER registers
03cfa39b2778 drm/i915/icl: Program T_INIT_MASTER registers
d55b00eb762f drm/i915/icl: Define data/clock lanes dphy timing registers
-:31: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to
avoid precedence issues
#31: FILE: drivers/gpu/drm/i915/i915_reg.h:9905:
+#define CLK_PREP_TIME(x) (x << 28)
-:33: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to
avoid precedence issues
#33: FILE: drivers/gpu/drm/i915/i915_reg.h:9907:
+#define CLK_ZERO_TIME(x) (x << 20)
-:35: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to
avoid precedence issues
#35: FILE: drivers/gpu/drm/i915/i915_reg.h:9909:
+#define CLK_PRE_TIME(x) (x << 16)
-:37: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to
avoid precedence issues
#37: FILE: drivers/gpu/drm/i915/i915_reg.h:9911:
+#define CLK_POST_TIME(x) (x << 8)
-:39: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to
avoid precedence issues
#39: FILE: drivers/gpu/drm/i915/i915_reg.h:9913:
+#define CLK_TRAIL_TIME(x) (x << 0)
-:52: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to
avoid precedence issues
#52: FILE: drivers/gpu/drm/i915/i915_reg.h:9926:
+#define HS_PREP_TIME(x) (x << 24)
-:54: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to
avoid precedence issues
#54: FILE: drivers/gpu/drm/i915/i915_reg.h:9928:
+#define HS_ZERO_TIME(x) (x << 16)
-:56: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to
avoid precedence issues
#56: FILE: drivers/gpu/drm/i915/i915_reg.h:9930:
+#define HS_TRAIL_TIME(x) (x << 8)
-:58: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to
avoid precedence issues
#58: FILE: drivers/gpu/drm/i915/i915_reg.h:9932:
+#define HS_EXIT_TIME(x) (x << 0)
total: 0 errors, 0 warnings, 9 checks, 46 lines checked
0f1272e068f1 drm/i915/icl: Program DSI clock and data lane timing params
-:80: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#80: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:631:
+ ths_prepare_ns = max(mipi_config->ths_prepare,
+ mipi_config->tclk_prepare);
-:114: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#114: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:655:
+ clk_zero_cnt = DIV_ROUND_UP(
-:128: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#128: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:669:
+ hs_zero_cnt = DIV_ROUND_UP(
-:190: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#190: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:727:
+ prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den,
+ ui_num * mul);
-:196: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#196: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:731:
+ DRM_DEBU
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for ICELAKE DSI DRIVER
== Series Details == Series: ICELAKE DSI DRIVER URL : https://patchwork.freedesktop.org/series/44823/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/icl: Define register for DSI PLL Okay! Commit: drm/i915/icl: Program DSI Escape clock Divider Okay! Commit: drm/i915/icl: Define DSI mode ctl register Okay! Commit: drm/i915/icl: Enable DSI IO power Okay! Commit: drm/i915/icl: Define PORT_CL_DW_10 register Okay! Commit: drm/i915/icl: Power down unused DSI lanes Okay! Commit: drm/i915/icl: Define AUX lane registers for Port A/B Okay! Commit: drm/i915/icl: Configure lane sequencing of combo phy transmitter Okay! Commit: drm/i915/icl: DSI vswing programming sequence Okay! Commit: drm/i915/icl: Enable DDI Buffer Okay! Commit: drm/i915/icl: Define T_INIT_MASTER registers Okay! Commit: drm/i915/icl: Program T_INIT_MASTER registers Okay! Commit: drm/i915/icl: Define data/clock lanes dphy timing registers Okay! Commit: drm/i915/icl: Program DSI clock and data lane timing params -O:drivers/gpu/drm/i915/intel_dsi_vbt.c:644:26: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_dsi_vbt.c:644:26: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_dsi_vbt.c:686:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_dsi_vbt.c:686:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_dsi_vbt.c:718:37: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_dsi_vbt.c:718:37: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dsi_vbt.c:629:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dsi_vbt.c:629:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dsi_vbt.c:630:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dsi_vbt.c:630:26: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dsi_vbt.c:802:37: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_dsi_vbt.c:802:37: warning: expression using sizeof(void) Commit: drm/i915/icl: Define TA_TIMING_PARAM registers Okay! Commit: drm/i915/icl: Program TA_TIMING_PARAM registers Okay! Commit: drm/i915/icl: Get DSI transcoder for a given port Okay! Commit: drm/i915/icl: Add macros for MMIO of DSI transcoder registers Okay! Commit: drm/i915/icl: Define TRANS_DSI_FUNC_CONF register Okay! Commit: drm/i915/icl: Configure DSI transcoders Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/gtt: Enable full-ppgtt by default everywhere
Quoting Chris Wilson (2018-06-14 23:14:18) > We should we have all the kinks worked out and full-ppgtt now works > reliably on gen7 (Ivybridge, Valleyview/Baytrail and Haswell). If we can > let userspace have full control over their own ppgtt, it makes softpinning > far more effective, in turn making GPU dispatch far more efficient and > more secure (due to better mm segregation). On the other hand, switching > over to a different GTT for every client does incur noticeable overhead. > > Signed-off-by: Chris Wilson > Cc: Joonas Lahtinen > Cc: Mika Kuoppala > Cc: Matthew Auld I'd love to get Acks here from Mesa folks for documentation. But for the kernel portions and by my understanding for userspace too this is ready to go, so from me it is: Reviewed-by: Joonas Lahtinen Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/gtt: Full ppgtt everywhere, no excuses
Quoting Chris Wilson (2018-06-14 23:14:19)
> We believe we have all the kinks worked out, even for the early
> Valleyview devices, for whom we currently disable all ppgtt.
>
> References: 62942ed7279d ("drm/i915/vlv: disable PPGTT on early revs v3")
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjälä
> Cc: Joonas Lahtinen
For the rather limited scope of the patch, can you Ville give a Tested-by?
Reviewed-by: Joonas Lahtinen
Regards, Joonas
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Keep the ctx workarounds tightly packed
Chris Wilson writes:
> For each platform, we have a few registers that rewritten with multiple
> values -- they are not part of a sequence, just different parts of a
> masked register set at different times (e.g. platform and gen
> workarounds). Consolidate these into a single register write to keep the
> table compact.
>
> While adjusting the construction of the wa table, make it non fatal so
> that the driver still loads but keeping the warning and extra details
> for inspection.
>
> Signed-off-by: Chris Wilson
> Cc: Oscar Mateo
> Cc: Mika Kuoppala
> Cc: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 25 ++
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_workarounds.c | 63 +---
> 3 files changed, 52 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index c600279d3db5..f78895ffab9b 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3378,28 +3378,13 @@ static int i915_shared_dplls_info(struct seq_file *m,
> void *unused)
>
> static int i915_wa_registers(struct seq_file *m, void *unused)
> {
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> - struct i915_workarounds *workarounds = &dev_priv->workarounds;
> + struct i915_workarounds *wa = &node_to_i915(m->private)->workarounds;
> int i;
>
> - intel_runtime_pm_get(dev_priv);
> -
> - seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
> - for (i = 0; i < workarounds->count; ++i) {
> - i915_reg_t addr;
> - u32 mask, value, read;
> - bool ok;
> -
> - addr = workarounds->reg[i].addr;
> - mask = workarounds->reg[i].mask;
> - value = workarounds->reg[i].value;
> - read = I915_READ(addr);
> - ok = (value & mask) == (read & mask);
> - seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x,
> status: %s\n",
> -i915_mmio_reg_offset(addr), value, mask, read, ok ?
> "OK" : "FAIL");
> - }
> -
> - intel_runtime_pm_put(dev_priv);
> + seq_printf(m, "Workarounds applied: %d\n", wa->count);
> + for (i = 0; i < wa->count; ++i)
> + seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
> +wa->reg[i].addr, wa->reg[i].value, wa->reg[i].mask);
It seems that gem_workarounds is already smart enough to not
parse/trust the driver provided read value.
Perhaps the only value in here was that we saw what
were context and non context saved ones. But we
have other tools for that.
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2c12de678e32..91c389622217 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1308,7 +1308,7 @@ struct i915_frontbuffer_tracking {
> };
>
> struct i915_wa_reg {
> - i915_reg_t addr;
> + u32 addr;
> u32 value;
> /* bitmask representing WA bits */
> u32 mask;
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> b/drivers/gpu/drm/i915/intel_workarounds.c
> index 24b929ce3341..f8bb32e974f6 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -48,29 +48,58 @@
> * - Public functions to init or apply the given workaround type.
> */
>
> -static int wa_add(struct drm_i915_private *dev_priv,
> - i915_reg_t addr,
> - const u32 mask, const u32 val)
> +static void wa_add(struct drm_i915_private *i915,
> +i915_reg_t reg, const u32 mask, const u32 val)
> {
> - const unsigned int idx = dev_priv->workarounds.count;
> + struct i915_workarounds *wa = &i915->workarounds;
> + unsigned int start = 0, end = wa->count;
> + unsigned int addr = i915_mmio_reg_offset(reg);
> + struct i915_wa_reg *r;
> +
> + while (start < end) {
> + unsigned int mid = start + (end - start) / 2;
> +
> + if (wa->reg[mid].addr < addr) {
> + start = mid + 1;
> + } else if (wa->reg[mid].addr > addr) {
> + end = mid;
> + } else {
> + r = &wa->reg[mid];
> +
> + if ((mask & ~r->mask) == 0) {
> + DRM_ERROR("Discarding overwritten w/a for reg
> %04x (mask: %08x, value: %08x)\n",
> + addr, r->mask, r->value);
> +
> + r->value &= ~mask;
> + }
> +
> + r->value |= val;
> + r->mask |= mask;
> + return;
> + }
> + }
>
> - if (WARN_ON(idx >= I915_MAX_WA_REGS))
> - return -ENOSPC;
> + if (WARN_ON_ONCE(wa->count >= I915_MAX_WA_REGS)) {
> + DRM_ERROR("Droppi
[Intel-gfx] ✓ Fi.CI.BAT: success for ICELAKE DSI DRIVER
== Series Details == Series: ICELAKE DSI DRIVER URL : https://patchwork.freedesktop.org/series/44823/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4323 -> Patchwork_9324 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9324 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9324, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44823/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9324: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:PASS -> SKIP == Known issues == Here are the changes found in Patchwork_9324 that come from known issues: === IGT changes === Issues hit igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097, fdo#106000) igt@kms_pipe_crc_basic@hang-read-crc-pipe-b: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106238) +1 Possible fixes igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: FAIL (fdo#100368) -> PASS igt@kms_flip@basic-plain-flip: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#106238 https://bugs.freedesktop.org/show_bug.cgi?id=106238 == Participating hosts (43 -> 38) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4323 -> Patchwork_9324 CI_DRM_4323: 25d3805133071406ffae77c994f464dbbb3bb34e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4519: 3381a56be31defb3b5c23a4fbc19ac26a000c35b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9324: 93beeefce6e707b87e1fb545dc6c79f55dbe11dc @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 93beeefce6e7 drm/i915/icl: Configure DSI transcoders a6e5e2fd35e0 drm/i915/icl: Define TRANS_DSI_FUNC_CONF register 8ec34fab7e4a drm/i915/icl: Add macros for MMIO of DSI transcoder registers dc59f86128ed drm/i915/icl: Get DSI transcoder for a given port f0613ae3d0c5 drm/i915/icl: Program TA_TIMING_PARAM registers baa4e013e1cc drm/i915/icl: Define TA_TIMING_PARAM registers 0f1272e068f1 drm/i915/icl: Program DSI clock and data lane timing params d55b00eb762f drm/i915/icl: Define data/clock lanes dphy timing registers 03cfa39b2778 drm/i915/icl: Program T_INIT_MASTER registers 1c8e8d05b24e drm/i915/icl: Define T_INIT_MASTER registers cb25fce515b5 drm/i915/icl: Enable DDI Buffer 60ff8f5c139f drm/i915/icl: DSI vswing programming sequence 873188f7da58 drm/i915/icl: Configure lane sequencing of combo phy transmitter ead6060f69a5 drm/i915/icl: Define AUX lane registers for Port A/B 159663d4b051 drm/i915/icl: Power down unused DSI lanes cb9ea5efade8 drm/i915/icl: Define PORT_CL_DW_10 register 0c9ae5501a9c drm/i915/icl: Enable DSI IO power 377567cee3fb drm/i915/icl: Define DSI mode ctl register 034415bf480c drm/i915/icl: Program DSI Escape clock Divider c891c2690e61 drm/i915/icl: Define register for DSI PLL == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9324/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Keep the ctx workarounds tightly packed
Quoting Mika Kuoppala (2018-06-15 12:29:23)
> Chris Wilson writes:
>
> > For each platform, we have a few registers that rewritten with multiple
> > values -- they are not part of a sequence, just different parts of a
> > masked register set at different times (e.g. platform and gen
> > workarounds). Consolidate these into a single register write to keep the
> > table compact.
> >
> > While adjusting the construction of the wa table, make it non fatal so
> > that the driver still loads but keeping the warning and extra details
> > for inspection.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Oscar Mateo
> > Cc: Mika Kuoppala
> > Cc: Joonas Lahtinen
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 25 ++
> > drivers/gpu/drm/i915/i915_drv.h | 2 +-
> > drivers/gpu/drm/i915/intel_workarounds.c | 63 +---
> > 3 files changed, 52 insertions(+), 38 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index c600279d3db5..f78895ffab9b 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -3378,28 +3378,13 @@ static int i915_shared_dplls_info(struct seq_file
> > *m, void *unused)
> >
> > static int i915_wa_registers(struct seq_file *m, void *unused)
> > {
> > - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> > - struct i915_workarounds *workarounds = &dev_priv->workarounds;
> > + struct i915_workarounds *wa = &node_to_i915(m->private)->workarounds;
> > int i;
> >
> > - intel_runtime_pm_get(dev_priv);
> > -
> > - seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
> > - for (i = 0; i < workarounds->count; ++i) {
> > - i915_reg_t addr;
> > - u32 mask, value, read;
> > - bool ok;
> > -
> > - addr = workarounds->reg[i].addr;
> > - mask = workarounds->reg[i].mask;
> > - value = workarounds->reg[i].value;
> > - read = I915_READ(addr);
> > - ok = (value & mask) == (read & mask);
> > - seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x,
> > status: %s\n",
> > -i915_mmio_reg_offset(addr), value, mask, read, ok
> > ? "OK" : "FAIL");
> > - }
> > -
> > - intel_runtime_pm_put(dev_priv);
> > + seq_printf(m, "Workarounds applied: %d\n", wa->count);
> > + for (i = 0; i < wa->count; ++i)
> > + seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
> > +wa->reg[i].addr, wa->reg[i].value,
> > wa->reg[i].mask);
>
> It seems that gem_workarounds is already smart enough to not
> parse/trust the driver provided read value.
>
> Perhaps the only value in here was that we saw what
> were context and non context saved ones. But we
> have other tools for that.
We couldn't even rely on it doing that, since what it read would be
random (we may have had a context, the power context may or may not have
the same values, we may never had loaded the values)...
Fortunately, we stopped using them :)
> > return 0;
> > }
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 2c12de678e32..91c389622217 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1308,7 +1308,7 @@ struct i915_frontbuffer_tracking {
> > };
> >
> > struct i915_wa_reg {
> > - i915_reg_t addr;
> > + u32 addr;
> > u32 value;
> > /* bitmask representing WA bits */
> > u32 mask;
> > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> > b/drivers/gpu/drm/i915/intel_workarounds.c
> > index 24b929ce3341..f8bb32e974f6 100644
> > --- a/drivers/gpu/drm/i915/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> > @@ -48,29 +48,58 @@
> > * - Public functions to init or apply the given workaround type.
> > */
> >
> > -static int wa_add(struct drm_i915_private *dev_priv,
> > - i915_reg_t addr,
> > - const u32 mask, const u32 val)
> > +static void wa_add(struct drm_i915_private *i915,
> > +i915_reg_t reg, const u32 mask, const u32 val)
> > {
> > - const unsigned int idx = dev_priv->workarounds.count;
> > + struct i915_workarounds *wa = &i915->workarounds;
> > + unsigned int start = 0, end = wa->count;
> > + unsigned int addr = i915_mmio_reg_offset(reg);
> > + struct i915_wa_reg *r;
> > +
> > + while (start < end) {
> > + unsigned int mid = start + (end - start) / 2;
> > +
> > + if (wa->reg[mid].addr < addr) {
> > + start = mid + 1;
> > + } else if (wa->reg[mid].addr > addr) {
> > + end = mid;
> > + } else {
> > + r = &wa->reg[mid];
> > +
> > + if ((mask & ~r->mask) == 0) {
> > + DRM_ERROR("Discarding overwritten w
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Keep the ctx workarounds tightly packed
Chris Wilson writes:
> For each platform, we have a few registers that rewritten with multiple
> values -- they are not part of a sequence, just different parts of a
> masked register set at different times (e.g. platform and gen
> workarounds). Consolidate these into a single register write to keep the
> table compact.
>
> While adjusting the construction of the wa table, make it non fatal so
> that the driver still loads but keeping the warning and extra details
> for inspection.
>
> Signed-off-by: Chris Wilson
> Cc: Oscar Mateo
> Cc: Mika Kuoppala
> Cc: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 25 ++
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_workarounds.c | 63 +---
> 3 files changed, 52 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index c600279d3db5..f78895ffab9b 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3378,28 +3378,13 @@ static int i915_shared_dplls_info(struct seq_file *m,
> void *unused)
>
> static int i915_wa_registers(struct seq_file *m, void *unused)
> {
> - struct drm_i915_private *dev_priv = node_to_i915(m->private);
> - struct i915_workarounds *workarounds = &dev_priv->workarounds;
> + struct i915_workarounds *wa = &node_to_i915(m->private)->workarounds;
> int i;
>
> - intel_runtime_pm_get(dev_priv);
> -
> - seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
> - for (i = 0; i < workarounds->count; ++i) {
> - i915_reg_t addr;
> - u32 mask, value, read;
> - bool ok;
> -
> - addr = workarounds->reg[i].addr;
> - mask = workarounds->reg[i].mask;
> - value = workarounds->reg[i].value;
> - read = I915_READ(addr);
> - ok = (value & mask) == (read & mask);
> - seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x,
> status: %s\n",
> -i915_mmio_reg_offset(addr), value, mask, read, ok ?
> "OK" : "FAIL");
> - }
> -
> - intel_runtime_pm_put(dev_priv);
> + seq_printf(m, "Workarounds applied: %d\n", wa->count);
> + for (i = 0; i < wa->count; ++i)
> + seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
> +wa->reg[i].addr, wa->reg[i].value, wa->reg[i].mask);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2c12de678e32..91c389622217 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1308,7 +1308,7 @@ struct i915_frontbuffer_tracking {
> };
>
> struct i915_wa_reg {
> - i915_reg_t addr;
> + u32 addr;
> u32 value;
> /* bitmask representing WA bits */
> u32 mask;
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> b/drivers/gpu/drm/i915/intel_workarounds.c
> index 24b929ce3341..f8bb32e974f6 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -48,29 +48,58 @@
> * - Public functions to init or apply the given workaround type.
> */
>
> -static int wa_add(struct drm_i915_private *dev_priv,
> - i915_reg_t addr,
> - const u32 mask, const u32 val)
> +static void wa_add(struct drm_i915_private *i915,
> +i915_reg_t reg, const u32 mask, const u32 val)
> {
> - const unsigned int idx = dev_priv->workarounds.count;
> + struct i915_workarounds *wa = &i915->workarounds;
> + unsigned int start = 0, end = wa->count;
> + unsigned int addr = i915_mmio_reg_offset(reg);
> + struct i915_wa_reg *r;
> +
> + while (start < end) {
> + unsigned int mid = start + (end - start) / 2;
> +
> + if (wa->reg[mid].addr < addr) {
> + start = mid + 1;
> + } else if (wa->reg[mid].addr > addr) {
> + end = mid;
> + } else {
> + r = &wa->reg[mid];
> +
> + if ((mask & ~r->mask) == 0) {
> + DRM_ERROR("Discarding overwritten w/a for reg
> %04x (mask: %08x, value: %08x)\n",
> + addr, r->mask, r->value);
> +
> + r->value &= ~mask;
> + }
> +
> + r->value |= val;
> + r->mask |= mask;
> + return;
> + }
> + }
>
> - if (WARN_ON(idx >= I915_MAX_WA_REGS))
> - return -ENOSPC;
> + if (WARN_ON_ONCE(wa->count >= I915_MAX_WA_REGS)) {
> + DRM_ERROR("Dropping w/a for reg %04x (mask: %08x, value:
> %08x)\n",
> + addr, mask, val);
> + return;
> + }
>
> - dev_priv->workarounds.reg[idx].addr = addr;
> - dev_priv->workarounds.reg[idx].value = v
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix context ban and hang accounting for client (rev2)
== Series Details == Series: drm/i915: Fix context ban and hang accounting for client (rev2) URL : https://patchwork.freedesktop.org/series/44820/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Fix context ban and hang accounting for client -drivers/gpu/drm/i915/selftests/../i915_drv.h:3683:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3690:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Keep the ctx workarounds tightly packed
== Series Details == Series: drm/i915: Keep the ctx workarounds tightly packed URL : https://patchwork.freedesktop.org/series/44807/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4323_full -> Patchwork_9316_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9316_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9316_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9316_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-bsd2: shard-kbl: SKIP -> PASS igt@gem_mocs_settings@mocs-rc6-vebox: shard-kbl: PASS -> SKIP igt@pm_rc6_residency@rc6-accuracy: shard-snb: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9316_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_hangcheck: shard-kbl: PASS -> DMESG-FAIL (fdo#106560) igt@kms_atomic_transition@1x-modeset-transitions-nonblocking: shard-glk: PASS -> FAIL (fdo#105703) igt@kms_flip@2x-plain-flip-fb-recreate: shard-hsw: PASS -> FAIL (fdo#100368) +1 igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: shard-glk: PASS -> FAIL (fdo#100368) +1 igt@prime_busy@wait-after-bsd: shard-snb: NOTRUN -> INCOMPLETE (fdo#105411) igt@prime_vgem@basic-fence-flip: shard-snb: PASS -> FAIL (fdo#104008) Possible fixes igt@drv_selftest@live_gtt: shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> PASS igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: FAIL (fdo#105703) -> PASS igt@kms_flip_tiling@flip-y-tiled: shard-glk: FAIL (fdo#103822, fdo#104724) -> PASS igt@perf_pmu@other-init-2: shard-snb: INCOMPLETE (fdo#105411) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4323 -> Patchwork_9316 CI_DRM_4323: 25d3805133071406ffae77c994f464dbbb3bb34e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4519: 3381a56be31defb3b5c23a4fbc19ac26a000c35b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9316: fa1c64fa7e2045edc633d8b6babd4320be4b7341 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9316/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915: Keep the ctx workarounds tightly packed
For each platform, we have a few registers that are rewritten with
different values -- they are not part of a sequence, just different parts
of a masked register set at different times (e.g. platform and gen
workarounds). Consolidate these into a single register write to keep the
table compact, important since we are running of room in the current
fixed sized buffer.
While adjusting the construction of the wa table, make it non fatal so
that the driver still loads but keeping the warning and extra details
for inspection.
Inspecting the changes for a Kabylake system,
Before:
Address val maskread
0x07014 0x20002000 0x2000 0x2100
0x0E194 0x01000100 0x0100 0x0114
0x0E4F0 0x81008100 0x8100 0x8120
0x0E184 0x00200020 0x0020 0x0022
0x0E194 0x00140014 0x0014 0x0114
0x07004 0x00420042 0x0042 0x29C2
0x0E188 0x0008 0x0008 0x8030
0x07300 0x80208020 0x8020 0x8830
0x07300 0x00100010 0x0010 0x8830
0x0E184 0x00020002 0x0002 0x0022
0x0E180 0x20002000 0x2000 0x2000
0x02580 0x0001 0x0001 0x0004
0x02580 0x00060004 0x0006 0x0004
0x07014 0x01000100 0x0100 0x2100
0x0E100 0x00100010 0x0010 0x8050
After:
Address val maskread
0x02580 0x00070004 0x0007 0x0004
0x07004 0x00420042 0x0042 0x29C2
0x07014 0x21002100 0x2100 0x2100
0x07300 0x80308030 0x8030 0x8830
0x0E100 0x00100010 0x0010 0x8050
0x0E180 0x20002000 0x2000 0x2000
0x0E184 0x00220022 0x0022 0x0022
0x0E188 0x0008 0x0008 0x8030
0x0E194 0x01140114 0x0114 0x0114
0x0E4F0 0x81008100 0x8100 0x8120
Signed-off-by: Chris Wilson
Cc: Oscar Mateo
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_debugfs.c | 25 ++
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_workarounds.c | 63 +---
3 files changed, 52 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 99d3272d82d8..c400f42a54ec 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3378,28 +3378,13 @@ static int i915_shared_dplls_info(struct seq_file *m,
void *unused)
static int i915_wa_registers(struct seq_file *m, void *unused)
{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct i915_workarounds *workarounds = &dev_priv->workarounds;
+ struct i915_workarounds *wa = &node_to_i915(m->private)->workarounds;
int i;
- intel_runtime_pm_get(dev_priv);
-
- seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
- for (i = 0; i < workarounds->count; ++i) {
- i915_reg_t addr;
- u32 mask, value, read;
- bool ok;
-
- addr = workarounds->reg[i].addr;
- mask = workarounds->reg[i].mask;
- value = workarounds->reg[i].value;
- read = I915_READ(addr);
- ok = (value & mask) == (read & mask);
- seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x,
status: %s\n",
- i915_mmio_reg_offset(addr), value, mask, read, ok ?
"OK" : "FAIL");
- }
-
- intel_runtime_pm_put(dev_priv);
+ seq_printf(m, "Workarounds applied: %d\n", wa->count);
+ for (i = 0; i < wa->count; ++i)
+ seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
+ wa->reg[i].addr, wa->reg[i].value, wa->reg[i].mask);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 74dd88d8563e..ea389771f917 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1305,7 +1305,7 @@ struct i915_frontbuffer_tracking {
};
struct i915_wa_reg {
- i915_reg_t addr;
+ u32 addr;
u32 value;
/* bitmask representing WA bits */
u32 mask;
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 24b929ce3341..f8bb32e974f6 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -48,29 +48,58 @@
* - Public functions to init or apply the given workaround type.
*/
-static int wa_add(struct drm_i915_private *dev_priv,
- i915_reg_t addr,
- const u32 mask, c
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix context ban and hang accounting for client (rev2)
== Series Details == Series: drm/i915: Fix context ban and hang accounting for client (rev2) URL : https://patchwork.freedesktop.org/series/44820/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4323 -> Patchwork_9325 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9325 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9325, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44820/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9325: === IGT changes === Warnings igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: fi-glk-j4005: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_9325 that come from known issues: === IGT changes === Issues hit igt@gem_exec_gttfill@basic: fi-byt-n2820: PASS -> FAIL (fdo#106744) igt@kms_addfb_basic@invalid-set-prop-any: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106745) igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097, fdo#106000) +1 Possible fixes igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: FAIL (fdo#100368) -> PASS igt@kms_flip@basic-plain-flip: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#106744 https://bugs.freedesktop.org/show_bug.cgi?id=106744 fdo#106745 https://bugs.freedesktop.org/show_bug.cgi?id=106745 == Participating hosts (43 -> 38) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4323 -> Patchwork_9325 CI_DRM_4323: 25d3805133071406ffae77c994f464dbbb3bb34e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4519: 3381a56be31defb3b5c23a4fbc19ac26a000c35b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9325: 1cdd28f59475c5776076afbbfeca9c72c7f94328 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 1cdd28f59475 drm/i915: Fix context ban and hang accounting for client == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9325/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Keep the ctx workarounds tightly packed (rev2)
== Series Details == Series: drm/i915: Keep the ctx workarounds tightly packed (rev2) URL : https://patchwork.freedesktop.org/series/44807/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4323 -> Patchwork_9326 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/44807/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_9326 that come from known issues: === IGT changes === Issues hit igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097) +2 igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097, fdo#106000) Possible fixes igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: FAIL (fdo#100368) -> PASS igt@kms_flip@basic-plain-flip: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 == Participating hosts (43 -> 38) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4323 -> Patchwork_9326 CI_DRM_4323: 25d3805133071406ffae77c994f464dbbb3bb34e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4519: 3381a56be31defb3b5c23a4fbc19ac26a000c35b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9326: b2844226b8e3d36fc007de932d0e9b2b45762f51 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b2844226b8e3 drm/i915: Keep the ctx workarounds tightly packed == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9326/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Keep the ctx workarounds tightly packed
== Series Details == Series: series starting with [1/2] drm/i915: Keep the ctx workarounds tightly packed URL : https://patchwork.freedesktop.org/series/44809/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4323_full -> Patchwork_9318_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9318_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9318_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9318_full: === IGT changes === Warnings igt@gem_mocs_settings@mocs-rc6-vebox: shard-kbl: PASS -> SKIP +1 igt@pm_rc6_residency@rc6-accuracy: shard-snb: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9318_full that come from known issues: === IGT changes === Issues hit igt@gem_eio@in-flight-internal-immediate: shard-apl: PASS -> FAIL (fdo#105957) igt@gem_exec_suspend@basic-s3: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@kms_cursor_legacy@cursor-vs-flip-toggle: shard-hsw: PASS -> FAIL (fdo#103355) igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: shard-glk: PASS -> FAIL (fdo#100368) +1 igt@kms_flip@2x-plain-flip-ts-check: shard-hsw: PASS -> FAIL (fdo#100368) igt@kms_flip_tiling@flip-to-y-tiled: shard-glk: PASS -> FAIL (fdo#103822, fdo#104724) +1 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt: shard-glk: PASS -> FAIL (fdo#103167, fdo#104724) Possible fixes igt@drv_selftest@live_gtt: shard-glk: INCOMPLETE (fdo#103359, k.org#198133) -> PASS igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: FAIL (fdo#105703) -> PASS igt@kms_setmode@basic: shard-kbl: FAIL (fdo#99912) -> PASS igt@perf_pmu@other-init-2: shard-snb: INCOMPLETE (fdo#105411) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#105957 https://bugs.freedesktop.org/show_bug.cgi?id=105957 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4323 -> Patchwork_9318 CI_DRM_4323: 25d3805133071406ffae77c994f464dbbb3bb34e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4519: 3381a56be31defb3b5c23a4fbc19ac26a000c35b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9318: 5917a776ca11e12245c16146f7f54012f91c @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9318/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] igt/gem_tiled_partial_pwrite_pread: Check for known swizzling
As we want to compare a templated tiling pattern against the target_bo,
we need to know that the swizzling is compatible. Or else the two
tiling pattern may differ due to underlying page address that we cannot
know, and so the test may sporadically fail.
References: https://bugs.freedesktop.org/show_bug.cgi?id=102575
Signed-off-by: Chris Wilson
---
tests/gem_tiled_partial_pwrite_pread.c | 24
1 file changed, 24 insertions(+)
diff --git a/tests/gem_tiled_partial_pwrite_pread.c
b/tests/gem_tiled_partial_pwrite_pread.c
index fe573c37c..83c57c07d 100644
--- a/tests/gem_tiled_partial_pwrite_pread.c
+++ b/tests/gem_tiled_partial_pwrite_pread.c
@@ -249,6 +249,24 @@ static void test_partial_read_writes(void)
}
}
+static bool known_swizzling(uint32_t handle)
+{
+ struct drm_i915_gem_get_tiling2 {
+ uint32_t handle;
+ uint32_t tiling_mode;
+ uint32_t swizzle_mode;
+ uint32_t phys_swizzle_mode;
+ } arg = {
+ .handle = handle,
+ };
+#define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE +
DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
+
+ if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg))
+ return false;
+
+ return arg.phys_swizzle_mode == arg.swizzle_mode;
+}
+
igt_main
{
uint32_t tiling_mode = I915_TILING_X;
@@ -271,6 +289,12 @@ igt_main
&tiling_mode,
&scratch_pitch, 0);
igt_assert(tiling_mode == I915_TILING_X);
igt_assert(scratch_pitch == 4096);
+
+ /*
+* As we want to compare our template tiled pattern against
+* the target bo, we need consistent swizzling on both.
+*/
+ igt_require(known_swizzling(scratch_bo->handle));
staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE,
4096);
tiled_staging_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch
bo", 1024,
BO_SIZE/4096, 4,
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fix context ban and hang accounting for client
Chris Wilson writes:
> Quoting Mika Kuoppala (2018-06-15 11:18:28)
>> If client is smart or lucky enough to create a new context
>> after each hang, our context banning mechanism will never
>> catch up, and as a result of that it will be saved from
>> client banning. This can result in a never ending streak of
>> gpu hangs caused by bad or malicious client, preventing
>> access from other legit gpu clients.
>>
>> Fix this by always incrementing per client ban score if
>> it hangs in short successions regardless of context ban
>> scoring. The exception are non bannable contexts. They remain
>> detached from client ban scoring mechanism.
>>
>> v2: xchg timestamp, tidyup (Chris)
>>
>> Fixes: b083a0870c79 ("drm/i915: Add per client max context ban limit")
>> Cc: Chris Wilson
>> Signed-off-by: Mika Kuoppala
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 20 ++---
>> drivers/gpu/drm/i915/i915_gem.c | 57 +
>> drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
>> 3 files changed, 54 insertions(+), 25 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 74dd88d8563e..93aa8e7dfaba 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -352,14 +352,20 @@ struct drm_i915_file_private {
>>
>> unsigned int bsd_engine;
>>
>> -/* Client can have a maximum of 3 contexts banned before
>> - * it is denied of creating new contexts. As one context
>> - * ban needs 4 consecutive hangs, and more if there is
>> - * progress in between, this is a last resort stop gap measure
>> - * to limit the badly behaving clients access to gpu.
>> +/* Every context ban increments per client ban score. Also
>
> /*
> * Every
>
> One day we'll have rewritten every line of code, and every comment.
>
>> + * hangs in short succession increments ban score. If client suffers 3
>> + * context bans, 9 hangs in quick succession or combination of those,
>
> Leave out the numbers if possible, just explain the rationale of the
> multilevel system.
>
>> + * it is banned and submitting more work will fail. This is a stop gap
>> + * measure to limit the badly behaving clients access to gpu.
>> + * Note that unbannable contexts never increment the client ban score.
>> */
>> -#define I915_MAX_CLIENT_CONTEXT_BANS 3
>> - atomic_t context_bans;
>> +#define I915_CLIENT_SCORE_HANG_FAST1
>> +#define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
>> +#define I915_CLIENT_SCORE_CONTEXT_BAN 3
>> +#define I915_CLIENT_SCORE_BANNED 9
>> + /** ban_score: Accumulated score of all ctx bans and fast hangs. */
>> + atomic_t ban_score;
>> + unsigned long hang_timestamp;
>> };
>>
>> /* Interface history:
>> diff --git a/drivers/gpu/drm/i915/i915_gem.c
>> b/drivers/gpu/drm/i915/i915_gem.c
>> index 8dd4d35655af..f06fe1c636e5 100644
>> --- a/drivers/gpu/drm/i915/i915_gem.c
>> +++ b/drivers/gpu/drm/i915/i915_gem.c
>> @@ -2941,32 +2941,54 @@ i915_gem_object_pwrite_gtt(struct
>> drm_i915_gem_object *obj,
>> return 0;
>> }
>>
>> +static void i915_gem_client_mark_guilty(struct drm_i915_file_private
>> *file_priv,
>> + const struct i915_gem_context *ctx)
>> +{
>> + unsigned int score;
>> + unsigned long prev_hang;
>> +
>> + if (i915_gem_context_is_banned(ctx))
>> + score = I915_CLIENT_SCORE_CONTEXT_BAN;
>> + else
>> + score = 0;
>> +
>> + prev_hang = xchg(&file_priv->hang_timestamp, jiffies);
>> + if (time_before(jiffies, prev_hang + I915_CLIENT_FAST_HANG_JIFFIES))
>> + score += I915_CLIENT_SCORE_HANG_FAST;
>> +
>> + if (score) {
>> + atomic_add(score, &file_priv->ban_score);
>> +
>> + DRM_DEBUG_DRIVER("client %s: gained %u ban score, now %u\n",
>> +ctx->name, score,
>> +atomic_read(&file_priv->ban_score));
>> + }
>> +}
>> +
>> static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx)
>> {
>> - bool banned;
>> + unsigned int score;
>> + bool banned, bannable;
>>
>> atomic_inc(&ctx->guilty_count);
>>
>> - banned = false;
>> - if (i915_gem_context_is_bannable(ctx)) {
>> - unsigned int score;
>> + bannable = i915_gem_context_is_bannable(ctx);
>> + score = atomic_add_return(CONTEXT_SCORE_GUILTY, &ctx->ban_score);
>> + banned = score >= CONTEXT_SCORE_BAN_THRESHOLD;
>>
>> - score = atomic_add_return(CONTEXT_SCORE_GUILTY,
>> - &ctx->ban_score);
>> - banned = score >= CONTEXT_SCORE_BAN_THRESHOLD;
>> + DRM_DEBUG_DRIVER("context %s: guilty %d, score %u, ban %s:%s\n",
>> +ctx->name, atomic_read(&ctx->guilty_count),
>> +score, yesno(bannable), yesno(banned));
>
> ban: no
Re: [Intel-gfx] [PATCH 2/2] drm/i915/gtt: Full ppgtt everywhere, no excuses
On Fri, Jun 15, 2018 at 02:29:08PM +0300, Joonas Lahtinen wrote:
> Quoting Chris Wilson (2018-06-14 23:14:19)
> > We believe we have all the kinks worked out, even for the early
> > Valleyview devices, for whom we currently disable all ppgtt.
> >
> > References: 62942ed7279d ("drm/i915/vlv: disable PPGTT on early revs v3")
> > Signed-off-by: Chris Wilson
> > Cc: Ville Syrjälä
> > Cc: Joonas Lahtinen
>
> For the rather limited scope of the patch, can you Ville give a Tested-by?
Not sure I want to trust the B0 results quite that far.
>
> Reviewed-by: Joonas Lahtinen
>
> Regards, Joonas
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/gtt: Full ppgtt everywhere, no excuses
Quoting Ville Syrjälä (2018-06-15 14:54:39)
> On Fri, Jun 15, 2018 at 02:29:08PM +0300, Joonas Lahtinen wrote:
> > Quoting Chris Wilson (2018-06-14 23:14:19)
> > > We believe we have all the kinks worked out, even for the early
> > > Valleyview devices, for whom we currently disable all ppgtt.
> > >
> > > References: 62942ed7279d ("drm/i915/vlv: disable PPGTT on early revs v3")
> > > Signed-off-by: Chris Wilson
> > > Cc: Ville Syrjälä
> > > Cc: Joonas Lahtinen
> >
> > For the rather limited scope of the patch, can you Ville give a Tested-by?
>
> Not sure I want to trust the B0 results quite that far.
But perhaps an ack? :)
-Chris
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Be irqsafe inside reset
== Series Details == Series: drm/i915: Be irqsafe inside reset URL : https://patchwork.freedesktop.org/series/44814/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4323_full -> Patchwork_9321_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9321_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9321_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9321_full: === IGT changes === Warnings igt@gem_exec_schedule@deep-bsd1: shard-kbl: PASS -> SKIP +3 igt@gem_exec_schedule@deep-bsd2: shard-kbl: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9321_full that come from known issues: === IGT changes === Issues hit igt@drv_selftest@live_hangcheck: shard-apl: PASS -> DMESG-FAIL (fdo#106560) igt@gem_exec_big: shard-hsw: PASS -> INCOMPLETE (fdo#103540) +1 igt@gem_exec_suspend@basic-s3: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@kms_atomic_transition@1x-modeset-transitions-nonblocking: shard-glk: PASS -> FAIL (fdo#105703) igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#105363, fdo#102887) igt@kms_flip@plain-flip-fb-recreate: shard-glk: PASS -> FAIL (fdo#100368) igt@kms_flip_tiling@flip-x-tiled: shard-glk: PASS -> FAIL (fdo#103822, fdo#104724) igt@perf_pmu@idle-vecs0: shard-snb: SKIP -> INCOMPLETE (fdo#105411) Possible fixes igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: FAIL (fdo#105703) -> PASS igt@kms_setmode@basic: shard-apl: FAIL (fdo#99912) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4323 -> Patchwork_9321 CI_DRM_4323: 25d3805133071406ffae77c994f464dbbb3bb34e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4519: 3381a56be31defb3b5c23a4fbc19ac26a000c35b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9321: bd825aa461c85924212bd5614820e3b25903463b @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9321/shards.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/gtt: Full ppgtt everywhere, no excuses
On Fri, Jun 15, 2018 at 02:57:32PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-06-15 14:54:39)
> > On Fri, Jun 15, 2018 at 02:29:08PM +0300, Joonas Lahtinen wrote:
> > > Quoting Chris Wilson (2018-06-14 23:14:19)
> > > > We believe we have all the kinks worked out, even for the early
> > > > Valleyview devices, for whom we currently disable all ppgtt.
> > > >
> > > > References: 62942ed7279d ("drm/i915/vlv: disable PPGTT on early revs
> > > > v3")
> > > > Signed-off-by: Chris Wilson
> > > > Cc: Ville Syrjälä
> > > > Cc: Joonas Lahtinen
> > >
> > > For the rather limited scope of the patch, can you Ville give a Tested-by?
> >
> > Not sure I want to trust the B0 results quite that far.
>
> But perhaps an ack? :)
Sure
Acked-by: Ville Syrjälä
Hopefully we'll get the B2 soon to verify the results.
--
Ville Syrjälä
Intel
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[Intel-gfx] [PATCH] drm/i915/guc: Print CTL params passed to Guc
While debugging we may want to examine params passed to GuC.
Print them all if config I915_DEBUG_GUC is enabled.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
---
drivers/gpu/drm/i915/intel_guc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 1aff30b..f84fbde 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -327,6 +327,11 @@ void intel_guc_init_params(struct intel_guc *guc)
params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
+#ifdef CONFIG_DRM_I915_DEBUG_GUC
+ for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
+ DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
+#endif
+
/*
* All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
* they are power context saved so it's ok to release forcewake
--
1.9.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Print CTL params passed to Guc
== Series Details == Series: drm/i915/guc: Print CTL params passed to Guc URL : https://patchwork.freedesktop.org/series/44834/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4325 -> Patchwork_9327 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/44834/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_9327 that come from known issues: === IGT changes === Issues hit igt@drv_module_reload@basic-reload: fi-skl-6700k2: PASS -> DMESG-WARN (fdo#106697, fdo#104238) igt@drv_module_reload@basic-reload-inject: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106248, fdo#106725, fdo#106000) igt@gem_exec_gttfill@basic: fi-byt-n2820: PASS -> FAIL (fdo#106744) igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: PASS -> FAIL (fdo#100368) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097) Possible fixes igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS +2 igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: fi-glk-j4005: DMESG-WARN (fdo#106097, fdo#106000) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#104238 https://bugs.freedesktop.org/show_bug.cgi?id=104238 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248 fdo#106697 https://bugs.freedesktop.org/show_bug.cgi?id=106697 fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725 fdo#106744 https://bugs.freedesktop.org/show_bug.cgi?id=106744 == Participating hosts (43 -> 38) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4325 -> Patchwork_9327 CI_DRM_4325: 4275ebe85ad179007c49b7bcf78d340b7681871e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4520: 91f5d4665b07f073c78abd3cd4b8e0e347dbf638 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9327: fd446e2e7ecc404cb033f64bc40ab0aa06106cd7 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == fd446e2e7ecc drm/i915/guc: Print CTL params passed to Guc == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9327/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/icl: Fix MG PLL setup when refclk is 38.4MHz
Atm we're zeroing out fields in MG_PLL_BIAS and MG_PLL_TDC_COLDST_BIAS
if refclk is 38.4MHz, whereas the spec tells us to preserve them.
Although the calculated values mostly match the register defaults even
for the 38.4MHz case, there are some differences wrt. what BIOS
programs (I noticed at least differences in the MG_PLL_BIAS/IREFTRIM and
MG_PLL_BIAS/BIASCAL_EN fields). In the lack of further info on how to
program these fields, just do what the spec says and preserve the BIOS
state.
v2:
- Preserve the BIOS programmed reg fields instead of programming them.
Cc: Vandita Kulkarni
Cc: Paulo Zanoni
Cc: James Ausmus
Signed-off-by: Imre Deak
Reviewed-by: James Ausmus (v1)
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 63 +--
drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 ++
2 files changed, 47 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 132fe63e042a..d4c7bacbe83e 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2812,25 +2812,31 @@ static bool icl_calc_mg_pll_state(struct
intel_crtc_state *crtc_state,
MG_PLL_SSC_FLLEN |
MG_PLL_SSC_STEPSIZE(ssc_stepsize);
- pll_state->mg_pll_tdc_coldst_bias = MG_PLL_TDC_COLDST_COLDSTART;
+ pll_state->mg_pll_tdc_coldst_bias = MG_PLL_TDC_COLDST_COLDSTART |
+ MG_PLL_TDC_COLDST_IREFINT_EN |
+
MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) |
+ MG_PLL_TDC_TDCOVCCORR_EN |
+ MG_PLL_TDC_TDCSEL(3);
- if (refclk_khz != 38400) {
- pll_state->mg_pll_tdc_coldst_bias |=
- MG_PLL_TDC_COLDST_IREFINT_EN |
- MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) |
- MG_PLL_TDC_COLDST_COLDSTART |
- MG_PLL_TDC_TDCOVCCORR_EN |
- MG_PLL_TDC_TDCSEL(3);
+ pll_state->mg_pll_bias = MG_PLL_BIAS_BIAS_GB_SEL(3) |
+MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
+MG_PLL_BIAS_BIAS_BONUS(10) |
+MG_PLL_BIAS_BIASCAL_EN |
+MG_PLL_BIAS_CTRIM(12) |
+MG_PLL_BIAS_VREF_RDAC(4) |
+MG_PLL_BIAS_IREFTRIM(iref_trim);
- pll_state->mg_pll_bias = MG_PLL_BIAS_BIAS_GB_SEL(3) |
-MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
-MG_PLL_BIAS_BIAS_BONUS(10) |
-MG_PLL_BIAS_BIASCAL_EN |
-MG_PLL_BIAS_CTRIM(12) |
-MG_PLL_BIAS_VREF_RDAC(4) |
-MG_PLL_BIAS_IREFTRIM(iref_trim);
+ if (refclk_khz == 38400) {
+ pll_state->mg_pll_tdc_coldst_bias_mask =
MG_PLL_TDC_COLDST_COLDSTART;
+ pll_state->mg_pll_bias_mask = 0;
+ } else {
+ pll_state->mg_pll_tdc_coldst_bias_mask = -1U;
+ pll_state->mg_pll_bias_mask = -1U;
}
+ pll_state->mg_pll_tdc_coldst_bias &=
pll_state->mg_pll_tdc_coldst_bias_mask;
+ pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
+
return true;
}
@@ -2948,9 +2954,21 @@ static bool icl_pll_get_hw_state(struct drm_i915_private
*dev_priv,
hw_state->mg_pll_lf = I915_READ(MG_PLL_LF(port));
hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(port));
hw_state->mg_pll_ssc = I915_READ(MG_PLL_SSC(port));
+
hw_state->mg_pll_bias = I915_READ(MG_PLL_BIAS(port));
hw_state->mg_pll_tdc_coldst_bias =
I915_READ(MG_PLL_TDC_COLDST_BIAS(port));
+
+ if (dev_priv->cdclk.hw.ref == 38400) {
+ hw_state->mg_pll_tdc_coldst_bias_mask =
MG_PLL_TDC_COLDST_COLDSTART;
+ hw_state->mg_pll_bias_mask = 0;
+ } else {
+ hw_state->mg_pll_tdc_coldst_bias_mask = -1U;
+ hw_state->mg_pll_bias_mask = -1U;
+ }
+
+ hw_state->mg_pll_tdc_coldst_bias &=
hw_state->mg_pll_tdc_coldst_bias_mask;
+ hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask;
break;
default:
MISSING_CASE(id);
@@ -2978,6 +2996,7 @@ static void icl_mg_pll_write(struct drm_i915_private
*dev_priv,
{
struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
enum port port = icl_mg_pll_id_to_port(pll->info->id);
+ u32 val;
I915_WRITE(MG_REFCLKIN_CTL(port), hw_state->mg_refclkin_ctl);
I915_WRITE(MG_CLKTOP2_
[Intel-gfx] [PATCH 2/2] drm/i915/icl: Do read-modify-write as needed during MG PLL programming
Some MG PLL registers have fields that need to be preserved at their HW
default or BIOS programmed values. So make sure we preserve them.
Cc: Vandita Kulkarni
Cc: Paulo Zanoni
Cc: James Ausmus
Signed-off-by: Imre Deak
Reviewed-by: James Ausmus
---
drivers/gpu/drm/i915/i915_reg.h | 13 +
drivers/gpu/drm/i915/intel_dpll_mgr.c | 33 +
2 files changed, 42 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b8c0ebd50889..506e6896f8ea 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9005,6 +9005,7 @@ enum skl_power_gate {
#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
#define _MG_REFCLKIN_CTL_PORT4 0x16B92C
#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
+#define MG_REFCLKIN_CTL_OD_2_MUX_MASK(0x7 << 8)
#define MG_REFCLKIN_CTL(port) _MMIO_PORT((port) - PORT_C, \
_MG_REFCLKIN_CTL_PORT1, \
_MG_REFCLKIN_CTL_PORT2)
@@ -9014,7 +9015,9 @@ enum skl_power_gate {
#define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8
#define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8
#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
+#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
+#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
#define MG_CLKTOP2_CORECLKCTL1(port) _MMIO_PORT((port) - PORT_C, \
_MG_CLKTOP2_CORECLKCTL1_PORT1, \
_MG_CLKTOP2_CORECLKCTL1_PORT2)
@@ -9024,9 +9027,13 @@ enum skl_power_gate {
#define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
#define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
+#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
+#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(x) ((x) << 12)
+#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
+#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
#define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \
_MG_CLKTOP2_HSCLKCTL_PORT1, \
_MG_CLKTOP2_HSCLKCTL_PORT2)
@@ -9100,12 +9107,18 @@ enum skl_power_gate {
#define _MG_PLL_BIAS_PORT3 0x16AA14
#define _MG_PLL_BIAS_PORT4 0x16BA14
#define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
+#define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
#define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
+#define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)
#define MG_PLL_BIAS_BIAS_BONUS(x)((x) << 16)
+#define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)
#define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
#define MG_PLL_BIAS_CTRIM(x) ((x) << 8)
+#define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)
#define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)
+#define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
#define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
+#define MG_PLL_BIAS_IREFTRIM_MASK(0x1f << 0)
#define MG_PLL_BIAS(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_BIAS_PORT1, \
_MG_PLL_BIAS_PORT2)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index d4c7bacbe83e..3ffc219a2407 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2945,10 +2945,21 @@ static bool icl_pll_get_hw_state(struct
drm_i915_private *dev_priv,
case DPLL_ID_ICL_MGPLL4:
port = icl_mg_pll_id_to_port(id);
hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(port));
+ hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
+
hw_state->mg_clktop2_coreclkctl1 =
I915_READ(MG_CLKTOP2_CORECLKCTL1(port));
+ hw_state->mg_clktop2_coreclkctl1 &=
+ MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
+
hw_state->mg_clktop2_hsclkctl =
I915_READ(MG_CLKTOP2_HSCLKCTL(port));
+ hw_state->mg_clktop2_hsclkctl &= (
+ MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
+ MG_CLKTOP2_HSCLKCTL
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Enable provoking vertex fix on Gen9+ systems.
== Series Details ==
Series: drm/i915: Enable provoking vertex fix on Gen9+ systems.
URL : https://patchwork.freedesktop.org/series/44781/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4325 -> Patchwork_9328 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_9328 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9328, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/44781/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9328:
=== IGT changes ===
Possible regressions
igt@gem_workarounds@basic-read:
fi-skl-6260u: PASS -> FAIL
fi-cfl-s3: PASS -> FAIL
fi-skl-6700k2: PASS -> FAIL
fi-skl-6770hq: PASS -> FAIL
fi-kbl-7560u: PASS -> FAIL
fi-skl-6600u: PASS -> FAIL
fi-bxt-dsi: PASS -> FAIL
fi-kbl-guc: PASS -> FAIL
fi-kbl-7500u: PASS -> FAIL
fi-skl-6700hq: PASS -> FAIL
fi-bxt-j4205: PASS -> FAIL
fi-skl-gvtdvm: PASS -> FAIL
fi-cfl-guc: PASS -> FAIL
{fi-whl-u}: PASS -> FAIL
fi-cfl-8700k: PASS -> FAIL
fi-glk-j4005: PASS -> FAIL
fi-skl-guc: PASS -> FAIL
fi-kbl-7567u: PASS -> FAIL
fi-kbl-r: PASS -> FAIL
== Known issues ==
Here are the changes found in Patchwork_9328 that come from known issues:
=== IGT changes ===
Issues hit
igt@debugfs_test@read_all_entries:
fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713)
igt@kms_pipe_crc_basic@bad-source:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#106238)
igt@pm_rpm@basic-rte:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097)
Possible fixes
igt@kms_flip@basic-flip-vs-modeset:
fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS +1
igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence:
fi-glk-j4005: DMESG-WARN (fdo#106000, fdo#106097) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000
fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097
fdo#106238 https://bugs.freedesktop.org/show_bug.cgi?id=106238
== Participating hosts (43 -> 38) ==
Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4325 -> Patchwork_9328
CI_DRM_4325: 4275ebe85ad179007c49b7bcf78d340b7681871e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4520: 91f5d4665b07f073c78abd3cd4b8e0e347dbf638 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9328: da50a83a608b97e04d4953e56ddc22100dd8d2e1 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
da50a83a608b drm/i915: Enable provoking vertex fix on Gen9+ systems.
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9328/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/icl: Fix MG PLL setup when refclk is 38.4MHz
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Fix MG PLL setup when refclk
is 38.4MHz
URL : https://patchwork.freedesktop.org/series/44836/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b74cd00bcd1f drm/i915/icl: Fix MG PLL setup when refclk is 38.4MHz
53a13e6c6e2b drm/i915/icl: Do read-modify-write as needed during MG PLL
programming
-:88: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#88: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2957:
+ hw_state->mg_clktop2_hsclkctl &= (
total: 0 errors, 0 warnings, 1 checks, 96 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/icl: Fix MG PLL setup when refclk is 38.4MHz
== Series Details == Series: series starting with [1/2] drm/i915/icl: Fix MG PLL setup when refclk is 38.4MHz URL : https://patchwork.freedesktop.org/series/44836/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4325 -> Patchwork_9329 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9329 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9329, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44836/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9329: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9329 that come from known issues: === IGT changes === Issues hit igt@gem_exec_gttfill@basic: fi-byt-n2820: PASS -> FAIL (fdo#106744) igt@kms_pipe_crc_basic@read-crc-pipe-c: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927) Possible fixes igt@kms_flip@basic-plain-flip: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: fi-glk-j4005: DMESG-WARN (fdo#106000, fdo#106097) -> PASS fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#106744 https://bugs.freedesktop.org/show_bug.cgi?id=106744 == Participating hosts (43 -> 38) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4325 -> Patchwork_9329 CI_DRM_4325: 4275ebe85ad179007c49b7bcf78d340b7681871e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4520: 91f5d4665b07f073c78abd3cd4b8e0e347dbf638 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9329: 53a13e6c6e2b34622403c66aa9b8f08015ff9236 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 53a13e6c6e2b drm/i915/icl: Do read-modify-write as needed during MG PLL programming b74cd00bcd1f drm/i915/icl: Fix MG PLL setup when refclk is 38.4MHz == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9329/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] drm/i915: Prevent writing into a read-only object via a GGTT mmap
If the user has created a read-only object, they should not be allowed
to circumvent the write protection by using a GGTT mmapping. Deny it.
Also most machines do not support read-only GGTT PTEs, so again we have
to reject attempted writes. Fortunately, this is known a priori, so we
can at least reject in the call to create the mmap (with a sanity check
in the fault handler).
v2: Check the vma->vm_flags during mmap() to allow readonly access.
v3: Remove VM_MAYWRITE to curtail mprotect()
Testcase: igt/gem_userptr_blits/readonly_mmap*
Signed-off-by: Chris Wilson
Cc: Jon Bloomfield
Cc: Joonas Lahtinen
Cc: Matthew Auld
Cc: David Herrmann
Reviewed-by: Matthew Auld #v1
Reviewed-by: Jon Bloomfield
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/drm_gem.c | 9 +
drivers/gpu/drm/i915/i915_gem.c | 4
drivers/gpu/drm/i915/i915_gem_gtt.c | 12 +++-
drivers/gpu/drm/i915/i915_gem_object.h| 13 -
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_gem_context.c | 5 +++--
include/drm/drm_vma_manager.h | 1 +
7 files changed, 37 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 4a16d7b26c89..bf90625df3c5 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -1036,6 +1036,15 @@ int drm_gem_mmap(struct file *filp, struct
vm_area_struct *vma)
return -EACCES;
}
+ if (node->readonly) {
+ if (vma->vm_flags & VM_WRITE) {
+ drm_gem_object_put_unlocked(obj);
+ return -EINVAL;
+ }
+
+ vma->vm_flags &= ~VM_MAYWRITE;
+ }
+
ret = drm_gem_mmap_obj(obj, drm_vma_node_size(node) << PAGE_SHIFT,
vma);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a3515cad0b51..3c475c9fcdd9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2009,6 +2009,10 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
unsigned int flags;
int ret;
+ /* Sanity check that we allow writing into this object */
+ if (i915_gem_object_is_readonly(obj) && write)
+ return VM_FAULT_SIGBUS;
+
/* We don't use vmf->pgoff since that has the fake offset */
page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 64f11cc9c3f2..a28943ae8d40 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -198,7 +198,7 @@ static int ppgtt_bind_vma(struct i915_vma *vma,
/* Applicable to VLV, and gen8+ */
pte_flags = 0;
- if (vma->obj->gt_ro)
+ if (i915_gem_object_is_readonly(vma->obj))
pte_flags |= PTE_READ_ONLY;
vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
@@ -2413,8 +2413,10 @@ static void gen8_ggtt_insert_entries(struct
i915_address_space *vm,
const gen8_pte_t pte_encode = gen8_pte_encode(0, level, 0);
dma_addr_t addr;
- /* The GTT does not support read-only mappings */
- GEM_BUG_ON(flags & PTE_READ_ONLY);
+ /*
+* Note that we ignore PTE_READ_ONLY here. The caller must be careful
+* not to allow the user to override access to a read only page.
+*/
gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm;
gtt_entries += vma->node.start >> PAGE_SHIFT;
@@ -2653,7 +2655,7 @@ static int ggtt_bind_vma(struct i915_vma *vma,
/* Applicable to VLV (gen8+ do not support RO in the GGTT) */
pte_flags = 0;
- if (obj->gt_ro)
+ if (i915_gem_object_is_readonly(obj))
pte_flags |= PTE_READ_ONLY;
intel_runtime_pm_get(i915);
@@ -2691,7 +2693,7 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma,
/* Currently applicable only to VLV */
pte_flags = 0;
- if (vma->obj->gt_ro)
+ if (i915_gem_object_is_readonly(vma->obj))
pte_flags |= PTE_READ_ONLY;
if (flags & I915_VMA_LOCAL_BIND) {
diff --git a/drivers/gpu/drm/i915/i915_gem_object.h
b/drivers/gpu/drm/i915/i915_gem_object.h
index 54f00b350779..fd703d768b70 100644
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -141,7 +141,6 @@ struct drm_i915_gem_object {
* Is the object to be mapped as read-only to the GPU
* Only honoured if hardware has relevant pte bit
*/
- unsigned long gt_ro:1;
unsigned int cache_level:3;
unsigned int cache_coherent:2;
#define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
@@ -367,6 +366,18 @@ static inline void i915_gem_object_unlock(struct
drm_i915_gem_object *obj)
reservation_object_unlock(obj->resv);
}
+static inl
[Intel-gfx] [PATCH i-g-t 1/2] igt/gem_userptr: Exercise new PROBE | POPULATE flags
Exercise new API to probe that the userptr range is valid (backed by
struct pages and not pfn) or to populate the userptr upon creation (by
calling get_user_pages() on the range).
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Michał Winiarski
---
tests/gem_userptr_blits.c | 140 ++
1 file changed, 140 insertions(+)
diff --git a/tests/gem_userptr_blits.c b/tests/gem_userptr_blits.c
index 7e3b6ef38..0c2bdf5b2 100644
--- a/tests/gem_userptr_blits.c
+++ b/tests/gem_userptr_blits.c
@@ -557,6 +557,140 @@ static int test_invalid_gtt_mapping(int fd)
return 0;
}
+static void store_dword(int fd, uint32_t target,
+ uint32_t offset, uint32_t value)
+{
+ const int gen = intel_gen(intel_get_drm_devid(fd));
+ struct drm_i915_gem_exec_object2 obj[2];
+ struct drm_i915_gem_relocation_entry reloc;
+ struct drm_i915_gem_execbuffer2 execbuf;
+ uint32_t batch[16];
+ int i;
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.buffer_count = ARRAY_SIZE(obj);
+ execbuf.flags = 0;
+ if (gen < 6)
+ execbuf.flags |= I915_EXEC_SECURE;
+
+ memset(obj, 0, sizeof(obj));
+ obj[0].handle = target;
+ obj[1].handle = gem_create(fd, 4096);
+
+ memset(&reloc, 0, sizeof(reloc));
+ reloc.target_handle = obj[0].handle;
+ reloc.presumed_offset = 0;
+ reloc.offset = sizeof(uint32_t);
+ reloc.delta = offset;
+ reloc.read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc.write_domain = I915_GEM_DOMAIN_RENDER;
+ obj[1].relocs_ptr = to_user_pointer(&reloc);
+ obj[1].relocation_count = 1;
+
+ i = 0;
+ batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
+ if (gen >= 8) {
+ batch[++i] = offset;
+ batch[++i] = 0;
+ } else if (gen >= 4) {
+ batch[++i] = 0;
+ batch[++i] = offset;
+ reloc.offset += sizeof(uint32_t);
+ } else {
+ batch[i]--;
+ batch[++i] = offset;
+ }
+ batch[++i] = value;
+ batch[++i] = MI_BATCH_BUFFER_END;
+ gem_write(fd, obj[1].handle, 0, batch, sizeof(batch));
+ gem_execbuf(fd, &execbuf);
+ gem_close(fd, obj[1].handle);
+}
+
+#define LOCAL_USERPTR_PROBE 0x2
+#define LOCAL_USERPTR_POPULATE 0x4
+static void test_probe(int fd, unsigned int flags)
+{
+#define N_PAGES 5
+ struct drm_i915_gem_mmap_gtt mmap_gtt;
+ uint32_t handle;
+
+ igt_require(__gem_userptr(fd,
+ (void *)-PAGE_SIZE, 2*PAGE_SIZE, 0,
+ flags, &handle) == -EFAULT);
+
+ /*
+* We allocate 5 pages, and apply various combinations
+* of unmap, remap-gtt to the pages. Then we try to
+* create a userptr from the middle 3 pages and check
+* if unexpectedly succeeds or fails.
+*/
+ memset(&mmap_gtt, 0, sizeof(mmap_gtt));
+ mmap_gtt.handle = gem_create(fd, PAGE_SIZE);
+ drmIoctl(fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &mmap_gtt);
+
+ for (unsigned long pass = 0; pass < 4 * 4 * 4 * 4 *4; pass++) {
+ int expected = 0;
+ void *ptr;
+
+ ptr = mmap(NULL, N_PAGES * PAGE_SIZE,
+ PROT_READ | PROT_WRITE,
+ MAP_SHARED | MAP_ANONYMOUS,
+ -1, 0);
+
+ for (int page = 0; page < N_PAGES; page++) {
+ int mode = (pass >> (2 * page)) & 3;
+ void *fixed = ptr + page * PAGE_SIZE;
+
+ switch (mode) {
+ default:
+ case 0:
+ break;
+
+ case 1:
+ munmap(fixed, PAGE_SIZE);
+ if (page >= 1 && page <= 3)
+ expected = -EFAULT;
+ break;
+
+ case 2:
+ fixed = mmap(fixed, PAGE_SIZE,
+PROT_READ | PROT_WRITE,
+MAP_SHARED | MAP_FIXED,
+fd, mmap_gtt.offset);
+ igt_assert(fixed != MAP_FAILED);
+ if (page >= 1 && page <= 3)
+ expected = -EFAULT;
+ break;
+ }
+ }
+
+ errno = 0;
+ handle = 0;
+ igt_assert_eq(__gem_userptr(fd, ptr + PAGE_SIZE, 3*PAGE_SIZE,
+ 0, flags, &handle),
+ expected);
+ if (handle) {
+ for (int page = 0; page < 3; page++)
+
[Intel-gfx] [PATCH i-g-t 2/2] igt/gem_userptr: Check read-only mappings
Setup a userptr object that only has a read-only mapping back to a file
store (memfd). Then attempt to write into that mapping using the GPU and
assert that those writes do not land (while also writing via a writable
userptr mapping into the same memfd to verify that the GPU is working!)
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
---
configure.ac | 1 +
lib/ioctl_wrappers.c | 4 +-
lib/ioctl_wrappers.h | 4 +-
tests/Makefile.am | 4 +-
tests/gem_userptr_blits.c | 282 ++
5 files changed, 289 insertions(+), 6 deletions(-)
diff --git a/configure.ac b/configure.ac
index 2f6bc70ee..f5a059d6a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -125,6 +125,7 @@ PKG_CHECK_MODULES(PCIACCESS, [pciaccess >= 0.10])
PKG_CHECK_MODULES(KMOD, [libkmod])
PKG_CHECK_MODULES(PROCPS, [libprocps])
PKG_CHECK_MODULES(LIBUNWIND, [libunwind])
+PKG_CHECK_MODULES(SSL, [openssl])
PKG_CHECK_MODULES(VALGRIND, [valgrind], [have_valgrind=yes],
[have_valgrind=no])
if test x$have_valgrind = xyes; then
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 79db44a8c..d5d2a4e4c 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -869,7 +869,7 @@ int gem_madvise(int fd, uint32_t handle, int state)
return madv.retained;
}
-int __gem_userptr(int fd, void *ptr, int size, int read_only, uint32_t flags,
uint32_t *handle)
+int __gem_userptr(int fd, void *ptr, uint64_t size, int read_only, uint32_t
flags, uint32_t *handle)
{
struct drm_i915_gem_userptr userptr;
@@ -898,7 +898,7 @@ int __gem_userptr(int fd, void *ptr, int size, int
read_only, uint32_t flags, ui
*
* Returns userptr handle for the GEM object.
*/
-void gem_userptr(int fd, void *ptr, int size, int read_only, uint32_t flags,
uint32_t *handle)
+void gem_userptr(int fd, void *ptr, uint64_t size, int read_only, uint32_t
flags, uint32_t *handle)
{
igt_assert_eq(__gem_userptr(fd, ptr, size, read_only, flags, handle),
0);
}
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index b966f72c9..8e2cd380b 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -133,8 +133,8 @@ struct local_i915_gem_userptr {
#define LOCAL_I915_USERPTR_UNSYNCHRONIZED (1<<31)
uint32_t handle;
};
-void gem_userptr(int fd, void *ptr, int size, int read_only, uint32_t flags,
uint32_t *handle);
-int __gem_userptr(int fd, void *ptr, int size, int read_only, uint32_t flags,
uint32_t *handle);
+void gem_userptr(int fd, void *ptr, uint64_t size, int read_only, uint32_t
flags, uint32_t *handle);
+int __gem_userptr(int fd, void *ptr, uint64_t size, int read_only, uint32_t
flags, uint32_t *handle);
void gem_sw_finish(int fd, uint32_t handle);
diff --git a/tests/Makefile.am b/tests/Makefile.am
index f41ad5096..ba307b220 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -126,8 +126,8 @@ gem_tiled_swapping_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
gem_tiled_swapping_LDADD = $(LDADD) -lpthread
prime_self_import_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
prime_self_import_LDADD = $(LDADD) -lpthread
-gem_userptr_blits_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
-gem_userptr_blits_LDADD = $(LDADD) -lpthread
+gem_userptr_blits_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) $(SSL_CFLAGS)
+gem_userptr_blits_LDADD = $(LDADD) $(SSL_LIBS) -lpthread
perf_pmu_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la
gem_eio_LDADD = $(LDADD) -lrt
diff --git a/tests/gem_userptr_blits.c b/tests/gem_userptr_blits.c
index 0c2bdf5b2..8e362cd41 100644
--- a/tests/gem_userptr_blits.c
+++ b/tests/gem_userptr_blits.c
@@ -43,13 +43,17 @@
#include
#include
#include
+#include
#include
#include
#include
+#include
#include
#include
#include
+#include
+
#include "drm.h"
#include "i915_drm.h"
@@ -1075,6 +1079,275 @@ static int test_dmabuf(void)
return 0;
}
+static void test_readonly(int i915)
+{
+ unsigned char orig[SHA_DIGEST_LENGTH];
+ uint64_t aperture_size;
+ uint32_t whandle, rhandle;
+ size_t sz, total;
+ void *pages, *space;
+ int memfd;
+
+ /*
+* A small batch of pages; small enough to cheaply check for stray
+* writes but large enough that we don't create too many VMA pointing
+* back to this set from the large arena. The limit on total number
+* of VMA for a process is 65,536 (at least on this kernel).
+*/
+ sz = 16 << 12;
+ memfd = memfd_create("pages", 0);
+ igt_require(memfd != -1);
+ igt_require(ftruncate(memfd, sz) == 0);
+
+ pages = mmap(NULL, sz, PROT_WRITE, MAP_SHARED, memfd, 0);
+ igt_assert(pages != MAP_FAILED);
+
+ igt_require(__gem_userptr(i915, pages, sz, true, userptr_flags,
&rhandle) == 0);
+ gem_close(i915, rhandle);
+
+ gem_userptr(i915, pages, sz, false, userptr_flags, &whandle);
+
+ total = 2048ull << 20;
+ aperture_size = gem_aperture_size(i915) / 2;
+
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915/gtt: Add read only pages to gen8_pte_encode (rev3)
== Series Details ==
Series: series starting with [1/5] drm/i915/gtt: Add read only pages to
gen8_pte_encode (rev3)
URL : https://patchwork.freedesktop.org/series/44776/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0358c9fd1b9b drm/i915/gtt: Add read only pages to gen8_pte_encode
765448876d70 drm/i915/gtt: Read-only pages for insert_entries on bdw+
-:192: WARNING:BOOL_BITFIELD: Avoid using bool as bitfield. Prefer bool
bitfields as unsigned int or u<8|16|32>
#192: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:330:
+ bool pt_kmap_wc:1;
-:195: WARNING:BOOL_BITFIELD: Avoid using bool as bitfield. Prefer bool
bitfields as unsigned int or u<8|16|32>
#195: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:333:
+ bool has_read_only:1;
-:271: WARNING:LINE_SPACING: Missing a blank line after declarations
#271: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:430:
+ struct drm_file *file;
+ I915_RND_STATE(prng);
-:342: ERROR:CODE_INDENT: code indent should use tabs where possible
#342: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:501:
+^I ^Indwords, INTEL_INFO(i915)->num_rings);$
-:342: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#342: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:501:
+^I ^Indwords, INTEL_INFO(i915)->num_rings);$
-:342: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#342: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:501:
+ pr_info("Submitted %lu dwords (across %u engines)\n",
+ ndwords, INTEL_INFO(i915)->num_rings);
total: 1 errors, 4 warnings, 1 checks, 323 lines checked
9468f84d4626 drm/i915: Prevent writing into a read-only object via a GGTT mmap
-:182: WARNING:BOOL_BITFIELD: Avoid using bool as bitfield. Prefer bool
bitfields as unsigned int or u<8|16|32>
#182: FILE: include/drm/drm_vma_manager.h:44:
+ bool readonly:1;
total: 0 errors, 1 warnings, 0 checks, 118 lines checked
7927204dc8b7 drm/i915: Reject attempted pwrites into a read-only object
af7db8229431 drm/i915/userptr: Enable read-only support on gen8+
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915/gtt: Add read only pages to gen8_pte_encode (rev3)
== Series Details == Series: series starting with [1/5] drm/i915/gtt: Add read only pages to gen8_pte_encode (rev3) URL : https://patchwork.freedesktop.org/series/44776/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/gtt: Add read only pages to gen8_pte_encode Okay! Commit: drm/i915/gtt: Read-only pages for insert_entries on bdw+ +drivers/gpu/drm/i915/selftests/i915_gem_context.c:506:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:506:25: warning: expression using sizeof(void) Commit: drm/i915: Prevent writing into a read-only object via a GGTT mmap Okay! Commit: drm/i915: Reject attempted pwrites into a read-only object Okay! Commit: drm/i915/userptr: Enable read-only support on gen8+ Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/gtt: Add read only pages to gen8_pte_encode (rev3)
== Series Details == Series: series starting with [1/5] drm/i915/gtt: Add read only pages to gen8_pte_encode (rev3) URL : https://patchwork.freedesktop.org/series/44776/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4325 -> Patchwork_9330 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9330 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9330, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44776/revisions/3/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9330: === IGT changes === Warnings igt@gem_exec_gttfill@basic: fi-pnv-d510:SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9330 that come from known issues: === IGT changes === Issues hit igt@gem_exec_gttfill@basic: fi-byt-n2820: PASS -> FAIL (fdo#106744) Possible fixes igt@kms_flip@basic-plain-flip: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS +1 igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: fi-glk-j4005: DMESG-WARN (fdo#106000, fdo#106097) -> PASS fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#106744 https://bugs.freedesktop.org/show_bug.cgi?id=106744 == Participating hosts (43 -> 38) == Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4325 -> Patchwork_9330 CI_DRM_4325: 4275ebe85ad179007c49b7bcf78d340b7681871e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4520: 91f5d4665b07f073c78abd3cd4b8e0e347dbf638 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9330: af7db8229431c36770ba54e8e5003451794c8151 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == af7db8229431 drm/i915/userptr: Enable read-only support on gen8+ 7927204dc8b7 drm/i915: Reject attempted pwrites into a read-only object 9468f84d4626 drm/i915: Prevent writing into a read-only object via a GGTT mmap 765448876d70 drm/i915/gtt: Read-only pages for insert_entries on bdw+ 0358c9fd1b9b drm/i915/gtt: Add read only pages to gen8_pte_encode == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9330/issues.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Keep the ctx workarounds tightly packed
On 6/15/2018 1:59 AM, Chris Wilson wrote:
For each platform, we have a few registers that rewritten with multiple
values -- they are not part of a sequence, just different parts of a
masked register set at different times (e.g. platform and gen
workarounds). Consolidate these into a single register write to keep the
table compact.
While adjusting the construction of the wa table, make it non fatal so
that the driver still loads but keeping the warning and extra details
for inspection.
A while ago I sent a patch
(https://patchwork.freedesktop.org/patch/205035/) that uses simple MMIO
writes to apply ctx workarounds. This is possible since we now have
proper golden contexts, and avoids the need for these patches.
It also has the advantage that an improperly classified WA doesn't get
lost (we still need the classification if we want to properly validate
the WAs, but that's a different story).
Are we sure we prefer to do this instead?
Signed-off-by: Chris Wilson
Cc: Oscar Mateo
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c | 25 ++
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_workarounds.c | 63 +---
3 files changed, 52 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index c600279d3db5..f78895ffab9b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3378,28 +3378,13 @@ static int i915_shared_dplls_info(struct seq_file *m,
void *unused)
static int i915_wa_registers(struct seq_file *m, void *unused)
{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct i915_workarounds *workarounds = &dev_priv->workarounds;
+ struct i915_workarounds *wa = &node_to_i915(m->private)->workarounds;
int i;
- intel_runtime_pm_get(dev_priv);
-
- seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
- for (i = 0; i < workarounds->count; ++i) {
- i915_reg_t addr;
- u32 mask, value, read;
- bool ok;
-
- addr = workarounds->reg[i].addr;
- mask = workarounds->reg[i].mask;
- value = workarounds->reg[i].value;
- read = I915_READ(addr);
- ok = (value & mask) == (read & mask);
- seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status:
%s\n",
- i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" :
"FAIL");
- }
-
- intel_runtime_pm_put(dev_priv);
+ seq_printf(m, "Workarounds applied: %d\n", wa->count);
+ for (i = 0; i < wa->count; ++i)
+ seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
+ wa->reg[i].addr, wa->reg[i].value, wa->reg[i].mask);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2c12de678e32..91c389622217 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1308,7 +1308,7 @@ struct i915_frontbuffer_tracking {
};
struct i915_wa_reg {
- i915_reg_t addr;
+ u32 addr;
u32 value;
/* bitmask representing WA bits */
u32 mask;
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 24b929ce3341..f8bb32e974f6 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -48,29 +48,58 @@
* - Public functions to init or apply the given workaround type.
*/
-static int wa_add(struct drm_i915_private *dev_priv,
- i915_reg_t addr,
- const u32 mask, const u32 val)
+static void wa_add(struct drm_i915_private *i915,
+ i915_reg_t reg, const u32 mask, const u32 val)
{
- const unsigned int idx = dev_priv->workarounds.count;
+ struct i915_workarounds *wa = &i915->workarounds;
+ unsigned int start = 0, end = wa->count;
+ unsigned int addr = i915_mmio_reg_offset(reg);
+ struct i915_wa_reg *r;
+
+ while (start < end) {
+ unsigned int mid = start + (end - start) / 2;
+
+ if (wa->reg[mid].addr < addr) {
+ start = mid + 1;
+ } else if (wa->reg[mid].addr > addr) {
+ end = mid;
+ } else {
+ r = &wa->reg[mid];
+
+ if ((mask & ~r->mask) == 0) {
+ DRM_ERROR("Discarding overwritten w/a for reg %04x
(mask: %08x, value: %08x)\n",
+ addr, r->mask, r->value);
+
+ r->value &= ~mask;
+ }
+
+ r->value |= val;
+ r->mask |= mask;
+ return;
+ }
+ }
- if (WARN_ON(idx >= I915_MAX_WA_
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Keep the ctx workarounds tightly packed
Quoting Oscar Mateo Lozano (2018-06-15 17:01:37) > > > On 6/15/2018 1:59 AM, Chris Wilson wrote: > > For each platform, we have a few registers that rewritten with multiple > > values -- they are not part of a sequence, just different parts of a > > masked register set at different times (e.g. platform and gen > > workarounds). Consolidate these into a single register write to keep the > > table compact. > > > > While adjusting the construction of the wa table, make it non fatal so > > that the driver still loads but keeping the warning and extra details > > for inspection. > > A while ago I sent a patch > (https://patchwork.freedesktop.org/patch/205035/) that uses simple MMIO > writes to apply ctx workarounds. This is possible since we now have > proper golden contexts, and avoids the need for these patches. > It also has the advantage that an improperly classified WA doesn't get > lost (we still need the classification if we want to properly validate > the WAs, but that's a different story). > Are we sure we prefer to do this instead? Short attention span, I was caught up in trying to fix the overflow. So I think I want to keep the checker here that we aren't using conflicting workarounds, and keep the list ordered (because that helps us when reading and checking them). Care to respin? :) Meanwhile, gem_workarounds is still complaining that the write here to _3D_CHICKEN3 isn't sticking. It works locally, and I can't see anything to explain why it wouldn't for CI. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Keep the ctx workarounds tightly packed
On Fri, Jun 15, 2018 at 09:01:37AM -0700, Oscar Mateo Lozano wrote: > > > On 6/15/2018 1:59 AM, Chris Wilson wrote: > > For each platform, we have a few registers that rewritten with multiple > > values -- they are not part of a sequence, just different parts of a > > masked register set at different times (e.g. platform and gen > > workarounds). Consolidate these into a single register write to keep the > > table compact. > > > > While adjusting the construction of the wa table, make it non fatal so > > that the driver still loads but keeping the warning and extra details > > for inspection. > > A while ago I sent a patch > (https://patchwork.freedesktop.org/patch/205035/) that uses simple MMIO > writes to apply ctx workarounds. This is possible since we now have > proper golden contexts, and avoids the need for these patches. > It also has the advantage that an improperly classified WA doesn't get > lost (we still need the classification if we want to properly validate > the WAs, but that's a different story). > Are we sure we prefer to do this instead? Wouldn't that require PSMI+FSM dance to make sure execlist has an active context when you write the regs? Can't see anything like that in the code currently, nor is there anything in the referenced patch. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Keep the ctx workarounds tightly packed
Quoting Ville Syrjälä (2018-06-15 17:19:14) > On Fri, Jun 15, 2018 at 09:01:37AM -0700, Oscar Mateo Lozano wrote: > > > > > > On 6/15/2018 1:59 AM, Chris Wilson wrote: > > > For each platform, we have a few registers that rewritten with multiple > > > values -- they are not part of a sequence, just different parts of a > > > masked register set at different times (e.g. platform and gen > > > workarounds). Consolidate these into a single register write to keep the > > > table compact. > > > > > > While adjusting the construction of the wa table, make it non fatal so > > > that the driver still loads but keeping the warning and extra details > > > for inspection. > > > > A while ago I sent a patch > > (https://patchwork.freedesktop.org/patch/205035/) that uses simple MMIO > > writes to apply ctx workarounds. This is possible since we now have > > proper golden contexts, and avoids the need for these patches. > > It also has the advantage that an improperly classified WA doesn't get > > lost (we still need the classification if we want to properly validate > > the WAs, but that's a different story). > > Are we sure we prefer to do this instead? > > Wouldn't that require PSMI+FSM dance to make sure execlist has > an active context when you write the regs? Can't see anything like that > in the code currently, nor is there anything in the referenced patch. We keep forcewake asserted across the bringup, from before we load the default context until after we have saved the context image. These mmio writes should be saved along with the image. That's the theory at least. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Keep the ctx workarounds tightly packed
On Fri, Jun 15, 2018 at 05:22:40PM +0100, Chris Wilson wrote: > Quoting Ville Syrjälä (2018-06-15 17:19:14) > > On Fri, Jun 15, 2018 at 09:01:37AM -0700, Oscar Mateo Lozano wrote: > > > > > > > > > On 6/15/2018 1:59 AM, Chris Wilson wrote: > > > > For each platform, we have a few registers that rewritten with multiple > > > > values -- they are not part of a sequence, just different parts of a > > > > masked register set at different times (e.g. platform and gen > > > > workarounds). Consolidate these into a single register write to keep the > > > > table compact. > > > > > > > > While adjusting the construction of the wa table, make it non fatal so > > > > that the driver still loads but keeping the warning and extra details > > > > for inspection. > > > > > > A while ago I sent a patch > > > (https://patchwork.freedesktop.org/patch/205035/) that uses simple MMIO > > > writes to apply ctx workarounds. This is possible since we now have > > > proper golden contexts, and avoids the need for these patches. > > > It also has the advantage that an improperly classified WA doesn't get > > > lost (we still need the classification if we want to properly validate > > > the WAs, but that's a different story). > > > Are we sure we prefer to do this instead? > > > > Wouldn't that require PSMI+FSM dance to make sure execlist has > > an active context when you write the regs? Can't see anything like that > > in the code currently, nor is there anything in the referenced patch. > > We keep forcewake asserted across the bringup, from before we load the > default context until after we have saved the context image. These mmio > writes should be saved along with the image. That's the theory at least. Force wake isn't quite enough from what I understand. Or maybe it was that there is at least some delay between forcewake ack asserting and the context actually having been loaded (just my recollection of what Mika's experiments once showed). The spec at least still lists the extra dance for MMIO access into context saved registers. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Apply context workarounds directly
From: Oscar Mateo
Once upon a time, we tried to apply workarounds for registers that lived
inside the context image for every new context. That meant emitting LRI
commands soon after each context was created.
Nowadays, we have a single golden context that gets used as a master
template for future contexts. That golden context will acquire initial
values for its image from the existing values in HW (thanks to inhibit
restore bit). If all WAs are applied normally (i.e. using MMIO writes)
before that happens, they will get soaked up by the golden context and
transmitted correctly to new contexts.
All of this means we don't have to distinguish between context and
non-context WAs anymore, because both can be applied in the same way
(we still want to distinguish them though, because we would like to
check their validity using i-g-t, and that means making sure we have
a context loaded for ctx-residing WAs).
Signed-off-by: Oscar Mateo
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/i915_gem_context.c | 5 -
drivers/gpu/drm/i915/intel_lrc.c | 4 -
drivers/gpu/drm/i915/intel_ringbuffer.c | 4 -
drivers/gpu/drm/i915/intel_workarounds.c | 196 ---
drivers/gpu/drm/i915/intel_workarounds.h | 5 +-
6 files changed, 67 insertions(+), 148 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 977982a987c8..d37f4940276e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5513,6 +5513,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
* FIXME: break up the workarounds and apply them at the right time!
*/
intel_init_clock_gating(dev_priv);
+ intel_ctx_workarounds_apply(dev_priv);
ret = __intel_engines_record_defaults(dev_priv);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index ccf463ab6562..bed77734e7db 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -470,16 +470,11 @@ static bool needs_preempt_context(struct drm_i915_private
*i915)
int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
{
struct i915_gem_context *ctx;
- int ret;
/* Reassure ourselves we are only called once */
GEM_BUG_ON(dev_priv->kernel_context);
GEM_BUG_ON(dev_priv->preempt_context);
- ret = intel_ctx_workarounds_init(dev_priv);
- if (ret)
- return ret;
-
INIT_LIST_HEAD(&dev_priv->contexts.list);
INIT_WORK(&dev_priv->contexts.free_work, contexts_free_worker);
init_llist_head(&dev_priv->contexts.free_list);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 839cb1fc6a01..5517ea5fb3be 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2283,10 +2283,6 @@ static int gen8_init_rcs_context(struct i915_request *rq)
{
int ret;
- ret = intel_ctx_workarounds_emit(rq);
- if (ret)
- return ret;
-
ret = intel_rcs_context_init_mocs(rq);
/*
* Failing to program the MOCS is non-fatal.The system will not
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ef3c76425843..9f4781109c12 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -601,10 +601,6 @@ static int intel_rcs_ctx_init(struct i915_request *rq)
{
int ret;
- ret = intel_ctx_workarounds_emit(rq);
- if (ret != 0)
- return ret;
-
ret = i915_gem_render_state_emit(rq);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index f8bb32e974f6..aa534b364b30 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -48,14 +48,16 @@
* - Public functions to init or apply the given workaround type.
*/
-static void wa_add(struct drm_i915_private *i915,
+static void wa_add(struct drm_i915_private *dev_priv,
i915_reg_t reg, const u32 mask, const u32 val)
{
- struct i915_workarounds *wa = &i915->workarounds;
+ struct i915_workarounds *wa = &dev_priv->workarounds;
unsigned int start = 0, end = wa->count;
unsigned int addr = i915_mmio_reg_offset(reg);
struct i915_wa_reg *r;
+ I915_WRITE(reg, val);
+
while (start < end) {
unsigned int mid = start + (end - start) / 2;
@@ -110,7 +112,7 @@ static void wa_add(struct drm_i915_private *i915,
#define WA_SET_FIELD_MASKED(addr, mask, value) \
WA_REG(addr, (mask), _MASKED_FIELD(mask, value))
-static int gen8_ctx_workarounds_init(struct drm_i915_private *dev_priv)
+static void gen8_ctx_workarounds_apply(stru
[Intel-gfx] [PATCH 1/2] drm/i915: Apply context workarounds directly
From: Oscar Mateo
Once upon a time, we tried to apply workarounds for registers that lived
inside the context image for every new context. That meant emitting LRI
commands soon after each context was created.
Nowadays, we have a single golden context that gets used as a master
template for future contexts. That golden context will acquire initial
values for its image from the existing values in HW (thanks to inhibit
restore bit). If all WAs are applied normally (i.e. using MMIO writes)
before that happens, they will get soaked up by the golden context and
transmitted correctly to new contexts.
All of this means we don't have to distinguish between context and
non-context WAs anymore, because both can be applied in the same way
(we still want to distinguish them though, because we would like to
check their validity using i-g-t, and that means making sure we have
a context loaded for ctx-residing WAs).
Signed-off-by: Oscar Mateo
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/i915_gem_context.c | 5 -
drivers/gpu/drm/i915/intel_lrc.c | 4 -
drivers/gpu/drm/i915/intel_ringbuffer.c | 4 -
drivers/gpu/drm/i915/intel_workarounds.c | 196 ---
drivers/gpu/drm/i915/intel_workarounds.h | 5 +-
6 files changed, 67 insertions(+), 148 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 977982a987c8..d37f4940276e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5513,6 +5513,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
* FIXME: break up the workarounds and apply them at the right time!
*/
intel_init_clock_gating(dev_priv);
+ intel_ctx_workarounds_apply(dev_priv);
ret = __intel_engines_record_defaults(dev_priv);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index ccf463ab6562..bed77734e7db 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -470,16 +470,11 @@ static bool needs_preempt_context(struct drm_i915_private
*i915)
int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
{
struct i915_gem_context *ctx;
- int ret;
/* Reassure ourselves we are only called once */
GEM_BUG_ON(dev_priv->kernel_context);
GEM_BUG_ON(dev_priv->preempt_context);
- ret = intel_ctx_workarounds_init(dev_priv);
- if (ret)
- return ret;
-
INIT_LIST_HEAD(&dev_priv->contexts.list);
INIT_WORK(&dev_priv->contexts.free_work, contexts_free_worker);
init_llist_head(&dev_priv->contexts.free_list);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 839cb1fc6a01..5517ea5fb3be 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2283,10 +2283,6 @@ static int gen8_init_rcs_context(struct i915_request *rq)
{
int ret;
- ret = intel_ctx_workarounds_emit(rq);
- if (ret)
- return ret;
-
ret = intel_rcs_context_init_mocs(rq);
/*
* Failing to program the MOCS is non-fatal.The system will not
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ef3c76425843..9f4781109c12 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -601,10 +601,6 @@ static int intel_rcs_ctx_init(struct i915_request *rq)
{
int ret;
- ret = intel_ctx_workarounds_emit(rq);
- if (ret != 0)
- return ret;
-
ret = i915_gem_render_state_emit(rq);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index f8bb32e974f6..aa534b364b30 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -48,14 +48,16 @@
* - Public functions to init or apply the given workaround type.
*/
-static void wa_add(struct drm_i915_private *i915,
+static void wa_add(struct drm_i915_private *dev_priv,
i915_reg_t reg, const u32 mask, const u32 val)
{
- struct i915_workarounds *wa = &i915->workarounds;
+ struct i915_workarounds *wa = &dev_priv->workarounds;
unsigned int start = 0, end = wa->count;
unsigned int addr = i915_mmio_reg_offset(reg);
struct i915_wa_reg *r;
+ I915_WRITE(reg, val);
+
while (start < end) {
unsigned int mid = start + (end - start) / 2;
@@ -110,7 +112,7 @@ static void wa_add(struct drm_i915_private *i915,
#define WA_SET_FIELD_MASKED(addr, mask, value) \
WA_REG(addr, (mask), _MASKED_FIELD(mask, value))
-static int gen8_ctx_workarounds_init(struct drm_i915_private *dev_priv)
+static void gen8_ctx_workarounds_apply(stru
[Intel-gfx] [PATCH 2/2] drm/i915: Enable provoking vertex fix on Gen9+ systems.
From: Kenneth Graunke
The SF and clipper units mishandle the provoking vertex in some cases,
which can cause misrendering with shaders that use flat shaded inputs.
There are chicken bits in 3D_CHICKEN3 (for SF) and FF_SLICE_CHICKEN
(for the clipper) that work around the issue. These registers are
unfortunately not part of the logical context (even the power context).
This patch sets both bits, and bumps the number of allowed workaround
registers to avoid running out of space (thanks to Chris Wilson for
helping debug that issue).
I am not aware of any workaround names or numbers assigned for these
issues, they're simply recommended in the documentation for each of
the registers.
Bugzilla: https://bugs.freedesktop.org/103047
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b8c0ebd50889..54ec7ab57ce8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2432,12 +2432,17 @@ enum i915_power_well_id {
#define _3D_CHICKEN_MMIO(0x2084)
#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
#define _3D_CHICKEN2 _MMIO(0x208c)
+
+#define FF_SLICE_CHICKEN _MMIO(0x2088)
+#define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1)
+
/* Disables pipelining of read flushes past the SF-WIZ interface.
* Required on all Ironlake steppings according to the B-Spec, but the
* particular danger of not doing so is not specified.
*/
# define _3D_CHICKEN2_WM_READ_PIPELINED(1 << 14)
#define _3D_CHICKEN3 _MMIO(0x2090)
+#define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12)
#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL(1 << 10)
#define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5)
#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index aa534b364b30..0ccbd42962f3 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -296,6 +296,12 @@ static void gen9_ctx_workarounds_apply(struct
drm_i915_private *dev_priv)
/* WaClearHIZ_WM_CHICKEN3:bxt,glk */
if (IS_GEN9_LP(dev_priv))
WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
+
+ /* BSpec: 11391 */
+ WA_SET_BIT_MASKED(FF_SLICE_CHICKEN,
+ FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX);
+ /* BSpec: 11299 */
+ WA_SET_BIT_MASKED(_3D_CHICKEN3, _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX);
}
static void skl_tune_iz_hashing(struct drm_i915_private *dev_priv)
--
2.17.1
___
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