[Intel-gfx] ✗ Fi.CI.BAT: warning for YCBCR 4:2:0 support for LSPCON
== Series Details == Series: YCBCR 4:2:0 support for LSPCON URL : https://patchwork.freedesktop.org/series/28536/ State : warning == Summary == Series 28536v1 YCBCR 4:2:0 support for LSPCON https://patchwork.freedesktop.org/api/1.0/series/28536/revisions/1/mbox/ Test gem_exec_suspend: Subgroup basic-s3: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-s4-devices: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Test kms_busy: Subgroup basic-flip-a: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-b: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-c: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: pass -> DMESG-WARN (fi-skl-6770hq) fdo#100215 +3 pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-busy-flip-before-cursor-legacy: pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-after-cursor-atomic: pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-after-cursor-legacy: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-after-cursor-varying-size: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-before-cursor-atomic: pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-before-cursor-legacy: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-before-cursor-varying-size: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Test kms_flip: Subgroup basic-flip-vs-dpms: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-vs-modeset: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-vs-wf_vblank: pass -> DMESG-WARN (fi-skl-6770hq) fdo#99739 pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-plain-flip: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Test kms_frontbuffer_tracking: Subgroup basic: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Test kms_pipe_crc_basic: Subgroup hang-read-crc-pipe-a: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup hang-read-crc-pipe-b: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup hang-read-crc-pipe-c: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup nonblocking-crc-pipe-a: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup nonblocking-crc-pipe-a-frame-sequence: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup nonblocking-crc-pipe-b: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup nonblocking-crc-pipe-b-frame-sequence: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup nonblocking-crc-pipe-c: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup nonblocking-crc-pipe-c-frame-sequence: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup read-crc-pipe-a: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup read-crc-pipe-a-frame-sequence: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup read-crc-pipe-b: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup read-crc-pipe-b-frame-sequence: pass -
Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for YCBCR 4:2:0 support for LSPCON
These failure are from Parade based LSPCON's, where the delay is not yet fine tuned: [ 197.761072] [drm:lspcon_write_infoframe [i915]] *ERROR* LSPCON FW not ready for infoframes [ 197.761100] [drm:lspcon_write_infoframe [i915]] *ERROR* Failed to write AVI infoframes Regards Shashank -Original Message- From: Patchwork [mailto:patchw...@emeril.freedesktop.org] Sent: Wednesday, August 9, 2017 12:35 PM To: Sharma, Shashank Cc: intel-gfx@lists.freedesktop.org Subject: ✗ Fi.CI.BAT: warning for YCBCR 4:2:0 support for LSPCON == Series Details == Series: YCBCR 4:2:0 support for LSPCON URL : https://patchwork.freedesktop.org/series/28536/ State : warning == Summary == Series 28536v1 YCBCR 4:2:0 support for LSPCON https://patchwork.freedesktop.org/api/1.0/series/28536/revisions/1/mbox/ Test gem_exec_suspend: Subgroup basic-s3: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-s4-devices: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Test kms_busy: Subgroup basic-flip-a: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-b: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-c: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: pass -> DMESG-WARN (fi-skl-6770hq) fdo#100215 +3 pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-busy-flip-before-cursor-legacy: pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-after-cursor-atomic: pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-after-cursor-legacy: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-after-cursor-varying-size: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-before-cursor-atomic: pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-before-cursor-legacy: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-before-cursor-varying-size: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Test kms_flip: Subgroup basic-flip-vs-dpms: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-vs-modeset: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-flip-vs-wf_vblank: pass -> DMESG-WARN (fi-skl-6770hq) fdo#99739 pass -> DMESG-WARN (fi-kbl-7500u) Subgroup basic-plain-flip: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Test kms_frontbuffer_tracking: Subgroup basic: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Test kms_pipe_crc_basic: Subgroup hang-read-crc-pipe-a: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup hang-read-crc-pipe-b: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup hang-read-crc-pipe-c: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup nonblocking-crc-pipe-a: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup nonblocking-crc-pipe-a-frame-sequence: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup nonblocking-crc-pipe-b: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup nonblocking-crc-pipe-b-frame-sequence: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup nonblocking-crc-pipe-c: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kbl-7500u) Subgroup nonblocking-crc-pipe-c-frame-sequence: pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-kb
Re: [Intel-gfx] [PATCH v13 5/7] vfio: ABI for mdev display dma-buf operation
> -Original Message- > From: intel-gvt-dev [mailto:intel-gvt-dev-boun...@lists.freedesktop.org] On > Behalf Of Alex Williamson > Sent: Tuesday, August 8, 2017 1:43 AM > To: Zhang, Tina > Cc: Tian, Kevin ; intel-gfx@lists.freedesktop.org; dri- > de...@lists.freedesktop.org; kwankh...@nvidia.com; kra...@redhat.com; > intel-gvt-...@lists.freedesktop.org; Wang, Zhi A ; Lv, > Zhiyuan > Subject: Re: [PATCH v13 5/7] vfio: ABI for mdev display dma-buf operation > > On Mon, 7 Aug 2017 08:11:43 + > "Zhang, Tina" wrote: > > > After going through the previous discussions, here are some summaries may > be related to the current discussion: > > 1. How does user mode figure the device capabilities between region and > dma-buf? > > VFIO_DEVICE_GET_REGION_INFO could tell if the mdev supports region case. > > Otherwise, the mdev supports dma-buf. > > Why do we need to make this assumption? What happens when dma-buf is > superseded? What happens if a device supports both dma-buf and regions? > We have a flags field in vfio_device_gfx_plane_info, doesn't it make sense to > use > it to identify which field, between region_index and fd, is valid? We could > even > put region_index and fd into a union with the flag bits indicating how to > interpret the union, but I'm not sure everyone was onboard with this idea. > Seems like a waste of 4 bytes not to do that though. It seems we discussed this idea before: https://lists.freedesktop.org/archives/intel-gvt-dev/2017-June/001304.html https://lists.freedesktop.org/archives/intel-gvt-dev/2017-June/001333.html Thanks. Tina > > Thinking further, is the user ever in a situation where they query the > graphics > plane info and can handle either a dma-buf or a region? It seems more likely > that the user needs to know early on which is supported and would then require > that they continue to see compatible plane information... Should the user > then > be able to specify whether they want a dma-buf or a region? Perhaps these > flag > bits are actually input and the return should be -errno if the driver cannot > produce something compatible. From the previously discussion, it seems user space workflow will look quite different for these two cases. So once user space finds out which case is supported, it just uses that case, and won't change it. Meanwhile, I'm not sure whether there will be a mdev would like to support both region and dma-buf cases. In my opinion, either region or dma-buf is supported by one mdev. (Yeah, agree, there may be other cases in future) It's like we want to propose a general interface used to share guest's buffer with host. And the general interface, so far, has two choice: region and dma-buf. So each mdev likes this interface can implement one kind of it and gets the benefit from the general interface. So, if we think about this, the difference in user mode should be as little as possible. Thanks. Tina > > Maybe we'd therefore define 3 flag bits: PROBE, DMABUF, REGION. In this > initial implementation, DMABUF or REGION would always be set by the user to > request that type of interface. Additionally, the QUERY bit could be set to > probe > compatibility, thus if PROBE and REGION are set, the vendor driver would > return > success only if it supports the region based interface. If PROBE and DMABUF > are > set, the vendor driver returns success only if the dma-buf based interface is > supported. The value of the remainder of the structure is undefined for > PROBE. > Additionally setting both DMABUF and REGION is invalid. Undefined flags bits > must be validated as zero by the drivers for future use (thus if we later > define > DMABUFv2, an older driver should automatically return -errno when probed or > requested). > > It seems like this handles all the cases, the user can ask what's supported > and > specifies the interface they want on every call. The user therefore can also > choose between region_index and fd and we can make that a union. Agree, that's a good proposal, which can handle all the cases. I'm just not sure about the usage case of "on every call". In previous discussion, it seems we think static is enough. Thanks. Tina > > > 2. For dma-buf, how to differentiate unsupported vs not initialized? > > For dma-buf, when the mdev doesn't support some arguments, -EINVAL will > be returned. And -errno will return when meeting other failures, like -ENOMEM. > > If the mdev is not initialized, there won't be any returned err. Just zero > > all the > fields in structure vfio_device_gfx_plane_info. > > So we're relying on special values again :-\ For which fields is zero not a > valid > value? I prefer the probe interface above unless there are better ideas. > > > 3. The id field in structure vfio_device_gfx_plane_info So far we > > haven't figured out the usage of this field for dma-buf usage. So, this > > field is > changed to "region_index" and only used for region usage. > > In previous discussio
Re: [Intel-gfx] [PATCH 3/8] drm/i915/gen10: Calculate and enable transition WM
Op 18-07-17 om 14:49 schreef Mahesh Kumar:
> From: "Kumar, Mahesh"
>
> GEN > 9 require transition WM to be programmed if IPC is enabled.
> This patch calculates & enable transition WM for supported platforms.
> If transition WM is enabled, Plane read requests are sent at high
> priority until filling above the transition watermark, then the
> requests are sent at lower priority until dropping below the level-0 WM.
> The lower priority requests allow other memory clients to have better
> memory access.
>
> transition minimum is the minimum amount needed for trans_wm to work to
> ensure the demote does not happen before enough data has been read to
> meet the level 0 watermark requirements.
>
> transition amount is configurable value. Higher values will
> tend to cause longer periods of high priority reads followed by longer
> periods of lower priority reads. Tuning to lower values will tend to
> cause shorter periods of high and lower priority reads.
>
> Keeping transition amount to 10 in this patch, as suggested by HW team.
>
> Signed-off-by: Mahesh Kumar
> Acked-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_pm.c | 51
> +++--
> 1 file changed, 49 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b2bd65847d9b..9a2ed1b734d5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4579,12 +4579,55 @@ skl_compute_linetime_wm(struct intel_crtc_state
> *cstate)
> }
>
> static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
> + struct skl_wm_params *wp,
> + struct skl_wm_level *wm_l0,
> + uint16_t ddb_allocation,
> struct skl_wm_level *trans_wm /* out */)
> {
> + struct drm_device *dev = cstate->base.crtc->dev;
> + const struct drm_i915_private *dev_priv = to_i915(dev);
> + uint16_t trans_min, trans_y_tile_min;
> + uint16_t trans_amount = 10; /* This is configurable amount */
should probably be a const since it's a tweakable.
> + uint16_t trans_offset_b, res_blocks;
> +
> if (!cstate->base.active)
> + goto exit;
> +
> + /* Transition WM are not recommended by HW team for GEN9 */
> + if (INTEL_GEN(dev_priv) <= 9)
> + goto exit;
> +
> + /* Transition WM don't make any sense if ipc is disabled */
> + if (!dev_priv->ipc_enabled)
> + goto exit;
> +
> + if (INTEL_GEN(dev_priv) >= 10)
> + trans_min = 4;
> +
> + trans_offset_b = trans_min + trans_amount;
> + trans_y_tile_min = (uint16_t) mul_round_up_u32_fixed16(2,
> + wp->y_tile_minimum);
> +
> + if (wp->y_tiled) {
> + res_blocks = max(wm_l0->plane_res_b, trans_y_tile_min) +
> + trans_offset_b;
Perhaps only calculate trans_y_tile_min if y-tiled?
> + } else {
> + res_blocks = wm_l0->plane_res_b + trans_offset_b;
> + }
> +
> + res_blocks += 1;
> +
> + /* WA BUG:1938466 add one block for non y-tile planes */
> + if (!wp->y_tiled && IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
> + res_blocks += 1;
Could be added to the !y_tiled branch?
Patch looks sane though, and seems to match bspec exactly. I couldn't find the
value for trans_amount, but I'll take your word it's the right one. :)
With the minor fixes:
Reviewed-by: Maarten Lankhorst
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Re: [Intel-gfx] [PATCH] drm/i915: Clear lost context-switch interrupts across reset
Quoting Dong, Chuanxiao (2017-08-09 01:26:00)
> > -Original Message-
> > From: Thierry, Michel
> > Sent: Tuesday, August 8, 2017 1:40 AM
> > To: Chris Wilson ; intel-gfx@lists.freedesktop.org
> > Cc: Dong, Chuanxiao ; Ursulin, Tvrtko
> > ; Winiarski, Michal
> > Subject: Re: [PATCH] drm/i915: Clear lost context-switch interrupts across
> > reset
> >
> > On 8/7/2017 5:19 AM, Chris Wilson wrote:
> > > During a global reset, we disable the irq. As we disable the irq, the
> > > hardware may be raising a GT interrupt that we then ignore, leaving it
> > > pending in the GTIIR. After the reset, we then re-enable the irq,
> > > triggering the pending interrupt. However, that interrupt was for the
> > > stale state from before the reset, and the contents of the CSB buffer
> > > are now invalid.
> > >
> > > Reported-by: "Dong, Chuanxiao"
> > > Signed-off-by: Chris Wilson
> > > Cc: "Dong, Chuanxiao"
> > > Cc: Tvrtko Ursulin
> > > Cc: Michal Winiarski
> > > Cc: Michel Thierry
> > > ---
> > > drivers/gpu/drm/i915/intel_lrc.c | 17 -
> > > 1 file changed, 16 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> > > b/drivers/gpu/drm/i915/intel_lrc.c
> > > index b0738d2b2a7f..bc61948e2601 100644
> > > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > > @@ -1221,6 +1221,14 @@ static int intel_init_workaround_bb(struct
> > intel_engine_cs *engine)
> > > return ret;
> > > }
> > >
> > > +static u8 gtiir[] = {
> > > + [RCS] = 0,
> > > + [BCS] = 0,
> > > + [VCS] = 1,
> > > + [VCS2] = 1,
> > > + [VECS] = 3,
> > > +};
> > > +
> > > static int gen8_init_common_ring(struct intel_engine_cs *engine)
> > > {
> > > struct drm_i915_private *dev_priv = engine->i915; @@ -1245,9
> > > +1253,16 @@ static int gen8_init_common_ring(struct intel_engine_cs
> > > *engine)
> > >
> > > DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
> > >
> > > - /* After a GPU reset, we may have requests to replay */
> > > + GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
> > > +
> > > + /* Clear any pending interrupt state */
> > > + I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
> > > + GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift);
> > > + I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
> > > + GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift);
> >
> > Clear twice? Or the second was supposed to be user_interrupt?
I never know which of the IIR are double buffered, so in case they
decide to double buffer GTIIR, I cleared it twice.
We do want to service the user_interrupt even after the hang in case we
don't notify it during reset processing. Might be worth kicking the
engine just in case, but we have contingency plans.
-Chris
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] lib: Add hooks for enabling ftrace
On Tue, Aug 08, 2017 at 02:46:51PM +, Patchwork wrote: > PASS: igt_list_only > XFAIL: igt_no_exit_list_only > XFAIL: igt_no_subtest > FAIL: igt_simulation > XFAIL: igt_no_exit > FAIL: igt_segfault > PASS: igt_fork_helper > FAIL: igt_exit_handler > XFAIL: igt_simple_test_subtests > FAIL: igt_hdmi_inject > FAIL: igt_stats > XFAIL: igt_timeout > XFAIL: igt_invalid_subtest_name > FAIL: igt_assert > FAIL: igt_subtest_group > > Testsuite summary for intel-gpu-tools 1.19 > > # TOTAL: 15 > # PASS: 2 > # SKIP: 0 > # XFAIL: 6 > # FAIL: 7 > # XPASS: 0 > # ERROR: 0 Can't reproduce this locally. > > See lib/tests/test-suite.log Changes are underway to have this dumped into the output for pw failures. -- Petri Latvala ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] tests/kms_flip: Remove $engine-flip-vs-dpms/modeset
This is already tested in kms_busy, and without cs flips there's no
point in doing those tests any more.
Signed-off-by: Maarten Lankhorst
---
tests/kms_flip.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/tests/kms_flip.c b/tests/kms_flip.c
index ede5fd2ba9c5..ea860e191a67 100644
--- a/tests/kms_flip.c
+++ b/tests/kms_flip.c
@@ -755,13 +755,8 @@ static unsigned int run_test_step(struct test_output *o)
if (o->flags & TEST_MODESET)
igt_assert(set_mode(o, o->fb_ids[o->current_fb_id], 0, 0) == 0);
- if (o->flags & TEST_DPMS) {
- if (spin_rcs)
- igt_spin_batch_set_timeout(spin_rcs, NSEC_PER_SEC);
- if (spin_bcs)
- igt_spin_batch_set_timeout(spin_bcs, NSEC_PER_SEC);
+ if (o->flags & TEST_DPMS)
set_dpms(o, DRM_MODE_DPMS_ON);
- }
if (o->flags & TEST_VBLANK_RACE) {
struct vblank_reply reply;
@@ -1592,14 +1587,10 @@ int main(int argc, char **argv)
"plain-flip-fb-recreate" },
{ 30, TEST_FLIP | TEST_RMFB | TEST_MODESET , "flip-vs-rmfb" },
{ 20, TEST_FLIP | TEST_DPMS | TEST_EINVAL | TEST_BASIC,
"flip-vs-dpms" },
- { 60, TEST_FLIP | TEST_DPMS | TEST_WITH_DUMMY_BCS,
"blt-flip-vs-dpms" },
- { 60, TEST_FLIP | TEST_DPMS | TEST_WITH_DUMMY_RCS,
"render-flip-vs-dpms" },
{ 30, TEST_FLIP | TEST_PAN, "flip-vs-panning" },
{ 60, TEST_FLIP | TEST_PAN | TEST_WITH_DUMMY_BCS,
"blt-flip-vs-panning" },
{ 60, TEST_FLIP | TEST_PAN | TEST_WITH_DUMMY_RCS,
"render-flip-vs-panning" },
{ 20, TEST_FLIP | TEST_MODESET | TEST_EINVAL | TEST_BASIC,
"flip-vs-modeset" },
- { 60, TEST_FLIP | TEST_MODESET | TEST_WITH_DUMMY_BCS,
"blt-flip-vs-modeset" },
- { 60, TEST_FLIP | TEST_MODESET | TEST_WITH_DUMMY_RCS,
"render-flip-vs-modeset" },
{ 30, TEST_FLIP | TEST_VBLANK_EXPIRED_SEQ,
"flip-vs-expired-vblank" },
--
2.11.0
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Re: [Intel-gfx] [PATCH igt] tools/null_state_gen: Don't upload color calc and depth stencil on gen6
Chris Wilson writes: > Quoting Mika Kuoppala (2017-08-08 14:36:59) >> Mika Kuoppala writes: >> >> > We were pointing the color calc and depth stencil states blindly >> > to an offset of 1k from bb start. This was foolhardy as it collides >> > with other state in the batch and results in a wrecked state upload. >> > >> > Chris noticed that with snb gt1, it takes 10 seconds for renderstate batch >> > to complete. However pointing the states to a known valid 64 aligned >> > zero blocks didn't work to reduce the upload time either. >> > >> > Cave in and omit uploading color calc and depth stencil states. >> >> Not just yet, ignore this patch. > > Right, we found the root cause for my issue, so we can actually load the > correct state here (i.e. create a NUL block and point both depth-stencil > and color-calc to it). We could use that same block for the blend state > as well, etc. I chose to keep the blend state as is, for the first step. As the blend state is is not all zeros. But after the patch to add cc and depth stencil states as null, it is a minor step, as in code, to nullify the blend state also. -Mika > -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt] tools/null_state_gen: Add proper color calc and depth stencil states
We were just pointing these states blindly into the 1k offset
in the bb. Make a suitable sized and aligned null block and
point both indirect state pointers to that block.
v2: move blend state generation into the same function
Reported-by: Chris Wilson
Signed-off-by: Mika Kuoppala
---
tools/null_state_gen/intel_renderstate_gen6.c | 64 ---
1 file changed, 39 insertions(+), 25 deletions(-)
diff --git a/tools/null_state_gen/intel_renderstate_gen6.c
b/tools/null_state_gen/intel_renderstate_gen6.c
index 5c1b7f97..1aa97d39 100644
--- a/tools/null_state_gen/intel_renderstate_gen6.c
+++ b/tools/null_state_gen/intel_renderstate_gen6.c
@@ -216,13 +216,46 @@ gen6_emit_invariant(struct intel_batchbuffer *batch)
OUT_BATCH(1);
}
+static uint32_t
+gen6_create_cc_blend(struct intel_batchbuffer *batch)
+{
+ struct gen6_blend_state blend;
+
+ memset(&blend, 0, sizeof(blend));
+
+ blend.blend0.dest_blend_factor = GEN6_BLENDFACTOR_ZERO;
+ blend.blend0.source_blend_factor = GEN6_BLENDFACTOR_ONE;
+ blend.blend0.blend_func = GEN6_BLENDFUNCTION_ADD;
+ blend.blend0.blend_enable = 1;
+
+ blend.blend1.post_blend_clamp_enable = 1;
+ blend.blend1.pre_blend_clamp_enable = 1;
+
+ return OUT_STATE_STRUCT(blend, 64);
+}
+
static void
-gen6_emit_cc(struct intel_batchbuffer *batch, uint32_t blend)
+gen6_emit_cc(struct intel_batchbuffer *batch)
{
+ struct null_blk_s {
+ union {
+ struct gen6_depth_stencil_state s_state;
+ struct gen6_color_calc_state c_state;
+ };
+ } null_block;
+ uint32_t null_block_offset, blend_offset;
+
+ memset(&null_block, 0, sizeof(null_block));
+
+ blend_offset = gen6_create_cc_blend(batch);
+ null_block_offset = OUT_STATE_STRUCT(null_block, 64);
+
OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
- OUT_BATCH_STATE_OFFSET(blend | 1);
- OUT_BATCH(1024 | 1);
- OUT_BATCH(1024 | 1);
+ OUT_BATCH_STATE_OFFSET(blend_offset | 1);
+ /* color calc state */
+ OUT_BATCH_STATE_OFFSET(null_block_offset | 1);
+ /* depth stencil state */
+ OUT_BATCH_STATE_OFFSET(null_block_offset | 1);
}
static void
@@ -354,24 +387,6 @@ gen6_create_cc_viewport(struct intel_batchbuffer *batch)
}
static uint32_t
-gen6_create_cc_blend(struct intel_batchbuffer *batch)
-{
- struct gen6_blend_state blend;
-
- memset(&blend, 0, sizeof(blend));
-
- blend.blend0.dest_blend_factor = GEN6_BLENDFACTOR_ZERO;
- blend.blend0.source_blend_factor = GEN6_BLENDFACTOR_ONE;
- blend.blend0.blend_func = GEN6_BLENDFUNCTION_ADD;
- blend.blend0.blend_enable = 1;
-
- blend.blend1.post_blend_clamp_enable = 1;
- blend.blend1.pre_blend_clamp_enable = 1;
-
- return OUT_STATE_STRUCT(blend, 64);
-}
-
-static uint32_t
gen6_create_kernel(struct intel_batchbuffer *batch)
{
return intel_batch_state_copy(batch, ps_kernel_nomask_affine,
@@ -463,7 +478,7 @@ static void gen6_emit_vertex_buffer(struct
intel_batchbuffer *batch)
void gen6_setup_null_render_state(struct intel_batchbuffer *batch)
{
uint32_t wm_state, wm_kernel, wm_table;
- uint32_t cc_vp, cc_blend;
+ uint32_t cc_vp;
wm_table = gen6_bind_surfaces(batch);
wm_kernel = gen6_create_kernel(batch);
@@ -472,7 +487,6 @@ void gen6_setup_null_render_state(struct intel_batchbuffer
*batch)
SAMPLER_EXTEND_NONE);
cc_vp = gen6_create_cc_viewport(batch);
- cc_blend = gen6_create_cc_blend(batch);
gen6_emit_invariant(batch);
gen6_emit_state_base_address(batch);
@@ -488,7 +502,7 @@ void gen6_setup_null_render_state(struct intel_batchbuffer
*batch)
gen6_emit_null_depth_buffer(batch);
gen6_emit_drawing_rectangle(batch);
- gen6_emit_cc(batch, cc_blend);
+ gen6_emit_cc(batch);
gen6_emit_sampler(batch, wm_state);
gen6_emit_sf(batch);
gen6_emit_wm(batch, wm_kernel);
--
2.11.0
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Re: [Intel-gfx] [PATCH 8/8] drm/i915/skl+: debugfs entry to control IPC
Op 18-07-17 om 14:49 schreef Mahesh Kumar:
> From: "Kumar, Mahesh"
>
> This patch creates an entry in debugfs to check the status of IPC.
> This can also be used to enable/disable IPC in supported platforms.
>
> Signed-off-by: Mahesh Kumar
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 73
> -
> 1 file changed, 72 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 2ef75c1a6119..368f64de0fdc 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3592,6 +3592,76 @@ static int i915_wa_registers(struct seq_file *m, void
> *unused)
> return 0;
> }
>
> +static int i915_ipc_status_show(struct seq_file *m, void *data)
> +{
> + struct drm_i915_private *dev_priv = m->private;
> +
> + seq_printf(m, "Isochronous Priority Control: %s\n",
> + enableddisabled(dev_priv->ipc_enabled));
> + return 0;
> +}
> +
> +static int i915_ipc_status_open(struct inode *inode, struct file *file)
> +{
> + struct drm_i915_private *dev_priv = inode->i_private;
> +
> + if (HAS_IPC(dev_priv))
> + return -ENODEV;
I take it you didn't test this version of the patch? :p
> +
> + return single_open(file, i915_ipc_status_show, dev_priv);
> +}
> +
> +static ssize_t i915_ipc_status_write(struct file *file, const char __user
> *ubuf,
> + size_t len, loff_t *offp)
> +{
> + struct seq_file *m = file->private_data;
> + struct drm_i915_private *dev_priv = m->private;
> + char *newline;
> + char tmp[16];
> + bool enable;
> +
> + if (HAS_IPC(dev_priv))
> + return -ENODEV;
Again, though I would remove this check since you already test in open().
> + if (len >= sizeof(tmp))
> + return -EINVAL;
> +
> + if (copy_from_user(tmp, ubuf, len))
> + return -EFAULT;
> +
> + tmp[len] = '\0';
> +
> + /* Strip newline, if any */
> + newline = strchr(tmp, '\n');
> + if (newline)
> + *newline = '\0';
> +
> + if (strcmp(tmp, "0") == 0 || strcmp(tmp, "disable") == 0 ||
> + strcmp(tmp, "off") == 0 || strcmp(tmp, "dis") == 0)
> + enable = false;
> + else if (strcmp(tmp, "1") == 0 || strcmp(tmp, "enable") == 0 ||
> + strcmp(tmp, "on") == 0 || strcmp(tmp, "en") == 0)
> + enable = true;
> + else
> + return -EINVAL;
Maybe replace with kstrtobool_from_user, and use yesno for ipc_enabled in
show()? That way you won't have to do all these special cases here. :)
> +
> + intel_runtime_pm_get(dev_priv);
> + dev_priv->ipc_enabled = enable;
> + intel_enable_ipc(dev_priv);
> + intel_runtime_pm_put(dev_priv);
> +
> + return len;
> +}
> +
> +static const struct file_operations i915_ipc_status_fops = {
> + .owner = THIS_MODULE,
> + .open = i915_ipc_status_open,
> + .read = seq_read,
> + .llseek = seq_lseek,
> + .release = single_release,
> + .write = i915_ipc_status_write
> +};
> +
> static int i915_ddb_info(struct seq_file *m, void *unused)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> @@ -4929,7 +4999,8 @@ static const struct i915_debugfs_files {
> {"i915_dp_test_type", &i915_displayport_test_type_fops},
> {"i915_dp_test_active", &i915_displayport_test_active_fops},
> {"i915_guc_log_control", &i915_guc_log_control_fops},
> - {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}
> + {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
> + {"i915_ipc_status", &i915_ipc_status_fops}
> };
>
> int i915_debugfs_register(struct drm_i915_private *dev_priv)
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Re: [Intel-gfx] [PATCH 8/8] drm/i915/skl+: debugfs entry to control IPC
Op 18-07-17 om 14:49 schreef Mahesh Kumar:
> From: "Kumar, Mahesh"
>
> This patch creates an entry in debugfs to check the status of IPC.
> This can also be used to enable/disable IPC in supported platforms.
>
> Signed-off-by: Mahesh Kumar
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 73
> -
> 1 file changed, 72 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 2ef75c1a6119..368f64de0fdc 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3592,6 +3592,76 @@ static int i915_wa_registers(struct seq_file *m, void
> *unused)
> return 0;
> }
>
> +static int i915_ipc_status_show(struct seq_file *m, void *data)
> +{
> + struct drm_i915_private *dev_priv = m->private;
> +
> + seq_printf(m, "Isochronous Priority Control: %s\n",
> + enableddisabled(dev_priv->ipc_enabled));
> + return 0;
> +}
> +
> +static int i915_ipc_status_open(struct inode *inode, struct file *file)
> +{
> + struct drm_i915_private *dev_priv = inode->i_private;
> +
> + if (HAS_IPC(dev_priv))
> + return -ENODEV;
> +
> + return single_open(file, i915_ipc_status_show, dev_priv);
> +}
> +
> +static ssize_t i915_ipc_status_write(struct file *file, const char __user
> *ubuf,
> + size_t len, loff_t *offp)
> +{
> + struct seq_file *m = file->private_data;
> + struct drm_i915_private *dev_priv = m->private;
> + char *newline;
> + char tmp[16];
> + bool enable;
> +
> + if (HAS_IPC(dev_priv))
> + return -ENODEV;
> +
> + if (len >= sizeof(tmp))
> + return -EINVAL;
> +
> + if (copy_from_user(tmp, ubuf, len))
> + return -EFAULT;
> +
> + tmp[len] = '\0';
> +
> + /* Strip newline, if any */
> + newline = strchr(tmp, '\n');
> + if (newline)
> + *newline = '\0';
> +
> + if (strcmp(tmp, "0") == 0 || strcmp(tmp, "disable") == 0 ||
> + strcmp(tmp, "off") == 0 || strcmp(tmp, "dis") == 0)
> + enable = false;
> + else if (strcmp(tmp, "1") == 0 || strcmp(tmp, "enable") == 0 ||
> + strcmp(tmp, "on") == 0 || strcmp(tmp, "en") == 0)
> + enable = true;
> + else
> + return -EINVAL;
> +
> + intel_runtime_pm_get(dev_priv);
> + dev_priv->ipc_enabled = enable;
> + intel_enable_ipc(dev_priv);
> + intel_runtime_pm_put(dev_priv);
Hm, intel_enable_ipc should take a bool on whether to enable ipc.
Forcefully enabling IPC here might give weird effects until the next plane
update. The transition watermarks are not updated yet until the next commit.
This could probably be handled here, but that would be overkill..
Perhaps add a drm_info or something about it when setting enable = true, when
it was previously false?
> +
> + return len;
> +}
> +
> +static const struct file_operations i915_ipc_status_fops = {
> + .owner = THIS_MODULE,
> + .open = i915_ipc_status_open,
> + .read = seq_read,
> + .llseek = seq_lseek,
> + .release = single_release,
> + .write = i915_ipc_status_write
> +};
> +
> static int i915_ddb_info(struct seq_file *m, void *unused)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> @@ -4929,7 +4999,8 @@ static const struct i915_debugfs_files {
> {"i915_dp_test_type", &i915_displayport_test_type_fops},
> {"i915_dp_test_active", &i915_displayport_test_active_fops},
> {"i915_guc_log_control", &i915_guc_log_control_fops},
> - {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}
> + {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
> + {"i915_ipc_status", &i915_ipc_status_fops}
> };
>
> int i915_debugfs_register(struct drm_i915_private *dev_priv)
___
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Re: [Intel-gfx] [PATCH 7/8] drm/i915/bxt+: Enable IPC support
Op 18-07-17 om 14:49 schreef Mahesh Kumar: > From: "Kumar, Mahesh" > > This patch adds IPC support. This patch also enables IPC in all supported > platforms based on has_ipc flag. > IPC (Isochronous Priority Control) is the hardware feature, which > dynamically controls the memory read priority of Display. > > When IPC is enabled, plane read requests are sent at high priority until > filling above the transition watermark, then the requests are sent at > lower priority until dropping below the level 0 watermark. > The lower priority requests allow other memory clients to have better > memory access. When IPC is disabled, all plane read requests are sent at > high priority. > > Changes since V1: > - Remove commandline parameter to disable ipc > - Address Paulo's comments > Changes since V2: > - Address review comments > - Set ipc_enabled flag > Changes since V3: > - move ipc_enabled flag assignment inside intel_ipc_enable function > Changes since V4: > - Re-enable IPC after suspend/resume > Changes since V5: > - Enable IPC for all gen >=9 except SKL > Changes since V6: > - fix commit msg > - after resume program IPC based on SW state. > Changes since V7: > - Modify IPC support check based on HAS_IPC macro (suggested by Chris) Much better, for all patches without comments.. Reviewed-by: Maarten Lankhorst ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 8/8] drm/i915/skl+: debugfs entry to control IPC
Hi,
Thanks for review.
On Wednesday 09 August 2017 03:03 PM, Maarten Lankhorst wrote:
Op 18-07-17 om 14:49 schreef Mahesh Kumar:
From: "Kumar, Mahesh"
This patch creates an entry in debugfs to check the status of IPC.
This can also be used to enable/disable IPC in supported platforms.
Signed-off-by: Mahesh Kumar
---
drivers/gpu/drm/i915/i915_debugfs.c | 73 -
1 file changed, 72 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2ef75c1a6119..368f64de0fdc 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3592,6 +3592,76 @@ static int i915_wa_registers(struct seq_file *m, void
*unused)
return 0;
}
+static int i915_ipc_status_show(struct seq_file *m, void *data)
+{
+ struct drm_i915_private *dev_priv = m->private;
+
+ seq_printf(m, "Isochronous Priority Control: %s\n",
+ enableddisabled(dev_priv->ipc_enabled));
+ return 0;
+}
+
+static int i915_ipc_status_open(struct inode *inode, struct file *file)
+{
+ struct drm_i915_private *dev_priv = inode->i_private;
+
+ if (HAS_IPC(dev_priv))
+ return -ENODEV;
I take it you didn't test this version of the patch? :p
hmm, I switched HAS_IPC macro in this version of patch only. will fix
this. thanks for catching it.
+
+ return single_open(file, i915_ipc_status_show, dev_priv);
+}
+
+static ssize_t i915_ipc_status_write(struct file *file, const char __user
*ubuf,
+size_t len, loff_t *offp)
+{
+ struct seq_file *m = file->private_data;
+ struct drm_i915_private *dev_priv = m->private;
+ char *newline;
+ char tmp[16];
+ bool enable;
+
+ if (HAS_IPC(dev_priv))
+ return -ENODEV;
Again, though I would remove this check since you already test in open().
ok, will remove this check.
+ if (len >= sizeof(tmp))
+ return -EINVAL;
+
+ if (copy_from_user(tmp, ubuf, len))
+ return -EFAULT;
+
+ tmp[len] = '\0';
+
+ /* Strip newline, if any */
+ newline = strchr(tmp, '\n');
+ if (newline)
+ *newline = '\0';
+
+ if (strcmp(tmp, "0") == 0 || strcmp(tmp, "disable") == 0 ||
+ strcmp(tmp, "off") == 0 || strcmp(tmp, "dis") == 0)
+ enable = false;
+ else if (strcmp(tmp, "1") == 0 || strcmp(tmp, "enable") == 0 ||
+ strcmp(tmp, "on") == 0 || strcmp(tmp, "en") == 0)
+ enable = true;
+ else
+ return -EINVAL;
Maybe replace with kstrtobool_from_user, and use yesno for ipc_enabled in
show()? That way you won't have to do all these special cases here. :)
kstrtobool_from_user sounds good, will use this macro :)
-Mahesh
+
+ intel_runtime_pm_get(dev_priv);
+ dev_priv->ipc_enabled = enable;
+ intel_enable_ipc(dev_priv);
+ intel_runtime_pm_put(dev_priv);
+
+ return len;
+}
+
+static const struct file_operations i915_ipc_status_fops = {
+ .owner = THIS_MODULE,
+ .open = i915_ipc_status_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+ .write = i915_ipc_status_write
+};
+
static int i915_ddb_info(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4929,7 +4999,8 @@ static const struct i915_debugfs_files {
{"i915_dp_test_type", &i915_displayport_test_type_fops},
{"i915_dp_test_active", &i915_displayport_test_active_fops},
{"i915_guc_log_control", &i915_guc_log_control_fops},
- {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}
+ {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops},
+ {"i915_ipc_status", &i915_ipc_status_fops}
};
int i915_debugfs_register(struct drm_i915_private *dev_priv)
___
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[Intel-gfx] [PATCH igt] lib/kms: Clear unused fields for getproperty ioctl
==24749== Syscall param ioctl(generic) points to uninitialised byte(s)
==24749==at 0x6A8ADC7: ioctl (syscall-template.S:84)
==24749==by 0x5067687: drmIoctl (in /opt/xorg/lib64/libdrm.so.2.4.0)
==24749==by 0x138531: kmstest_set_connector_dpms (igt_kms.c:1022)
==24749==by 0x112937: set_dpms (kms_flip.c:263)
==24749==by 0x112937: run_test_step (kms_flip.c:776)
==24749==by 0x112937: event_loop (kms_flip.c:1138)
==24749==by 0x115468: run_test_on_crtc_set (kms_flip.c:1378)
==24749==by 0x115468: run_test (kms_flip.c:1450)
==24749==by 0xCF: main (kms_flip.c:1673)
==24749== Address 0x1ffefff2a0 is on thread 1's stack
==24749== in frame #2, created by kmstest_set_connector_dpms (igt_kms.c:1012)
Signed-off-by: Chris Wilson
---
lib/igt_kms.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 9fe800d1..0c6dbf74 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1014,11 +1014,10 @@ void kmstest_set_connector_dpms(int fd,
drmModeConnector *connector, int mode)
bool found_it = false;
for (i = 0; i < connector->count_props; i++) {
- struct drm_mode_get_property prop;
+ struct drm_mode_get_property prop = {
+ .prop_id = connector->props[i],
+ };
- prop.prop_id = connector->props[i];
- prop.count_values = 0;
- prop.count_enum_blobs = 0;
if (drmIoctl(fd, DRM_IOCTL_MODE_GETPROPERTY, &prop))
continue;
--
2.13.3
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[Intel-gfx] [PATCH 3/8] drm/i915/guc: Handle GuC HW/SW state cleanup in unload path
Teardown of GuC HW/SW state was not properly done in unload path.
During unload, we can rely on intel_guc_reset_prepare being done
as part of i915_gem_suspend for disabling GuC interfaces.
We will have to disable GuC submission prior to suspend as that involves
communication with GuC to destroy doorbell. So intel_uc_fini_hw has to
be called as part of i915_gem_suspend during unload as that really
takes care of finishing the GuC operations. Created new parameter for
i915_gem_suspend to handle unload/suspend path w.r.t gem and GuC suspend.
GuC related allocations are cleaned up as part of intel_uc_cleanup_hw.
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c | 8
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/i915_gem.c | 8 ++--
drivers/gpu/drm/i915/intel_guc.c | 13 +
drivers/gpu/drm/i915/intel_guc.h | 1 +
drivers/gpu/drm/i915/intel_uc.c | 14 +-
drivers/gpu/drm/i915/intel_uc.h | 1 +
7 files changed, 32 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 218a8e1..c3fb73f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -599,7 +599,7 @@ static void i915_gem_fini(struct drm_i915_private *dev_priv)
i915_gem_drain_workqueue(dev_priv);
mutex_lock(&dev_priv->drm.struct_mutex);
- intel_uc_fini_hw(dev_priv);
+ intel_uc_cleanup_hw(dev_priv);
i915_gem_cleanup_engines(dev_priv);
i915_gem_contexts_fini(dev_priv);
i915_gem_cleanup_userptr(dev_priv);
@@ -680,7 +680,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
return 0;
cleanup_gem:
- if (i915_gem_suspend(dev_priv))
+ if (i915_gem_suspend(dev_priv, true))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
i915_gem_fini(dev_priv);
cleanup_uc:
@@ -1373,7 +1373,7 @@ void i915_driver_unload(struct drm_device *dev)
i915_driver_unregister(dev_priv);
- if (i915_gem_suspend(dev_priv))
+ if (i915_gem_suspend(dev_priv, true))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
@@ -1518,7 +1518,7 @@ static int i915_drm_suspend(struct drm_device *dev)
pci_save_state(pdev);
- error = i915_gem_suspend(dev_priv);
+ error = i915_gem_suspend(dev_priv, false);
if (error) {
dev_err(&pdev->dev,
"GEM idle failed, resume might fail\n");
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 085647a..dd6a3ff 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3547,7 +3547,8 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine,
void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
unsigned int flags);
-int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
+int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv,
+ bool unload);
void i915_gem_resume(struct drm_i915_private *dev_priv);
int i915_gem_fault(struct vm_fault *vmf);
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e118b9a..1b1b9c7 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4525,7 +4525,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
}
}
-int i915_gem_suspend(struct drm_i915_private *dev_priv)
+int i915_gem_suspend(struct drm_i915_private *dev_priv, bool unload)
{
struct drm_device *dev = &dev_priv->drm;
int ret;
@@ -4572,7 +4572,11 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
WARN_ON(dev_priv->gt.awake);
WARN_ON(!intel_engines_are_idle(dev_priv));
- intel_guc_system_suspend(&dev_priv->guc);
+ /* Handle GuC suspension in case of unloading/system suspend */
+ if (unload)
+ intel_uc_fini_hw(dev_priv);
+ else
+ intel_guc_system_suspend(&dev_priv->guc);
/*
* Neither the BIOS, ourselves or any other kernel
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 3777659..f4ddfbb 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -313,3 +313,16 @@ int intel_guc_system_resume(struct intel_guc *guc)
*/
return ret;
}
+
+void intel_guc_fini(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_device *dev = &dev_priv->drm;
+
+ if (i915.enable_guc_submission) {
+ mutex_lock(&dev->struct_mutex);
+ i915_guc_
[Intel-gfx] [PATCH 6/8] drm/i915/guc: Change default GuC FW for BXT to v9.29
This patch makes v9.29 firmware as default firmware for BXT. This update includes (since v8.7): - Added support to log media reset count for host to read it - BXT WA for fixing MTP hangs. WaDisableDOPRenderClkGatingAtSubmit - Sub-feature level control for power management features. - Minor clean-up for power management interface. - Unified power management interface and scheduler interface into 1 file using same version. - Bug Fix for multi context scheduler flag. - DCC spec changes for BXT + DCT enabling - Springboard based Pre-ETM/ETM flow enabling for debug signed GuC/HuC - Moving GuC non_critical r/w data to lower SRAM 64KB - Enabled IBC for BXT - Media engine Reset fix. Correctly marking context for resubmission in Media Reset case. - SLPC Dynamic RPe fix to resolve issues where incorrect frequency was set. - ABT Disable bug fix. Disabled Evaluation mode on context change. - GuC clean up to align developer build in line to production build. - Disable ARAT interrupt before programming ARAT delta. - Memory range check in Parse to avoid failure due to overflow. - Clear forcewake in CSB when SQ is empty. - SLPC IBC 1.6 for APL to ensure multiplier does not cap IA below Pe. - Move UkGuckmdInterface.h file from 2016 folders to common 2016 folder. - This is file location change. No functional change done as part of this check in. - 3 tries of wake request needed from GuC2CSME for ME to wake up. Request has come from ME spec - During reset one parameter was not getting accounted - Enabling Guc Log changes for ultra low logging for OCA - Disable build.bat redundant prints. - Move few least used functions to non-critical section. - Rearrange GuC documentation folder structure. - Fixing Issue with Default Guc Log changes for OCA using special Control Bit Cc: Arkadiusz Hiler Cc: Spotswood John A Cc: Anusha Srivatsa Signed-off-by: Jeff McGee Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/intel_guc_loader.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index b704193..9a41386 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -54,8 +54,8 @@ #define SKL_FW_MAJOR 9 #define SKL_FW_MINOR 33 -#define BXT_FW_MAJOR 8 -#define BXT_FW_MINOR 7 +#define BXT_FW_MAJOR 9 +#define BXT_FW_MINOR 29 #define KBL_FW_MAJOR 9 #define KBL_FW_MINOR 14 -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/8] drm/i915/guc: Handle GuC interaction in reset/suspend scenarios
Tearing down of guc_ggtt_invalidate/guc_interrupts/guc_communication
setup should happen towards end of reset/suspend as these are
setup back again during recovery/resume.
Prepared helpers intel_guc_pause and intel_guc_unpause that will do
teardown/bringup of this setup along with suspension/resumption of GuC if
loaded. Moved intel_guc_suspend, intel_guc_resume to intel_guc.c.
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c| 6 +-
drivers/gpu/drm/i915/i915_gem.c| 6 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 52
drivers/gpu/drm/i915/intel_guc.c | 131 +
drivers/gpu/drm/i915/intel_guc.h | 7 +-
5 files changed, 142 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5512cce..218a8e1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1688,8 +1688,6 @@ static int i915_drm_resume(struct drm_device *dev)
}
mutex_unlock(&dev->struct_mutex);
- intel_guc_resume(dev_priv);
-
intel_modeset_init_hw(dev);
spin_lock_irq(&dev_priv->irq_lock);
@@ -2484,7 +2482,7 @@ static int intel_runtime_suspend(struct device *kdev)
*/
i915_gem_runtime_suspend(dev_priv);
- intel_guc_suspend(dev_priv);
+ intel_guc_runtime_suspend(&dev_priv->guc);
intel_runtime_pm_disable_interrupts(dev_priv);
@@ -2569,7 +2567,7 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
- intel_guc_resume(dev_priv);
+ intel_guc_runtime_resume(&dev_priv->guc);
if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 000a764..e118b9a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2840,6 +2840,8 @@ int i915_gem_reset_prepare(struct drm_i915_private
*dev_priv)
i915_gem_revoke_fences(dev_priv);
+ intel_guc_reset_prepare(&dev_priv->guc);
+
return err;
}
@@ -4555,8 +4557,6 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
i915_gem_contexts_lost(dev_priv);
mutex_unlock(&dev->struct_mutex);
- intel_guc_suspend(dev_priv);
-
cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
cancel_delayed_work_sync(&dev_priv->gt.retire_work);
@@ -4572,6 +4572,8 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
WARN_ON(dev_priv->gt.awake);
WARN_ON(!intel_engines_are_idle(dev_priv));
+ intel_guc_system_suspend(&dev_priv->guc);
+
/*
* Neither the BIOS, ourselves or any other kernel
* expects the system to be in execlists mode on startup,
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 602ae8a..2f977ab 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1287,55 +1287,3 @@ void i915_guc_submission_disable(struct drm_i915_private
*dev_priv)
guc_client_free(guc->execbuf_client);
guc->execbuf_client = NULL;
}
-
-/**
- * intel_guc_suspend() - notify GuC entering suspend state
- * @dev_priv: i915 device private
- */
-int intel_guc_suspend(struct drm_i915_private *dev_priv)
-{
- struct intel_guc *guc = &dev_priv->guc;
- struct i915_gem_context *ctx;
- u32 data[3];
-
- if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
- return 0;
-
- gen9_disable_guc_interrupts(dev_priv);
-
- ctx = dev_priv->kernel_context;
-
- data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
- /* any value greater than GUC_POWER_D0 */
- data[1] = GUC_POWER_D1;
- /* first page is shared data with GuC */
- data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
-
- return intel_guc_send(guc, data, ARRAY_SIZE(data));
-}
-
-/**
- * intel_guc_resume() - notify GuC resuming from suspend state
- * @dev_priv: i915 device private
- */
-int intel_guc_resume(struct drm_i915_private *dev_priv)
-{
- struct intel_guc *guc = &dev_priv->guc;
- struct i915_gem_context *ctx;
- u32 data[3];
-
- if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
- return 0;
-
- if (i915.guc_log_level >= 0)
- gen9_enable_guc_interrupts(dev_priv);
-
- ctx = dev_priv->kernel_context;
-
- data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
- data[1] = GUC_POWER_D0;
- /* first page is shared data with GuC */
- data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
-
- return intel_guc_send(guc, data, ARRAY_SIZE(data));
-}
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/driv
[Intel-gfx] [PATCH 7/8] drm/i915/guc: Change default GuC FW for KBL to v9.39
This patch makes v9.39 firmware as default firmware for KBL. This update includes (since v9.14): - DCC spec changes for BXT + DCT enabling - Bug Fix for power conservation feature SLPC_DCC - Scheduler 1-element submission during DCC cycles. - SB based Pre-ETM/ETM flow enabling for debug signed GuC/HuC - Moving GuC non_critical r/w data to lower SRAM 64KB - Media engine Reset fix. Correctly marking context for resubmission in Media Reset case. - ABT Disable bug fix. Disabled Evaluation mode on context change. - Async FW in Engine Schedule feature (not enabled from KMD) - GuC clean up to align developer build in line to production build. - Disable ARAT interrupt before programming ARAT delta. - Memory range check in Parse to avoid failure due to overflow. - GuC Msg Channel Hang WA - Stall GUC for mmio access when IDI is low during CPD flow. - Fix for submit queue over flow issue - Enabling IBC on KBL GT3 15W, GT4 45W - Disabling wrong device ID WA in production signed kernel - Enabling WA for MSGCH hang issue upto required KBL stepping - Clear forcewake in CSB when SQ is empty. - 3Tries of GuC2CSME wake request - During reset one parameter was not getting accounted - Disable DCC 1-elem mode submission - Move UkGuckmdInterface.h file from 2016 folders to common 2016 folder. - This is file location change.No functional change done as part of this check in. - Enabling Guc Log changes for ultra low logging for OCA - Enabling Dynamic Render Power Well Hysteresis Programming for Compute Worklaods - Enabling build failure check to catch critical section overflow. - Disable build.bat redundant prints. - Move few least used functions to non-critical section. - Rearrange GuC documentation folder structure. - Synchronize SLPC internal debug interface with other branches. - Fixing Issue with Default Guc Log changes for OCA using special Control Bit - Aggressive DCC implementation for supported platforms. Cc: Arkadiusz Hiler Cc: Spotswood John A Cc: Anusha Srivatsa Signed-off-by: Jeff McGee Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/intel_guc_loader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index 9a41386..05696f2 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -58,7 +58,7 @@ #define BXT_FW_MINOR 29 #define KBL_FW_MAJOR 9 -#define KBL_FW_MINOR 14 +#define KBL_FW_MINOR 39 #define GLK_FW_MAJOR 10 #define GLK_FW_MINOR 56 -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/8] drm/i915: Separate GuC/HuC specific functionality from intel_uc
Removed unnecessary intel_uc.h includes as it is present in i915_drv.h.
Created intel_guc.c and intel_guc.h for placing GuC specific code.
Created intel_huc.h to refer to HuC specific functions.
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/i915_drv.c| 1 -
drivers/gpu/drm/i915/i915_drv.h| 2 +
drivers/gpu/drm/i915/i915_guc_submission.c | 1 -
drivers/gpu/drm/i915/intel_guc.c | 184 ++
drivers/gpu/drm/i915/intel_guc.h | 203 +
drivers/gpu/drm/i915/intel_guc_loader.c| 1 -
drivers/gpu/drm/i915/intel_huc.c | 2 -
drivers/gpu/drm/i915/intel_huc.h | 38 ++
drivers/gpu/drm/i915/intel_uc.c| 159 +-
drivers/gpu/drm/i915/intel_uc.h| 178 -
11 files changed, 430 insertions(+), 341 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_guc.c
create mode 100644 drivers/gpu/drm/i915/intel_guc.h
create mode 100644 drivers/gpu/drm/i915/intel_huc.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f822731..efa7605 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -58,6 +58,8 @@ i915-y += i915_cmd_parser.o \
# general-purpose microcontroller (GuC) support
i915-y += intel_uc.o \
+ intel_guc.o \
+ intel_huc.o \
intel_guc_ct.o \
intel_guc_log.o \
intel_guc_loader.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 214555e..5512cce 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -50,7 +50,6 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
-#include "intel_uc.h"
static struct drm_driver driver;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2c7456f..085647a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -59,6 +59,8 @@
#include "intel_bios.h"
#include "intel_dpll_mgr.h"
#include "intel_uc.h"
+#include "intel_guc.h"
+#include "intel_huc.h"
#include "intel_lrc.h"
#include "intel_ringbuffer.h"
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 48a1e93..602ae8a 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -23,7 +23,6 @@
*/
#include
#include "i915_drv.h"
-#include "intel_uc.h"
#include
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
new file mode 100644
index 000..a812d3d
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915_drv.h"
+
+inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
+{
+ GEM_BUG_ON(!guc->send_regs.base);
+ GEM_BUG_ON(!guc->send_regs.count);
+ GEM_BUG_ON(i >= guc->send_regs.count);
+
+ return _MMIO(guc->send_regs.base + 4 * i);
+}
+
+void guc_capture_load_err_log(struct intel_guc *guc)
+{
+ if (!guc->log.vma || i915.guc_log_level < 0)
+ return;
+
+ if (!guc->load_err_log)
+ guc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
+}
+
+void guc_free_load_err_log(struct intel_guc *guc)
+{
+ if (guc->load_err_log)
+ i915_gem_object_put(guc->load_err_log);
+}
+
+static void guc_init_send_regs(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ enum forcewake_domains fw_domains = 0;
+ unsigned int i;
+
+ guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
+ gu
[Intel-gfx] [PATCH 4/8] drm/i915/guc: Disable critical logging in GuC by default from GuC v9
From GuC v9 firmware (for KBL v9.39+), separate control is added to enable
critical logging in GuC to enable capturing minimal important logs in
production systems.
i915.guc_log_level controls the verbosity and logging in GuC for logs other
than critical logs. By default, logging in GuC is disabled through
i915.guc_log_level.
This patch introduces new kernel param i915.enable_guc_critical_logging.
For Linux release builds, if needed critical GuC logs can be enabled
separately through this parameter. GuC log snapshot captured in error state
will have these minimal critical events logged.
Default value for this parameter is currently set to false.
This patch updates the initialization parameter sent during GuC load to
disable critical logging unless i915.guc_log_level is set to enable logging
and ensures it is enabled/disabling while enabling/disabling through
debugfs based on i915.enable_guc_critical_logging.
Cc: Arkadiusz Hiler
Cc: Spotswood John A
Cc: Anusha Srivatsa
Signed-off-by: Jeff McGee
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_params.c | 5 +
drivers/gpu/drm/i915/i915_params.h | 3 ++-
drivers/gpu/drm/i915/intel_guc_fwif.h | 14 +-
drivers/gpu/drm/i915/intel_guc_loader.c | 21 -
drivers/gpu/drm/i915/intel_guc_log.c| 9 -
5 files changed, 48 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 14e2c2e..902bf2c 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -59,6 +59,7 @@ struct i915_params i915 __read_mostly = {
.enable_guc_loading = 0,
.enable_guc_submission = 0,
.guc_log_level = -1,
+ .enable_guc_critical_logging = false,
.guc_firmware_path = NULL,
.huc_firmware_path = NULL,
.enable_dp_mst = true,
@@ -232,6 +233,10 @@ struct i915_params i915 __read_mostly = {
MODULE_PARM_DESC(guc_log_level,
"GuC firmware logging level (-1:disabled (default), 0-3:enabled)");
+module_param_named(enable_guc_critical_logging,
i915.enable_guc_critical_logging, bool, 0400);
+MODULE_PARM_DESC(enable_guc_critical_logging,
+ "Enable GuC firmware critical logging (default: false)");
+
module_param_named_unsafe(guc_firmware_path, i915.guc_firmware_path, charp,
0400);
MODULE_PARM_DESC(guc_firmware_path,
"GuC firmware path to use instead of the default one");
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index febbfdb..7c208f0 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -67,7 +67,8 @@
func(bool, nuclear_pageflip); \
func(bool, enable_dp_mst); \
func(bool, enable_dpcd_backlight); \
- func(bool, enable_gvt)
+ func(bool, enable_gvt); \
+ func(bool, enable_guc_critical_logging)
#define MEMBER(T, member) T member
struct i915_params {
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 5fa2860..353b081 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -132,6 +132,7 @@
#define GUC_WQ_TRACK_ENABLED (1 << 8)
#define GUC_ADS_ENABLED (1 << 9)
#define GUC_DEBUG_RESERVED (1 << 10)
+#define GUC_V9_CRITICAL_LOGGING_DISABLED (1 << 10)
#define GUC_ADS_ADDR_SHIFT 11
#define GUC_ADS_ADDR_MASK0xf800
@@ -139,6 +140,16 @@
#define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
+/*
+ * Critical logging in GuC is to be enabled always from GuC v9+.
+ * (for KBL - v9.39+)
+ */
+#define NEEDS_GUC_CRITICAL_LOGGING(dev_priv, guc_fw) \
+ (((IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) && \
+ guc_fw->major_ver_found >= 9) || \
+ (IS_KABYLAKE(dev_priv) && guc_fw->major_ver_found >= 9 && \
+ guc_fw->minor_ver_found >= 39))
+
/**
* DOC: GuC Firmware Layout
*
@@ -539,7 +550,8 @@ struct guc_log_buffer_state {
u32 logging_enabled:1;
u32 reserved1:3;
u32 verbosity:4;
- u32 reserved2:24;
+ u32 critical_logging_enabled:1;
+ u32 reserved2:23;
};
u32 value;
} __packed;
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 81e03a6..535c665 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -106,8 +106,10 @@ static u32 get_core_family(struct drm_i915_private
*dev_priv)
static void guc_params_init(struct drm_i915_private *dev_priv)
{
struct intel_guc *guc = &dev_priv->guc;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
u32 params[GUC_CTL_MAX_DWORDS];
int i;
+ bool enable_critical_logging = false;
memset(¶ms, 0, sizeof
[Intel-gfx] [PATCH 5/8] drm/i915/guc: Change default GuC FW for SKL to v9.33
This patch makes v9.33 firmware as default firmware for SKL. This update includes (since v6.1): - HuC RSA Keys updated. - Adding per engine preemption support in GuC scheduler - Minor bug fixes. - Added support to log media reset count for host to read it - Sub-feature level control for power management features. - Minor clean-up for power management interface. - Unified power management interface and scheduler interface into 1 file using same version. - Bug Fix for multi context scheduler flag. - DCC spec changes for BXT + DCT enabling - SB based Pre-ETM/ETM flow enabling for debug signed GuC/HuC - Moving GuC non_critical r/w data to lower SRAM 64KB - Media engine Reset fix. Correctly marking context for resubmission in Media Reset case. - ABT Disable bug fix. Disabled Evaluation mode on context change. - Async FW in Engine Schedule feature (not enabled from KMD) - GuC clean up to align developer build in line to production build. - DCC consistency fix for SKL - Disable ARAT interrupt before programming ARAT delta. - Memory range check in Parse to avoid failure due to overflow. - Enabled WA for MSGCH hang issue - Clear forcewake in CSB when SQ is empty. - Move UkGuckmdInterface.h file from 2016 folders to common 2016 folder. - This is file location change.No functional change done as part of this check in. - Enable decoupled freq for SKL GT4 - 3 tries of wake request needed from GuC2CSME for ME to wake up. Request has come from ME spec - During reset one parameter was not getting accounted - Enabling Guc Log changes for ultra low logging for OCA - Enabling build failure check to catch critical section overflow. - Disable build.bat redundant prints. - Move few least used functions to non-critical section. - Rearrange GuC documentation folder structure. - Synchronize SLPC internal debug interface with other branches. - Fixing Issue with Default Guc Log changes for OCA using special Control Bit Cc: Arkadiusz Hiler Cc: Spotswood John A Cc: Anusha Srivatsa Signed-off-by: Jeff McGee Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/intel_guc_loader.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index 535c665..b704193 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -51,8 +51,8 @@ * */ -#define SKL_FW_MAJOR 6 -#define SKL_FW_MINOR 1 +#define SKL_FW_MAJOR 9 +#define SKL_FW_MINOR 33 #define BXT_FW_MAJOR 8 #define BXT_FW_MINOR 7 -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for tools/null_state_gen: Add proper color calc and depth stencil states
== Series Details == Series: tools/null_state_gen: Add proper color calc and depth stencil states URL : https://patchwork.freedesktop.org/series/28542/ State : success == Summary == IGT patchset tested on top of latest successful build c129026622accef6f54c0cfb0dc55e930cfa60b5 igt: add syncobj_basic. with latest DRM-Tip kernel build CI_DRM_2937 4641b60d14c7 drm-tip: 2017y-08m-09d-08h-53m-33s UTC integration manifest Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: pass -> DMESG-WARN (fi-byt-n2820) fdo#101705 fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705 fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:438s fi-bdw-gvtdvmtotal:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:418s fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:358s fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:499s fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:493s fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:522s fi-byt-n2820 total:279 pass:250 dwarn:1 dfail:0 fail:0 skip:28 time:513s fi-glk-2atotal:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:585s fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:442s fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:412s fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:416s fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:512s fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:480s fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:468s fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:566s fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:570s fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:520s fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:446s fi-skl-6700k total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:645s fi-skl-6770hqtotal:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:463s fi-skl-gvtdvmtotal:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:422s fi-skl-x1585ltotal:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:483s fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:547s fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:412s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_36/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/8] drm/i915/guc: Disable critical logging in GuC by default from GuC v9
Quoting Sagar Arun Kamble (2017-08-09 11:23:48)
> From GuC v9 firmware (for KBL v9.39+), separate control is added to enable
> critical logging in GuC to enable capturing minimal important logs in
> production systems.
> i915.guc_log_level controls the verbosity and logging in GuC for logs other
> than critical logs. By default, logging in GuC is disabled through
> i915.guc_log_level.
> This patch introduces new kernel param i915.enable_guc_critical_logging.
> For Linux release builds, if needed critical GuC logs can be enabled
> separately through this parameter. GuC log snapshot captured in error state
> will have these minimal critical events logged.
> Default value for this parameter is currently set to false.
> This patch updates the initialization parameter sent during GuC load to
> disable critical logging unless i915.guc_log_level is set to enable logging
> and ensures it is enabled/disabling while enabling/disabling through
> debugfs based on i915.enable_guc_critical_logging.
>
> Cc: Arkadiusz Hiler
> Cc: Spotswood John A
> Cc: Anusha Srivatsa
> Signed-off-by: Jeff McGee
> Signed-off-by: Sagar Arun Kamble
> ---
> drivers/gpu/drm/i915/i915_params.c | 5 +
> drivers/gpu/drm/i915/i915_params.h | 3 ++-
> drivers/gpu/drm/i915/intel_guc_fwif.h | 14 +-
> drivers/gpu/drm/i915/intel_guc_loader.c | 21 -
> drivers/gpu/drm/i915/intel_guc_log.c| 9 -
> 5 files changed, 48 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_params.c
> b/drivers/gpu/drm/i915/i915_params.c
> index 14e2c2e..902bf2c 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -59,6 +59,7 @@ struct i915_params i915 __read_mostly = {
> .enable_guc_loading = 0,
> .enable_guc_submission = 0,
> .guc_log_level = -1,
> + .enable_guc_critical_logging = false,
What's the point in having a log level if LOG_LEVEL_CRITICAL is not part
of it? Please do explain why the current parameter does not cover this.
-Chris
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Re: [Intel-gfx] [PATCH igt] lib/kms: Clear unused fields for getproperty ioctl
Chris Wilson writes:
> ==24749== Syscall param ioctl(generic) points to uninitialised byte(s)
> ==24749==at 0x6A8ADC7: ioctl (syscall-template.S:84)
> ==24749==by 0x5067687: drmIoctl (in /opt/xorg/lib64/libdrm.so.2.4.0)
> ==24749==by 0x138531: kmstest_set_connector_dpms (igt_kms.c:1022)
> ==24749==by 0x112937: set_dpms (kms_flip.c:263)
> ==24749==by 0x112937: run_test_step (kms_flip.c:776)
> ==24749==by 0x112937: event_loop (kms_flip.c:1138)
> ==24749==by 0x115468: run_test_on_crtc_set (kms_flip.c:1378)
> ==24749==by 0x115468: run_test (kms_flip.c:1450)
> ==24749==by 0xCF: main (kms_flip.c:1673)
> ==24749== Address 0x1ffefff2a0 is on thread 1's stack
> ==24749== in frame #2, created by kmstest_set_connector_dpms (igt_kms.c:1012)
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> lib/igt_kms.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/lib/igt_kms.c b/lib/igt_kms.c
> index 9fe800d1..0c6dbf74 100644
> --- a/lib/igt_kms.c
> +++ b/lib/igt_kms.c
> @@ -1014,11 +1014,10 @@ void kmstest_set_connector_dpms(int fd,
> drmModeConnector *connector, int mode)
> bool found_it = false;
>
> for (i = 0; i < connector->count_props; i++) {
> - struct drm_mode_get_property prop;
> + struct drm_mode_get_property prop = {
> + .prop_id = connector->props[i],
> + };
>
> - prop.prop_id = connector->props[i];
> - prop.count_values = 0;
> - prop.count_enum_blobs = 0;
> if (drmIoctl(fd, DRM_IOCTL_MODE_GETPROPERTY, &prop))
> continue;
>
> --
> 2.13.3
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [RFC i-g-t] tests/gem_exec_basic: Documentation for subtests
Hi, I'm a bit confused by this patch. How is this idea different from
what previous patch from Petri offered? I mean what additional value
does this solution brings? Is this something we want on top of previous
solution or instead of previous solution?
This doesn't take in to account auto generated tests and is more
'description of functions' then 'subtest documentation'.
If we take Petris example here we have basically the same information:
"(WHAT) Frob knobs
"(WHY) to see if one of the crossbeams will go out of skew on the
treadle."
but directly related to the subtest.
On Tue, 2017-08-08 at 15:09 -0700, Vinay Belgaumkar wrote:
> This is an RFC for adding documentation to IGT subtests. Each subtest
> can have
> something similar to a WHAT - explaining what the subtest actually
> does,
> and a WHY - which explains a use case, if applicable. Additionally,
> include comments for anything in the subtest code which can help
> explain HOW the test has been implemented. We don't actually need the
> WHAT
> and WHY tags in the documentation.
>
> These comments will not be linked to gtkdoc as of now, since we do
> not have a
> mechanism to link it to every subtest name.
>
> Signed-off-by: Vinay Belgaumkar
> Cc: Daniel Vetter
> Cc: Petri Latvala
> Cc: Chris Wilson
> ---
> tests/gem_exec_basic.c | 21 +
> 1 file changed, 21 insertions(+)
>
> diff --git a/tests/gem_exec_basic.c b/tests/gem_exec_basic.c
> index 2f057ef..b1491cd 100644
> --- a/tests/gem_exec_basic.c
> +++ b/tests/gem_exec_basic.c
> @@ -25,6 +25,11 @@
>
> IGT_TEST_DESCRIPTION("Basic sanity check of execbuf-ioctl rings.");
>
> +/*
> +(WHAT) This subtest submits an empty batch to each ring and verifies
> +that it is executed successfully
> +(WHY) It validates that GT buffer submission mechanism is functional
> +*/
> static void noop(int fd, unsigned ring)
> {
> uint32_t bbe = MI_BATCH_BUFFER_END;
> @@ -45,6 +50,11 @@ static void noop(int fd, unsigned ring)
> gem_close(fd, exec.handle);
> }
>
> +/*
> +(WHAT) This subtest memory maps a buffer, marks it as read only,
> +and submits it to each ring for execution.
> +(WHY) It helps us validate that the GT can execute read-only buffers
> +*/
> static void readonly(int fd, unsigned ring)
> {
> uint32_t bbe = MI_BATCH_BUFFER_END;
> @@ -57,12 +67,15 @@ static void readonly(int fd, unsigned ring)
> exec.handle = gem_create(fd, 4096);
> gem_write(fd, exec.handle, 0, &bbe, sizeof(bbe));
>
> + /* Memory map a buffer and use it as the execbuf to be
> submitted */
> execbuf = mmap(NULL, 4096, PROT_WRITE, MAP_ANON |
> MAP_PRIVATE, -1, 0);
> igt_assert(execbuf != NULL);
>
> execbuf->buffers_ptr = to_user_pointer(&exec);
> execbuf->buffer_count = 1;
> execbuf->flags = ring;
> +
> + /* Now mark the buffer as read-only */
> igt_assert(mprotect(execbuf, 4096, PROT_READ) == 0);
>
> gem_execbuf(fd, execbuf);
> @@ -70,6 +83,10 @@ static void readonly(int fd, unsigned ring)
> gem_close(fd, exec.handle);
> }
>
> +/*
> +(WHAT) Create a gtt mapped buffer and submit to the GPU.
> +(WHY) It ensures GPU can properly map and access GTT mapped buffers
> +*/
> static void gtt(int fd, unsigned ring)
> {
> uint32_t bbe = MI_BATCH_BUFFER_END;
> @@ -82,6 +99,8 @@ static void gtt(int fd, unsigned ring)
> handle = gem_create(fd, 4096);
>
> gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT,
> I915_GEM_DOMAIN_GTT);
> +
> + /* Create a memory mapping through GTT */
> execbuf = gem_mmap__gtt(fd, handle, 4096, PROT_WRITE);
> exec = (struct drm_i915_gem_exec_object2 *)(execbuf + 1);
> gem_close(fd, handle);
> @@ -108,6 +127,8 @@ igt_main
> fd = drm_open_driver(DRIVER_INTEL);
> igt_require_gem(fd);
>
> + /* Start the hang detector process. Test will fail
> + if a GPU hang is detected during any subtest */
> igt_fork_hang_detector(fd);
> }
>
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[Intel-gfx] [maintainer-tools PATCH 2/7] dim: fix end-of-line in regex
Signed-off-by: Eric Engestrom
---
dim | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/dim b/dim
index af1baa11c7b2..eaabcec43c8f 100755
--- a/dim
+++ b/dim
@@ -1970,7 +1970,7 @@ function dim_add_missing_cc
name=''
if echo "$cc" | grep -q '<'; then
- name="$(echo ${cc/<*/} | sed -e 's/[[:space:]]*\$//')";
+ name="$(echo ${cc/<*/} | sed -e 's/[[:space:]]*$//')";
fi
# Don't add main mailing lists
@@ -1988,7 +1988,7 @@ function dim_add_missing_cc
if [ "$testemail" != "$email" ]; then
if [ -z "$name" ]; then continue; fi
- testname="$(echo ${testcc/<*/} | sed -e
's/[[:space:]]*\$//' -e 's/^[[:space:]]*//')"
+ testname="$(echo ${testcc/<*/} | sed -e
's/[[:space:]]*$//' -e 's/^[[:space:]]*//')"
if [ "$testname" != "$name" ]; then
continue; fi
fi
--
Cheers,
Eric
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[Intel-gfx] [maintainer-tools PATCH 1/7] dim: don't run add-missing-cc on merge commits
get_maintainer.pl needs a diff, so this script can't run on a merge
commit.
Signed-off-by: Eric Engestrom
---
dim | 5 +
1 file changed, 5 insertions(+)
diff --git a/dim b/dim
index 619d855b321b..af1baa11c7b2 100755
--- a/dim
+++ b/dim
@@ -1960,6 +1960,11 @@ function dim_fixes
function dim_add_missing_cc
{
+ if [ $(git cat-file -p HEAD | grep -cE ^parent) -ne 1 ]; then
+ echoerr "This script doesn't work on merge commits"
+ return
+ fi
+
git show | scripts/get_maintainer.pl --email --norolestats
--pattern-depth 1 | while read cc; do
email="$(echo "$cc" | sed -e 's/.*.*//')"
name=''
--
Cheers,
Eric
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[Intel-gfx] [maintainer-tools PATCH 5/7] dim: move empty name logic to function
Fair warning: this slightly changes the behaviour, as $testname would
previously contain the email if $testcc didn't contain a name.
Shouldn't affect anything though.
Signed-off-by: Eric Engestrom
---
dim | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/dim b/dim
index 4ffac497c621..481a53e23035 100755
--- a/dim
+++ b/dim
@@ -1965,7 +1965,9 @@ function email_get_address
function email_get_name
{
- sed -e 's/[[:space:]]*<.*$//' <<< "$1"
+ if grep -q '<' <<< "$1"; then
+ sed -e 's/[[:space:]]*<.*$//' <<< "$1"
+ fi
}
function dim_add_missing_cc
@@ -1977,11 +1979,7 @@ function dim_add_missing_cc
git show | scripts/get_maintainer.pl --email --norolestats
--pattern-depth 1 | while read cc; do
email="$(email_get_address "$cc")"
- name=''
-
- if echo "$cc" | grep -q '<'; then
- name="$(email_get_name "$cc")";
- fi
+ name="$(email_get_name "$cc")"
# Don't add main mailing lists
if [ "$email" = "dri-de...@lists.freedesktop.org" -o \
--
Cheers,
Eric
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[Intel-gfx] [maintainer-tools PATCH 3/7] dim: split out email parsing functions
Signed-off-by: Eric Engestrom
---
dim | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/dim b/dim
index eaabcec43c8f..a656afa0d255 100755
--- a/dim
+++ b/dim
@@ -1958,6 +1958,16 @@ function dim_fixes
fi
}
+function email_get_address
+{
+ sed -e 's/.*.*//' <<< "$1"
+}
+
+function email_get_name
+{
+ echo ${cc/<*/} | sed -e 's/[[:space:]]*$//' <<< "$1"
+}
+
function dim_add_missing_cc
{
if [ $(git cat-file -p HEAD | grep -cE ^parent) -ne 1 ]; then
@@ -1966,11 +1976,11 @@ function dim_add_missing_cc
fi
git show | scripts/get_maintainer.pl --email --norolestats
--pattern-depth 1 | while read cc; do
- email="$(echo "$cc" | sed -e 's/.*.*//')"
+ email="$(email_get_address "$cc")"
name=''
if echo "$cc" | grep -q '<'; then
- name="$(echo ${cc/<*/} | sed -e 's/[[:space:]]*$//')";
+ name="$(email_get_name "$cc")";
fi
# Don't add main mailing lists
@@ -1983,12 +1993,12 @@ function dim_add_missing_cc
# print out a 1 on success
matches=$(
git show -s | grep -i "^Cc:" | sed 's/^ *[Cc][Cc]:
*//' | while read testcc; do
- testemail="$(echo "$testcc" | sed -e 's/.*.*//')"
+ testemail="$(email_get_address "$testcc")"
if [ "$testemail" != "$email" ]; then
if [ -z "$name" ]; then continue; fi
- testname="$(echo ${testcc/<*/} | sed -e
's/[[:space:]]*$//' -e 's/^[[:space:]]*//')"
+ testname="$(email_get_name "$testcc" |
sed -e 's/^[[:space:]]*//')"
if [ "$testname" != "$name" ]; then
continue; fi
fi
--
Cheers,
Eric
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[Intel-gfx] [maintainer-tools PATCH 4/7] dim: merge string substitutions
Signed-off-by: Eric Engestrom
---
dim | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/dim b/dim
index a656afa0d255..4ffac497c621 100755
--- a/dim
+++ b/dim
@@ -1965,7 +1965,7 @@ function email_get_address
function email_get_name
{
- echo ${cc/<*/} | sed -e 's/[[:space:]]*$//' <<< "$1"
+ sed -e 's/[[:space:]]*<.*$//' <<< "$1"
}
function dim_add_missing_cc
--
Cheers,
Eric
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[Intel-gfx] [maintainer-tools PATCH 7/7] dim: protect against escaped chars when reading cc'ed emails
Suggested by shellcheck (`make check`). Signed-off-by: Eric Engestrom --- dim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dim b/dim index 2e22fefa8867..75ce55188af4 100755 --- a/dim +++ b/dim @@ -2002,7 +2002,7 @@ function dim_add_missing_cc return fi - git show | scripts/get_maintainer.pl --email --norolestats --pattern-depth 1 | while read cc; do + git show | scripts/get_maintainer.pl --email --norolestats --pattern-depth 1 | while read -r cc; do email="$(email_get_address "$cc")" name="$(email_get_name "$cc")" -- Cheers, Eric ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [maintainer-tools PATCH 6/7] dim: split out 'is email cc'ed in latest commit' to a function
Signed-off-by: Eric Engestrom
---
dim | 46 ++
1 file changed, 26 insertions(+), 20 deletions(-)
diff --git a/dim b/dim
index 481a53e23035..2e22fefa8867 100755
--- a/dim
+++ b/dim
@@ -1970,6 +1970,31 @@ function email_get_name
fi
}
+function email_cc_in_latest_commit
+{
+ email="$1"
+ name="$2"
+
+ git show -s | grep -i "^Cc:" | sed 's/^ *[Cc][Cc]: *//' | while
read -r testcc; do
+ testemail="$(email_get_address "$testcc")"
+ testname="$(email_get_name "$testcc" | sed -e
's/^[[:space:]]*//')"
+
+ if [ "$testemail" = "$email" ]; then
+ return 1
+ fi
+
+ if [ -z "$testname" ] || [ -z "$name" ]; then
+ continue
+ fi
+
+ if [ "$testname" = "$name" ]; then
+ return 1
+ fi
+ done || return 0
+
+ return 1
+}
+
function dim_add_missing_cc
{
if [ $(git cat-file -p HEAD | grep -cE ^parent) -ne 1 ]; then
@@ -1987,26 +2012,7 @@ function dim_add_missing_cc
continue
fi
- # Variables from the while loop don't propagate,
- # print out a 1 on success
- matches=$(
- git show -s | grep -i "^Cc:" | sed 's/^ *[Cc][Cc]:
*//' | while read testcc; do
- testemail="$(email_get_address "$testcc")"
-
- if [ "$testemail" != "$email" ]; then
- if [ -z "$name" ]; then continue; fi
-
- testname="$(email_get_name "$testcc" |
sed -e 's/^[[:space:]]*//')"
-
- if [ "$testname" != "$name" ]; then
continue; fi
- fi
-
- echo 1
- break
- done
- )
-
- if [ -z "$matches" ]; then
+ if ! email_cc_in_latest_commit "$email" "$name"; then
$DRY dim_commit_add_tag "Cc: ${cc}"
fi
done
--
Cheers,
Eric
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[Intel-gfx] [PATCH i-g-t 2/2] docs: Include subtest documentation
A simple and naive format: Double newline denotes paragraph change, otherwise insert subtest documentation into the generated docs as-is. Signed-off-by: Petri Latvala --- This works for me, but I don't know if the generated docs are actually valid docbook xml. docs/reference/intel-gpu-tools/Makefile.am | 6 ++ 1 file changed, 6 insertions(+) diff --git a/docs/reference/intel-gpu-tools/Makefile.am b/docs/reference/intel-gpu-tools/Makefile.am index ee1e900..2407e37 100644 --- a/docs/reference/intel-gpu-tools/Makefile.am +++ b/docs/reference/intel-gpu-tools/Makefile.am @@ -56,6 +56,12 @@ xml/igt_test_programs_%_description.xml: $(TESTLISTS) for subtest in $$subtest_list; do \ echo "" >> $@; \ echo "$$subtest" | perl -pe 's/\b$(KEYWORDS)\b/\1<\/acronym>/g' >> $@; \ + subtest_doc=`./$$testprog --document-subtest $$subtest`; \ + if [ -n "$$subtest_doc" ]; then \ + echo "" >> $@; \ + fi; \ echo "" >> $@; \ done; \ echo "" >> $@; \ -- 2.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 1/2] Add support for subtest-specific documentation
The current documentation for tests is limited to a single string per
test binary. This patch adds support for documenting individual
subtests.
The syntax for subtest documentation is:
igt_document_subtest("Frob knobs to see if one of the "
"crossbeams will go out of skew on the "
"treadle.\n");
igt_subtest("knob-frobbing-askew")
test_frob();
or with a format string:
for_example_loop(e) {
igt_document_subtest_f("Frob %s to see if one of the "
"crossbeams will go out of skew on the "
"treadle.\n", e->readable_name);
igt_subtest_f("%s-frob-askew", e->name)
test_frob(e);
}
The documentation cannot be extracted from just comments, because
associating them with the correct subtest name will then require doing
pattern matching in the documentation generator, for subtests where
the name is generated at runtime using igt_subtest_f.
v2: Rebase, change function name in commit message to match code
Signed-off-by: Petri Latvala
Acked-by: Leo Li
---
lib/igt_aux.c | 8 ++--
lib/igt_core.c | 147 +
lib/igt_core.h | 6 ++-
3 files changed, 126 insertions(+), 35 deletions(-)
diff --git a/lib/igt_aux.c b/lib/igt_aux.c
index f428f15..d56f41f 100644
--- a/lib/igt_aux.c
+++ b/lib/igt_aux.c
@@ -311,7 +311,7 @@ static void sig_handler(int i)
*/
void igt_fork_signal_helper(void)
{
- if (igt_only_list_subtests())
+ if (igt_only_collect_data())
return;
/* We pick SIGCONT as it is a "safe" signal - if we send SIGCONT to
@@ -344,7 +344,7 @@ void igt_fork_signal_helper(void)
*/
void igt_stop_signal_helper(void)
{
- if (igt_only_list_subtests())
+ if (igt_only_collect_data())
return;
igt_stop_helper(&signal_helper);
@@ -375,7 +375,7 @@ static void __attribute__((noreturn))
shrink_helper_process(int fd, pid_t pid)
*/
void igt_fork_shrink_helper(int drm_fd)
{
- assert(!igt_only_list_subtests());
+ assert(!igt_only_collect_data());
igt_require(igt_drop_caches_has(drm_fd, DROP_SHRINK_ALL));
igt_fork_helper(&shrink_helper)
shrink_helper_process(drm_fd, getppid());
@@ -473,7 +473,7 @@ void igt_stop_hang_detector(void)
#else
void igt_fork_hang_detector(int fd)
{
- if (igt_only_list_subtests())
+ if (igt_only_collect_data())
return;
}
diff --git a/lib/igt_core.c b/lib/igt_core.c
index c0488e9..f1cb0e9 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -99,7 +99,7 @@
*
* To allow this i-g-t provides #igt_fixture code blocks for setup code outside
* of subtests and automatically skips the subtest code blocks themselves. For
- * special cases igt_only_list_subtests() is also provided. For setup code only
+ * special cases igt_only_collect_data() is also provided. For setup code only
* shared by a group of subtest encapsulate the #igt_fixture block and all the
* subtestest in a #igt_subtest_group block.
*
@@ -253,9 +253,9 @@ static unsigned int exit_handler_count;
const char *igt_interactive_debug;
/* subtests helpers */
-static bool list_subtests = false;
-static char *run_single_subtest = NULL;
-static bool run_single_subtest_found = false;
+static char *single_subtest = NULL;
+static bool single_subtest_found = false;
+static char *current_subtest_documentation = NULL;
static const char *in_subtest = NULL;
static struct timespec subtest_time;
static clockid_t igt_clock = (clockid_t)-1;
@@ -265,6 +265,13 @@ static bool in_atexit_handler = false;
static enum {
CONT = 0, SKIP, FAIL
} skip_subtests_henceforth = CONT;
+static enum {
+ EXECUTE_ALL,
+ EXECUTE_SINGLE,
+ LIST_SUBTESTS,
+ DOCUMENT,
+ DOCUMENT_SINGLE
+} runmode = EXECUTE_ALL;
bool __igt_plain_output = false;
@@ -277,6 +284,8 @@ bool test_child;
enum {
OPT_LIST_SUBTESTS,
OPT_RUN_SUBTEST,
+ OPT_DOC_SUBTESTS,
+ OPT_DOC_SINGLE_SUBTEST,
OPT_DESCRIPTION,
OPT_DEBUG,
OPT_INTERACTIVE_DEBUG,
@@ -469,7 +478,7 @@ bool __igt_fixture(void)
{
assert(!in_fixture);
- if (igt_only_list_subtests())
+ if (igt_only_collect_data())
return false;
if (skip_subtests_henceforth)
@@ -563,7 +572,7 @@ static void low_mem_killer_disable(bool disable)
bool igt_exit_called;
static void common_exit_handler(int sig)
{
- if (!igt_only_list_subtests()) {
+ if (!igt_only_collect_data()) {
low_mem_killer_disable(false);
kick_fbcon(true);
}
@@ -583,7 +592,7 @@ static void print_version(void)
{
struct utsname uts;
- if (list_subtests)
+ if (igt_only_collect_data())
return;
uname(&uts);
@@ -599,6 +608,8 @@ static void print_usage(const char *help_str, bool
output_on_stderr)
fprintf(f, "Usage: %s [OPTIONS]\n", command_str);
Re: [Intel-gfx] [PATCH i-g-t 1/2] Add support for subtest-specific documentation
On Wed, Aug 09, 2017 at 02:40:49PM +0300, Petri Latvala wrote:
> The current documentation for tests is limited to a single string per
> test binary. This patch adds support for documenting individual
> subtests.
>
> The syntax for subtest documentation is:
>
>igt_document_subtest("Frob knobs to see if one of the "
> "crossbeams will go out of skew on the "
> "treadle.\n");
>igt_subtest("knob-frobbing-askew")
> test_frob();
>
> or with a format string:
>
> for_example_loop(e) {
> igt_document_subtest_f("Frob %s to see if one of the "
>"crossbeams will go out of skew on the "
>"treadle.\n", e->readable_name);
> igt_subtest_f("%s-frob-askew", e->name)
> test_frob(e);
> }
>
> The documentation cannot be extracted from just comments, because
> associating them with the correct subtest name will then require doing
> pattern matching in the documentation generator, for subtests where
> the name is generated at runtime using igt_subtest_f.
>
> v2: Rebase, change function name in commit message to match code
>
> Signed-off-by: Petri Latvala
> Acked-by: Leo Li
I like approach of pairing the documentation 1:1 with subtests much
better than just having comments on top of internal functions (those
does not have to map directly onto subtests).
Bonus points for having it right above the igt_subtest_f() call and
making it easily accessible from the command line as those are the two
places developers and maintainers check first.
Acked-by: Arkadiusz Hiler
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[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave, drm/i915 fixes for v4.13-rc5. BR, Jani. The following changes since commit aae4e7a8bc44722fe70d58920a36916b1043195e: Linux 4.13-rc4 (2017-08-06 18:44:49 -0700) are available in the git repository at: git://anongit.freedesktop.org/git/drm-intel tags/drm-intel-fixes-2017-08-09-1 for you to fetch changes up to 1e2ba788787c86f527eca6ffd9adb97d691a810e: drm/i915: fix backlight invert for non-zero minimum brightness (2017-08-07 13:39:04 +0300) drm/i915 fixes for v4.13-rc5 Chris Wilson (1): drm/i915/shrinker: Wrap need_resched() inside preempt-disable Chuanxiao Dong (2): drm/i915/gvt: change resetting to resetting_eng drm/i915/gvt: clean workload queue if error happened Jani Nikula (2): Merge tag 'gvt-fixes-2017-08-07' of https://github.com/01org/gvt-linux into drm-intel-fixes drm/i915: fix backlight invert for non-zero minimum brightness Lionel Landwerlin (1): drm/i915/perf: fix flex eu registers programming Maarten Lankhorst (1): drm/i915: Fix out-of-bounds array access in bdw_load_gamma_lut Tina Zhang (1): drm/i915/gvt: Initialize MMIO Block with HW state Xiong Zhang (1): drm/i915/gvt: Change the max length of mmio_reg_rw from 4 to 8 drivers/gpu/drm/i915/gvt/execlist.c | 27 ++- drivers/gpu/drm/i915/gvt/firmware.c | 11 - drivers/gpu/drm/i915/gvt/gvt.h | 14 +++- drivers/gpu/drm/i915/gvt/handlers.c | 38 +++- drivers/gpu/drm/i915/gvt/scheduler.c | 3 ++- drivers/gpu/drm/i915/gvt/vgpu.c | 8 --- drivers/gpu/drm/i915/i915_gem_shrinker.c | 11 ++--- drivers/gpu/drm/i915/i915_perf.c | 4 ++-- drivers/gpu/drm/i915/intel_color.c | 1 + drivers/gpu/drm/i915/intel_panel.c | 2 +- 10 files changed, 82 insertions(+), 37 deletions(-) -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] lib: Add hooks for enabling ftrace
== Series Details == Series: series starting with [1/2] lib: Add hooks for enabling ftrace URL : https://patchwork.freedesktop.org/series/28491/ State : failure == Summary == IGT patchset build failed on latest successful build c129026622accef6f54c0cfb0dc55e930cfa60b5 igt: add syncobj_basic. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 2/2] lib/core: Don't leak dummyloads between subtests
If a test fails or skips early, it may not clean up after itself. In
lieu of having a framework for test deconstructors, hook
igt_terminate_spin_batches() into exit_subtest() itself so that we don't
allow a recursive batch from an earlier test to leak into the next and
cause an unexpected GPU hang.
Similarly, we also want to terminate the dummyload as the first step in
our atexit handlers (currently it is at the start of the last step) as
some atexit handlers may be unwittingly exposed to dummyloads and so
cause another wait on GPU hang.
We trust that the core already distinguishes correctly between the
principal test process and its children.
Signed-off-by: Chris Wilson
---
lib/igt_core.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/lib/igt_core.c b/lib/igt_core.c
index e1cab46f..77402267 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -63,6 +63,7 @@
#include "intel_chipset.h"
#include "intel_io.h"
#include "igt_debugfs.h"
+#include "igt_dummyload.h"
#include "igt_ftrace.h"
#include "igt_kcov.h"
#include "version.h"
@@ -1068,6 +1069,8 @@ static void exit_subtest(const char *result)
}
}
+ igt_terminate_spin_batches();
+
in_subtest = NULL;
siglongjmp(igt_subtest_jmpbuf, 1);
}
@@ -1872,6 +1875,8 @@ static void call_exit_handlers(int sig)
{
int i;
+ igt_terminate_spin_batches();
+
if (!exit_handler_count) {
return;
}
--
2.13.3
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[Intel-gfx] [PATCH igt 1/2] lib/dummyload: Wrap global list inside its own mutex
Give the list a mutex, for we try to iterate over it from many a random
context.
Signed-off-by: Chris Wilson
---
lib/igt_dummyload.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 5ad386a5..5d654825 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -50,6 +50,7 @@
static const int BATCH_SIZE = 4096;
static IGT_LIST(spin_list);
+static pthread_mutex_t list_lock = PTHREAD_MUTEX_INITIALIZER;
static void
fill_reloc(struct drm_i915_gem_relocation_entry *reloc,
@@ -162,7 +163,9 @@ __igt_spin_batch_new(int fd, uint32_t ctx, unsigned engine,
uint32_t dep)
emit_recursive_batch(spin, fd, ctx, engine, dep);
igt_assert(gem_bo_busy(fd, spin->handle));
+ pthread_mutex_lock(&list_lock);
igt_list_add(&spin->link, &spin_list);
+ pthread_mutex_unlock(&list_lock);
return spin;
}
@@ -261,7 +264,9 @@ void igt_spin_batch_free(int fd, igt_spin_t *spin)
if (!spin)
return;
+ pthread_mutex_lock(&list_lock);
igt_list_del(&spin->link);
+ pthread_mutex_unlock(&list_lock);
if (spin->timer)
timer_delete(spin->timer);
@@ -277,6 +282,8 @@ void igt_terminate_spin_batches(void)
{
struct igt_spin *iter;
+ pthread_mutex_lock(&list_lock);
igt_list_for_each(iter, &spin_list, link)
igt_spin_batch_end(iter);
+ pthread_mutex_unlock(&list_lock);
}
--
2.13.3
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Re: [Intel-gfx] [PATCH 1/6] drm/i915: Introduce intel_ddi_dp_level.
On Tue, 08 Aug 2017, Rodrigo Vivi wrote: > +static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp) Sorry to pick on specifically this patch when there continue to be offenders all over the place... but shouldn't we prefer the kernel types over standard C types? Not that checkpatch is an authority here, but with --strict it complains about using e.g. uint32_t. BR, Jani. -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for lib/kms: Clear unused fields for getproperty ioctl
== Series Details == Series: lib/kms: Clear unused fields for getproperty ioctl URL : https://patchwork.freedesktop.org/series/28546/ State : failure == Summary == IGT patchset tested on top of latest successful build c129026622accef6f54c0cfb0dc55e930cfa60b5 igt: add syncobj_basic. with latest DRM-Tip kernel build CI_DRM_2938 6da5aacea58f drm-tip: 2017y-08m-09d-10h-44m-50s UTC integration manifest Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: fail -> PASS (fi-snb-2600) fdo#100215 Test kms_flip: Subgroup basic-flip-vs-modeset: skip -> PASS (fi-skl-x1585l) fdo#101781 Test kms_pipe_crc_basic: Subgroup nonblocking-crc-pipe-c-frame-sequence: pass -> INCOMPLETE (fi-bxt-j4205) Subgroup suspend-read-crc-pipe-b: dmesg-warn -> PASS (fi-byt-n2820) fdo#101705 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781 fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705 fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:434s fi-bdw-gvtdvmtotal:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:416s fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:355s fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:494s fi-bxt-j4205 total:229 pass:212 dwarn:0 dfail:0 fail:0 skip:16 fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:520s fi-byt-n2820 total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:515s fi-glk-2atotal:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:582s fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:430s fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:404s fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:421s fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:499s fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:473s fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:460s fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:568s fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:578s fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:522s fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:451s fi-skl-6700k total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:644s fi-skl-6770hqtotal:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:459s fi-skl-gvtdvmtotal:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:426s fi-skl-x1585ltotal:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:488s fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:547s fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:411s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_39/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] lib: Add hooks for enabling ftrace
== Series Details == Series: series starting with [1/2] lib: Add hooks for enabling ftrace URL : https://patchwork.freedesktop.org/series/28491/ State : failure == Summary == IGT patchset build failed on latest successful build c129026622accef6f54c0cfb0dc55e930cfa60b5 igt: add syncobj_basic. Making check in lib make check-recursive Making check in . Making check in tests make igt_no_exit igt_no_exit_list_only igt_fork_helper igt_list_only igt_no_subtest igt_simulation igt_simple_test_subtests igt_stats igt_timeout igt_invalid_subtest_name igt_segfault igt_subtest_group igt_assert igt_exit_handler igt_hdmi_inject CC igt_no_exit.o CC igt_no_exit_list_only.o CC igt_fork_helper.o CC igt_list_only.o CC igt_no_subtest.o CC igt_simulation.o CC igt_simple_test_subtests.o CC igt_stats.o CC igt_timeout.o CC igt_invalid_subtest_name.o CC igt_subtest_group.o CC igt_segfault.o CC igt_assert.o CC igt_exit_handler.o CC igt_hdmi_inject.o CCLD igt_invalid_subtest_name CCLD igt_no_exit_list_only CCLD igt_no_exit CCLD igt_timeout CCLD igt_subtest_group CCLD igt_no_subtest CCLD igt_list_only CCLD igt_simple_test_subtests CCLD igt_segfault CCLD igt_fork_helper CCLD igt_simulation CCLD igt_hdmi_inject CCLD igt_exit_handler CCLD igt_assert CCLD igt_stats make check-TESTS PASS: igt_list_only XFAIL: igt_no_exit XFAIL: igt_no_exit_list_only FAIL: igt_segfault XFAIL: igt_no_subtest FAIL: igt_simulation FAIL: igt_exit_handler PASS: igt_fork_helper FAIL: igt_hdmi_inject XFAIL: igt_simple_test_subtests XFAIL: igt_timeout FAIL: igt_stats FAIL: igt_subtest_group FAIL: igt_assert XFAIL: igt_invalid_subtest_name Testsuite summary for intel-gpu-tools 1.19 # TOTAL: 15 # PASS: 2 # SKIP: 0 # XFAIL: 6 # FAIL: 7 # XPASS: 0 # ERROR: 0 See lib/tests/test-suite.log Please report to https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=IGT Makefile:983: recipe for target 'test-suite.log' failed Makefile:1089: recipe for target 'check-TESTS' failed Makefile:1260: recipe for target 'check-am' failed Makefile:716: recipe for target 'check-recursive' failed Makefile:865: recipe for target 'check' failed Makefile:528: recipe for target 'check-recursive' failed ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] Add support for subtest-specific documentation
== Series Details == Series: series starting with [1/2] Add support for subtest-specific documentation URL : https://patchwork.freedesktop.org/series/28554/ State : success == Summary == IGT patchset tested on top of latest successful build c129026622accef6f54c0cfb0dc55e930cfa60b5 igt: add syncobj_basic. with latest DRM-Tip kernel build CI_DRM_2938 6da5aacea58f drm-tip: 2017y-08m-09d-10h-44m-50s UTC integration manifest Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: pass -> FAIL (fi-snb-2600) fdo#17 Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: fail -> PASS (fi-snb-2600) fdo#100215 Test kms_flip: Subgroup basic-flip-vs-modeset: skip -> PASS (fi-skl-x1585l) fdo#101781 fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781 fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:433s fi-bdw-gvtdvmtotal:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:424s fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:361s fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:491s fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:494s fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:520s fi-glk-2atotal:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:582s fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:434s fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:405s fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:420s fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:508s fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:477s fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:459s fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:562s fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:574s fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:520s fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:452s fi-skl-6700k total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:640s fi-skl-6770hqtotal:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:462s fi-skl-gvtdvmtotal:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:433s fi-skl-x1585ltotal:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:490s fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:544s fi-snb-2600 total:279 pass:249 dwarn:0 dfail:0 fail:1 skip:29 time:409s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_40/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [maintainer-tools PATCH 1/7] dim: don't run add-missing-cc on merge commits
On Wed, 09 Aug 2017, Eric Engestrom wrote:
> get_maintainer.pl needs a diff, so this script can't run on a merge
> commit.
>
> Signed-off-by: Eric Engestrom
> ---
> dim | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/dim b/dim
> index 619d855b321b..af1baa11c7b2 100755
> --- a/dim
> +++ b/dim
> @@ -1960,6 +1960,11 @@ function dim_fixes
>
> function dim_add_missing_cc
> {
> + if [ $(git cat-file -p HEAD | grep -cE ^parent) -ne 1 ]; then
> + echoerr "This script doesn't work on merge commits"
To be pedantic, it's the subcommand that fails on merges, not the
script.
> + return
Please return 1.
BR,
Jani.
> + fi
> +
> git show | scripts/get_maintainer.pl --email --norolestats
> --pattern-depth 1 | while read cc; do
> email="$(echo "$cc" | sed -e 's/.*.*//')"
> name=''
--
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [maintainer-tools PATCH 2/7] dim: fix end-of-line in regex
On Wed, 09 Aug 2017, Eric Engestrom wrote:
> Signed-off-by: Eric Engestrom
> ---
> dim | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/dim b/dim
> index af1baa11c7b2..eaabcec43c8f 100755
> --- a/dim
> +++ b/dim
> @@ -1970,7 +1970,7 @@ function dim_add_missing_cc
> name=''
>
> if echo "$cc" | grep -q '<'; then
> - name="$(echo ${cc/<*/} | sed -e 's/[[:space:]]*\$//')";
> + name="$(echo ${cc/<*/} | sed -e 's/[[:space:]]*$//')";
What's the failure mode? It never nukes trailing space after all? Please
say so in the commit message.
BR,
Jani.
> fi
>
> # Don't add main mailing lists
> @@ -1988,7 +1988,7 @@ function dim_add_missing_cc
> if [ "$testemail" != "$email" ]; then
> if [ -z "$name" ]; then continue; fi
>
> - testname="$(echo ${testcc/<*/} | sed -e
> 's/[[:space:]]*\$//' -e 's/^[[:space:]]*//')"
> + testname="$(echo ${testcc/<*/} | sed -e
> 's/[[:space:]]*$//' -e 's/^[[:space:]]*//')"
>
> if [ "$testname" != "$name" ]; then
> continue; fi
> fi
--
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [maintainer-tools PATCH 3/7] dim: split out email parsing functions
On Wed, 09 Aug 2017, Eric Engestrom wrote:
> Signed-off-by: Eric Engestrom
> ---
> dim | 18 ++
> 1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/dim b/dim
> index eaabcec43c8f..a656afa0d255 100755
> --- a/dim
> +++ b/dim
> @@ -1958,6 +1958,16 @@ function dim_fixes
> fi
> }
>
> +function email_get_address
> +{
> + sed -e 's/.*.*//' <<< "$1"
> +}
> +
> +function email_get_name
> +{
> + echo ${cc/<*/} | sed -e 's/[[:space:]]*$//' <<< "$1"
I don't think the ${cc bit belongs in this function, even for the
transitional period until you fix it in a later patch.
BR,
Jani.
> +}
> +
> function dim_add_missing_cc
> {
> if [ $(git cat-file -p HEAD | grep -cE ^parent) -ne 1 ]; then
> @@ -1966,11 +1976,11 @@ function dim_add_missing_cc
> fi
>
> git show | scripts/get_maintainer.pl --email --norolestats
> --pattern-depth 1 | while read cc; do
> - email="$(echo "$cc" | sed -e 's/.*.*//')"
> + email="$(email_get_address "$cc")"
> name=''
>
> if echo "$cc" | grep -q '<'; then
> - name="$(echo ${cc/<*/} | sed -e 's/[[:space:]]*$//')";
> + name="$(email_get_name "$cc")";
> fi
>
> # Don't add main mailing lists
> @@ -1983,12 +1993,12 @@ function dim_add_missing_cc
> # print out a 1 on success
> matches=$(
> git show -s | grep -i "^Cc:" | sed 's/^ *[Cc][Cc]:
> *//' | while read testcc; do
> - testemail="$(echo "$testcc" | sed -e 's/.* -e 's/>.*//')"
> + testemail="$(email_get_address "$testcc")"
>
> if [ "$testemail" != "$email" ]; then
> if [ -z "$name" ]; then continue; fi
>
> - testname="$(echo ${testcc/<*/} | sed -e
> 's/[[:space:]]*$//' -e 's/^[[:space:]]*//')"
> + testname="$(email_get_name "$testcc" |
> sed -e 's/^[[:space:]]*//')"
>
> if [ "$testname" != "$name" ]; then
> continue; fi
> fi
--
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [dim PATCH] dim: drop rebuild-nightly alias
Let tab completion handle rebuild-tip better. If someone needs the old
alias, it can be placed in ~/.dimrc.
Signed-off-by: Jani Nikula
---
dim | 1 -
1 file changed, 1 deletion(-)
diff --git a/dim b/dim
index 619d855b321b..f576fca0488a 100755
--- a/dim
+++ b/dim
@@ -546,7 +546,6 @@ function commit_rerere_cache
fi
}
-dim_alias_rebuild_nightly=rebuild-tip
function dim_rebuild_tip
{
local integration_branch specfile time first rerere repo url remote
--
2.11.0
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] lib: Add hooks for enabling ftrace
== Series Details == Series: series starting with [1/2] lib: Add hooks for enabling ftrace URL : https://patchwork.freedesktop.org/series/28491/ State : failure == Summary == IGT patchset build failed on latest successful build c129026622accef6f54c0cfb0dc55e930cfa60b5 igt: add syncobj_basic. Making check in lib make check-recursive Making check in . Making check in tests make igt_no_exit igt_no_exit_list_only igt_fork_helper igt_list_only igt_no_subtest igt_simulation igt_simple_test_subtests igt_stats igt_timeout igt_invalid_subtest_name igt_segfault igt_subtest_group igt_assert igt_exit_handler igt_hdmi_inject CC igt_no_exit_list_only.o CC igt_no_exit.o CC igt_list_only.o CC igt_fork_helper.o CC igt_no_subtest.o CC igt_simulation.o CCLD igt_simple_test_subtests CC igt_segfault.o CCLD igt_stats CCLD igt_timeout CCLD igt_invalid_subtest_name CCLD igt_subtest_group CCLD igt_assert CC igt_hdmi_inject.o CCLD igt_exit_handler CCLD igt_no_subtest CCLD igt_no_exit_list_only CCLD igt_list_only CCLD igt_fork_helper CCLD igt_no_exit CCLD igt_segfault CCLD igt_simulation CCLD igt_hdmi_inject make check-TESTS PASS: igt_list_only XFAIL: igt_no_exit FAIL: igt_segfault XFAIL: igt_no_subtest XFAIL: igt_no_exit_list_only FAIL: igt_simulation PASS: igt_fork_helper FAIL: igt_exit_handler XFAIL: igt_timeout FAIL: igt_stats FAIL: igt_hdmi_inject XFAIL: igt_simple_test_subtests FAIL: igt_subtest_group FAIL: igt_assert XFAIL: igt_invalid_subtest_name Testsuite summary for intel-gpu-tools 1.19 # TOTAL: 15 # PASS: 2 # SKIP: 0 # XFAIL: 6 # FAIL: 7 # XPASS: 0 # ERROR: 0 See lib/tests/test-suite.log Please report to https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=IGT Makefile:983: recipe for target 'test-suite.log' failed Makefile:1089: recipe for target 'check-TESTS' failed Makefile:1260: recipe for target 'check-am' failed Makefile:716: recipe for target 'check-recursive' failed Makefile:865: recipe for target 'check' failed Makefile:528: recipe for target 'check-recursive' failed intel-gpu-tools 1.19: lib/tests/test-suite.log # TOTAL: 15 # PASS: 2 # SKIP: 0 # XFAIL: 6 # FAIL: 7 # XPASS: 0 # ERROR: 0 .. contents:: :depth: 2 XFAIL: igt_no_exit == IGT-Version: 1.19-g6913f219 (x86_64) (Linux: 4.10.0-28-generic x86_64) (igt_no_exit:10666) igt-debugfs-CRITICAL: Test assertion failure function is_mountpoint, file igt_debugfs.c:94: (igt_no_exit:10666) igt-debugfs-CRITICAL: Failed assertion: stat(buf, &st) == 0 (igt_no_exit:10666) igt-debugfs-CRITICAL: Last errno: 13, Permission denied (igt_no_exit:10666) igt-debugfs-CRITICAL: error: -1 != 0 Test igt_no_exit failed. DEBUG (igt_no_exit:10666) igt-debugfs-CRITICAL: Test assertion failure function is_mountpoint, file igt_debugfs.c:94: (igt_no_exit:10666) igt-debugfs-CRITICAL: Failed assertion: stat(buf, &st) == 0 (igt_no_exit:10666) igt-debugfs-CRITICAL: Last errno: 13, Permission denied (igt_no_exit:10666) igt-debugfs-CRITICAL: error: -1 != 0 END igt_no_exit: igt_core.c:1178: igt_fail: Assertion `!test_with_subtests || in_fixture' failed. Stack trace: #0 [__igt_fail_assert+0x101] #1 [igt_debugfs_mount+0x232] #2 [+0x232] XFAIL igt_no_exit (exit status: 134) XFAIL: igt_no_exit_list_only igt_no_exit_list_only: igt_core.c:576: common_exit_handler: Assertion `sig != 0 || igt_exit_called' failed. A XFAIL igt_no_exit_list_only (exit status: 134) XFAIL: igt_no_subtest = IGT-Version: 1.19-g6913f219 (x86_64) (Linux: 4.10.0-28-generic x86_64) (igt_no_subtest:10670) igt-debugfs-CRITICAL: Test assertion failure function is_mountpoint, file igt_debugfs.c:94: (igt_no_subtest:10670) igt-debugfs-CRITICAL: Failed assertion: stat(buf, &st) == 0 (igt_no_subtest:10670) igt-debugfs-CRITICAL: Last errno: 13, Permission denied (igt_no_subtest:10670) igt-debugfs-CRITICAL: error: -1 != 0 Test igt_no_exit failed. DEBUG (igt_no_subtest:10670) igt-debugfs-CRITICAL: Test assertion failure function is_mountpoint, file igt_debugfs.c:94: (igt_no_subtest:10670) igt-debugfs-CRITICAL: Failed assertion: stat(buf, &st) == 0 (igt_no_subtest:10670) igt-debugfs-CRITICAL: Last errno: 13, Permission denied (igt_no_subtest:10670) igt-debugfs-CRITICAL: error: -1 != 0 END igt_no_subtest: igt_core.c:1178: igt_fail: Assertion `!test_with_subtests || in_fixture' failed. Stack trace: #0 [__igt_fail_assert+0x101]
[Intel-gfx] [PATCH igt] lib/kms: Pass fd to igt_enable_connectors()
Pass the fd along to igt_enable_connectors() so that it actually dtrt
when there are multiple drm devices in the system.
Signed-off-by: Chris Wilson
---
lib/igt_kms.c| 13 -
lib/igt_kms.h| 2 +-
tests/kms_flip.c | 2 +-
tests/kms_invalid_dotclock.c | 2 +-
tests/kms_pipe_crc_basic.c | 2 +-
5 files changed, 8 insertions(+), 13 deletions(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 0c6dbf74..4ad16f13 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -3182,21 +3182,18 @@ void igt_wait_for_vblank(int drm_fd, enum pipe pipe)
* An exit handler is installed to ensure connectors are reset when the test
* exits.
*/
-void igt_enable_connectors(void)
+void igt_enable_connectors(int fd)
{
drmModeRes *res;
- int drm_fd;
- drm_fd = drm_open_driver(DRIVER_ANY);
-
- res = drmModeGetResources(drm_fd);
+ res = drmModeGetResources(fd);
igt_assert(res != NULL);
for (int i = 0; i < res->count_connectors; i++) {
drmModeConnector *c;
/* Do a probe. This may be the first action after booting */
- c = drmModeGetConnector(drm_fd, res->connectors[i]);
+ c = drmModeGetConnector(fd, res->connectors[i]);
if (!c) {
igt_warn("Could not read connector %u: %m\n",
res->connectors[i]);
continue;
@@ -3209,7 +3206,7 @@ void igt_enable_connectors(void)
/* just enable VGA for now */
if (c->connector_type == DRM_MODE_CONNECTOR_VGA) {
- if (!kmstest_force_connector(drm_fd, c,
FORCE_CONNECTOR_ON))
+ if (!kmstest_force_connector(fd, c, FORCE_CONNECTOR_ON))
igt_info("Unable to force state on %s-%d\n",
kmstest_connector_type_str(c->connector_type),
c->connector_type_id);
@@ -3217,8 +3214,6 @@ void igt_enable_connectors(void)
drmModeFreeConnector(c);
}
-
- close(drm_fd);
}
/**
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 4e7cd385..c2bc0d3a 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -539,7 +539,7 @@ static inline bool igt_output_is_connected(igt_output_t
*output)
igt_assert_lt(0, drmModeAtomicAddProperty(req,
output->config.connector->connector_id,\
output->config.atomic_props_connector[prop], value))
-void igt_enable_connectors(void);
+void igt_enable_connectors(int fd);
void igt_reset_connectors(void);
void igt_kms_disallow_hotplug(int fd);
diff --git a/tests/kms_flip.c b/tests/kms_flip.c
index 4210d663..81516def 100644
--- a/tests/kms_flip.c
+++ b/tests/kms_flip.c
@@ -1650,7 +1650,7 @@ int main(int argc, char **argv)
igt_fixture {
drm_fd = drm_open_driver_master(DRIVER_ANY);
- igt_enable_connectors();
+ igt_enable_connectors(drm_fd);
kmstest_set_vt_graphics_mode();
igt_install_exit_handler(kms_flip_exit_handler);
diff --git a/tests/kms_invalid_dotclock.c b/tests/kms_invalid_dotclock.c
index e6e72f52..b0942e59 100644
--- a/tests/kms_invalid_dotclock.c
+++ b/tests/kms_invalid_dotclock.c
@@ -131,7 +131,7 @@ igt_simple_main
data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
igt_require_intel(data.drm_fd);
- igt_enable_connectors();
+ igt_enable_connectors(data.drm_fd);
kmstest_set_vt_graphics_mode();
igt_display_init(&data.display, data.drm_fd);
data.res = drmModeGetResources(data.drm_fd);
diff --git a/tests/kms_pipe_crc_basic.c b/tests/kms_pipe_crc_basic.c
index 35adddba..bf51b4cb 100644
--- a/tests/kms_pipe_crc_basic.c
+++ b/tests/kms_pipe_crc_basic.c
@@ -185,7 +185,7 @@ igt_main
igt_fixture {
data.drm_fd = drm_open_driver_master(DRIVER_ANY);
- igt_enable_connectors();
+ igt_enable_connectors(data.drm_fd);
kmstest_set_vt_graphics_mode();
--
2.13.3
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Re: [Intel-gfx] [RFC i-g-t] tests/gem_exec_basic: Documentation for subtests
On Tue, 2017-08-08 at 15:09 -0700, Vinay Belgaumkar wrote:
> This is an RFC for adding documentation to IGT subtests. Each subtest can have
> something similar to a WHAT - explaining what the subtest actually does,
> and a WHY - which explains a use case, if applicable. Additionally,
> include comments for anything in the subtest code which can help
> explain HOW the test has been implemented. We don't actually need the WHAT
> and WHY tags in the documentation.
>
> These comments will not be linked to gtkdoc as of now, since we do not have a
> mechanism to link it to every subtest name.
>
> Signed-off-by: Vinay Belgaumkar
> Cc: Daniel Vetter
> Cc: Petri Latvala
> Cc: Chris Wilson
> ---
> tests/gem_exec_basic.c | 21 +
> 1 file changed, 21 insertions(+)
>
> diff --git a/tests/gem_exec_basic.c b/tests/gem_exec_basic.c
> index 2f057ef..b1491cd 100644
> --- a/tests/gem_exec_basic.c
> +++ b/tests/gem_exec_basic.c
> @@ -25,6 +25,11 @@
>
> IGT_TEST_DESCRIPTION("Basic sanity check of execbuf-ioctl rings.");
>
> +/*
> +(WHAT) This subtest submits an empty batch to each ring and verifies
> +that it is executed successfully
> +(WHY) It validates that GT buffer submission mechanism is functional
> +*/
> static void noop(int fd, unsigned ring)
> {
> uint32_t bbe = MI_BATCH_BUFFER_END;
> @@ -45,6 +50,11 @@ static void noop(int fd, unsigned ring)
> gem_close(fd, exec.handle);
> }
>
> +/*
> +(WHAT) This subtest memory maps a buffer, marks it as read only,
> +and submits it to each ring for execution.
> +(WHY) It helps us validate that the GT can execute read-only buffers
> +*/
> static void readonly(int fd, unsigned ring)
> {
> uint32_t bbe = MI_BATCH_BUFFER_END;
> @@ -57,12 +67,15 @@ static void readonly(int fd, unsigned ring)
> exec.handle = gem_create(fd, 4096);
> gem_write(fd, exec.handle, 0, &bbe, sizeof(bbe));
>
> + /* Memory map a buffer and use it as the execbuf to be submitted */
I am not convinced that comment describing what mmap does is needed. I think we
should not document what system calls do.
> execbuf = mmap(NULL, 4096, PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1,
> 0);
> igt_assert(execbuf != NULL);
>
> execbuf->buffers_ptr = to_user_pointer(&exec);
> execbuf->buffer_count = 1;
> execbuf->flags = ring;
> +
> + /* Now mark the buffer as read-only */
> igt_assert(mprotect(execbuf, 4096, PROT_READ) == 0);
Same as before - mprotect is a system call, this does not need any documentation
in my opinion. If there is a reason of making buffer read only that is not
obvious or not described in test description then it is worth stating why you
are marking it this way.
>
> gem_execbuf(fd, execbuf);
> @@ -70,6 +83,10 @@ static void readonly(int fd, unsigned ring)
> gem_close(fd, exec.handle);
> }
>
> +/*
> +(WHAT) Create a gtt mapped buffer and submit to the GPU.
> +(WHY) It ensures GPU can properly map and access GTT mapped buffers
> +*/
> static void gtt(int fd, unsigned ring)
> {
> uint32_t bbe = MI_BATCH_BUFFER_END;
> @@ -82,6 +99,8 @@ static void gtt(int fd, unsigned ring)
> handle = gem_create(fd, 4096);
>
> gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
> +
> + /* Create a memory mapping through GTT */
> execbuf = gem_mmap__gtt(fd, handle, 4096, PROT_WRITE);
> exec = (struct drm_i915_gem_exec_object2 *)(execbuf + 1);
> gem_close(fd, handle);
> @@ -108,6 +127,8 @@ igt_main
> fd = drm_open_driver(DRIVER_INTEL);
> igt_require_gem(fd);
>
> + /* Start the hang detector process. Test will fail
> + if a GPU hang is detected during any subtest */
> igt_fork_hang_detector(fd);
> }
>
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[Intel-gfx] [PULL] drm-misc-fixes
Hi Dave, Here's the -fixes pull for last week. Considering this is 2 weeks worth, it's pretty light. You might recognize some of these patches. The rockchip set and Chris' dma-buf patch were also applied to -misc-next. Misplaced patches continues to be the primary growing pain for the misc trees. I made a flowchart a few weeks ago to aid in the decision process, but it seems it hasn't gained traction yet. drm-misc-fixes-2017-08-08: Core Changes: - dma-buf: Allow multiple sync_files to wrap a single dma-fence (Chris) Driver Changes: - rockchip: misc fixes to vop driver from the downstream rockchip tree (Mark) - Error path cleanups to tc358767 & host1x (Lucas & Paul, respectively) Cheers, Sean The following changes since commit fea20995976f4b2e8968f852a18e280487d42f0d: gpu: host1x: Free the IOMMU domain when there is no device to attach (2017-07-27 16:57:34 +0200) are available in the git repository at: git://anongit.freedesktop.org/git/drm-misc tags/drm-misc-fixes-2017-08-08 for you to fetch changes up to 80c471ea040ad9006ebff6d64221a04e8fa1b7f6: drm/rockchip: vop: report error when check resource error (2017-08-04 15:39:32 +0800) Core Changes: - dma-buf: Allow multiple sync_files to wrap a single dma-fence (Chris) Driver Changes: - rockchip: misc fixes to vop driver from the downstream rockchip tree (Mark) - Error path cleanups to tc358767 & host1x (Lucas & Paul, respectively) Chris Wilson (1): dma-buf/sync_file: Allow multiple sync_files to wrap a single dma-fence Lucas Stach (1): drm/bridge: tc358767: fix probe without attached output node Mark yao (4): drm/rockchip: vop: fix iommu page fault when resume drm/rockchip: vop: fix NV12 video display error drm/rockchip: vop: round_up pitches to word align drm/rockchip: vop: report error when check resource error drivers/dma-buf/sync_file.c | 5 ++-- drivers/gpu/drm/bridge/tc358767.c | 2 +- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 41 ++--- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 3 +++ include/linux/sync_file.h | 3 ++- 5 files changed, 29 insertions(+), 25 deletions(-) -- Sean Paul, Software Engineer, Google / Chromium OS ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Allow HW status page to be bound high
On ti, 2017-08-08 at 13:54 +0100, Chris Wilson wrote:
> At the time of commit 1f767e02d69f ("drm/i915: HWS must be in the
> mappable region for g33"), drm_mm insertion would often default to
> placing a new object high in the zone forcing us to specify that certain
> HWSP must be bound within the low mappable region. Since then, drm_mm
> has gained more finesse over its placement and exposes that to the
> caller, commit 4e64e5539d15 ("drm: Improve drm_mm search (and fix
> topdown allocation) with rbtrees"). As such where possible we want the
> HWSP to be outside of the mappable aperture and so need to tell to
> specify that it is to be pinned high.
>
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Ville Syrjälä
> Cc: Michel Thierry
> Cc: Tvrtko Ursulin
> Cc: Mika Kuoppala
Reviewed-by: Joonas Lahtinen
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 1/8] drm/i915: Separate GuC/HuC specific functionality from intel_uc
On Wed, Aug 09, 2017 at 03:53:45PM +0530, Sagar Arun Kamble wrote:
> Removed unnecessary intel_uc.h includes as it is present in i915_drv.h.
> Created intel_guc.c and intel_guc.h for placing GuC specific code.
> Created intel_huc.h to refer to HuC specific functions.
>
> Cc: Chris Wilson
> Cc: Michal Wajdeczko
> Cc: Daniele Ceraolo Spurio
> Signed-off-by: Sagar Arun Kamble
> ---
> drivers/gpu/drm/i915/Makefile | 2 +
> drivers/gpu/drm/i915/i915_drv.c| 1 -
> drivers/gpu/drm/i915/i915_drv.h| 2 +
> drivers/gpu/drm/i915/i915_guc_submission.c | 1 -
> drivers/gpu/drm/i915/intel_guc.c | 184 ++
> drivers/gpu/drm/i915/intel_guc.h | 203
> +
> drivers/gpu/drm/i915/intel_guc_loader.c| 1 -
> drivers/gpu/drm/i915/intel_huc.c | 2 -
> drivers/gpu/drm/i915/intel_huc.h | 38 ++
> drivers/gpu/drm/i915/intel_uc.c| 159 +-
> drivers/gpu/drm/i915/intel_uc.h| 178 -
> 11 files changed, 430 insertions(+), 341 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/intel_guc.c
> create mode 100644 drivers/gpu/drm/i915/intel_guc.h
> create mode 100644 drivers/gpu/drm/i915/intel_huc.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index f822731..efa7605 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -58,6 +58,8 @@ i915-y += i915_cmd_parser.o \
>
> # general-purpose microcontroller (GuC) support
> i915-y += intel_uc.o \
> + intel_guc.o \
> + intel_huc.o \
Please leave intel_huc.o below, *after* all intel_guc... files
> intel_guc_ct.o \
> intel_guc_log.o \
> intel_guc_loader.o \
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 214555e..5512cce 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -50,7 +50,6 @@
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> #include "intel_drv.h"
> -#include "intel_uc.h"
>
> static struct drm_driver driver;
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2c7456f..085647a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -59,6 +59,8 @@
> #include "intel_bios.h"
> #include "intel_dpll_mgr.h"
> #include "intel_uc.h"
> +#include "intel_guc.h"
> +#include "intel_huc.h"
Hmm, I'm not sure this is right direction.
We should use intel_uc.h as super set of all our [gh]uc components.
> #include "intel_lrc.h"
> #include "intel_ringbuffer.h"
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
> b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 48a1e93..602ae8a 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -23,7 +23,6 @@
> */
> #include
> #include "i915_drv.h"
> -#include "intel_uc.h"
>
> #include
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.c
> b/drivers/gpu/drm/i915/intel_guc.c
> new file mode 100644
> index 000..a812d3d
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -0,0 +1,184 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include "i915_drv.h"
> +
> +inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
Why "static" was dropped ?
Also, please keep this function near other "send" functions
> +{
> + GEM_BUG_ON(!guc->send_regs.base);
> + GEM_BUG_ON(!guc->send_regs.count);
> + GEM_BUG_ON(i >= guc->send_regs.count);
> +
> + return _MMIO(guc->send_regs.base + 4 * i);
> +}
> +
> +void guc_capture_load_err_log(struct intel_guc *guc)
> +{
> + if (!guc->log.vma || i915.guc_log_level
Re: [Intel-gfx] [PATCH v13 5/7] vfio: ABI for mdev display dma-buf operation
On 8/8/2017 11:37 PM, Alex Williamson wrote:
> On Tue, 8 Aug 2017 14:18:07 +0530
> Kirti Wankhede wrote:
>
>> On 8/7/2017 11:13 PM, Alex Williamson wrote:
>>> On Mon, 7 Aug 2017 08:11:43 +
>>> "Zhang, Tina" wrote:
>>>
After going through the previous discussions, here are some summaries may
be related to the current discussion:
1. How does user mode figure the device capabilities between region and
dma-buf?
VFIO_DEVICE_GET_REGION_INFO could tell if the mdev supports region case.
Otherwise, the mdev supports dma-buf.
>>>
>>> Why do we need to make this assumption?
>>
>> Right, we should not make such assumption. Vendor driver might not
>> support both or disable console vnc ( for example, for performance
>> testing console VNC need to be disabled)
>>
>>> What happens when dma-buf is
>>> superseded? What happens if a device supports both dma-buf and
>>> regions? We have a flags field in vfio_device_gfx_plane_info, doesn't
>>> it make sense to use it to identify which field, between region_index
>>> and fd, is valid? We could even put region_index and fd into a union
>>> with the flag bits indicating how to interpret the union, but I'm not
>>> sure everyone was onboard with this idea. Seems like a waste of 4
>>> bytes not to do that though.
>>>
>>
>> Agree.
>>
>>> Thinking further, is the user ever in a situation where they query the
>>> graphics plane info and can handle either a dma-buf or a region? It
>>> seems more likely that the user needs to know early on which is
>>> supported and would then require that they continue to see compatible
>>> plane information... Should the user then be able to specify whether
>>> they want a dma-buf or a region? Perhaps these flag bits are actually
>>> input and the return should be -errno if the driver cannot produce
>>> something compatible.
>>>
>>> Maybe we'd therefore define 3 flag bits: PROBE, DMABUF, REGION. In
>>> this initial implementation, DMABUF or REGION would always be set by
>>> the user to request that type of interface. Additionally, the QUERY
>>> bit could be set to probe compatibility, thus if PROBE and REGION are
>>> set, the vendor driver would return success only if it supports the
>>> region based interface. If PROBE and DMABUF are set, the vendor driver
>>> returns success only if the dma-buf based interface is supported. The
>>> value of the remainder of the structure is undefined for PROBE.
>>> Additionally setting both DMABUF and REGION is invalid. Undefined
>>> flags bits must be validated as zero by the drivers for future use
>>> (thus if we later define DMABUFv2, an older driver should
>>> automatically return -errno when probed or requested).
>>>
>>
>> Are you saying all of this to be part of VFIO_DEVICE_QUERY_GFX_PLANE ioctl?
>>
>> Let me summarize what we need, taking QEMU as reference:
>> 1. From vfio_initfn(), for REGION case, get region info:
>> vfio_get_dev_region_info(.., VFIO_REGION_SUBTYPE_CONSOLE_REGION,
>> &vdev->console_opregion)
>>
>> If above return success, setup console REGION and mmap.
>> I don't know what is required for DMABUF at this moment.
>>
>> If console VNC is supported either DMABUF or REGION, initialize console
>> and register its callback operations:
>>
>> static const GraphicHwOps vfio_console_ops = {
>> .gfx_update = vfio_console_update_display,
>> };
>>
>> vdev->console = graphic_console_init(DEVICE(vdev), 0, &vfio_console_ops,
>> vdev);
>
> I might structure it that vfio_initfn() would call
> ioctl(VFIO_DEVICE_QUERY_GFX_PLANE) with the PROBE bit set with either
> DMABUF or REGION set as the interface type in the flags field. If
> REGION is the probed interface and success is returned, then QEMU might
> go look for regions of the appropriate type, however the
> vfio_device_gfx_plane_info structure is canonical source for the region
> index, so QEMU would probably be wise to use that and only use the
> region type for consistency testing.
>
>> 2. On above console registration, vfio_console_update_display() gets
>> called for each refresh cycle of console. In that:
>> - call ioctl(VFIO_DEVICE_QUERY_GFX_PLANE)
>> - if (queried size > 0), update QEMU console surface (for REGION case
>> read mmaped region, for DMABUF read surface using fd)
>
> The ioctl would be called with REGION or DMABUF based on the initial
> probe call, ex. we probed that REGION is supported and now we continue
> to ask for region based updates. QEMU would need to verify the region
> index matches that already mapped, remapping a different region if
> necessary, and interpret the graphics parameters to provide the screen
> update.
>
>> Alex, in your proposal above, my understanding is
>> ioctl(VFIO_DEVICE_QUERY_GFX_PLANE) with PROBE flag should be called in
>> step #1.
>> In step #2, ioctl(VFIO_DEVICE_QUERY_GFX_PLANE) will be without PROBE
>> flag, but either DMABUF or REGION flag based on what is returned as
>> supported by vendor driver in step #1. Is that correc
Re: [Intel-gfx] [RFC i-g-t] tests/gem_exec_basic: Documentation for subtests
On Tue, Aug 08, 2017 at 03:09:00PM -0700, Vinay Belgaumkar wrote: > This is an RFC for adding documentation to IGT subtests. Each subtest can have > something similar to a WHAT - explaining what the subtest actually does, > and a WHY - which explains a use case, if applicable. Additionally, > include comments for anything in the subtest code which can help > explain HOW the test has been implemented. We don't actually need the WHAT > and WHY tags in the documentation. > > These comments will not be linked to gtkdoc as of now, since we do not have a > mechanism to link it to every subtest name. Hey Vinay, I get similar feelings towards this RFC as Lukasz and Radek do. Was your intention to propose format of the comments? Or maybe force people to comment more on the code? Or just pointing out that we could use some subtest documentation? You are not documenting subtests, you are documenting arbitrary functions that may or may not be used as a subtest. I cannot help but feel lost here. Being explicit as of your intention and coming up with more abstract or better examples would also help, as current ones are detracting from the idea itself. I do not get this RFC and it's purpose but I am looking forward to seeing revised version that is clearer on your intentions and easier to grasp. -- Cheers, Arek ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/8] drm/i915/guc: Handle GuC HW/SW state cleanup in unload path
On Wed, Aug 09, 2017 at 03:53:47PM +0530, Sagar Arun Kamble wrote:
> Teardown of GuC HW/SW state was not properly done in unload path.
> During unload, we can rely on intel_guc_reset_prepare being done
> as part of i915_gem_suspend for disabling GuC interfaces.
> We will have to disable GuC submission prior to suspend as that involves
> communication with GuC to destroy doorbell. So intel_uc_fini_hw has to
> be called as part of i915_gem_suspend during unload as that really
> takes care of finishing the GuC operations. Created new parameter for
> i915_gem_suspend to handle unload/suspend path w.r.t gem and GuC suspend.
> GuC related allocations are cleaned up as part of intel_uc_cleanup_hw.
>
> Cc: Chris Wilson
> Cc: Michal Wajdeczko
> Cc: Daniele Ceraolo Spurio
> Signed-off-by: Sagar Arun Kamble
> ---
> drivers/gpu/drm/i915/i915_drv.c | 8
> drivers/gpu/drm/i915/i915_drv.h | 3 ++-
> drivers/gpu/drm/i915/i915_gem.c | 8 ++--
> drivers/gpu/drm/i915/intel_guc.c | 13 +
> drivers/gpu/drm/i915/intel_guc.h | 1 +
> drivers/gpu/drm/i915/intel_uc.c | 14 +-
> drivers/gpu/drm/i915/intel_uc.h | 1 +
> 7 files changed, 32 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 218a8e1..c3fb73f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -599,7 +599,7 @@ static void i915_gem_fini(struct drm_i915_private
> *dev_priv)
> i915_gem_drain_workqueue(dev_priv);
>
> mutex_lock(&dev_priv->drm.struct_mutex);
> - intel_uc_fini_hw(dev_priv);
> + intel_uc_cleanup_hw(dev_priv);
> i915_gem_cleanup_engines(dev_priv);
> i915_gem_contexts_fini(dev_priv);
> i915_gem_cleanup_userptr(dev_priv);
> @@ -680,7 +680,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
> return 0;
>
> cleanup_gem:
> - if (i915_gem_suspend(dev_priv))
> + if (i915_gem_suspend(dev_priv, true))
> DRM_ERROR("failed to idle hardware; continuing to unload!\n");
> i915_gem_fini(dev_priv);
> cleanup_uc:
> @@ -1373,7 +1373,7 @@ void i915_driver_unload(struct drm_device *dev)
>
> i915_driver_unregister(dev_priv);
>
> - if (i915_gem_suspend(dev_priv))
> + if (i915_gem_suspend(dev_priv, true))
> DRM_ERROR("failed to idle hardware; continuing to unload!\n");
>
> intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
> @@ -1518,7 +1518,7 @@ static int i915_drm_suspend(struct drm_device *dev)
>
> pci_save_state(pdev);
>
> - error = i915_gem_suspend(dev_priv);
> + error = i915_gem_suspend(dev_priv, false);
> if (error) {
> dev_err(&pdev->dev,
> "GEM idle failed, resume might fail\n");
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 085647a..dd6a3ff 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3547,7 +3547,8 @@ void i915_gem_reset_engine(struct intel_engine_cs
> *engine,
> void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
> int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
> unsigned int flags);
> -int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
> +int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv,
> + bool unload);
> void i915_gem_resume(struct drm_i915_private *dev_priv);
> int i915_gem_fault(struct vm_fault *vmf);
> int i915_gem_object_wait(struct drm_i915_gem_object *obj,
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index e118b9a..1b1b9c7 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4525,7 +4525,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
> }
> }
>
> -int i915_gem_suspend(struct drm_i915_private *dev_priv)
> +int i915_gem_suspend(struct drm_i915_private *dev_priv, bool unload)
This extra param is not very intuitive.
Can we have two public functions:
int i915_gem_suspend(struct drm_i915_private *dev_priv)
int i915_gem_unload(struct drm_i915_private *dev_priv)
> {
> struct drm_device *dev = &dev_priv->drm;
> int ret;
> @@ -4572,7 +4572,11 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
> WARN_ON(dev_priv->gt.awake);
> WARN_ON(!intel_engines_are_idle(dev_priv));
>
> - intel_guc_system_suspend(&dev_priv->guc);
> + /* Handle GuC suspension in case of unloading/system suspend */
> + if (unload)
> + intel_uc_fini_hw(dev_priv);
> + else
> + intel_guc_system_suspend(&dev_priv->guc);
>
> /*
>* Neither the BIOS, ourselves or any other kernel
> diff --git a/drivers/gpu/drm/i915/intel_guc.c
> b/drivers/gpu/drm/i915/intel_guc.c
> index 3777659..f4ddfbb 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> ++
[Intel-gfx] [PATCH] drm/i915/perf: Initialise dynamic sysfs group before creation
Another case where we need to call sysfs_attr_init() to setup the
internal lockdep class prior to use:
[9.325229] BUG: key 880168bc7bb0 not in .data!
[9.325240] DEBUG_LOCKS_WARN_ON(1)
[9.325250] [ cut here ]
[9.325280] WARNING: CPU: 1 PID: 275 at kernel/locking/lockdep.c:3156
lockdep_init_map+0x1b2/0x1c0
[9.325301] Modules linked in: intel_powerclamp(+) coretemp crct10dif_pclmul
crc32_pclmul ghash_clmulni_intel i915(+) snd_hda_intel snd_hda_codec snd_hwdep
r8169 mii snd_hda_core snd_pcm prime_numbers i2c_hid pinctrl_geminilake
pinctrl_intel
[9.325375] CPU: 1 PID: 275 Comm: modprobe Not tainted
4.13.0-rc4-CI-Trybot_1040+ #1
[9.325395] Hardware name: Intel Corp. Geminilake/GLK RVP2 LP4SD (07), BIOS
GELKRVPA.X64.0045.B51.1704281422 04/28/2017
[9.325422] task: 8801721a4ec0 task.stack: c91dc000
[9.325440] RIP: 0010:lockdep_init_map+0x1b2/0x1c0
[9.325456] RSP: 0018:c91dfa10 EFLAGS: 00010282
[9.325473] RAX: 0016 RBX: 880168d54b80 RCX:
[9.325488] RDX: 8001 RSI: 0001 RDI: 810f0800
[9.325505] RBP: c91dfa30 R08: 0001 R09:
[9.325521] R10: R11: R12: 880168bc7bb0
[9.325537] R13: R14: 880168bc7b98 R15: 81a263a0
[9.325554] FS: 7fb60c3fd700() GS:88017fc8()
knlGS:
[9.325574] CS: 0010 DS: ES: CR0: 80050033
[9.325588] CR2: 006582777d80 CR3: 00016d818000 CR4: 003406e0
[9.325604] Call Trace:
[9.325618] __kernfs_create_file+0x76/0xe0
[9.325632] sysfs_add_file_mode_ns+0x8a/0x1a0
[9.325646] internal_create_group+0xea/0x2c0
[9.325660] sysfs_create_group+0x13/0x20
[9.325737] i915_perf_register+0xde/0x220 [i915]
[9.325800] i915_driver_load+0xa77/0x16c0 [i915]
[9.325863] i915_pci_probe+0x37/0x90 [i915]
[9.325880] pci_device_probe+0xa8/0x130
[9.325894] driver_probe_device+0x29c/0x450
[9.325908] __driver_attach+0xe3/0xf0
[9.325922] ? driver_probe_device+0x450/0x450
[9.325935] bus_for_each_dev+0x62/0xa0
[9.325948] driver_attach+0x1e/0x20
[9.325960] bus_add_driver+0x173/0x270
[9.325974] driver_register+0x60/0xe0
[9.325986] __pci_register_driver+0x60/0x70
[9.326044] i915_init+0x6f/0x78 [i915]
[9.326066] ? 0xa024e000
[9.326079] do_one_initcall+0x43/0x170
[9.326094] ? rcu_read_lock_sched_held+0x7a/0x90
[9.326109] ? kmem_cache_alloc_trace+0x261/0x2d0
[9.326124] do_init_module+0x5f/0x206
[9.326137] load_module+0x2561/0x2da0
[9.326150] ? show_coresize+0x30/0x30
[9.326165] ? kernel_read_file+0x105/0x190
[9.326180] SyS_finit_module+0xc1/0x100
[9.326192] ? SyS_finit_module+0xc1/0x100
[9.326210] entry_SYSCALL_64_fastpath+0x1c/0xb1
[9.326223] RIP: 0033:0x7fb60bf359f9
[9.326234] RSP: 002b:7fff92b47c48 EFLAGS: 0246 ORIG_RAX:
0139
[9.326255] RAX: ffda RBX: 814898a3 RCX: 7fb60bf359f9
[9.326271] RDX: RSI: 0028a9ceef8b RDI:
[9.326287] RBP: c91dff88 R08: R09:
[9.326303] R10: R11: 0246 R12: 0004
[9.326319] R13: 0028aaef2a70 R14: R15: 0028aaeee5d0
[9.326339] ? __this_cpu_preempt_check+0x13/0x20
[9.326353] Code: f1 39 00 85 c0 0f 84 38 ff ff ff 83 3d 9f 44 ce 01 00 0f
85 2b ff ff ff 48 c7 c6 b2 a2 c7 81 48 c7 c7 53 40 c5 81 e8 3f 82 01 00 <0f> ff
e9 11 ff ff ff 0f 1f 80 00 00 00 00 55 31 c9 31 d2 31 f6
Fixes: 701f8231a2fe ("drm/i915/perf: prune OA configs")
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_perf.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e3e2663117e9..1be355d14e8a 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2908,8 +2908,7 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
if (!dev_priv->perf.metrics_kobj)
goto exit;
- memset(&dev_priv->perf.oa.test_config, 0,
- sizeof(dev_priv->perf.oa.test_config));
+ sysfs_attr_init(&dev_priv->perf.oa.test_config.sysfs_metric_id.attr);
if (IS_HASWELL(dev_priv)) {
i915_perf_load_test_config_hsw(dev_priv);
--
2.13.3
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/perf: Initialise dynamic sysfs group before creation
Right, that's exactly what I was asking in our previous exchange.
You need to leave the memset() I think, because we check further down
that function that id == 0 to detect failure to recognize that the (Gen,
GT) is supported.
Unless there is a guarantee that dev_priv is fully memset()?
Thanks a lot,
-
Lionel
On 09/08/17 15:47, Chris Wilson wrote:
Another case where we need to call sysfs_attr_init() to setup the
internal lockdep class prior to use:
[9.325229] BUG: key 880168bc7bb0 not in .data!
[9.325240] DEBUG_LOCKS_WARN_ON(1)
[9.325250] [ cut here ]
[9.325280] WARNING: CPU: 1 PID: 275 at kernel/locking/lockdep.c:3156
lockdep_init_map+0x1b2/0x1c0
[9.325301] Modules linked in: intel_powerclamp(+) coretemp crct10dif_pclmul
crc32_pclmul ghash_clmulni_intel i915(+) snd_hda_intel snd_hda_codec snd_hwdep
r8169 mii snd_hda_core snd_pcm prime_numbers i2c_hid pinctrl_geminilake
pinctrl_intel
[9.325375] CPU: 1 PID: 275 Comm: modprobe Not tainted
4.13.0-rc4-CI-Trybot_1040+ #1
[9.325395] Hardware name: Intel Corp. Geminilake/GLK RVP2 LP4SD (07), BIOS
GELKRVPA.X64.0045.B51.1704281422 04/28/2017
[9.325422] task: 8801721a4ec0 task.stack: c91dc000
[9.325440] RIP: 0010:lockdep_init_map+0x1b2/0x1c0
[9.325456] RSP: 0018:c91dfa10 EFLAGS: 00010282
[9.325473] RAX: 0016 RBX: 880168d54b80 RCX:
[9.325488] RDX: 8001 RSI: 0001 RDI: 810f0800
[9.325505] RBP: c91dfa30 R08: 0001 R09:
[9.325521] R10: R11: R12: 880168bc7bb0
[9.325537] R13: R14: 880168bc7b98 R15: 81a263a0
[9.325554] FS: 7fb60c3fd700() GS:88017fc8()
knlGS:
[9.325574] CS: 0010 DS: ES: CR0: 80050033
[9.325588] CR2: 006582777d80 CR3: 00016d818000 CR4: 003406e0
[9.325604] Call Trace:
[9.325618] __kernfs_create_file+0x76/0xe0
[9.325632] sysfs_add_file_mode_ns+0x8a/0x1a0
[9.325646] internal_create_group+0xea/0x2c0
[9.325660] sysfs_create_group+0x13/0x20
[9.325737] i915_perf_register+0xde/0x220 [i915]
[9.325800] i915_driver_load+0xa77/0x16c0 [i915]
[9.325863] i915_pci_probe+0x37/0x90 [i915]
[9.325880] pci_device_probe+0xa8/0x130
[9.325894] driver_probe_device+0x29c/0x450
[9.325908] __driver_attach+0xe3/0xf0
[9.325922] ? driver_probe_device+0x450/0x450
[9.325935] bus_for_each_dev+0x62/0xa0
[9.325948] driver_attach+0x1e/0x20
[9.325960] bus_add_driver+0x173/0x270
[9.325974] driver_register+0x60/0xe0
[9.325986] __pci_register_driver+0x60/0x70
[9.326044] i915_init+0x6f/0x78 [i915]
[9.326066] ? 0xa024e000
[9.326079] do_one_initcall+0x43/0x170
[9.326094] ? rcu_read_lock_sched_held+0x7a/0x90
[9.326109] ? kmem_cache_alloc_trace+0x261/0x2d0
[9.326124] do_init_module+0x5f/0x206
[9.326137] load_module+0x2561/0x2da0
[9.326150] ? show_coresize+0x30/0x30
[9.326165] ? kernel_read_file+0x105/0x190
[9.326180] SyS_finit_module+0xc1/0x100
[9.326192] ? SyS_finit_module+0xc1/0x100
[9.326210] entry_SYSCALL_64_fastpath+0x1c/0xb1
[9.326223] RIP: 0033:0x7fb60bf359f9
[9.326234] RSP: 002b:7fff92b47c48 EFLAGS: 0246 ORIG_RAX:
0139
[9.326255] RAX: ffda RBX: 814898a3 RCX: 7fb60bf359f9
[9.326271] RDX: RSI: 0028a9ceef8b RDI:
[9.326287] RBP: c91dff88 R08: R09:
[9.326303] R10: R11: 0246 R12: 0004
[9.326319] R13: 0028aaef2a70 R14: R15: 0028aaeee5d0
[9.326339] ? __this_cpu_preempt_check+0x13/0x20
[9.326353] Code: f1 39 00 85 c0 0f 84 38 ff ff ff 83 3d 9f 44 ce 01 00 0f 85 2b
ff ff ff 48 c7 c6 b2 a2 c7 81 48 c7 c7 53 40 c5 81 e8 3f 82 01 00 <0f> ff e9 11
ff ff ff 0f 1f 80 00 00 00 00 55 31 c9 31 d2 31 f6
Fixes: 701f8231a2fe ("drm/i915/perf: prune OA configs")
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_perf.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e3e2663117e9..1be355d14e8a 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2908,8 +2908,7 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
if (!dev_priv->perf.metrics_kobj)
goto exit;
- memset(&dev_priv->perf.oa.test_config, 0,
- sizeof(dev_priv->perf.oa.test_config));
+ sysfs_attr_init(&dev_priv->perf.oa.test_config.sysfs_metric_id.attr);
if (IS_HASWELL(dev_priv)) {
i915_perf_load_test_config_hsw(dev_priv);
___
Re: [Intel-gfx] [PATCH] drm/i915/perf: Initialise dynamic sysfs group before creation
Quoting Lionel Landwerlin (2017-08-09 15:57:59) > Right, that's exactly what I was asking in our previous exchange. I just follow the traces, and am internally screaming at how much we are stuffing inside drm_i915_private nowadays. > You need to leave the memset() I think, because we check further down It is already zeroed. > that function that id == 0 to detect failure to recognize that the (Gen, > GT) is supported. > Unless there is a guarantee that dev_priv is fully memset()? It is allocated using kzalloc() and we depend upon that in many, many places. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/perf: Initialise dynamic sysfs group before creation
On 09/08/17 16:02, Chris Wilson wrote:
Quoting Lionel Landwerlin (2017-08-09 15:57:59)
Right, that's exactly what I was asking in our previous exchange.
I just follow the traces, and am internally screaming at how much we are
stuffing inside drm_i915_private nowadays.
You need to leave the memset() I think, because we check further down
It is already zeroed.
that function that id == 0 to detect failure to recognize that the (Gen,
GT) is supported.
Unless there is a guarantee that dev_priv is fully memset()?
It is allocated using kzalloc() and we depend upon that in many, many
places.
-Chris
Cool,
Fixes: f89823c21224 ("drm/i915/perf: Implement
I915_PERF_ADD/REMOVE_CONFIG interface")
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/perf: Initialise dynamic sysfs group before creation
On 09/08/17 16:14, Lionel Landwerlin wrote:
On 09/08/17 16:02, Chris Wilson wrote:
Quoting Lionel Landwerlin (2017-08-09 15:57:59)
Right, that's exactly what I was asking in our previous exchange.
I just follow the traces, and am internally screaming at how much we are
stuffing inside drm_i915_private nowadays.
You need to leave the memset() I think, because we check further down
It is already zeroed.
that function that id == 0 to detect failure to recognize that the
(Gen,
GT) is supported.
Unless there is a guarantee that dev_priv is fully memset()?
It is allocated using kzalloc() and we depend upon that in many, many
places.
-Chris
Cool,
Fixes: f89823c21224 ("drm/i915/perf: Implement
I915_PERF_ADD/REMOVE_CONFIG interface")
The line above is wrong and not what I wanted to write... :
Reviewed-by: Lionel Landwerlin
___
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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/perf: Initialise dynamic sysfs group before creation
== Series Details == Series: drm/i915/perf: Initialise dynamic sysfs group before creation URL : https://patchwork.freedesktop.org/series/28560/ State : warning == Summary == Series 28560v1 drm/i915/perf: Initialise dynamic sysfs group before creation https://patchwork.freedesktop.org/api/1.0/series/28560/revisions/1/mbox/ Test gem_busy: Subgroup basic-hang-default: pass -> DMESG-WARN (fi-bdw-5557u) pass -> DMESG-WARN (fi-bdw-gvtdvm) pass -> DMESG-WARN (fi-bsw-n3050) pass -> DMESG-WARN (fi-skl-6260u) pass -> DMESG-WARN (fi-skl-6700k) pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-skl-gvtdvm) pass -> DMESG-WARN (fi-skl-x1585l) pass -> DMESG-WARN (fi-kbl-7500u) pass -> DMESG-WARN (fi-kbl-7560u) pass -> DMESG-WARN (fi-kbl-r) pass -> DMESG-WARN (fi-glk-2a) Test gem_exec_fence: Subgroup await-hang-default: pass -> DMESG-WARN (fi-bdw-5557u) pass -> DMESG-WARN (fi-bdw-gvtdvm) pass -> DMESG-WARN (fi-bsw-n3050) pass -> DMESG-WARN (fi-skl-6260u) pass -> DMESG-WARN (fi-skl-6700k) pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-skl-gvtdvm) pass -> DMESG-WARN (fi-skl-x1585l) pass -> DMESG-WARN (fi-kbl-7500u) pass -> DMESG-WARN (fi-kbl-7560u) pass -> DMESG-WARN (fi-kbl-r) pass -> DMESG-WARN (fi-glk-2a) Test gem_exec_suspend: Subgroup basic-s4-devices: pass -> INCOMPLETE (fi-pnv-d510) fdo#102065 Test kms_flip: Subgroup basic-flip-vs-modeset: pass -> SKIP (fi-skl-x1585l) fdo#101781 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: dmesg-warn -> PASS (fi-byt-n2820) fdo#101705 fdo#102065 https://bugs.freedesktop.org/show_bug.cgi?id=102065 fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781 fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705 fi-bdw-5557u total:279 pass:266 dwarn:2 dfail:0 fail:0 skip:11 time:456s fi-bdw-gvtdvmtotal:279 pass:263 dwarn:2 dfail:0 fail:0 skip:14 time:436s fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:358s fi-bsw-n3050 total:279 pass:241 dwarn:2 dfail:0 fail:0 skip:36 time:538s fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:519s fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:522s fi-byt-n2820 total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:510s fi-glk-2atotal:279 pass:258 dwarn:2 dfail:0 fail:0 skip:19 time:598s fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:443s fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:422s fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:420s fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:503s fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:483s fi-kbl-7500u total:279 pass:259 dwarn:2 dfail:0 fail:0 skip:18 time:477s fi-kbl-7560u total:279 pass:267 dwarn:2 dfail:0 fail:0 skip:10 time:587s fi-kbl-r total:279 pass:259 dwarn:2 dfail:0 fail:0 skip:18 time:591s fi-pnv-d510 total:110 pass:77 dwarn:0 dfail:0 fail:0 skip:32 fi-skl-6260u total:279 pass:267 dwarn:2 dfail:0 fail:0 skip:10 time:461s fi-skl-6700k total:279 pass:259 dwarn:2 dfail:0 fail:0 skip:18 time:474s fi-skl-6770hqtotal:279 pass:267 dwarn:2 dfail:0 fail:0 skip:10 time:479s fi-skl-gvtdvmtotal:279 pass:264 dwarn:2 dfail:0 fail:0 skip:13 time:440s fi-skl-x1585ltotal:279 pass:266 dwarn:2 dfail:0 fail:0 skip:11 time:475s fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:550s fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:407s 77b1bb6a1c72df55182beb47faf0df25918c6698 drm-tip: 2017y-08m-09d-14h-36m-30s UTC integration manifest a35e33ea8b25 drm/i915/perf: Initialise dynamic sysfs group before creation == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5349/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/perf: Initialise dynamic sysfs group before creation
Another case where we need to call sysfs_attr_init() to setup the
internal lockdep class prior to use:
[9.325229] BUG: key 880168bc7bb0 not in .data!
[9.325240] DEBUG_LOCKS_WARN_ON(1)
[9.325250] [ cut here ]
[9.325280] WARNING: CPU: 1 PID: 275 at kernel/locking/lockdep.c:3156
lockdep_init_map+0x1b2/0x1c0
[9.325301] Modules linked in: intel_powerclamp(+) coretemp crct10dif_pclmul
crc32_pclmul ghash_clmulni_intel i915(+) snd_hda_intel snd_hda_codec snd_hwdep
r8169 mii snd_hda_core snd_pcm prime_numbers i2c_hid pinctrl_geminilake
pinctrl_intel
[9.325375] CPU: 1 PID: 275 Comm: modprobe Not tainted
4.13.0-rc4-CI-Trybot_1040+ #1
[9.325395] Hardware name: Intel Corp. Geminilake/GLK RVP2 LP4SD (07), BIOS
GELKRVPA.X64.0045.B51.1704281422 04/28/2017
[9.325422] task: 8801721a4ec0 task.stack: c91dc000
[9.325440] RIP: 0010:lockdep_init_map+0x1b2/0x1c0
[9.325456] RSP: 0018:c91dfa10 EFLAGS: 00010282
[9.325473] RAX: 0016 RBX: 880168d54b80 RCX:
[9.325488] RDX: 8001 RSI: 0001 RDI: 810f0800
[9.325505] RBP: c91dfa30 R08: 0001 R09:
[9.325521] R10: R11: R12: 880168bc7bb0
[9.325537] R13: R14: 880168bc7b98 R15: 81a263a0
[9.325554] FS: 7fb60c3fd700() GS:88017fc8()
knlGS:
[9.325574] CS: 0010 DS: ES: CR0: 80050033
[9.325588] CR2: 006582777d80 CR3: 00016d818000 CR4: 003406e0
[9.325604] Call Trace:
[9.325618] __kernfs_create_file+0x76/0xe0
[9.325632] sysfs_add_file_mode_ns+0x8a/0x1a0
[9.325646] internal_create_group+0xea/0x2c0
[9.325660] sysfs_create_group+0x13/0x20
[9.325737] i915_perf_register+0xde/0x220 [i915]
[9.325800] i915_driver_load+0xa77/0x16c0 [i915]
[9.325863] i915_pci_probe+0x37/0x90 [i915]
[9.325880] pci_device_probe+0xa8/0x130
[9.325894] driver_probe_device+0x29c/0x450
[9.325908] __driver_attach+0xe3/0xf0
[9.325922] ? driver_probe_device+0x450/0x450
[9.325935] bus_for_each_dev+0x62/0xa0
[9.325948] driver_attach+0x1e/0x20
[9.325960] bus_add_driver+0x173/0x270
[9.325974] driver_register+0x60/0xe0
[9.325986] __pci_register_driver+0x60/0x70
[9.326044] i915_init+0x6f/0x78 [i915]
[9.326066] ? 0xa024e000
[9.326079] do_one_initcall+0x43/0x170
[9.326094] ? rcu_read_lock_sched_held+0x7a/0x90
[9.326109] ? kmem_cache_alloc_trace+0x261/0x2d0
[9.326124] do_init_module+0x5f/0x206
[9.326137] load_module+0x2561/0x2da0
[9.326150] ? show_coresize+0x30/0x30
[9.326165] ? kernel_read_file+0x105/0x190
[9.326180] SyS_finit_module+0xc1/0x100
[9.326192] ? SyS_finit_module+0xc1/0x100
[9.326210] entry_SYSCALL_64_fastpath+0x1c/0xb1
[9.326223] RIP: 0033:0x7fb60bf359f9
[9.326234] RSP: 002b:7fff92b47c48 EFLAGS: 0246 ORIG_RAX:
0139
[9.326255] RAX: ffda RBX: 814898a3 RCX: 7fb60bf359f9
[9.326271] RDX: RSI: 0028a9ceef8b RDI:
[9.326287] RBP: c91dff88 R08: R09:
[9.326303] R10: R11: 0246 R12: 0004
[9.326319] R13: 0028aaef2a70 R14: R15: 0028aaeee5d0
[9.326339] ? __this_cpu_preempt_check+0x13/0x20
[9.326353] Code: f1 39 00 85 c0 0f 84 38 ff ff ff 83 3d 9f 44 ce 01 00 0f
85 2b ff ff ff 48 c7 c6 b2 a2 c7 81 48 c7 c7 53 40 c5 81 e8 3f 82 01 00 <0f> ff
e9 11 ff ff ff 0f 1f 80 00 00 00 00 55 31 c9 31 d2 31 f6
Fixes: 701f8231a2fe ("drm/i915/perf: prune OA configs")
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_perf.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e3e2663117e9..1be355d14e8a 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2908,8 +2908,7 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
if (!dev_priv->perf.metrics_kobj)
goto exit;
- memset(&dev_priv->perf.oa.test_config, 0,
- sizeof(dev_priv->perf.oa.test_config));
+ sysfs_attr_init(&dev_priv->perf.oa.test_config.sysfs_metric_id.attr);
if (IS_HASWELL(dev_priv)) {
i915_perf_load_test_config_hsw(dev_priv);
--
2.13.3
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[Intel-gfx] [PATCH 2/2] drm/i915/perf: Drop lockdep assert for i915_oa_init_reg_state()
This is called from execlist context init which we need to be unlocked.
Commit f89823c21224 ("drm/i915/perf: Implement
I915_PERF_ADD/REMOVE_CONFIG interface") added a lockdep assert to this
path for unclear reasons, remove it again!
Fixes: 701f8231a2fe ("drm/i915/perf: prune OA configs")
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_perf.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 1be355d14e8a..3bdf53faae24 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2173,8 +2173,6 @@ void i915_oa_init_reg_state(struct intel_engine_cs
*engine,
struct drm_i915_private *dev_priv = engine->i915;
struct i915_perf_stream *stream = dev_priv->perf.oa.exclusive_stream;
- lockdep_assert_held(&dev_priv->drm.struct_mutex);
-
if (engine->id != RCS)
return;
--
2.13.3
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[Intel-gfx] [PATCH] drm/i915/perf: Drop redundant check for perf.initialised on reset
As we cannot have an exclusive stream set if the perf has not been
initialized, we only need to check for that exclusive stream.
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_perf.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 3bdf53faae24..94185d610673 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2170,15 +2170,12 @@ void i915_oa_init_reg_state(struct intel_engine_cs
*engine,
struct i915_gem_context *ctx,
u32 *reg_state)
{
- struct drm_i915_private *dev_priv = engine->i915;
- struct i915_perf_stream *stream = dev_priv->perf.oa.exclusive_stream;
+ struct i915_perf_stream *stream;
if (engine->id != RCS)
return;
- if (!dev_priv->perf.initialized)
- return;
-
+ stream = engine->i915->perf.oa.exclusive_stream;
if (stream)
gen8_update_reg_state_unlocked(ctx, reg_state,
stream->oa_config);
}
--
2.13.3
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/perf: Drop redundant check for perf.initialised on reset
== Series Details == Series: drm/i915/perf: Drop redundant check for perf.initialised on reset URL : https://patchwork.freedesktop.org/series/28564/ State : failure == Summary == CHK include/config/kernel.release CHK include/generated/uapi/linux/version.h CHK include/generated/utsrelease.h CHK include/generated/bounds.h CHK include/generated/timeconst.h CHK include/generated/asm-offsets.h CALLscripts/checksyscalls.sh CHK scripts/mod/devicetable-offsets.h CHK include/generated/compile.h CHK kernel/config_data.h CC [M] drivers/gpu/drm/i915/i915_perf.o In file included from ./arch/x86/include/asm/bug.h:81:0, from ./include/linux/bug.h:4, from ./include/linux/mmdebug.h:4, from ./include/linux/gfp.h:4, from ./include/linux/slab.h:14, from ./include/linux/io-mapping.h:22, from drivers/gpu/drm/i915/i915_drv.h:36, from drivers/gpu/drm/i915/i915_perf.c:198: drivers/gpu/drm/i915/i915_perf.c: In function ‘i915_oa_init_reg_state’: drivers/gpu/drm/i915/i915_perf.c:2175:23: error: ‘dev_priv’ undeclared (first use in this function) lockdep_assert_held(&dev_priv->drm.struct_mutex); ^ ./include/asm-generic/bug.h:116:25: note: in definition of macro ‘WARN’ int __ret_warn_on = !!(condition);\ ^ ./include/linux/lockdep.h:383:3: note: in expansion of macro ‘WARN_ON’ WARN_ON(debug_locks && !lockdep_is_held(l)); \ ^~~ ./include/linux/lockdep.h:383:27: note: in expansion of macro ‘lockdep_is_held’ WARN_ON(debug_locks && !lockdep_is_held(l)); \ ^~~ drivers/gpu/drm/i915/i915_perf.c:2175:2: note: in expansion of macro ‘lockdep_assert_held’ lockdep_assert_held(&dev_priv->drm.struct_mutex); ^~~ drivers/gpu/drm/i915/i915_perf.c:2175:23: note: each undeclared identifier is reported only once for each function it appears in lockdep_assert_held(&dev_priv->drm.struct_mutex); ^ ./include/asm-generic/bug.h:116:25: note: in definition of macro ‘WARN’ int __ret_warn_on = !!(condition);\ ^ ./include/linux/lockdep.h:383:3: note: in expansion of macro ‘WARN_ON’ WARN_ON(debug_locks && !lockdep_is_held(l)); \ ^~~ ./include/linux/lockdep.h:383:27: note: in expansion of macro ‘lockdep_is_held’ WARN_ON(debug_locks && !lockdep_is_held(l)); \ ^~~ drivers/gpu/drm/i915/i915_perf.c:2175:2: note: in expansion of macro ‘lockdep_assert_held’ lockdep_assert_held(&dev_priv->drm.struct_mutex); ^~~ scripts/Makefile.build:302: recipe for target 'drivers/gpu/drm/i915/i915_perf.o' failed make[4]: *** [drivers/gpu/drm/i915/i915_perf.o] Error 1 scripts/Makefile.build:561: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:561: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:561: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1019: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 6/8] dmi: Move memdev_dmi_entry definition to dmi.h (v2)
On Mon, Jul 31, 2017 at 10:36:05AM +0200, Jean Delvare wrote: > Hi Matt, Mauro, > > On Thu, 17 Mar 2016 15:18:20 +0100, Jean Delvare wrote: > > On Tue, 8 Mar 2016 10:32:37 -0800, Matt Roper wrote: > > > A couple of the EDAC drivers have a nice memdev_dmi_entry structure for > > > decoding DMI memory device entries. Move the structure definition to > > > dmi.h so that it can be shared between those drivers and also other > > > parts of the kernel; the i915 graphics driver is going to need to use > > > this structure soon as well. As part of this move we rename the > > > structure s/memdev_dmi_entry/dmi_entry_memdev/ to ensure it has a proper > > > 'dmi' prefix. > > > > > > v2: > > > - Rename structure to dmi_entry_memdev. (Jean) > > > - Use __packed instead of __attribute__((__packed__)) for consistency > > >with the rest of the dmi.h header. (Jean) > > > > Looks better. (...) > > What happened to this patch? I never received v3. Is it sill needed? We ended up going a different direction in the graphics driver and wound up not needing access to this structure. If there's still interest in the general refactoring here, let me know and I can incorporate your last feedback and respin a v3. Matt > -- > Jean Delvare > SUSE L3 Support -- Matt Roper Graphics Software Engineer IoTG Platform Enabling & Development Intel Corporation (916) 356-2795 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 14/16] drm/i915/guc: Enable GuC interrupts when using CT
We will need them in G2H communication to properly handle
responses and requests from the Guc.
v2: keep irq enabled while disabling GuC logging (Oscar)
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
---
drivers/gpu/drm/i915/i915_guc_submission.c | 2 +-
drivers/gpu/drm/i915/intel_guc_log.c | 10 ++
drivers/gpu/drm/i915/intel_uc.c| 2 +-
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 48a1e93..509497e 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1328,7 +1328,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
- if (i915.guc_log_level >= 0)
+ if (HAS_GUC_CT(dev_priv) || i915.guc_log_level >= 0)
gen9_enable_guc_interrupts(dev_priv);
ctx = dev_priv->kernel_context;
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c
b/drivers/gpu/drm/i915/intel_guc_log.c
index acd9a3f..64fb879 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -505,8 +505,9 @@ static void guc_flush_logs(struct intel_guc *guc)
if (!i915.enable_guc_submission || (i915.guc_log_level < 0))
return;
- /* First disable the interrupts, will be renabled afterwards */
- gen9_disable_guc_interrupts(dev_priv);
+ /* GuC logging maybe the only user of Guc2Host interrupts */
+ if (!HAS_GUC_CT(dev_priv))
+ gen9_disable_guc_interrupts(dev_priv);
/* Before initiating the forceful flush, wait for any pending/ongoing
* flush to complete otherwise forceful flush may not actually happen.
@@ -663,8 +664,9 @@ void i915_guc_log_unregister(struct drm_i915_private
*dev_priv)
return;
mutex_lock(&dev_priv->drm.struct_mutex);
- /* GuC logging is currently the only user of Guc2Host interrupts */
- gen9_disable_guc_interrupts(dev_priv);
+ /* GuC logging maybe the only user of Guc2Host interrupts */
+ if (!HAS_GUC_CT(dev_priv))
+ gen9_disable_guc_interrupts(dev_priv);
guc_log_runtime_destroy(&dev_priv->guc);
mutex_unlock(&dev_priv->drm.struct_mutex);
}
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 774d740..0209ad0 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -395,7 +395,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
intel_guc_auth_huc(dev_priv);
if (i915.enable_guc_submission) {
- if (i915.guc_log_level >= 0)
+ if (HAS_GUC_CT(dev_priv) || i915.guc_log_level >= 0)
gen9_enable_guc_interrupts(dev_priv);
ret = i915_guc_submission_enable(dev_priv);
--
2.7.4
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[Intel-gfx] [PATCH] drm/i915: Supply the engine-id for our mock_engine()
In the initial selftest, we didn't care what the engine->id was, just
that it could uniquely identify it. Later though, we started tracking in
the fixed size arrays around the drm_i915_private and so we now require
it to be appropriate. This becomes an issue when using the standalone
harness of running all available tests at module load as we quickly
assign an out-of-bounds index to an engine as repeatedly reallocate the
mock GEM device (and doesn't show up in igt/drv_selftest as that ran
each subtest individually).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102045
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/mock_engine.c | 8 +---
drivers/gpu/drm/i915/selftests/mock_engine.h | 3 ++-
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
3 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.c
b/drivers/gpu/drm/i915/selftests/mock_engine.c
index 5b18a2dc19a8..fc0fd7498689 100644
--- a/drivers/gpu/drm/i915/selftests/mock_engine.c
+++ b/drivers/gpu/drm/i915/selftests/mock_engine.c
@@ -123,10 +123,12 @@ static struct intel_ring *mock_ring(struct
intel_engine_cs *engine)
}
struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
- const char *name)
+ const char *name,
+ int id)
{
struct mock_engine *engine;
- static int id;
+
+ GEM_BUG_ON(id >= I915_NUM_ENGINES);
engine = kzalloc(sizeof(*engine) + PAGE_SIZE, GFP_KERNEL);
if (!engine)
@@ -141,7 +143,7 @@ struct intel_engine_cs *mock_engine(struct drm_i915_private
*i915,
/* minimal engine setup for requests */
engine->base.i915 = i915;
snprintf(engine->base.name, sizeof(engine->base.name), "%s", name);
- engine->base.id = id++;
+ engine->base.id = id;
engine->base.status_page.page_addr = (void *)(engine + 1);
engine->base.context_pin = mock_context_pin;
diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.h
b/drivers/gpu/drm/i915/selftests/mock_engine.h
index e5e240216ba3..133d0c21790d 100644
--- a/drivers/gpu/drm/i915/selftests/mock_engine.h
+++ b/drivers/gpu/drm/i915/selftests/mock_engine.h
@@ -40,7 +40,8 @@ struct mock_engine {
};
struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
- const char *name);
+ const char *name,
+ int id);
void mock_engine_flush(struct intel_engine_cs *engine);
void mock_engine_reset(struct intel_engine_cs *engine);
void mock_engine_free(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index ec92b6569b50..678723430d78 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -226,7 +226,7 @@ struct drm_i915_private *mock_gem_device(void)
mutex_unlock(&i915->drm.struct_mutex);
mkwrite_device_info(i915)->ring_mask = BIT(0);
- i915->engine[RCS] = mock_engine(i915, "mock");
+ i915->engine[RCS] = mock_engine(i915, "mock", RCS);
if (!i915->engine[RCS])
goto err_priorities;
--
2.13.3
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Re: [Intel-gfx] [PATCH v13 5/7] vfio: ABI for mdev display dma-buf operation
On Wed, 9 Aug 2017 08:31:00 + "Zhang, Tina" wrote: > > -Original Message- > > From: intel-gvt-dev [mailto:intel-gvt-dev-boun...@lists.freedesktop.org] On > > Behalf Of Alex Williamson > > Sent: Tuesday, August 8, 2017 1:43 AM > > To: Zhang, Tina > > Cc: Tian, Kevin ; intel-gfx@lists.freedesktop.org; > > dri- > > de...@lists.freedesktop.org; kwankh...@nvidia.com; kra...@redhat.com; > > intel-gvt-...@lists.freedesktop.org; Wang, Zhi A ; Lv, > > Zhiyuan > > Subject: Re: [PATCH v13 5/7] vfio: ABI for mdev display dma-buf operation > > > > On Mon, 7 Aug 2017 08:11:43 + > > "Zhang, Tina" wrote: > > > > > After going through the previous discussions, here are some summaries may > > > > > be related to the current discussion: > > > 1. How does user mode figure the device capabilities between region and > > dma-buf? > > > VFIO_DEVICE_GET_REGION_INFO could tell if the mdev supports region case. > > > Otherwise, the mdev supports dma-buf. > > > > Why do we need to make this assumption? What happens when dma-buf is > > superseded? What happens if a device supports both dma-buf and regions? > > We have a flags field in vfio_device_gfx_plane_info, doesn't it make sense > > to use > > it to identify which field, between region_index and fd, is valid? We > > could even > > put region_index and fd into a union with the flag bits indicating how to > > interpret the union, but I'm not sure everyone was onboard with this idea. > > Seems like a waste of 4 bytes not to do that though. > It seems we discussed this idea before: > https://lists.freedesktop.org/archives/intel-gvt-dev/2017-June/001304.html > https://lists.freedesktop.org/archives/intel-gvt-dev/2017-June/001333.html These are both from Gerd. Gerd, do you have any objection to using a union to provide either the dmabuf fd or region index? It's inefficient to provide separate fields when we can only provide one or the other and I don't like the idea of using implicit values to determine which is active. > > Thinking further, is the user ever in a situation where they query the > > graphics > > plane info and can handle either a dma-buf or a region? It seems more > > likely > > that the user needs to know early on which is supported and would then > > require > > that they continue to see compatible plane information... Should the user > > then > > be able to specify whether they want a dma-buf or a region? Perhaps these > > flag > > bits are actually input and the return should be -errno if the driver cannot > > produce something compatible. > From the previously discussion, it seems user space workflow will look quite > different > for these two cases. So once user space finds out which case is supported, it > just uses > that case, and won't change it. And that's supported, the user tests whether a given interface type is supported and continues to request updates for that interface type. > Meanwhile, I'm not sure whether there will be a mdev would like to support > both region > and dma-buf cases. In my opinion, either region or dma-buf is supported by > one mdev. (Yeah, > agree, there may be other cases in future) There's no requirement to support both. > It's like we want to propose a general interface used to share guest's buffer > with host. And the > general interface, so far, has two choice: region and dma-buf. So each mdev > likes this interface > can implement one kind of it and gets the benefit from the general interface. > So, if we think about this, the difference in user mode should be as little > as possible. The difference seems pretty minimal here, the user probes supported interface types, and explicitly picks one by requesting updates using that interface type. The difference is only in the interpretation of one dword field. Furthermore, we're not limiting ourselves to these two interface types, this same API could support dmabuf-v2 if we define a flag bit for it and define the structure of the interface union. > > Maybe we'd therefore define 3 flag bits: PROBE, DMABUF, REGION. In this > > initial implementation, DMABUF or REGION would always be set by the user to > > request that type of interface. Additionally, the QUERY bit could be set > > to probe > > compatibility, thus if PROBE and REGION are set, the vendor driver would > > return > > success only if it supports the region based interface. If PROBE and > > DMABUF are > > set, the vendor driver returns success only if the dma-buf based interface > > is > > supported. The value of the remainder of the structure is undefined for > > PROBE. > > Additionally setting both DMABUF and REGION is invalid. Undefined flags > > bits > > must be validated as zero by the drivers for future use (thus if we later > > define > > DMABUFv2, an older driver should automatically return -errno when probed or > > requested). > > > > It seems like this handles all the cases, the user can ask what's supported > > and > > specifie
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Supply the engine-id for our mock_engine()
== Series Details == Series: drm/i915: Supply the engine-id for our mock_engine() URL : https://patchwork.freedesktop.org/series/28565/ State : success == Summary == Series 28565v1 drm/i915: Supply the engine-id for our mock_engine() https://patchwork.freedesktop.org/api/1.0/series/28565/revisions/1/mbox/ Test gem_ringfill: Subgroup basic-default: pass -> SKIP (fi-bsw-n3050) fdo#101915 fdo#101915 https://bugs.freedesktop.org/show_bug.cgi?id=101915 fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:429s fi-bdw-gvtdvmtotal:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:418s fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:355s fi-bsw-n3050 total:279 pass:242 dwarn:0 dfail:0 fail:0 skip:37 time:500s fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:495s fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:521s fi-byt-n2820 total:279 pass:250 dwarn:1 dfail:0 fail:0 skip:28 time:512s fi-glk-2atotal:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:582s fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:429s fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:406s fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:426s fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:507s fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:476s fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:459s fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:571s fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:575s fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:449s fi-skl-6700k total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:642s fi-skl-6770hqtotal:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:461s fi-skl-gvtdvmtotal:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:430s fi-skl-x1585ltotal:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:496s fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:549s fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:409s 77b1bb6a1c72df55182beb47faf0df25918c6698 drm-tip: 2017y-08m-09d-14h-36m-30s UTC integration manifest 706cda155c08 drm/i915: Supply the engine-id for our mock_engine() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5352/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC i-g-t] tests/gem_exec_basic: Documentation for subtests
On 8/9/2017 7:32 AM, Arkadiusz Hiler wrote: On Tue, Aug 08, 2017 at 03:09:00PM -0700, Vinay Belgaumkar wrote: This is an RFC for adding documentation to IGT subtests. Each subtest can have something similar to a WHAT - explaining what the subtest actually does, and a WHY - which explains a use case, if applicable. Additionally, include comments for anything in the subtest code which can help explain HOW the test has been implemented. We don't actually need the WHAT and WHY tags in the documentation. These comments will not be linked to gtkdoc as of now, since we do not have a mechanism to link it to every subtest name. Hey Vinay, I get similar feelings towards this RFC as Lukasz and Radek do. Was your intention to propose format of the comments? Or maybe force people to comment more on the code? Or just pointing out that we could use some subtest documentation? You are not documenting subtests, you are documenting arbitrary functions that may or may not be used as a subtest. I cannot help but feel lost here. Being explicit as of your intention and coming up with more abstract or better examples would also help, as current ones are detracting from the idea itself. I do not get this RFC and it's purpose but I am looking forward to seeing revised version that is clearer on your intentions and easier to grasp. Hi Arek, The purpose of this RFC is to complement Petri's subtest documentation patch. That patch will give us an ability to add a line of documentation per subtest, which is definitely useful. However, what I noticed is that when you actually start debugging a test issue and step into the subtest code, it is very hard to understand what the purpose of certain commands are. My intention was to provide a text only documentation in the test source to allow test developers to understand the code better. It's hard to explain the how and and why all in a single sentence. If we provided an ability/guideline to test developers for mentioning the same at the beginning of the actual subtest code, it can make debugging a lot more simpler rather than having to jump back to the main function to figure out what the subtest is supposed to do. I have also included some comments inside the test function to explain why we use certain system calls. Idea was not to define the system call, but explain why it is being used. Again, I did not mean to duplicate the subtest documentation effort. My initial plan was to send out an RFC using Petri's patch as well, so that the intention is more clear. I can do that with the second version of the patch if needed. However, the main aim is to agree on a convention to add more documentation to the subtest code so that it simplifies debugging and helps with understanding of the aim behind writing the particular subtest. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] syncobj: Add some wait and reset tests
This adds both trivial error-checking tests as well as more complex
tests which actually test whether or not waits do what they're supposed
to do. They only currently work on i915 but it should be simple to hook
them up for other drivers by simply implementing the little function
pointer hook provided at the top for triggering a syncobj.
---
tests/Makefile.sources | 1 +
tests/syncobj_wait.c | 624 +
2 files changed, 625 insertions(+)
create mode 100644 tests/syncobj_wait.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index bb013c7..430b637 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -230,6 +230,7 @@ TESTS_progs = \
prime_vgem \
sw_sync \
syncobj_basic \
+ syncobj_wait \
template \
tools_test \
vgem_basic \
diff --git a/tests/syncobj_wait.c b/tests/syncobj_wait.c
new file mode 100644
index 000..6689d34
--- /dev/null
+++ b/tests/syncobj_wait.c
@@ -0,0 +1,624 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include
+#include
+#include
+#include "drm.h"
+
+IGT_TEST_DESCRIPTION("Tests for the drm sync object wait API");
+
+/* One one tenth of a second */
+#define SHORT_TIME_NSEC 1ull
+
+/** A per-platform function which triggers a set of sync objects
+ *
+ * If wait is set, the function should wait for the work to complete so
+ * that an immediate call to SYNCOBJ_WAIT will return success. If wait is
+ * not set, then the function should try to submit enough work that an
+ * immediate call to SYNCOBJ_WAIT with a timeout of 0 will time out.
+ */
+void (*trigger_syncobj)(int fd, uint32_t *syncobjs, int count, bool wait);
+
+#define NSECS_PER_SEC 10ull
+
+static uint64_t
+gettime_ns(void)
+{
+ struct timespec current;
+ clock_gettime(CLOCK_MONOTONIC, ¤t);
+ return (uint64_t)current.tv_sec * NSECS_PER_SEC + current.tv_nsec;
+}
+
+static uint64_t
+short_timeout(void)
+{
+ return gettime_ns() + SHORT_TIME_NSEC;
+}
+
+static uint32_t
+syncobj_create(int fd)
+{
+ struct drm_syncobj_create create = { 0 };
+ int ret;
+
+ ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &create);
+ igt_assert(ret == 0);
+ igt_assert(create.handle > 0);
+
+ return create.handle;
+}
+
+static void
+syncobj_destroy(int fd, uint32_t handle)
+{
+ struct drm_syncobj_destroy destroy = { 0 };
+ int ret;
+
+ destroy.handle = handle;
+ ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_DESTROY, &destroy);
+ igt_assert(ret == 0);
+}
+
+struct delayed_trigger {
+ int fd;
+ uint32_t *syncobjs;
+ int count;
+ uint64_t nsec;
+};
+
+static void *
+trigger_syncobj_delayed_func(void *data)
+{
+ struct delayed_trigger *trigger = data;
+ struct timespec time;
+
+ time.tv_sec = trigger->nsec / NSECS_PER_SEC;
+ time.tv_nsec = trigger->nsec % NSECS_PER_SEC;
+
+ nanosleep(&time, NULL);
+ trigger_syncobj(trigger->fd, trigger->syncobjs, trigger->count, true);
+ free(data);
+
+ return NULL;
+}
+
+static pthread_t
+trigger_syncobj_delayed(int fd, uint32_t *syncobjs, int count, uint64_t nsec)
+{
+ struct delayed_trigger *trigger;
+ pthread_t thread;
+ int ret;
+
+ trigger = malloc(sizeof(*trigger));
+ trigger->fd = fd;
+ trigger->syncobjs = syncobjs;
+ trigger->count = count;
+ trigger->nsec = nsec;
+
+ ret = pthread_create(&thread, NULL,
+trigger_syncobj_delayed_func, trigger);
+ igt_assert(ret == 0);
+
+ return thread;
+}
+
+static void
+test_wait_bad_flags(int fd)
+{
+ struct drm_syncobj_wait wait = { 0 };
+ int ret;
+
+ wait.flags = 0xdeadbeef;
+ ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait);
+ igt_assert(ret == -1
Re: [Intel-gfx] [PATCH v3 14/16] drm/i915/guc: Enable GuC interrupts when using CT
On 08/09/2017 09:24 AM, Michal Wajdeczko wrote:
We will need them in G2H communication to properly handle
responses and requests from the Guc.
v2: keep irq enabled while disabling GuC logging (Oscar)
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
---
drivers/gpu/drm/i915/i915_guc_submission.c | 2 +-
drivers/gpu/drm/i915/intel_guc_log.c | 10 ++
drivers/gpu/drm/i915/intel_uc.c| 2 +-
3 files changed, 8 insertions(+), 6 deletions(-)
Acked-by: Oscar Mateo
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 48a1e93..509497e 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1328,7 +1328,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;
- if (i915.guc_log_level >= 0)
+ if (HAS_GUC_CT(dev_priv) || i915.guc_log_level >= 0)
gen9_enable_guc_interrupts(dev_priv);
ctx = dev_priv->kernel_context;
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c
b/drivers/gpu/drm/i915/intel_guc_log.c
index acd9a3f..64fb879 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -505,8 +505,9 @@ static void guc_flush_logs(struct intel_guc *guc)
if (!i915.enable_guc_submission || (i915.guc_log_level < 0))
return;
- /* First disable the interrupts, will be renabled afterwards */
- gen9_disable_guc_interrupts(dev_priv);
+ /* GuC logging maybe the only user of Guc2Host interrupts */
+ if (!HAS_GUC_CT(dev_priv))
+ gen9_disable_guc_interrupts(dev_priv);
/* Before initiating the forceful flush, wait for any pending/ongoing
* flush to complete otherwise forceful flush may not actually happen.
@@ -663,8 +664,9 @@ void i915_guc_log_unregister(struct drm_i915_private
*dev_priv)
return;
mutex_lock(&dev_priv->drm.struct_mutex);
- /* GuC logging is currently the only user of Guc2Host interrupts */
- gen9_disable_guc_interrupts(dev_priv);
+ /* GuC logging maybe the only user of Guc2Host interrupts */
+ if (!HAS_GUC_CT(dev_priv))
+ gen9_disable_guc_interrupts(dev_priv);
guc_log_runtime_destroy(&dev_priv->guc);
mutex_unlock(&dev_priv->drm.struct_mutex);
}
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 774d740..0209ad0 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -395,7 +395,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
intel_guc_auth_huc(dev_priv);
if (i915.enable_guc_submission) {
- if (i915.guc_log_level >= 0)
+ if (HAS_GUC_CT(dev_priv) || i915.guc_log_level >= 0)
gen9_enable_guc_interrupts(dev_priv);
ret = i915_guc_submission_enable(dev_priv);
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for syncobj: Add some wait and reset tests
== Series Details == Series: syncobj: Add some wait and reset tests URL : https://patchwork.freedesktop.org/series/28567/ State : failure == Summary == IGT patchset build failed on latest successful build c129026622accef6f54c0cfb0dc55e930cfa60b5 igt: add syncobj_basic. make all-recursive Making all in lib make all-recursive Making all in . Making all in tests make[4]: Nothing to be done for 'all'. Making all in man make[2]: Nothing to be done for 'all'. Making all in tools Making all in null_state_gen make[3]: Nothing to be done for 'all'. Making all in registers make[3]: Nothing to be done for 'all'. make[3]: Nothing to be done for 'all-am'. Making all in scripts make[2]: Nothing to be done for 'all'. Making all in benchmarks make[2]: Nothing to be done for 'all'. Making all in tests Making all in intel-ci make[3]: Nothing to be done for 'all'. CCLD debugfs_test CCLD drm_import_export CCLD drm_mm CCLD drm_read CCLD drm_vma_limiter CCLD drm_vma_limiter_cached CCLD drm_vma_limiter_cpu CCLD drm_vma_limiter_gtt CCLD drv_getparams_basic CCLD drv_hangman CCLD drv_missed_irq CCLD drv_module_reload CCLD drv_selftest CCLD drv_suspend CCLD gem_bad_length CCLD gem_bad_reloc CCLD gem_basic CCLD gem_busy CCLD gem_caching CCLD gem_close_race CCLD gem_concurrent_blit CCLD gem_cpu_reloc CCLD gem_create CCLD gem_cs_prefetch CCLD gem_cs_tlb CCLD gem_ctx_bad_destroy CCLD gem_ctx_bad_exec CCLD gem_ctx_basic CCLD gem_ctx_create CCLD gem_ctx_exec CCLD gem_ctx_param CCLD gem_ctx_switch CCLD gem_ctx_thrash CCLD gem_double_irq_loop CCLD gem_eio CCLD gem_evict_alignment CCLD gem_evict_everything CCLD gem_exec_alignment CCLD gem_exec_async CCLD gem_exec_await CCLD gem_exec_bad_domains CCLD gem_exec_basic CCLD gem_exec_big CCLD gem_exec_blt CCLD gem_exec_capture CCLD gem_exec_create CCLD gem_exec_faulting_reloc CCLD gem_exec_fence CCLD gem_exec_flush CCLD gem_exec_gttfill CCLD gem_exec_latency CCLD gem_exec_lut_handle CCLD gem_exec_nop CCLD gem_exec_parallel CCLD gem_exec_params CCLD gem_exec_parse CCLD gem_exec_reloc CCLD gem_exec_reuse CCLD gem_exec_schedule CCLD gem_exec_store CCLD gem_exec_suspend CCLD gem_exec_whisper CCLD gem_fd_exhaustion CCLD gem_fence_thrash CCLD gem_fence_upload CCLD gem_fenced_exec_thrash CCLD gem_flink_basic CCLD gem_flink_race CCLD gem_gpgpu_fill CCLD gem_gtt_cpu_tlb CCLD gem_gtt_hog CCLD gem_gtt_speed CCLD gem_hangcheck_forcewake CCLD gem_largeobject CCLD gem_linear_blits CCLD gem_lut_handle CCLD gem_madvise CCLD gem_media_fill CCLD gem_mmap CCLD gem_mmap_gtt CCLD gem_mmap_offset_exhaustion CCLD gem_mmap_wc CCLD gem_mocs_settings CCLD gem_partial_pwrite_pread CCLD gem_persistent_relocs CCLD gem_pin CCLD gem_pipe_control_store_loop CCLD gem_ppgtt CCLD gem_pread CCLD gem_pread_after_blit CCLD gem_pwrite CCLD gem_pwrite_pread CCLD gem_pwrite_snooped CCLD gem_read_read_speed CCLD gem_readwrite CCLD gem_reg_read CCLD gem_reloc_overflow CCLD gem_reloc_vs_gpu CCLD gem_render_copy CCLD gem_render_copy_redux CCLD gem_render_linear_blits CCLD gem_render_tiled_blits CCLD gem_request_retire CCLD gem_reset_stats CCLD gem_ring_sync_copy CCLD gem_ring_sync_loop CCLD gem_ringfill CCLD gem_seqno_wrap CCLD gem_set_tiling_vs_blt CCLD gem_set_tiling_vs_gtt CCLD gem_set_tiling_vs_pwrite CCLD gem_shrink CCLD gem_softpin CCLD gem_spin_batch CCLD gem_stolen CCLD gem_storedw_batches_loop CCLD gem_storedw_loop CCLD gem_streaming_writes CCLD gem_sync CCLD gem_threaded_access_tiled CCLD gem_tiled_blits CCLD gem_tiled_fence_blits CCLD gem_tiled_partial_pwrite_pread CCLD gem_tiled_pread_basic CCLD gem_tiled_pread_pwrite CCLD gem_tiled_swapping CCLD gem_tiled_wb CCLD gem_tiled_wc CCLD gem_tiling_max_stride CCLD gem_unfence_active_buffers CCLD gem_unref_active_buffers CCLD gem_userptr_blits CCLD gem_wait CCLD gem_workarounds CCLD gem_write_read_ring_switch CCLD gen3_mixed_blits CCLD gen3_render_linear_blits CCLD gen3_render_mixed_blits CCLD gen3_render_tiledx_blits CCLD gen3_render_tiledy_blits CCLD gen7_forcewake_mt CCLD gvt_basic CCLD kms_3d CCLD kms_addfb_basic CCLD kms_atomic CCLD kms_atomic_transition CCLD kms_busy CCLD kms_ccs CCLD kms_chv_cur
Re: [Intel-gfx] [PATCH 1/6] drm/i915: Introduce intel_ddi_dp_level.
On Wed, 2017-08-09 at 15:20 +0300, Jani Nikula wrote: > On Tue, 08 Aug 2017, Rodrigo Vivi wrote: > > +static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp) > > Sorry to pick on specifically this patch when there continue to be > offenders all over the place... don't be sorry. I'm glad that you spotted this ;) I'm always confused about this and try to get the closest one, although I prefer the linux style u32. > but shouldn't we prefer the kernel types > over standard C types? Not that checkpatch is an authority here, but > with --strict it complains about using e.g. uint32_t. I went to https://www.kernel.org/doc/html/v4.10/process/coding-style.html """ d. New types which are identical to standard C99 types, in certain exceptional circumstances. Although it would only take a short amount of time for the eyes and brain to become accustomed to the standard types like uint32_t, some people object to their use anyway. Therefore, the Linux-specific u8/u16/u32/u64 types and their signed equivalents which are identical to standard types are permitted – although they are not mandatory in new code of your own. When editing existing code which already uses one or the other set of types, you should conform to the existing choices in that code. """ I wonder if we should do a one time replace in all our code and start accepting only one to avoid confusion. > > BR, > Jani. > > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] syncobj: Add some wait and reset tests (v2)
This adds both trivial error-checking tests as well as more complex
tests which actually test whether or not waits do what they're supposed
to do. They only currently work on i915 but it should be simple to hook
them up for other drivers by simply implementing the little function
pointer hook provided at the top for triggering a syncobj.
v2:
- Actually add the reset tests.
Signed-off-by: Jason Ekstrand
---
tests/Makefile.sources | 1 +
tests/syncobj_wait.c | 714 +
2 files changed, 715 insertions(+)
create mode 100644 tests/syncobj_wait.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index bb013c7..430b637 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -230,6 +230,7 @@ TESTS_progs = \
prime_vgem \
sw_sync \
syncobj_basic \
+ syncobj_wait \
template \
tools_test \
vgem_basic \
diff --git a/tests/syncobj_wait.c b/tests/syncobj_wait.c
new file mode 100644
index 000..2e39e6d
--- /dev/null
+++ b/tests/syncobj_wait.c
@@ -0,0 +1,714 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include
+#include
+#include
+#include "drm.h"
+
+IGT_TEST_DESCRIPTION("Tests for the drm sync object wait API");
+
+/* One one tenth of a second */
+#define SHORT_TIME_NSEC 1ull
+
+/** A per-platform function which triggers a set of sync objects
+ *
+ * If wait is set, the function should wait for the work to complete so
+ * that an immediate call to SYNCOBJ_WAIT will return success. If wait is
+ * not set, then the function should try to submit enough work that an
+ * immediate call to SYNCOBJ_WAIT with a timeout of 0 will time out.
+ */
+void (*trigger_syncobj)(int fd, uint32_t *syncobjs, int count, bool wait);
+
+#define NSECS_PER_SEC 10ull
+
+static uint64_t
+gettime_ns(void)
+{
+ struct timespec current;
+ clock_gettime(CLOCK_MONOTONIC, ¤t);
+ return (uint64_t)current.tv_sec * NSECS_PER_SEC + current.tv_nsec;
+}
+
+static uint64_t
+short_timeout(void)
+{
+ return gettime_ns() + SHORT_TIME_NSEC;
+}
+
+static uint32_t
+syncobj_create(int fd)
+{
+ struct drm_syncobj_create create = { 0 };
+ int ret;
+
+ ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &create);
+ igt_assert(ret == 0);
+ igt_assert(create.handle > 0);
+
+ return create.handle;
+}
+
+static void
+syncobj_destroy(int fd, uint32_t handle)
+{
+ struct drm_syncobj_destroy destroy = { 0 };
+ int ret;
+
+ destroy.handle = handle;
+ ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_DESTROY, &destroy);
+ igt_assert(ret == 0);
+}
+
+struct delayed_trigger {
+ int fd;
+ uint32_t *syncobjs;
+ int count;
+ uint64_t nsec;
+};
+
+static void *
+trigger_syncobj_delayed_func(void *data)
+{
+ struct delayed_trigger *trigger = data;
+ struct timespec time;
+
+ time.tv_sec = trigger->nsec / NSECS_PER_SEC;
+ time.tv_nsec = trigger->nsec % NSECS_PER_SEC;
+
+ nanosleep(&time, NULL);
+ trigger_syncobj(trigger->fd, trigger->syncobjs, trigger->count, true);
+ free(data);
+
+ return NULL;
+}
+
+static pthread_t
+trigger_syncobj_delayed(int fd, uint32_t *syncobjs, int count, uint64_t nsec)
+{
+ struct delayed_trigger *trigger;
+ pthread_t thread;
+ int ret;
+
+ trigger = malloc(sizeof(*trigger));
+ trigger->fd = fd;
+ trigger->syncobjs = syncobjs;
+ trigger->count = count;
+ trigger->nsec = nsec;
+
+ ret = pthread_create(&thread, NULL,
+trigger_syncobj_delayed_func, trigger);
+ igt_assert(ret == 0);
+
+ return thread;
+}
+
+static void
+test_wait_bad_flags(int fd)
+{
+ struct drm_syncobj_wait wait = { 0 };
+ int ret;
+
+ wait.flags = 0xdeadbeef;
+ ret = i
Re: [Intel-gfx] [PATCH i-g-t] syncobj: Add some wait and reset tests
Quoting Jason Ekstrand (2017-08-09 18:04:42)
> This adds both trivial error-checking tests as well as more complex
> tests which actually test whether or not waits do what they're supposed
> to do. They only currently work on i915 but it should be simple to hook
> them up for other drivers by simply implementing the little function
> pointer hook provided at the top for triggering a syncobj.
Note that this requires a libdrm version more recent than is requested.
> ---
> tests/Makefile.sources | 1 +
> tests/syncobj_wait.c | 624
> +
> 2 files changed, 625 insertions(+)
> create mode 100644 tests/syncobj_wait.c
>
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> index bb013c7..430b637 100644
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -230,6 +230,7 @@ TESTS_progs = \
> prime_vgem \
> sw_sync \
> syncobj_basic \
> + syncobj_wait \
> template \
> tools_test \
> vgem_basic \
> diff --git a/tests/syncobj_wait.c b/tests/syncobj_wait.c
> new file mode 100644
> index 000..6689d34
> --- /dev/null
> +++ b/tests/syncobj_wait.c
> @@ -0,0 +1,624 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "igt.h"
> +#include
> +#include
> +#include
> +#include "drm.h"
> +
> +IGT_TEST_DESCRIPTION("Tests for the drm sync object wait API");
> +
> +/* One one tenth of a second */
> +#define SHORT_TIME_NSEC 1ull
> +
> +/** A per-platform function which triggers a set of sync objects
> + *
> + * If wait is set, the function should wait for the work to complete so
> + * that an immediate call to SYNCOBJ_WAIT will return success. If wait is
> + * not set, then the function should try to submit enough work that an
> + * immediate call to SYNCOBJ_WAIT with a timeout of 0 will time out.
> + */
> +void (*trigger_syncobj)(int fd, uint32_t *syncobjs, int count, bool wait);
> +
> +#define NSECS_PER_SEC 10ull
> +
> +static uint64_t
> +gettime_ns(void)
> +{
> + struct timespec current;
> + clock_gettime(CLOCK_MONOTONIC, ¤t);
> + return (uint64_t)current.tv_sec * NSECS_PER_SEC + current.tv_nsec;
> +}
> +
> +static uint64_t
> +short_timeout(void)
> +{
> + return gettime_ns() + SHORT_TIME_NSEC;
> +}
> +
> +static uint32_t
> +syncobj_create(int fd)
> +{
> + struct drm_syncobj_create create = { 0 };
> + int ret;
> +
> + ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &create);
> + igt_assert(ret == 0);
> + igt_assert(create.handle > 0);
> +
> + return create.handle;
> +}
> +
> +static void
> +syncobj_destroy(int fd, uint32_t handle)
> +{
> + struct drm_syncobj_destroy destroy = { 0 };
> + int ret;
> +
> + destroy.handle = handle;
> + ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_DESTROY, &destroy);
> + igt_assert(ret == 0);
> +}
> +
> +struct delayed_trigger {
> + int fd;
> + uint32_t *syncobjs;
> + int count;
> + uint64_t nsec;
> +};
> +
> +static void *
> +trigger_syncobj_delayed_func(void *data)
> +{
> + struct delayed_trigger *trigger = data;
> + struct timespec time;
> +
> + time.tv_sec = trigger->nsec / NSECS_PER_SEC;
> + time.tv_nsec = trigger->nsec % NSECS_PER_SEC;
> +
> + nanosleep(&time, NULL);
> + trigger_syncobj(trigger->fd, trigger->syncobjs, trigger->count, true);
> + free(data);
> +
> + return NULL;
> +}
> +
> +static pthread_t
> +trigger_syncobj_delayed(int fd, uint32_t *syncobjs, int count, uint64_t nsec)
> +{
> + struct delayed_trigger *trigger;
> + pthread_t thread;
> + int ret;
> +
> + trigger = malloc(sizeof(*trigger));
> + trigger->fd = fd;
> + trigger->syncobjs = syncobjs;
> + trigger->count = count;
> + trigge
[Intel-gfx] [PATCH] drm/i915/guc: Rename GuC irq trigger function
We should emphasize that irq trigger function depends on Gen.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_uc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 27e072c..d78ecae 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -94,7 +94,7 @@ void intel_uc_sanitize_options(struct drm_i915_private
*dev_priv)
i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
}
-static void guc_write_irq_trigger(struct intel_guc *guc)
+static void gen8_guc_trigger_irq(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -109,7 +109,7 @@ void intel_uc_init_early(struct drm_i915_private *dev_priv)
mutex_init(&guc->send_mutex);
guc->send = intel_guc_send_nop;
- guc->notify = guc_write_irq_trigger;
+ guc->notify = gen8_guc_trigger_irq;
}
static void fetch_uc_fw(struct drm_i915_private *dev_priv,
--
2.7.4
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[Intel-gfx] [PATCH] drm/i915: Update from drm-next
---
include/drm/i915_drm.h | 61 ++
1 file changed, 52 insertions(+), 9 deletions(-)
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 5ebe046..c26bf7c 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -412,6 +412,25 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_PARAM_HAS_EXEC_FENCE 44
+/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture
+ * user specified bufffers for post-mortem debugging of GPU hangs. See
+ * EXEC_OBJECT_CAPTURE.
+ */
+#define I915_PARAM_HAS_EXEC_CAPTURE 45
+
+#define I915_PARAM_SLICE_MASK 46
+
+/* Assuming it's uniform for each slice, this queries the mask of subslices
+ * per-slice for this system.
+ */
+#define I915_PARAM_SUBSLICE_MASK47
+
+/*
+ * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer
+ * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST.
+ */
+#define I915_PARAM_HAS_EXEC_BATCH_FIRST 48
+
typedef struct drm_i915_getparam {
__s32 param;
/*
@@ -666,6 +685,8 @@ struct drm_i915_gem_relocation_entry {
#define I915_GEM_DOMAIN_VERTEX 0x0020
/** GTT domain - aperture and scanout */
#define I915_GEM_DOMAIN_GTT0x0040
+/** WC domain - uncached access */
+#define I915_GEM_DOMAIN_WC 0x0080
/** @} */
struct drm_i915_gem_exec_object {
@@ -773,8 +794,15 @@ struct drm_i915_gem_exec_object2 {
* I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
*/
#define EXEC_OBJECT_ASYNC (1<<6)
+/* Request that the contents of this execobject be copied into the error
+ * state upon a GPU hang involving this batch for post-mortem debugging.
+ * These buffers are recorded in no particular order as "user" in
+ * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see
+ * if the kernel supports this flag.
+ */
+#define EXEC_OBJECT_CAPTURE(1<<7)
/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
-#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_ASYNC<<1)
+#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)
__u64 flags;
union {
@@ -889,7 +917,17 @@ struct drm_i915_gem_execbuffer2 {
*/
#define I915_EXEC_FENCE_OUT(1<<17)
-#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_OUT<<1))
+/*
+ * Traditionally the execbuf ioctl has only considered the final element in
+ * the execobject[] to be the executable batch. Often though, the client
+ * will known the batch object prior to construction and being able to place
+ * it into the execobject[] array first can simplify the relocation tracking.
+ * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the
+ * execobject[] as the * batch instead (the default is to use the last
+ * element).
+ */
+#define I915_EXEC_BATCH_FIRST (1<<18)
+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_BATCH_FIRST<<1))
#define I915_EXEC_CONTEXT_ID_MASK (0x)
#define i915_execbuffer2_set_context_id(eb2, context) \
@@ -1293,13 +1331,18 @@ struct drm_i915_gem_context_param {
};
enum drm_i915_oa_format {
- I915_OA_FORMAT_A13 = 1,
- I915_OA_FORMAT_A29,
- I915_OA_FORMAT_A13_B8_C8,
- I915_OA_FORMAT_B4_C8,
- I915_OA_FORMAT_A45_B8_C8,
- I915_OA_FORMAT_B4_C8_A16,
- I915_OA_FORMAT_C4_B8,
+ I915_OA_FORMAT_A13 = 1, /* HSW only */
+ I915_OA_FORMAT_A29, /* HSW only */
+ I915_OA_FORMAT_A13_B8_C8, /* HSW only */
+ I915_OA_FORMAT_B4_C8, /* HSW only */
+ I915_OA_FORMAT_A45_B8_C8, /* HSW only */
+ I915_OA_FORMAT_B4_C8_A16, /* HSW only */
+ I915_OA_FORMAT_C4_B8, /* HSW+ */
+
+ /* Gen8+ */
+ I915_OA_FORMAT_A12,
+ I915_OA_FORMAT_A12_B8_C8,
+ I915_OA_FORMAT_A32u40_A4u32_B8_C8,
I915_OA_FORMAT_MAX /* non-ABI */
};
--
2.5.0.400.gff86faf
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Re: [Intel-gfx] [PATCH i-g-t] syncobj: Add some wait and reset tests
Hi Jason,
On 9 August 2017 at 18:04, Jason Ekstrand wrote:
> +/* One one tenth of a second */
> +#define SHORT_TIME_NSEC 1ull
Er, a hundredth? Or only one, one tenth?
> +static void
> +test_wait_illegal_handle(int fd)
> +{
> + struct drm_syncobj_wait wait = { 0 };
> + uint32_t handle = 2;
Use 0.
> +static void
> +test_wait_for_submit_unsignaled(int fd)
> +{
> + uint32_t syncobj = syncobj_create(fd);
> + struct drm_syncobj_wait wait = { 0 };
> + int ret;
> +
> + wait.handles = to_user_pointer(&syncobj);
> + wait.count_handles = 1;
> + wait.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> + wait.timeout_nsec = short_timeout();
> +
> + ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait);
> + igt_assert(ret == -1 && errno == ETIME);
There's do_ioctl_err() for this pattern BTW, and I think that takes
care of EINTR as well.
> +static void
> +test_wait_signaled(int fd)
> +{
> + uint32_t syncobj = syncobj_create(fd);
> + struct drm_syncobj_wait wait = { 0 };
> + int ret;
> +
> + wait.handles = to_user_pointer(&syncobj);
> + wait.count_handles = 1;
> +
> + trigger_syncobj(fd, &syncobj, 1, false);
> +
> + wait.timeout_nsec = 0;
> + ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait);
> + igt_warn_on(ret != -1 || errno != ETIME);
> +
> + wait.timeout_nsec = short_timeout();
> + ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait);
> + igt_assert(ret == 0);
... and do_ioctl() for this pattern.
> +static bool
> +has_syncobj_wait(int fd)
> +{
> + struct drm_syncobj_wait wait = { 0 };
This probably needs a local_ definition.
> + uint64_t value;
> + int ret;
> +
> + if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
> + return false;
> + if (!value)
> + return false;
> +
> + /* Try waiting for zero sync objects should fail with EINVAL */
> + ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait);
> + return ret == -1 && errno == EINVAL;
Unfortunately an unrecognised ioctl also leads to a failure with
EINVAL. Try another test for ioctl presence, e.g. do you get ENOENT if
you pass one handle to wait for, but that handle is 0 (invalid GEM
object ID)?
I couldn't see much else obvious, and it seems like a decent enough
workout of the wait API, so, with these and what Chris suggested:
Acked-by: Daniel Stone
Cheers,
Daniel
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Re: [Intel-gfx] [PATCH v2] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init
Reviewed-by: Rodrigo Vivi
On Tue, Aug 8, 2017 at 2:51 PM, Jim Bride wrote:
> Bit 29 of SRD_CTL needs to have its value preserved according to the
> B-Spec, so right before we write out the register we go ahead and read
> the register and preserve the value of that bit before we write out
> the configured register value.
>
> v2: Spaces => tabs, minor name change, and commit message wording (Rodrigo)
>
> Cc: Rodrigo Vivi
> Cc: Chris Wilson
> Cc: Jani Nikula
> Signed-off-by: Jim Bride
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_psr.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b2546ad..56df86e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3872,6 +3872,7 @@ enum {
> #define EDP_PSR_CTL_MMIO(dev_priv->psr_mmio_base
> + 0)
> #define EDP_PSR_ENABLE (1<<31)
> #define BDW_PSR_SINGLE_FRAME (1<<30)
> +#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1<<29) /* SW can't modify */
> #define EDP_PSR_LINK_STANDBY (1<<27)
> #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
> #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 559f1ab..1b31ab0 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -315,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp
> *intel_dp)
> else
> val |= EDP_PSR_TP1_TP2_SEL;
>
> + val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
> I915_WRITE(EDP_PSR_CTL, val);
> }
>
> --
> 2.7.4
>
> ___
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--
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Blog: http://blog.vivi.eng.br
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Rename GuC irq trigger function
== Series Details == Series: drm/i915/guc: Rename GuC irq trigger function URL : https://patchwork.freedesktop.org/series/28570/ State : success == Summary == Series 28570v1 drm/i915/guc: Rename GuC irq trigger function https://patchwork.freedesktop.org/api/1.0/series/28570/revisions/1/mbox/ Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: fail -> PASS (fi-snb-2600) fdo#17 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: pass -> DMESG-WARN (fi-byt-n2820) fdo#101705 fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17 fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705 fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:440s fi-bdw-gvtdvmtotal:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:417s fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:361s fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:494s fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:492s fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:525s fi-byt-n2820 total:279 pass:250 dwarn:1 dfail:0 fail:0 skip:28 time:513s fi-glk-2atotal:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:581s fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:433s fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:416s fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:421s fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:506s fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:477s fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:458s fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:568s fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:573s fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:518s fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:448s fi-skl-6700k total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:647s fi-skl-6770hqtotal:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:470s fi-skl-gvtdvmtotal:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:433s fi-skl-x1585ltotal:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:485s fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:551s fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:405s db85100f75f1c20b2058bdc03939a5d377a263e6 drm-tip: 2017y-08m-09d-16h-41m-17s UTC integration manifest f417295f785d drm/i915/guc: Rename GuC irq trigger function == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5353/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] syncobj: Add some wait and reset tests
On Wed, Aug 9, 2017 at 10:28 AM, Chris Wilson
wrote:
> Quoting Jason Ekstrand (2017-08-09 18:04:42)
> > This adds both trivial error-checking tests as well as more complex
> > tests which actually test whether or not waits do what they're supposed
> > to do. They only currently work on i915 but it should be simple to hook
> > them up for other drivers by simply implementing the little function
> > pointer hook provided at the top for triggering a syncobj.
>
> Note that this requires a libdrm version more recent than is requested.
>
> > ---
> > tests/Makefile.sources | 1 +
> > tests/syncobj_wait.c | 624 ++
> +++
> > 2 files changed, 625 insertions(+)
> > create mode 100644 tests/syncobj_wait.c
> >
> > diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> > index bb013c7..430b637 100644
> > --- a/tests/Makefile.sources
> > +++ b/tests/Makefile.sources
> > @@ -230,6 +230,7 @@ TESTS_progs = \
> > prime_vgem \
> > sw_sync \
> > syncobj_basic \
> > + syncobj_wait \
> > template \
> > tools_test \
> > vgem_basic \
> > diff --git a/tests/syncobj_wait.c b/tests/syncobj_wait.c
> > new file mode 100644
> > index 000..6689d34
> > --- /dev/null
> > +++ b/tests/syncobj_wait.c
> > @@ -0,0 +1,624 @@
> > +/*
> > + * Copyright © 2017 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> obtaining a
> > + * copy of this software and associated documentation files (the
> "Software"),
> > + * to deal in the Software without restriction, including without
> limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including the
> next
> > + * paragraph) shall be included in all copies or substantial portions
> of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
> SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> > + * IN THE SOFTWARE.
> > + */
> > +
> > +#include "igt.h"
> > +#include
> > +#include
> > +#include
> > +#include "drm.h"
> > +
> > +IGT_TEST_DESCRIPTION("Tests for the drm sync object wait API");
> > +
> > +/* One one tenth of a second */
> > +#define SHORT_TIME_NSEC 1ull
> > +
> > +/** A per-platform function which triggers a set of sync objects
> > + *
> > + * If wait is set, the function should wait for the work to complete so
> > + * that an immediate call to SYNCOBJ_WAIT will return success. If wait
> is
> > + * not set, then the function should try to submit enough work that an
> > + * immediate call to SYNCOBJ_WAIT with a timeout of 0 will time out.
> > + */
> > +void (*trigger_syncobj)(int fd, uint32_t *syncobjs, int count, bool
> wait);
> > +
> > +#define NSECS_PER_SEC 10ull
> > +
> > +static uint64_t
> > +gettime_ns(void)
> > +{
> > + struct timespec current;
> > + clock_gettime(CLOCK_MONOTONIC, ¤t);
> > + return (uint64_t)current.tv_sec * NSECS_PER_SEC + current.tv_nsec;
> > +}
> > +
> > +static uint64_t
> > +short_timeout(void)
> > +{
> > + return gettime_ns() + SHORT_TIME_NSEC;
> > +}
> > +
> > +static uint32_t
> > +syncobj_create(int fd)
> > +{
> > + struct drm_syncobj_create create = { 0 };
> > + int ret;
> > +
> > + ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &create);
> > + igt_assert(ret == 0);
> > + igt_assert(create.handle > 0);
> > +
> > + return create.handle;
> > +}
> > +
> > +static void
> > +syncobj_destroy(int fd, uint32_t handle)
> > +{
> > + struct drm_syncobj_destroy destroy = { 0 };
> > + int ret;
> > +
> > + destroy.handle = handle;
> > + ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_DESTROY, &destroy);
> > + igt_assert(ret == 0);
> > +}
> > +
> > +struct delayed_trigger {
> > + int fd;
> > + uint32_t *syncobjs;
> > + int count;
> > + uint64_t nsec;
> > +};
> > +
> > +static void *
> > +trigger_syncobj_delayed_func(void *data)
> > +{
> > + struct delayed_trigger *trigger = data;
> > + struct timespec time;
> > +
> > + time.tv_sec = trigger->nsec / NSECS_PER_SEC;
> > + time.tv_nsec = trigger->nsec % NSECS_PER_SEC;
> > +
> > + nanosleep(&time, NULL);
> > + trigger_syncobj(trigger->fd, trigger->syncobjs, trigger->count,
> true);
> > + free(data);
> > +
> > + return NULL;
> > +}
> > +
> > +st
Re: [Intel-gfx] [PATCH v2] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init
merged to dinq.
Thanks for the patch and reviews
On Wed, Aug 9, 2017 at 10:37 AM, Rodrigo Vivi wrote:
> Reviewed-by: Rodrigo Vivi
>
> On Tue, Aug 8, 2017 at 2:51 PM, Jim Bride wrote:
>> Bit 29 of SRD_CTL needs to have its value preserved according to the
>> B-Spec, so right before we write out the register we go ahead and read
>> the register and preserve the value of that bit before we write out
>> the configured register value.
>>
>> v2: Spaces => tabs, minor name change, and commit message wording (Rodrigo)
>>
>> Cc: Rodrigo Vivi
>> Cc: Chris Wilson
>> Cc: Jani Nikula
>> Signed-off-by: Jim Bride
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>> drivers/gpu/drm/i915/intel_psr.c | 1 +
>> 2 files changed, 2 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index b2546ad..56df86e 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -3872,6 +3872,7 @@ enum {
>> #define EDP_PSR_CTL
>> _MMIO(dev_priv->psr_mmio_base + 0)
>> #define EDP_PSR_ENABLE (1<<31)
>> #define BDW_PSR_SINGLE_FRAME (1<<30)
>> +#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1<<29) /* SW can't modify */
>> #define EDP_PSR_LINK_STANDBY (1<<27)
>> #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
>> #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c
>> b/drivers/gpu/drm/i915/intel_psr.c
>> index 559f1ab..1b31ab0 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -315,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp
>> *intel_dp)
>> else
>> val |= EDP_PSR_TP1_TP2_SEL;
>>
>> + val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
>> I915_WRITE(EDP_PSR_CTL, val);
>> }
>>
>> --
>> 2.7.4
>>
>> ___
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for syncobj: Add some wait and reset tests (rev2)
== Series Details == Series: syncobj: Add some wait and reset tests (rev2) URL : https://patchwork.freedesktop.org/series/28567/ State : failure == Summary == IGT patchset build failed on latest successful build c129026622accef6f54c0cfb0dc55e930cfa60b5 igt: add syncobj_basic. make all-recursive Making all in lib make all-recursive Making all in . Making all in tests make[4]: Nothing to be done for 'all'. Making all in man make[2]: Nothing to be done for 'all'. Making all in tools Making all in null_state_gen make[3]: Nothing to be done for 'all'. Making all in registers make[3]: Nothing to be done for 'all'. make[3]: Nothing to be done for 'all-am'. Making all in scripts make[2]: Nothing to be done for 'all'. Making all in benchmarks make[2]: Nothing to be done for 'all'. Making all in tests Making all in intel-ci make[3]: Nothing to be done for 'all'. CCLD core_getstats CCLD core_getversion CCLD core_prop_blob CCLD core_setmaster_vs_auth CCLD debugfs_test CCLD drm_import_export CCLD drm_mm CCLD drm_read CCLD drm_vma_limiter CCLD drm_vma_limiter_cached CCLD drm_vma_limiter_cpu CCLD drm_vma_limiter_gtt CCLD drv_getparams_basic CCLD drv_hangman CCLD drv_missed_irq CCLD drv_module_reload CCLD drv_selftest CCLD drv_suspend CCLD gem_bad_length CCLD gem_bad_reloc CCLD gem_basic CCLD gem_busy CCLD gem_caching CCLD gem_close_race CCLD gem_concurrent_blit CCLD gem_cpu_reloc CCLD gem_create CCLD gem_cs_prefetch CCLD gem_cs_tlb CCLD gem_ctx_bad_destroy CCLD gem_ctx_bad_exec CCLD gem_ctx_basic CCLD gem_ctx_create CCLD gem_ctx_exec CCLD gem_ctx_param CCLD gem_ctx_switch CCLD gem_ctx_thrash CCLD gem_double_irq_loop CCLD gem_eio CCLD gem_evict_alignment CCLD gem_evict_everything CCLD gem_exec_alignment CCLD gem_exec_async CCLD gem_exec_await CCLD gem_exec_bad_domains CCLD gem_exec_basic CCLD gem_exec_big CCLD gem_exec_blt CCLD gem_exec_capture CCLD gem_exec_create CCLD gem_exec_faulting_reloc CCLD gem_exec_fence CCLD gem_exec_flush CCLD gem_exec_gttfill CCLD gem_exec_latency CCLD gem_exec_lut_handle CCLD gem_exec_nop CCLD gem_exec_parallel CCLD gem_exec_params CCLD gem_exec_parse CCLD gem_exec_reloc CCLD gem_exec_reuse CCLD gem_exec_schedule CCLD gem_exec_store CCLD gem_exec_suspend CCLD gem_exec_whisper CCLD gem_fd_exhaustion CCLD gem_fence_thrash CCLD gem_fence_upload CCLD gem_fenced_exec_thrash CCLD gem_flink_basic CCLD gem_flink_race CCLD gem_gpgpu_fill CCLD gem_gtt_cpu_tlb CCLD gem_gtt_hog CCLD gem_gtt_speed CCLD gem_hangcheck_forcewake CCLD gem_largeobject CCLD gem_linear_blits CCLD gem_lut_handle CCLD gem_madvise CCLD gem_media_fill CCLD gem_mmap CCLD gem_mmap_gtt CCLD gem_mmap_offset_exhaustion CCLD gem_mmap_wc CCLD gem_mocs_settings CCLD gem_partial_pwrite_pread CCLD gem_persistent_relocs CCLD gem_pin CCLD gem_pipe_control_store_loop CCLD gem_ppgtt CCLD gem_pread CCLD gem_pread_after_blit CCLD gem_pwrite CCLD gem_pwrite_pread CCLD gem_pwrite_snooped CCLD gem_read_read_speed CCLD gem_readwrite CCLD gem_reg_read CCLD gem_reloc_overflow CCLD gem_reloc_vs_gpu CCLD gem_render_copy CCLD gem_render_copy_redux CCLD gem_render_linear_blits CCLD gem_render_tiled_blits CCLD gem_request_retire CCLD gem_reset_stats CCLD gem_ring_sync_copy CCLD gem_ring_sync_loop CCLD gem_ringfill CCLD gem_seqno_wrap CCLD gem_set_tiling_vs_blt CCLD gem_set_tiling_vs_gtt CCLD gem_set_tiling_vs_pwrite CCLD gem_shrink CCLD gem_softpin CCLD gem_spin_batch CCLD gem_stolen CCLD gem_storedw_batches_loop CCLD gem_storedw_loop CCLD gem_streaming_writes CCLD gem_sync CCLD gem_threaded_access_tiled CCLD gem_tiled_blits CCLD gem_tiled_fence_blits CCLD gem_tiled_partial_pwrite_pread CCLD gem_tiled_pread_basic CCLD gem_tiled_pread_pwrite CCLD gem_tiled_swapping CCLD gem_tiled_wb CCLD gem_tiled_wc CCLD gem_tiling_max_stride CCLD gem_unfence_active_buffers CCLD gem_unref_active_buffers CCLD gem_userptr_blits CCLD gem_wait CCLD gem_workarounds CCLD gem_write_read_ring_switch CCLD gen3_mixed_blits CCLD gen3_render_linear_blits CCLD gen3_render_mixed_blits CCLD gen3_render_tiledx_blits CCLD gen3_render_tiledy_blits CCLD gen7_forcewake_mt CCLD gvt_basic CCLD kms_3d CCLD kms_addfb_bas
Re: [Intel-gfx] [PATCH i-g-t] syncobj: Add some wait and reset tests
On Wed, Aug 9, 2017 at 10:28 AM, Chris Wilson wrote: > > [snip] > > Key tests missing here are signal (SIGINT) handling, especially how the > timeout parameters is handled on repeats, see igt_interruptible(), though > you must use igt_ioctl(). I'll see what I can do > Polling multiple handles is not > checked, especially combinations of signaled/unsignaled syncojbs. Uh... that should be covered (maybe not well enough) by the wait_any and wait_all tests. --Jason ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] syncobj: Add some wait and reset tests
Quoting Jason Ekstrand (2017-08-09 18:46:49)
> On Wed, Aug 9, 2017 at 10:28 AM, Chris Wilson
> wrote:
>
> Quoting Jason Ekstrand (2017-08-09 18:04:42)
> > This adds both trivial error-checking tests as well as more complex
> > tests which actually test whether or not waits do what they're supposed
> > to do. They only currently work on i915 but it should be simple to hook
> > them up for other drivers by simply implementing the little function
> > pointer hook provided at the top for triggering a syncobj.
>
> Note that this requires a libdrm version more recent than is requested.
>
> > ---
> > tests/Makefile.sources | 1 +
> > tests/syncobj_wait.c | 624 ++
> +++
> > 2 files changed, 625 insertions(+)
> > create mode 100644 tests/syncobj_wait.c
> >
> > diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> > index bb013c7..430b637 100644
> > --- a/tests/Makefile.sources
> > +++ b/tests/Makefile.sources
> > @@ -230,6 +230,7 @@ TESTS_progs = \
> > prime_vgem \
> > sw_sync \
> > syncobj_basic \
> > + syncobj_wait \
> > template \
> > tools_test \
> > vgem_basic \
> > diff --git a/tests/syncobj_wait.c b/tests/syncobj_wait.c
> > new file mode 100644
> > index 000..6689d34
> > --- /dev/null
> > +++ b/tests/syncobj_wait.c
> > @@ -0,0 +1,624 @@
> > +/*
> > + * Copyright © 2017 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> obtaining
> a
> > + * copy of this software and associated documentation files (the
> "Software"),
> > + * to deal in the Software without restriction, including without
> limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom
> the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including the
> next
> > + * paragraph) shall be included in all copies or substantial portions
> of
> the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
> SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> > + * IN THE SOFTWARE.
> > + */
> > +
> > +#include "igt.h"
> > +#include
> > +#include
> > +#include
> > +#include "drm.h"
> > +
> > +IGT_TEST_DESCRIPTION("Tests for the drm sync object wait API");
> > +
> > +/* One one tenth of a second */
> > +#define SHORT_TIME_NSEC 1ull
> > +
> > +/** A per-platform function which triggers a set of sync objects
> > + *
> > + * If wait is set, the function should wait for the work to complete so
> > + * that an immediate call to SYNCOBJ_WAIT will return success. If wait
> is
> > + * not set, then the function should try to submit enough work that an
> > + * immediate call to SYNCOBJ_WAIT with a timeout of 0 will time out.
> > + */
> > +void (*trigger_syncobj)(int fd, uint32_t *syncobjs, int count, bool
> wait);
> > +
> > +#define NSECS_PER_SEC 10ull
> > +
> > +static uint64_t
> > +gettime_ns(void)
> > +{
> > + struct timespec current;
> > + clock_gettime(CLOCK_MONOTONIC, ¤t);
> > + return (uint64_t)current.tv_sec * NSECS_PER_SEC + current.tv_nsec;
> > +}
> > +
> > +static uint64_t
> > +short_timeout(void)
> > +{
> > + return gettime_ns() + SHORT_TIME_NSEC;
> > +}
> > +
> > +static uint32_t
> > +syncobj_create(int fd)
> > +{
> > + struct drm_syncobj_create create = { 0 };
> > + int ret;
> > +
> > + ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &create);
> > + igt_assert(ret == 0);
> > + igt_assert(create.handle > 0);
> > +
> > + return create.handle;
> > +}
> > +
> > +static void
> > +syncobj_destroy(int fd, uint32_t handle)
> > +{
> > + struct drm_syncobj_destroy destroy = { 0 };
> > + int ret;
> > +
> > + destroy.handle = handle;
> > + ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_DESTROY, &destroy);
> > + igt_assert(ret == 0);
> > +}
> > +
> > +struct delayed_trigger {
> > +
[Intel-gfx] [PATCH i-g-t] syncobj: Add some wait and reset tests (v3)
This adds both trivial error-checking tests as well as more complex
tests which actually test whether or not waits do what they're supposed
to do. They only currently work on i915 but it should be simple to hook
them up for other drivers by simply implementing the little function
pointer hook provided at the top for triggering a syncobj.
v2:
- Actually add the reset tests.
v3:
- Only do one execbuf for trigger
- Use do_ioctl and do_ioctl_err
- Better check for syncobj support
- Add local_/LOCAL_ defines of things
- Use a timer instead of a pthread
Signed-off-by: Jason Ekstrand
---
tests/Makefile.sources | 1 +
tests/syncobj_wait.c | 691 +
2 files changed, 692 insertions(+)
create mode 100644 tests/syncobj_wait.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index bb013c7..430b637 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -230,6 +230,7 @@ TESTS_progs = \
prime_vgem \
sw_sync \
syncobj_basic \
+ syncobj_wait \
template \
tools_test \
vgem_basic \
diff --git a/tests/syncobj_wait.c b/tests/syncobj_wait.c
new file mode 100644
index 000..d584b96
--- /dev/null
+++ b/tests/syncobj_wait.c
@@ -0,0 +1,691 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include
+#include
+#include
+#include "drm.h"
+
+IGT_TEST_DESCRIPTION("Tests for the drm sync object wait API");
+
+/* One tenth of a second */
+#define SHORT_TIME_NSEC 1ull
+
+/** A per-platform function which triggers a set of sync objects
+ *
+ * If wait is set, the function should wait for the work to complete so
+ * that an immediate call to SYNCOBJ_WAIT will return success. If wait is
+ * not set, then the function should try to submit enough work that an
+ * immediate call to SYNCOBJ_WAIT with a timeout of 0 will time out.
+ */
+void (*trigger_syncobj)(int fd, uint32_t *syncobjs, int count, bool wait);
+
+#define LOCAL_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
+#define LOCAL_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
+struct local_syncobj_wait {
+ __u64 handles;
+ /* absolute timeout */
+ __s64 timeout_nsec;
+ __u32 count_handles;
+ __u32 flags;
+ __u32 first_signaled; /* only valid when not waiting all */
+ __u32 pad;
+};
+
+struct local_syncobj_reset {
+ __u32 handle;
+ __u32 flags;
+};
+
+#define LOCAL_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct
local_syncobj_wait)
+#define LOCAL_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct
local_syncobj_reset)
+
+#define NSECS_PER_SEC 10ull
+
+static uint64_t
+gettime_ns(void)
+{
+ struct timespec current;
+ clock_gettime(CLOCK_MONOTONIC, ¤t);
+ return (uint64_t)current.tv_sec * NSECS_PER_SEC + current.tv_nsec;
+}
+
+static uint64_t
+short_timeout(void)
+{
+ return gettime_ns() + SHORT_TIME_NSEC;
+}
+
+static uint32_t
+syncobj_create(int fd)
+{
+ struct drm_syncobj_create create = { 0 };
+ int ret;
+
+ ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &create);
+ igt_assert(ret == 0);
+ igt_assert(create.handle > 0);
+
+ return create.handle;
+}
+
+static void
+syncobj_destroy(int fd, uint32_t handle)
+{
+ struct drm_syncobj_destroy destroy = { 0 };
+ int ret;
+
+ destroy.handle = handle;
+ ret = ioctl(fd, DRM_IOCTL_SYNCOBJ_DESTROY, &destroy);
+ igt_assert(ret == 0);
+}
+
+struct delayed_trigger {
+ int fd;
+ uint32_t *syncobjs;
+ int count;
+ uint64_t nsec;
+};
+
+static void
+trigger_syncobj_delayed_func(union sigval sigval)
+{
+ struct delayed_trigger *trigger = sigval.sival_ptr;
+ struct timespec time;
+
+ trigger_syncobj(trigger->fd, trigger->syncobjs, trigger->count, true);
+ free(trigger);
+}
+
+static timer_t
+trigger_syncobj_delaye
[Intel-gfx] [PATCH] drm/vgem: Couple in drm_syncobj support
To further facilitate GEM testing, allow testing of drm_syncobj by
attaching them to vgem fences. These fences are already employed by igt
for testing inter-driver fence handling (across dmabuf and sync_file).
An igt example use would be like:
int vgem = drm_driver_open(DRIVER_VGEM);
uint32_t handle = vgem_create_dummy(vgem);
uint32_t syncobj = drm_syncobj_create(vgem);
uint32_t fence = drmIoctl(vgem,
DRM_IOCTL_VGEM_FENCE_ATTACH,
&(struct vgem_fence_attach){
.handle = handle,
.flags = VGEM_FENCE_SYNCOBJ,
.syncobj = syncobj,
});
/* ... use syncobj for profit ... */
vgem_fence_signal(vgem, fence);
For wider use though, there is little immediate benefit to syncobj
over the vgem fence as both are handles in an idr (the fence here is not
a sync-file fd like in most other drivers). The main benefit for syncobj
is that it allows to create channels between objects and drivers by
virtue of its persistence beyond the vgem fence itself.
Signed-off-by: Chris Wilson
Cc: Jason Ekstrand
Cc: Daniel Vetter
---
drivers/gpu/drm/vgem/vgem_drv.c | 4 +++-
drivers/gpu/drm/vgem/vgem_fence.c | 26 ++
include/drm/drm_syncobj.h | 2 ++
include/uapi/drm/vgem_drm.h | 3 ++-
4 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/vgem/vgem_drv.c b/drivers/gpu/drm/vgem/vgem_drv.c
index 12289673f457..a0202e1eaf6b 100644
--- a/drivers/gpu/drm/vgem/vgem_drv.c
+++ b/drivers/gpu/drm/vgem/vgem_drv.c
@@ -432,7 +432,9 @@ static void vgem_release(struct drm_device *dev)
}
static struct drm_driver vgem_driver = {
- .driver_features= DRIVER_GEM | DRIVER_PRIME,
+ .driver_features= (DRIVER_GEM |
+ DRIVER_PRIME |
+ DRIVER_SYNCOBJ),
.release= vgem_release,
.open = vgem_open,
.postclose = vgem_postclose,
diff --git a/drivers/gpu/drm/vgem/vgem_fence.c
b/drivers/gpu/drm/vgem/vgem_fence.c
index 3109c8308eb5..988e860c03d3 100644
--- a/drivers/gpu/drm/vgem/vgem_fence.c
+++ b/drivers/gpu/drm/vgem/vgem_fence.c
@@ -23,6 +23,8 @@
#include
#include
+#include
+
#include "vgem_drv.h"
#define VGEM_FENCE_TIMEOUT (10*HZ)
@@ -156,20 +158,30 @@ int vgem_fence_attach_ioctl(struct drm_device *dev,
struct drm_vgem_fence_attach *arg = data;
struct vgem_file *vfile = file->driver_priv;
struct reservation_object *resv;
+ struct drm_syncobj *sync = NULL;
struct drm_gem_object *obj;
struct dma_fence *fence;
int ret;
- if (arg->flags & ~VGEM_FENCE_WRITE)
- return -EINVAL;
-
- if (arg->pad)
+ if (arg->flags & ~(VGEM_FENCE_WRITE | VGEM_FENCE_SYNCOBJ))
return -EINVAL;
obj = drm_gem_object_lookup(file, arg->handle);
if (!obj)
return -ENOENT;
+ if (arg->flags & VGEM_FENCE_SYNCOBJ) {
+ sync = drm_syncobj_find(file, arg->syncobj);
+ if (!sync) {
+ ret = -ENOENT;
+ goto err;
+ }
+
+ /* We don't check if the current syncobj is busy or not, we
+* will just replace it with ourselves.
+*/
+ }
+
ret = attach_dmabuf(dev, obj);
if (ret)
goto err;
@@ -207,12 +219,18 @@ int vgem_fence_attach_ioctl(struct drm_device *dev,
ret = 0;
}
}
+
+ if (ret == 0 && sync)
+ drm_syncobj_replace_fence(sync, fence);
+
err_fence:
if (ret) {
dma_fence_signal(fence);
dma_fence_put(fence);
}
err:
+ if (sync)
+ drm_syncobj_put(sync);
drm_gem_object_unreference_unlocked(obj);
return ret;
}
diff --git a/include/drm/drm_syncobj.h b/include/drm/drm_syncobj.h
index 89976da542b1..9010ab8343e5 100644
--- a/include/drm/drm_syncobj.h
+++ b/include/drm/drm_syncobj.h
@@ -28,6 +28,8 @@
#include "linux/dma-fence.h"
+struct drm_file;
+
/**
* struct drm_syncobj - sync object.
*
diff --git a/include/uapi/drm/vgem_drm.h b/include/uapi/drm/vgem_drm.h
index bf66f5db6da8..94777197e561 100644
--- a/include/uapi/drm/vgem_drm.h
+++ b/include/uapi/drm/vgem_drm.h
@@ -46,8 +46,9 @@ struct drm_vgem_fence_attach {
__u32 handle;
__u32 flags;
#define VGEM_FENCE_WRITE 0x1
+#define VGEM_FENCE_SYNCOBJ 0x2
__u32 out_fence;
- __u32 pad;
+ __u32 syncobj;
};
struct drm_vgem_fence_signal {
--
2.13.3
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesk
[Intel-gfx] ✓ Fi.CI.BAT: success for syncobj: Add some wait and reset tests (rev3)
== Series Details == Series: syncobj: Add some wait and reset tests (rev3) URL : https://patchwork.freedesktop.org/series/28567/ State : success == Summary == IGT patchset tested on top of latest successful build c129026622accef6f54c0cfb0dc55e930cfa60b5 igt: add syncobj_basic. with latest DRM-Tip kernel build CI_DRM_2942 2d0288b5b28c drm-tip: 2017y-08m-09d-18h-09m-54s UTC integration manifest Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: fail -> PASS (fi-snb-2600) fdo#17 Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: dmesg-warn -> PASS (fi-byt-n2820) fdo#101705 fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17 fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705 fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:435s fi-bdw-gvtdvmtotal:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:418s fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:359s fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:494s fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:495s fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:519s fi-byt-n2820 total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:514s fi-glk-2atotal:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:590s fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:426s fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:403s fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:420s fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:510s fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:473s fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:461s fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:575s fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:572s fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:518s fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:455s fi-skl-6700k total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:639s fi-skl-6770hqtotal:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:468s fi-skl-gvtdvmtotal:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:425s fi-skl-x1585ltotal:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:486s fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:558s fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:415s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_47/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH libdrm] drm: Remove create_handle() drm_framebuffer "virtual".
Den 09.08.2017 01.42, skrev Joe Kniss:
Because all drivers currently use gem objects for framebuffer planes,
the virtual create_handle() is not required. This change adds a
struct drm_gem_object *gems[4] field to drm_framebuffer and removes
create_handle() function pointer from drm_framebuffer_funcs. The
corresponding *_create_handle() function is removed from each driver.
In many cases this change eliminates a struct *_framebuffer object,
as the only need for the derived struct is the addition of the gem
object pointer.
TESTED: compiled: allyesconfig ARCH=x86,arm platforms:i915, rockchip
Signed-off-by: Joe Kniss
---
Hi Joe,
I'm also looking into adding gem objs to drm_framebuffer in this patch:
[PATCH v2 01/22] drm: Add GEM backed framebuffer library
https://lists.freedesktop.org/archives/dri-devel/2017-August/149782.html
[...]
diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c
b/drivers/gpu/drm/drm_fb_cma_helper.c
index ade319d10e70..f5f011b910b1 100644
--- a/drivers/gpu/drm/drm_fb_cma_helper.c
+++ b/drivers/gpu/drm/drm_fb_cma_helper.c
@@ -31,14 +31,9 @@
#define DEFAULT_FBDEFIO_DELAY_MS 50
-struct drm_fb_cma {
- struct drm_framebuffer fb;
- struct drm_gem_cma_object *obj[4];
-};
-
struct drm_fbdev_cma {
struct drm_fb_helperfb_helper;
- struct drm_fb_cma *fb;
+ struct drm_framebuffer *fb;
This fb pointer isn't necessary, since fb_helper already has one.
Noralf.
const struct drm_framebuffer_funcs *fb_funcs;
};
@@ -72,7 +67,6 @@ struct drm_fbdev_cma {
*
* static struct drm_framebuffer_funcs driver_fb_funcs = {
* .destroy = drm_fb_cma_destroy,
- * .create_handle = drm_fb_cma_create_handle,
* .dirty = driver_fb_dirty,
* };
*
@@ -90,67 +84,50 @@ static inline struct drm_fbdev_cma *to_fbdev_cma(struct
drm_fb_helper *helper)
return container_of(helper, struct drm_fbdev_cma, fb_helper);
}
-static inline struct drm_fb_cma *to_fb_cma(struct drm_framebuffer *fb)
-{
- return container_of(fb, struct drm_fb_cma, fb);
-}
-
void drm_fb_cma_destroy(struct drm_framebuffer *fb)
{
- struct drm_fb_cma *fb_cma = to_fb_cma(fb);
int i;
for (i = 0; i < 4; i++) {
- if (fb_cma->obj[i])
- drm_gem_object_put_unlocked(&fb_cma->obj[i]->base);
+ if (fb->gem_objs[i])
+ drm_gem_object_put_unlocked(fb->gem_objs[i]);
}
drm_framebuffer_cleanup(fb);
- kfree(fb_cma);
+ kfree(fb);
}
EXPORT_SYMBOL(drm_fb_cma_destroy);
-int drm_fb_cma_create_handle(struct drm_framebuffer *fb,
- struct drm_file *file_priv, unsigned int *handle)
-{
- struct drm_fb_cma *fb_cma = to_fb_cma(fb);
-
- return drm_gem_handle_create(file_priv,
- &fb_cma->obj[0]->base, handle);
-}
-EXPORT_SYMBOL(drm_fb_cma_create_handle);
-
static struct drm_framebuffer_funcs drm_fb_cma_funcs = {
.destroy= drm_fb_cma_destroy,
- .create_handle = drm_fb_cma_create_handle,
};
-static struct drm_fb_cma *drm_fb_cma_alloc(struct drm_device *dev,
+static struct drm_framebuffer *drm_fb_cma_alloc(struct drm_device *dev,
const struct drm_mode_fb_cmd2 *mode_cmd,
struct drm_gem_cma_object **obj,
unsigned int num_planes, const struct drm_framebuffer_funcs *funcs)
{
- struct drm_fb_cma *fb_cma;
+ struct drm_framebuffer *fb;
int ret;
int i;
- fb_cma = kzalloc(sizeof(*fb_cma), GFP_KERNEL);
- if (!fb_cma)
+ fb = kzalloc(sizeof(*fb), GFP_KERNEL);
+ if (!fb)
return ERR_PTR(-ENOMEM);
- drm_helper_mode_fill_fb_struct(dev, &fb_cma->fb, mode_cmd);
+ drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd);
for (i = 0; i < num_planes; i++)
- fb_cma->obj[i] = obj[i];
+ fb->gem_objs[i] = &obj[i]->base;
- ret = drm_framebuffer_init(dev, &fb_cma->fb, funcs);
+ ret = drm_framebuffer_init(dev, fb, funcs);
if (ret) {
dev_err(dev->dev, "Failed to initialize framebuffer: %d\n",
ret);
- kfree(fb_cma);
+ kfree(fb);
return ERR_PTR(ret);
}
- return fb_cma;
+ return fb;
}
/**
@@ -171,7 +148,7 @@ struct drm_framebuffer *drm_fb_cma_create_with_funcs(struct
drm_device *dev,
const struct drm_framebuffer_funcs *funcs)
{
const struct drm_format_info *info;
- struct drm_fb_cma *fb_cma;
+ struct drm_framebuffer *fb;
struct drm_gem_cma_object *objs[4];
struct drm_gem_object *obj;
int ret;
@@ -205,13 +182,13 @@ struct drm_framebuffer
*drm_fb_cma_create_with_funcs(struct drm_device *dev,
objs[i] = to_drm_gem_cma_obj(obj);
}
- fb_cma = drm_fb_cma_alloc(dev, mode_cmd, objs, i, funcs);
- if (IS_ERR(fb_cma)) {
- ret = PTR_ERR(f
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/vgem: Couple in drm_syncobj support
== Series Details == Series: drm/vgem: Couple in drm_syncobj support URL : https://patchwork.freedesktop.org/series/28576/ State : success == Summary == Series 28576v1 drm/vgem: Couple in drm_syncobj support https://patchwork.freedesktop.org/api/1.0/series/28576/revisions/1/mbox/ Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: fail -> PASS (fi-snb-2600) fdo#17 fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17 fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:434s fi-bdw-gvtdvmtotal:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:419s fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:362s fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:495s fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:482s fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:527s fi-byt-n2820 total:279 pass:250 dwarn:1 dfail:0 fail:0 skip:28 time:512s fi-glk-2atotal:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:582s fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:433s fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:403s fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:416s fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:511s fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:475s fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:466s fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:568s fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:579s fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:533s fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:442s fi-skl-6700k total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:644s fi-skl-6770hqtotal:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:463s fi-skl-gvtdvmtotal:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:431s fi-skl-x1585ltotal:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:483s fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:548s fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:412s 2d0288b5b28c0d67460f0258a41bb4f78b812f29 drm-tip: 2017y-08m-09d-18h-09m-54s UTC integration manifest 9888927f81b2 drm/vgem: Couple in drm_syncobj support == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5355/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6] drm/i915/edp: Allow alternate fixed mode for eDP if available.
Some fixed resolution panels actually support more than one mode,
with the only thing different being the refresh rate. Having this
alternate mode available to us is desirable, because it allows us to
test PSR on panels whose setup time at the preferred mode is too long.
With this patch we allow the use of the alternate mode if it's
available and it was specifically requested.
v2 and v3: Rebase
v4: * Fix up some leaky mode stuff (Chris)
* Rebase
v5: * Fix a NULL pointer derefrence (David Weinehall)
v6: * Whitespace / spelling / checkpatch clean-up; no functional
change. (David)
* Rebase
Cc: David Weinehall
Cc: Rodrigo Vivi
Cc: Paulo Zanoni
Cc: Jani Nikula
Cc: Chris Wilson
Reviewed-by: David Weinehall
Signed-off-by: Jim Bride
---
drivers/gpu/drm/i915/intel_dp.c| 38 +-
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_dsi.c | 2 +-
drivers/gpu/drm/i915/intel_dvo.c | 2 +-
drivers/gpu/drm/i915/intel_lvds.c | 3 ++-
drivers/gpu/drm/i915/intel_panel.c | 6 ++
6 files changed, 45 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 76c8a0b..576b5af 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1606,6 +1606,23 @@ static int intel_dp_compute_bpp(struct intel_dp
*intel_dp,
return bpp;
}
+static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
+ struct drm_display_mode *m2)
+{
+ bool bres = false;
+
+ if (m1 && m2)
+ bres = (m1->hdisplay == m2->hdisplay &&
+ m1->hsync_start == m2->hsync_start &&
+ m1->hsync_end == m2->hsync_end &&
+ m1->htotal == m2->htotal &&
+ m1->vdisplay == m2->vdisplay &&
+ m1->vsync_start == m2->vsync_start &&
+ m1->vsync_end == m2->vsync_end &&
+ m1->vtotal == m2->vtotal);
+ return bres;
+}
+
bool
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
@@ -1652,8 +1669,16 @@ intel_dp_compute_config(struct intel_encoder *encoder,
pipe_config->has_audio = intel_conn_state->force_audio ==
HDMI_AUDIO_ON;
if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
- intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
- adjusted_mode);
+ struct drm_display_mode *panel_mode =
+ intel_connector->panel.alt_fixed_mode;
+ struct drm_display_mode *req_mode = &pipe_config->base.mode;
+
+ if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
+ panel_mode = intel_connector->panel.fixed_mode;
+
+ drm_mode_debug_printmodeline(panel_mode);
+
+ intel_fixed_panel_mode(panel_mode, adjusted_mode);
if (INTEL_GEN(dev_priv) >= 9) {
int ret;
@@ -5780,6 +5805,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_display_mode *fixed_mode = NULL;
+ struct drm_display_mode *alt_fixed_mode = NULL;
struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
struct drm_display_mode *scan;
@@ -5835,13 +5861,14 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
}
intel_connector->edid = edid;
- /* prefer fixed mode from EDID if available */
+ /* prefer fixed mode from EDID if available, save an alt mode also */
list_for_each_entry(scan, &connector->probed_modes, head) {
if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
fixed_mode = drm_mode_duplicate(dev, scan);
downclock_mode = intel_dp_drrs_init(
intel_connector, fixed_mode);
- break;
+ } else if (!alt_fixed_mode) {
+ alt_fixed_mode = drm_mode_duplicate(dev, scan);
}
}
@@ -5878,7 +5905,8 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
pipe_name(pipe));
}
- intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
+ intel_panel_init(&intel_connector->panel, fixed_mode, alt_fixed_mode,
+downclock_mode);
intel_connector->panel.backlight.power = intel_edp_backlight_power;
intel_panel_setup_backlight(connector, pipe);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f91de9c..b3fcbb9 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915
Re: [Intel-gfx] [PATCH 1/3] drm/i915/cnl: Add allowed DP rates for Cannonlake.
Clint or Mika, could you please review this patch and next 2 here?
I remember Clint telling me at some point that rates had possibly
change on spec but I checked here and I still see:
"eDP/DP link bit rates: 1.62, 2.16, 2.7, 3.24, 4.32, 5.4, 6.48*, 8.1* GHz"
Thanks in advance,
Rodrigo.
On Thu, Jul 6, 2017 at 1:54 PM, Rodrigo Vivi wrote:
> One warning is that in order to get DPLL Link rates
> 3240 and 4050 that allows 648000 and 81 is that:
> "Some SKUs may require elevated I/O voltage to support
> this."
>
> v2: Rebase on top of source_rates changes.
>
> Cc: Clint Taylor
> Cc: Mika Kahola
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_dp.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 2d42d09..4355bdf 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -97,6 +97,9 @@ struct dp_link_dpll {
> 324000, 432000, 54 };
> static const int skl_rates[] = { 162000, 216000, 27,
> 324000, 432000, 54 };
> +static const int cnl_rates[] = { 162000, 216000, 27,
> +324000, 432000, 54,
> +648000, 81 };
> static const int default_rates[] = { 162000, 27, 54 };
>
> /**
> @@ -238,6 +241,9 @@ int intel_dp_max_lane_count(struct intel_dp *intel_dp)
> if (IS_GEN9_LP(dev_priv)) {
> source_rates = bxt_rates;
> size = ARRAY_SIZE(bxt_rates);
> + } else if (IS_CANNONLAKE(dev_priv)) {
> + source_rates = cnl_rates;
> + size = ARRAY_SIZE(cnl_rates);
> } else if (IS_GEN9_BC(dev_priv)) {
> source_rates = skl_rates;
> size = ARRAY_SIZE(skl_rates);
> --
> 1.9.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/cnl: Add slice and subslice information to debugfs.
A missing part to EU slice power gating is the
debugfs interface. This patch actually should have been
squashed to the initial EU slice power gating one.
v2: Initial patch was merged without this part.
Fixes: c7ae7e9ab207 ("drm/i915/cnl: Configure EU slice power gating.")
Cc: Joonas Lahtinen
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 6480897bcaf4..329fb3649dc3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4560,7 +4560,7 @@ static void gen9_sseu_device_status(struct
drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
- if (IS_GEN9_BC(dev_priv))
+ if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
sseu->subslice_mask =
INTEL_INFO(dev_priv)->sseu.subslice_mask;
--
2.13.2
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt] igt: Add vgem_syncobj
Exercise the drm_syncobj / vGEM coupling.
Signed-off-by: Chris Wilson
---
lib/igt_vgem.c | 68 +++-
lib/igt_vgem.h | 15 +++-
tests/Makefile.sources | 1 +
tests/vgem_syncobj.c | 212 +
4 files changed, 276 insertions(+), 20 deletions(-)
create mode 100644 tests/vgem_syncobj.c
diff --git a/lib/igt_vgem.c b/lib/igt_vgem.c
index 21cccb37..d2f65adb 100644
--- a/lib/igt_vgem.c
+++ b/lib/igt_vgem.c
@@ -64,6 +64,15 @@ void vgem_create(int fd, struct vgem_bo *bo)
igt_assert_eq(__vgem_create(fd, bo), 0);
}
+struct vgem_bo vgem_create_dummy(int fd)
+{
+ struct vgem_bo bo = { .width = 1, .height = 1, .bpp = 4 };
+
+ vgem_create(fd, &bo);
+
+ return bo;
+}
+
void *__vgem_mmap(int fd, struct vgem_bo *bo, unsigned prot)
{
struct drm_mode_map_dumb arg;
@@ -134,26 +143,11 @@ static int __vgem_fence_attach(int fd, struct
local_vgem_fence_attach *arg)
bool vgem_fence_has_flag(int fd, unsigned flags)
{
- struct local_vgem_fence_attach arg;
- struct vgem_bo bo;
- bool ret = false;
+ struct local_vgem_fence_attach arg = {
+ .flags = flags,
+ };
- memset(&bo, 0, sizeof(bo));
- bo.width = 1;
- bo.height = 1;
- bo.bpp = 32;
- vgem_create(fd, &bo);
-
- memset(&arg, 0, sizeof(arg));
- arg.handle = bo.handle;
- arg.flags = flags;
- if (__vgem_fence_attach(fd, &arg) == 0) {
- vgem_fence_signal(fd, arg.out_fence);
- ret = true;
- }
- gem_close(fd, bo.handle);
-
- return ret;
+ return __vgem_fence_attach(fd, &arg) != -EINVAL;
}
uint32_t vgem_fence_attach(int fd, struct vgem_bo *bo, unsigned flags)
@@ -167,6 +161,42 @@ uint32_t vgem_fence_attach(int fd, struct vgem_bo *bo,
unsigned flags)
return arg.out_fence;
}
+int __vgem_fence_attach_to_syncobj(int fd,
+ struct vgem_bo *bo,
+ uint32_t syncobj,
+ unsigned flags,
+ uint32_t *fence)
+{
+ struct local_vgem_fence_attach arg = {
+ .handle = bo->handle,
+ .flags = VGEM_FENCE_SYNCOBJ | flags,
+ .pad = syncobj,
+ };
+ int err;
+
+ err = __vgem_fence_attach(fd, &arg);
+ if (err)
+ return err;
+
+ *fence = arg.out_fence;
+ return 0;
+}
+
+uint32_t vgem_fence_attach_to_syncobj(int fd,
+ struct vgem_bo *bo,
+ uint32_t syncobj,
+ unsigned flags)
+{
+ struct local_vgem_fence_attach arg = {
+ .handle = bo->handle,
+ .flags = VGEM_FENCE_SYNCOBJ | flags,
+ .pad = syncobj,
+ };
+ igt_assert_eq(__vgem_fence_attach(fd, &arg), 0);
+
+ return arg.out_fence;
+}
+
static int ioctl_vgem_fence_signal(int fd, struct local_vgem_fence_signal *arg)
{
int err = 0;
diff --git a/lib/igt_vgem.h b/lib/igt_vgem.h
index 002ad7f0..f50c70b4 100644
--- a/lib/igt_vgem.h
+++ b/lib/igt_vgem.h
@@ -35,15 +35,28 @@ struct vgem_bo {
int __vgem_create(int fd, struct vgem_bo *bo);
void vgem_create(int fd, struct vgem_bo *bo);
+struct vgem_bo vgem_create_dummy(int fd);
void *__vgem_mmap(int fd, struct vgem_bo *bo, unsigned prot);
void *vgem_mmap(int fd, struct vgem_bo *bo, unsigned prot);
bool vgem_has_fences(int fd);
bool vgem_fence_has_flag(int fd, unsigned flags);
+
uint32_t vgem_fence_attach(int fd, struct vgem_bo *bo, unsigned flags);
#define VGEM_FENCE_WRITE 0x1
-#define WIP_VGEM_FENCE_NOTIMEOUT 0x2
+#define VGEM_FENCE_SYNCOBJ 0x2
+#define WIP_VGEM_FENCE_NOTIMEOUT (1<<31)
+int __vgem_fence_attach_to_syncobj(int fd,
+ struct vgem_bo *bo,
+ uint32_t syncobj,
+ unsigned flags,
+ uint32_t *fence);
+uint32_t vgem_fence_attach_to_syncobj(int fd,
+ struct vgem_bo *bo,
+ uint32_t syncobj,
+ unsigned flags);
+
int __vgem_fence_signal(int fd, uint32_t fence);
void vgem_fence_signal(int fd, uint32_t fence);
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 7a99cafc..3352aad4 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -235,6 +235,7 @@ TESTS_progs = \
tools_test \
vgem_basic \
vgem_slow \
+ vgem_syncobj \
$(NULL)
TESTS_progs_X = \
diff --git a/tests/vgem_syncobj.c b/tests/vgem_syncobj.c
new file mode 100644
index ..6ef2d8ba
--- /dev/null
+++ b/tests/vgem_syncobj.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaini
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/edp: Allow alternate fixed mode for eDP if available.
== Series Details == Series: drm/i915/edp: Allow alternate fixed mode for eDP if available. URL : https://patchwork.freedesktop.org/series/28578/ State : success == Summary == Series 28578v1 drm/i915/edp: Allow alternate fixed mode for eDP if available. https://patchwork.freedesktop.org/api/1.0/series/28578/revisions/1/mbox/ Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: fail -> PASS (fi-snb-2600) fdo#17 fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17 fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:439s fi-bdw-gvtdvmtotal:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:424s fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:356s fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:489s fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:491s fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:522s fi-byt-n2820 total:279 pass:250 dwarn:1 dfail:0 fail:0 skip:28 time:509s fi-glk-2atotal:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:588s fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:426s fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:408s fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:419s fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:496s fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:474s fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:459s fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:579s fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:574s fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:528s fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:449s fi-skl-6700k total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:639s fi-skl-6770hqtotal:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:465s fi-skl-gvtdvmtotal:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:424s fi-skl-x1585ltotal:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:484s fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:547s fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:406s 2d0288b5b28c0d67460f0258a41bb4f78b812f29 drm-tip: 2017y-08m-09d-18h-09m-54s UTC integration manifest 13011d53221c drm/i915/edp: Allow alternate fixed mode for eDP if available. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5356/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 1/2] Add support for subtest-specific documentation
On 8/9/2017 4:40 AM, Petri Latvala wrote:
The current documentation for tests is limited to a single string per
test binary. This patch adds support for documenting individual
subtests.
The syntax for subtest documentation is:
igt_document_subtest("Frob knobs to see if one of the "
"crossbeams will go out of skew on the "
"treadle.\n");
igt_subtest("knob-frobbing-askew")
test_frob();
or with a format string:
for_example_loop(e) {
igt_document_subtest_f("Frob %s to see if one of the "
"crossbeams will go out of skew on the "
"treadle.\n", e->readable_name);
igt_subtest_f("%s-frob-askew", e->name)
test_frob(e);
}
The documentation cannot be extracted from just comments, because
associating them with the correct subtest name will then require doing
pattern matching in the documentation generator, for subtests where
the name is generated at runtime using igt_subtest_f.
v2: Rebase, change function name in commit message to match code
Signed-off-by: Petri Latvala
Acked-by: Leo Li
---
lib/igt_aux.c | 8 ++--
lib/igt_core.c | 147 +
lib/igt_core.h | 6 ++-
3 files changed, 126 insertions(+), 35 deletions(-)
diff --git a/lib/igt_aux.c b/lib/igt_aux.c
index f428f15..d56f41f 100644
--- a/lib/igt_aux.c
+++ b/lib/igt_aux.c
@@ -311,7 +311,7 @@ static void sig_handler(int i)
*/
void igt_fork_signal_helper(void)
{
- if (igt_only_list_subtests())
+ if (igt_only_collect_data())
return;
/* We pick SIGCONT as it is a "safe" signal - if we send SIGCONT to
@@ -344,7 +344,7 @@ void igt_fork_signal_helper(void)
*/
void igt_stop_signal_helper(void)
{
- if (igt_only_list_subtests())
+ if (igt_only_collect_data())
return;
igt_stop_helper(&signal_helper);
@@ -375,7 +375,7 @@ static void __attribute__((noreturn))
shrink_helper_process(int fd, pid_t pid)
*/
void igt_fork_shrink_helper(int drm_fd)
{
- assert(!igt_only_list_subtests());
+ assert(!igt_only_collect_data());
igt_require(igt_drop_caches_has(drm_fd, DROP_SHRINK_ALL));
igt_fork_helper(&shrink_helper)
shrink_helper_process(drm_fd, getppid());
@@ -473,7 +473,7 @@ void igt_stop_hang_detector(void)
#else
void igt_fork_hang_detector(int fd)
{
- if (igt_only_list_subtests())
+ if (igt_only_collect_data())
return;
}
diff --git a/lib/igt_core.c b/lib/igt_core.c
index c0488e9..f1cb0e9 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -99,7 +99,7 @@
*
* To allow this i-g-t provides #igt_fixture code blocks for setup code
outside
* of subtests and automatically skips the subtest code blocks themselves. For
- * special cases igt_only_list_subtests() is also provided. For setup code only
+ * special cases igt_only_collect_data() is also provided. For setup code only
* shared by a group of subtest encapsulate the #igt_fixture block and all the
* subtestest in a #igt_subtest_group block.
*
@@ -253,9 +253,9 @@ static unsigned int exit_handler_count;
const char *igt_interactive_debug;
/* subtests helpers */
-static bool list_subtests = false;
-static char *run_single_subtest = NULL;
-static bool run_single_subtest_found = false;
+static char *single_subtest = NULL;
+static bool single_subtest_found = false;
+static char *current_subtest_documentation = NULL;
static const char *in_subtest = NULL;
static struct timespec subtest_time;
static clockid_t igt_clock = (clockid_t)-1;
@@ -265,6 +265,13 @@ static bool in_atexit_handler = false;
static enum {
CONT = 0, SKIP, FAIL
} skip_subtests_henceforth = CONT;
+static enum {
+ EXECUTE_ALL,
+ EXECUTE_SINGLE,
+ LIST_SUBTESTS,
+ DOCUMENT,
+ DOCUMENT_SINGLE
+} runmode = EXECUTE_ALL;
bool __igt_plain_output = false;
@@ -277,6 +284,8 @@ bool test_child;
enum {
OPT_LIST_SUBTESTS,
OPT_RUN_SUBTEST,
+ OPT_DOC_SUBTESTS,
+ OPT_DOC_SINGLE_SUBTEST,
OPT_DESCRIPTION,
OPT_DEBUG,
OPT_INTERACTIVE_DEBUG,
@@ -469,7 +478,7 @@ bool __igt_fixture(void)
{
assert(!in_fixture);
- if (igt_only_list_subtests())
+ if (igt_only_collect_data())
return false;
if (skip_subtests_henceforth)
@@ -563,7 +572,7 @@ static void low_mem_killer_disable(bool disable)
bool igt_exit_called;
static void common_exit_handler(int sig)
{
- if (!igt_only_list_subtests()) {
+ if (!igt_only_collect_data()) {
low_mem_killer_disable(false);
kick_fbcon(true);
}
@@ -583,7 +592,7 @@ static void print_version(void)
{
struct utsname uts;
- if (list_subtests)
+ if (igt_only_collect_data())
return;
uname(&uts);
@@ -599,6 +608,8 @@ static void print_usage(const char *help_str, boo
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Add slice and subslice information to debugfs.
== Series Details == Series: drm/i915/cnl: Add slice and subslice information to debugfs. URL : https://patchwork.freedesktop.org/series/28579/ State : success == Summary == Series 28579v1 drm/i915/cnl: Add slice and subslice information to debugfs. https://patchwork.freedesktop.org/api/1.0/series/28579/revisions/1/mbox/ Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: fail -> PASS (fi-snb-2600) fdo#17 Test gem_ringfill: Subgroup basic-default: pass -> SKIP (fi-bsw-n3050) fdo#101915 fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17 fdo#101915 https://bugs.freedesktop.org/show_bug.cgi?id=101915 fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:439s fi-bdw-gvtdvmtotal:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:424s fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:356s fi-bsw-n3050 total:279 pass:242 dwarn:0 dfail:0 fail:0 skip:37 time:495s fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:484s fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:524s fi-byt-n2820 total:279 pass:250 dwarn:1 dfail:0 fail:0 skip:28 time:509s fi-glk-2atotal:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:591s fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:430s fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:407s fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:423s fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:501s fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:472s fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:459s fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:566s fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:571s fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:520s fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:445s fi-skl-6700k total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:640s fi-skl-6770hqtotal:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:464s fi-skl-gvtdvmtotal:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:429s fi-skl-x1585ltotal:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:489s fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:545s fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:406s 2d0288b5b28c0d67460f0258a41bb4f78b812f29 drm-tip: 2017y-08m-09d-18h-09m-54s UTC integration manifest f611a691d78d drm/i915/cnl: Add slice and subslice information to debugfs. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5357/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
