Re: [Intel-gfx] [PATCH 05/20] drm/i915: Cancel reset-engine if we couldn't find an active request
On Tue, May 16, 2017 at 05:13:58PM -0700, Michel Thierry wrote:
> On 16/05/17 00:54, Chris Wilson wrote:
> >On Mon, May 15, 2017 at 03:25:27PM -0700, Michel Thierry wrote:
> >>On 5/15/2017 2:47 PM, Chris Wilson wrote:
> >>>On Mon, May 15, 2017 at 10:31:58PM +0100, Chris Wilson wrote:
> On Mon, May 15, 2017 at 02:20:01PM -0700, Michel Thierry wrote:
> >@@ -2827,21 +2830,34 @@ int i915_gem_reset_prepare_engine(struct
> >intel_engine_cs *engine)
> >
> > if (engine_stalled(engine)) {
> > request = i915_gem_find_active_request(engine);
> >-if (request && request->fence.error == -EIO)
> >-err = -EIO; /* Previous reset failed! */
> >+
> >+if (request) {
> >+if (request->fence.error == -EIO)
> >+return ERR_PTR(-EIO); /* Previous reset
> >failed! */
> >+
> >+if (__i915_gem_request_completed(request,
> >+
> >engine->hangcheck.seqno))
>
> This is not the seqno for the request, so this is incorrect. It will
> judge that the request was preempted (as hangcheck.seqno must be less
> thn request->global_seqno) and so conclude that the request was never
> completed.
>
> You just want if (i915_gem_request_completed(request))
> >>
> >>Thanks, I'll change the function.
> >>
> >>>
> >>>Also not here. This pardon check should be deferred to the caller just
> >>>before commiting to thre reset. In the case of global reset, we want to
> >>>gather up all the engines' active requests first, complete our
> >>>preparations and then double check the engine was hung.
> >>
> >>i915_reset_engine calls this directly, but 'full reset' [from
> >>i915_gem_reset_prepare()] would not be affected and it won't pardon
> >>anything... i915_gem_reset_engine is doing the double check you
> >>mention.
> >
> >Aye, but in the long run I was thinking of capturing this request in
> >engine->hangcheck.active_request and then we reuse that info in the later
> >phases.
>
> Capture hangcheck.active_request during hangcheck_declare_hang? Or
> still here in reset_prepare?
Not in the hangcheck worker itself since we want that to be as lockless
as we can make it and since putting it inside the reset works just as
well, we should.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] ✓ Fi.CI.BAT: success for Enhancement to intel_dp_aux_backlight driver (rev7)
== Series Details == Series: Enhancement to intel_dp_aux_backlight driver (rev7) URL : https://patchwork.freedesktop.org/series/21086/ State : success == Summary == Series 21086v7 Enhancement to intel_dp_aux_backlight driver https://patchwork.freedesktop.org/api/1.0/series/21086/revisions/7/mbox/ Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: pass -> FAIL (fi-snb-2600) fdo#17 fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17 fi-bdw-gvtdvmtotal:278 pass:256 dwarn:8 dfail:0 fail:0 skip:14 time:432s fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:492s fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:490s fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:415s fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:420s fi-skl-gvtdvmtotal:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 time:437s fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:535s fi-snb-2600 total:278 pass:248 dwarn:0 dfail:0 fail:1 skip:29 time:404s fi-bxt-j4205 failed to connect after reboot fi-kbl-7560u failed to connect after reboot fi-skl-6700k failed to connect after reboot 713f8ec675d5a793326b94d9a0cc484608eff75e drm-tip: 2017y-05m-16d-15h-22m-08s UTC integration manifest d43d284 drm/i915: Set PWM divider to match desired frequency in vbt b1c58bc drm: Add definition for eDP backlight frequency d79f3e2 drm/i915: Add option to support dynamic backlight via DPCD 76d9737 drm/i915: Allow choosing how to adjust brightness if both supported d6e0566 drm/i915: Drop AUX backlight enable check for backlight control == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4716/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] Call trace on 4.12.0-rc1
Hi, I'm using 4.12.0-rc1 from https://github.com/jwrdegoede/linux-sunxi and got the following weird trace yesterday. Previously I've been getting output similar to https://www.spinics.net/lists/intel-gfx/msg127638.html, some boots on 4.12.0-rc1 I don't get any trace at all. [ 2383.844192] perf: interrupt took too long (2522 > 2500), lowering kernel.perf_event_max_sample_rate to 79200 [ 2634.863978] [drm:intel_pipe_update_end] *ERROR* Atomic update failure on pipe A (start=157909 end=157910) time 322 us, min 1073, max 1079, scanline start 1063, end 1084 [ 2647.881794] perf: interrupt took too long (3193 > 3152), lowering kernel.perf_event_max_sample_rate to 62400 [ 3297.857921] perf: interrupt took too long (4020 > 3991), lowering kernel.perf_event_max_sample_rate to 49500 [ 4670.977136] mmc0: Tuning timeout, falling back to fixed sampling clock [ 4671.436604] mmc0: Tuning timeout, falling back to fixed sampling clock [ 4680.756302] mmc0: Tuning timeout, falling back to fixed sampling clock [ 4707.846872] perf: interrupt took too long (5046 > 5025), lowering kernel.perf_event_max_sample_rate to 39600 [ 4846.672969] RPM wakelock ref not held during HW access [ 4846.673050] [ cut here ] [ 4846.673084] WARNING: CPU: 0 PID: 5227 at drivers/gpu/drm/i915/intel_drv.h: 1780 intel_uncore_forcewake_get+0xa0/0xb0 [ 4846.673088] Modules linked in: snd_soc_sst_cht_bsw_nau8824 btusb btintel bluetooth axp288_fuel_gauge ecdh_generic axp288_charger extcon_axp288 axp288_adc snd_hdmi_lpe_audio snd_intel_sst_acpi extcon_intel_int3496 snd_intel_sst_core extcon_core snd_soc_nau8824 snd_soc_sst_atom_hifi2_platform snd_soc_core snd_compress snd_soc_sst_match snd_pcm snd_timer kxcjk_1013 industrialio_triggered_buffer intel_cht_int33fe snd soundcore intel_int0002 [ 4846.673201] CPU: 0 PID: 5227 Comm: kworker/0:1 Not tainted 4.12.0-rc1+ #3 [ 4846.673206] Hardware name: MEDION E2228T MD60250/NT16H, BIOS 5.11 02/27/2017 [ 4846.673224] Workqueue: events fuel_gauge_status_monitor [axp288_fuel_gauge] [ 4846.673235] task: 8800a85be800 task.stack: c9000261 [ 4846.673248] RIP: 0010:intel_uncore_forcewake_get+0xa0/0xb0 [ 4846.673255] RSP: 0018:c90002613aa0 EFLAGS: 00010286 [ 4846.673265] RAX: 002a RBX: 880136cc8000 RCX: 82063e88 [ 4846.673272] RDX: RSI: 0082 RDI: 0247 [ 4846.673278] RBP: c90002613ac0 R08: 002a R09: 02ac [ 4846.673284] R10: 0001 R11: R12: 0007 [ 4846.673289] R13: 0001 R14: R15: [ 4846.673298] FS: () GS:88013fc0() knlGS: [ 4846.673305] CS: 0010 DS: ES: CR0: 80050033 [ 4846.673311] CR2: 0758c709c000 CR3: 02009000 CR4: 001006f0 [ 4846.673317] Call Trace: [ 4846.673340] i915_pmic_bus_access_notifier+0x37/0x40 [ 4846.673354] notifier_call_chain+0x4a/0x70 [ 4846.673368] __blocking_notifier_call_chain+0x47/0x60 [ 4846.673380] blocking_notifier_call_chain+0x16/0x20 [ 4846.673393] iosf_mbi_call_pmic_bus_access_notifier_chain+0x1b/0x20 [ 4846.673406] baytrail_i2c_acquire+0x64/0x220 [ 4846.673420] i2c_dw_acquire_lock+0x21/0x50 [ 4846.673431] i2c_dw_xfer+0xa3/0x4a0 [ 4846.673444] __i2c_transfer+0x115/0x430 [ 4846.673456] i2c_transfer+0x5c/0xc0 [ 4846.673469] regmap_i2c_read+0x6d/0xa0 [ 4846.673482] _regmap_raw_read+0xda/0x210 [ 4846.673491] ? _regmap_raw_read+0xda/0x210 [ 4846.673503] ? __update_load_avg_se.isra.5+0x15b/0x180 [ 4846.673514] _regmap_bus_read+0x2a/0x60 [ 4846.673524] _regmap_read+0x6c/0x130 [ 4846.673535] regmap_read+0x3f/0x60 [ 4846.673549] fuel_gauge_reg_readb.isra.5+0x40/0x90 [axp288_fuel_gauge] [ 4846.673564] fuel_gauge_get_status+0x2d/0x100 [axp288_fuel_gauge] [ 4846.673577] ? __schedule+0x2e3/0x840 [ 4846.673590] fuel_gauge_status_monitor+0x16/0x40 [axp288_fuel_gauge] [ 4846.673603] process_one_work+0x1e0/0x420 [ 4846.673616] worker_thread+0x48/0x3f0 [ 4846.673629] kthread+0x108/0x140 [ 4846.673640] ? process_one_work+0x420/0x420 [ 4846.673650] ? kthread_create_on_node+0x70/0x70 [ 4846.673662] ret_from_fork+0x2c/0x40 [ 4846.673673] Code: 05 51 79 a1 00 01 e8 84 3c ae ff 0f ff eb a5 80 3d 40 79 a1 00 00 75 a6 48 c7 c7 98 fe e9 81 c6 05 30 79 a1 00 01 e8 64 3c ae ff <0f> ff eb 8f 66 90 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 [ 4846.673896] ---[ end trace 4f0b6934a8fd8068 ]--- Regards, FKr ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Call trace on 4.12.0-rc1
On Tue, May 16, 2017 at 10:43:39PM +0200, Hans de Goede wrote: > Hi, > > On 05/16/2017 09:55 PM, FKr wrote: > > Hi, > > I'm using 4.12.0-rc1 from https://github.com/jwrdegoede/linux-sunxi and got > > the following weird trace yesterday. Previously I've been getting output > > similar to https://www.spinics.net/lists/intel-gfx/msg127638.html, some > > boots > > on 4.12.0-rc1 I don't get any trace at all. > > This is really weird, we are getting the error while we are trying to > acquire the wakelock ... ? Or do we need some other lock before we can > take the wakelock ? You would also need the runtime pm reference. IIRC we unregister the notifier in runtime suspend, so I think intel_runtime_pm_get_noresume() should be OK in this case. Imre? > > Any input from one of the Intel developers would be appreciated. > > Regards, > > Hans > > > > > > [ 2383.844192] perf: interrupt took too long (2522 > 2500), lowering > > kernel.perf_event_max_sample_rate to 79200 > > [ 2634.863978] [drm:intel_pipe_update_end] *ERROR* Atomic update failure on > > pipe A (start=157909 end=157910) time 322 us, min 1073, max 1079, scanline > > start 1063, end 1084 > > [ 2647.881794] perf: interrupt took too long (3193 > 3152), lowering > > kernel.perf_event_max_sample_rate to 62400 > > [ 3297.857921] perf: interrupt took too long (4020 > 3991), lowering > > kernel.perf_event_max_sample_rate to 49500 > > [ 4670.977136] mmc0: Tuning timeout, falling back to fixed sampling clock > > [ 4671.436604] mmc0: Tuning timeout, falling back to fixed sampling clock > > [ 4680.756302] mmc0: Tuning timeout, falling back to fixed sampling clock > > [ 4707.846872] perf: interrupt took too long (5046 > 5025), lowering > > kernel.perf_event_max_sample_rate to 39600 > > [ 4846.672969] RPM wakelock ref not held during HW access > > [ 4846.673050] [ cut here ] > > [ 4846.673084] WARNING: CPU: 0 PID: 5227 at > > drivers/gpu/drm/i915/intel_drv.h: > > 1780 intel_uncore_forcewake_get+0xa0/0xb0 > > [ 4846.673088] Modules linked in: snd_soc_sst_cht_bsw_nau8824 btusb btintel > > bluetooth axp288_fuel_gauge ecdh_generic axp288_charger extcon_axp288 > > axp288_adc snd_hdmi_lpe_audio snd_intel_sst_acpi extcon_intel_int3496 > > snd_intel_sst_core extcon_core snd_soc_nau8824 > > snd_soc_sst_atom_hifi2_platform > > snd_soc_core snd_compress snd_soc_sst_match snd_pcm snd_timer kxcjk_1013 > > industrialio_triggered_buffer intel_cht_int33fe snd soundcore intel_int0002 > > [ 4846.673201] CPU: 0 PID: 5227 Comm: kworker/0:1 Not tainted 4.12.0-rc1+ #3 > > [ 4846.673206] Hardware name: MEDION E2228T MD60250/NT16H, BIOS 5.11 > > 02/27/2017 > > [ 4846.673224] Workqueue: events fuel_gauge_status_monitor > > [axp288_fuel_gauge] > > [ 4846.673235] task: 8800a85be800 task.stack: c9000261 > > [ 4846.673248] RIP: 0010:intel_uncore_forcewake_get+0xa0/0xb0 > > [ 4846.673255] RSP: 0018:c90002613aa0 EFLAGS: 00010286 > > [ 4846.673265] RAX: 002a RBX: 880136cc8000 RCX: > > 82063e88 > > [ 4846.673272] RDX: RSI: 0082 RDI: > > 0247 > > [ 4846.673278] RBP: c90002613ac0 R08: 002a R09: > > 02ac > > [ 4846.673284] R10: 0001 R11: R12: > > 0007 > > [ 4846.673289] R13: 0001 R14: R15: > > > > [ 4846.673298] FS: () GS:88013fc0() knlGS: > > > > [ 4846.673305] CS: 0010 DS: ES: CR0: 80050033 > > [ 4846.673311] CR2: 0758c709c000 CR3: 02009000 CR4: > > 001006f0 > > [ 4846.673317] Call Trace: > > [ 4846.673340] i915_pmic_bus_access_notifier+0x37/0x40 > > [ 4846.673354] notifier_call_chain+0x4a/0x70 > > [ 4846.673368] __blocking_notifier_call_chain+0x47/0x60 > > [ 4846.673380] blocking_notifier_call_chain+0x16/0x20 > > [ 4846.673393] iosf_mbi_call_pmic_bus_access_notifier_chain+0x1b/0x20 > > [ 4846.673406] baytrail_i2c_acquire+0x64/0x220 > > [ 4846.673420] i2c_dw_acquire_lock+0x21/0x50 > > [ 4846.673431] i2c_dw_xfer+0xa3/0x4a0 > > [ 4846.673444] __i2c_transfer+0x115/0x430 > > [ 4846.673456] i2c_transfer+0x5c/0xc0 > > [ 4846.673469] regmap_i2c_read+0x6d/0xa0 > > [ 4846.673482] _regmap_raw_read+0xda/0x210 > > [ 4846.673491] ? _regmap_raw_read+0xda/0x210 > > [ 4846.673503] ? __update_load_avg_se.isra.5+0x15b/0x180 > > [ 4846.673514] _regmap_bus_read+0x2a/0x60 > > [ 4846.673524] _regmap_read+0x6c/0x130 > > [ 4846.673535] regmap_read+0x3f/0x60 > > [ 4846.673549] fuel_gauge_reg_readb.isra.5+0x40/0x90 [axp288_fuel_gauge] > > [ 4846.673564] fuel_gauge_get_status+0x2d/0x100 [axp288_fuel_gauge] > > [ 4846.673577] ? __schedule+0x2e3/0x840 > > [ 4846.673590] fuel_gauge_status_monitor+0x16/0x40 [axp288_fuel_gauge] > > [ 4846.673603] process_one_work+0x1e0/0x420 > > [ 4846.673616] worker_thread+0x48/0x3f0 > > [ 4846.673629] kthread+0x108/0x140 > > [ 4846.673640] ? process_one_work+0
Re: [Intel-gfx] [PATCH] drm/i915: Workaround VLV/CHV DSI scanline counter hardware fail
The patch does what it says.
Tested-by: Mika Kahola
Reviewed-by: Mika Kahola
On Thu, 2016-12-15 at 19:47 +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The scanline counter is bonkers on VLV/CHV DSI. The scanline counter
> increment is not lined up with the start of vblank like it is on
> every other platform and output type. This causes problems for
> both the vblank timestamping and atomic update vblank evasion.
>
> On my FFRD8 machine at least, the scanline counter increment
> happens about 1/3 of a scanline ahead of the start of vblank (which
> is where all register latching happens still). That means we can't
> trust the scanline counter to tell us whether we're in vblank or not
> while we're on that particular line. In order to keep vblank
> timestamping in working condition when called from the vblank irq,
> we'll leave scanline_offset at one, which means that the entire
> line containing the start of vblank is considered to be inside
> the vblank.
>
> For the vblank evasion we'll need to consider that entire line
> to be bad, since we can't tell whether the registers already
> got latched or not. And we can't actually use the start of vblank
> interrupt to get us past that line as the interrupt would fire
> too soon, and then we'd up waiting for the next start of vblank
> instead. One way around that would using the frame start
> interrupt instead since that wouldn't fire until the next
> scanline, but that would require some bigger changes in the
> interrupt code. So for simplicity we'll just poll until we get
> past the bad line.
>
> v2: Adjust the comments a bit
>
> Cc: sta...@vger.kernel.org
> Cc: Jonas Aaberg
> Tested-by: Jonas Aaberg
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99086
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 9 +
> drivers/gpu/drm/i915/intel_sprite.c | 21 +
> 2 files changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 9cc5dbfc314b..159b2eb9766b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13852,6 +13852,15 @@ static void update_scanline_offset(struct
> intel_crtc *crtc)
> * type. For DP ports it behaves like most other platforms,
> but on HDMI
> * there's an extra 1 line difference. So we need to add two
> instead of
> * one to the value.
> + *
> + * On VLV/CHV DSI the scanline counter would appear to
> increment
> + * approx. 1/3 of a scanline before start of vblank.
> Unfortunately
> + * that means we can't tell whether we're in vblank or not
> while
> + * we're on that particular line. We must still set
> scanline_offset
> + * to 1 so that the vblank timestamps come out correct when
> we query
> + * the scanline counter from within the vblank interrupt
> handler.
> + * However if queried just before the start of vblank we'll
> get an
> + * answer that's slightly in the future.
> */
> if (IS_GEN2(dev_priv)) {
> const struct drm_display_mode *adjusted_mode =
> &crtc->config->base.adjusted_mode;
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 7031bc733d97..fb0e0d8e893a 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -81,10 +81,13 @@ int intel_usecs_to_scanlines(const struct
> drm_display_mode *adjusted_mode,
> */
> void intel_pipe_update_start(struct intel_crtc *crtc)
> {
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> const struct drm_display_mode *adjusted_mode = &crtc-
> >config->base.adjusted_mode;
> long timeout = msecs_to_jiffies_timeout(1);
> int scanline, min, max, vblank_start;
> wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc-
> >base);
> + bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) ||
> IS_CHERRYVIEW(dev_priv)) &&
> + intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI);
> DEFINE_WAIT(wait);
>
> vblank_start = adjusted_mode->crtc_vblank_start;
> @@ -136,6 +139,24 @@ void intel_pipe_update_start(struct intel_crtc
> *crtc)
>
> drm_crtc_vblank_put(&crtc->base);
>
> + /*
> + * On VLV/CHV DSI the scanline counter would appear to
> + * increment approx. 1/3 of a scanline before start of
> vblank.
> + * The registers still get latched at start of vblank
> however.
> + * This means we must not write any registers on the first
> + * line of vblank (since not the whole line is actually in
> + * vblank). And unfortunately we can't use the interrupt to
> + * wait here since it will fire too soon. We could use the
> + * frame start interrupt instead since it will fire after
> the
> + * critical scanline, but that would require more changes
> + * in the interrupt code. So for now we'll
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable decoupled mmio for GEN9LP (rev2)
== Series Details == Series: drm/i915: Disable decoupled mmio for GEN9LP (rev2) URL : https://patchwork.freedesktop.org/series/24470/ State : success == Summary == Series 24470v2 drm/i915: Disable decoupled mmio for GEN9LP https://patchwork.freedesktop.org/api/1.0/series/24470/revisions/2/mbox/ fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:446s fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time:582s fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:512s fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:496s fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:485s fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:414s fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:411s fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:421s fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:501s fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:468s fi-kbl-7500u total:278 pass:255 dwarn:5 dfail:0 fail:0 skip:18 time:462s fi-kbl-7560u total:278 pass:263 dwarn:5 dfail:0 fail:0 skip:10 time:572s fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:455s fi-skl-6700hqtotal:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time:582s fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:466s fi-skl-6770hqtotal:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:500s fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:530s fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time:411s 713f8ec675d5a793326b94d9a0cc484608eff75e drm-tip: 2017y-05m-16d-15h-22m-08s UTC integration manifest a0485f8 drm/i915: Disable decoupled mmio for GEN9LP == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4718/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 1/3] drm: Plumb modifiers through plane init
On Tue, May 16, 2017 at 02:31:24PM -0700, Ben Widawsky wrote:
> This is the plumbing for supporting fb modifiers on planes. Modifiers
> have already been introduced to some extent, but this series will extend
> this to allow querying modifiers per plane. Based on this, the client to
> enable optimal modifications for framebuffers.
>
> This patch simply allows the DRM drivers to initialize their list of
> supported modifiers upon initializing the plane.
>
> v2: A minor addition from Daniel
>
> v3: Updated commit message
> s/INVALID/DRM_FORMAT_MOD_INVALID (Liviu)
> Remove some excess newlines (Liviu)
> Update comment for > 64 modifiers (Liviu)
>
> Cc: Liviu Dudau
> Reviewed-by: Daniel Stone (v2)
> Signed-off-by: Ben Widawsky
Minor nits, see below, but otherwise:
Reviewed-by: Liviu Dudau
Thanks,
Liviu
> ---
> drivers/gpu/drm/arc/arcpgu_crtc.c | 1 +
> drivers/gpu/drm/arm/hdlcd_crtc.c| 1 +
> drivers/gpu/drm/arm/malidp_planes.c | 2 +-
> drivers/gpu/drm/armada/armada_crtc.c| 1 +
> drivers/gpu/drm/armada/armada_overlay.c | 1 +
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 4 ++-
> drivers/gpu/drm/drm_modeset_helper.c| 1 +
> drivers/gpu/drm/drm_plane.c | 35
> -
> drivers/gpu/drm/drm_simple_kms_helper.c | 3 +++
> drivers/gpu/drm/exynos/exynos_drm_plane.c | 2 +-
> drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c | 2 +-
> drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | 1 +
> drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c| 5 +++-
> drivers/gpu/drm/i915/intel_sprite.c | 4 +--
> drivers/gpu/drm/imx/ipuv3-plane.c | 4 +--
> drivers/gpu/drm/mediatek/mtk_drm_plane.c| 2 +-
> drivers/gpu/drm/meson/meson_plane.c | 1 +
> drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c | 2 +-
> drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 4 +--
> drivers/gpu/drm/mxsfb/mxsfb_drv.c | 2 +-
> drivers/gpu/drm/nouveau/nv50_display.c | 5 ++--
> drivers/gpu/drm/omapdrm/omap_plane.c| 3 ++-
> drivers/gpu/drm/qxl/qxl_display.c | 2 +-
> drivers/gpu/drm/rcar-du/rcar_du_plane.c | 4 +--
> drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 4 +--
> drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 4 +--
> drivers/gpu/drm/sti/sti_cursor.c| 2 +-
> drivers/gpu/drm/sti/sti_gdp.c | 2 +-
> drivers/gpu/drm/sti/sti_hqvdp.c | 2 +-
> drivers/gpu/drm/sun4i/sun4i_layer.c | 2 +-
> drivers/gpu/drm/tegra/dc.c | 12 -
> drivers/gpu/drm/vc4/vc4_plane.c | 2 +-
> drivers/gpu/drm/virtio/virtgpu_plane.c | 2 +-
> drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c | 4 +--
> drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c| 4 +--
> drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c| 4 +--
> drivers/gpu/drm/zte/zx_plane.c | 2 +-
> include/drm/drm_plane.h | 20 +-
> include/drm/drm_simple_kms_helper.h | 1 +
> include/uapi/drm/drm_fourcc.h | 11
> 41 files changed, 126 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/arc/arcpgu_crtc.c
> b/drivers/gpu/drm/arc/arcpgu_crtc.c
> index ad9a95916f1f..cd8a24c7c67d 100644
> --- a/drivers/gpu/drm/arc/arcpgu_crtc.c
> +++ b/drivers/gpu/drm/arc/arcpgu_crtc.c
> @@ -218,6 +218,7 @@ static struct drm_plane *arc_pgu_plane_init(struct
> drm_device *drm)
>
> ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs,
> formats, ARRAY_SIZE(formats),
> +NULL,
> DRM_PLANE_TYPE_PRIMARY, NULL);
> if (ret)
> return ERR_PTR(ret);
> diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c
> b/drivers/gpu/drm/arm/hdlcd_crtc.c
> index 798a3cc480a2..0caa03ae8708 100644
> --- a/drivers/gpu/drm/arm/hdlcd_crtc.c
> +++ b/drivers/gpu/drm/arm/hdlcd_crtc.c
> @@ -303,6 +303,7 @@ static struct drm_plane *hdlcd_plane_init(struct
> drm_device *drm)
>
> ret = drm_universal_plane_init(drm, plane, 0xff, &hdlcd_plane_funcs,
> formats, ARRAY_SIZE(formats),
> +NULL,
> DRM_PLANE_TYPE_PRIMARY, NULL);
> if (ret) {
> devm_kfree(drm->dev, plane);
> diff --git a/drivers/gpu/drm/arm/malidp_planes.c
> b/drivers/gpu/drm/arm/malidp_planes.c
> index 814fda23cead..b156610c68a5 100644
> --- a/drivers/gpu/drm/arm/malidp_planes.c
> +++ b/drivers/gpu/drm/arm/malidp_planes.c
> @@ -400,7 +400,7 @@ int malidp_de_planes_init(struct drm_device *drm)
> DRM_PLANE_TYPE_OVERLAY;
> re
Re: [Intel-gfx] [PATCH] drm/i915: Disable decoupled mmio for GEN9LP
On 17/05/2017 02:07, kai.c...@intel.com wrote:
From: Kai Chen
The decoupled mmio feature doesn't work as intended by HW team. Enabling
it with forcewake will only make debugging efforts more difficult, so
let's just simply remove it.
v2:
- Remove dead code related to GEN9LP decoupled mmio.
- Change backgrounds: In theory, decoupled mmio should require less cycles
for single read/write operation by avoiding frequent software forcewake.
However, it turns out this design not to be true on HW practice and not to
provide any decoupling benefit. It also introduces problems which cause
failures in intel-gpu-tools (gem), and also cause driver code and debugging
more complex.
- This change therefore reverts:
commit 85ee17ebeedd1af0dccd98f82ab4e644e29d84c0
Author: Praveen Paneri
Date: Tue, 15 Nov 2016 22:49:20 +0530
drm/i915/bxt: Broxton decoupled MMIO
coomit a3f79ca63b9bcf5a527b886953092bfd65e78940
Author: Ander Conselvan de Oliveira
Date: Thu, 24 Nov 2016 15:23:27 +0200
drm/i915: Don't sanitize has_decoupled_mmio if platform is not broxton
Revert looks incomplete since it is leaving behind the field in the
device info and HAS_DECOUPLED_MMIO macro.
But revert in principle is fine by me.
Regards,
Tvrtko
Signed-off-by: Kai Chen
---
drivers/gpu/drm/i915/i915_pci.c | 1 -
drivers/gpu/drm/i915/i915_reg.h | 7 --
drivers/gpu/drm/i915/intel_uncore.c | 126
3 files changed, 134 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f80db2c..cf43dc1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -385,7 +385,6 @@ static const struct intel_device_info
intel_skylake_gt3_info = {
.has_gmbus_irq = 1, \
.has_logical_ring_contexts = 1, \
.has_guc = 1, \
- .has_decoupled_mmio = 1, \
.has_aliasing_ppgtt = 1, \
.has_full_ppgtt = 1, \
.has_full_48bit_ppgtt = 1, \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ee144ec..78872f9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7792,13 +7792,6 @@ enum {
#define SKL_FUSE_PG1_DIST_STATUS (1<<26)
#define SKL_FUSE_PG2_DIST_STATUS (1<<25)
-/* Decoupled MMIO register pair for kernel driver */
-#define GEN9_DECOUPLED_REG0_DW0_MMIO(0xF00)
-#define GEN9_DECOUPLED_REG0_DW1_MMIO(0xF04)
-#define GEN9_DECOUPLED_DW1_GO (1<<31)
-#define GEN9_DECOUPLED_PD_SHIFT28
-#define GEN9_DECOUPLED_OP_SHIFT24
-
/* Per-pipe DDI Function Control */
#define _TRANS_DDI_FUNC_CTL_A 0x60400
#define _TRANS_DDI_FUNC_CTL_B 0x61400
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index a9a6933..3901800 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -400,8 +400,6 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
bool restore_forcewake)
{
- struct intel_device_info *info = mkwrite_device_info(dev_priv);
-
/* clear out unclaimed reg detection bit */
if (check_for_unclaimed_mmio(dev_priv))
DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
@@ -414,9 +412,6 @@ static void __intel_uncore_early_sanitize(struct
drm_i915_private *dev_priv,
GT_FIFO_CTL_RC6_POLICY_STALL);
}
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST))
- info->has_decoupled_mmio = false;
-
intel_uncore_forcewake_reset(dev_priv, restore_forcewake);
}
@@ -801,78 +796,6 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
__unclaimed_reg_debug(dev_priv, reg, read, before);
}
-enum decoupled_power_domain {
- GEN9_DECOUPLED_PD_BLITTER = 0,
- GEN9_DECOUPLED_PD_RENDER,
- GEN9_DECOUPLED_PD_MEDIA,
- GEN9_DECOUPLED_PD_ALL
-};
-
-enum decoupled_ops {
- GEN9_DECOUPLED_OP_WRITE = 0,
- GEN9_DECOUPLED_OP_READ
-};
-
-static const enum decoupled_power_domain fw2dpd_domain[] = {
- GEN9_DECOUPLED_PD_RENDER,
- GEN9_DECOUPLED_PD_BLITTER,
- GEN9_DECOUPLED_PD_ALL,
- GEN9_DECOUPLED_PD_MEDIA,
- GEN9_DECOUPLED_PD_ALL,
- GEN9_DECOUPLED_PD_ALL,
- GEN9_DECOUPLED_PD_ALL
-};
-
-/*
- * Decoupled MMIO access for only 1 DWORD
- */
-static void __gen9_decoupled_mmio_access(struct drm_i915_private *dev_priv,
-u32 reg,
-enum forcewake_domains fw_domain,
-enum decoupled_ops operation)
-{
- enum decoupled_power_domain dp_domain;
- u32 ctrl_reg_data = 0;
-
- dp_d
[Intel-gfx] ✓ Fi.CI.BAT: success for Enhancement to intel_dp_aux_backlight driver (rev7)
== Series Details == Series: Enhancement to intel_dp_aux_backlight driver (rev7) URL : https://patchwork.freedesktop.org/series/21086/ State : success == Summary == Series 21086v7 Enhancement to intel_dp_aux_backlight driver https://patchwork.freedesktop.org/api/1.0/series/21086/revisions/7/mbox/ Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-legacy: pass -> FAIL (fi-snb-2600) fdo#100215 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:447s fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time:580s fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:516s fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:488s fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:490s fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:423s fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:415s fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:418s fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:488s fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:458s fi-kbl-7500u total:278 pass:255 dwarn:5 dfail:0 fail:0 skip:18 time:466s fi-kbl-7560u total:278 pass:263 dwarn:5 dfail:0 fail:0 skip:10 time:575s fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:459s fi-skl-6700hqtotal:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time:575s fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:478s fi-skl-6770hqtotal:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:510s fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:539s fi-snb-2600 total:278 pass:248 dwarn:0 dfail:0 fail:1 skip:29 time:410s 713f8ec675d5a793326b94d9a0cc484608eff75e drm-tip: 2017y-05m-16d-15h-22m-08s UTC integration manifest 6c06613 drm/i915: Set PWM divider to match desired frequency in vbt d1d9671 drm: Add definition for eDP backlight frequency 9f1b542 drm/i915: Add option to support dynamic backlight via DPCD 427d4aa drm/i915: Allow choosing how to adjust brightness if both supported bac5d76 drm/i915: Drop AUX backlight enable check for backlight control == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4719/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/guc: Remove action status and statistics from debugfs
On Mon, May 15, 2017 at 05:06:09PM +, Michal Wajdeczko wrote: > Usefulness of these stats was over-advertised. > > v2: remove duplicated engine stats (Chris) > > Suggested-by: Chris Wilson > Signed-off-by: Michal Wajdeczko > Cc: Chris Wilson > Cc: Daniele Ceraolo Spurio I'm not hearing any shouts of outrage, so I presume nobody cares for them? > diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c > b/drivers/gpu/drm/i915/i915_guc_submission.c > index 7e85b5a..edda4da 100644 > --- a/drivers/gpu/drm/i915/i915_guc_submission.c > +++ b/drivers/gpu/drm/i915/i915_guc_submission.c > @@ -618,9 +618,6 @@ static void __i915_guc_submit(struct drm_i915_gem_request > *rq) > if (b_ret) > client->b_fail += 1; Next on the agenda will be these... -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: capture GuC logs if FW fails to load (rev5)
== Series Details == Series: drm/i915/guc: capture GuC logs if FW fails to load (rev5) URL : https://patchwork.freedesktop.org/series/23982/ State : success == Summary == Series 23982v5 drm/i915/guc: capture GuC logs if FW fails to load https://patchwork.freedesktop.org/api/1.0/series/23982/revisions/5/mbox/ fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:448s fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time:583s fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:523s fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:496s fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:482s fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:417s fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:415s fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:427s fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:498s fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:456s fi-kbl-7500u total:278 pass:255 dwarn:5 dfail:0 fail:0 skip:18 time:463s fi-kbl-7560u total:278 pass:263 dwarn:5 dfail:0 fail:0 skip:10 time:631s fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:460s fi-skl-6700hqtotal:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time:570s fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:468s fi-skl-6770hqtotal:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:499s fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:536s fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time:401s 713f8ec675d5a793326b94d9a0cc484608eff75e drm-tip: 2017y-05m-16d-15h-22m-08s UTC integration manifest 9e205b0 drm/i915/guc: capture GuC logs if FW fails to load == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4720/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/guc: Remove action status and statistics from debugfs
On 15/05/2017 18:06, Michal Wajdeczko wrote:
Usefulness of these stats was over-advertised.
v2: remove duplicated engine stats (Chris)
Suggested-by: Chris Wilson
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_debugfs.c| 19 ---
drivers/gpu/drm/i915/i915_guc_submission.c | 3 ---
drivers/gpu/drm/i915/intel_uc.c| 7 ---
drivers/gpu/drm/i915/intel_uc.h| 10 --
4 files changed, 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index bd9abef..fdb2fd0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2514,9 +2514,6 @@ static int i915_guc_info(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
const struct intel_guc *guc = &dev_priv->guc;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
- u64 total;
if (!check_guc_submission(m))
return 0;
@@ -2525,22 +2522,6 @@ static int i915_guc_info(struct seq_file *m, void *data)
seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap);
seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc->db_cacheline);
- seq_printf(m, "GuC total action count: %llu\n", guc->action_count);
- seq_printf(m, "GuC action failure count: %u\n", guc->action_fail);
- seq_printf(m, "GuC last action command: 0x%x\n", guc->action_cmd);
- seq_printf(m, "GuC last action status: 0x%x\n", guc->action_status);
- seq_printf(m, "GuC last action error code: %d\n", guc->action_err);
-
- total = 0;
- seq_printf(m, "\nGuC submissions:\n");
- for_each_engine(engine, dev_priv, id) {
- u64 submissions = guc->submissions[id];
- total += submissions;
- seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
- engine->name, submissions, guc->last_seqno[id]);
- }
- seq_printf(m, "\t%s: %llu\n", "Total", total);
-
seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
i915_guc_client_info(m, dev_priv, guc->execbuf_client);
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 7e85b5a..edda4da 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -618,9 +618,6 @@ static void __i915_guc_submit(struct drm_i915_gem_request
*rq)
if (b_ret)
client->b_fail += 1;
- guc->submissions[engine_id] += 1;
- guc->last_seqno[engine_id] = rq->global_seqno;
-
spin_unlock_irqrestore(&client->wq_lock, flags);
}
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 07c5658..d27b527 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -440,9 +440,6 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*action, u32 len)
mutex_lock(&guc->send_mutex);
intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
- dev_priv->guc.action_count += 1;
- dev_priv->guc.action_cmd = action[0];
-
for (i = 0; i < len; i++)
I915_WRITE(guc_send_reg(guc, i), action[i]);
@@ -471,11 +468,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32
*action, u32 len)
DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
" ret=%d status=0x%08X response=0x%08X\n",
action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
-
- dev_priv->guc.action_fail += 1;
- dev_priv->guc.action_err = ret;
}
- dev_priv->guc.action_status = status;
intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
mutex_unlock(&guc->send_mutex);
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 7618b71..b432747 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -195,16 +195,6 @@ struct intel_guc {
DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
uint32_t db_cacheline; /* Cyclic counter mod pagesize */
- /* Action status & statistics */
- uint64_t action_count; /* Total commands issued*/
- uint32_t action_cmd;/* Last command word*/
- uint32_t action_status; /* Last return status */
- uint32_t action_fail; /* Total number of failures */
- int32_t action_err; /* Last error code */
-
- uint64_t submissions[I915_NUM_ENGINES];
- uint32_t last_seqno[I915_NUM_ENGINES];
-
/* GuC's FW specific registers used in MMIO send */
struct {
u32 base;
Can't see that we need these.
Acked-by: Tvrtko Ursulin
Regards,
[Intel-gfx] [PATCH v13 00/14] Enable OA unit for Gen 8 and 9 in i915 perf
Hi, Here are the changes from v12 : * At Chris' recommendation, record sseu configuration per context & engine (patch 3) * In patch 8, request rpcs update on all engines (not just RCS) * Drop previous device GET_PARAM ioctls. Those were confusing from the userspace point of view, as the returned value depends on whether someone's opened a perf stream. Instead we introduce an ioctl on the perf stream itself (patch 5) Cheers, Chris Wilson (3): drm/i915: Record both min/max eu_per_subslice in sseu_dev_info drm/i915: Program RPCS for Broadwell drm/i915: Record the sseu configuration per-context & engine Lionel Landwerlin (6): drm/i915/perf: add property to select an engine sseu configuration drm/i915/perf: expose sseu configuration to userspace on perf fd drm/i915/perf: rework mux configurations queries drm/i915: add KBL GT2/GT3 check macros drm/i915/perf: add KBL support drm/i915/perf: add GLK support Robert Bragg (5): drm/i915/perf: Add 'render basic' Gen8+ OA unit configs drm/i915/perf: Add OA unit support for Gen 8+ drm/i915/perf: Add more OA configs for BDW, CHV, SKL + BXT drm/i915/perf: per-gen timebase for checking sample freq drm/i915/perf: remove perf.hook_lock drivers/gpu/drm/i915/Makefile | 11 +- drivers/gpu/drm/i915/i915_debugfs.c| 36 +- drivers/gpu/drm/i915/i915_drv.h| 127 +- drivers/gpu/drm/i915/i915_gem_context.c|6 + drivers/gpu/drm/i915/i915_gem_context.h| 21 + drivers/gpu/drm/i915/i915_gem_execbuffer.c | 31 +- drivers/gpu/drm/i915/i915_oa_bdw.c | 5374 drivers/gpu/drm/i915/i915_oa_bdw.h | 38 + drivers/gpu/drm/i915/i915_oa_bxt.c | 2688 ++ drivers/gpu/drm/i915/i915_oa_bxt.h | 38 + drivers/gpu/drm/i915/i915_oa_chv.c | 2871 +++ drivers/gpu/drm/i915/i915_oa_chv.h | 38 + drivers/gpu/drm/i915/i915_oa_glk.c | 2600 ++ drivers/gpu/drm/i915/i915_oa_glk.h | 38 + drivers/gpu/drm/i915/i915_oa_hsw.c | 259 +- drivers/gpu/drm/i915/i915_oa_kblgt2.c | 2989 drivers/gpu/drm/i915/i915_oa_kblgt2.h | 38 + drivers/gpu/drm/i915/i915_oa_kblgt3.c | 3038 drivers/gpu/drm/i915/i915_oa_kblgt3.h | 38 + drivers/gpu/drm/i915/i915_oa_sklgt2.c | 3477 ++ drivers/gpu/drm/i915/i915_oa_sklgt2.h | 38 + drivers/gpu/drm/i915/i915_oa_sklgt3.c | 3037 drivers/gpu/drm/i915/i915_oa_sklgt3.h | 38 + drivers/gpu/drm/i915/i915_oa_sklgt4.c | 3091 drivers/gpu/drm/i915/i915_oa_sklgt4.h | 38 + drivers/gpu/drm/i915/i915_perf.c | 1149 +- drivers/gpu/drm/i915/i915_reg.h| 22 + drivers/gpu/drm/i915/intel_device_info.c | 32 +- drivers/gpu/drm/i915/intel_lrc.c | 61 +- drivers/gpu/drm/i915/intel_lrc.h |6 + include/uapi/drm/i915_drm.h| 41 +- 31 files changed, 31039 insertions(+), 270 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_oa_bdw.c create mode 100644 drivers/gpu/drm/i915/i915_oa_bdw.h create mode 100644 drivers/gpu/drm/i915/i915_oa_bxt.c create mode 100644 drivers/gpu/drm/i915/i915_oa_bxt.h create mode 100644 drivers/gpu/drm/i915/i915_oa_chv.c create mode 100644 drivers/gpu/drm/i915/i915_oa_chv.h create mode 100644 drivers/gpu/drm/i915/i915_oa_glk.c create mode 100644 drivers/gpu/drm/i915/i915_oa_glk.h create mode 100644 drivers/gpu/drm/i915/i915_oa_kblgt2.c create mode 100644 drivers/gpu/drm/i915/i915_oa_kblgt2.h create mode 100644 drivers/gpu/drm/i915/i915_oa_kblgt3.c create mode 100644 drivers/gpu/drm/i915/i915_oa_kblgt3.h create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt2.c create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt2.h create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt3.c create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt3.h create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt4.c create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt4.h -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/14] drm/i915: Record the sseu configuration per-context & engine
From: Chris Wilson
We want to expose the ability to reconfigure the slices, subslice and
eu per context and per engine. To facilitate that, store the current
configuration on the context for each engine, which is initially set
to the device default upon creation.
v2: record sseu configuration per context & engine (Chris)
Signed-off-by: Chris Wilson
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 19 ---
drivers/gpu/drm/i915/i915_gem_context.c | 6 ++
drivers/gpu/drm/i915/i915_gem_context.h | 21 +
drivers/gpu/drm/i915/intel_lrc.c| 23 +--
4 files changed, 36 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f64038332bad..33bc0b04400b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -731,25 +731,6 @@ struct intel_csr {
func(overlay_needs_physical); \
func(supports_tv);
-struct sseu_dev_info {
- u8 slice_mask;
- u8 subslice_mask;
- u8 eu_total;
- u8 min_eu_per_subslice;
- u8 max_eu_per_subslice;
- u8 min_eu_in_pool;
- /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
- u8 subslice_7eu[3];
- u8 has_slice_pg:1;
- u8 has_subslice_pg:1;
- u8 has_eu_pg:1;
-};
-
-static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu)
-{
- return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
-}
-
/* Keep in gen based order, and chronological order within a gen */
enum intel_platform {
INTEL_PLATFORM_UNINITIALIZED = 0,
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 31a73c39239f..8dac00ee2650 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -184,6 +184,8 @@ __create_hw_context(struct drm_i915_private *dev_priv,
struct drm_i915_file_private *file_priv)
{
struct i915_gem_context *ctx;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
int ret;
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
@@ -228,6 +230,10 @@ __create_hw_context(struct drm_i915_private *dev_priv,
* is no remap info, it will be a NOP. */
ctx->remap_slice = ALL_L3_SLICES(dev_priv);
+ /* On all engines, use the whole device by default */
+ for_each_engine(engine, dev_priv, id)
+ ctx->engine[id].sseu = INTEL_INFO(dev_priv)->sseu;
+
i915_gem_context_set_bannable(ctx);
ctx->ring_size = 4 * PAGE_SIZE;
ctx->desc_template =
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h
b/drivers/gpu/drm/i915/i915_gem_context.h
index 4af2ab94558b..e8247e2f6011 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -39,6 +39,25 @@ struct i915_hw_ppgtt;
struct i915_vma;
struct intel_ring;
+struct sseu_dev_info {
+ u8 slice_mask;
+ u8 subslice_mask;
+ u8 eu_total;
+ u8 min_eu_per_subslice;
+ u8 max_eu_per_subslice;
+ u8 min_eu_in_pool;
+ /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
+ u8 subslice_7eu[3];
+ u8 has_slice_pg:1;
+ u8 has_subslice_pg:1;
+ u8 has_eu_pg:1;
+};
+
+static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu)
+{
+ return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
+}
+
#define DEFAULT_CONTEXT_HANDLE 0
/**
@@ -151,6 +170,8 @@ struct i915_gem_context {
u64 lrc_desc;
int pin_count;
bool initialised;
+ /** sseu: Control eu/slice partitioning */
+ struct sseu_dev_info sseu;
} engine[I915_NUM_ENGINES];
/** ring_size: size for allocating the per-engine ring buffer */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 7e257d5cd9a0..f4a05c52c98e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1729,8 +1729,7 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine)
return logical_ring_init(engine);
}
-static u32
-make_rpcs(struct drm_i915_private *dev_priv)
+static u32 make_rpcs(const struct sseu_dev_info *sseu)
{
u32 rpcs = 0;
@@ -1740,25 +1739,21 @@ make_rpcs(struct drm_i915_private *dev_priv)
* must make an explicit request through RPCS for full
* enablement.
*/
- if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
+ if (sseu->has_slice_pg) {
rpcs |= GEN8_RPCS_S_CNT_ENABLE;
- rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
- GEN8_RPCS_S_CNT_SHIFT;
+ rpcs |= hweight8(sseu->slice_mask) << GEN8_RPCS_S_CNT_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
- if (INTEL_INFO(dev_priv)->sseu.
[Intel-gfx] [PATCH 01/14] drm/i915: Record both min/max eu_per_subslice in sseu_dev_info
From: Chris Wilson
When we query the available eu on each subslice, we currently only
report the max. It would also be useful to report the minimum found as
well.
When we set RPCS (power gating over the EU), we can also specify both
the min and max number of eu to configure on each slice; currently we
just set it to a single value, but the flexibility may be beneficial in
future.
Signed-off-by: Chris Wilson
Signed-off-by: Lionel Landwerlin
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c | 36 +++-
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_device_info.c | 32 +---
drivers/gpu/drm/i915/intel_lrc.c | 4 ++--
4 files changed, 50 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 76abff186d01..0fea0aaa3bec 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4509,6 +4509,7 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
+ unsigned int min_eu_per_subslice, max_eu_per_subslice;
int ss_max = 2;
int ss;
u32 sig1[ss_max], sig2[ss_max];
@@ -4518,6 +4519,9 @@ static void cherryview_sseu_device_status(struct
drm_i915_private *dev_priv,
sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
+ min_eu_per_subslice = ~0u;
+ max_eu_per_subslice = 0;
+
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
@@ -4532,14 +4536,18 @@ static void cherryview_sseu_device_status(struct
drm_i915_private *dev_priv,
((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
sseu->eu_total += eu_cnt;
- sseu->eu_per_subslice = max_t(unsigned int,
- sseu->eu_per_subslice, eu_cnt);
+ min_eu_per_subslice = min(min_eu_per_subslice, eu_cnt);
+ max_eu_per_subslice = max(max_eu_per_subslice, eu_cnt);
}
+
+ sseu->min_eu_per_subslice = min_eu_per_subslice;
+ sseu->max_eu_per_subslice = max_eu_per_subslice;
}
static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
+ unsigned int min_eu_per_subslice, max_eu_per_subslice;
int s_max = 3, ss_max = 4;
int s, ss;
u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
@@ -4565,6 +4573,9 @@ static void gen9_sseu_device_status(struct
drm_i915_private *dev_priv,
GEN9_PGCTL_SSB_EU210_ACK |
GEN9_PGCTL_SSB_EU311_ACK;
+ min_eu_per_subslice = ~0u;
+ max_eu_per_subslice = 0;
+
for (s = 0; s < s_max; s++) {
if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
/* skip disabled slice */
@@ -4590,11 +4601,14 @@ static void gen9_sseu_device_status(struct
drm_i915_private *dev_priv,
eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
eu_mask[ss%2]);
sseu->eu_total += eu_cnt;
- sseu->eu_per_subslice = max_t(unsigned int,
- sseu->eu_per_subslice,
- eu_cnt);
+
+ min_eu_per_subslice = min(min_eu_per_subslice, eu_cnt);
+ max_eu_per_subslice = max(max_eu_per_subslice, eu_cnt);
}
}
+
+ sseu->min_eu_per_subslice = min_eu_per_subslice;
+ sseu->max_eu_per_subslice = max_eu_per_subslice;
}
static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
@@ -4607,9 +4621,11 @@ static void broadwell_sseu_device_status(struct
drm_i915_private *dev_priv,
if (sseu->slice_mask) {
sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
- sseu->eu_per_subslice =
- INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
- sseu->eu_total = sseu->eu_per_subslice *
+ sseu->min_eu_per_subslice =
+ INTEL_INFO(dev_priv)->sseu.min_eu_per_subslice;
+ sseu->max_eu_per_subslice =
+ INTEL_INFO(dev_priv)->sseu.max_eu_per_subslice;
+ sseu->eu_total = sseu->max_eu_per_subslice *
sseu_subslice_total(sseu);
/* subtract fused off EU(s) from enabled slice(s) */
@@ -4640,8 +4656,8 @@ static void i915_print_sseu_info(struct seq_file *m, bool
is_available_info,
hweight8(sseu->subslice_mask));
seq_printf(m, "
[Intel-gfx] [PATCH 02/14] drm/i915: Program RPCS for Broadwell
From: Chris Wilson Currently we only configure the power gating for Skylake and above, but the configuration should equally apply to Broadwell and Braswell. Even though, there is not as much variation as for later generations, we want to expose control over the configuration to userspace and may want to opt out of the "always-enabled" setting. Signed-off-by: Chris Wilson Signed-off-by: Lionel Landwerlin Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/intel_lrc.c | 7 --- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 4a6041eb0fed..7e257d5cd9a0 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1735,13 +1735,6 @@ make_rpcs(struct drm_i915_private *dev_priv) u32 rpcs = 0; /* -* No explicit RPCS request is needed to ensure full -* slice/subslice/EU enablement prior to Gen9. - */ - if (INTEL_GEN(dev_priv) < 9) - return 0; - - /* * Starting in Gen9, render power gating can leave * slice/subslice/EU in a partially enabled state. We * must make an explicit request through RPCS for full -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/14] drm/i915/perf: add property to select an engine sseu configuration
When monitoring a particular context, we also want to select what
engine we interested in monitoring as different engine can have
different sseu configurations. This is required because the reports
produced by the OA unit have to be interpreted using the
slice/subslice configuration.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h| 11 +++
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 31 --
drivers/gpu/drm/i915/i915_perf.c | 22 +
include/uapi/drm/i915_drm.h| 7 +++
4 files changed, 57 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 33bc0b04400b..10ffbfec3b2e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2332,6 +2332,12 @@ struct drm_i915_private {
u32 specific_ctx_id;
+ /**
+* Configuration at which the GPU is locked for the
+* duration of the monitoring.
+*/
+ struct sseu_dev_info sseu;
+
struct hrtimer poll_check_timer;
wait_queue_head_t poll_wq;
bool pollin;
@@ -3162,6 +3168,11 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
+struct intel_engine_cs *
+i915_gem_engine_from_user_flags(struct drm_i915_private *dev_priv,
+ struct drm_file *file,
+ u64 user_flags);
+
void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
static inline int __sg_page_count(const struct scatterlist *sg)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index af1965774e7b..bc14014eec83 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1502,37 +1502,40 @@ static const enum intel_engine_id
user_ring_map[I915_USER_RINGS + 1] = {
[I915_EXEC_VEBOX] = VECS
};
-static struct intel_engine_cs *
-eb_select_engine(struct drm_i915_private *dev_priv,
-struct drm_file *file,
-struct drm_i915_gem_execbuffer2 *args)
+struct intel_engine_cs *
+i915_gem_engine_from_user_flags(struct drm_i915_private *dev_priv,
+ struct drm_file *file,
+ u64 user_flags)
{
- unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
+ unsigned int user_ring_id = user_flags & I915_EXEC_RING_MASK;
struct intel_engine_cs *engine;
if (user_ring_id > I915_USER_RINGS) {
- DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
+ DRM_DEBUG("user flags with unknown ring: %u\n", user_ring_id);
return NULL;
}
if ((user_ring_id != I915_EXEC_BSD) &&
- ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
- DRM_DEBUG("execbuf with non bsd ring but with invalid "
- "bsd dispatch flags: %d\n", (int)(args->flags));
+ ((user_flags & I915_EXEC_BSD_MASK) != 0)) {
+ DRM_DEBUG("user flags with non bsd ring but with invalid "
+ "bsd dispatch flags: %d\n", (int)(user_flags));
return NULL;
}
if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) {
- unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
+ unsigned int bsd_idx = user_flags & I915_EXEC_BSD_MASK;
if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
- bsd_idx = gen8_dispatch_bsd_engine(dev_priv, file);
+ if (file)
+ bsd_idx = gen8_dispatch_bsd_engine(dev_priv,
file);
+ else
+ bsd_idx = 0;
} else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
bsd_idx <= I915_EXEC_BSD_RING2) {
bsd_idx >>= I915_EXEC_BSD_SHIFT;
bsd_idx--;
} else {
- DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
+ DRM_DEBUG("user flags with unknown bsd ring: %u\n",
bsd_idx);
return NULL;
}
@@ -1543,7 +1546,7 @@ eb_select_engine(struct drm_i915_private *dev_priv,
}
if (!engine) {
- DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id);
+ DRM_DEBUG("user flags with invalid ring: %u\n", user_ring_id);
return NULL;
}
@@ -1590,7 +1593,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
if (args->flags & I915_EXEC
[Intel-gfx] [PATCH 10/14] drm/i915/perf: per-gen timebase for checking sample freq
From: Robert Bragg
An oa_exponent_to_ns() utility and per-gen timebase constants where
recently removed when updating the tail pointer race condition WA, and
this restores those so we can update the _PROP_OA_EXPONENT validation
done in read_properties_unlocked() to not assume we have a 12.5MHz
timebase as we did for Haswell.
Accordingly the oa_sample_rate_hard_limit value that's referenced by
proc_dointvec_minmax defining the absolute limit for the OA sampling
frequency is now initialized to (timestamp_frequency / 2) instead of the
6.25MHz constant for Haswell.
v2:
Specify frequency of 19.2MHz for BXT (Ville)
Initialize oa_sample_rate_hard_limit per-gen too (Lionel)
Signed-off-by: Robert Bragg
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_perf.c | 39 ---
2 files changed, 29 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 48e1825bd497..654607770542 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2351,6 +2351,7 @@ struct drm_i915_private {
bool periodic;
int period_exponent;
+ int timestamp_frequency;
int metrics_set;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 9a00d4ab2a1f..cf5f4a2cec52 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -288,10 +288,12 @@ static u32 i915_perf_stream_paranoid = true;
/* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate
*
- * 160ns is the smallest sampling period we can theoretically program the OA
- * unit with on Haswell, corresponding to 6.25MHz.
+ * The highest sampling frequency we can theoretically program the OA unit
+ * with is always half the timestamp frequency: E.g. 6.25Mhz for Haswell.
+ *
+ * Initialized just before we register the sysctl parameter.
*/
-static int oa_sample_rate_hard_limit = 625;
+static int oa_sample_rate_hard_limit;
/* Theoretically we can program the OA unit to sample every 160ns but don't
* allow that by default unless root...
@@ -2659,6 +2661,12 @@ i915_perf_open_ioctl_locked(struct drm_i915_private
*dev_priv,
return ret;
}
+static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent)
+{
+ return div_u64(10ULL * (2ULL << exponent),
+ dev_priv->perf.oa.timestamp_frequency);
+}
+
/**
* read_properties_unlocked - validate + copy userspace stream open properties
* @dev_priv: i915 device instance
@@ -2755,16 +2763,13 @@ static int read_properties_unlocked(struct
drm_i915_private *dev_priv,
}
/* Theoretically we can program the OA unit to sample
-* every 160ns but don't allow that by default unless
-* root.
-*
-* On Haswell the period is derived from the exponent
-* as:
-*
-* period = 80ns * 2^(exponent + 1)
+* e.g. every 160ns for HSW, 167ns for BDW/SKL or 104ns
+* for BXT. We don't allow such high sampling
+* frequencies by default unless root.
*/
+
BUILD_BUG_ON(sizeof(oa_period) != 8);
- oa_period = 80ull * (2ull << value);
+ oa_period = oa_exponent_to_ns(dev_priv, value);
/* This check is primarily to ensure that oa_period <=
* UINT32_MAX (before passing to do_div which only
@@ -3029,6 +3034,8 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.ops.oa_hw_tail_read =
gen7_oa_hw_tail_read;
+ dev_priv->perf.oa.timestamp_frequency = 1250;
+
dev_priv->perf.oa.oa_formats = hsw_oa_formats;
dev_priv->perf.oa.n_builtin_sets =
@@ -3044,6 +3051,9 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
if (IS_GEN8(dev_priv)) {
dev_priv->perf.oa.ctx_oactxctrl_offset = 0x120;
dev_priv->perf.oa.ctx_flexeu0_offset = 0x2ce;
+
+ dev_priv->perf.oa.timestamp_frequency = 1250;
+
dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<25);
if (IS_BROADWELL(dev_priv)) {
@@ -3060,6 +3070,9 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
} else if (IS_GEN9(dev_priv)) {
dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;
+
+ dev_priv->perf.oa.timestamp_
[Intel-gfx] [PATCH 05/14] drm/i915/perf: expose sseu configuration to userspace on perf fd
Enables userspace to determine the number of slices & subslices
enabled and also know what specific slices & subslices are enabled.
This information is required, for example, to be able to analyse some
OA counter reports where the counter configuration depends on the HW
slice configuration.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 12
drivers/gpu/drm/i915/i915_perf.c | 14 ++
include/uapi/drm/i915_drm.h | 15 +++
3 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 10ffbfec3b2e..18e12e61949b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2966,6 +2966,18 @@ extern long i915_compat_ioctl(struct file *filp,
unsigned int cmd,
#endif
extern const struct dev_pm_ops i915_pm_ops;
+static inline u64 i915_pack_sseu_to_user(struct sseu_dev_info *sseu)
+{
+ union drm_i915_gem_param_sseu user;
+
+ user.packed.slice_mask = sseu->slice_mask;
+ user.packed.subslice_mask = sseu->subslice_mask;
+ user.packed.min_eu_per_subslice = sseu->min_eu_per_subslice;
+ user.packed.max_eu_per_subslice = sseu->max_eu_per_subslice;
+
+ return user.value;
+}
+
extern int i915_driver_load(struct pci_dev *pdev,
const struct pci_device_id *ent);
extern void i915_driver_unload(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 5f4eccaa06d6..d20cceef93d0 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1618,6 +1618,18 @@ static void i915_perf_disable_locked(struct
i915_perf_stream *stream)
stream->ops->disable(stream);
}
+static int i915_perf_get_sseu_locked(struct i915_perf_stream *stream,
+unsigned long arg)
+{
+ struct drm_i915_private *dev_priv = stream->dev_priv;
+ u64 sseu = i915_pack_sseu_to_user(&dev_priv->perf.oa.sseu);
+
+ if (copy_to_user((void __user *)arg, &sseu, sizeof(sseu)) != 0)
+ return -EFAULT;
+
+ return 0;
+}
+
/**
* i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs
* @stream: An i915 perf stream
@@ -1641,6 +1653,8 @@ static long i915_perf_ioctl_locked(struct
i915_perf_stream *stream,
case I915_PERF_IOCTL_DISABLE:
i915_perf_disable_locked(stream);
return 0;
+ case I915_PERF_IOCTL_GET_SSEU:
+ return i915_perf_get_sseu_locked(stream, arg);
}
return -EINVAL;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index ba722fb343a4..8871c526205b 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -350,6 +350,16 @@ typedef struct drm_i915_irq_wait {
int irq_seq;
} drm_i915_irq_wait_t;
+union drm_i915_gem_param_sseu {
+ struct {
+ u8 slice_mask;
+ u8 subslice_mask;
+ u8 min_eu_per_subslice;
+ u8 max_eu_per_subslice;
+ } packed;
+ __u64 value;
+};
+
/* Ioctl to query kernel params:
*/
#define I915_PARAM_IRQ_ACTIVE1
@@ -1399,6 +1409,11 @@ struct drm_i915_perf_open_param {
#define I915_PERF_IOCTL_DISABLE_IO('i', 0x1)
/**
+ * Query sseu configuration for a stream.
+ */
+#define I915_PERF_IOCTL_GET_SSEU _IOW('i', 0x2, union drm_i915_gem_param_sseu)
+
+/**
* Common to all i915 perf records
*/
struct drm_i915_perf_record_header {
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/14] drm/i915/perf: Add OA unit support for Gen 8+
From: Robert Bragg
Enables access to OA unit metrics for BDW, CHV, SKL and BXT which all
share (more-or-less) the same OA unit design.
Of particular note in comparison to Haswell: some OA unit HW config
state has become per-context state and as a consequence it is somewhat
more complicated to manage synchronous state changes from the cpu while
there's no guarantee of what context (if any) is currently actively
running on the gpu.
The periodic sampling frequency which can be particularly useful for
system-wide analysis (as opposed to command stream synchronised
MI_REPORT_PERF_COUNT commands) is perhaps the most surprising state to
have become per-context save and restored (while the OABUFFER
destination is still a shared, system-wide resource).
This support for gen8+ takes care to consider a number of timing
challenges involved in synchronously updating per-context state
primarily by programming all config state from the cpu and updating all
current and saved contexts synchronously while the OA unit is still
disabled.
The driver intentionally avoids depending on command streamer
programming to update OA state considering the lack of synchronization
between the automatic loading of OACTXCONTROL state (that includes the
periodic sampling state and enable state) on context restore and the
parsing of any general purpose BB the driver can control. I.e. this
implementation is careful to avoid the possibility of a context restore
temporarily enabling any out-of-date periodic sampling state. In
addition to the risk of transiently-out-of-date state being loaded
automatically; there are also internal HW latencies involved in the
loading of MUX configurations which would be difficult to account for
from the command streamer (and we only want to enable the unit when once
the MUX configuration is complete).
Since the Gen8+ OA unit design no longer supports clock gating the unit
off for a single given context (which effectively stopped any progress
of counters while any other context was running) and instead supports
tagging OA reports with a context ID for filtering on the CPU, it means
we can no longer hide the system-wide progress of counters from a
non-privileged application only interested in metrics for its own
context. Although we could theoretically try and subtract the progress
of other contexts before forwarding reports via read() we aren't in a
position to filter reports captured via MI_REPORT_PERF_COUNT commands.
As a result, for Gen8+, we always require the
dev.i915.perf_stream_paranoid to be unset for any access to OA metrics
if not root.
v5: Drain submitted requests when enabling metric set to ensure no
lite-restore erases the context image we just updated (Lionel)
v6: In addition to drain, switch to kernel context & update all
context in place (Chris)
v7: Add missing mutex_unlock() if switching to kernel context fails
(Matthew)
v8: Simplify OA period/flex-eu-counters programming by using the
batchbuffer instead of modifying ctx-image (Lionel)
v9: Back to updating the context image (due to erroneous testing,
batchbuffer programming the OA unit doesn't actually work)
(Lionel)
Pin context before updating context image (Chris)
Drop MMIO programming now that we switch to a kernel context with
right values in initial context image (Chris)
v10: Just pin_map the contexts we want to modify or let the
configuration happen on first use (Chris)
v11: Update kernel context OA config through the batchbuffer rather
than on the fly ctx-image update (Lionel)
v12: Rework OA context registers update again by swithing away from
user contexts and reconfiguring the kernel context through the
batchbuffer and updating all the other contexts' context image.
Also take care to lock slice/subslice configuration when OA is
on. (Lionel)
v13: Request rpcs updates on all engine when updating the OA config
(Lionel)
Signed-off-by: Robert Bragg
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld \o/
---
drivers/gpu/drm/i915/i915_drv.h | 72 ++-
drivers/gpu/drm/i915/i915_perf.c | 1024 +++---
drivers/gpu/drm/i915/i915_reg.h | 22 +
drivers/gpu/drm/i915/intel_lrc.c | 35 +-
drivers/gpu/drm/i915/intel_lrc.h |6 +
include/uapi/drm/i915_drm.h | 19 +-
6 files changed, 1081 insertions(+), 97 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5185752981b2..5275f1117850 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1949,9 +1949,17 @@ struct i915_oa_ops {
void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
/**
-* @enable_metric_set: Applies any MUX configuration to set up the
-* Boolean and Custom (B/C) counters that are part of the counter
-* reports being sampled. May apply system constraints such as
+* @select_metric_set: The auto generated code that checks
[Intel-gfx] [PATCH 06/14] drm/i915/perf: rework mux configurations queries
Gen8+ might have mux configurations per slices/subslices. Depending on
whether slices/subslices have been fused off, only part of the
configuration needs to be applied. This change reworks the mux
configurations query mechanism to allow more than one set of registers
to be programmed.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h| 5 +-
drivers/gpu/drm/i915/i915_oa_hsw.c | 211 -
drivers/gpu/drm/i915/i915_perf.c | 7 +-
3 files changed, 144 insertions(+), 79 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 18e12e61949b..56ed5a0651e2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2353,8 +2353,9 @@ struct drm_i915_private {
int metrics_set;
- const struct i915_oa_reg *mux_regs;
- int mux_regs_len;
+ const struct i915_oa_reg *mux_regs[1];
+ int mux_regs_lens[1];
+ int n_mux_regs;
const struct i915_oa_reg *b_counter_regs;
int b_counter_regs_len;
diff --git a/drivers/gpu/drm/i915/i915_oa_hsw.c
b/drivers/gpu/drm/i915/i915_oa_hsw.c
index 4ddf756add31..ccd6e5124992 100644
--- a/drivers/gpu/drm/i915/i915_oa_hsw.c
+++ b/drivers/gpu/drm/i915/i915_oa_hsw.c
@@ -109,12 +109,21 @@ static const struct i915_oa_reg mux_config_render_basic[]
= {
{ _MMIO(0x25428), 0x00042049 },
};
-static const struct i915_oa_reg *
+static int
get_render_basic_mux_config(struct drm_i915_private *dev_priv,
- int *len)
+ const struct i915_oa_reg **regs,
+ int *lens)
{
- *len = ARRAY_SIZE(mux_config_render_basic);
- return mux_config_render_basic;
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_render_basic;
+ lens[n] = ARRAY_SIZE(mux_config_render_basic);
+ n++;
+
+ return n;
}
static const struct i915_oa_reg b_counter_config_compute_basic[] = {
@@ -172,12 +181,21 @@ static const struct i915_oa_reg
mux_config_compute_basic[] = {
{ _MMIO(0x25428), 0x0c03 },
};
-static const struct i915_oa_reg *
+static int
get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
-int *len)
+const struct i915_oa_reg **regs,
+int *lens)
{
- *len = ARRAY_SIZE(mux_config_compute_basic);
- return mux_config_compute_basic;
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_compute_basic;
+ lens[n] = ARRAY_SIZE(mux_config_compute_basic);
+ n++;
+
+ return n;
}
static const struct i915_oa_reg b_counter_config_compute_extended[] = {
@@ -221,12 +239,21 @@ static const struct i915_oa_reg
mux_config_compute_extended[] = {
{ _MMIO(0x25428), 0x },
};
-static const struct i915_oa_reg *
+static int
get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
- int *len)
+ const struct i915_oa_reg **regs,
+ int *lens)
{
- *len = ARRAY_SIZE(mux_config_compute_extended);
- return mux_config_compute_extended;
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_compute_extended;
+ lens[n] = ARRAY_SIZE(mux_config_compute_extended);
+ n++;
+
+ return n;
}
static const struct i915_oa_reg b_counter_config_memory_reads[] = {
@@ -281,12 +308,21 @@ static const struct i915_oa_reg mux_config_memory_reads[]
= {
{ _MMIO(0x25428), 0x },
};
-static const struct i915_oa_reg *
+static int
get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
- int *len)
+ const struct i915_oa_reg **regs,
+ int *lens)
{
- *len = ARRAY_SIZE(mux_config_memory_reads);
- return mux_config_memory_reads;
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_memory_reads;
+ lens[n] = ARRAY_SIZE(mux_config_memory_reads);
+ n++;
+
+ return n;
}
static const struct i915_oa_reg b_counter_config_memory_writes[] = {
@@ -341,12 +377,21 @@ static const struct i915_oa_reg
mux_config_memory_writes[] = {
{ _MMIO(0x25428), 0x },
};
-static const struct i915_oa_reg *
+static i
[Intel-gfx] [PATCH 12/14] drm/i915: add KBL GT2/GT3 check macros
Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_drv.h | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7b9fd9d0f5b8..1d9c75caa26a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2758,6 +2758,10 @@ intel_info(const struct drm_i915_private *dev_priv) (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030) +#define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ +(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010) +#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ +(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support) -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/14] drm/i915/perf: Add 'render basic' Gen8+ OA unit configs
From: Robert Bragg
Adds a static OA unit, MUX, B Counter + Flex EU configurations for basic
render metrics on Broadwell, Cherryview, Skylake and Broxton. These are
auto generated from an XML description of metric sets, currently
maintained in gputop, ref:
https://github.com/rib/gputop
> gputop-data/oa-*.xml
> scripts/i915-perf-kernelgen.py
$ make -C gputop-data -f Makefile.xml WHITELIST=RenderBasic
v2: add newlines to debug messages + fix comment (Matthew Auld)
Signed-off-by: Robert Bragg
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/Makefile | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/i915_oa_bdw.c| 390 ++
drivers/gpu/drm/i915/i915_oa_bdw.h| 38
drivers/gpu/drm/i915/i915_oa_bxt.c| 246 +
drivers/gpu/drm/i915/i915_oa_bxt.h| 38
drivers/gpu/drm/i915/i915_oa_chv.c| 236
drivers/gpu/drm/i915/i915_oa_chv.h| 38
drivers/gpu/drm/i915/i915_oa_sklgt2.c | 236
drivers/gpu/drm/i915/i915_oa_sklgt2.h | 38
drivers/gpu/drm/i915/i915_oa_sklgt3.c | 247 +
drivers/gpu/drm/i915/i915_oa_sklgt3.h | 38
drivers/gpu/drm/i915/i915_oa_sklgt4.c | 258 ++
drivers/gpu/drm/i915/i915_oa_sklgt4.h | 38
14 files changed, 1852 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_oa_bdw.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_bdw.h
create mode 100644 drivers/gpu/drm/i915/i915_oa_bxt.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_bxt.h
create mode 100644 drivers/gpu/drm/i915/i915_oa_chv.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_chv.h
create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt2.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt2.h
create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt3.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt3.h
create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt4.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_sklgt4.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7b05fb802f4c..aabc660f94cb 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -128,7 +128,13 @@ i915-y += i915_vgpu.o
# perf code
i915-y += i915_perf.o \
- i915_oa_hsw.o
+ i915_oa_hsw.o \
+ i915_oa_bdw.o \
+ i915_oa_chv.o \
+ i915_oa_sklgt2.o \
+ i915_oa_sklgt3.o \
+ i915_oa_sklgt4.o \
+ i915_oa_bxt.o
ifeq ($(CONFIG_DRM_I915_GVT),y)
i915-y += intel_gvt.o
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 56ed5a0651e2..5185752981b2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2353,11 +2353,13 @@ struct drm_i915_private {
int metrics_set;
- const struct i915_oa_reg *mux_regs[1];
- int mux_regs_lens[1];
+ const struct i915_oa_reg *mux_regs[2];
+ int mux_regs_lens[2];
int n_mux_regs;
const struct i915_oa_reg *b_counter_regs;
int b_counter_regs_len;
+ const struct i915_oa_reg *flex_regs;
+ int flex_regs_len;
struct {
struct i915_vma *vma;
diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.c
b/drivers/gpu/drm/i915/i915_oa_bdw.c
new file mode 100644
index ..ff6b3564dddf
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_bdw.c
@@ -0,0 +1,390 @@
+/*
+ * Autogenerated file, DO NOT EDIT manually!
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+
+#include "i915_drv.h"
+#incl
[Intel-gfx] [PATCH 14/14] drm/i915/perf: add GLK support
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/Makefile |3 +-
drivers/gpu/drm/i915/i915_oa_glk.c | 2600
drivers/gpu/drm/i915/i915_oa_glk.h | 38 +
drivers/gpu/drm/i915/i915_perf.c | 15 +-
4 files changed, 2654 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_oa_glk.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_glk.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 859e1751d7ab..bb781bc628df 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -136,7 +136,8 @@ i915-y += i915_perf.o \
i915_oa_sklgt4.o \
i915_oa_bxt.o \
i915_oa_kblgt2.o \
- i915_oa_kblgt3.o
+ i915_oa_kblgt3.o \
+ i915_oa_glk.o
ifeq ($(CONFIG_DRM_I915_GVT),y)
i915-y += intel_gvt.o
diff --git a/drivers/gpu/drm/i915/i915_oa_glk.c
b/drivers/gpu/drm/i915/i915_oa_glk.c
new file mode 100644
index ..bda07ffaa40b
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_glk.c
@@ -0,0 +1,2600 @@
+/*
+ * Autogenerated file, DO NOT EDIT manually!
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+
+#include "i915_drv.h"
+#include "i915_oa_glk.h"
+
+enum metric_set_id {
+ METRIC_SET_ID_RENDER_BASIC = 1,
+ METRIC_SET_ID_COMPUTE_BASIC,
+ METRIC_SET_ID_RENDER_PIPE_PROFILE,
+ METRIC_SET_ID_MEMORY_READS,
+ METRIC_SET_ID_MEMORY_WRITES,
+ METRIC_SET_ID_COMPUTE_EXTENDED,
+ METRIC_SET_ID_COMPUTE_L3_CACHE,
+ METRIC_SET_ID_HDC_AND_SF,
+ METRIC_SET_ID_L3_1,
+ METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
+ METRIC_SET_ID_SAMPLER,
+ METRIC_SET_ID_TDL_1,
+ METRIC_SET_ID_TDL_2,
+ METRIC_SET_ID_COMPUTE_EXTRA,
+ METRIC_SET_ID_TEST_OA,
+};
+
+int i915_oa_n_builtin_metric_sets_glk = 15;
+
+static const struct i915_oa_reg b_counter_config_render_basic[] = {
+ { _MMIO(0x2710), 0x },
+ { _MMIO(0x2714), 0x0080 },
+ { _MMIO(0x2720), 0x },
+ { _MMIO(0x2724), 0x0080 },
+ { _MMIO(0x2740), 0x },
+};
+
+static const struct i915_oa_reg flex_eu_config_render_basic[] = {
+ { _MMIO(0xe458), 0x5004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_render_basic[] = {
+ { _MMIO(0x9888), 0x166c00f0 },
+ { _MMIO(0x9888), 0x12120280 },
+ { _MMIO(0x9888), 0x12320280 },
+ { _MMIO(0x9888), 0x11930317 },
+ { _MMIO(0x9888), 0x159303df },
+ { _MMIO(0x9888), 0x3f900c00 },
+ { _MMIO(0x9888), 0x419000a0 },
+ { _MMIO(0x9888), 0x002d1000 },
+ { _MMIO(0x9888), 0x062d4000 },
+ { _MMIO(0x9888), 0x082d5000 },
+ { _MMIO(0x9888), 0x0a2d1000 },
+ { _MMIO(0x9888), 0x0c2e0800 },
+ { _MMIO(0x9888), 0x0e2e5900 },
+ { _MMIO(0x9888), 0x0a4c8000 },
+ { _MMIO(0x9888), 0x0c4c8000 },
+ { _MMIO(0x9888), 0x0e4c4000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e2000 },
+ { _MMIO(0x9888), 0x1c4f0010 },
+ { _MMIO(0x9888), 0x0a6c0053 },
+ { _MMIO(0x9888), 0x106c },
+ { _MMIO(0x9888), 0x1c6c },
+ { _MMIO(0x9888), 0x1a0fcc00 },
+ { _MMIO(0x9888), 0x1c0f0002 },
+ { _MMIO(0x9888), 0x1c2c0040 },
+ { _MMIO(0x9888), 0x00101000 },
+ { _MMIO(0x9888), 0x04101000 },
+ { _MMIO(0x9888), 0x00114000 },
+ { _MMIO(0x9888), 0x08114000 },
+ { _MMIO(0x9888), 0x00120020 },
+ { _MMIO(0x9888), 0x08120021 },
+ { _MMIO(0x9888), 0x00141000 },
+ { _MMIO(0x9888), 0x08
[Intel-gfx] [PATCH 11/14] drm/i915/perf: remove perf.hook_lock
From: Robert Bragg
In earlier iterations of the i915-perf driver we had a number of
callbacks/hooks from other parts of the i915 driver to e.g. notify us
when a legacy context was pinned and these could run asynchronously with
respect to the stream file operations and might also run in atomic
context.
dev_priv->perf.hook_lock had been for serialising access to state needed
within these callbacks, but as the code has evolved some of the hooks
have gone away or are implemented to avoid needing to lock any state.
The remaining use of this lock was actually redundant considering how
the gen7 oacontrol state used to be updated as part of a context pin
hook.
Signed-off-by: Robert Bragg
Signed-off-by: Lionel Landwerlin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_perf.c | 32 ++--
2 files changed, 10 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 654607770542..7b9fd9d0f5b8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2326,8 +2326,6 @@ struct drm_i915_private {
struct mutex lock;
struct list_head streams;
- spinlock_t hook_lock;
-
struct {
struct i915_perf_stream *exclusive_stream;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index cf5f4a2cec52..b262a005aa54 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1831,9 +1831,17 @@ static void gen8_disable_metric_set(struct
drm_i915_private *dev_priv)
gen8_configure_all_contexts(dev_priv, false);
}
-static void gen7_update_oacontrol_locked(struct drm_i915_private *dev_priv)
+static void gen7_oa_enable(struct drm_i915_private *dev_priv)
{
- lockdep_assert_held(&dev_priv->perf.hook_lock);
+ /* Reset buf pointers so we don't forward reports from before now.
+*
+* Think carefully if considering trying to avoid this, since it
+* also ensures status flags and the buffer itself are cleared
+* in error paths, and we have checks for invalid reports based
+* on the assumption that certain fields are written to zeroed
+* memory which this helps maintains.
+*/
+ gen7_init_oa_buffer(dev_priv);
if (dev_priv->perf.oa.exclusive_stream->enabled) {
struct i915_gem_context *ctx =
@@ -1856,25 +1864,6 @@ static void gen7_update_oacontrol_locked(struct
drm_i915_private *dev_priv)
I915_WRITE(GEN7_OACONTROL, 0);
}
-static void gen7_oa_enable(struct drm_i915_private *dev_priv)
-{
- unsigned long flags;
-
- /* Reset buf pointers so we don't forward reports from before now.
-*
-* Think carefully if considering trying to avoid this, since it
-* also ensures status flags and the buffer itself are cleared
-* in error paths, and we have checks for invalid reports based
-* on the assumption that certain fields are written to zeroed
-* memory which this helps maintains.
-*/
- gen7_init_oa_buffer(dev_priv);
-
- spin_lock_irqsave(&dev_priv->perf.hook_lock, flags);
- gen7_update_oacontrol_locked(dev_priv);
- spin_unlock_irqrestore(&dev_priv->perf.hook_lock, flags);
-}
-
static void gen8_oa_enable(struct drm_i915_private *dev_priv)
{
u32 report_format = dev_priv->perf.oa.oa_buffer.format;
@@ -3124,7 +3113,6 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
INIT_LIST_HEAD(&dev_priv->perf.streams);
mutex_init(&dev_priv->perf.lock);
- spin_lock_init(&dev_priv->perf.hook_lock);
spin_lock_init(&dev_priv->perf.oa.oa_buffer.ptr_lock);
oa_sample_rate_hard_limit =
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Import the kfence selftests for i915_sw_fence
Chris Wilson writes: > On Mon, May 15, 2017 at 11:52:55AM +0100, Chris Wilson wrote: >> A long time ago, I wrote some selftests for the struct kfence idea. Now >> that we have infrastructure in i915/igt for running kselftests, include >> some for i915_sw_fence. >> >> Signed-off-by: Chris Wilson > > Anyone want to stamp these? kref has a stamp and I will take a look at this one. -Mika > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Import the kfence selftests for i915_sw_fence
Chris Wilson writes: > A long time ago, I wrote some selftests for the struct kfence idea. Now > that we have infrastructure in i915/igt for running kselftests, include > some for i915_sw_fence. > > Signed-off-by: Chris Wilson Only minor thing that caught my eye was that I would have preferred: err_free_C: type of gotos instead of just err_C. In here tho everything was straightfoward teardown of allocations so it was clear. Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/Kconfig.debug | 12 + > drivers/gpu/drm/i915/i915_sw_fence.c | 7 +- > .../gpu/drm/i915/selftests/i915_mock_selftests.h | 1 + > drivers/gpu/drm/i915/selftests/i915_sw_fence.c | 576 > + > 4 files changed, 595 insertions(+), 1 deletion(-) > create mode 100644 drivers/gpu/drm/i915/selftests/i915_sw_fence.c > > diff --git a/drivers/gpu/drm/i915/Kconfig.debug > b/drivers/gpu/drm/i915/Kconfig.debug > index b00edd3b8800..78c5c049a347 100644 > --- a/drivers/gpu/drm/i915/Kconfig.debug > +++ b/drivers/gpu/drm/i915/Kconfig.debug > @@ -61,6 +61,18 @@ config DRM_I915_SW_FENCE_DEBUG_OBJECTS > >If in doubt, say "N". > > +config DRM_I915_SW_FENCE_CHECK_DAG > +bool "Enable additional driver debugging for detecting dependency > cycles" > +depends on DRM_I915 > +default n > +help > + Choose this option to turn on extra driver debugging that may > affect > + performance but will catch some internal issues. > + > + Recommended for driver developers only. > + > + If in doubt, say "N". > + > config DRM_I915_SELFTEST > bool "Enable selftests upon driver load" > depends on DRM_I915 > diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c > b/drivers/gpu/drm/i915/i915_sw_fence.c > index a0a690d6627e..474d23c0c0ce 100644 > --- a/drivers/gpu/drm/i915/i915_sw_fence.c > +++ b/drivers/gpu/drm/i915/i915_sw_fence.c > @@ -12,6 +12,7 @@ > #include > > #include "i915_sw_fence.h" > +#include "i915_selftest.h" > > #define I915_SW_FENCE_FLAG_ALLOC BIT(3) /* after WQ_FLAG_* for safety */ > > @@ -274,7 +275,7 @@ static bool i915_sw_fence_check_if_after(struct > i915_sw_fence *fence, > unsigned long flags; > bool err; > > - if (!IS_ENABLED(CONFIG_I915_SW_FENCE_CHECK_DAG)) > + if (!IS_ENABLED(CONFIG_DRM_I915_SW_FENCE_CHECK_DAG)) > return false; > > spin_lock_irqsave(&i915_sw_fence_lock, flags); > @@ -490,3 +491,7 @@ int i915_sw_fence_await_reservation(struct i915_sw_fence > *fence, > > return ret; > } > + > +#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) > +#include "selftests/i915_sw_fence.c" > +#endif > diff --git a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h > b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h > index 76c1f149a0a0..fc74687501ba 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h > +++ b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h > @@ -9,6 +9,7 @@ > * Tests are executed in order by igt/drv_selftest > */ > selftest(sanitycheck, i915_mock_sanitycheck) /* keep first (igt selfcheck) */ > +selftest(fence, i915_sw_fence_mock_selftests) > selftest(scatterlist, scatterlist_mock_selftests) > selftest(syncmap, i915_syncmap_mock_selftests) > selftest(uncore, intel_uncore_mock_selftests) > diff --git a/drivers/gpu/drm/i915/selftests/i915_sw_fence.c > b/drivers/gpu/drm/i915/selftests/i915_sw_fence.c > new file mode 100644 > index ..c552c23eecff > --- /dev/null > +++ b/drivers/gpu/drm/i915/selftests/i915_sw_fence.c > @@ -0,0 +1,576 @@ > +/* > + * Copyright © 2017 Intel Corporation > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice (including the next > + * paragraph) shall be included in all copies or substantial portions of the > + * Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER > DEALINGS > + * IN THE SOFTWARE. > + * > + */ > + > +#include > +#include > + > +#include "../i915_selftest.h" > + > +static int __i915_sw_fence_call > +fence_notify(struct i915_sw_fence *fe
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Reorder media/render reset on g4x
Chris Wilson writes: > Ville found a reference to WaMediaResetBeforeFullReset which we presume > means that we should simply do the media reset first. Yesterday I reordered the resets but I recall it didnt help. I will retry but regardless yeah resetting media first makes sense. > > References: https://bugs.freedesktop.org/show_bug.cgi?id=100942 > Suggested-by: Ville Syrjälä > Signed-off-by: Chris Wilson > Cc: Ville Syrjälä > Cc: Mika Kuoppala > --- > drivers/gpu/drm/i915/intel_uncore.c | 12 ++-- > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c > b/drivers/gpu/drm/i915/intel_uncore.c > index fc3da0a6fdbb..c3d0d81b50e4 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -1504,12 +1504,6 @@ static int g4x_do_reset(struct drm_i915_private > *dev_priv, unsigned engine_mask) > struct pci_dev *pdev = dev_priv->drm.pdev; > int ret; > > - pci_write_config_byte(pdev, I915_GDRST, > - GRDOM_RENDER | GRDOM_RESET_ENABLE); > - ret = wait_for(g4x_reset_complete(pdev), 500); > - if (ret) > - goto out; > - > /* WaVcpClkGateDisableForMediaReset:ctg,elk */ > I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | > VCP_UNIT_CLOCK_GATE_DISABLE); > POSTING_READ(VDECCLK_GATE_D); > @@ -1517,11 +1511,17 @@ static int g4x_do_reset(struct drm_i915_private > *dev_priv, unsigned engine_mask) > pci_write_config_byte(pdev, I915_GDRST, > GRDOM_MEDIA | GRDOM_RESET_ENABLE); > ret = wait_for(g4x_reset_complete(pdev), 500); > + if (ret) > + goto out; > We should restore the WaVcp... state if we fail. Not that it was right to begin with. -Mika > /* WaVcpClkGateDisableForMediaReset:ctg,elk */ > I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & > ~VCP_UNIT_CLOCK_GATE_DISABLE); > POSTING_READ(VDECCLK_GATE_D); > > + pci_write_config_byte(pdev, I915_GDRST, > + GRDOM_RENDER | GRDOM_RESET_ENABLE); > + ret = wait_for(g4x_reset_complete(pdev), 500); > + > out: > pci_write_config_byte(pdev, I915_GDRST, 0); > return ret; > -- > 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Try harder to reset the GPU
Chris Wilson writes:
> Repeat the reset a couple of times if at first we do not succeed.
>
> Signed-off-by: Chris Wilson
> Link:
> http://patchwork.freedesktop.org/patch/msgid/20170513083726.502-1-ch...@chris-wilson.co.uk
Seems that this is already merged but FWIW.
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 44
> +
> 1 file changed, 25 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 71b9b387ad04..fc3da0a6fdbb 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1463,9 +1463,10 @@ int i915_reg_read_ioctl(struct drm_device *dev,
> return ret;
> }
>
> -static int i915_reset_complete(struct pci_dev *pdev)
> +static bool i915_reset_complete(struct pci_dev *pdev)
> {
> u8 gdrst;
> +
> pci_read_config_byte(pdev, I915_GDRST, &gdrst);
> return (gdrst & GRDOM_RESET_STATUS) == 0;
> }
> @@ -1476,15 +1477,16 @@ static int i915_do_reset(struct drm_i915_private
> *dev_priv, unsigned engine_mask
>
> /* assert reset for at least 20 usec */
> pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
> - udelay(20);
> + usleep_range(50, 200);
> pci_write_config_byte(pdev, I915_GDRST, 0);
>
> return wait_for(i915_reset_complete(pdev), 500);
> }
>
> -static int g4x_reset_complete(struct pci_dev *pdev)
> +static bool g4x_reset_complete(struct pci_dev *pdev)
> {
> u8 gdrst;
> +
> pci_read_config_byte(pdev, I915_GDRST, &gdrst);
> return (gdrst & GRDOM_RESET_ENABLE) == 0;
> }
> @@ -1492,6 +1494,7 @@ static int g4x_reset_complete(struct pci_dev *pdev)
> static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned
> engine_mask)
> {
> struct pci_dev *pdev = dev_priv->drm.pdev;
> +
> pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
> return wait_for(g4x_reset_complete(pdev), 500);
> }
> @@ -1505,7 +1508,7 @@ static int g4x_do_reset(struct drm_i915_private
> *dev_priv, unsigned engine_mask)
> GRDOM_RENDER | GRDOM_RESET_ENABLE);
> ret = wait_for(g4x_reset_complete(pdev), 500);
> if (ret)
> - return ret;
> + goto out;
>
> /* WaVcpClkGateDisableForMediaReset:ctg,elk */
> I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) |
> VCP_UNIT_CLOCK_GATE_DISABLE);
> @@ -1514,16 +1517,14 @@ static int g4x_do_reset(struct drm_i915_private
> *dev_priv, unsigned engine_mask)
> pci_write_config_byte(pdev, I915_GDRST,
> GRDOM_MEDIA | GRDOM_RESET_ENABLE);
> ret = wait_for(g4x_reset_complete(pdev), 500);
> - if (ret)
> - return ret;
>
> /* WaVcpClkGateDisableForMediaReset:ctg,elk */
> I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) &
> ~VCP_UNIT_CLOCK_GATE_DISABLE);
> POSTING_READ(VDECCLK_GATE_D);
>
> +out:
> pci_write_config_byte(pdev, I915_GDRST, 0);
> -
> - return 0;
> + return ret;
> }
>
> static int ironlake_do_reset(struct drm_i915_private *dev_priv,
> @@ -1531,25 +1532,21 @@ static int ironlake_do_reset(struct drm_i915_private
> *dev_priv,
> {
> int ret;
>
> - I915_WRITE(ILK_GDSR,
> -ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
> + I915_WRITE(ILK_GDSR, ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
> ret = intel_wait_for_register(dev_priv,
> ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
> 500);
> if (ret)
> - return ret;
> + goto out;
>
> - I915_WRITE(ILK_GDSR,
> -ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
> + I915_WRITE(ILK_GDSR, ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
> ret = intel_wait_for_register(dev_priv,
> ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
> 500);
> - if (ret)
> - return ret;
> -
> +out:
> I915_WRITE(ILK_GDSR, 0);
> -
> - return 0;
> + POSTING_READ(ILK_GDSR);
> + return ret;
> }
>
> /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
> @@ -1758,8 +1755,11 @@ static reset_func intel_get_gpu_reset(struct
> drm_i915_private *dev_priv)
> int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
> {
> reset_func reset;
> + int retry;
> int ret;
>
> + might_sleep();
> +
> reset = intel_get_gpu_reset(dev_priv);
> if (reset == NULL)
> return -ENODEV;
> @@ -1768,7 +1768,13 @@ int intel_gpu_reset(struct drm_i915_private *dev_priv,
> unsigned engine_mask)
>* request may be dropped and never completes (causing -EIO).
>*/
> intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> - ret = reset(dev_priv, engine_mask);
> + for (retry = 0; retry < 3; retry+
Re: [Intel-gfx] [PATCH] drm/i915: Disable decoupled mmio for GEN9LP
On Wed, 17 May 2017, Tvrtko Ursulin wrote:
> On 17/05/2017 02:07, kai.c...@intel.com wrote:
>> From: Kai Chen
>>
>> The decoupled mmio feature doesn't work as intended by HW team. Enabling
>> it with forcewake will only make debugging efforts more difficult, so
>> let's just simply remove it.
>>
>> v2:
>> - Remove dead code related to GEN9LP decoupled mmio.
>> - Change backgrounds: In theory, decoupled mmio should require less cycles
>> for single read/write operation by avoiding frequent software forcewake.
>> However, it turns out this design not to be true on HW practice and not to
>> provide any decoupling benefit. It also introduces problems which cause
>> failures in intel-gpu-tools (gem), and also cause driver code and debugging
>> more complex.
>> - This change therefore reverts:
>>
>> commit 85ee17ebeedd1af0dccd98f82ab4e644e29d84c0
>> Author: Praveen Paneri
>> Date: Tue, 15 Nov 2016 22:49:20 +0530
>>
>> drm/i915/bxt: Broxton decoupled MMIO
>>
>> coomit a3f79ca63b9bcf5a527b886953092bfd65e78940
>> Author: Ander Conselvan de Oliveira
>> Date: Thu, 24 Nov 2016 15:23:27 +0200
>>
>> drm/i915: Don't sanitize has_decoupled_mmio if platform is not broxton
>
> Revert looks incomplete since it is leaving behind the field in the
> device info and HAS_DECOUPLED_MMIO macro.
We've shipped kernels with decoupled mmio enabled, so we need to
backport the fix. IOW, we'll need the simple patch [1] with proper
Fixes: annotations, which will be backported, and another patch on top
with the rest that's not going to be backported.
BR,
Jani.
[1]
http://patchwork.freedesktop.org/patch/msgid/20170515231827.17902-1-kai.c...@intel.com
>
> But revert in principle is fine by me.
>
> Regards,
>
> Tvrtko
>
>> Signed-off-by: Kai Chen
>> ---
>> drivers/gpu/drm/i915/i915_pci.c | 1 -
>> drivers/gpu/drm/i915/i915_reg.h | 7 --
>> drivers/gpu/drm/i915/intel_uncore.c | 126
>>
>> 3 files changed, 134 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c
>> b/drivers/gpu/drm/i915/i915_pci.c
>> index f80db2c..cf43dc1 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -385,7 +385,6 @@ static const struct intel_device_info
>> intel_skylake_gt3_info = {
>> .has_gmbus_irq = 1, \
>> .has_logical_ring_contexts = 1, \
>> .has_guc = 1, \
>> -.has_decoupled_mmio = 1, \
>> .has_aliasing_ppgtt = 1, \
>> .has_full_ppgtt = 1, \
>> .has_full_48bit_ppgtt = 1, \
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index ee144ec..78872f9 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7792,13 +7792,6 @@ enum {
>> #define SKL_FUSE_PG1_DIST_STATUS (1<<26)
>> #define SKL_FUSE_PG2_DIST_STATUS (1<<25)
>>
>> -/* Decoupled MMIO register pair for kernel driver */
>> -#define GEN9_DECOUPLED_REG0_DW0 _MMIO(0xF00)
>> -#define GEN9_DECOUPLED_REG0_DW1 _MMIO(0xF04)
>> -#define GEN9_DECOUPLED_DW1_GO (1<<31)
>> -#define GEN9_DECOUPLED_PD_SHIFT 28
>> -#define GEN9_DECOUPLED_OP_SHIFT 24
>> -
>> /* Per-pipe DDI Function Control */
>> #define _TRANS_DDI_FUNC_CTL_A 0x60400
>> #define _TRANS_DDI_FUNC_CTL_B 0x61400
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
>> b/drivers/gpu/drm/i915/intel_uncore.c
>> index a9a6933..3901800 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -400,8 +400,6 @@ check_for_unclaimed_mmio(struct drm_i915_private
>> *dev_priv)
>> static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
>>bool restore_forcewake)
>> {
>> -struct intel_device_info *info = mkwrite_device_info(dev_priv);
>> -
>> /* clear out unclaimed reg detection bit */
>> if (check_for_unclaimed_mmio(dev_priv))
>> DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
>> @@ -414,9 +412,6 @@ static void __intel_uncore_early_sanitize(struct
>> drm_i915_private *dev_priv,
>> GT_FIFO_CTL_RC6_POLICY_STALL);
>> }
>>
>> -if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST))
>> -info->has_decoupled_mmio = false;
>> -
>> intel_uncore_forcewake_reset(dev_priv, restore_forcewake);
>> }
>>
>> @@ -801,78 +796,6 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
>> __unclaimed_reg_debug(dev_priv, reg, read, before);
>> }
>>
>> -enum decoupled_power_domain {
>> -GEN9_DECOUPLED_PD_BLITTER = 0,
>> -GEN9_DECOUPLED_PD_RENDER,
>> -GEN9_DECOUPLED_PD_MEDIA,
>> -GEN9_DECOUPLED_PD_ALL
>> -};
>> -
>> -enum decoupled_ops {
>> -GEN9_DECOUPLED_OP_WRITE = 0,
>> -GEN9_DECOUPLED_OP_READ
>> -};
>> -
>> -static const enum decoupled_power_domain
Re: [Intel-gfx] [PATCH 2/3] drm: Create a format/modifier blob
On Tue, May 16, 2017 at 02:19:12PM -0700, Ben Widawsky wrote:
> On 17-05-03 17:08:27, Daniel Vetter wrote:
> > On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote:
> > > +struct drm_format_modifier_blob {
> > > +#define FORMAT_BLOB_CURRENT 1
> > > + /* Version of this blob format */
> > > + u32 version;
> > > +
> > > + /* Flags */
> > > + u32 flags;
> > > +
> > > + /* Number of fourcc formats supported */
> > > + u32 count_formats;
> > > +
> > > + /* Where in this blob the formats exist (in bytes) */
> > > + u32 formats_offset;
> > > +
> > > + /* Number of drm_format_modifiers */
> > > + u32 count_modifiers;
> > > +
> > > + /* Where in this blob the modifiers exist (in bytes) */
> > > + u32 modifiers_offset;
> > > +
> > > + /* u32 formats[] */
> > > + /* struct drm_format_modifier modifiers[] */
> > > +} __packed;
> >
> > The struct should be in the uapi header. Otherwise it won't show up in
> > libdrm headers when following the proper process.
> > -Daniel
> >
>
> I don't agree that blobs are ever really part of the API, but it doesn't hurt
> to
> move it... in other words, done.
Userspace writes them, the kernel reads them (or maybe even the other way
round). How exactly is a specific blob and its layout not part of uapi?
Can you explain your reasoning here pls?
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH] drm/i915/gen9: Reintroduce WaEnableYV12BugFixInHalfSliceChicken7
Arkadiusz Hiler writes:
> This basically reverts commit 465418c6064c
> ("drm/i915/gen9: Remove WaEnableYV12BugFixInHalfSliceChicken7")
> with small addition - marking it as affecting KBL as well.
>
> It was incorrectly considered fixed in production steppings.
>
> References: HSD#2126385, HSD#2131381, HSDES#1504433555, BSID#0764
> Cc: Mika Kuoppala
> Cc: Jeff McGee
> Signed-off-by: Arkadiusz Hiler
Pushed, thanks for the patch.
-Mika
> ---
> drivers/gpu/drm/i915/intel_engine_cs.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 483ed76..49c2315 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -851,8 +851,10 @@ static int gen9_init_workarounds(struct intel_engine_cs
> *engine)
>*/
> }
>
> + /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk */
> /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
> WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
> + GEN9_ENABLE_YV12_BUGFIX |
> GEN9_ENABLE_GPGPU_PREEMPTION);
>
> /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk */
> --
> 2.9.3
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Reorder media/render reset on g4x
On Tue, May 16, 2017 at 04:38:01PM +0300, Mika Kuoppala wrote: > Chris Wilson writes: > > > Ville found a reference to WaMediaResetBeforeFullReset which we presume > > means that we should simply do the media reset first. > > Yesterday I reordered the resets but I recall it didnt help. > I will retry but regardless yeah resetting media first makes > sense. > > > > > References: https://bugs.freedesktop.org/show_bug.cgi?id=100942 > > Suggested-by: Ville Syrjälä > > Signed-off-by: Chris Wilson > > Cc: Ville Syrjälä > > Cc: Mika Kuoppala > > --- > > drivers/gpu/drm/i915/intel_uncore.c | 12 ++-- > > 1 file changed, 6 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c > > b/drivers/gpu/drm/i915/intel_uncore.c > > index fc3da0a6fdbb..c3d0d81b50e4 100644 > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > @@ -1504,12 +1504,6 @@ static int g4x_do_reset(struct drm_i915_private > > *dev_priv, unsigned engine_mask) > > struct pci_dev *pdev = dev_priv->drm.pdev; > > int ret; > > > > - pci_write_config_byte(pdev, I915_GDRST, > > - GRDOM_RENDER | GRDOM_RESET_ENABLE); > > - ret = wait_for(g4x_reset_complete(pdev), 500); > > - if (ret) > > - goto out; > > - > > /* WaVcpClkGateDisableForMediaReset:ctg,elk */ > > I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | > > VCP_UNIT_CLOCK_GATE_DISABLE); > > POSTING_READ(VDECCLK_GATE_D); > > @@ -1517,11 +1511,17 @@ static int g4x_do_reset(struct drm_i915_private > > *dev_priv, unsigned engine_mask) > > pci_write_config_byte(pdev, I915_GDRST, > > GRDOM_MEDIA | GRDOM_RESET_ENABLE); > > ret = wait_for(g4x_reset_complete(pdev), 500); > > + if (ret) > > + goto out; > > > > We should restore the WaVcp... state if we fail. Not that it > was right to begin with. I had it that way so that one could figure out which part of the reset failed by examining the registers afterwards. If we change that then we should add more debug/error prints to let us know exactly what failed. > > -Mika > > > /* WaVcpClkGateDisableForMediaReset:ctg,elk */ > > I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & > > ~VCP_UNIT_CLOCK_GATE_DISABLE); > > POSTING_READ(VDECCLK_GATE_D); > > > > + pci_write_config_byte(pdev, I915_GDRST, > > + GRDOM_RENDER | GRDOM_RESET_ENABLE); > > + ret = wait_for(g4x_reset_complete(pdev), 500); > > + > > out: > > pci_write_config_byte(pdev, I915_GDRST, 0); > > return ret; > > -- > > 2.11.0 -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Reorder media/render reset on g4x
Ville Syrjälä writes: > On Tue, May 16, 2017 at 04:38:01PM +0300, Mika Kuoppala wrote: >> Chris Wilson writes: >> >> > Ville found a reference to WaMediaResetBeforeFullReset which we presume >> > means that we should simply do the media reset first. >> >> Yesterday I reordered the resets but I recall it didnt help. >> I will retry but regardless yeah resetting media first makes >> sense. >> >> > >> > References: https://bugs.freedesktop.org/show_bug.cgi?id=100942 >> > Suggested-by: Ville Syrjälä >> > Signed-off-by: Chris Wilson >> > Cc: Ville Syrjälä >> > Cc: Mika Kuoppala >> > --- >> > drivers/gpu/drm/i915/intel_uncore.c | 12 ++-- >> > 1 file changed, 6 insertions(+), 6 deletions(-) >> > >> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c >> > b/drivers/gpu/drm/i915/intel_uncore.c >> > index fc3da0a6fdbb..c3d0d81b50e4 100644 >> > --- a/drivers/gpu/drm/i915/intel_uncore.c >> > +++ b/drivers/gpu/drm/i915/intel_uncore.c >> > @@ -1504,12 +1504,6 @@ static int g4x_do_reset(struct drm_i915_private >> > *dev_priv, unsigned engine_mask) >> >struct pci_dev *pdev = dev_priv->drm.pdev; >> >int ret; >> > >> > - pci_write_config_byte(pdev, I915_GDRST, >> > -GRDOM_RENDER | GRDOM_RESET_ENABLE); >> > - ret = wait_for(g4x_reset_complete(pdev), 500); >> > - if (ret) >> > - goto out; >> > - >> >/* WaVcpClkGateDisableForMediaReset:ctg,elk */ >> >I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | >> > VCP_UNIT_CLOCK_GATE_DISABLE); >> >POSTING_READ(VDECCLK_GATE_D); >> > @@ -1517,11 +1511,17 @@ static int g4x_do_reset(struct drm_i915_private >> > *dev_priv, unsigned engine_mask) >> >pci_write_config_byte(pdev, I915_GDRST, >> > GRDOM_MEDIA | GRDOM_RESET_ENABLE); >> >ret = wait_for(g4x_reset_complete(pdev), 500); >> > + if (ret) >> > + goto out; >> > >> >> We should restore the WaVcp... state if we fail. Not that it >> was right to begin with. > > I had it that way so that one could figure out which part of the reset > failed by examining the registers afterwards. If we change that then > we should add more debug/error prints to let us know exactly what failed. > Well with that explanation, Reviewed-by: Mika Kuoppala Sadly, the reset can still fail even with this applied. -Mika >> >> -Mika >> >> >/* WaVcpClkGateDisableForMediaReset:ctg,elk */ >> >I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & >> > ~VCP_UNIT_CLOCK_GATE_DISABLE); >> >POSTING_READ(VDECCLK_GATE_D); >> > >> > + pci_write_config_byte(pdev, I915_GDRST, >> > +GRDOM_RENDER | GRDOM_RESET_ENABLE); >> > + ret = wait_for(g4x_reset_complete(pdev), 500); >> > + >> > out: >> >pci_write_config_byte(pdev, I915_GDRST, 0); >> >return ret; >> > -- >> > 2.11.0 > > -- > Ville Syrjälä > Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Call trace on 4.12.0-rc1
On Wed, May 17, 2017 at 12:36:35PM +0300, Ville Syrjälä wrote: > On Tue, May 16, 2017 at 10:43:39PM +0200, Hans de Goede wrote: > > Hi, > > > > On 05/16/2017 09:55 PM, FKr wrote: > > > Hi, > > > I'm using 4.12.0-rc1 from https://github.com/jwrdegoede/linux-sunxi and > > > got > > > the following weird trace yesterday. Previously I've been getting output > > > similar to https://www.spinics.net/lists/intel-gfx/msg127638.html, some > > > boots > > > on 4.12.0-rc1 I don't get any trace at all. > > > > This is really weird, we are getting the error while we are trying to > > acquire the wakelock ... ? Or do we need some other lock before we can > > take the wakelock ? > > You would also need the runtime pm reference. IIRC we unregister the > notifier in runtime suspend, so I think intel_runtime_pm_get_noresume() > should be OK in this case. Imre? Imre pointed out that the current code also fails to re-registering the notifier from runtime resume. So there's more to fix here. As far as using the get_noresume() from the notifier, we'll at least need to reorder the runtime suspend code to do the uncore suspend before we do the allow_gt_wake(false) etc. Actually, that part of the sequence seems to be already somewhat wrong because the forcewake timer might still be active until the uncore suspend, and having active forcewakes while we've already told the GT wake stuff to stop acting normally doesn't seem quite right to me. > > > > > Any input from one of the Intel developers would be appreciated. > > > > Regards, > > > > Hans > > > > > > > > > > [ 2383.844192] perf: interrupt took too long (2522 > 2500), lowering > > > kernel.perf_event_max_sample_rate to 79200 > > > [ 2634.863978] [drm:intel_pipe_update_end] *ERROR* Atomic update failure > > > on > > > pipe A (start=157909 end=157910) time 322 us, min 1073, max 1079, scanline > > > start 1063, end 1084 > > > [ 2647.881794] perf: interrupt took too long (3193 > 3152), lowering > > > kernel.perf_event_max_sample_rate to 62400 > > > [ 3297.857921] perf: interrupt took too long (4020 > 3991), lowering > > > kernel.perf_event_max_sample_rate to 49500 > > > [ 4670.977136] mmc0: Tuning timeout, falling back to fixed sampling clock > > > [ 4671.436604] mmc0: Tuning timeout, falling back to fixed sampling clock > > > [ 4680.756302] mmc0: Tuning timeout, falling back to fixed sampling clock > > > [ 4707.846872] perf: interrupt took too long (5046 > 5025), lowering > > > kernel.perf_event_max_sample_rate to 39600 > > > [ 4846.672969] RPM wakelock ref not held during HW access > > > [ 4846.673050] [ cut here ] > > > [ 4846.673084] WARNING: CPU: 0 PID: 5227 at > > > drivers/gpu/drm/i915/intel_drv.h: > > > 1780 intel_uncore_forcewake_get+0xa0/0xb0 > > > [ 4846.673088] Modules linked in: snd_soc_sst_cht_bsw_nau8824 btusb > > > btintel > > > bluetooth axp288_fuel_gauge ecdh_generic axp288_charger extcon_axp288 > > > axp288_adc snd_hdmi_lpe_audio snd_intel_sst_acpi extcon_intel_int3496 > > > snd_intel_sst_core extcon_core snd_soc_nau8824 > > > snd_soc_sst_atom_hifi2_platform > > > snd_soc_core snd_compress snd_soc_sst_match snd_pcm snd_timer kxcjk_1013 > > > industrialio_triggered_buffer intel_cht_int33fe snd soundcore > > > intel_int0002 > > > [ 4846.673201] CPU: 0 PID: 5227 Comm: kworker/0:1 Not tainted 4.12.0-rc1+ > > > #3 > > > [ 4846.673206] Hardware name: MEDION E2228T MD60250/NT16H, BIOS 5.11 > > > 02/27/2017 > > > [ 4846.673224] Workqueue: events fuel_gauge_status_monitor > > > [axp288_fuel_gauge] > > > [ 4846.673235] task: 8800a85be800 task.stack: c9000261 > > > [ 4846.673248] RIP: 0010:intel_uncore_forcewake_get+0xa0/0xb0 > > > [ 4846.673255] RSP: 0018:c90002613aa0 EFLAGS: 00010286 > > > [ 4846.673265] RAX: 002a RBX: 880136cc8000 RCX: > > > 82063e88 > > > [ 4846.673272] RDX: RSI: 0082 RDI: > > > 0247 > > > [ 4846.673278] RBP: c90002613ac0 R08: 002a R09: > > > 02ac > > > [ 4846.673284] R10: 0001 R11: R12: > > > 0007 > > > [ 4846.673289] R13: 0001 R14: R15: > > > > > > [ 4846.673298] FS: () GS:88013fc0() > > > knlGS: > > > > > > [ 4846.673305] CS: 0010 DS: ES: CR0: 80050033 > > > [ 4846.673311] CR2: 0758c709c000 CR3: 02009000 CR4: > > > 001006f0 > > > [ 4846.673317] Call Trace: > > > [ 4846.673340] i915_pmic_bus_access_notifier+0x37/0x40 > > > [ 4846.673354] notifier_call_chain+0x4a/0x70 > > > [ 4846.673368] __blocking_notifier_call_chain+0x47/0x60 > > > [ 4846.673380] blocking_notifier_call_chain+0x16/0x20 > > > [ 4846.673393] iosf_mbi_call_pmic_bus_access_notifier_chain+0x1b/0x20 > > > [ 4846.673406] baytrail_i2c_acquire+0x64/0x220 > > > [ 4846.673420] i2c_dw_acquire_lock+0x21/0x50 > > > [ 4846.673431] i2c_dw_xfer+0xa3/0x4a0 > > > [ 484
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Try harder to reset the GPU
On Tue, May 16, 2017 at 04:55:29PM +0300, Mika Kuoppala wrote: > Chris Wilson writes: > > > Repeat the reset a couple of times if at first we do not succeed. > > > > Signed-off-by: Chris Wilson > > Link: > > http://patchwork.freedesktop.org/patch/msgid/20170513083726.502-1-ch...@chris-wilson.co.uk > > Seems that this is already merged but FWIW. No, just the only way to get it tested on the right machines was to apply it into a topic branch. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 00/12] Implement DDB algorithm and WM cleanup
This series implements new DDB allocation algorithm to solve the cases, where we have sufficient DDB available to enable multiple planes, But due to the current algorithm not dividing it properly among planes, we end-up failing the flip. It also takes care of enabling same watermark level for each plane, for efficient power saving. Series also fixes/cleans-up few bug in present code. There are two steps in current WM programming. 1. Calculate minimum number of blocks required for a WM level to be enabled. For 1440x2560 panel we need 41 blocks as minimum number of blocks to enable WM0. This is the step which doesn't use vertical size. It only depends on Pipe drain rate and plane horizontal size as per the current Bspec algorithm. So all the plane below have minimum number of blocks required to enable WM0 as 41 Plane 1 - 1440x2560-Min blocks to enable WM0 = 41 Plane 2 - 1440x2560-Min blocks to enable WM0 = 41 Plane 3 - 1440x48 -Min blocks to enable WM0 = 41 Plane 4 - 1440x96 -Min blocks to enable WM0 = 41 2. Number of blocks allotted by the driver Driver allocates 12 for Plane 3 & 16 for plane 4 Total Dbuf Available = 508 Dbuf Available after 32 blocks for cursor = 508 - (32) = 476 allocate minimum blocks for each plane 8 * 4 = 32 remaining blocks = 476 - 32 = 444 Relative Data Rate for Planes Plane 1 = 1440 * 2560 * 3 = 11059200 Plane 2 = 1440 * 2560 * 3 = 11059200 Plane 3 = 1440 * 48 * 3 = 207360 Plane 4 = 1440 * 96 * 3 = 414720 Total Relative BW= 22740480 - Allocate Buffer buffer allocation = (Plane relative data rate / total data rate) * total remaming DDB + minimum plane DDB Plane 1 buffer allocation = (11059200 / 22740480) * 444 + 8 = 223 Plane 2 buffer allocation = (11059200 / 22740480) * 444 + 8 = 223 Plane 3 buffer allocation = (207360 / 22740480) * 444 + 8 = 12 Plane 4 buffer allocation = (414720 / 22740480) * 444 + 8 = 16 In this case it forced driver to disable Plane 3 & 4. Driver need to use more efficient way to allocate buffer that is optimum for power. New Algorithm suggested by HW team is: 1. Calculate minimum buffer allocations for each plane and for each watermark level 2. Add minimum buffer allocations required for enabling WM7 for all the planes Level 0 = 41 + 41 + 41 + 41 = 164 Level 1 = 42 + 42 + 42 + 42 = 168 Level 2 = 42 + 42 + 42 + 42 = 168 Level 3 = 94 + 94 + 94 + 94 = 376 Level 4 = 94 + 94 + 94 + 94 = 376 Level 5 = 94 + 94 + 94 + 94 = 376 Level 6 = 94 + 94 + 94 + 94 = 376 Level 7 = 94 + 94 + 94 + 94 = 376 3. Check to see how many buffer allocation are left and enable the best case. In this case since we have 476 blocks we can enable WM0-7 on all 4 planes. Let's say if we have only 200 block available then the best cases allocation is to enable Level2 which requires 168 blocks Kumar, Mahesh (11): drm/i915: fix naming of fixed_16_16 wrapper. drm/i915: Add more wrapper for fixed_point_16_16 operations drm/i915: Use fixed_16_16 wrapper for division operation drm/i915/skl+: calculate pixel_rate & relative_data_rate in fixed point drm/i915/skl: Fail the flip if no FB for WM calculation drm/i915/skl+: no need to memset again drm/i915/skl+: Fail the flip if ddb min requirement exceeds pipe allocation drm/i915/skl+: Watermark calculation cleanup drm/i915/skl+: use linetime latency if ddb size is not available drm/i915/skl: New ddb allocation algorithm drm/i915/skl+: consider max supported plane pixel rate while scaling Kumar, Mahesh (12): drm/i915: fix naming of fixed_16_16 wrapper. drm/i915: Add more wrapper for fixed_point_16_16 operations drm/i915: Use fixed_16_16 wrapper for division operation drm/i915/skl+: calculate pixel_rate & relative_data_rate in fixed point drm/i915/skl: Fail the flip if no FB for WM calculation drm/i915/skl+: no need to memset again drm/i915/skl+: Fail the flip if ddb min requirement exceeds pipe allocation drm/i915/skl+: Watermark calculation cleanup drm/i915/skl+: Perform wm level calculations in separate function drm/i915/skl+: use linetime latency if ddb size is not available drm/i915/skl: New ddb allocation algorithm drm/i915/skl+: consider max supported plane pixel rate while scaling drivers/gpu/drm/i915/i915_drv.h | 56 +++- drivers/gpu/drm/i915/intel_display.c | 3 + drivers/gpu/drm/i915/intel_drv.h | 2 + drivers/gpu/drm/i915/intel_pm.c | 527 +++ 4 files changed, 400 insertions(+), 188 deletions(-) -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/12] drm/i915: fix naming of fixed_16_16 wrapper.
From: "Kumar, Mahesh"
fixed_16_16_div_round_up(_u64), wrapper for fixed_16_16 division
operation don't really round_up the result. Wrapper round_up only the
fraction part of the result to make it 16-bit.
This patch eliminates round_up keyword from the wrapper.
Later patch will introduce the new wrapper to do rounding-off the result
and give unt32_t output to cleanup mix use of fixed_16_16_t & uint32_t
variables.
Signed-off-by: Mahesh Kumar
Reviewed-by: Matt Roper
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/intel_pm.c | 6 +++---
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a6f20471b4cd..a6042013cd75 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -153,8 +153,7 @@ static inline uint_fixed_16_16_t
max_fixed_16_16(uint_fixed_16_16_t max1,
return max;
}
-static inline uint_fixed_16_16_t fixed_16_16_div_round_up(uint32_t val,
- uint32_t d)
+static inline uint_fixed_16_16_t fixed_16_16_div(uint32_t val, uint32_t d)
{
uint_fixed_16_16_t fp, res;
@@ -163,8 +162,7 @@ static inline uint_fixed_16_16_t
fixed_16_16_div_round_up(uint32_t val,
return res;
}
-static inline uint_fixed_16_16_t fixed_16_16_div_round_up_u64(uint32_t val,
- uint32_t d)
+static inline uint_fixed_16_16_t fixed_16_16_div_u64(uint32_t val, uint32_t d)
{
uint_fixed_16_16_t res;
uint64_t interm_val;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ef0e9f8d4dbd..d12bbe651dd5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4165,7 +4165,7 @@ static uint_fixed_16_16_t skl_wm_method1(uint32_t
pixel_rate, uint8_t cpp,
return FP_16_16_MAX;
wm_intermediate_val = latency * pixel_rate * cpp;
- ret = fixed_16_16_div_round_up_u64(wm_intermediate_val, 1000 * 512);
+ ret = fixed_16_16_div_u64(wm_intermediate_val, 1000 * 512);
return ret;
}
@@ -4301,8 +4301,8 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
if (y_tiled) {
interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line *
y_min_scanlines, 512);
- plane_blocks_per_line =
- fixed_16_16_div_round_up(interm_pbpl, y_min_scanlines);
+ plane_blocks_per_line = fixed_16_16_div(interm_pbpl,
+ y_min_scanlines);
} else if (x_tiled) {
interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512);
plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
--
2.11.0
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[Intel-gfx] [PATCH 02/12] drm/i915: Add more wrapper for fixed_point_16_16 operations
From: "Kumar, Mahesh"
This patch adds few wrapper to perform fixed_point_16_16 operations
mul_round_up_u32_fixed16 : Multiplies u32 and fixed_16_16_t variables
& returns u32 result with rounding-up.
mul_fixed16 : Multiplies two fixed_16_16_t variable & returns fixed_16_16
div_round_up_fixed16 : Perform division operation on fixed_16_16_t
variables & return u32 result with round-off
div_round_up_u32_fixed16 : devide uint32_t variable by fixed_16_16 variable
and round_up the result to uint32_t.
These wrappers will be used by later patches in the series.
Changes from V1:
- Rename wrapper as per Matt's comment
Changes from V2:
- Fix indentation
Signed-off-by: Mahesh Kumar
Reviewed-by: Matt Roper
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_drv.h | 43 +
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a6042013cd75..e9144634e720 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -153,6 +153,38 @@ static inline uint_fixed_16_16_t
max_fixed_16_16(uint_fixed_16_16_t max1,
return max;
}
+static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
+ uint_fixed_16_16_t d)
+{
+ return DIV_ROUND_UP(val.val, d.val);
+}
+
+static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
+ uint_fixed_16_16_t mul)
+{
+ uint64_t intermediate_val;
+ uint32_t result;
+
+ intermediate_val = (uint64_t) val * mul.val;
+ intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
+ WARN_ON(intermediate_val >> 32);
+ result = clamp_t(uint32_t, intermediate_val, 0, ~0);
+ return result;
+}
+
+static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
+uint_fixed_16_16_t mul)
+{
+ uint64_t intermediate_val;
+ uint_fixed_16_16_t fp;
+
+ intermediate_val = (uint64_t) val.val * mul.val;
+ intermediate_val = intermediate_val >> 16;
+ WARN_ON(intermediate_val >> 32);
+ fp.val = clamp_t(uint32_t, intermediate_val, 0, ~0);
+ return fp;
+}
+
static inline uint_fixed_16_16_t fixed_16_16_div(uint32_t val, uint32_t d)
{
uint_fixed_16_16_t fp, res;
@@ -175,6 +207,17 @@ static inline uint_fixed_16_16_t
fixed_16_16_div_u64(uint32_t val, uint32_t d)
return res;
}
+static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
+ uint_fixed_16_16_t d)
+{
+ uint64_t interm_val;
+
+ interm_val = (uint64_t)val << 16;
+ interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
+ WARN_ON(interm_val >> 32);
+ return clamp_t(uint32_t, interm_val, 0, ~0);
+}
+
static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
uint_fixed_16_16_t mul)
{
--
2.11.0
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[Intel-gfx] [PATCH 04/12] drm/i915/skl+: calculate pixel_rate & relative_data_rate in fixed point
From: "Kumar, Mahesh"
This patch make changes to calculate adjusted plane pixel rate &
plane downscale amount using fixed_point functions available.
This patch will give uniformity in code, & will help to avoid mixing of
32bit uint32_t variable for fixed-16.16 with fixed_16_16_t variables in
later patch in the series.
Changes from V1:
- Rebase based on wrapper name change
- Remove unnecessary comment
Signed-off-by: Mahesh Kumar
Reviewed-by: Matt Roper
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_pm.c | 38 +++---
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8ff8cc59dcca..ab056952cfa4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3827,26 +3827,27 @@ void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv,
* Return value is provided in 16.16 fixed point form to retain fractional
part.
* Caller should take care of dividing & rounding off the value.
*/
-static uint32_t
+static uint_fixed_16_16_t
skl_plane_downscale_amount(const struct intel_crtc_state *cstate,
const struct intel_plane_state *pstate)
{
struct intel_plane *plane = to_intel_plane(pstate->base.plane);
- uint32_t downscale_h, downscale_w;
uint32_t src_w, src_h, dst_w, dst_h;
+ uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
+ uint_fixed_16_16_t downscale_h, downscale_w;
if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
- return DRM_PLANE_HELPER_NO_SCALING;
+ return u32_to_fixed_16_16(0);
/* n.b., src is 16.16 fixed point, dst is whole integer */
if (plane->id == PLANE_CURSOR) {
- src_w = pstate->base.src_w;
- src_h = pstate->base.src_h;
+ src_w = pstate->base.src_w >> 16;
+ src_h = pstate->base.src_h >> 16;
dst_w = pstate->base.crtc_w;
dst_h = pstate->base.crtc_h;
} else {
- src_w = drm_rect_width(&pstate->base.src);
- src_h = drm_rect_height(&pstate->base.src);
+ src_w = drm_rect_width(&pstate->base.src) >> 16;
+ src_h = drm_rect_height(&pstate->base.src) >> 16;
dst_w = drm_rect_width(&pstate->base.dst);
dst_h = drm_rect_height(&pstate->base.dst);
}
@@ -3854,11 +3855,12 @@ skl_plane_downscale_amount(const struct
intel_crtc_state *cstate,
if (drm_rotation_90_or_270(pstate->base.rotation))
swap(dst_w, dst_h);
- downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
- downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
+ fp_w_ratio = fixed_16_16_div(src_w, dst_w);
+ fp_h_ratio = fixed_16_16_div(src_h, dst_h);
+ downscale_w = max_fixed_16_16(fp_w_ratio, u32_to_fixed_16_16(1));
+ downscale_h = max_fixed_16_16(fp_h_ratio, u32_to_fixed_16_16(1));
- /* Provide result in 16.16 fixed point */
- return (uint64_t)downscale_w * downscale_h >> 16;
+ return mul_fixed16(downscale_w, downscale_h);
}
static unsigned int
@@ -3868,10 +3870,11 @@ skl_plane_relative_data_rate(const struct
intel_crtc_state *cstate,
{
struct intel_plane *plane = to_intel_plane(pstate->plane);
struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
- uint32_t down_scale_amount, data_rate;
+ uint32_t data_rate;
uint32_t width = 0, height = 0;
struct drm_framebuffer *fb;
u32 format;
+ uint_fixed_16_16_t down_scale_amount;
if (!intel_pstate->base.visible)
return 0;
@@ -3905,7 +3908,7 @@ skl_plane_relative_data_rate(const struct
intel_crtc_state *cstate,
down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
- return (uint64_t)data_rate * down_scale_amount >> 16;
+ return mul_round_up_u32_fixed16(data_rate, down_scale_amount);
}
/*
@@ -4191,8 +4194,7 @@ static uint32_t skl_adjusted_plane_pixel_rate(const
struct intel_crtc_state *cst
struct intel_plane_state *pstate)
{
uint64_t adjusted_pixel_rate;
- uint64_t downscale_amount;
- uint64_t pixel_rate;
+ uint_fixed_16_16_t downscale_amount;
/* Shouldn't reach here on disabled planes... */
if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
@@ -4205,10 +4207,8 @@ static uint32_t skl_adjusted_plane_pixel_rate(const
struct intel_crtc_state *cst
adjusted_pixel_rate = cstate->pixel_rate;
downscale_amount = skl_plane_downscale_amount(cstate, pstate);
- pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
- WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
-
- return pixel_rate;
+ return mul_round_up_u32_fixed16(adjusted_pixel_rate,
[Intel-gfx] [PATCH 03/12] drm/i915: Use fixed_16_16 wrapper for division operation
From: "Kumar, Mahesh"
Don't use fixed_16_16 structure members directly, instead use wrapper to
perform fixed_16_16 division operation.
Signed-off-by: Mahesh Kumar
Reviewed-by: Matt Roper
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d12bbe651dd5..8ff8cc59dcca 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4334,8 +4334,8 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
}
res_blocks = fixed_16_16_to_u32_round_up(selected_result) + 1;
- res_lines = DIV_ROUND_UP(selected_result.val,
-plane_blocks_per_line.val);
+ res_lines = div_round_up_fixed16(selected_result,
+plane_blocks_per_line);
if (level >= 1 && level <= 7) {
if (y_tiled) {
--
2.11.0
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[Intel-gfx] [PATCH 06/12] drm/i915/skl+: no need to memset again
From: "Kumar, Mahesh"
We are already doing memset of ddb structure at the begining of
skl_allocate_pipe_ddb
function, No need to again do a memset.
Signed-off-by: Mahesh Kumar
Reviewed-by: Matt Roper
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_pm.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f494af358874..37dd3e7108c9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4072,10 +4072,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
alloc_size = skl_ddb_entry_size(alloc);
- if (alloc_size == 0) {
- memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
+ if (alloc_size == 0)
return 0;
- }
skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
--
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[Intel-gfx] [PATCH 05/12] drm/i915/skl: Fail the flip if no FB for WM calculation
From: "Kumar, Mahesh" Fail the flip if no FB is present but plane_state is set as visible. Above is not a valid combination so instead of continue fail the flip. Signed-off-by: Mahesh Kumar Reviewed-by: Matt Roper Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_pm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ab056952cfa4..f494af358874 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4408,7 +4408,8 @@ skl_compute_wm_level(const struct drm_i915_private *dev_priv, if (!intel_pstate) intel_pstate = to_intel_plane_state(plane->state); - WARN_ON(!intel_pstate->base.fb); + if (WARN_ON(!intel_pstate->base.fb)) + return -EINVAL; ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]); -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/12] drm/i915/skl+: Fail the flip if ddb min requirement exceeds pipe allocation
From: "Kumar, Mahesh"
DDB minimum requirement of crtc configuration (cumulative of all the
enabled planes in crtc) may exceed the allocated DDB for crtc/pipe.
This patch make changes to fail the flip/ioctl if minimum requirement
for pipe exceeds the total ddb allocated to the pipe.
Previously it succeeded but making alloc_size a negative value. Which
will make subsequent calculations for plane ddb allocation bogus & may
lead to screen corruption or system hang.
Changes from V1:
- Improve commit message as per Ander's comment
- Remove extra parentheses (Ander)
Signed-off-by: Mahesh Kumar
Reviewed-by: Matt Roper
Reviewed-by: Ander Conselvan de Oliveira
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_pm.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 37dd3e7108c9..bbc72069ab57 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4057,6 +4057,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
int num_active;
unsigned plane_data_rate[I915_MAX_PLANES] = {};
unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
+ uint16_t total_min_blocks = 0;
/* Clear the partitioning for disabled planes. */
memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
@@ -4084,10 +4085,18 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
*/
for_each_plane_id_on_crtc(intel_crtc, plane_id) {
- alloc_size -= minimum[plane_id];
- alloc_size -= y_minimum[plane_id];
+ total_min_blocks += minimum[plane_id];
+ total_min_blocks += y_minimum[plane_id];
}
+ if (total_min_blocks > alloc_size) {
+ DRM_DEBUG_KMS("Requested display configuration exceeds system
DDB limitations");
+ DRM_DEBUG_KMS("minimum required %d/%d\n", total_min_blocks,
+ alloc_size);
+ return -EINVAL;
+ }
+
+ alloc_size -= total_min_blocks;
ddb->plane[pipe][PLANE_CURSOR].start = alloc->end -
minimum[PLANE_CURSOR];
ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
--
2.11.0
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[Intel-gfx] [PATCH 09/12] drm/i915/skl+: Perform wm level calculations in separate function
From: "Kumar, Mahesh"
Instead of iterating over planes & wm levels in a single function use
skl_compute_wm_level function to interate over WM levels.
Change name of function to skl_compute_wm_levels (Matt).
These changes are to clean-up WM code & will help in making only new
ddb algorithm related changes in later patch in series.
Signed-off-by: Mahesh Kumar
Reviewed-by: Matt Roper
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_pm.c | 48 -
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c24a4e1bcb8b..0f1d9f672e83 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4382,18 +4382,18 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
}
static int
-skl_compute_wm_level(const struct drm_i915_private *dev_priv,
-struct skl_ddb_allocation *ddb,
-struct intel_crtc_state *cstate,
-const struct intel_plane_state *intel_pstate,
-int level,
-struct skl_wm_level *result)
+skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
+ struct skl_ddb_allocation *ddb,
+ struct intel_crtc_state *cstate,
+ const struct intel_plane_state *intel_pstate,
+ struct skl_plane_wm *wm)
{
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_plane *plane = intel_pstate->base.plane;
struct intel_plane *intel_plane = to_intel_plane(plane);
uint16_t ddb_blocks;
enum pipe pipe = intel_crtc->pipe;
+ int level, max_level = ilk_wm_max_level(dev_priv);
int ret;
if (WARN_ON(!intel_pstate->base.fb))
@@ -4401,16 +4401,20 @@ skl_compute_wm_level(const struct drm_i915_private
*dev_priv,
ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
- ret = skl_compute_plane_wm(dev_priv,
- cstate,
- intel_pstate,
- ddb_blocks,
- level,
- &result->plane_res_b,
- &result->plane_res_l,
- &result->plane_en);
- if (ret)
- return ret;
+ for (level = 0; level <= max_level; level++) {
+ struct skl_wm_level *result = &wm->wm[level];
+
+ ret = skl_compute_plane_wm(dev_priv,
+ cstate,
+ intel_pstate,
+ ddb_blocks,
+ level,
+ &result->plane_res_b,
+ &result->plane_res_l,
+ &result->plane_en);
+ if (ret)
+ return ret;
+ }
return 0;
}
@@ -4461,7 +4465,6 @@ static int skl_build_pipe_wm(struct intel_crtc_state
*cstate,
struct drm_plane *plane;
const struct drm_plane_state *pstate;
struct skl_plane_wm *wm;
- int level, max_level = ilk_wm_max_level(dev_priv);
int ret;
/*
@@ -4477,13 +4480,10 @@ static int skl_build_pipe_wm(struct intel_crtc_state
*cstate,
wm = &pipe_wm->planes[plane_id];
- for (level = 0; level <= max_level; level++) {
- ret = skl_compute_wm_level(dev_priv, ddb, cstate,
- intel_pstate, level,
- &wm->wm[level]);
- if (ret)
- return ret;
- }
+ ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
+ intel_pstate, wm);
+ if (ret)
+ return ret;
skl_compute_transition_wm(cstate, &wm->trans_wm);
}
pipe_wm->linetime = skl_compute_linetime_wm(cstate);
--
2.11.0
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[Intel-gfx] [PATCH 08/12] drm/i915/skl+: Watermark calculation cleanup
From: "Kumar, Mahesh"
This patch cleanup/reorganises the watermark calculation functions.
This patch make use of already available macro
"drm_atomic_crtc_state_for_each_plane_state" to walk through
plane_state list instead of calculating plane_state in function itself.
This restructuring will help later patch for new DDB allocation
algorithm to do only algo related changes.
Changes from V1:
- split the patch in two parts as per Matt's comment
Signed-off-by: Mahesh Kumar
Reviewed-by: Matt Roper
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_pm.c | 53 +++--
1 file changed, 19 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bbc72069ab57..c24a4e1bcb8b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4197,8 +4197,9 @@ static uint_fixed_16_16_t skl_wm_method2(uint32_t
pixel_rate,
return ret;
}
-static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state
*cstate,
- struct intel_plane_state *pstate)
+static uint32_t
+skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
+ const struct intel_plane_state *pstate)
{
uint64_t adjusted_pixel_rate;
uint_fixed_16_16_t downscale_amount;
@@ -4220,7 +4221,7 @@ static uint32_t skl_adjusted_plane_pixel_rate(const
struct intel_crtc_state *cst
static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
- struct intel_plane_state *intel_pstate,
+ const struct intel_plane_state *intel_pstate,
uint16_t ddb_allocation,
int level,
uint16_t *out_blocks, /* out */
@@ -4228,8 +4229,8 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
bool *enabled /* out */)
{
struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
- struct drm_plane_state *pstate = &intel_pstate->base;
- struct drm_framebuffer *fb = pstate->fb;
+ const struct drm_plane_state *pstate = &intel_pstate->base;
+ const struct drm_framebuffer *fb = pstate->fb;
uint32_t latency = dev_priv->wm.skl_latency[level];
uint_fixed_16_16_t method1, method2;
uint_fixed_16_16_t plane_blocks_per_line;
@@ -4384,37 +4385,17 @@ static int
skl_compute_wm_level(const struct drm_i915_private *dev_priv,
struct skl_ddb_allocation *ddb,
struct intel_crtc_state *cstate,
-struct intel_plane *intel_plane,
+const struct intel_plane_state *intel_pstate,
int level,
struct skl_wm_level *result)
{
- struct drm_atomic_state *state = cstate->base.state;
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
- struct drm_plane *plane = &intel_plane->base;
- struct intel_plane_state *intel_pstate = NULL;
+ struct drm_plane *plane = intel_pstate->base.plane;
+ struct intel_plane *intel_plane = to_intel_plane(plane);
uint16_t ddb_blocks;
enum pipe pipe = intel_crtc->pipe;
int ret;
- if (state)
- intel_pstate =
- intel_atomic_get_existing_plane_state(state,
- intel_plane);
-
- /*
-* Note: If we start supporting multiple pending atomic commits against
-* the same planes/CRTC's in the future, plane->state will no longer be
-* the correct pre-state to use for the calculations here and we'll
-* need to change where we get the 'unchanged' plane data from.
-*
-* For now this is fine because we only allow one queued commit against
-* a CRTC. Even if the plane isn't modified by this transaction and we
-* don't have a plane lock, we still have the CRTC's lock, so we know
-* that no other transactions are racing with us to update it.
-*/
- if (!intel_pstate)
- intel_pstate = to_intel_plane_state(plane->state);
-
if (WARN_ON(!intel_pstate->base.fb))
return -EINVAL;
@@ -4475,8 +4456,10 @@ static int skl_build_pipe_wm(struct intel_crtc_state
*cstate,
struct skl_pipe_wm *pipe_wm)
{
struct drm_device *dev = cstate->base.crtc->dev;
+ struct drm_crtc_state *crtc_state = &cstate->base;
const struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_plane *intel_plane;
+ struct drm_plane *plane;
+ const struct drm_plane_state *pstate;
struct skl_plane_wm *wm;
int level, max_level = ilk_wm_max_level(dev_p
[Intel-gfx] [PATCH 10/12] drm/i915/skl+: use linetime latency if ddb size is not available
From: "Kumar, Mahesh"
This patch make changes to use linetime latency if allocated
DDB size during plane watermark calculation is not available.
linetime is the time, display engine takes to fetch one line worth of
pixels with given pixel clock rate.
This is required to implement new DDB allocation algorithm.
In New Algorithm DDB is allocated based on WM values, because of which
number of DDB blocks will not be available during WM calculation,
So this "linetime latency" is suggested by SV/HW team to be used during
switch-case for WM blocks selection.
linetime latency us = pipe horizontal total pixels/adjusted pixel rate MHz
Changes since v1:
- Rebase on top of Paulo's patch series
Changes since v2:
- Fix if-else condition (pointed by Maarten)
Changes since v3:
- Use common function for timetime_us calculation (Paulo)
- rebase on drm-tip
Changes since v4:
- Use consistent name for fixed_point operation
Changes since v5:
- Improve commit message
- rename skl_get_linetime_us to intel_get_linetime_us
- fix watermark result selection (Matt)
Signed-off-by: "Mahesh Kumar"
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++
drivers/gpu/drm/i915/intel_pm.c | 42 -
2 files changed, 40 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e9144634e720..0100100fdaf9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -115,6 +115,13 @@ typedef struct {
fp; \
})
+static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
+{
+ if (val.val == 0)
+ return true;
+ return false;
+}
+
static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
{
uint_fixed_16_16_t fp;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0f1d9f672e83..936eef1634c7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4197,6 +4197,27 @@ static uint_fixed_16_16_t skl_wm_method2(uint32_t
pixel_rate,
return ret;
}
+static uint_fixed_16_16_t
+intel_get_linetime_us(struct intel_crtc_state *cstate)
+{
+ uint32_t pixel_rate;
+ uint32_t crtc_htotal;
+ uint_fixed_16_16_t linetime_us;
+
+ if (!cstate->base.active)
+ return u32_to_fixed_16_16(0);
+
+ pixel_rate = cstate->pixel_rate;
+
+ if (WARN_ON(pixel_rate == 0))
+ return u32_to_fixed_16_16(0);
+
+ crtc_htotal = cstate->base.adjusted_mode.crtc_htotal;
+ linetime_us = fixed_16_16_div_u64(crtc_htotal * 1000, pixel_rate);
+
+ return linetime_us;
+}
+
static uint32_t
skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
const struct intel_plane_state *pstate)
@@ -4331,12 +4352,18 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
if (y_tiled) {
selected_result = max_fixed_16_16(method2, y_tile_minimum);
} else {
+ uint32_t linetime_us;
+
+ linetime_us = fixed_16_16_to_u32_round_up(
+ intel_get_linetime_us(cstate));
if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
(plane_bytes_per_line / 512 < 1))
selected_result = method2;
- else if ((ddb_allocation /
+ else if ((ddb_allocation && ddb_allocation /
fixed_16_16_to_u32_round_up(plane_blocks_per_line)) >=
1)
selected_result = min_fixed_16_16(method1, method2);
+ else if (latency >= linetime_us)
+ selected_result = min_fixed_16_16(method1, method2);
else
selected_result = method1;
}
@@ -4424,19 +4451,16 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate)
{
struct drm_atomic_state *state = cstate->base.state;
struct drm_i915_private *dev_priv = to_i915(state->dev);
- uint32_t pixel_rate;
+ uint_fixed_16_16_t linetime_us;
uint32_t linetime_wm;
- if (!cstate->base.active)
- return 0;
+ linetime_us = intel_get_linetime_us(cstate);
- pixel_rate = cstate->pixel_rate;
-
- if (WARN_ON(pixel_rate == 0))
+ if (is_fixed16_zero(linetime_us))
return 0;
- linetime_wm = DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal *
- 1000, pixel_rate);
+ linetime_wm = fixed_16_16_to_u32_round_up(mul_u32_fixed_16_16(8,
+ linetime_us));
/* Display WA #1135: bxt. */
if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled)
--
2.11.0
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[Intel-gfx] [PATCH 11/12] drm/i915/skl: New ddb allocation algorithm
From: "Kumar, Mahesh"
This patch implements new DDB allocation algorithm as per HW team
recommendation. This algo takecare of scenario where we allocate less DDB
for the planes with lower relative pixel rate, but they require more DDB
to work.
It also takes care of enabling same watermark level for each
plane in crtc, for efficient power saving.
Changes since v1:
- Rebase on top of Paulo's patch series
Changes since v2:
- Fix the for loop condition to enable WM
Changes since v3:
- Fix crash in cursor i-g-t reported by Maarten
- Rebase after addressing Paulo's comments
- Few other ULT fixes
Changes since v4:
- Rebase on drm-tip
- Added separate function to enable WM levels
Changes since v5:
- Fix a crash identified in skl-6770HQ system
Changes since v6:
- Address review comments from Matt
Signed-off-by: Mahesh Kumar
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_pm.c | 255
1 file changed, 155 insertions(+), 100 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 936eef1634c7..ade06d3f6bdc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4039,13 +4039,41 @@ skl_ddb_calc_min(const struct intel_crtc_state *cstate,
int num_active,
minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
}
+static void
+skl_enable_plane_wm_levels(const struct drm_i915_private *dev_priv,
+ uint16_t plane_ddb,
+ uint16_t max_level,
+ struct skl_plane_wm *wm)
+{
+ int level;
+ /*
+* Now enable all levels in WM structure which can be enabled
+* using current DDB allocation
+*/
+ for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
+ struct skl_wm_level *level_wm = &wm->wm[level];
+
+ if (level > max_level || level_wm->plane_res_b == 0
+ || level_wm->plane_res_l >= 31
+ || level_wm->plane_res_b >= plane_ddb) {
+ level_wm->plane_en = false;
+ level_wm->plane_res_b = 0;
+ level_wm->plane_res_l = 0;
+ } else {
+ level_wm->plane_en = true;
+ }
+ }
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
+ struct skl_pipe_wm *pipe_wm,
struct skl_ddb_allocation *ddb /* out */)
{
struct drm_atomic_state *state = cstate->base.state;
struct drm_crtc *crtc = cstate->base.crtc;
struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum pipe pipe = intel_crtc->pipe;
struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
@@ -4058,6 +4086,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
unsigned plane_data_rate[I915_MAX_PLANES] = {};
unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
uint16_t total_min_blocks = 0;
+ uint16_t total_level_ddb;
+ int max_level, level;
/* Clear the partitioning for disabled planes. */
memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
@@ -4096,10 +4126,48 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
return -EINVAL;
}
- alloc_size -= total_min_blocks;
- ddb->plane[pipe][PLANE_CURSOR].start = alloc->end -
minimum[PLANE_CURSOR];
+ alloc_size -= minimum[PLANE_CURSOR];
+ ddb->plane[pipe][PLANE_CURSOR].start = alloc->end -
+ minimum[PLANE_CURSOR];
ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
+ for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
+ total_level_ddb = 0;
+ for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+ /*
+* TODO: We should calculate watermark values for Y/UV
+* plane both in case of NV12 format and use both values
+* for ddb calculation. NV12 is disabled as of now, So
+* using only single/UV plane value here.
+*/
+ struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
+ uint16_t plane_res_b = wm->wm[level].plane_res_b;
+ uint16_t min = minimum[plane_id] + y_minimum[plane_id];
+
+ if (plane_id == PLANE_CURSOR)
+ continue;
+
+ total_level_ddb += max(plane_res_b, min);
+ }
+
+ /*
+* If This this level can successfully be enabled with the
+* pipe's current DDB allocation, then all lower levels are
+* guaranteed
[Intel-gfx] [PATCH 12/12] drm/i915/skl+: consider max supported plane pixel rate while scaling
From: "Kumar, Mahesh"
A display resolution is only supported if it meets all the restrictions
below for Maximum Pipe Pixel Rate.
The display resolution must fit within the maximum pixel rate output
from the pipe. Make sure that the display pipe is able to feed pixels at
a rate required to support the desired resolution.
For each enabled plane on the pipe {
If plane scaling enabled {
Horizontal down scale amount = Maximum[1, plane horizontal size /
scaler horizontal window size]
Vertical down scale amount = Maximum[1, plane vertical size /
scaler vertical window size]
Plane down scale amount = Horizontal down scale amount *
Vertical down scale amount
Plane Ratio = 1 / Plane down scale amount
}
Else {
Plane Ratio = 1
}
If plane source pixel format is 64 bits per pixel {
Plane Ratio = Plane Ratio * 8/9
}
}
Pipe Ratio = Minimum Plane Ratio of all enabled planes on the pipe
If pipe scaling is enabled {
Horizontal down scale amount = Maximum[1, pipe horizontal source size /
scaler horizontal window size]
Vertical down scale amount = Maximum[1, pipe vertical source size /
scaler vertical window size]
Note: The progressive fetch - interlace display mode is equivalent to a
2.0 vertical down scale
Pipe down scale amount = Horizontal down scale amount *
Vertical down scale amount
Pipe Ratio = Pipe Ratio / Pipe down scale amount
}
Pipe maximum pixel rate = CDCLK frequency * Pipe Ratio
In this patch our calculation is based on pipe downscale amount
(plane max downscale amount * pipe downscale amount) instead of Pipe
Ratio. So,
max supported crtc clock with given scaling = CDCLK / pipe downscale.
Flip will fail if,
current crtc clock > max supported crct clock with given scaling.
Changes since V1:
- separate out fixed_16_16 wrapper API definition
Changes since V2:
- Fix buggy crtc !active condition (Maarten)
- use intel_wm_plane_visible wrapper as per Maarten's suggestion
Changes since V3:
- Change failure return from ERANGE to EINVAL
Changes since V4:
- Rebase based on previous patch changes
Changes since V5:
- return EINVAL instead of continue (Maarten)
Changes since V6:
- Improve commit message
- Address review comment
Signed-off-by: Mahesh Kumar
Reviewed-by: Matt Roper
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 3 ++
drivers/gpu/drm/i915/intel_drv.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 87
3 files changed, 92 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c1cbfcef1f89..2cc1d11d9e6c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11186,6 +11186,9 @@ static int intel_crtc_atomic_check(struct drm_crtc
*crtc,
ret = skl_update_scaler_crtc(pipe_config);
if (!ret)
+ ret = skl_check_pipe_max_pixel_rate(intel_crtc,
+ pipe_config);
+ if (!ret)
ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
pipe_config);
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bd500977b3fc..93afac4a83fa 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1885,6 +1885,8 @@ bool skl_ddb_allocation_overlaps(const struct
skl_ddb_entry **entries,
int ignore);
bool ilk_disable_lp_wm(struct drm_device *dev);
int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
+int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *cstate);
static inline int intel_enable_rc6(void)
{
return i915.enable_rc6;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ade06d3f6bdc..2c3f90c21e6c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3863,6 +3863,93 @@ skl_plane_downscale_amount(const struct intel_crtc_state
*cstate,
return mul_fixed16(downscale_w, downscale_h);
}
+static uint_fixed_16_16_t
+skl_pipe_downscale_amount(const struct intel_crtc_state *config)
+{
+ uint_fixed_16_16_t pipe_downscale = u32_to_fixed_16_16(1);
+
+ if (!config->base.active)
+ return pipe_downscale;
+
+ if (config->pch_pfit.enabled) {
+ uint32_t src_w, src_h, dst_w, dst_h;
+ uint32_t pfit_size = config->pch_pfit.size;
+ uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
+ uint_fixed_16_16_t downscale_h, downscale_w;
+
+ src_w = config->pipe_src_w;
+ sr
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Reorder media/render reset on g4x
On Tue, May 16, 2017 at 04:38:01PM +0300, Mika Kuoppala wrote: > Chris Wilson writes: > > > Ville found a reference to WaMediaResetBeforeFullReset which we presume > > means that we should simply do the media reset first. > > Yesterday I reordered the resets but I recall it didnt help. > I will retry but regardless yeah resetting media first makes > sense. > > > > > References: https://bugs.freedesktop.org/show_bug.cgi?id=100942 > > Suggested-by: Ville Syrjälä > > Signed-off-by: Chris Wilson > > Cc: Ville Syrjälä > > Cc: Mika Kuoppala > > --- > > drivers/gpu/drm/i915/intel_uncore.c | 12 ++-- > > 1 file changed, 6 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c > > b/drivers/gpu/drm/i915/intel_uncore.c > > index fc3da0a6fdbb..c3d0d81b50e4 100644 > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > @@ -1504,12 +1504,6 @@ static int g4x_do_reset(struct drm_i915_private > > *dev_priv, unsigned engine_mask) > > struct pci_dev *pdev = dev_priv->drm.pdev; > > int ret; > > > > - pci_write_config_byte(pdev, I915_GDRST, > > - GRDOM_RENDER | GRDOM_RESET_ENABLE); > > - ret = wait_for(g4x_reset_complete(pdev), 500); > > - if (ret) > > - goto out; > > - > > /* WaVcpClkGateDisableForMediaReset:ctg,elk */ > > I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | > > VCP_UNIT_CLOCK_GATE_DISABLE); > > POSTING_READ(VDECCLK_GATE_D); > > @@ -1517,11 +1511,17 @@ static int g4x_do_reset(struct drm_i915_private > > *dev_priv, unsigned engine_mask) > > pci_write_config_byte(pdev, I915_GDRST, > > GRDOM_MEDIA | GRDOM_RESET_ENABLE); > > ret = wait_for(g4x_reset_complete(pdev), 500); > > + if (ret) > > + goto out; > > > > We should restore the WaVcp... state if we fail. Not that it > was right to begin with. Did it right in the previous patch, then promptly undid it. I was thinking if we should just do the clock gate tweak for the whole function, it will look slightly easier to follow. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 01/12] drm/i915: Remove kref from i915_sw_fence
My original intention was for i915_sw_fence to be the base class and
provide the reference count for the container. This was from starting
with a design to handle async_work. In practice, for i915 we embed
fences into structs which have their own independent reference counting,
making the i915_sw_fence.kref duplicitous. If we remove the kref, we
remove the i915_sw_fence's ability to free itself and its independence,
it can only exist within a container and must be supplied with a
callback to handle its release.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_sw_fence.c | 55
drivers/gpu/drm/i915/i915_sw_fence.h | 1 -
2 files changed, 11 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c
b/drivers/gpu/drm/i915/i915_sw_fence.c
index a277f8eb7beb..a0a690d6627e 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -120,34 +120,6 @@ void i915_sw_fence_fini(struct i915_sw_fence *fence)
}
#endif
-static void i915_sw_fence_release(struct kref *kref)
-{
- struct i915_sw_fence *fence = container_of(kref, typeof(*fence), kref);
-
- WARN_ON(atomic_read(&fence->pending) > 0);
- debug_fence_destroy(fence);
-
- if (fence->flags & I915_SW_FENCE_MASK) {
- __i915_sw_fence_notify(fence, FENCE_FREE);
- } else {
- i915_sw_fence_fini(fence);
- kfree(fence);
- }
-}
-
-static void i915_sw_fence_put(struct i915_sw_fence *fence)
-{
- debug_fence_assert(fence);
- kref_put(&fence->kref, i915_sw_fence_release);
-}
-
-static struct i915_sw_fence *i915_sw_fence_get(struct i915_sw_fence *fence)
-{
- debug_fence_assert(fence);
- kref_get(&fence->kref);
- return fence;
-}
-
static void __i915_sw_fence_wake_up_all(struct i915_sw_fence *fence,
struct list_head *continuation)
{
@@ -202,13 +174,15 @@ static void __i915_sw_fence_complete(struct i915_sw_fence
*fence,
debug_fence_set_state(fence, DEBUG_FENCE_IDLE, DEBUG_FENCE_NOTIFY);
- if (fence->flags & I915_SW_FENCE_MASK &&
- __i915_sw_fence_notify(fence, FENCE_COMPLETE) != NOTIFY_DONE)
+ if (__i915_sw_fence_notify(fence, FENCE_COMPLETE) != NOTIFY_DONE)
return;
debug_fence_set_state(fence, DEBUG_FENCE_NOTIFY, DEBUG_FENCE_IDLE);
__i915_sw_fence_wake_up_all(fence, continuation);
+
+ debug_fence_destroy(fence);
+ __i915_sw_fence_notify(fence, FENCE_FREE);
}
static void i915_sw_fence_complete(struct i915_sw_fence *fence)
@@ -232,33 +206,26 @@ void __i915_sw_fence_init(struct i915_sw_fence *fence,
const char *name,
struct lock_class_key *key)
{
- BUG_ON((unsigned long)fn & ~I915_SW_FENCE_MASK);
+ BUG_ON(!fn || (unsigned long)fn & ~I915_SW_FENCE_MASK);
debug_fence_init(fence);
__init_waitqueue_head(&fence->wait, name, key);
- kref_init(&fence->kref);
atomic_set(&fence->pending, 1);
fence->flags = (unsigned long)fn;
}
-static void __i915_sw_fence_commit(struct i915_sw_fence *fence)
-{
- i915_sw_fence_complete(fence);
- i915_sw_fence_put(fence);
-}
-
void i915_sw_fence_commit(struct i915_sw_fence *fence)
{
debug_fence_activate(fence);
- __i915_sw_fence_commit(fence);
+ i915_sw_fence_complete(fence);
}
static int i915_sw_fence_wake(wait_queue_t *wq, unsigned mode, int flags, void
*key)
{
list_del(&wq->task_list);
__i915_sw_fence_complete(wq->private, key);
- i915_sw_fence_put(wq->private);
+
if (wq->flags & I915_SW_FENCE_FLAG_ALLOC)
kfree(wq);
return 0;
@@ -353,7 +320,7 @@ static int __i915_sw_fence_await_sw_fence(struct
i915_sw_fence *fence,
INIT_LIST_HEAD(&wq->task_list);
wq->flags = pending;
wq->func = i915_sw_fence_wake;
- wq->private = i915_sw_fence_get(fence);
+ wq->private = fence;
i915_sw_fence_await(fence);
@@ -402,7 +369,7 @@ static void timer_i915_sw_fence_wake(unsigned long data)
dma_fence_put(cb->dma);
cb->dma = NULL;
- __i915_sw_fence_commit(cb->fence);
+ i915_sw_fence_complete(cb->fence);
cb->timer.function = NULL;
}
@@ -413,7 +380,7 @@ static void dma_i915_sw_fence_wake(struct dma_fence *dma,
del_timer_sync(&cb->timer);
if (cb->timer.function)
- __i915_sw_fence_commit(cb->fence);
+ i915_sw_fence_complete(cb->fence);
dma_fence_put(cb->dma);
kfree(cb);
@@ -440,7 +407,7 @@ int i915_sw_fence_await_dma_fence(struct i915_sw_fence
*fence,
return dma_fence_wait(dma, false);
}
- cb->fence = i915_sw_fence_get(fence);
+ cb->fence = fence;
i915_sw_fence_await(fence);
cb->dma = NULL;
diff --git a/drivers/
[Intel-gfx] [CI 06/12] drm/i915: Don't mark an execlists context-switch when idle
If we *know* that the engine is idle, i.e. we have not more contexts in
flight, we can skip any spurious CSB idle interrupts. These spurious
interrupts seem to arrive long after we assert that the engines are
completely idle, triggering later assertions:
[ 178.896646] intel_engine_is_idle(bcs): interrupt not handled, irq_posted=2
[ 178.896655] [ cut here ]
[ 178.896658] kernel BUG at drivers/gpu/drm/i915/intel_engine_cs.c:226!
[ 178.896661] invalid opcode: [#1] SMP
[ 178.896663] Modules linked in: i915(E) x86_pkg_temp_thermal(E)
crct10dif_pclmul(E) crc32_pclmul(E) crc32c_intel(E) ghash_clmulni_intel(E)
nls_ascii(E) nls_cp437(E) vfat(E) fat(E) intel_gtt(E) i2c_algo_bit(E)
drm_kms_helper(E) syscopyarea(E) sysfillrect(E) sysimgblt(E) fb_sys_fops(E)
aesni_intel(E) prime_numbers(E) evdev(E) aes_x86_64(E) drm(E) crypto_simd(E)
cryptd(E) glue_helper(E) mei_me(E) mei(E) lpc_ich(E) efivars(E) mfd_core(E)
battery(E) video(E) acpi_pad(E) button(E) tpm_tis(E) tpm_tis_core(E) tpm(E)
autofs4(E) i2c_i801(E) fan(E) thermal(E) i2c_designware_platform(E)
i2c_designware_core(E)
[ 178.896694] CPU: 1 PID: 522 Comm: gem_exec_whispe Tainted: GE
4.11.0-rc5+ #14
[ 178.896702] task: 88040aba8d40 task.stack: c93f
[ 178.896722] RIP: 0010:intel_engine_init_global_seqno+0x1db/0x1f0 [i915]
[ 178.896725] RSP: 0018:c93f3ab0 EFLAGS: 00010246
[ 178.896728] RAX: RBX: 88040af54000 RCX:
[ 178.896731] RDX: 88041ec933e0 RSI: 88041ec8cc48 RDI: 88041ec8cc48
[ 178.896734] RBP: c93f3ac8 R08: R09: 047d
[ 178.896736] R10: 0040 R11: 88040b344f80 R12:
[ 178.896739] R13: 88040bce R14: 88040bce52d8 R15: 88040bce
[ 178.896742] FS: 7f22d8c0() GS:88041ec8()
knlGS:
[ 178.896746] CS: 0010 DS: ES: CR0: 80050033
[ 178.896749] CR2: 7f41ddd8f000 CR3: 00040bb03000 CR4: 001406e0
[ 178.896752] Call Trace:
[ 178.896768] reset_all_global_seqno.part.33+0x4e/0xd0 [i915]
[ 178.896782] i915_gem_request_alloc+0x304/0x330 [i915]
[ 178.896795] i915_gem_do_execbuffer+0x8a1/0x17d0 [i915]
[ 178.896799] ? remove_wait_queue+0x48/0x50
[ 178.896812] ? i915_wait_request+0x300/0x590 [i915]
[ 178.896816] ? wake_up_q+0x70/0x70
[ 178.896819] ? refcount_dec_and_test+0x11/0x20
[ 178.896823] ? reservation_object_add_excl_fence+0xa5/0x100
[ 178.896835] i915_gem_execbuffer2+0xab/0x1f0 [i915]
[ 178.896844] drm_ioctl+0x1e6/0x460 [drm]
[ 178.896858] ? i915_gem_execbuffer+0x260/0x260 [i915]
[ 178.896862] ? dput+0xcf/0x250
[ 178.896866] ? full_proxy_release+0x66/0x80
[ 178.896869] ? mntput+0x1f/0x30
[ 178.896872] do_vfs_ioctl+0x8f/0x5b0
[ 178.896875] ? fput+0x9/0x10
[ 178.896878] ? task_work_run+0x80/0xa0
[ 178.896881] SyS_ioctl+0x3c/0x70
[ 178.896885] entry_SYSCALL_64_fastpath+0x17/0x98
[ 178.896888] RIP: 0033:0x7f2ccb455ca7
[ 178.896890] RSP: 002b:7ffcabec72d8 EFLAGS: 0246 ORIG_RAX:
0010
[ 178.896894] RAX: ffda RBX: 55f897a44b90 RCX: 7f2ccb455ca7
[ 178.896897] RDX: 7ffcabec74a0 RSI: 40406469 RDI: 0003
[ 178.896900] RBP: 7f2ccb70a440 R08: 7f2ccb70d0a4 R09:
[ 178.896903] R10: R11: 0246 R12:
[ 178.896905] R13: 55f89782d71a R14: 7ffcabecf838 R15: 0003
[ 178.896908] Code: 00 31 d2 4c 89 ef 8d 70 48 41 ff 95 f8 06 00 00 e9 68 fe
ff ff be 0f 00 00 00 48 c7 c7 48 dc 37 a0 e8 fa 33 d6 e0 e9 0b ff ff ff <0f> 0b
0f 0b 0f 0b 0f 0b 0f 1f 00 66 2e 0f 1f 84 00 00 00 00 00
On the other hand, by ignoring the interrupt do we risk running out of
space in CSB ring? Testing for a few hours suggests not, i.e. that we
only seem to get the odd delayed CSB idle notification.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_irq.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9f5ae1e938be..927b408e6e95 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1323,8 +1323,10 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32
iir, int test_shift)
bool tasklet = false;
if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) {
- set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
- tasklet = true;
+ if (port_count(&engine->execlist_port[0])) {
+ set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
+ tasklet = true;
+ }
}
if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) {
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
h
[Intel-gfx] [CI 02/12] drm/i915: Import the kfence selftests for i915_sw_fence
A long time ago, I wrote some selftests for the struct kfence idea. Now
that we have infrastructure in i915/igt for running kselftests, include
some for i915_sw_fence.
v2: INIT_WORK_ONSTACK/destroy_work_on_stack (Mika)
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/Kconfig.debug | 12 +
drivers/gpu/drm/i915/i915_sw_fence.c | 7 +-
.../gpu/drm/i915/selftests/i915_mock_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/i915_sw_fence.c | 577 +
4 files changed, 596 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_sw_fence.c
diff --git a/drivers/gpu/drm/i915/Kconfig.debug
b/drivers/gpu/drm/i915/Kconfig.debug
index b00edd3b8800..78c5c049a347 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -61,6 +61,18 @@ config DRM_I915_SW_FENCE_DEBUG_OBJECTS
If in doubt, say "N".
+config DRM_I915_SW_FENCE_CHECK_DAG
+bool "Enable additional driver debugging for detecting dependency
cycles"
+depends on DRM_I915
+default n
+help
+ Choose this option to turn on extra driver debugging that may affect
+ performance but will catch some internal issues.
+
+ Recommended for driver developers only.
+
+ If in doubt, say "N".
+
config DRM_I915_SELFTEST
bool "Enable selftests upon driver load"
depends on DRM_I915
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c
b/drivers/gpu/drm/i915/i915_sw_fence.c
index a0a690d6627e..474d23c0c0ce 100644
--- a/drivers/gpu/drm/i915/i915_sw_fence.c
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -12,6 +12,7 @@
#include
#include "i915_sw_fence.h"
+#include "i915_selftest.h"
#define I915_SW_FENCE_FLAG_ALLOC BIT(3) /* after WQ_FLAG_* for safety */
@@ -274,7 +275,7 @@ static bool i915_sw_fence_check_if_after(struct
i915_sw_fence *fence,
unsigned long flags;
bool err;
- if (!IS_ENABLED(CONFIG_I915_SW_FENCE_CHECK_DAG))
+ if (!IS_ENABLED(CONFIG_DRM_I915_SW_FENCE_CHECK_DAG))
return false;
spin_lock_irqsave(&i915_sw_fence_lock, flags);
@@ -490,3 +491,7 @@ int i915_sw_fence_await_reservation(struct i915_sw_fence
*fence,
return ret;
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftests/i915_sw_fence.c"
+#endif
diff --git a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
index 76c1f149a0a0..fc74687501ba 100644
--- a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
@@ -9,6 +9,7 @@
* Tests are executed in order by igt/drv_selftest
*/
selftest(sanitycheck, i915_mock_sanitycheck) /* keep first (igt selfcheck) */
+selftest(fence, i915_sw_fence_mock_selftests)
selftest(scatterlist, scatterlist_mock_selftests)
selftest(syncmap, i915_syncmap_mock_selftests)
selftest(uncore, intel_uncore_mock_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_sw_fence.c
b/drivers/gpu/drm/i915/selftests/i915_sw_fence.c
new file mode 100644
index ..98baf10c28c6
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/i915_sw_fence.c
@@ -0,0 +1,577 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include
+
+#include "../i915_selftest.h"
+
+static int __i915_sw_fence_call
+fence_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
+{
+ switch (state) {
+ case FENCE_COMPLETE:
+ break;
+
+ case FENCE_FREE:
+ /* Leave the fence for the caller to free it after testing */
+ break;
+ }
+
+ return NOTIFY_DONE;
+}
+
+static struct i915_sw_fence *alloc_fence(void)
+{
+ struct i915_sw_fence *fence;
+
+ fence = kmalloc(si
[Intel-gfx] [CI 04/12] drm/i915: Redefine ptr_pack_bits() and friends
Rebrand the current (pointer | bits) pack/unpack utility macros as
explicit bit twiddling for PAGE_SIZE so that we can use the more
flexible underlying macros for different bits.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c| 6 +++---
drivers/gpu/drm/i915/i915_utils.h | 19 +--
3 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 2a1a3347495a..f0cb22cc0dd6 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -1284,7 +1284,7 @@ int intel_engine_cmd_parser(struct intel_engine_cs
*engine,
if (*cmd == MI_BATCH_BUFFER_END) {
if (needs_clflush_after) {
- void *ptr =
ptr_mask_bits(shadow_batch_obj->mm.mapping);
+ void *ptr =
page_mask_bits(shadow_batch_obj->mm.mapping);
drm_clflush_virt_range(ptr,
(void *)(cmd + 1) - ptr);
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8dbd302be36a..ffd20dc71ba9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2280,7 +2280,7 @@ void __i915_gem_object_put_pages(struct
drm_i915_gem_object *obj,
if (obj->mm.mapping) {
void *ptr;
- ptr = ptr_mask_bits(obj->mm.mapping);
+ ptr = page_mask_bits(obj->mm.mapping);
if (is_vmalloc_addr(ptr))
vunmap(ptr);
else
@@ -2612,7 +2612,7 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj,
}
GEM_BUG_ON(!obj->mm.pages);
- ptr = ptr_unpack_bits(obj->mm.mapping, &has_type);
+ ptr = page_unpack_bits(obj->mm.mapping, &has_type);
if (ptr && has_type != type) {
if (pinned) {
ret = -EBUSY;
@@ -2634,7 +2634,7 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj,
goto err_unpin;
}
- obj->mm.mapping = ptr_pack_bits(ptr, type);
+ obj->mm.mapping = page_pack_bits(ptr, type);
}
out_unlock:
diff --git a/drivers/gpu/drm/i915/i915_utils.h
b/drivers/gpu/drm/i915/i915_utils.h
index 18630d8f4be8..d9df23795f9a 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -70,20 +70,27 @@
#define overflows_type(x, T) \
(sizeof(x) > sizeof(T) && (x) >> (sizeof(T) * BITS_PER_BYTE))
-#define ptr_mask_bits(ptr) ({ \
+#define ptr_mask_bits(ptr, n) ({ \
unsigned long __v = (unsigned long)(ptr); \
- (typeof(ptr))(__v & PAGE_MASK); \
+ (typeof(ptr))(__v & -BIT(n)); \
})
-#define ptr_unpack_bits(ptr, bits) ({ \
+#define ptr_unmask_bits(ptr, n) ((unsigned long)(ptr) & (BIT(n) - 1))
+
+#define ptr_unpack_bits(ptr, bits, n) ({ \
unsigned long __v = (unsigned long)(ptr); \
- *(bits) = __v & ~PAGE_MASK; \
- (typeof(ptr))(__v & PAGE_MASK); \
+ *(bits) = __v & (BIT(n) - 1); \
+ (typeof(ptr))(__v & -BIT(n)); \
})
-#define ptr_pack_bits(ptr, bits) \
+#define ptr_pack_bits(ptr, bits, n)\
((typeof(ptr))((unsigned long)(ptr) | (bits)))
+#define page_mask_bits(ptr) ptr_mask_bits(ptr, PAGE_SHIFT)
+#define page_unmask_bits(ptr) ptr_unmask_bits(ptr, PAGE_SHIFT)
+#define page_pack_bits(ptr, bits) ptr_pack_bits(ptr, bits, PAGE_SHIFT)
+#define page_unpack_bits(ptr, bits) ptr_unpack_bits(ptr, bits, PAGE_SHIFT)
+
#define ptr_offset(ptr, member) offsetof(typeof(*(ptr)), member)
#define fetch_and_zero(ptr) ({ \
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 05/12] drm/i915/execlists: Pack the count into the low bits of the port.request
add/remove: 1/1 grow/shrink: 5/4 up/down: 391/-578 (-187)
function old new delta
execlists_submit_ports 262 471+209
port_assign.isra - 136+136
capture 63446359 +15
reset_common_ring438 452 +14
execlists_submit_request 228 238 +10
gen8_init_common_ring334 341 +7
intel_engine_is_idle 106 105 -1
i915_engine_info23142290 -24
__i915_gem_set_wedged_BKL485 411 -74
intel_lrc_irq_handler 17891604-185
execlists_update_context 294 --294
The most important change there is the improve to the
intel_lrc_irq_handler and excclist_submit_ports (net improvement since
execlists_update_context is now inlined).
v2: Use the port_api() for guc as well (even though currently we do not
pack any counters in there, yet) and hide all port->request_count inside
the helpers.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c| 32
drivers/gpu/drm/i915/i915_gem.c| 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 13 +++-
drivers/gpu/drm/i915/i915_guc_submission.c | 34 +---
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 121 -
drivers/gpu/drm/i915/intel_ringbuffer.h| 11 ++-
7 files changed, 126 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 76abff186d01..e08ac708e547 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3353,6 +3353,7 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
if (i915.enable_execlists) {
u32 ptr, read, write;
struct rb_node *rb;
+ unsigned int idx;
seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
I915_READ(RING_EXECLIST_STATUS_LO(engine)),
@@ -3370,8 +3371,7 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
if (read > write)
write += GEN8_CSB_ENTRIES;
while (read < write) {
- unsigned int idx = ++read % GEN8_CSB_ENTRIES;
-
+ idx = ++read % GEN8_CSB_ENTRIES;
seq_printf(m, "\tExeclist CSB[%d]: 0x%08x,
context: %d\n",
idx,
I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
@@ -3379,21 +3379,19 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
}
rcu_read_lock();
- rq = READ_ONCE(engine->execlist_port[0].request);
- if (rq) {
- seq_printf(m, "\t\tELSP[0] count=%d, ",
- engine->execlist_port[0].count);
- print_request(m, rq, "rq: ");
- } else {
- seq_printf(m, "\t\tELSP[0] idle\n");
- }
- rq = READ_ONCE(engine->execlist_port[1].request);
- if (rq) {
- seq_printf(m, "\t\tELSP[1] count=%d, ",
- engine->execlist_port[1].count);
- print_request(m, rq, "rq: ");
- } else {
- seq_printf(m, "\t\tELSP[1] idle\n");
+ for (idx = 0; idx < ARRAY_SIZE(engine->execlist_port);
idx++) {
+ unsigned int count;
+
+ rq = port_unpack(&engine->execlist_port[idx],
+&count);
+ if (rq) {
+ seq_printf(m, "\t\tELSP[%d] count=%d, ",
+ idx, count);
+ print_request(m, rq, "rq: ");
+ } else {
+ seq_printf(m, "\t\tELSP[%d] idle\n",
+ idx);
+ }
}
rcu_read_unlock();
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ffd20dc71ba9..83518cdb19f3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/
[Intel-gfx] [CI 03/12] drm/i915: Make ptr_unpack_bits() more function-like
ptr_unpack_bits() is a function-like macro, as such it is meant to be
replaceable by a function. In this case, we should be passing in the
out-param as a pointer.
Bizarrely this does affect code generation:
function old new delta
i915_gem_object_pin_map 409 389 -20
An improvement(?) in this case, but one can't help wonder what
strict-aliasing optimisations we are preventing.
The generated code looks identical in using ptr_unpack_bits (no extra
motions to stack, the pointer and bits appear to be kept in registers),
the difference appears to be code ordering and with a reorder it is able
to use smaller forward jumps.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_utils.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0c1cbe98c994..8dbd302be36a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2612,7 +2612,7 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj,
}
GEM_BUG_ON(!obj->mm.pages);
- ptr = ptr_unpack_bits(obj->mm.mapping, has_type);
+ ptr = ptr_unpack_bits(obj->mm.mapping, &has_type);
if (ptr && has_type != type) {
if (pinned) {
ret = -EBUSY;
diff --git a/drivers/gpu/drm/i915/i915_utils.h
b/drivers/gpu/drm/i915/i915_utils.h
index f9d6607ef52f..18630d8f4be8 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -77,7 +77,7 @@
#define ptr_unpack_bits(ptr, bits) ({ \
unsigned long __v = (unsigned long)(ptr); \
- (bits) = __v & ~PAGE_MASK; \
+ *(bits) = __v & ~PAGE_MASK; \
(typeof(ptr))(__v & PAGE_MASK); \
})
--
2.11.0
___
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[Intel-gfx] [CI 09/12] drm/i915: Create a kmem_cache to allocate struct i915_priolist from
The i915_priolist are allocated within an atomic context on a path where
we wish to minimise latency. If we use a dedicated kmem_cache, we have
the advantage of a local freelist from which to service new requests
that should keep the latency impact of an allocation small. Though
currently we expect the majority of requests to be at default priority
(and so hit the preallocate priolist), once userspace starts using
priorities they are likely to use many fine grained policies improving
the utilisation of a private slab.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem.c | 9 -
drivers/gpu/drm/i915/i915_guc_submission.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 4 ++--
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 9 -
5 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a6f20471b4cd..08ee5c8834fb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2027,6 +2027,7 @@ struct drm_i915_private {
struct kmem_cache *vmas;
struct kmem_cache *requests;
struct kmem_cache *dependencies;
+ struct kmem_cache *priorities;
const struct intel_device_info info;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 07db08cc6be0..02adf8241394 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4866,12 +4866,16 @@ i915_gem_load_init(struct drm_i915_private *dev_priv)
if (!dev_priv->dependencies)
goto err_requests;
+ dev_priv->priorities = KMEM_CACHE(i915_priolist, SLAB_HWCACHE_ALIGN);
+ if (!dev_priv->priorities)
+ goto err_dependencies;
+
mutex_lock(&dev_priv->drm.struct_mutex);
INIT_LIST_HEAD(&dev_priv->gt.timelines);
err = i915_gem_timeline_init__global(dev_priv);
mutex_unlock(&dev_priv->drm.struct_mutex);
if (err)
- goto err_dependencies;
+ goto err_priorities;
INIT_LIST_HEAD(&dev_priv->context_list);
INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work);
@@ -4895,6 +4899,8 @@ i915_gem_load_init(struct drm_i915_private *dev_priv)
return 0;
+err_priorities:
+ kmem_cache_destroy(dev_priv->priorities);
err_dependencies:
kmem_cache_destroy(dev_priv->dependencies);
err_requests:
@@ -4918,6 +4924,7 @@ void i915_gem_load_cleanup(struct drm_i915_private
*dev_priv)
WARN_ON(!list_empty(&dev_priv->gt.timelines));
mutex_unlock(&dev_priv->drm.struct_mutex);
+ kmem_cache_destroy(dev_priv->priorities);
kmem_cache_destroy(dev_priv->dependencies);
kmem_cache_destroy(dev_priv->requests);
kmem_cache_destroy(dev_priv->vmas);
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 3b9cdb0907c2..b3da056ea8f1 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -704,7 +704,7 @@ static bool i915_guc_dequeue(struct intel_engine_cs *engine)
rb_erase(&p->node, &engine->execlist_queue);
INIT_LIST_HEAD(&p->requests);
if (p->priority != I915_PRIORITY_NORMAL)
- kfree(p);
+ kmem_cache_free(engine->i915->priorities, p);
}
done:
engine->execlist_first = rb;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 626db6185a21..8529746dd7cc 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -499,7 +499,7 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
rb_erase(&p->node, &engine->execlist_queue);
INIT_LIST_HEAD(&p->requests);
if (p->priority != I915_PRIORITY_NORMAL)
- kfree(p);
+ kmem_cache_free(engine->i915->priorities, p);
}
done:
engine->execlist_first = rb;
@@ -661,7 +661,7 @@ insert_request(struct intel_engine_cs *engine,
if (prio == I915_PRIORITY_NORMAL) {
p = &engine->default_priolist;
} else {
- p = kmalloc(sizeof(*p), GFP_ATOMIC);
+ p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC);
/* Convert an allocation failure to a priority bump */
if (unlikely(!p)) {
prio = I915_PRIORITY_NORMAL; /* recurses just once */
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 2c1500d0d55a..f4edd4c6cb07 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -74,6 +74,7 @@ static void mock_device_re
[Intel-gfx] [CI 07/12] drm/i915: Use a define for the default priority [0]
Explicitly assign the default priority, and give it a name. After much
discussion, we have chosen to call it I915_PRIORITY_NORMAL!
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_context.c | 1 +
drivers/gpu/drm/i915/i915_gem_request.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 31a73c39239f..c5d1666d7071 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -199,6 +199,7 @@ __create_hw_context(struct drm_i915_private *dev_priv,
kref_init(&ctx->ref);
list_add_tail(&ctx->link, &dev_priv->context_list);
ctx->i915 = dev_priv;
+ ctx->priority = I915_PRIORITY_NORMAL;
/* Default context will never have a file_priv */
ret = DEFAULT_CONTEXT_HANDLE;
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h
b/drivers/gpu/drm/i915/i915_gem_request.h
index 219a9c954278..4c8fb6efc0f1 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -70,6 +70,7 @@ struct i915_priotree {
struct rb_node node;
int priority;
#define I915_PRIORITY_MAX 1024
+#define I915_PRIORITY_NORMAL 0
#define I915_PRIORITY_MIN (-I915_PRIORITY_MAX)
};
--
2.11.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 08/12] drm/i915: Split execlist priority queue into rbtree + linked list
All the requests at the same priority are executed in FIFO order. They
do not need to be stored in the rbtree themselves, as they are a simple
list within a level. If we move the requests at one priority into a list,
we can then reduce the rbtree to the set of priorities. This should keep
the height of the rbtree small, as the number of active priorities can not
exceed the number of active requests and should be typically only a few.
Currently, we have ~2k possible different priority levels, that may
increase to allow even more fine grained selection. Allocating those in
advance seems a waste (and may be impossible), so we opt for allocating
upon first use, and freeing after its requests are depleted. To avoid
the possibility of an allocation failure causing us to lose a request,
we preallocate the default priority (0) and bump any request to that
priority if we fail to allocate it the appropriate plist. Having a
request (that is ready to run, so not leading to corruption) execute
out-of-order is better than leaking the request (and its dependency
tree) entirely.
There should be a benefit to reducing execlists_dequeue() to principally
using a simple list (and reducing the frequency of both rbtree iteration
and balancing on erase) but for typical workloads, request coalescing
should be small enough that we don't notice any change. The main gain is
from improving PI calls to schedule, and the explicit list within a
level should make request unwinding simpler (we just need to insert at
the head of the list rather than the tail and not have to make the
rbtree search more complicated).
v2: Avoid use-after-free when deleting a depleted priolist
v3: Michał found the solution to handling the allocation failure
gracefully. If we disable all priority scheduling following the
allocation failure, those requests will be executed in fifo and we will
ensure that this request and its dependencies are in strict fifo (even
when it doesn't realise it is only a single list). Normal scheduling is
restored once we know the device is idle, until the next failure!
Suggested-by: Michał Wajdeczko
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Reviewed-by: Michał Winiarski
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c| 11 +-
drivers/gpu/drm/i915/i915_gem.c| 7 +-
drivers/gpu/drm/i915/i915_gem_request.c| 4 +-
drivers/gpu/drm/i915/i915_gem_request.h| 2 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 50
drivers/gpu/drm/i915/i915_utils.h | 9 ++
drivers/gpu/drm/i915/intel_engine_cs.c | 12 ++
drivers/gpu/drm/i915/intel_lrc.c | 183 +++--
drivers/gpu/drm/i915/intel_ringbuffer.h| 9 ++
9 files changed, 192 insertions(+), 95 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index e08ac708e547..8abb93994c48 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3352,7 +3352,6 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
if (i915.enable_execlists) {
u32 ptr, read, write;
- struct rb_node *rb;
unsigned int idx;
seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
@@ -3396,9 +3395,13 @@ static int i915_engine_info(struct seq_file *m, void
*unused)
rcu_read_unlock();
spin_lock_irq(&engine->timeline->lock);
- for (rb = engine->execlist_first; rb; rb = rb_next(rb))
{
- rq = rb_entry(rb, typeof(*rq), priotree.node);
- print_request(m, rq, "\t\tQ ");
+ for (rb = engine->execlist_first; rb; rb = rb_next(rb)){
+ struct i915_priolist *p =
+ rb_entry(rb, typeof(*p), node);
+
+ list_for_each_entry(rq, &p->requests,
+ priotree.link)
+ print_request(m, rq, "\t\tQ ");
}
spin_unlock_irq(&engine->timeline->lock);
} else if (INTEL_GEN(dev_priv) > 6) {
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 83518cdb19f3..07db08cc6be0 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3155,8 +3155,6 @@ i915_gem_idle_work_handler(struct work_struct *work)
struct drm_i915_private *dev_priv =
container_of(work, typeof(*dev_priv), gt.idle_work.work);
struct drm_device *dev = &dev_priv->drm;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
bool rearm_hangcheck;
if (!READ_ONCE(dev_priv->gt.awake))
@@ -3194,10 +3192,7 @@ i915_gem_idle_w
[Intel-gfx] [CI 10/12] drm/i915/execlists: Reduce lock contention between schedule/submit_request
If we do not require to perform priority bumping, and we haven't yet
submitted the request, we can update its priority in situ and skip
acquiring the engine locks -- thus avoiding any contention between us
and submit/execute.
v2: Remove the stack element from the list if we can do the early
assignment.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 8529746dd7cc..014b30ace8a0 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -779,6 +779,19 @@ static void execlists_schedule(struct drm_i915_gem_request
*request, int prio)
list_safe_reset_next(dep, p, dfs_link);
}
+ /* If we didn't need to bump any existing priorities, and we haven't
+* yet submitted this request (i.e. there is no potential race with
+* execlists_submit_request()), we can set our own priority and skip
+* acquiring the engine locks.
+*/
+ if (request->priotree.priority == INT_MIN) {
+ GEM_BUG_ON(!list_empty(&request->priotree.link));
+ request->priotree.priority = prio;
+ if (stack.dfs_link.next == stack.dfs_link.prev)
+ return;
+ __list_del_entry(&stack.dfs_link);
+ }
+
engine = request->engine;
spin_lock_irq(&engine->timeline->lock);
--
2.11.0
___
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[Intel-gfx] [CI 11/12] drm/i915: Stop inlining the execlists IRQ handler
As the handler is now quite complex, involving a few atomics, the cost
of the function preamble is negligible in comparison and so we should
leave the function out-of-line for better I$.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 927b408e6e95..a58152dd7021 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1317,7 +1317,7 @@ static void snb_gt_irq_handler(struct drm_i915_private
*dev_priv,
ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
}
-static __always_inline void
+static void
gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
{
bool tasklet = false;
--
2.11.0
___
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[Intel-gfx] [CI 12/12] drm/i915: Don't force serialisation on marking up execlists irq posted
Since we coordinate with the execlists tasklet using a locked schedule
operation that ensures that after we set the engine->irq_posted we
always have an invocation of the tasklet, we do not need to use a locked
operation to set the engine->irq_posted itself.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a58152dd7021..7b7f55a28eec 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1324,7 +1324,7 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32
iir, int test_shift)
if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) {
if (port_count(&engine->execlist_port[0])) {
- set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
+ __set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
tasklet = true;
}
}
--
2.11.0
___
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[Intel-gfx] [PATCH] drm/i915/selftest: Fix dma_buf_vmap error handling
The dma_buf_vmap in itself warns on error and then downgrades
the return value from error ptr to NULL. Don't try to decode error
value from the return in our test.
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/selftests/i915_gem_dmabuf.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/selftests/i915_gem_dmabuf.c
index d15cc9d3a5cd..89dc25a5a53b 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_dmabuf.c
@@ -246,9 +246,9 @@ static int igt_dmabuf_export_vmap(void *arg)
i915_gem_object_put(obj);
ptr = dma_buf_vmap(dmabuf);
- if (IS_ERR(ptr)) {
- err = PTR_ERR(ptr);
- pr_err("dma_buf_vmap failed with err=%d\n", err);
+ if (!ptr) {
+ pr_err("dma_buf_vmap failed\n");
+ err = -ENOMEM;
goto out;
}
--
2.11.0
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Re: [Intel-gfx] [PATCH] drm/i915/selftest: Fix dma_buf_vmap error handling
On Wed, May 17, 2017 at 03:41:49PM +0300, Mika Kuoppala wrote: > The dma_buf_vmap in itself warns on error and then downgrades > the return value from error ptr to NULL. Don't try to decode error > value from the return in our test. > Actually dma_buf_vmap shouldn't be WARNing here, so go fix that instead. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Implement DDB algorithm and WM cleanup (rev8)
== Series Details == Series: Implement DDB algorithm and WM cleanup (rev8) URL : https://patchwork.freedesktop.org/series/20376/ State : success == Summary == Series 20376v8 Implement DDB algorithm and WM cleanup https://patchwork.freedesktop.org/api/1.0/series/20376/revisions/8/mbox/ Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: pass -> FAIL (fi-snb-2600) fdo#17 fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17 fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:446s fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time:581s fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:511s fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:492s fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:487s fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:416s fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:409s fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:421s fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:495s fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:472s fi-kbl-7500u total:278 pass:255 dwarn:5 dfail:0 fail:0 skip:18 time:462s fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:461s fi-skl-6700hqtotal:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time:573s fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:472s fi-skl-6770hqtotal:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:506s fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:536s fi-snb-2600 total:278 pass:248 dwarn:0 dfail:0 fail:1 skip:29 time:401s f7b4cf45f680e7ed60f8e015e1a1b050ba68fc28 drm-tip: 2017y-05m-17d-11h-32m-43s UTC integration manifest 0bb103b drm/i915/skl+: consider max supported plane pixel rate while scaling 2113f15 drm/i915/skl: New ddb allocation algorithm 0815c9e drm/i915/skl+: use linetime latency if ddb size is not available a73d677 drm/i915/skl+: Perform wm level calculations in separate function c9068b3 drm/i915/skl+: Watermark calculation cleanup 287b1d4 drm/i915/skl+: Fail the flip if ddb min requirement exceeds pipe allocation 5762c93 drm/i915/skl+: no need to memset again 9eb2811 drm/i915/skl: Fail the flip if no FB for WM calculation b70205e drm/i915/skl+: calculate pixel_rate & relative_data_rate in fixed point 8e389c4 drm/i915: Use fixed_16_16 wrapper for division operation 838c98c drm/i915: Add more wrapper for fixed_point_16_16 operations 8c7da70 drm/i915: fix naming of fixed_16_16 wrapper. == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4721/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Use a cached mapping for the physical HWS
Older gen use a physical address for the hardware status page, for which
we use cache-coherent writes. As the writes are into the cpu cache, we use
a normal WB mapped page to read the HWS, used for our seqno tracking.
Anecdotally, I observed lost breadcrumbs writes into the HWS on i965gm,
which so far have not reoccurred with this patch. How reliable that
evidence is remains to be seen.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_ringbuffer.c | 34 -
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 -
3 files changed, 25 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8ec3bb2913d4..bc223471d391 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2061,7 +2061,6 @@ struct drm_i915_private {
struct i915_gem_context *kernel_context;
struct intel_engine_cs *engine[I915_NUM_ENGINES];
- struct drm_dma_handle *status_page_dmah;
struct resource mch_res;
/* protects the irq masks */
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c32a4ba9579f..3d80cbcd5d94 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -342,9 +342,10 @@ static void ring_setup_phys_status_page(struct
intel_engine_cs *engine)
struct drm_i915_private *dev_priv = engine->i915;
u32 addr;
- addr = dev_priv->status_page_dmah->busaddr;
+ addr = engine->status_page.dma_addr;
if (INTEL_GEN(dev_priv) >= 4)
- addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
+ addr |= (engine->status_page.dma_addr >> 28) & 0xf0;
+
I915_WRITE(HWS_PGA, addr);
}
@@ -1000,12 +1001,14 @@ i915_emit_bb_start(struct drm_i915_gem_request *req,
static void cleanup_phys_status_page(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
-
- if (!dev_priv->status_page_dmah)
+ if (!engine->status_page.page_addr)
return;
- drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah);
+ dma_unmap_page(engine->i915->drm.dev,
+ engine->status_page.dma_addr, PAGE_SIZE,
+ PCI_DMA_BIDIRECTIONAL);
+
+ __free_page(virt_to_page(engine->status_page.page_addr));
engine->status_page.page_addr = NULL;
}
@@ -1091,17 +1094,22 @@ static int init_status_page(struct intel_engine_cs
*engine)
static int init_phys_status_page(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->i915;
+ struct page *page;
- GEM_BUG_ON(engine->id != RCS);
+ page = alloc_page(GFP_KERNEL | __GFP_ZERO);
+ if (!page)
+ return -ENOMEM;
- dev_priv->status_page_dmah =
- drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE);
- if (!dev_priv->status_page_dmah)
+ engine->status_page.dma_addr =
+ dma_map_page(engine->i915->drm.dev, page, 0, PAGE_SIZE,
+PCI_DMA_BIDIRECTIONAL);
+ if (dma_mapping_error(engine->i915->drm.dev,
+ engine->status_page.dma_addr)) {
+ __free_page(page);
return -ENOMEM;
+ }
- engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
- memset(engine->status_page.page_addr, 0, PAGE_SIZE);
+ engine->status_page.page_addr = page_address(page);
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 46927e9530a2..fc3a2ac8914e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -18,9 +18,12 @@
#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
struct intel_hw_status_page {
- struct i915_vma *vma;
u32 *page_addr;
u32 ggtt_offset;
+ union {
+ struct i915_vma *vma;
+ dma_addr_t dma_addr;
+ };
};
#define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base))
--
2.11.0
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[Intel-gfx] [PATCH] Revert "drm/i915: Restore lost "Initialized i915" welcome message"
This reverts commit bc5ca47c0af4f949ba889e666b7da65569e36093.
Gabriel put this back into generic code with
commit 75f6dfe3e652e1adef8cc1b073c89f3e22103a8f
Author: Gabriel Krisman Bertazi
Date: Wed Dec 28 12:32:11 2016 -0200
drm: Deduplicate driver initialization message
but somehow he missed Chris' patch to add the message meanwhile.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101025
Fixes: 75f6dfe3e652 ("drm: Deduplicate driver initialization message")
Cc: Gabriel Krisman Bertazi
Cc: Daniel Vetter
Cc: Jani Nikula
Cc: Chris Wilson
Cc: # v4.11+
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_drv.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b0c003498b6b..6052798bb626 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1286,10 +1286,6 @@ int i915_driver_load(struct pci_dev *pdev, const struct
pci_device_id *ent)
dev_priv->ipc_enabled = false;
- /* Everything is in place, we can now relax! */
- DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
-driver.name, driver.major, driver.minor, driver.patchlevel,
-driver.date, pci_name(pdev), dev_priv->drm.primary->index);
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
DRM_INFO("DRM_I915_DEBUG enabled\n");
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
--
2.11.0
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Re: [Intel-gfx] [PATCH] Revert "drm/i915: Restore lost "Initialized i915" welcome message"
On Wed, May 17, 2017 at 03:15:57PM +0200, Daniel Vetter wrote:
> This reverts commit bc5ca47c0af4f949ba889e666b7da65569e36093.
>
> Gabriel put this back into generic code with
>
> commit 75f6dfe3e652e1adef8cc1b073c89f3e22103a8f
> Author: Gabriel Krisman Bertazi
> Date: Wed Dec 28 12:32:11 2016 -0200
>
> drm: Deduplicate driver initialization message
>
> but somehow he missed Chris' patch to add the message meanwhile.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101025
> Fixes: 75f6dfe3e652 ("drm: Deduplicate driver initialization message")
> Cc: Gabriel Krisman Bertazi
> Cc: Daniel Vetter
> Cc: Jani Nikula
> Cc: Chris Wilson
> Cc: # v4.11+
> Signed-off-by: Daniel Vetter
/me waves goodbye to amusing comment.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,01/12] drm/i915: Remove kref from i915_sw_fence
== Series Details == Series: series starting with [CI,01/12] drm/i915: Remove kref from i915_sw_fence URL : https://patchwork.freedesktop.org/series/24560/ State : success == Summary == Series 24560v1 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/24560/revisions/1/mbox/ fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:446s fi-bdw-gvtdvmtotal:278 pass:256 dwarn:8 dfail:0 fail:0 skip:14 time:431s fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time:602s fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:516s fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:497s fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:496s fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:423s fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:409s fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:430s fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:495s fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:459s fi-kbl-7500u total:278 pass:255 dwarn:5 dfail:0 fail:0 skip:18 time:465s fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:459s fi-skl-6700hqtotal:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time:585s fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:471s fi-skl-6770hqtotal:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:506s fi-skl-gvtdvmtotal:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 time:437s fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:537s fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time:404s 2a803862b93e594c668bd2c48b9d84e5c9dd6607 drm-tip: 2017y-05m-17d-12h-46m-57s UTC integration manifest ab495dc drm/i915: Don't force serialisation on marking up execlists irq posted 753233d drm/i915: Stop inlining the execlists IRQ handler 23db85d drm/i915/execlists: Reduce lock contention between schedule/submit_request 37ce057 drm/i915: Create a kmem_cache to allocate struct i915_priolist from 1ede3f0 drm/i915: Split execlist priority queue into rbtree + linked list 7e4f4bf drm/i915: Use a define for the default priority [0] ee50632 drm/i915: Don't mark an execlists context-switch when idle d5fb305 drm/i915/execlists: Pack the count into the low bits of the port.request c37594d drm/i915: Redefine ptr_pack_bits() and friends 9315737 drm/i915: Make ptr_unpack_bits() more function-like 3a17339 drm/i915: Import the kfence selftests for i915_sw_fence 13c89d2 drm/i915: Remove kref from i915_sw_fence == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4722/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftest: Fix dma_buf_vmap error handling
== Series Details == Series: drm/i915/selftest: Fix dma_buf_vmap error handling URL : https://patchwork.freedesktop.org/series/24561/ State : success == Summary == Series 24561v1 drm/i915/selftest: Fix dma_buf_vmap error handling https://patchwork.freedesktop.org/api/1.0/series/24561/revisions/1/mbox/ fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:445s fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time:592s fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:510s fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:491s fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:484s fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:420s fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:415s fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:424s fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:498s fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:458s fi-kbl-7500u total:278 pass:255 dwarn:5 dfail:0 fail:0 skip:18 time:465s fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:457s fi-skl-6700hqtotal:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time:570s fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:471s fi-skl-6770hqtotal:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:497s fi-skl-gvtdvmtotal:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 time:440s fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:535s fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time:404s fi-bdw-gvtdvm failed to connect after reboot 2a803862b93e594c668bd2c48b9d84e5c9dd6607 drm-tip: 2017y-05m-17d-12h-46m-57s UTC integration manifest fbc7a75 drm/i915/selftest: Fix dma_buf_vmap error handling == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4723/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,01/12] drm/i915: Remove kref from i915_sw_fence
On Wed, May 17, 2017 at 01:38:07PM -, Patchwork wrote: > == Series Details == > > Series: series starting with [CI,01/12] drm/i915: Remove kref from > i915_sw_fence > URL : https://patchwork.freedesktop.org/series/24560/ > State : success > > == Summary == > > Series 24560v1 Series without cover letter > https://patchwork.freedesktop.org/api/1.0/series/24560/revisions/1/mbox/ > > fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 > time:446s > fi-bdw-gvtdvmtotal:278 pass:256 dwarn:8 dfail:0 fail:0 skip:14 > time:431s > fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 > time:602s > fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 > time:516s > fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 > time:497s > fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 > time:496s > fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 > time:423s > fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 > time:409s > fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 > time:430s > fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 > time:495s > fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 > time:459s > fi-kbl-7500u total:278 pass:255 dwarn:5 dfail:0 fail:0 skip:18 > time:465s > fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 > time:459s > fi-skl-6700hqtotal:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 > time:585s > fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 > time:471s > fi-skl-6770hqtotal:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 > time:506s > fi-skl-gvtdvmtotal:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 > time:437s > fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 > time:537s > fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 > time:404s And pushed. Thanks everyone for the review, onwards to execbuf! -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] Revert "drm/i915: Restore lost "Initialized i915" welcome message"
Daniel Vetter writes: > This reverts commit bc5ca47c0af4f949ba889e666b7da65569e36093. > > Gabriel put this back into generic code with > > commit 75f6dfe3e652e1adef8cc1b073c89f3e22103a8f > Author: Gabriel Krisman Bertazi > Date: Wed Dec 28 12:32:11 2016 -0200 > > drm: Deduplicate driver initialization message > > but somehow he missed Chris' patch to add the message meanwhile. Hmmm. In the commit message, I even mentioned that i915 was an exception because it used its own registration handle, so I'm pretty sure I didn't miss that commit. Not that this is supposed to make it any better... what the heck happened back then?? :( This is Reviewed-by: Gabriel Krisman Bertazi -- Gabriel Krisman Bertazi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/4] drm/dp: device identification and quirks
New version of [1] with DPCD OUI etc. reading moved from i915 to DP helpers, and the quirks based on that. Helps improve the documentation that Daniel longed for. BR, Jani. [1] 20170511095721.7392-1-jani.nikula@intel.com">http://mid.mail-archive.com/20170511095721.7392-1-jani.nikula@intel.com Jani Nikula (4): drm/dp: add helper for reading DP sink/branch device desc from DPCD drm/i915: use drm DP helper to read DPCD desc drm/dp: start a DPCD based DP sink/branch device quirk database drm/i915: Detect USB-C specific dongles before reducing M and N drivers/gpu/drm/drm_dp_helper.c | 83 drivers/gpu/drm/i915/i915_drv.h | 3 +- drivers/gpu/drm/i915/intel_display.c | 22 ++ drivers/gpu/drm/i915/intel_dp.c | 45 +-- drivers/gpu/drm/i915/intel_dp_mst.c | 5 ++- drivers/gpu/drm/i915/intel_drv.h | 5 +-- drivers/gpu/drm/i915/intel_lspcon.c | 2 +- include/drm/drm_dp_helper.h | 51 ++ 8 files changed, 166 insertions(+), 50 deletions(-) -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/4] drm/dp: start a DPCD based DP sink/branch device quirk database
Face the fact, there are Display Port sink and branch devices out there
in the wild that don't follow the Display Port specifications, or they
have bugs, or just otherwise require special treatment. Start a common
quirk database the drivers can query based on the DP device
identification. At least for now, we leave the workarounds for the
drivers to implement as they see fit.
For starters, add a branch device that can't handle full 24-bit main
link M and N attributes properly. Naturally, the workaround of reducing
main link attributes for all devices ended up in regressions for other
devices. So here we are.
v2: Rebase on DRM DP desc read helpers
Cc: Ville Syrjälä
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
Cc: Adam Jackson
Cc: Harry Wentland
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_helper.c | 52 +++--
include/drm/drm_dp_helper.h | 32 +
2 files changed, 82 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 52e0ca9a5bb1..8c3797283c3b 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1209,6 +1209,51 @@ int drm_dp_stop_crc(struct drm_dp_aux *aux)
}
EXPORT_SYMBOL(drm_dp_stop_crc);
+struct dpcd_quirk {
+ u8 oui[3];
+ bool is_branch;
+ u32 quirks;
+};
+
+#define OUI(first, second, third) { (first), (second), (third) }
+
+static const struct dpcd_quirk dpcd_quirk_list[] = {
+ /* Analogix 7737 needs reduced M and N at HBR2 link rates */
+ { OUI(0x00, 0x22, 0xb9), true, BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
+};
+
+#undef OUI
+
+/*
+ * Get a bit mask of DPCD quirks for the sink/branch device identified by
+ * ident. The quirk data is shared but it's up to the drivers to act on the
+ * data.
+ *
+ * For now, only the OUI (first three bytes) is used, but this may be extended
+ * to device identification string and hardware/firmware revisions later.
+ */
+static u32
+drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
+{
+ const struct dpcd_quirk *quirk;
+ u32 quirks = 0;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
+ quirk = &dpcd_quirk_list[i];
+
+ if (quirk->is_branch != is_branch)
+ continue;
+
+ if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui) != 0))
+ continue;
+
+ quirks |= quirk->quirks;
+ }
+
+ return quirks;
+}
+
/**
* drm_dp_read_desc - read sink/branch descriptor from DPCD
* @aux: DisplayPort AUX channel
@@ -1231,14 +1276,17 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct
drm_dp_desc *desc,
if (ret < 0)
return ret;
+ desc->quirks = drm_dp_get_quirks(ident, is_branch);
+
dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
- DRM_DEBUG_KMS("DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev
%d.%d\n",
+ DRM_DEBUG_KMS("DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d
quirks 0x%04x\n",
is_branch ? "branch" : "sink",
(int)sizeof(ident->oui), ident->oui,
dev_id_len, ident->device_id,
ident->hw_rev >> 4, ident->hw_rev & 0xf,
- ident->sw_major_rev, ident->sw_minor_rev);
+ ident->sw_major_rev, ident->sw_minor_rev,
+ desc->quirks);
return 0;
}
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index aee5b96b51d7..717cb8496725 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1090,12 +1090,44 @@ struct drm_dp_dpcd_ident {
/**
* struct drm_dp_desc - DP branch/sink device descriptor
* @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
+ * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
*/
struct drm_dp_desc {
struct drm_dp_dpcd_ident ident;
+ u32 quirks;
};
int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
bool is_branch);
+/**
+ * enum drm_dp_quirk - Display Port sink/branch device specific quirks
+ *
+ * Display Port sink and branch devices in the wild have a variety of bugs, try
+ * to collect them here. The quirks are shared, but it's up to the drivers to
+ * implement workarounds for them.
+ */
+enum drm_dp_quirk {
+ /**
+* @DP_DPCD_QUIRK_LIMITED_M_N:
+*
+* The device requires main link attributes Mdiv and Ndiv to be limited
+* to 16 bits.
+*/
+ DP_DPCD_QUIRK_LIMITED_M_N,
+};
+
+/**
+ * drm_dp_has_quirk() - does the DP device have a specific quirk
+ * @desc: Device decriptor filled by drm_dp_read_desc()
+ * @quirk: Quirk to query for
+ *
+ * Return true if DP device identified by @desc has @quirk.
+ */
+static inline bool
+drm_dp_has_quirk(const struct drm_dp_desc *desc, enum
[Intel-gfx] [PATCH 2/4] drm/i915: use drm DP helper to read DPCD desc
Switch to using the common DP helpers instead of using our own.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c | 37 -
drivers/gpu/drm/i915/intel_drv.h| 5 +
drivers/gpu/drm/i915/intel_lspcon.c | 2 +-
3 files changed, 6 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4a6feb6a69bd..2a5f385e8f44 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1548,37 +1548,6 @@ static void intel_dp_print_rates(struct intel_dp
*intel_dp)
DRM_DEBUG_KMS("common rates: %s\n", str);
}
-bool
-__intel_dp_read_desc(struct intel_dp *intel_dp, struct intel_dp_desc *desc)
-{
- u32 base = drm_dp_is_branch(intel_dp->dpcd) ? DP_BRANCH_OUI :
- DP_SINK_OUI;
-
- return drm_dp_dpcd_read(&intel_dp->aux, base, desc, sizeof(*desc)) ==
- sizeof(*desc);
-}
-
-bool intel_dp_read_desc(struct intel_dp *intel_dp)
-{
- struct intel_dp_desc *desc = &intel_dp->desc;
- bool oui_sup = intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] &
- DP_OUI_SUPPORT;
- int dev_id_len;
-
- if (!__intel_dp_read_desc(intel_dp, desc))
- return false;
-
- dev_id_len = strnlen(desc->device_id, sizeof(desc->device_id));
- DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev
%d.%d\n",
- drm_dp_is_branch(intel_dp->dpcd) ? "branch" : "sink",
- (int)sizeof(desc->oui), desc->oui, oui_sup ? "" : "(NS)",
- dev_id_len, desc->device_id,
- desc->hw_rev >> 4, desc->hw_rev & 0xf,
- desc->sw_major_rev, desc->sw_minor_rev);
-
- return true;
-}
-
int
intel_dp_max_link_rate(struct intel_dp *intel_dp)
{
@@ -3662,7 +3631,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
if (!intel_dp_read_dpcd(intel_dp))
return false;
- intel_dp_read_desc(intel_dp);
+ drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
+drm_dp_is_branch(intel_dp->dpcd));
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
@@ -4677,7 +4647,8 @@ intel_dp_long_pulse(struct intel_connector
*intel_connector)
intel_dp_print_rates(intel_dp);
- intel_dp_read_desc(intel_dp);
+ drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
+drm_dp_is_branch(intel_dp->dpcd));
intel_dp_configure_mst(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bd500977b3fc..61a9981343d5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -996,7 +996,7 @@ struct intel_dp {
/* Max rate for the current link */
int max_link_rate;
/* sink or branch descriptor */
- struct intel_dp_desc desc;
+ struct drm_dp_desc desc;
struct drm_dp_aux aux;
enum intel_display_power_domain aux_power_domain;
uint8_t train_set[4];
@@ -1571,9 +1571,6 @@ static inline unsigned int intel_dp_unused_lane_mask(int
lane_count)
}
bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
-bool __intel_dp_read_desc(struct intel_dp *intel_dp,
- struct intel_dp_desc *desc);
-bool intel_dp_read_desc(struct intel_dp *intel_dp);
int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_lspcon.c
b/drivers/gpu/drm/i915/intel_lspcon.c
index 71cbe9c08932..5abef482eacf 100644
--- a/drivers/gpu/drm/i915/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/intel_lspcon.c
@@ -240,7 +240,7 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port)
return false;
}
- intel_dp_read_desc(dp);
+ drm_dp_read_desc(&dp->aux, &dp->desc, drm_dp_is_branch(dp->dpcd));
DRM_DEBUG_KMS("Success: LSPCON init\n");
return true;
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/4] drm/dp: add helper for reading DP sink/branch device desc from DPCD
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_helper.c | 35 +++
include/drm/drm_dp_helper.h | 19 +++
2 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 3e5f52110ea1..52e0ca9a5bb1 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1208,3 +1208,38 @@ int drm_dp_stop_crc(struct drm_dp_aux *aux)
return 0;
}
EXPORT_SYMBOL(drm_dp_stop_crc);
+
+/**
+ * drm_dp_read_desc - read sink/branch descriptor from DPCD
+ * @aux: DisplayPort AUX channel
+ * @desc: Device decriptor to fill from DPCD
+ * @is_branch: true for branch devices, false for sink devices
+ *
+ * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
+ * identification.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
+bool is_branch)
+{
+ struct drm_dp_dpcd_ident *ident = &desc->ident;
+ unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
+ int ret, dev_id_len;
+
+ ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
+ if (ret < 0)
+ return ret;
+
+ dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
+
+ DRM_DEBUG_KMS("DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev
%d.%d\n",
+ is_branch ? "branch" : "sink",
+ (int)sizeof(ident->oui), ident->oui,
+ dev_id_len, ident->device_id,
+ ident->hw_rev >> 4, ident->hw_rev & 0xf,
+ ident->sw_major_rev, ident->sw_minor_rev);
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_read_desc);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index f7007e544f29..aee5b96b51d7 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1079,4 +1079,23 @@ void drm_dp_aux_unregister(struct drm_dp_aux *aux);
int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
int drm_dp_stop_crc(struct drm_dp_aux *aux);
+struct drm_dp_dpcd_ident {
+ u8 oui[3];
+ u8 device_id[6];
+ u8 hw_rev;
+ u8 sw_major_rev;
+ u8 sw_minor_rev;
+} __packed;
+
+/**
+ * struct drm_dp_desc - DP branch/sink device descriptor
+ * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
+ */
+struct drm_dp_desc {
+ struct drm_dp_dpcd_ident ident;
+};
+
+int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
+bool is_branch);
+
#endif /* _DRM_DP_HELPER_H_ */
--
2.11.0
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/4] drm/i915: Detect USB-C specific dongles before reducing M and N
The Analogix 7737 DP to HDMI converter requires reduced M and N values
when to operate correctly at HBR2. Detect this IC by its OUI value of
0x0022B9 via the DPCD quirk list.
v2 by Jani: Rebased on the DP quirk database
v3 by Jani: Rebased on the reworked DP quirk database
Fixes: 9a86cda07af2 ("drm/i915/dp: reduce link M/N parameters")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93578
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100755
Cc: Jani Nikula
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjälä
Signed-off-by: Clint Taylor
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_display.c | 22 ++
drivers/gpu/drm/i915/intel_dp.c | 8 ++--
drivers/gpu/drm/i915/intel_dp_mst.c | 5 -
4 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a6f20471b4cd..699e07362044 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -563,7 +563,8 @@ struct intel_link_m_n {
void intel_link_compute_m_n(int bpp, int nlanes,
int pixel_clock, int link_clock,
- struct intel_link_m_n *m_n);
+ struct intel_link_m_n *m_n,
+ bool reduce_m_n);
/* Interface history:
*
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8217ed0e7132..ea4f116bd410 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6116,7 +6116,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc,
pipe_config->fdi_lanes = lane;
intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
- link_bw, &pipe_config->fdi_m_n);
+ link_bw, &pipe_config->fdi_m_n, false);
ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
@@ -6292,7 +6292,8 @@ intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
}
static void compute_m_n(unsigned int m, unsigned int n,
- uint32_t *ret_m, uint32_t *ret_n)
+ uint32_t *ret_m, uint32_t *ret_n,
+ bool reduce_m_n)
{
/*
* Reduce M/N as much as possible without loss in precision. Several DP
@@ -6300,9 +6301,11 @@ static void compute_m_n(unsigned int m, unsigned int n,
* values. The passed in values are more likely to have the least
* significant bits zero than M after rounding below, so do this first.
*/
- while ((m & 1) == 0 && (n & 1) == 0) {
- m >>= 1;
- n >>= 1;
+ if (reduce_m_n) {
+ while ((m & 1) == 0 && (n & 1) == 0) {
+ m >>= 1;
+ n >>= 1;
+ }
}
*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
@@ -6313,16 +6316,19 @@ static void compute_m_n(unsigned int m, unsigned int n,
void
intel_link_compute_m_n(int bits_per_pixel, int nlanes,
int pixel_clock, int link_clock,
- struct intel_link_m_n *m_n)
+ struct intel_link_m_n *m_n,
+ bool reduce_m_n)
{
m_n->tu = 64;
compute_m_n(bits_per_pixel * pixel_clock,
link_clock * nlanes * 8,
- &m_n->gmch_m, &m_n->gmch_n);
+ &m_n->gmch_m, &m_n->gmch_n,
+ reduce_m_n);
compute_m_n(pixel_clock, link_clock,
- &m_n->link_m, &m_n->link_n);
+ &m_n->link_m, &m_n->link_n,
+ reduce_m_n);
}
static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2a5f385e8f44..1ae9de5cf39c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1627,6 +1627,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
int link_avail, link_clock;
int common_len;
uint8_t link_bw, rate_select;
+ bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
+ DP_DPCD_QUIRK_LIMITED_M_N);
common_len = intel_dp_common_len_rate_limit(intel_dp,
intel_dp->max_link_rate);
@@ -1759,7 +1761,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_link_compute_m_n(bpp, lane_count,
adjusted_mode->crtc_clock,
pipe_config->port_clock,
- &pipe_config->dp_m_n);
+ &pipe_config->dp_m_n,
+ reduce_m_n);
if (intel_connector->panel.down
Re: [Intel-gfx] [PATCH] drm/i915/selftest: Fix dma_buf_vmap error handling
Chris Wilson writes: > On Wed, May 17, 2017 at 03:41:49PM +0300, Mika Kuoppala wrote: >> The dma_buf_vmap in itself warns on error and then downgrades >> the return value from error ptr to NULL. Don't try to decode error >> value from the return in our test. >> > > Actually dma_buf_vmap shouldn't be WARNing here, so go fix that > instead. Regarless of warn, we have mixed use of null and errptr checks in the test. So eventually it might be best to return errptr from dma_buf_vmap along of fixing the WARN. But as discussed in irc, this might not bring much value. -Mika ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/i915: Restore lost "Initialized i915" welcome message"
== Series Details == Series: Revert "drm/i915: Restore lost "Initialized i915" welcome message" URL : https://patchwork.freedesktop.org/series/24563/ State : success == Summary == Series 24563v1 Revert "drm/i915: Restore lost "Initialized i915" welcome message" https://patchwork.freedesktop.org/api/1.0/series/24563/revisions/1/mbox/ Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: pass -> FAIL (fi-snb-2600) fdo#17 Test gem_exec_suspend: Subgroup basic-s4-devices: pass -> DMESG-WARN (fi-snb-2600) fdo#100125 fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17 fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125 fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:445s fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time:590s fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:513s fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:497s fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:491s fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:415s fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:419s fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:416s fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:499s fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:469s fi-kbl-7500u total:278 pass:255 dwarn:5 dfail:0 fail:0 skip:18 time:462s fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:462s fi-skl-6700hqtotal:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time:584s fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:467s fi-skl-6770hqtotal:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:498s fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:541s fi-snb-2600 total:278 pass:247 dwarn:1 dfail:0 fail:1 skip:29 time:404s eb3549d312620118dec3a69200894ac8a8fff358 drm-tip: 2017y-05m-17d-13h-53m-40s UTC integration manifest 372b5ed Revert "drm/i915: Restore lost "Initialized i915" welcome message" == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4725/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Mark CPU cache as dirty on every transition for CPU writes
Currently, we only mark the CPU cache as dirty if we skip a clflush.
This leads to some confusion where we have to ask if the object is in
the write domain or missed a clflush. If we always mark the cache as
dirty, this becomes a much simply question to answer.
The goal remains to do as few clflushes as required and to do them as
late as possible, in the hope of deferring the work to a kthread and not
block the caller (e.g. execbuf, flips).
v2: Always call clflush before GPU execution when the cache_dirty flag
is set. This may cause some extra work on llc systems that migrate dirty
buffers back and forth - but we do try to limit that by only setting
cache_dirty at the end of the gpu sequence.
v3: Always mark the cache as dirty upon a level change, as we need to
invalidate any stale cachelines due to external writes.
Reported-by: Dongwon Kim
Fixes: a6a7cc4b7db6 ("drm/i915: Always flush the dirty CPU cache when pinning
the scanout")
Signed-off-by: Chris Wilson
Cc: Dongwon Kim
Cc: Matt Roper
---
drivers/gpu/drm/i915/i915_gem.c | 76 ++--
drivers/gpu/drm/i915/i915_gem_clflush.c | 15 +++--
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 21 +++
drivers/gpu/drm/i915/i915_gem_internal.c | 3 +-
drivers/gpu/drm/i915/i915_gem_userptr.c | 5 +-
drivers/gpu/drm/i915/selftests/huge_gem_object.c | 3 +-
6 files changed, 67 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 02adf8241394..155dd52f2d18 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -49,7 +49,7 @@ static void i915_gem_flush_free_objects(struct
drm_i915_private *i915);
static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
{
- if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
+ if (obj->cache_dirty)
return false;
if (!i915_gem_object_is_coherent(obj))
@@ -233,6 +233,14 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj)
return st;
}
+static void __start_cpu_write(struct drm_i915_gem_object *obj)
+{
+ obj->base.read_domains = I915_GEM_DOMAIN_CPU;
+ obj->base.write_domain = I915_GEM_DOMAIN_CPU;
+ if (cpu_write_needs_clflush(obj))
+ obj->cache_dirty = true;
+}
+
static void
__i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
struct sg_table *pages,
@@ -248,8 +256,7 @@ __i915_gem_object_release_shmem(struct drm_i915_gem_object
*obj,
!i915_gem_object_is_coherent(obj))
drm_clflush_sg(pages);
- obj->base.read_domains = I915_GEM_DOMAIN_CPU;
- obj->base.write_domain = I915_GEM_DOMAIN_CPU;
+ __start_cpu_write(obj);
}
static void
@@ -684,6 +691,12 @@ i915_gem_dumb_create(struct drm_file *file,
args->size, &args->handle);
}
+static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
+{
+ return !(obj->cache_level == I915_CACHE_NONE ||
+obj->cache_level == I915_CACHE_WT);
+}
+
/**
* Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -753,6 +766,11 @@ flush_write_domain(struct drm_i915_gem_object *obj,
unsigned int flush_domains)
case I915_GEM_DOMAIN_CPU:
i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
break;
+
+ case I915_GEM_DOMAIN_RENDER:
+ if (gpu_write_needs_clflush(obj))
+ obj->cache_dirty = true;
+ break;
}
obj->base.write_domain = 0;
@@ -854,7 +872,8 @@ int i915_gem_obj_prepare_shmem_read(struct
drm_i915_gem_object *obj,
* optimizes for the case when the gpu will dirty the data
* anyway again before the next pread happens.
*/
- if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
+ if (!obj->cache_dirty &&
+ !(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
*needs_clflush = CLFLUSH_BEFORE;
out:
@@ -906,14 +925,16 @@ int i915_gem_obj_prepare_shmem_write(struct
drm_i915_gem_object *obj,
* This optimizes for the case when the gpu will use the data
* right away and we therefore have to clflush anyway.
*/
- if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
+ if (!obj->cache_dirty) {
*needs_clflush |= CLFLUSH_AFTER;
- /* Same trick applies to invalidate partially written cachelines read
-* before writing.
-*/
- if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
- *needs_clflush |= CLFLUSH_BEFORE;
+ /*
+* Same trick applies to invalidate partially written
+* cachelines read before writing.
+*/
+ if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
+ *needs_clflush |= CLFLUSH_BEFORE;
+ }
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/dp: device identification and quirks
== Series Details == Series: drm/dp: device identification and quirks URL : https://patchwork.freedesktop.org/series/24566/ State : success == Summary == Series 24566v1 drm/dp: device identification and quirks https://patchwork.freedesktop.org/api/1.0/series/24566/revisions/1/mbox/ Test gem_exec_suspend: Subgroup basic-s3: dmesg-warn -> PASS (fi-kbl-7500u) fdo#101022 +3 Subgroup basic-s4-devices: dmesg-warn -> PASS (fi-kbl-7500u) fdo#100904 fdo#101022 https://bugs.freedesktop.org/show_bug.cgi?id=101022 fdo#100904 https://bugs.freedesktop.org/show_bug.cgi?id=100904 fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:445s fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time:581s fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:512s fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:496s fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:491s fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:417s fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:409s fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:424s fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:500s fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:461s fi-kbl-7500u total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:455s fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:452s fi-skl-6700hqtotal:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time:583s fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:464s fi-skl-6770hqtotal:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:502s fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:537s fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time:407s eb3549d312620118dec3a69200894ac8a8fff358 drm-tip: 2017y-05m-17d-13h-53m-40s UTC integration manifest faca378 drm/i915: Detect USB-C specific dongles before reducing M and N 0ca6878 drm/dp: start a DPCD based DP sink/branch device quirk database 48ad1d4 drm/i915: use drm DP helper to read DPCD desc 4a2f44b drm/dp: add helper for reading DP sink/branch device desc from DPCD == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4726/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] drm: Create a format/modifier blob
On Wed, May 17, 2017 at 1:31 PM, Daniel Vetter wrote:
> On Tue, May 16, 2017 at 02:19:12PM -0700, Ben Widawsky wrote:
>> On 17-05-03 17:08:27, Daniel Vetter wrote:
>> > On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote:
>> > > +struct drm_format_modifier_blob {
>> > > +#define FORMAT_BLOB_CURRENT 1
>> > > + /* Version of this blob format */
>> > > + u32 version;
>> > > +
>> > > + /* Flags */
>> > > + u32 flags;
>> > > +
>> > > + /* Number of fourcc formats supported */
>> > > + u32 count_formats;
>> > > +
>> > > + /* Where in this blob the formats exist (in bytes) */
>> > > + u32 formats_offset;
>> > > +
>> > > + /* Number of drm_format_modifiers */
>> > > + u32 count_modifiers;
>> > > +
>> > > + /* Where in this blob the modifiers exist (in bytes) */
>> > > + u32 modifiers_offset;
>> > > +
>> > > + /* u32 formats[] */
>> > > + /* struct drm_format_modifier modifiers[] */
>> > > +} __packed;
>> >
>> > The struct should be in the uapi header. Otherwise it won't show up in
>> > libdrm headers when following the proper process.
>> > -Daniel
>> >
>>
>> I don't agree that blobs are ever really part of the API, but it doesn't
>> hurt to
>> move it... in other words, done.
>
> Userspace writes them, the kernel reads them (or maybe even the other way
> round). How exactly is a specific blob and its layout not part of uapi?
> Can you explain your reasoning here pls?
Ok, this is the other way round, kernel writes this, userspace reads
it. Question still stands.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Mark CPU cache as dirty on every transition for CPU writes
== Series Details == Series: drm/i915: Mark CPU cache as dirty on every transition for CPU writes URL : https://patchwork.freedesktop.org/series/24569/ State : success == Summary == Series 24569v1 drm/i915: Mark CPU cache as dirty on every transition for CPU writes https://patchwork.freedesktop.org/api/1.0/series/24569/revisions/1/mbox/ Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-atomic: pass -> FAIL (fi-snb-2600) fdo#100215 fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215 fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:446s fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time:577s fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:514s fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:492s fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:485s fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:419s fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:415s fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:426s fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:495s fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:467s fi-kbl-7500u total:278 pass:255 dwarn:5 dfail:0 fail:0 skip:18 time:463s fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:460s fi-skl-6700hqtotal:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time:583s fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:468s fi-skl-6770hqtotal:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:500s fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:535s fi-snb-2600 total:278 pass:248 dwarn:0 dfail:0 fail:1 skip:29 time:409s eb3549d312620118dec3a69200894ac8a8fff358 drm-tip: 2017y-05m-17d-13h-53m-40s UTC integration manifest cce0e79 drm/i915: Mark CPU cache as dirty on every transition for CPU writes == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4727/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC v3] drm/i915: Select engines via class and instance in execbuffer2
From: Tvrtko Ursulin
Building on top of the previous patch which exported the concept
of engine classes and instances, we can also use this instead of
the current awkward engine selection uAPI.
This is primarily interesting for the VCS engine selection which
is a) currently done via disjoint set of flags, and b) the
current I915_EXEC_BSD flags has different semantics depending on
the underlying hardware which is bad.
Proposed idea here is to reserve 16-bits of flags, to pass in
the engine class and instance (8 bits each), and a new flag
named I915_EXEC_CLASS_INSTACE to tell the kernel this new engine
selection API is in use.
The new uAPI also removes access to the weak VCS engine
balancing as currently existing in the driver.
Example usage to send a command to VCS0:
eb.flags = i915_execbuffer2_engine(DRM_I915_ENGINE_CLASS_VIDEO_DECODE, 0);
Or to send a command to VCS1:
eb.flags = i915_execbuffer2_engine(DRM_I915_ENGINE_CLASS_VIDEO_DECODE, 1);
v2:
* Fix unknown flags mask.
* Use I915_EXEC_RING_MASK for class. (Chris Wilson)
v3:
* Add a map for fast class-instance engine lookup. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin
Cc: Ben Widawsky
Cc: Chris Wilson
Cc: Daniel Vetter
Cc: Joonas Lahtinen
Cc: Jon Bloomfield
Cc: Daniel Charles
Cc: "Rogozhkin, Dmitry V"
Cc: Oscar Mateo
Cc: "Gong, Zhipeng"
Cc: intel-vaapi-me...@lists.01.org
Cc: mesa-...@lists.freedesktop.org
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 30 ++
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_engine_cs.c | 7 +++
include/uapi/drm/i915_drm.h| 11 ++-
5 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5dfa4a12e647..7bf4fd42480c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2066,6 +2066,7 @@ struct drm_i915_private {
struct pci_dev *bridge_dev;
struct i915_gem_context *kernel_context;
struct intel_engine_cs *engine[I915_NUM_ENGINES];
+ struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS +
1][MAX_ENGINE_INSTANCE + 1];
struct i915_vma *semaphore;
struct drm_dma_handle *status_page_dmah;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index af1965774e7b..c1ad49ab64cd 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1492,6 +1492,33 @@ gen8_dispatch_bsd_engine(struct drm_i915_private
*dev_priv,
return file_priv->bsd_engine;
}
+extern u8 user_class_map[DRM_I915_ENGINE_CLASS_MAX];
+
+static struct intel_engine_cs *get_engine_class(struct drm_i915_private *i915,
+ u8 class, u8 instance)
+{
+ if (class > MAX_ENGINE_CLASS || instance > MAX_ENGINE_INSTANCE)
+ return NULL;
+
+ return i915->engine_class[class][instance];
+}
+
+static struct intel_engine_cs *
+eb_select_engine_class_instance(struct drm_i915_private *i915,
+ struct drm_i915_gem_execbuffer2 *args)
+{
+ u8 class, instance;
+
+ class = args->flags & I915_EXEC_RING_MASK;
+ if (class >= DRM_I915_ENGINE_CLASS_MAX)
+ return NULL;
+
+ instance = (args->flags >> I915_EXEC_INSTANCE_SHIFT) &&
+ I915_EXEC_INSTANCE_MASK;
+
+ return get_engine_class(i915, user_class_map[class], instance);
+}
+
#define I915_USER_RINGS (4)
static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = {
@@ -1510,6 +1537,9 @@ eb_select_engine(struct drm_i915_private *dev_priv,
unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
struct intel_engine_cs *engine;
+ if (args->flags & I915_EXEC_CLASS_INSTANCE)
+ return eb_select_engine_class_instance(dev_priv, args);
+
if (user_ring_id > I915_USER_RINGS) {
DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
return NULL;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ee144ec57935..a3b59043b991 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -92,6 +92,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define VIDEO_ENHANCEMENT_CLASS2
#define COPY_ENGINE_CLASS 3
#define OTHER_CLASS4
+#define MAX_ENGINE_CLASS 4
+
+#define MAX_ENGINE_INSTANCE1
/* PCI config space */
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 7566cf48012f..c5ad51c43d23 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -225,7 +225,14 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifi
Re: [Intel-gfx] [RFC v3] drm/i915: Select engines via class and instance in execbuffer2
On Wed, May 17, 2017 at 04:40:57PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Building on top of the previous patch which exported the concept
> of engine classes and instances, we can also use this instead of
> the current awkward engine selection uAPI.
>
> This is primarily interesting for the VCS engine selection which
> is a) currently done via disjoint set of flags, and b) the
> current I915_EXEC_BSD flags has different semantics depending on
> the underlying hardware which is bad.
>
> Proposed idea here is to reserve 16-bits of flags, to pass in
> the engine class and instance (8 bits each), and a new flag
> named I915_EXEC_CLASS_INSTACE to tell the kernel this new engine
> selection API is in use.
>
> The new uAPI also removes access to the weak VCS engine
> balancing as currently existing in the driver.
>
> Example usage to send a command to VCS0:
>
> eb.flags = i915_execbuffer2_engine(DRM_I915_ENGINE_CLASS_VIDEO_DECODE, 0);
>
> Or to send a command to VCS1:
>
> eb.flags = i915_execbuffer2_engine(DRM_I915_ENGINE_CLASS_VIDEO_DECODE, 1);
>
> v2:
> * Fix unknown flags mask.
> * Use I915_EXEC_RING_MASK for class. (Chris Wilson)
>
> v3:
> * Add a map for fast class-instance engine lookup. (Chris Wilson)
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Ben Widawsky
> Cc: Chris Wilson
> Cc: Daniel Vetter
> Cc: Joonas Lahtinen
> Cc: Jon Bloomfield
> Cc: Daniel Charles
> Cc: "Rogozhkin, Dmitry V"
> Cc: Oscar Mateo
> Cc: "Gong, Zhipeng"
> Cc: intel-vaapi-me...@lists.01.org
> Cc: mesa-...@lists.freedesktop.org
> ---
> drivers/gpu/drm/i915/i915_drv.h| 1 +
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 30
> ++
> drivers/gpu/drm/i915/i915_reg.h| 3 +++
> drivers/gpu/drm/i915/intel_engine_cs.c | 7 +++
> include/uapi/drm/i915_drm.h| 11 ++-
> 5 files changed, 51 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 5dfa4a12e647..7bf4fd42480c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2066,6 +2066,7 @@ struct drm_i915_private {
> struct pci_dev *bridge_dev;
> struct i915_gem_context *kernel_context;
> struct intel_engine_cs *engine[I915_NUM_ENGINES];
> + struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS +
> 1][MAX_ENGINE_INSTANCE + 1];
> struct i915_vma *semaphore;
>
> struct drm_dma_handle *status_page_dmah;
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index af1965774e7b..c1ad49ab64cd 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1492,6 +1492,33 @@ gen8_dispatch_bsd_engine(struct drm_i915_private
> *dev_priv,
> return file_priv->bsd_engine;
> }
>
> +extern u8 user_class_map[DRM_I915_ENGINE_CLASS_MAX];
> +
> +static struct intel_engine_cs *get_engine_class(struct drm_i915_private
> *i915,
> + u8 class, u8 instance)
> +{
> + if (class > MAX_ENGINE_CLASS || instance > MAX_ENGINE_INSTANCE)
> + return NULL;
> +
> + return i915->engine_class[class][instance];
> +}
Be bold make this this an intel_engine_lookup(), I forsee some other
users appearing very shortly.
> +static struct intel_engine_cs *
> +eb_select_engine_class_instance(struct drm_i915_private *i915,
> + struct drm_i915_gem_execbuffer2 *args)
> +{
> + u8 class, instance;
> +
> + class = args->flags & I915_EXEC_RING_MASK;
> + if (class >= DRM_I915_ENGINE_CLASS_MAX)
> + return NULL;
> +
> + instance = (args->flags >> I915_EXEC_INSTANCE_SHIFT) &&
> +I915_EXEC_INSTANCE_MASK;
> +
> + return get_engine_class(i915, user_class_map[class], instance);
> +}
> +
> #define I915_USER_RINGS (4)
>
> static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = {
> @@ -1510,6 +1537,9 @@ eb_select_engine(struct drm_i915_private *dev_priv,
> unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
> struct intel_engine_cs *engine;
>
> + if (args->flags & I915_EXEC_CLASS_INSTANCE)
> + return eb_select_engine_class_instance(dev_priv, args);
> +
> if (user_ring_id > I915_USER_RINGS) {
> DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
> return NULL;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ee144ec57935..a3b59043b991 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -92,6 +92,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define VIDEO_ENHANCEMENT_CLASS 2
> #define COPY_ENGINE_CLASS3
> #define OTHER_CLASS 4
> +#define MAX_ENGINE_CLASS 4
> +
> +#define MAX_ENGINE_INSTANCE 1
We also need the names in the u
Re: [Intel-gfx] [PATCH] drm/i915: Mark CPU cache as dirty on every transition for CPU writes
Chris,
This patch works now as we unconditionally set cache_dirty
in set_cache_level function.
Tested-by: Dongwon Kim
On Wed, May 17, 2017 at 04:05:24PM +0100, Chris Wilson wrote:
> Currently, we only mark the CPU cache as dirty if we skip a clflush.
> This leads to some confusion where we have to ask if the object is in
> the write domain or missed a clflush. If we always mark the cache as
> dirty, this becomes a much simply question to answer.
>
> The goal remains to do as few clflushes as required and to do them as
> late as possible, in the hope of deferring the work to a kthread and not
> block the caller (e.g. execbuf, flips).
>
> v2: Always call clflush before GPU execution when the cache_dirty flag
> is set. This may cause some extra work on llc systems that migrate dirty
> buffers back and forth - but we do try to limit that by only setting
> cache_dirty at the end of the gpu sequence.
>
> v3: Always mark the cache as dirty upon a level change, as we need to
> invalidate any stale cachelines due to external writes.
>
> Reported-by: Dongwon Kim
> Fixes: a6a7cc4b7db6 ("drm/i915: Always flush the dirty CPU cache when pinning
> the scanout")
> Signed-off-by: Chris Wilson
> Cc: Dongwon Kim
> Cc: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_gem.c | 76
> ++--
> drivers/gpu/drm/i915/i915_gem_clflush.c | 15 +++--
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 21 +++
> drivers/gpu/drm/i915/i915_gem_internal.c | 3 +-
> drivers/gpu/drm/i915/i915_gem_userptr.c | 5 +-
> drivers/gpu/drm/i915/selftests/huge_gem_object.c | 3 +-
> 6 files changed, 67 insertions(+), 56 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 02adf8241394..155dd52f2d18 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -49,7 +49,7 @@ static void i915_gem_flush_free_objects(struct
> drm_i915_private *i915);
>
> static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
> {
> - if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
> + if (obj->cache_dirty)
> return false;
>
> if (!i915_gem_object_is_coherent(obj))
> @@ -233,6 +233,14 @@ i915_gem_object_get_pages_phys(struct
> drm_i915_gem_object *obj)
> return st;
> }
>
> +static void __start_cpu_write(struct drm_i915_gem_object *obj)
> +{
> + obj->base.read_domains = I915_GEM_DOMAIN_CPU;
> + obj->base.write_domain = I915_GEM_DOMAIN_CPU;
> + if (cpu_write_needs_clflush(obj))
> + obj->cache_dirty = true;
> +}
> +
> static void
> __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
> struct sg_table *pages,
> @@ -248,8 +256,7 @@ __i915_gem_object_release_shmem(struct
> drm_i915_gem_object *obj,
> !i915_gem_object_is_coherent(obj))
> drm_clflush_sg(pages);
>
> - obj->base.read_domains = I915_GEM_DOMAIN_CPU;
> - obj->base.write_domain = I915_GEM_DOMAIN_CPU;
> + __start_cpu_write(obj);
> }
>
> static void
> @@ -684,6 +691,12 @@ i915_gem_dumb_create(struct drm_file *file,
> args->size, &args->handle);
> }
>
> +static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
> +{
> + return !(obj->cache_level == I915_CACHE_NONE ||
> + obj->cache_level == I915_CACHE_WT);
> +}
> +
> /**
> * Creates a new mm object and returns a handle to it.
> * @dev: drm device pointer
> @@ -753,6 +766,11 @@ flush_write_domain(struct drm_i915_gem_object *obj,
> unsigned int flush_domains)
> case I915_GEM_DOMAIN_CPU:
> i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
> break;
> +
> + case I915_GEM_DOMAIN_RENDER:
> + if (gpu_write_needs_clflush(obj))
> + obj->cache_dirty = true;
> + break;
> }
>
> obj->base.write_domain = 0;
> @@ -854,7 +872,8 @@ int i915_gem_obj_prepare_shmem_read(struct
> drm_i915_gem_object *obj,
>* optimizes for the case when the gpu will dirty the data
>* anyway again before the next pread happens.
>*/
> - if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
> + if (!obj->cache_dirty &&
> + !(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
> *needs_clflush = CLFLUSH_BEFORE;
>
> out:
> @@ -906,14 +925,16 @@ int i915_gem_obj_prepare_shmem_write(struct
> drm_i915_gem_object *obj,
>* This optimizes for the case when the gpu will use the data
>* right away and we therefore have to clflush anyway.
>*/
> - if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
> + if (!obj->cache_dirty) {
> *needs_clflush |= CLFLUSH_AFTER;
>
> - /* Same trick applies to invalidate partially written cachelines read
> - * before writing.
> - */
> - if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
>
Re: [Intel-gfx] [PATCH v7 9/9] drm/i915: Set PWM divider to match desired frequency in vbt
On Tue, 2017-05-16 at 17:39 -0700, Puthikorn Voravootivat wrote: > > > On Tue, May 16, 2017 at 2:21 PM, Pandiyan, Dhinakaran > wrote: > On Tue, 2017-05-16 at 13:56 -0700, Puthikorn Voravootivat > wrote: > > > > > > On Tue, May 16, 2017 at 1:29 PM, Pandiyan, Dhinakaran > > wrote: > > On Tue, 2017-05-16 at 11:07 -0700, Puthikorn > Voravootivat > > wrote: > > > > > > > > > On Mon, May 15, 2017 at 11:21 PM, Pandiyan, > Dhinakaran > > > wrote: > > > On Mon, 2017-05-15 at 17:43 -0700, > Puthikorn > > Voravootivat > > > wrote: > > > > > > > > > > > > On Mon, May 15, 2017 at 4:07 PM, > Pandiyan, > > Dhinakaran > > > > wrote: > > > > On Fri, 2017-05-12 at 17:31 > -0700, > > Puthikorn > > > Voravootivat > > > > wrote: > > > > > > > > > > > > > > > > > > > > On Fri, May 12, 2017 at 5:12 > PM, > > Pandiyan, > > > Dhinakaran > > > > > > wrote: > > > > > On Thu, 2017-05-11 at > 16:02 > > -0700, > > > Puthikorn > > > > Voravootivat > > > > > wrote: > > > > > > Read desired PWM > frequency > > from panel > > > vbt and > > > > calculate the > > > > > > value for divider in > DPCD > > address 0x724 > > > and 0x728 > > > > to have > > > > > > as many bits as > possible for > > PWM duty > > > cyle for > > > > granularity > > > > > of > > > > > > brightness > adjustment while > > the > > > frequency is still > > > > within > > > > > 25% > > > > > > of the desired > frequency. > > > > > > > > > > I read a few eDP panel > data > > sheets, the > > > PWM > > > > frequencies all > > > > > start from > > > > > ~200Hz. If the VBT > chooses this > > lowest > > > value to > > > > allow for more > > > > > brightness control, > and then > > this patch > > > lowers the > > > > value by > > > > > another 25%, > > > > > we'll end up below the > panel > > allowed PWM > > > frequency. > > > > > > > > > > In fact, one of the > systems I > > checked had > > > PWM > > > > frequency as > > > > > 200Hz in VBT > > > > > and the panel > datasheet also had > > PWM > > > frequency range > > > > starting > > > > > from > > > > > 200Hz. Have you > considered this > > case? > > > > > > > > > > The spec said "A given LCD > panel > > typically has a > > > limited > > > > range of > > > > > backlight frequency > capability. > > > > > To limit the programmable > frequency > > range, > > > limitations are > >
Re: [Intel-gfx] [PATCH] drm: i915: Preserve old FBC status if update with no new planes
On Tue, May 16, 2017 at 06:52:17PM -0700, Manasi Navare wrote: > On Tue, May 16, 2017 at 10:27:33PM -0300, Gabriel Krisman Bertazi wrote: > > Manasi Navare writes: > > > > Hi Manasi, > > > > > So the purpose of this patch is to avoid overwriting the no_fbc_reason > > > field during atomic_check in case there is no plane update so that > > > it retains the actual failure message from previous atomic commit > > > operation > > > failure where it failed to enable fbc in intel_fbc_can_enable() during > > > the post plane update right? > > > > yes, correct. > > > > > On Mon, May 15, 2017 at 09:33:04PM -0300, Gabriel Krisman Bertazi wrote: > > >> If the atomic commit doesn't include any new plane, there is no need to > > >> choose a new CRTC for FBC, and the intel_fbc_choose_crtc() will bail out > > >> early. Although, if the FBC setup failed beforehand for whatever reason, > > >> we don't bail early, but we change the no_fbc_reason to "no suitable > > >> CRTC for FBC", which simply hides the real reason why the FBC wasn't > > > > > > I think this can be reworded a bit like " Although, if the FBC setup > > > failed > > > in the previous commit, if the current commit doesnt include new plane > > > update, > > > it tries to overwrite no_fbc_reason to "no suitable CRTC for FBC". > > > > > > Could you reword this commit message like I mentioned above? Everything else looks good to me. Manasi > > >> initialized. For that scenario, it is better that we simply keep the > > >> old message in-place to make debugging easier. > > >> > > >> A scenario where this happens is with the > > >> igt@kms_frontbuffer_tracking@fbc-suspend testcase when executed on a > > >> Haswell system with not enough stolen memory. When enabling the CRTC, > > >> the FBC setup will be correctly initialized to a specific CRTC, but > > >> won't be enabled, since there is not enough memory. The testcase will > > >> then enable CRC checking, which requires a quirk for Haswell, which > > >> issues a new atomic commit that doesn't update the planes. Since that > > >> update doesn't include any new planes (and the FBC wasn't enabled), > > >> intel_fbc_choose_crtc() will not find any suitable CRTC, but update the > > >> error message, hiding the lack of memory information, which is the > > >> actual cause of the initialization failure. As a result, this causes > > >> that test to fail on Haswell. > > > > > > So the problem here is just a wrong error message. > > > How does a wrong error message cause the IGT test to fail? > > > > igt is prepared to skip the test on boxes where there isn't enough > > stolen memory, but since we overwrite that message, the test will > > execute and fail. We discussed earlier on the list about adding a new > > check to igt for the "no suitable CRTC for FBC" message, but that could > > end up hiding other real error conditions. > > > > Ok, yes then this fix makes sense. In that case it looks good to me. > > Manasi > > -- > > Gabriel Krisman Bertazi > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 36/67] drm/i915: Add MMIO helper for 6 ports with different offsets.
On Thu, Apr 06, 2017 at 12:15:32PM -0700, Rodrigo Vivi wrote: > Also new registers can have different mmio offsets > per different lane per port. > > v2: Use _PICK as PORT3 instead of creating a new > macro with if per port. > > Signed-off-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/i915_reg.h | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index c38c1fd..5777925 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -64,6 +64,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PIPE3(pipe, a, b, c)) > #define _PORT3(port, ...) _PICK(port, __VA_ARGS__) > #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PORT3(pipe, a, b, c)) > +#define _PORT6(port, ...) _PICK(port, __VA_ARGS__) Why do we need to define _PORT6() as a separate macro when all it has to do is _PICK between given ports so we can jsut use _PORT3 and it will pick amongst the _VA_ARGS_. Jani/Ville am I correct? Manasi > +#define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PORT6(port, a, b, c, d, > e, f)) > +#define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f) > \ > + _MMIO(_PORT6(port, a0, b, c, d, e, f) + (ln * (a1 - a0))) > #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) > #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) > > -- > 1.9.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8 5/5] drm/i915: Set PWM divider to match desired frequency in vbt
On Tue, 2017-05-16 at 17:34 -0700, Puthikorn Voravootivat wrote:
> Read desired PWM frequency from panel vbt and calculate the
> value for divider in DPCD address 0x724 and 0x728 to have
> as many bits as possible for PWM duty cyle for granularity of
> brightness adjustment while the frequency divisor is still
> within 25% of the desired value.
>
> Signed-off-by: Puthikorn Voravootivat
> ---
> drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 82
> +++
> 1 file changed, 82 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> index c0eeb8fc2013..a01cbf3db1c2 100644
> --- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> @@ -116,12 +116,87 @@ intel_dp_aux_set_dynamic_backlight_percent(struct
> intel_dp *intel_dp,
> }
> }
>
> +/*
> + * Set PWM Frequency divider to match desired frequency in vbt.
> + * The PWM Frequency is calculated as 27Mhz / (F x P).
> + * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
> + * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
> + * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
> + * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
> + */
> +static void intel_dp_aux_set_pwm_freq(struct intel_connector *connector)
> +{
> + struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> + struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
> + int freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
> + u8 pn, pn_min, pn_max;
> +
> + /* Find desired value of (F x P)
> + * Note that, if F x P is out of supported range, the maximum value or
> + * minimum value will applied automatically. So no need to check that.
> + */
> + freq = dev_priv->vbt.backlight.pwm_freq_hz;
> + DRM_DEBUG_KMS("VBT defined backlight frequency %u Hz\n", freq);
> + if (!freq) {
> + DRM_DEBUG_KMS("Use panel default backlight frequency\n");
> + return;
> + }
> +
> + fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
> +
> + /* Use highest possible value of Pn for more granularity of brightness
> + * adjustment while satifying the conditions below.
> + * - Pn is in the range of Pn_min and Pn_max
> + * - F is in the range of 1 and 255
> + * - FxP is within 25% of desired value.
> + * Note: 25% is arbitrary value and may need some tweak.
> + */
> + if (drm_dp_dpcd_readb(&intel_dp->aux,
> +DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min) != 1) {
> + DRM_DEBUG_KMS("Failed to read pwmgen bit count cap min\n");
> + return;
> + }
> + if (drm_dp_dpcd_readb(&intel_dp->aux,
> +DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max) != 1) {
> + DRM_DEBUG_KMS("Failed to read pwmgen bit count cap max\n");
> + return;
> + }
> + pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> + pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> +
> + fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
> + fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
> + if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
> + DRM_DEBUG_KMS("VBT defined backlight frequency out of range\n");
> + return;
> + }
> +
> + for (pn = pn_max; pn >= pn_min; pn--) {
> + f = clamp(DIV_ROUND_CLOSEST(fxp , 1 << pn), 1, 255);
> + fxp_actual = f << pn;
> + if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
> + break;
> + }
> +
> + if (drm_dp_dpcd_writeb(&intel_dp->aux,
> +DP_EDP_PWMGEN_BIT_COUNT, pn) < 0) {
> + DRM_DEBUG_KMS("Failed to write aux pwmgen bit count\n");
> + return;
> + }
> + if (drm_dp_dpcd_writeb(&intel_dp->aux,
> +DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {
> + DRM_DEBUG_KMS("Failed to write aux backlight freq\n");
> + return;
> + }
> +}
> +
> static void intel_dp_aux_enable_backlight(struct intel_connector *connector)
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
> uint8_t dpcd_buf = 0;
> uint8_t new_dpcd_buf = 0;
> uint8_t edp_backlight_mode = 0;
> + bool freq_cap;
>
> if (drm_dp_dpcd_readb(&intel_dp->aux,
> DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf) != 1) {
> @@ -154,6 +229,10 @@ static void intel_dp_aux_enable_backlight(struct
> intel_connector *connector)
> DRM_DEBUG_KMS("Enable dynamic brightness.\n");
> }
>
> + freq_cap = intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP;
> + if (freq_cap)
> + new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
> +
> if (new_dpcd_buf != dpcd_buf) {
> if (drm
Re: [Intel-gfx] [PATCH v8 1/5] drm/i915: Drop AUX backlight enable check for backlight control
From: Puthikorn Voravootivat [put...@google.com] on behalf of Puthikorn
Voravootivat [put...@chromium.org]
Sent: Tuesday, May 16, 2017 5:33 PM
To: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
Cc: dri-de...@lists.freedesktop.org; Jani Nikula; Navare, Manasi D; Stephane
Marchesin; Puthikorn Voravootivat
Subject: [PATCH v8 1/5] drm/i915: Drop AUX backlight enable check for backlight
control
There are some panel that
(1) does not support display backlight enable via AUX
(2) support display backlight adjustment via AUX
(3) support display backlight enable via eDP BL_ENABLE pin
The current driver required that (1) must be support to enable (2).
This patch drops that requirement.
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
index b87c5a381d6a..d32c06583e0b 100644
--- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -165,7 +165,6 @@ intel_dp_aux_display_control_capable(struct intel_connector
*connector)
* the panel can support backlight control over the aux channel
*/
if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
- (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) &&
!((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_PIN_ENABLE_CAP) ||
(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP))) {
--
2.13.0.303.g4ebf302169-goog
^ still has the problem I mentioned last time. How about this?
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
index b87c5a3..7072bcf 100644
--- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -28,6 +28,10 @@ static void set_aux_backlight_enable(struct intel_dp
*intel_dp, bool enable)
{
uint8_t reg_val = 0;
+ /* Early return when display use other mechanism to enable backlight. */
+ if (!(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP))
+ return;
+
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
®_val) < 0) {
DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
@@ -165,10 +169,8 @@ intel_dp_aux_display_control_capable(struct
intel_connector *connector)
* the panel can support backlight control over the aux channel
*/
if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
- (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) &&
- !((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_PIN_ENABLE_CAP) ||
- (intel_dp->edp_dpcd[2] &
DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP))) {
+ !(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP))
{
DRM_DEBUG_KMS("AUX Backlight Control Supported!\n");
return true;
}
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/selftests: Pretend to be a gfx pci device
Set the class on our mock pci device to GFX. This should be useful for utilities like intel-iommu that special case gfx devices. References: https://bugs.freedesktop.org/show_bug.cgi?id=101080 Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/mock_gem_device.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c index f4edd4c6cb07..627e2aa09766 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c @@ -121,6 +121,7 @@ struct drm_i915_private *mock_gem_device(void) goto err; device_initialize(&pdev->dev); + pdev->class = PCI_BASE_CLASS_DISPLAY << 16; pdev->dev.release = release_dev; dev_set_name(&pdev->dev, "mock"); dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8 3/5] drm/i915: Add option to support dynamic backlight via DPCD
On Tue, 2017-05-16 at 17:34 -0700, Puthikorn Voravootivat wrote:
> This patch adds option to enable dynamic backlight for eDP
> panel that supports this feature via DPCD register and
> set minimum / maximum brightness to 0% and 100% of the
> normal brightness.
>
> Signed-off-by: Puthikorn Voravootivat
> ---
> drivers/gpu/drm/i915/i915_params.c| 5
> drivers/gpu/drm/i915/i915_params.h| 3 +-
> drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 40
> +++
> 3 files changed, 41 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_params.c
> b/drivers/gpu/drm/i915/i915_params.c
> index 13cf3f1572ab..6eaf660e74da 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -65,6 +65,7 @@ struct i915_params i915 __read_mostly = {
> .inject_load_failure = 0,
> .enable_dpcd_backlight = -1,
> .enable_gvt = false,
> + .enable_dbc = false,
> };
>
> module_param_named(modeset, i915.modeset, int, 0400);
> @@ -255,3 +256,7 @@ MODULE_PARM_DESC(enable_dpcd_backlight,
> module_param_named(enable_gvt, i915.enable_gvt, bool, 0400);
> MODULE_PARM_DESC(enable_gvt,
> "Enable support for Intel GVT-g graphics virtualization host
> support(default:false)");
> +
> +module_param_named(enable_dbc, i915.enable_dbc, bool, 0600);
> +MODULE_PARM_DESC(enable_dbc,
> + "Enable support for dynamic backlight control (default:false)");
> diff --git a/drivers/gpu/drm/i915/i915_params.h
> b/drivers/gpu/drm/i915/i915_params.h
> index ac02efce6e22..2de3e2850b54 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -67,7 +67,8 @@
> func(bool, nuclear_pageflip); \
> func(bool, enable_dp_mst); \
> func(int, enable_dpcd_backlight); \
> - func(bool, enable_gvt)
> + func(bool, enable_gvt); \
> + func(bool, enable_dbc)
>
> #define MEMBER(T, member) T member
> struct i915_params {
> diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> index 16ba1924308d..c0eeb8fc2013 100644
> --- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> @@ -100,10 +100,27 @@ intel_dp_aux_set_backlight(struct intel_connector
> *connector, u32 level)
> }
> }
>
> +/*
> + * Set minimum / maximum dynamic brightness percentage. This value is
> expressed
> + * as the percentage of normal brightness in 5% increments.
> + */
> +static void
> +intel_dp_aux_set_dynamic_backlight_percent(struct intel_dp *intel_dp,
> +u32 min, u32 max)
> +{
> + u8 dbc[] = { DIV_ROUND_CLOSEST(min, 5), DIV_ROUND_CLOSEST(max, 5) };
> +
> + if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET,
> + dbc, sizeof(dbc) < 0)) {
Incorrect parentheses placement and return value check.
> + DRM_DEBUG_KMS("Failed to write aux DBC brightness level\n");
> + }
> +}
> +
> static void intel_dp_aux_enable_backlight(struct intel_connector *connector)
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
> uint8_t dpcd_buf = 0;
> + uint8_t new_dpcd_buf = 0;
nit: unnecessary initialization.
> uint8_t edp_backlight_mode = 0;
>
> if (drm_dp_dpcd_readb(&intel_dp->aux,
> @@ -113,18 +130,15 @@ static void intel_dp_aux_enable_backlight(struct
> intel_connector *connector)
> return;
> }
>
> + new_dpcd_buf = dpcd_buf;
> edp_backlight_mode = dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
>
> switch (edp_backlight_mode) {
> case DP_EDP_BACKLIGHT_CONTROL_MODE_PWM:
> case DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET:
> case DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT:
> - dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
> - dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
> - if (drm_dp_dpcd_writeb(&intel_dp->aux,
> - DP_EDP_BACKLIGHT_MODE_SET_REGISTER, dpcd_buf) < 0) {
> - DRM_DEBUG_KMS("Failed to write aux backlight mode\n");
> - }
> + new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
> + new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
> break;
>
> /* Do nothing when it is already DPCD mode */
> @@ -133,6 +147,20 @@ static void intel_dp_aux_enable_backlight(struct
> intel_connector *connector)
> break;
> }
>
> + if (i915.enable_dbc &&
> + (intel_dp->edp_dpcd[2] & DP_EDP_DYNAMIC_BACKLIGHT_CAP)) {
> + new_dpcd_buf |= DP_EDP_DYNAMIC_BACKLIGHT_ENABLE;
> + intel_dp_aux_set_dynamic_backlight_percent(intel_dp, 0, 100);
> + DRM_DEBUG_KMS("Enable dynamic brightness.\n");
> + }
> +
> + if (new_dpcd_buf != dpcd_buf) {
> + if (drm_dp_dpcd_writeb(&intel_dp->aux,
> +
[Intel-gfx] [PATCH] drm/i915: Move engine HWS setup into one shared function
Similar code was duplicated in ringbuffer.c and lrc.c
Lets share the code and move it to engine_cs.c
While around, move execlist enabling into separate inline
function, as this will make future patches simpler.
Suggested-by: Chris Wilson
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Oscar Mateo
---
drivers/gpu/drm/i915/intel_engine_cs.c | 83 +
drivers/gpu/drm/i915/intel_lrc.c| 30
drivers/gpu/drm/i915/intel_ringbuffer.c | 79 +--
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
4 files changed, 105 insertions(+), 88 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 413bfd8..8a37725 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -519,6 +519,89 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
engine->context_unpin(engine, engine->i915->kernel_context);
}
+static void setup_phys_status_page(struct intel_engine_cs *engine)
+{
+ struct drm_i915_private *dev_priv = engine->i915;
+ u32 addr;
+
+ addr = dev_priv->status_page_dmah->busaddr;
+ if (INTEL_GEN(dev_priv) >= 4)
+ addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
+ I915_WRITE(HWS_PGA, addr);
+}
+
+static void setup_status_page(struct intel_engine_cs *engine)
+{
+ struct drm_i915_private *dev_priv = engine->i915;
+ i915_reg_t mmio;
+
+ /* The ring status page addresses are no longer next to the rest of
+* the ring registers as of gen7.
+*/
+ if (IS_GEN7(dev_priv)) {
+ switch (engine->id) {
+ case RCS:
+ mmio = RENDER_HWS_PGA_GEN7;
+ break;
+ case BCS:
+ mmio = BLT_HWS_PGA_GEN7;
+ break;
+ /*
+* VCS2 actually doesn't exist on Gen7. Only shut up
+* gcc switch check warning
+*/
+ case VCS2:
+ case VCS:
+ mmio = BSD_HWS_PGA_GEN7;
+ break;
+ case VECS:
+ mmio = VEBOX_HWS_PGA_GEN7;
+ break;
+ }
+ } else if (IS_GEN6(dev_priv)) {
+ mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
+ } else {
+ /* XXX: gen8 returns to sanity */
+ mmio = RING_HWS_PGA(engine->mmio_base);
+ }
+
+ I915_WRITE(mmio, engine->status_page.ggtt_offset);
+ POSTING_READ(mmio);
+
+ /*
+* Flush the TLB for this page
+*
+* FIXME: These two bits have disappeared on gen8, so a question
+* arises: do we still need this and if so how should we go about
+* invalidating the TLB?
+*/
+ if (IS_GEN(dev_priv, 6, 7)) {
+ i915_reg_t reg = RING_INSTPM(engine->mmio_base);
+
+ /* ring should be idle before issuing a sync flush*/
+ WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
+
+ I915_WRITE(reg,
+ _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
+ INSTPM_SYNC_FLUSH));
+ if (intel_wait_for_register(dev_priv,
+ reg, INSTPM_SYNC_FLUSH, 0,
+ 1000))
+ DRM_ERROR("%s: wait for SyncFlush to complete for TLB
invalidation timed out\n",
+ engine->name);
+ }
+}
+
+void intel_engine_setup_hws(struct intel_engine_cs *engine)
+{
+ struct drm_i915_private *dev_priv = engine->i915;
+
+ if (HWS_NEEDS_PHYSICAL(dev_priv))
+ setup_phys_status_page(engine);
+ else
+ setup_status_page(engine);
+}
+
u64 intel_engine_get_active_head(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 014b30a..ed7ec52 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1220,9 +1220,25 @@ static int intel_init_workaround_bb(struct
intel_engine_cs *engine)
return ret;
}
-static int gen8_init_common_ring(struct intel_engine_cs *engine)
+static void intel_engine_mask_hws(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
+
+ I915_WRITE(RING_HWSTAM(engine->mmio_base), 0x);
+}
+
+static void gen8_execlist_enable(struct intel_engine_cs *engine)
+{
+ struct drm_i915_private *dev_priv = engine->i915;
+
+ I915_WRITE(RING_MODE_GEN7(engine),
+ _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
+
+ DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
+}
+
+static int gen8_init_common_ring(struc
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Pretend to be a gfx pci device
== Series Details == Series: drm/i915/selftests: Pretend to be a gfx pci device URL : https://patchwork.freedesktop.org/series/24580/ State : failure == Summary == Series 24580v1 drm/i915/selftests: Pretend to be a gfx pci device https://patchwork.freedesktop.org/api/1.0/series/24580/revisions/1/mbox/ Test gem_exec_flush: Subgroup basic-batch-kernel-default-uc: pass -> FAIL (fi-snb-2600) fdo#17 Test gem_exec_suspend: Subgroup basic-s4-devices: pass -> DMESG-WARN (fi-snb-2600) fdo#100125 Test kms_flip: Subgroup basic-flip-vs-wf_vblank: pass -> FAIL (fi-skl-6770hq) fdo#99739 Test kms_pipe_crc_basic: Subgroup nonblocking-crc-pipe-b-frame-sequence: pass -> FAIL (fi-skl-6770hq) fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17 fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125 fdo#99739 https://bugs.freedesktop.org/show_bug.cgi?id=99739 fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:446s fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time:583s fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:513s fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:493s fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:486s fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:413s fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:414s fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:425s fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:488s fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:459s fi-kbl-7500u total:278 pass:255 dwarn:5 dfail:0 fail:0 skip:18 time:471s fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:462s fi-skl-6700hqtotal:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time:578s fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:465s fi-skl-6770hqtotal:278 pass:266 dwarn:0 dfail:0 fail:2 skip:10 time:493s fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:535s fi-snb-2600 total:278 pass:247 dwarn:1 dfail:0 fail:1 skip:29 time:407s eb3549d312620118dec3a69200894ac8a8fff358 drm-tip: 2017y-05m-17d-13h-53m-40s UTC integration manifest af6b566 drm/i915/selftests: Pretend to be a gfx pci device == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4729/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Cancel reset-engine if we couldn't find an active request
Before reseting an engine, check if there is an active request, and if
the _hung_ request has completed. In these two cases, the seqno has moved
after hang declaration and we can skip the reset.
Also store the active request so that we only search for it once, this
applies for reset-engine and full reset.
v2: Check for request completion inside _prepare_engine, don't use
ECANCELED, remove unnecessary null checks (Chris).
v3: Capture active requests during reset_prepare and store it the
engine hangcheck obj (Chris).
Suggested-by: Chris Wilson
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c | 18 ++
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/i915_gem.c | 42 +++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
4 files changed, 46 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d62793805794..771857258292 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1900,15 +1900,19 @@ int i915_reset_engine(struct intel_engine_cs *engine)
DRM_DEBUG_DRIVER("resetting %s\n", engine->name);
- ret = i915_gem_reset_prepare_engine(engine);
- if (ret) {
- DRM_ERROR("Previous reset failed - promote to full reset\n");
+ engine->hangcheck.active_request =
i915_gem_reset_prepare_engine(engine);
+ if (!engine->hangcheck.active_request) {
+ DRM_DEBUG_DRIVER("seqno moved after hang declaration,
pardoned\n");
+ goto canceled;
+ } else if (IS_ERR(engine->hangcheck.active_request)) {
+ DRM_DEBUG_DRIVER("Previous reset failed, promote to full
reset\n");
+ ret = PTR_ERR(engine->hangcheck.active_request);
goto out;
}
/*
-* the request that caused the hang is stuck on elsp, identify the
-* active request and drop it, adjust head to skip the offending
+* the request that caused the hang is stuck on elsp, we know the
+* active request and can drop it, adjust head to skip the offending
* request to resume executing remaining requests in the queue.
*/
i915_gem_reset_engine(engine);
@@ -1942,6 +1946,10 @@ int i915_reset_engine(struct intel_engine_cs *engine)
out:
return ret;
+
+canceled:
+ i915_gem_reset_finish_engine(engine);
+ return 0;
}
static int i915_pm_suspend(struct device *kdev)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a5b9c666b3bf..6cbfeaa02246 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3370,7 +3370,8 @@ static inline u32 i915_reset_count(struct i915_gpu_error
*error)
return READ_ONCE(error->reset_count);
}
-int i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
+struct drm_i915_gem_request *
+i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
void i915_gem_reset(struct drm_i915_private *dev_priv);
void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b5dc073a5ddc..5ec454dafb9f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2793,12 +2793,14 @@ static bool engine_stalled(struct intel_engine_cs
*engine)
return true;
}
-/* Ensure irq handler finishes, and not run again. */
-int i915_gem_reset_prepare_engine(struct intel_engine_cs *engine)
+/*
+ * Ensure irq handler finishes, and not run again.
+ * Also store the active request so that we only search for it once.
+ */
+struct drm_i915_gem_request *
+i915_gem_reset_prepare_engine(struct intel_engine_cs *engine)
{
- struct drm_i915_gem_request *request;
- int err = 0;
-
+ struct drm_i915_gem_request *request = NULL;
/* Prevent the signaler thread from updating the request
* state (by calling dma_fence_signal) as we are processing
@@ -2827,21 +2829,35 @@ int i915_gem_reset_prepare_engine(struct
intel_engine_cs *engine)
if (engine_stalled(engine)) {
request = i915_gem_find_active_request(engine);
- if (request && request->fence.error == -EIO)
- err = -EIO; /* Previous reset failed! */
+
+ if (request) {
+ if (request->fence.error == -EIO)
+ return ERR_PTR(-EIO); /* Previous reset failed!
*/
+
+ if (i915_gem_request_completed(request))
+ return NULL; /* request completed, skip it */
+ }
}
- return err;
+ return request;
}
int i915_gem_reset_prepare(struct drm_i915_private *dev_priv)
{
struct intel_engine_cs *engine;
+ struct drm_i915_gem_request *reque
Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Get rid of the enable_guc_loading module parameter
I like the approach.
BR,
Anusha
>-Original Message-
>From: Mateo Lozano, Oscar
>Sent: Friday, May 5, 2017 6:23 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Mateo Lozano, Oscar ; Srivatsa, Anusha
>; Ceraolo Spurio, Daniele
>; Chris Wilson
>Subject: [PATCH 1/2] drm/i915/guc: Get rid of the enable_guc_loading module
>parameter
>
>The decission to enable GuC loading shouldn't be left to the user.
>Provided the HW supports the GuC, there are only two reasons to load it:
>
>- The user has requested GuC submission.
>- We have a HuC firmware available (so we need the GuC to validate it).
>
>We leave the enable_guc_submission parameter untouched ("auto", "never", "if
>supported", "required") but make its behavior a little bit more consistent.
>Also, if
>not really required, we do not try to fetch any firmware.
>
>Cc: Anusha Srivatsa
>Cc: Daniele Ceraolo Spurio
>Cc: Chris Wilson
>Signed-off-by: Oscar Mateo
Acked-by: Anusha Srivatsa
> drivers/gpu/drm/i915/i915_debugfs.c | 10 --
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 16 +
> drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> drivers/gpu/drm/i915/i915_params.c | 6
> drivers/gpu/drm/i915/i915_params.h | 2 --
> drivers/gpu/drm/i915/intel_guc_loader.c | 48 +++
> drivers/gpu/drm/i915/intel_huc.c| 5 +--
> drivers/gpu/drm/i915/intel_uc.c | 58 +
> drivers/gpu/drm/i915/intel_uc.h | 4 +--
> drivers/gpu/drm/i915/intel_uncore.c | 3 +-
> 13 files changed, 82 insertions(+), 78 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>b/drivers/gpu/drm/i915/i915_debugfs.c
>index 870c470..e030b41 100644
>--- a/drivers/gpu/drm/i915/i915_debugfs.c
>+++ b/drivers/gpu/drm/i915/i915_debugfs.c
>@@ -2366,8 +2366,10 @@ static int i915_huc_load_status_info(struct seq_file
>*m, void *data)
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
>
>- if (!HAS_HUC_UCODE(dev_priv))
>+ if (!HAS_GUC(dev_priv)) {
>+ seq_puts(m, "No HuC support in HW\n");
> return 0;
>+ }
>
> seq_puts(m, "HuC firmware status:\n");
> seq_printf(m, "\tpath: %s\n", huc_fw->path); @@ -2399,8 +2401,10 @@
>static int i915_guc_load_status_info(struct seq_file *m, void *data)
> struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
> u32 tmp, i;
>
>- if (!HAS_GUC_UCODE(dev_priv))
>+ if (!HAS_GUC(dev_priv)) {
>+ seq_puts(m, "No GuC support in HW\n");
> return 0;
>+ }
>
> seq_printf(m, "GuC firmware status:\n");
> seq_printf(m, "\tpath: %s\n",
>@@ -2504,7 +2508,7 @@ static int i915_guc_info(struct seq_file *m, void *data)
>
> if (!guc->execbuf_client) {
> seq_printf(m, "GuC submission %s\n",
>- HAS_GUC_SCHED(dev_priv) ?
>+ HAS_GUC(dev_priv) ?
> "disabled" :
> "not supported");
> return 0;
>diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>index 72fb47a..006ed91 100644
>--- a/drivers/gpu/drm/i915/i915_drv.c
>+++ b/drivers/gpu/drm/i915/i915_drv.c
>@@ -996,7 +996,7 @@ static void intel_sanitize_options(struct drm_i915_private
>*dev_priv)
> i915.semaphores = intel_sanitize_semaphores(dev_priv,
>i915.semaphores);
> DRM_DEBUG_DRIVER("use GPU semaphores? %s\n",
>yesno(i915.semaphores));
>
>- intel_uc_sanitize_options(dev_priv);
>+ intel_guc_sanitize_submission(dev_priv);
> }
>
> /**
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index b20ed16..5d00120 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -2921,15 +2921,17 @@ static inline struct scatterlist *__sg_next(struct
>scatterlist *sg) #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)-
>>info.has_runtime_pm) #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)-
>>info.has_64bit_reloc)
>
>+#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
>+#define HAS_GUC_UCODE(dev_priv) ((dev_priv)->guc.fw.path != NULL)
>+#define HAS_HUC_UCODE(dev_priv) ((dev_priv)->huc.fw.path != NULL)
>+
> /*
>- * For now, anything with a GuC requires uCode loading, and then supports
>- * command submission once loaded. But these are logically independent
>- * properties, so we have separate macros to test them.
>+ * Only two things require us to load the GuC firmware: either we want
>+ * to enable GuC submission or we need it to to validate a HuC firmware
> */
>-#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
>-#define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
>-#define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
>-#define HAS_HUC_UCODE(dev_priv)
Re: [Intel-gfx] [PATCH] drm/i915: Cancel reset-engine if we couldn't find an active request
On Wed, May 17, 2017 at 01:41:34PM -0700, Michel Thierry wrote:
> @@ -2827,21 +2829,35 @@ int i915_gem_reset_prepare_engine(struct
> intel_engine_cs *engine)
>
> if (engine_stalled(engine)) {
> request = i915_gem_find_active_request(engine);
> - if (request && request->fence.error == -EIO)
> - err = -EIO; /* Previous reset failed! */
> +
> + if (request) {
> + if (request->fence.error == -EIO)
> + return ERR_PTR(-EIO); /* Previous reset failed!
> */
> +
> + if (i915_gem_request_completed(request))
> + return NULL; /* request completed, skip it */
This check is pointless here. We are just a few cycles since it was
known to be true. Both paths should be doing it just before the actual
reset for symmetry.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move engine HWS setup into one shared function
== Series Details == Series: drm/i915: Move engine HWS setup into one shared function URL : https://patchwork.freedesktop.org/series/24581/ State : success == Summary == Series 24581v1 drm/i915: Move engine HWS setup into one shared function https://patchwork.freedesktop.org/api/1.0/series/24581/revisions/1/mbox/ Test kms_pipe_crc_basic: Subgroup nonblocking-crc-pipe-c-frame-sequence: pass -> FAIL (fi-skl-6770hq) fdo#99788 fdo#99788 https://bugs.freedesktop.org/show_bug.cgi?id=99788 fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:440s fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time:587s fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:513s fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time:495s fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:494s fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:413s fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:410s fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:419s fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:488s fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:457s fi-kbl-7500u total:278 pass:255 dwarn:5 dfail:0 fail:0 skip:18 time:462s fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:460s fi-skl-6700hqtotal:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time:569s fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:469s fi-skl-6770hqtotal:278 pass:267 dwarn:0 dfail:0 fail:1 skip:10 time:512s fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:537s fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time:405s eb3549d312620118dec3a69200894ac8a8fff358 drm-tip: 2017y-05m-17d-13h-53m-40s UTC integration manifest 69a91c0 drm/i915: Move engine HWS setup into one shared function == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4730/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8 1/5] drm/i915: Drop AUX backlight enable check for backlight control
On Wed, May 17, 2017 at 1:09 PM, Pandiyan, Dhinakaran <
dhinakaran.pandi...@intel.com> wrote:
>
>
> From: Puthikorn Voravootivat [put...@google.com] on behalf of Puthikorn
> Voravootivat [put...@chromium.org]
> Sent: Tuesday, May 16, 2017 5:33 PM
> To: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
> Cc: dri-de...@lists.freedesktop.org; Jani Nikula; Navare, Manasi D;
> Stephane Marchesin; Puthikorn Voravootivat
> Subject: [PATCH v8 1/5] drm/i915: Drop AUX backlight enable check for
> backlight control
>
>
> There are some panel that
> (1) does not support display backlight enable via AUX
> (2) support display backlight adjustment via AUX
> (3) support display backlight enable via eDP BL_ENABLE pin
>
> The current driver required that (1) must be support to enable (2).
> This patch drops that requirement.
>
> Signed-off-by: Puthikorn Voravootivat
> ---
> drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> index b87c5a381d6a..d32c06583e0b 100644
> --- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> @@ -165,7 +165,6 @@ intel_dp_aux_display_control_capable(struct
> intel_connector *connector)
> * the panel can support backlight control over the aux channel
> */
> if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
> - (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
> (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) &&
> !((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_PIN_ENABLE_CAP) ||
> (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP))) {
> --
> 2.13.0.303.g4ebf302169-goog
>
>
> ^ still has the problem I mentioned last time. How about this?
>
>
> diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> index b87c5a3..7072bcf 100644
> --- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> @@ -28,6 +28,10 @@ static void set_aux_backlight_enable(struct intel_dp
> *intel_dp, bool enable)
> {
> uint8_t reg_val = 0;
>
> + /* Early return when display use other mechanism to enable
> backlight. */
> + if (!(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP))
> + return;
> +
> if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_
> REGISTER,
> ®_val) < 0) {
> DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
> @@ -165,10 +169,8 @@ intel_dp_aux_display_control_capable(struct
> intel_connector *connector)
> * the panel can support backlight control over the aux channel
> */
> if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP
> &&
> - (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
> (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)
> &&
> - !((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_PIN_ENABLE_CAP) ||
> - (intel_dp->edp_dpcd[2] &
> DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)))
> {
> + !(intel_dp->edp_dpcd[2] &
> DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP))
> {
> DRM_DEBUG_KMS("AUX Backlight Control Supported!\n");
> return true;
> }
>
>
> This works too. I probably misunderstood your comment as I move the code
to next patch in the set.
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