[Intel-gfx] [i-g-t PATCH] tests: do snd_hda_intel unbind before unload in module reload test
Try to make sure the snd_hda_intel module is not in use, and can be
unloaded.
Cc: Keqiao Zhang
Cc: Libin Yang
Signed-off-by: Jani Nikula
---
Keqiao, Libin, here's the script this patch is against:
https://cgit.freedesktop.org/drm/igt-gpu-tools/tree/tests/drv_module_reload_basic
---
tests/drv_module_reload_basic | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/drv_module_reload_basic b/tests/drv_module_reload_basic
index b8cad88133e9..c0676fc65db0 100755
--- a/tests/drv_module_reload_basic
+++ b/tests/drv_module_reload_basic
@@ -33,6 +33,9 @@ function reload() {
pkill alsactl
snd_hda_intel_unloaded=0
if mod_loaded snd_hda_intel; then
+ if [ -e /sys/bus/pci/drivers/snd_hda_intel/unbind ]; then
+ echo ":00:03.0" >
/sys/bus/pci/drivers/snd_hda_intel/unbind
+ fi
if rmmod snd_hda_intel; then
snd_hda_intel_unloaded=1
else
--
2.1.4
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[Intel-gfx] [i-g-t PATCH] tests: add more debugs on failure to unload snd_hda_intel
List open files under sound devices.
Signed-off-by: Jani Nikula
---
tests/drv_module_reload_basic | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/drv_module_reload_basic b/tests/drv_module_reload_basic
index c0676fc65db0..bbe11f7fe5bd 100755
--- a/tests/drv_module_reload_basic
+++ b/tests/drv_module_reload_basic
@@ -40,6 +40,7 @@ function reload() {
snd_hda_intel_unloaded=1
else
lsmod >&2
+ lsof /dev/snd/* >&2
fi
fi
--
2.1.4
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Re: [Intel-gfx] [PATCH 1/2] drm: Track drm_mm allocators and show leaks on shutdown
Am 29.10.2016 um 20:42 schrieb Chris Wilson:
We can use the kernel's stack tracer and depot to record the allocation
site of every drm_mm user and then on shutdown as well as warning that
allocated nodes still reside with the drm_mm range manager, we can also
display who allocated them to aide tracking down the leak.
Signed-off-by: Chris Wilson
Thanks, exactly what I need to debug the leaks in amdgpu as well.
Patch is Reviewed-by: Christian König .
Regards,
Christian.
---
drivers/gpu/drm/Kconfig | 12
drivers/gpu/drm/drm_mm.c | 74 ++--
include/drm/drm_mm.h | 6
3 files changed, 89 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 483059a22b1b..e339ac9ca8cf 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -300,3 +300,15 @@ config DRM_SAVAGE
chipset. If M is selected the module will be called savage.
endif # DRM_LEGACY
+
+config DRM_DEBUG_MM
+ bool "Insert extra checks for tracking the memory manager"
+ default n
+ depends on DRM
+ select STACKDEPOT
+ help
+ Enable tracking of memory manager and leak detection.
+
+ Recommended for driver developers only.
+
+ If in doubt, say "N".
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index 11d44a1e0ab3..f7d25c02297d 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -104,6 +104,66 @@ static struct drm_mm_node
*drm_mm_search_free_in_range_generic(const struct drm_
u64 end,
enum drm_mm_search_flags flags);
+#if CONFIG_DRM_DEBUG_MM
+#define STACKDEPTH 32
+#define BUFSZ 4096
+
+static noinline void save_stack(struct drm_mm_node *node)
+{
+ unsigned long entries[STACKDEPTH];
+ struct stack_trace trace = {
+ .entries = entries,
+ .max_entries = STACKDEPTH,
+ .skip = 1
+ };
+
+ save_stack_trace(&trace);
+ if (trace.nr_entries != 0 &&
+ trace.entries[trace.nr_entries-1] == ULONG_MAX)
+ trace.nr_entries--;
+
+ /* May be called under spinlock, so avoid sleeping */
+ node->stack = depot_save_stack(&trace, GFP_NOWAIT);
+}
+
+static void show_leaks(struct drm_mm *mm)
+{
+ struct drm_mm_node *node;
+ unsigned long entries[STACKDEPTH];
+ char *buf;
+
+ buf = kmalloc(BUFSZ, GFP_KERNEL);
+ if (!buf)
+ return;
+
+ list_for_each_entry(node, &mm->head_node.node_list, node_list) {
+ struct stack_trace trace = {
+ .entries = entries,
+ .max_entries = STACKDEPTH
+ };
+
+ if (!node->stack) {
+ DRM_ERROR("node [%08llx + %08llx]: unknown owner\n",
+ node->start, node->size);
+ continue;
+ }
+
+ depot_fetch_stack(node->stack, &trace);
+ snprint_stack_trace(buf, BUFSZ, &trace, 0);
+ DRM_ERROR("node [%08llx + %08llx]: inserted at\n%s",
+ node->start, node->size, buf);
+ }
+
+ kfree(buf);
+}
+
+#undef STACKDEPTH
+#undef BUFSZ
+#else
+static void save_stack(struct drm_mm_node *node) { }
+static void show_leaks(struct drm_mm *mm) { }
+#endif
+
#define START(node) ((node)->start)
#define LAST(node) ((node)->start + (node)->size - 1)
@@ -228,6 +288,8 @@ static void drm_mm_insert_helper(struct drm_mm_node *hole_node,
list_add(&node->hole_stack, &mm->hole_stack);
node->hole_follows = 1;
}
+
+ save_stack(node);
}
/**
@@ -293,6 +355,8 @@ int drm_mm_reserve_node(struct drm_mm *mm, struct
drm_mm_node *node)
node->hole_follows = 1;
}
+ save_stack(node);
+
return 0;
}
EXPORT_SYMBOL(drm_mm_reserve_node);
@@ -397,6 +461,8 @@ static void drm_mm_insert_helper_range(struct drm_mm_node
*hole_node,
list_add(&node->hole_stack, &mm->hole_stack);
node->hole_follows = 1;
}
+
+ save_stack(node);
}
/**
@@ -861,10 +927,12 @@ EXPORT_SYMBOL(drm_mm_init);
* Note that it is a bug to call this function on an allocator which is not
* clean.
*/
-void drm_mm_takedown(struct drm_mm * mm)
+void drm_mm_takedown(struct drm_mm *mm)
{
- WARN(!list_empty(&mm->head_node.node_list),
-"Memory manager not clean during takedown.\n");
+ if (WARN(!list_empty(&mm->head_node.node_list),
+"Memory manager not clean during takedown.\n"))
+ show_leaks(mm);
+
}
EXPORT_SYMBOL(drm_mm_takedown);
diff --git a/include/drm/drm_mm.h b/include/drm/drm_mm.h
index 205ddcf6d55d..41ddafe92b2f 100644
--- a/include/drm/drm_mm.h
+++ b/include/drm/drm_mm.h
@@ -44,6 +44,9 @@
#if
Re: [Intel-gfx] [i-g-t PATCH] tests: do snd_hda_intel unbind before unload in module reload test
> -Original Message-
> From: Nikula, Jani
> Sent: Monday, October 31, 2016 4:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; Zhang, Keqiao
> ; Yang, Libin
> Subject: [i-g-t PATCH] tests: do snd_hda_intel unbind before unload in
> module reload test
>
> Try to make sure the snd_hda_intel module is not in use, and can be
> unloaded.
>
> Cc: Keqiao Zhang
> Cc: Libin Yang
> Signed-off-by: Jani Nikula
>
> ---
>
> Keqiao, Libin, here's the script this patch is against:
>
> https://cgit.freedesktop.org/drm/igt-gpu-
> tools/tree/tests/drv_module_reload_basic
> ---
> tests/drv_module_reload_basic | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/tests/drv_module_reload_basic b/tests/drv_module_reload_basic
> index b8cad88133e9..c0676fc65db0 100755
> --- a/tests/drv_module_reload_basic
> +++ b/tests/drv_module_reload_basic
> @@ -33,6 +33,9 @@ function reload() {
> pkill alsactl
> snd_hda_intel_unloaded=0
> if mod_loaded snd_hda_intel; then
> + if [ -e /sys/bus/pci/drivers/snd_hda_intel/unbind ]; then
> + echo ":00:03.0" >
":00:03.0" is platform related.
We should check lspci -vvv |grep Audio to get the number.
Or we can check /sys/bus/pci/drivers/snd_hda_intel/ folder to get the number.
And sometimes there are 2 sound cards to unbind.
Regards,
Libin
> /sys/bus/pci/drivers/snd_hda_intel/unbind
> + fi
> if rmmod snd_hda_intel; then
> snd_hda_intel_unloaded=1
> else
> --
> 2.1.4
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Re: [Intel-gfx] [i-g-t PATCH] tests: do snd_hda_intel unbind before unload in module reload test
On Mon, 31 Oct 2016, "Yang, Libin" wrote:
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Monday, October 31, 2016 4:40 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani ; Zhang, Keqiao
>> ; Yang, Libin
>> Subject: [i-g-t PATCH] tests: do snd_hda_intel unbind before unload in
>> module reload test
>>
>> Try to make sure the snd_hda_intel module is not in use, and can be
>> unloaded.
>>
>> Cc: Keqiao Zhang
>> Cc: Libin Yang
>> Signed-off-by: Jani Nikula
>>
>> ---
>>
>> Keqiao, Libin, here's the script this patch is against:
>>
>> https://cgit.freedesktop.org/drm/igt-gpu-
>> tools/tree/tests/drv_module_reload_basic
>> ---
>> tests/drv_module_reload_basic | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/tests/drv_module_reload_basic b/tests/drv_module_reload_basic
>> index b8cad88133e9..c0676fc65db0 100755
>> --- a/tests/drv_module_reload_basic
>> +++ b/tests/drv_module_reload_basic
>> @@ -33,6 +33,9 @@ function reload() {
>> pkill alsactl
>> snd_hda_intel_unloaded=0
>> if mod_loaded snd_hda_intel; then
>> +if [ -e /sys/bus/pci/drivers/snd_hda_intel/unbind ]; then
>> +echo ":00:03.0" >
>
> ":00:03.0" is platform related.
> We should check lspci -vvv |grep Audio to get the number.
> Or we can check /sys/bus/pci/drivers/snd_hda_intel/ folder to get the number.
> And sometimes there are 2 sound cards to unbind.
How about this?
for f in $(find /sys/bus/pci/drivers/snd_hda_intel -name ":*" -printf %f);
do
echo $f > /sys/bus/pci/drivers/snd_hda_intel/unbind
done
BR,
Jani.
>
> Regards,
> Libin
>
>> /sys/bus/pci/drivers/snd_hda_intel/unbind
>> +fi
>> if rmmod snd_hda_intel; then
>> snd_hda_intel_unloaded=1
>> else
>> --
>> 2.1.4
>
--
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [PATCH] drm/i915: rename preliminary_hw_support to alpha_support
The term "preliminary hardware support" has always caused confusion both
among users and developers. It has always been about preliminary driver
support for new hardware, and not so much about preliminary hardware. Of
course, initially both the software and hardware are in early stages,
but the distinction becomes more clear when the user picks up production
hardware and an older kernel to go with it, with just the early support
we had for the hardware at the time the kernel was released. The user
has to specifically enable the alpha quality *driver* support for the
hardware in that specific kernel version.
Rename preliminary_hw_support to alpha_support to emphasize that the
module parameter, config option, and flag are about software, not about
hardware. Improve the language in help texts and debug logging as well.
This appears to be a good time to do the change, as there are currently
no platforms with preliminary^W alpha support.
Cc: Rob Clark
Cc: Dave Airlie
Cc: Daniel Vetter
Cc: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Kconfig | 17 +++--
drivers/gpu/drm/i915/i915_drv.h| 4 ++--
drivers/gpu/drm/i915/i915_params.c | 9 +
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/i915_pci.c| 7 ---
5 files changed, 23 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index df96aed6975a..36941afba43f 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -36,15 +36,20 @@ config DRM_I915
If "M" is selected, the module will be called i915.
-config DRM_I915_PRELIMINARY_HW_SUPPORT
- bool "Enable preliminary support for prerelease Intel hardware by
default"
+config DRM_I915_ALPHA_SUPPORT
+ bool "Enable alpha quality support for new Intel hardware by default"
depends on DRM_I915
default n
help
- Choose this option if you have prerelease Intel hardware and want the
- i915 driver to support it by default. You can enable such support at
- runtime with the module option i915.preliminary_hw_support=1; this
- option changes the default for that module option.
+ Choose this option if you have new Intel hardware and want to enable
+ the alpha quality i915 driver support for the hardware in this kernel
+ version. You can also enable the support at runtime using the module
+ parameter i915.alpha_support=1; this option changes the default for
+ that module parameter.
+
+ It is recommended to upgrade to a kernel version with proper support
+ as soon as it is available. Generally fixes for platforms with alpha
+ support are not backported to older kernels.
If in doubt, say "N".
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 42a499681966..abddafba6220 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -668,7 +668,7 @@ struct intel_csr {
func(is_skylake); \
func(is_broxton); \
func(is_kabylake); \
- func(is_preliminary); \
+ func(is_alpha_support); \
/* Keep has_* in alphabetical order */ \
func(has_csr); \
func(has_ddi); \
@@ -2782,7 +2782,7 @@ struct drm_i915_cmd_table {
#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
-#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
+#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
#define SKL_REVID_A0 0x0
#define SKL_REVID_B0 0x1
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 629e4334719c..d46ffe7086bc 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -39,7 +39,7 @@ struct i915_params i915 __read_mostly = {
.enable_hangcheck = true,
.enable_ppgtt = -1,
.enable_psr = -1,
- .preliminary_hw_support =
IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT),
+ .alpha_support = IS_ENABLED(CONFIG_DRM_I915_ALPHA_SUPPORT),
.disable_power_well = -1,
.enable_ips = 1,
.fastboot = 0,
@@ -145,9 +145,10 @@ MODULE_PARM_DESC(enable_psr, "Enable PSR "
"(0=disabled, 1=enabled - link mode chosen per-platform,
2=force link-standby mode, 3=force link-off mode) "
"Default: -1 (use per-chip default)");
-module_param_named_unsafe(preliminary_hw_support, i915.preliminary_hw_support,
int, 0400);
-MODULE_PARM_DESC(preliminary_hw_support,
- "Enable preliminary hardware support.");
+module_param_named_unsafe(alpha_support, i915.alpha_support, int, 0400);
+MODULE_PARM_DESC(alpha_support,
+ "Enable alpha quality driver support for latest hardware. "
+ "See also CONFIG_DRM_I915_ALPHA_SUPPORT.");
module_param_named_unsafe(di
[Intel-gfx] [PATCH 1/6] drm/i915: Use the full hammer when shutting down the rcu tasks
To flush all call_rcu() tasks (here from i915_gem_free_object()) we need
to call rcu_barrier() (not synchronize_rcu()). If we don't then we may
still have objects being freed as we continue to teardown the driver -
in particular, the recently released rings may race with the memory
manager shutdown resulting in sporadic:
[ 142.217186] WARNING: CPU: 7 PID: 6185 at drivers/gpu/drm/drm_mm.c:932
drm_mm_takedown+0x2e/0x40
[ 142.217187] Memory manager not clean during takedown.
[ 142.217187] Modules linked in: i915(-) x86_pkg_temp_thermal intel_powerclamp
coretemp crct10dif_pclmul crc32_pclmul ghash_clmulni_intel lpc_ich
snd_hda_codec_realtek snd_hda_codec_generic mei_me mei snd_hda_codec_hdmi
snd_hda_codec snd_hwdep snd_hda_core snd_pcm e1000e ptp pps_core [last
unloaded: snd_hda_intel]
[ 142.217199] CPU: 7 PID: 6185 Comm: rmmod Not tainted
4.9.0-rc2-CI-Trybot_242+ #1
[ 142.217199] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS FBKT34AUS
04/24/2013
[ 142.217200] c90002ecfce0 8142dd65 c90002ecfd30
[ 142.217202] c90002ecfd20 8107e4e6 03a40778c2a8
880401355c48
[ 142.217204] 88040778c2a8 a040f3c0 a040f4a0
5621fbf8b1f0
[ 142.217206] Call Trace:
[ 142.217209] [] dump_stack+0x67/0x92
[ 142.217211] [] __warn+0xc6/0xe0
[ 142.217213] [] warn_slowpath_fmt+0x4a/0x50
[ 142.217214] [] drm_mm_takedown+0x2e/0x40
[ 142.217236] [] i915_gem_cleanup_stolen+0x1a/0x20 [i915]
[ 142.217246] [] i915_ggtt_cleanup_hw+0x31/0xb0 [i915]
[ 142.217253] [] i915_driver_cleanup_hw+0x31/0x40 [i915]
[ 142.217260] [] i915_driver_unload+0x141/0x1a0 [i915]
[ 142.217268] [] i915_pci_remove+0x14/0x20 [i915]
[ 142.217269] [] pci_device_remove+0x34/0xb0
[ 142.217271] [] __device_release_driver+0x9c/0x150
[ 142.217272] [] driver_detach+0xb6/0xc0
[ 142.217273] [] bus_remove_driver+0x53/0xd0
[ 142.217274] [] driver_unregister+0x27/0x50
[ 142.217276] [] pci_unregister_driver+0x25/0x70
[ 142.217287] [] i915_exit+0x1a/0x71 [i915]
[ 142.217289] [] SyS_delete_module+0x193/0x1e0
[ 142.217291] [] entry_SYSCALL_64_fastpath+0x1c/0xb1
[ 142.217292] ---[ end trace 6fd164859c154772 ]---
[ 142.217505] [drm:show_leaks] *ERROR* node [6b6b6b6b6b6b6b6b +
6b6b6b6b6b6b6b6b]: inserted at
[] save_stack.isra.1+0x53/0xa0
[]
drm_mm_insert_node_in_range_generic+0x2ad/0x360
[]
i915_gem_stolen_insert_node_in_range+0x93/0xe0 [i915]
[] i915_gem_object_create_stolen+0x75/0xb0
[i915]
[] intel_engine_create_ring+0x9a/0x140 [i915]
[] intel_init_ring_buffer+0xf1/0x440 [i915]
[] intel_init_render_ring_buffer+0xab/0x1b0
[i915]
[] intel_engines_init+0xc8/0x210 [i915]
[] i915_gem_init+0xac/0xf0 [i915]
[] i915_driver_load+0x9c4/0x1430 [i915]
[] i915_pci_probe+0x28/0x40 [i915]
[] pci_device_probe+0x85/0xf0
[] driver_probe_device+0x21f/0x430
[] __driver_attach+0xde/0xe0
In particular note that the node was being poisoned as we inspected the
list, a clear indication that the object is being freed as we make the
assertion.
Fixes: fbbd37b36fa5 ("drm/i915: Move object release to a freelist + worker")
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 839ce2ae38fa..ed01421e3be7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -544,8 +544,10 @@ static void i915_gem_fini(struct drm_i915_private
*dev_priv)
i915_gem_context_fini(&dev_priv->drm);
mutex_unlock(&dev_priv->drm.struct_mutex);
- synchronize_rcu();
- flush_work(&dev_priv->mm.free_work);
+ do {
+ rcu_barrier();
+ flush_work(&dev_priv->mm.free_work);
+ } while (!llist_empty(&dev_priv->mm.free_list));
WARN_ON(!list_empty(&dev_priv->context_list));
}
--
2.10.2
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[Intel-gfx] [PATCH 3/6] drm/i915: Track pages pinned due to swizzling quirk
If we have a tiled object and an unknown CPU swizzle pattern, we pin the
pages to prevent the object from being swapped out (and us corrupting
the contents as we do not know the access pattern and so cannot convert
it to linear and back to tiled on reuse). This requires us to remember
to drop the extra pinning when freeing the object, or else we trigger
warnings about the pin leak. In commit fbbd37b36fa5 ("drm/i915: Move
object release to a freelist + worker"), the object free path was
deferred to a work, but the unpinning of the quirk, along with marking
the object as reclaimable, was left on the immediate path (so that if
required we could reclaim the pages under memory pressure as early as
possible). However, this split introduced a bug where the pages we no
longer being unpinned if they were marked as unneeded.
[ 231.800401] WARNING: CPU: 1 PID: 90 at drivers/gpu/drm/i915/i915_gem.c:4275
__i915_gem_free_objects+0x326/0x3c0 [i915]
[ 231.800403] WARN_ON(i915_gem_object_has_pinned_pages(obj))
[ 231.800405] Modules linked in:
[ 231.800406] snd_hda_intel i915 snd_hda_codec_generic mei_me snd_hda_codec
coretemp snd_hwdep mei lpc_ich snd_hda_core snd_pcm e1000e ptp pps_core [last
unloaded: i915]
[ 231.800426] CPU: 1 PID: 90 Comm: kworker/1:4 Tainted: G U
4.9.0-rc2-CI-CI_DRM_1780+ #1
[ 231.800428] Hardware name: LENOVO 7465CTO/7465CTO, BIOS 6DET44WW (2.08 )
04/22/2009
[ 231.800456] Workqueue: events __i915_gem_free_work [i915]
[ 231.800459] c934fc80 8142dd65 c934fcd0
[ 231.800465] c934fcc0 8107e4e6 10b30001
1000
[ 231.800469] 88011d3db740 880130ef
880130ef5ea0
[ 231.800474] Call Trace:
[ 231.800479] [] dump_stack+0x67/0x92
[ 231.800484] [] __warn+0xc6/0xe0
[ 231.800487] [] warn_slowpath_fmt+0x4a/0x50
[ 231.800491] [] ? kmem_cache_free+0x2dc/0x340
[ 231.800520] [] __i915_gem_free_objects+0x326/0x3c0 [i915]
[ 231.800548] [] __i915_gem_free_work+0x2e/0x50 [i915]
[ 231.800552] [] process_one_work+0x1ec/0x6b0
[ 231.800555] [] ? process_one_work+0x166/0x6b0
[ 231.800558] [] worker_thread+0x49/0x490
[ 231.800561] [] ? process_one_work+0x6b0/0x6b0
[ 231.800563] [] ? process_one_work+0x6b0/0x6b0
[ 231.800566] [] kthread+0xeb/0x110
[ 231.800569] [] ? kthread_park+0x60/0x60
[ 231.800573] [] ret_from_fork+0x27/0x40
Fixes: fbbd37b36fa5 ("drm/i915: Move object release to a freelist + worker")
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h| 6 ++
drivers/gpu/drm/i915/i915_gem.c| 21 +
drivers/gpu/drm/i915/i915_gem_tiling.c | 9 +++--
3 files changed, 26 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 42a499681966..7a18bf66f797 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2304,6 +2304,12 @@ struct drm_i915_gem_object {
* pages were last acquired.
*/
bool dirty:1;
+
+ /**
+* This is set if the object has been pinned due to unknown
+* swizzling.
+*/
+ bool quirked:1;
} mm;
/** Breadcrumb of last rendering to the buffer.
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b9f540b16a45..c58b7cabe87b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2324,8 +2324,10 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj)
i915_gem_object_do_bit_17_swizzle(obj, st);
if (i915_gem_object_is_tiled(obj) &&
- dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
+ dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
__i915_gem_object_pin_pages(obj);
+ obj->mm.quirked = true;
+ }
return st;
@@ -4091,10 +4093,15 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void
*data,
if (obj->mm.pages &&
i915_gem_object_is_tiled(obj) &&
dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
- if (obj->mm.madv == I915_MADV_WILLNEED)
+ if (obj->mm.madv == I915_MADV_WILLNEED) {
+ GEM_BUG_ON(!obj->mm.quirked);
__i915_gem_object_unpin_pages(obj);
- if (args->madv == I915_MADV_WILLNEED)
+ obj->mm.quirked = false;
+ }
+ if (args->madv == I915_MADV_WILLNEED) {
__i915_gem_object_pin_pages(obj);
+ obj->mm.quirked = true;
+ }
}
if (obj->mm.madv != __I915_MADV_PURGED)
@@ -4335,14 +4342,12 @@ void i915_gem_free_object(struct drm_gem_object
*gem_obj)
{
struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
+ if (obj->mm.quirked)
+ _
[Intel-gfx] [PATCH 5/6] drm/i915: Move the recently scanned objects to the tail after shrinking
During shrinking, we walk over the list of objects searching for victims. Any that are not removed are put back into the global list. Currently, they are put back in order (at the front) which means they will be first to be scanned again. If we instead move them to the rear of the list, we will scan new potential victims on the next pass and waste less time rescanning unshrinkable objects. Normally the lists are kept in rough order to shrinking (with object least frequently used at the start), by moving just scanned objects to the rear we are acknowledging that they are still in use. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_shrinker.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c index b504ba091c4f..f4a1515737bd 100644 --- a/drivers/gpu/drm/i915/i915_gem_shrinker.c +++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c @@ -232,7 +232,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv, mutex_unlock(&obj->mm.lock); } } - list_splice(&still_in_list, phase->list); + list_splice_tail(&still_in_list, phase->list); } if (flags & I915_SHRINK_BOUND) -- 2.10.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/6] drm/i915: Discard objects from mm global_list after being shrunk
In the shrinker, we can safely remove an empty object (obj->mm.pages ==
NULL) after having discarded the pages because we are holding the
struct_mutex.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_shrinker.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c
b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index 0241658af16b..b504ba091c4f 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -226,6 +226,7 @@ i915_gem_shrink(struct drm_i915_private *dev_priv,
mutex_lock(&obj->mm.lock);
if (!obj->mm.pages) {
__i915_gem_object_invalidate(obj);
+ list_del_init(&obj->global_list);
count += obj->base.size >> PAGE_SHIFT;
}
mutex_unlock(&obj->mm.lock);
--
2.10.2
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[Intel-gfx] [PATCH 6/6] drm/i915: Store the vma in an rbtree under the object
With full-ppgtt one of the main bottlenecks is the lookup of the VMA
underneath the object. For execbuf there is merit in having a very fast
direct lookup of ctx:handle to the vma using a hashtree, but that still
leaves a large number of other lookups. One way to speed up the lookup
would be to use a rhashtable, but that requires extra allocations and
may exhibit poor worse case behaviour. An alternative is to use an
embedded rbtree, i.e. no extra allocations and deterministic behaviour,
but at the slight cost of O(lgN) lookups (instead of O(1) for
rhashtable). The major of such tree will be very shallow and so not much
slower, and still scales much, much better than the current unsorted
list.
References: https://bugs.freedesktop.org/show_bug.cgi?id=87726
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 80 +
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
3 files changed, 57 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7a18bf66f797..e923d6596cac 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2230,6 +2230,7 @@ struct drm_i915_gem_object {
/** List of VMAs backed by this object */
struct list_head vma_list;
+ struct rb_root vma_tree;
/** Stolen memory for this object, instead of being backed by shmem. */
struct drm_mm_node *stolen;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e7afad585929..aa2d21c41091 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3399,6 +3399,7 @@ void i915_vma_destroy(struct i915_vma *vma)
GEM_BUG_ON(!i915_vma_is_closed(vma));
GEM_BUG_ON(vma->fence);
+ rb_erase(&vma->obj_node, &vma->obj->vma_tree);
list_del(&vma->vm_link);
if (!i915_vma_is_ggtt(vma))
i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm));
@@ -3416,12 +3417,33 @@ void i915_vma_close(struct i915_vma *vma)
WARN_ON(i915_vma_unbind(vma));
}
+static inline int vma_compare(struct i915_vma *vma,
+ struct i915_address_space *vm,
+ const struct i915_ggtt_view *view)
+{
+ GEM_BUG_ON(view && !i915_vma_is_ggtt(vma));
+
+ if (vma->vm != vm)
+ return vma->vm - vm;
+
+ if (!view)
+ return vma->ggtt_view.type;
+
+ if (vma->ggtt_view.type != view->type)
+ return vma->ggtt_view.type - view->type;
+
+ return memcmp(&vma->ggtt_view.params,
+ &view->params,
+ sizeof(view->params));
+}
+
static struct i915_vma *
__i915_vma_create(struct drm_i915_gem_object *obj,
struct i915_address_space *vm,
const struct i915_ggtt_view *view)
{
struct i915_vma *vma;
+ struct rb_node *rb, **p;
int i;
GEM_BUG_ON(vm->closed);
@@ -3455,33 +3477,28 @@ __i915_vma_create(struct drm_i915_gem_object *obj,
if (i915_is_ggtt(vm)) {
vma->flags |= I915_VMA_GGTT;
+ list_add(&vma->obj_link, &obj->vma_list);
} else {
i915_ppgtt_get(i915_vm_to_ppgtt(vm));
+ list_add_tail(&vma->obj_link, &obj->vma_list);
}
- list_add_tail(&vma->obj_link, &obj->vma_list);
- return vma;
-}
+ rb = NULL;
+ p = &obj->vma_tree.rb_node;
+ while (*p) {
+ struct i915_vma *pos;
-static inline bool vma_matches(struct i915_vma *vma,
- struct i915_address_space *vm,
- const struct i915_ggtt_view *view)
-{
- if (vma->vm != vm)
- return false;
-
- if (!i915_vma_is_ggtt(vma))
- return true;
-
- if (!view)
- return vma->ggtt_view.type == 0;
-
- if (vma->ggtt_view.type != view->type)
- return false;
+ rb = *p;
+ pos = rb_entry(rb, struct i915_vma, obj_node);
+ if (vma_compare(pos, vm, view) < 0)
+ p = &rb->rb_right;
+ else
+ p = &rb->rb_left;
+ }
+ rb_link_node(&vma->obj_node, rb, p);
+ rb_insert_color(&vma->obj_node, &obj->vma_tree);
- return memcmp(&vma->ggtt_view.params,
- &view->params,
- sizeof(view->params)) == 0;
+ return vma;
}
struct i915_vma *
@@ -3501,11 +3518,22 @@ i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
struct i915_address_space *vm,
const struct i915_ggtt_view *view)
{
- struct i915_vma *vma;
+ struct rb_node *rb;
+
+ rb = obj->vma_tree.rb_node;
+ while (rb) {
+ struct i915_vma *vma;
+ int cmp;
- list_for_ea
[Intel-gfx] [PATCH 2/6] drm/i915: Avoid accessing request->timeline outside of its lifetime
Whilst waiting on a request, we may do so without holding any locks or any guards beyond a reference to the request. In order to avoid taking locks within request deallocation, we drop references to its timeline (via the context and ppgtt) upon retirement. We should avoid chasing such pointers outside of their control, in particular we inspect the request->timeline to see if we may restore the RPS waitboost for a client. If we instead look at the engine->timeline, we will have similar behaviour on both full-ppgtt and !full-ppgtt systems and reduce the amount of reward we give towards stalling clients (i.e. only if the client stalls and the GPU is uncontended does it reclaim its boost). This restores behaviour back to pre-timelines, whilst fixing: [ 645.078485] BUG: KASAN: use-after-free in i915_gem_object_wait_fence+0x1ee/0x2e0 at addr 8802335643a0 [ 645.078577] Read of size 4 by task gem_exec_schedu/28408 [ 645.078638] CPU: 1 PID: 28408 Comm: gem_exec_schedu Not tainted 4.9.0-rc2+ #64 [ 645.078724] Hardware name: /, BIOS PYBSWCEL.86A.0027.2015.0507.1758 05/07/2015 [ 645.078816] 88022daef9a0 8143d059 880235402a80 880233564200 [ 645.078998] 88022daef9c8 81229c5c 88022daefa48 880233564200 [ 645.079172] 880235402a80 88022daefa38 81229ef0 8110a796 [ 645.079345] Call Trace: [ 645.079404] [] dump_stack+0x68/0x9f [ 645.079467] [] kasan_object_err+0x1c/0x70 [ 645.079534] [] kasan_report_error+0x1f0/0x4b0 [ 645.079601] [] kasan_report+0x34/0x40 [ 645.079676] [] ? i915_gem_object_wait_fence+0x1ee/0x2e0 [ 645.079741] [] __asan_load4+0x61/0x80 [ 645.079807] [] i915_gem_object_wait_fence+0x1ee/0x2e0 [ 645.079876] [] i915_gem_object_wait+0x19f/0x590 [ 645.079944] [] ? i915_gem_object_wait_priority+0x500/0x500 [ 645.080016] [] ? debug_show_all_locks+0x1e0/0x1e0 [ 645.080084] [] ? check_chain_key+0x14c/0x210 [ 645.080157] [] ? __lock_is_held+0x46/0xc0 [ 645.080226] [] ? i915_gem_set_domain_ioctl+0x141/0x690 [ 645.080296] [] i915_gem_set_domain_ioctl+0x1a2/0x690 [ 645.080366] [] ? __might_fault+0x75/0xe0 [ 645.080433] [] drm_ioctl+0x327/0x640 [ 645.080508] [] ? i915_gem_obj_prepare_shmem_write+0x3a0/0x3a0 [ 645.080603] [] ? drm_ioctl_permit+0x120/0x120 [ 645.080670] [] ? check_chain_key+0x14c/0x210 [ 645.080738] [] do_vfs_ioctl+0x127/0xa20 [ 645.080804] [] ? do_mmap+0x47c/0x580 [ 645.080871] [] ? vm_mmap_pgoff+0x117/0x140 [ 645.080938] [] ? ioctl_preallocate+0x150/0x150 [ 645.081011] [] ? up_write+0x23/0x50 [ 645.081078] [] ? vm_mmap_pgoff+0x117/0x140 [ 645.081145] [] ? vma_is_stack_for_current+0x90/0x90 [ 645.081214] [] ? mark_held_locks+0x23/0xc0 [ 645.082030] [] ? __fget+0x168/0x250 [ 645.082106] [] ? entry_SYSCALL_64_fastpath+0x5/0xb1 [ 645.082176] [] ? __fget_light+0xa2/0xc0 [ 645.082242] [] SyS_ioctl+0x3c/0x70 [ 645.082309] [] entry_SYSCALL_64_fastpath+0x1c/0xb1 [ 645.082374] Object at 880233564200, in cache kmalloc-8192 size: 8192 [ 645.082431] Allocated: [ 645.082480] PID = 28408 [ 645.082535] [ 645.082566] [] save_stack_trace+0x16/0x20 [ 645.082623] [ 645.082656] [] save_stack+0x46/0xd0 [ 645.082716] [ 645.082756] [] kasan_kmalloc+0xad/0xe0 [ 645.082817] [ 645.082848] [] i915_ppgtt_create+0x52/0x220 [ 645.082908] [ 645.082941] [] i915_gem_create_context+0x396/0x560 [ 645.083027] [ 645.083059] [] i915_gem_context_create_ioctl+0x97/0xf0 [ 645.083152] [ 645.083183] [] drm_ioctl+0x327/0x640 [ 645.083243] [ 645.083274] [] do_vfs_ioctl+0x127/0xa20 [ 645.083334] [ 645.083372] [] SyS_ioctl+0x3c/0x70 [ 645.083432] [ 645.083464] [] entry_SYSCALL_64_fastpath+0x1c/0xb1 [ 645.083551] Freed: [ 645.083599] PID = 27629 [ 645.083648] [ 645.083676] [] save_stack_trace+0x16/0x20 [ 645.083738] [ 645.083770] [] save_stack+0x46/0xd0 [ 645.083830] [ 645.083862] [] kasan_slab_free+0x73/0xc0 [ 645.083922] [ 645.083961] [] kfree+0xa9/0x170 [ 645.084021] [ 645.084053] [] i915_ppgtt_release+0x100/0x180 [ 645.084139] [ 645.084171] [] i915_gem_context_free+0x1b4/0x230 [ 645.084257] [ 645.084288] [] intel_lr_context_unpin+0x192/0x230 [ 645.084380] [ 645.084413] [] i915_gem_request_retire+0x620/0x630 [ 645.084500] [ 645.085226] [] i915_gem_retire_requests+0x181/0x280 [ 645.085313] [ 645.085352] [] i915_gem_retire_work_handler+0xca/0xe0 [ 645.085440] [ 645.085471] [] process_one_work+0x4fb/0x920 [ 645.085532] [ 645.085562] [] worker_thread+0x8d/0x840 [ 645.085622] [ 645.085653] [] kthread+0x185/0x1b0 [ 645.085718] [ 645.085750] [] ret_from_fork+0x27/0x40 [ 645.085811] Memory state around the buggy address: [ 645.085869] 880233564280: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 645.085956] 880233564300: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 645.086053] >880233564380: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 645.086138]
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: rename preliminary_hw_support to alpha_support
== Series Details == Series: drm/i915: rename preliminary_hw_support to alpha_support URL : https://patchwork.freedesktop.org/series/14604/ State : failure == Summary == Series 14604v1 drm/i915: rename preliminary_hw_support to alpha_support https://patchwork.freedesktop.org/api/1.0/series/14604/revisions/1/mbox/ Test drv_module_reload_basic: pass -> DMESG-WARN (fi-ilk-650) Test gem_exec_suspend: Subgroup basic-s3: pass -> INCOMPLETE (fi-ilk-650) Test gem_ringfill: Subgroup basic-default-hang: incomplete -> PASS (fi-hsw-4770r) fi-bdw-5557u total:241 pass:226 dwarn:0 dfail:0 fail:0 skip:15 fi-bsw-n3050 total:241 pass:201 dwarn:0 dfail:0 fail:0 skip:40 fi-bxt-t5700 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28 fi-byt-j1900 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28 fi-byt-n2820 total:241 pass:209 dwarn:0 dfail:0 fail:0 skip:32 fi-hsw-4770 total:241 pass:221 dwarn:0 dfail:0 fail:0 skip:20 fi-hsw-4770r total:241 pass:220 dwarn:0 dfail:0 fail:0 skip:21 fi-ilk-650 total:76 pass:47 dwarn:1 dfail:0 fail:0 skip:27 fi-ivb-3520m total:241 pass:218 dwarn:0 dfail:0 fail:0 skip:23 fi-ivb-3770 total:241 pass:218 dwarn:0 dfail:0 fail:0 skip:23 fi-kbl-7200u total:241 pass:219 dwarn:0 dfail:0 fail:0 skip:22 fi-skl-6260u total:241 pass:227 dwarn:0 dfail:0 fail:0 skip:14 fi-skl-6700hqtotal:241 pass:220 dwarn:0 dfail:0 fail:0 skip:21 fi-skl-6700k total:241 pass:219 dwarn:1 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:241 pass:227 dwarn:0 dfail:0 fail:0 skip:14 fi-snb-2520m total:241 pass:208 dwarn:0 dfail:0 fail:0 skip:33 fi-snb-2600 total:241 pass:207 dwarn:0 dfail:0 fail:0 skip:34 bbb625b5b79bdbdefd87e68e15edaa120fe70d4f drm-intel-nightly: 2016y-10m-29d-12h-45m-44s UTC integration manifest dc85710 drm/i915: rename preliminary_hw_support to alpha_support == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2861/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [i-g-t PATCH v2] tests: do snd_hda_intel unbind before unload in module reload test
Try to make sure the snd_hda_intel module is not in use, and can be
unloaded.
v2: unbind all cards (Libin)
Cc: Keqiao Zhang
Cc: Libin Yang
Signed-off-by: Jani Nikula
---
Keqiao, Libin, here's the script this patch is against:
https://cgit.freedesktop.org/drm/igt-gpu-tools/tree/tests/drv_module_reload_basic
---
tests/drv_module_reload_basic | 5 +
1 file changed, 5 insertions(+)
diff --git a/tests/drv_module_reload_basic b/tests/drv_module_reload_basic
index b8cad88133e9..105852a56b46 100755
--- a/tests/drv_module_reload_basic
+++ b/tests/drv_module_reload_basic
@@ -33,6 +33,11 @@ function reload() {
pkill alsactl
snd_hda_intel_unloaded=0
if mod_loaded snd_hda_intel; then
+ # unbind sound cards
+ for card in $(find /sys/bus/pci/drivers/snd_hda_intel -name
":*" -printf "%f\n"); do
+ echo $card > /sys/bus/pci/drivers/snd_hda_intel/unbind
+ done
+
if rmmod snd_hda_intel; then
snd_hda_intel_unloaded=1
else
--
2.1.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915: Use the full hammer when shutting down the rcu tasks
== Series Details == Series: series starting with [1/6] drm/i915: Use the full hammer when shutting down the rcu tasks URL : https://patchwork.freedesktop.org/series/14606/ State : failure == Summary == Series 14606v1 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/14606/revisions/1/mbox/ Test drv_module_reload_basic: pass -> SKIP (fi-skl-6770hq) Test gem_exec_suspend: Subgroup basic-s3: pass -> DMESG-WARN (fi-skl-6770hq) Test gem_ringfill: Subgroup basic-default-hang: incomplete -> PASS (fi-hsw-4770r) Test kms_flip: Subgroup basic-flip-vs-wf_vblank: pass -> SKIP (fi-byt-n2820) Test kms_frontbuffer_tracking: Subgroup basic: pass -> FAIL (fi-skl-6770hq) Test kms_pipe_crc_basic: Subgroup nonblocking-crc-pipe-a-frame-sequence: pass -> DMESG-WARN (fi-ilk-650) fi-bdw-5557u total:241 pass:226 dwarn:0 dfail:0 fail:0 skip:15 fi-bsw-n3050 total:241 pass:201 dwarn:0 dfail:0 fail:0 skip:40 fi-bxt-t5700 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28 fi-byt-j1900 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28 fi-byt-n2820 total:241 pass:208 dwarn:0 dfail:0 fail:0 skip:33 fi-hsw-4770 total:241 pass:221 dwarn:0 dfail:0 fail:0 skip:20 fi-hsw-4770r total:241 pass:220 dwarn:0 dfail:0 fail:0 skip:21 fi-ilk-650 total:241 pass:186 dwarn:1 dfail:0 fail:0 skip:54 fi-ivb-3520m total:241 pass:218 dwarn:0 dfail:0 fail:0 skip:23 fi-ivb-3770 total:241 pass:218 dwarn:0 dfail:0 fail:0 skip:23 fi-kbl-7200u total:241 pass:219 dwarn:0 dfail:0 fail:0 skip:22 fi-skl-6260u total:241 pass:227 dwarn:0 dfail:0 fail:0 skip:14 fi-skl-6700hqtotal:241 pass:220 dwarn:0 dfail:0 fail:0 skip:21 fi-skl-6700k total:241 pass:219 dwarn:1 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:241 pass:224 dwarn:1 dfail:0 fail:1 skip:15 fi-snb-2520m total:241 pass:208 dwarn:0 dfail:0 fail:0 skip:33 fi-snb-2600 total:241 pass:207 dwarn:0 dfail:0 fail:0 skip:34 bbb625b5b79bdbdefd87e68e15edaa120fe70d4f drm-intel-nightly: 2016y-10m-29d-12h-45m-44s UTC integration manifest 59c8ae4 drm/i915: Store the vma in an rbtree under the object 89bc99d drm/i915: Move the recently scanned objects to the tail after shrinking 39da91c drm/i915: Discard objects from mm global_list after being shrunk c63d866 drm/i915: Track pages pinned due to swizzling quirk 002d32d drm/i915: Avoid accessing request->timeline outside of its lifetime b814cf8 drm/i915: Use the full hammer when shutting down the rcu tasks == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2862/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t v4] tests/kms_plane_multiple: CRC based atomic correctness test
On Mon, 2016-10-24 at 10:28 +0200, Daniel Vetter wrote:
> On Thu, Oct 20, 2016 at 12:27:23PM +0300, Mika Kahola wrote:
> >
> > This is a testcase with multiple planes. The idea here is the
> > following
> >
> > - draw a uniform frame with blue color
> > - grab crc for reference
> > - put planes randomly on top with the same blue color
> > - punch holes with black color into the primary framebuffer
> > - ideally the planes should cover these holes so that the output
> > is the
> > identical to reference crc
> > - composite all with one ioctl call
> > - grab crc and verify that the reference crc is equal
> > - repeat this for dozen iterations to maximize coverage
> >
> > v4: For atomic test enable crc capturing before entering into a
> > iteration loop. After each iteration, check that page flip
> > didn't take no more than 1 vblank, fetch all crc's and check
> > the values.
> >
> > Introduce new command line parameter for the number of
> > iterations.
> > The test run from 1 to 256 iterations.
> This seems real low. Screens run at usuall 50-60Hz, which means you
> just
> allow for a few seconds. I'd say for a normal validation run timing
> it to
> be 1 second (for each subtest) is a reasonable start.
>
> But for the knob we probably want to make this virtually unlimited,
> e.g.
> -1 == never stop. This would be useful for chasing hard-to-reproduct
> underruns and errors: Run testcase with unlimited iterations, it will
> die
> as soon as the first error shows up. Then try with next hack/debug
> trick
> until the test survives for hours and it all looks good ;-)
>
I was thinking this unlimited option too but then I thought it would be
safer if the test would stop at some point. Anyway, I can add this
option to the test.
> For the testcode itself I think it'd be good if at least Ville and
> Maarten
> review it, since this will be the groundwork for adding all kinds of
> atomic tests (rotation, yuv, scaling, anything else really).
> -Daniel
>
> >
> >
> > v3: Cleanup by removing separate plane array
> > For atomic, pass DRM_MODE_PAGE_FLIP_EVENT
> > Grab crc by using igt_pipe_crc_get_crc instead of
> > igt_pipe_crc_collect_crc
> > Rename nplanes variable to max_planes
> > To optimize test execution, run iterations after the modeset
> >
> > v2: Keep a logfile on random number seeds per subtest that are not
> > skipped
> > due to unmet test requirements
> >
> > Signed-off-by: Mika Kahola
> > ---
> > tests/Makefile.sources | 1 +
> > tests/kms_plane_multiple.c | 475
> > +
> > 2 files changed, 476 insertions(+)
> > create mode 100644 tests/kms_plane_multiple.c
> >
> > diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> > index 6d081c3..ffd59c1 100644
> > --- a/tests/Makefile.sources
> > +++ b/tests/Makefile.sources
> > @@ -105,6 +105,7 @@ TESTS_progs_M = \
> > kms_pipe_color \
> > kms_pipe_crc_basic \
> > kms_plane \
> > + kms_plane_multiple \
> > kms_properties \
> > kms_psr_sink_crc \
> > kms_render \
> > diff --git a/tests/kms_plane_multiple.c
> > b/tests/kms_plane_multiple.c
> > new file mode 100644
> > index 000..a18cdff
> > --- /dev/null
> > +++ b/tests/kms_plane_multiple.c
> > @@ -0,0 +1,475 @@
> > +/*
> > + * Copyright © 2016 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > obtaining a
> > + * copy of this software and associated documentation files (the
> > "Software"),
> > + * to deal in the Software without restriction, including without
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > sublicense,
> > + * and/or sell copies of the Software, and to permit persons to
> > whom the
> > + * Software is furnished to do so, subject to the following
> > conditions:
> > + *
> > + * The above copyright notice and this permission notice
> > (including the next
> > + * paragraph) shall be included in all copies or substantial
> > portions of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> > EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> > DAMAGES OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > OTHER DEALINGS
> > + * IN THE SOFTWARE.
> > + *
> > + */
> > +
> > +#include "igt.h"
> > +#include "drmtest.h"
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +IGT_TEST_DESCRIPTION("Test atomic mode setting with multiple
> > planes ");
> > +
> > +#define MAX_CRCS 1
> > +#define SIZE 128
> > +
> > +#define IN_RANGE(X, MIN, MAX) ((X) < (MIN) || (X) > (MAX) ? 16 :
> > X)
> > +
Re: [Intel-gfx] [PATCH 0/2] drm/i915/opregion: proper handling of DIDL and CADL
Hi Jani, one quick questions: What happened to those CADL patches. I was expecting them to showup in the mainstream kernel.org kernel some day, but even in 4.9rc3 I cant't find them. Best regards Rainer Am 25.08.2016 um 14:53 schrieb Jani Nikula: > This is the next iteration of [1] and [2]. Please review and/or test, > according to your abilities. > > Thanks, > Jani. > > Cc: Peter Wu > Cc: Rainer Koenig > Cc: Jan-Marek Glogowski > Cc: Maarten Lankhorst > Cc: Marcos Paulo de Souza > Cc: Paolo Stivanin > > [1] http://mid.mail-archive.com/cover.1467214151.git.jani.nikula@intel.com > [2] > http://mid.mail-archive.com/1471315782-925-1-git-send-email-marcos.souza.org@gmail.com > > Jani Nikula (2): > drm/i915: make i915 the source of acpi device ids for _DOD > drm/i915/opregion: update cadl based on actually active outputs > > drivers/gpu/drm/i915/i915_drv.h | 4 + > drivers/gpu/drm/i915/intel_display.c | 6 ++ > drivers/gpu/drm/i915/intel_drv.h | 3 + > drivers/gpu/drm/i915/intel_opregion.c | 157 > +- > 4 files changed, 74 insertions(+), 96 deletions(-) > -- Dipl.-Inf. (FH) Rainer Koenig Project Manager Linux Clients FJ EMEIA PR PSO PM&D CCD ENG SW OSS&C Fujitsu Technology Solutions Bürgermeister-Ullrich-Str. 100 86199 Augsburg Germany Telephone: +49-821-804-3321 Telefax: +49-821-804-2131 Mail: mailto:rainer.koe...@ts.fujitsu.com Internet ts.fujtsu.com Company Details ts.fujitsu.com/imprint.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/2] drm/i915/opregion: proper handling of DIDL and CADL
On Mon, 31 Oct 2016, Rainer Koenig wrote: > Hi Jani, > > one quick questions: What happened to those CADL patches. I was > expecting them to showup in the mainstream kernel.org kernel some day, > but even in 4.9rc3 I cant't find them. Basically [1] and [2] happened, no idea what went wrong, and no time to debug. BR, Jani. [1] http://mid.mail-archive.com/1472151415.3037046.706208097.7301895A@webmail.messagingengine.com [2] http://mid.mail-archive.com/34dfe08b-7646-8ea5-018e-549dc67564f2@skynet.be > > Best regards > Rainer > > Am 25.08.2016 um 14:53 schrieb Jani Nikula: >> This is the next iteration of [1] and [2]. Please review and/or test, >> according to your abilities. >> >> Thanks, >> Jani. >> >> Cc: Peter Wu >> Cc: Rainer Koenig >> Cc: Jan-Marek Glogowski >> Cc: Maarten Lankhorst >> Cc: Marcos Paulo de Souza >> Cc: Paolo Stivanin >> >> [1] http://mid.mail-archive.com/cover.1467214151.git.jani.nikula@intel.com >> [2] >> http://mid.mail-archive.com/1471315782-925-1-git-send-email-marcos.souza.org@gmail.com >> >> Jani Nikula (2): >> drm/i915: make i915 the source of acpi device ids for _DOD >> drm/i915/opregion: update cadl based on actually active outputs >> >> drivers/gpu/drm/i915/i915_drv.h | 4 + >> drivers/gpu/drm/i915/intel_display.c | 6 ++ >> drivers/gpu/drm/i915/intel_drv.h | 3 + >> drivers/gpu/drm/i915/intel_opregion.c | 157 >> +- >> 4 files changed, 74 insertions(+), 96 deletions(-) >> -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/2] drm/i915/opregion: proper handling of DIDL and CADL
On Mon, 31 Oct 2016, Jani Nikula wrote: > On Mon, 31 Oct 2016, Rainer Koenig wrote: >> Hi Jani, >> >> one quick questions: What happened to those CADL patches. I was >> expecting them to showup in the mainstream kernel.org kernel some day, >> but even in 4.9rc3 I cant't find them. > > Basically [1] and [2] happened, no idea what went wrong, and no time to > debug. Those, and virtually no positive feedback. > > BR, > Jani. > > [1] > http://mid.mail-archive.com/1472151415.3037046.706208097.7301895A@webmail.messagingengine.com > [2] http://mid.mail-archive.com/34dfe08b-7646-8ea5-018e-549dc67564f2@skynet.be > > >> >> Best regards >> Rainer >> >> Am 25.08.2016 um 14:53 schrieb Jani Nikula: >>> This is the next iteration of [1] and [2]. Please review and/or test, >>> according to your abilities. >>> >>> Thanks, >>> Jani. >>> >>> Cc: Peter Wu >>> Cc: Rainer Koenig >>> Cc: Jan-Marek Glogowski >>> Cc: Maarten Lankhorst >>> Cc: Marcos Paulo de Souza >>> Cc: Paolo Stivanin >>> >>> [1] http://mid.mail-archive.com/cover.1467214151.git.jani.nikula@intel.com >>> [2] >>> http://mid.mail-archive.com/1471315782-925-1-git-send-email-marcos.souza.org@gmail.com >>> >>> Jani Nikula (2): >>> drm/i915: make i915 the source of acpi device ids for _DOD >>> drm/i915/opregion: update cadl based on actually active outputs >>> >>> drivers/gpu/drm/i915/i915_drv.h | 4 + >>> drivers/gpu/drm/i915/intel_display.c | 6 ++ >>> drivers/gpu/drm/i915/intel_drv.h | 3 + >>> drivers/gpu/drm/i915/intel_opregion.c | 157 >>> +- >>> 4 files changed, 74 insertions(+), 96 deletions(-) >>> -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Mark up obj->mm.lock for shrinker
As we may allocate from within the obj->mm.lock we may enter the
shrinker for direct reclaim. Operating on the current object is
prevented by checking for obj->mm.pages (which is only set as the last
operation in the allocation path). However, we need to identity the
single recursion of accessing another object's obj->mm.lock as the two
locks have identical class and so appear to be the same to lockdep,
convincing it that a deadlock is possible. Use mutex_lock_nested() to
remove the false positive.
[ 2165.945734] =
[ 2165.945749] [ INFO: inconsistent lock state ]
[ 2165.945765] 4.9.0-rc2+ #2 Tainted: GW
[ 2165.945781] -
[ 2165.945796] inconsistent {RECLAIM_FS-ON-W} -> {IN-RECLAIM_FS-W} usage.
[ 2165.945816] kswapd0/62 [HC0[0]:SC0[0]:HE1:SE1] takes:
(&obj->mm.lock){+.+.?.}, at: [] i915_gem_shrink+0x29f/0x500
[i915]
[ 2165.945904] {RECLAIM_FS-ON-W} state was registered at:
[ 2165.945931] [] mark_held_locks+0x6f/0xa0
[ 2165.945956] [] lockdep_trace_alloc+0x69/0xc0
[ 2165.945982] [] kmem_cache_alloc_trace+0x33/0x2a0
[ 2165.946019] [] i915_gem_object_get_pages_stolen+0x6a/0xd0
[i915]
[ 2165.946060] [] i915_gem_object_get_pages+0x20/0x60
[i915]
[ 2165.946098] [] __i915_gem_object_get_pages+0x58/0x70 [i915]
[ 2165.946138] [] _i915_gem_object_create_stolen+0xec/0x120
[i915]
[ 2165.946177] []
i915_gem_object_create_stolen_for_preallocated+0xf3/0x3f0 [i915]
[ 2165.946222] []
intel_alloc_initial_plane_obj.isra.125+0xd3/0x200 [i915]
[ 2165.946266] [] intel_modeset_init+0x931/0x1530
[i915]
[ 2165.946301] [] i915_driver_load+0xa14/0x14a0 [i915]
[ 2165.946335] [] i915_pci_probe+0x4f/0x70 [i915]
[ 2165.946362] [] local_pci_probe+0x42/0xa0
[ 2165.946386] [] pci_device_probe+0x103/0x150
[ 2165.946411] [] driver_probe_device+0x223/0x430
[ 2165.946436] [] __driver_attach+0xe3/0xf0
[ 2165.946461] [] bus_for_each_dev+0x73/0xc0
[ 2165.946485] [] driver_attach+0x1e/0x20
[ 2165.946508] [] bus_add_driver+0x173/0x270
[ 2165.946533] [] driver_register+0x60/0xe0
[ 2165.946557] [] __pci_register_driver+0x5d/0x60
[ 2165.946606] [] soundcore_open+0x17/0x230 [soundcore]
[ 2165.946636] [] do_one_initcall+0x50/0x180
[ 2165.946661] [] do_init_module+0x5f/0x1f1
[ 2165.946685] [] load_module+0x2174/0x2a80
[ 2165.946709] [] SYSC_finit_module+0xdf/0x110
[ 2165.946734] [] SyS_finit_module+0xe/0x10
[ 2165.946758] [] entry_SYSCALL_64_fastpath+0x18/0xad
[ 2165.946776] irq event stamp: 90871
[ 2165.946788] hardirqs last enabled at (90871):
[ 2165.946805] [] __mutex_unlock_slowpath+0x11a/0x1c0
[ 2165.946823] hardirqs last disabled at (90870):
[ 2165.946839] [] __mutex_unlock_slowpath+0x5b/0x1c0
[ 2165.946856] softirqs last enabled at (90858):
[ 2165.946872] [] __do_softirq+0x39a/0x4c6
[ 2165.946887] softirqs last disabled at (90671):
[ 2165.946902] [] irq_exit+0xea/0xf0
[ 2165.946916] other info that might help us debug this:
[ 2165.946936] Possible unsafe locking scenario:
[ 2165.946955]CPU0
[ 2165.946965]
[ 2165.946975] lock(&obj->mm.lock);
[ 2165.947000]
[ 2165.947010] lock(&obj->mm.lock);
[ 2165.947035] *** DEADLOCK ***
[ 2165.947054] 2 locks held by kswapd0/62:
[ 2165.947067] #0: (shrinker_rwsem){..}, at: []
shrink_slab.part.40+0x5e/0x5d0
[ 2165.947120] #1: (&dev->struct_mutex){+.+.+.}, at: []
i915_gem_shrinker_lock+0x1b/0x60 [i915]
[ 2165.948909] stack backtrace:
[ 2165.950650] CPU: 2 PID: 62 Comm: kswapd0 Tainted: GW 4.9.0-rc2+ #2
[ 2165.951587] Hardware name: LENOVO 80MX/Lenovo E31-80, BIOS DCCN34WW(V2.03)
12/01/2015
[ 2165.952484] c9b5f8c8 b137f645 88016c5a2700
b25f20a0
[ 2165.953395] c9b5f918 b10bcecd
88010001
[ 2165.954305] 0001 000a 88016c5a2fd0
88016c5a2700
[ 2165.955240] Call Trace:
[ 2165.956170] [] dump_stack+0x68/0x93
[ 2165.957071] [] print_usage_bug+0x1dd/0x1f0
[ 2165.957979] [] mark_lock+0x559/0x5c0
[ 2165.958875] [] ?
print_shortest_lock_dependencies+0x1b0/0x1b0
[ 2165.959829] [] __lock_acquire+0x66d/0x12a0
[ 2165.960729] [] ? __slab_free+0xa1/0x340
[ 2165.961625] [] ? debug_lockdep_rcu_enabled+0x1d/0x20
[ 2165.962530] [] ? mark_held_locks+0x6f/0xa0
[ 2165.963457] [] lock_acquire+0xf0/0x1f0
[ 2165.964368] [] ? i915_gem_shrink+0x29f/0x500 [i915]
[ 2165.965269] [] ? i915_gem_shrink+0x29f/0x500 [i915]
[ 2165.966150] [] mutex_lock_nested+0x77/0x420
[ 2165.967030] [] ? i915_gem_shrink+0x29f/0x500 [i915]
[ 2165.967952] [] ?
__i915_gem_object_put_pages.part.58+0x161/0x1b0 [i915]
[ 2165.968835] [] i915_gem_shrink+0x29f/0x500 [i915]
[ 2165.969712] [] i915_gem_shrinker_scan+0x70/0xb0 [i915]
[ 2165.970591] [] shrink_slab.part.40+0x1fe/0x5d0
[ 2165.971504] [] shrink_node+0x22c/0x320
[ 2165.972371] [] kswapd+0x38b/0x9b0
[ 2165.973238] [] ? mem_cgroup_shrink_node+0x330/0x330
[ 2165.974068] [] kthread+0xff/0x120
[ 2165.974929] [] ? kthread_park+0x60/0x60
[ 2165.975847] [] ret_from_
Re: [Intel-gfx] [PATCH] drm/i915: Mark up obj->mm.lock for shrinker
On 31/10/2016 12:40, Chris Wilson wrote:
As we may allocate from within the obj->mm.lock we may enter the
shrinker for direct reclaim. Operating on the current object is
prevented by checking for obj->mm.pages (which is only set as the last
operation in the allocation path). However, we need to identity the
single recursion of accessing another object's obj->mm.lock as the two
locks have identical class and so appear to be the same to lockdep,
convincing it that a deadlock is possible. Use mutex_lock_nested() to
remove the false positive.
[ 2165.945734] =
[ 2165.945749] [ INFO: inconsistent lock state ]
[ 2165.945765] 4.9.0-rc2+ #2 Tainted: GW
[ 2165.945781] -
[ 2165.945796] inconsistent {RECLAIM_FS-ON-W} -> {IN-RECLAIM_FS-W} usage.
[ 2165.945816] kswapd0/62 [HC0[0]:SC0[0]:HE1:SE1] takes: (&obj->mm.lock){+.+.?.}, at:
[] i915_gem_shrink+0x29f/0x500 [i915]
[ 2165.945904] {RECLAIM_FS-ON-W} state was registered at:
[ 2165.945931] [] mark_held_locks+0x6f/0xa0
[ 2165.945956] [] lockdep_trace_alloc+0x69/0xc0
[ 2165.945982] [] kmem_cache_alloc_trace+0x33/0x2a0
[ 2165.946019] [] i915_gem_object_get_pages_stolen+0x6a/0xd0
[i915]
[ 2165.946060] [] i915_gem_object_get_pages+0x20/0x60
[i915]
[ 2165.946098] [] __i915_gem_object_get_pages+0x58/0x70 [i915]
[ 2165.946138] [] _i915_gem_object_create_stolen+0xec/0x120
[i915]
[ 2165.946177] []
i915_gem_object_create_stolen_for_preallocated+0xf3/0x3f0 [i915]
[ 2165.946222] []
intel_alloc_initial_plane_obj.isra.125+0xd3/0x200 [i915]
[ 2165.946266] [] intel_modeset_init+0x931/0x1530
[i915]
[ 2165.946301] [] i915_driver_load+0xa14/0x14a0 [i915]
[ 2165.946335] [] i915_pci_probe+0x4f/0x70 [i915]
[ 2165.946362] [] local_pci_probe+0x42/0xa0
[ 2165.946386] [] pci_device_probe+0x103/0x150
[ 2165.946411] [] driver_probe_device+0x223/0x430
[ 2165.946436] [] __driver_attach+0xe3/0xf0
[ 2165.946461] [] bus_for_each_dev+0x73/0xc0
[ 2165.946485] [] driver_attach+0x1e/0x20
[ 2165.946508] [] bus_add_driver+0x173/0x270
[ 2165.946533] [] driver_register+0x60/0xe0
[ 2165.946557] [] __pci_register_driver+0x5d/0x60
[ 2165.946606] [] soundcore_open+0x17/0x230 [soundcore]
[ 2165.946636] [] do_one_initcall+0x50/0x180
[ 2165.946661] [] do_init_module+0x5f/0x1f1
[ 2165.946685] [] load_module+0x2174/0x2a80
[ 2165.946709] [] SYSC_finit_module+0xdf/0x110
[ 2165.946734] [] SyS_finit_module+0xe/0x10
[ 2165.946758] [] entry_SYSCALL_64_fastpath+0x18/0xad
[ 2165.946776] irq event stamp: 90871
[ 2165.946788] hardirqs last enabled at (90871):
[ 2165.946805] [] __mutex_unlock_slowpath+0x11a/0x1c0
[ 2165.946823] hardirqs last disabled at (90870):
[ 2165.946839] [] __mutex_unlock_slowpath+0x5b/0x1c0
[ 2165.946856] softirqs last enabled at (90858):
[ 2165.946872] [] __do_softirq+0x39a/0x4c6
[ 2165.946887] softirqs last disabled at (90671):
[ 2165.946902] [] irq_exit+0xea/0xf0
[ 2165.946916] other info that might help us debug this:
[ 2165.946936] Possible unsafe locking scenario:
[ 2165.946955]CPU0
[ 2165.946965]
[ 2165.946975] lock(&obj->mm.lock);
[ 2165.947000]
[ 2165.947010] lock(&obj->mm.lock);
[ 2165.947035] *** DEADLOCK ***
[ 2165.947054] 2 locks held by kswapd0/62:
[ 2165.947067] #0: (shrinker_rwsem){..}, at: []
shrink_slab.part.40+0x5e/0x5d0
[ 2165.947120] #1: (&dev->struct_mutex){+.+.+.}, at: []
i915_gem_shrinker_lock+0x1b/0x60 [i915]
[ 2165.948909] stack backtrace:
[ 2165.950650] CPU: 2 PID: 62 Comm: kswapd0 Tainted: GW 4.9.0-rc2+ #2
[ 2165.951587] Hardware name: LENOVO 80MX/Lenovo E31-80, BIOS DCCN34WW(V2.03)
12/01/2015
[ 2165.952484] c9b5f8c8 b137f645 88016c5a2700
b25f20a0
[ 2165.953395] c9b5f918 b10bcecd
88010001
[ 2165.954305] 0001 000a 88016c5a2fd0
88016c5a2700
[ 2165.955240] Call Trace:
[ 2165.956170] [] dump_stack+0x68/0x93
[ 2165.957071] [] print_usage_bug+0x1dd/0x1f0
[ 2165.957979] [] mark_lock+0x559/0x5c0
[ 2165.958875] [] ?
print_shortest_lock_dependencies+0x1b0/0x1b0
[ 2165.959829] [] __lock_acquire+0x66d/0x12a0
[ 2165.960729] [] ? __slab_free+0xa1/0x340
[ 2165.961625] [] ? debug_lockdep_rcu_enabled+0x1d/0x20
[ 2165.962530] [] ? mark_held_locks+0x6f/0xa0
[ 2165.963457] [] lock_acquire+0xf0/0x1f0
[ 2165.964368] [] ? i915_gem_shrink+0x29f/0x500 [i915]
[ 2165.965269] [] ? i915_gem_shrink+0x29f/0x500 [i915]
[ 2165.966150] [] mutex_lock_nested+0x77/0x420
[ 2165.967030] [] ? i915_gem_shrink+0x29f/0x500 [i915]
[ 2165.967952] [] ?
__i915_gem_object_put_pages.part.58+0x161/0x1b0 [i915]
[ 2165.968835] [] i915_gem_shrink+0x29f/0x500 [i915]
[ 2165.969712] [] i915_gem_shrinker_scan+0x70/0xb0 [i915]
[ 2165.970591] [] shrink_slab.part.40+0x1fe/0x5d0
[ 2165.971504] [] shrink_node+0x22c/0x320
[ 2165.972371] [] kswapd+0x38b/0x9b0
[ 2165.973238] [] ? mem_cgroup_shrink_node+0x330/0x330
[ 2165.974068] [] kthread+0xff/0x120
[ 2165.974929] [] ? kthread_
Re: [Intel-gfx] [PATCH v2 1/4] drm: Add a new connector property for link status
On Sat, 29 Oct 2016, Manasi Navare wrote:
> A new default connector property is added for keeping
> track of whether the link is good (link training passed) or
> link is bad (link training failed). If the link status property
> is not good, then userspace should fire off a new modeset at the current
> mode even if there have not been any changes in the mode list
> or connector status.
> Also add link status connector member corersponding to the
> decoded value of link status property.
I'm still a bit uneasy about the name "link status", because I want it
to be evident that this is not just about display port link
layer. However, I don't have a good counter proposal, and it's easy to
change once we agree on everything else.
>
> v3: Add link status member to store property value locally
> (Ville Syrjala)
> v2:
> * Make this a default connector property (Daniel Vetter)
>
> Cc: dri-de...@lists.freedesktop.org
> Cc: Jani Nikula
> Cc: Daniel Vetter
> Cc: Ville Syrjala
> Cc: Chris Wilson
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/drm_connector.c | 17 +
> include/drm/drm_connector.h | 4 +++-
> include/drm/drm_crtc.h | 5 +
> include/uapi/drm/drm_mode.h | 4
> 4 files changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index 2db7fb5..d4e852f 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -243,6 +243,10 @@ int drm_connector_init(struct drm_device *dev,
> drm_object_attach_property(&connector->base,
> config->dpms_property, 0);
>
> + drm_object_attach_property(&connector->base,
> +config->link_status_property,
> +0);
> +
> if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
> drm_object_attach_property(&connector->base,
> config->prop_crtc_id, 0);
> }
> @@ -506,6 +510,12 @@ const char *drm_get_subpixel_order_name(enum
> subpixel_order order)
> };
> DRM_ENUM_NAME_FN(drm_get_dpms_name, drm_dpms_enum_list)
>
> +static const struct drm_prop_enum_list drm_link_status_enum_list[] = {
> + { DRM_MODE_LINK_STATUS_GOOD, "Good" },
> + { DRM_MODE_LINK_STATUS_BAD, "Bad" },
> +};
> +DRM_ENUM_NAME_FN(drm_get_link_status_name, drm_link_status_enum_list)
> +
> /**
> * drm_display_info_set_bus_formats - set the supported bus formats
> * @info: display info to store bus formats in
> @@ -622,6 +632,13 @@ int drm_connector_create_standard_properties(struct
> drm_device *dev)
> return -ENOMEM;
> dev->mode_config.tile_property = prop;
>
> + prop = drm_property_create_enum(dev, 0, "link-status",
> + drm_link_status_enum_list,
> + ARRAY_SIZE(drm_link_status_enum_list));
> + if (!prop)
> + return -ENOMEM;
> + dev->mode_config.link_status_property = prop;
> +
> return 0;
> }
>
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index ac9d7d8..90387a1 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -682,6 +682,9 @@ struct drm_connector {
> uint8_t num_h_tile, num_v_tile;
> uint8_t tile_h_loc, tile_v_loc;
> uint16_t tile_h_size, tile_v_size;
> +
> + /* Connector Link status for link training */
Drop the "link training" bit, this is not just about DP.
> + bool link_status;
What does it mean for link status to be true or false? Which one is good
and which one is bad? Please either name this differently, or make this
an int and expect it to have the same values as the property.
> };
>
> #define obj_to_connector(x) container_of(x, struct drm_connector, base)
> @@ -754,7 +757,6 @@ int drm_mode_create_tv_properties(struct drm_device *dev,
> int drm_mode_create_scaling_mode_property(struct drm_device *dev);
> int drm_mode_create_aspect_ratio_property(struct drm_device *dev);
> int drm_mode_create_suggested_offset_properties(struct drm_device *dev);
> -
> int drm_mode_connector_set_path_property(struct drm_connector *connector,
>const char *path);
> int drm_mode_connector_set_tile_property(struct drm_connector *connector);
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index fa1aa21..b86ca19 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -1151,6 +1151,11 @@ struct drm_mode_config {
>*/
> struct drm_property *tile_property;
> /**
> + * @link_status_property: Default connector property for link status
> + * of a connector as a result of link training.
Same about "link training".
> + */
> + struct drm_property *link_status_property;
> + /**
>* @plane_type_property: Default plane property to differentiate
>* CURSOR, PRIMARY and OVERLAY legacy uses of plane
[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Mark up obj->mm.lock for shrinker
== Series Details == Series: drm/i915: Mark up obj->mm.lock for shrinker URL : https://patchwork.freedesktop.org/series/14608/ State : warning == Summary == Series 14608v1 drm/i915: Mark up obj->mm.lock for shrinker https://patchwork.freedesktop.org/api/1.0/series/14608/revisions/1/mbox/ Test drv_module_reload_basic: pass -> DMESG-WARN (fi-hsw-4770r) Test gem_exec_suspend: Subgroup basic-s3: pass -> DMESG-WARN (fi-skl-6700hq) Test gem_ringfill: Subgroup basic-default-hang: incomplete -> PASS (fi-hsw-4770r) Test kms_cursor_legacy: Subgroup basic-flip-after-cursor-varying-size: pass -> DMESG-WARN (fi-ilk-650) Subgroup basic-flip-before-cursor-varying-size: pass -> DMESG-WARN (fi-ilk-650) Test kms_pipe_crc_basic: Subgroup hang-read-crc-pipe-b: pass -> DMESG-WARN (fi-ilk-650) Subgroup read-crc-pipe-a-frame-sequence: pass -> DMESG-WARN (fi-ilk-650) Subgroup read-crc-pipe-b-frame-sequence: pass -> DMESG-WARN (fi-ilk-650) fi-bdw-5557u total:241 pass:226 dwarn:0 dfail:0 fail:0 skip:15 fi-bsw-n3050 total:241 pass:201 dwarn:0 dfail:0 fail:0 skip:40 fi-bxt-t5700 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28 fi-byt-j1900 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28 fi-byt-n2820 total:241 pass:209 dwarn:0 dfail:0 fail:0 skip:32 fi-hsw-4770 total:241 pass:221 dwarn:0 dfail:0 fail:0 skip:20 fi-hsw-4770r total:241 pass:219 dwarn:1 dfail:0 fail:0 skip:21 fi-ilk-650 total:241 pass:182 dwarn:5 dfail:0 fail:0 skip:54 fi-ivb-3520m total:241 pass:218 dwarn:0 dfail:0 fail:0 skip:23 fi-ivb-3770 total:241 pass:218 dwarn:0 dfail:0 fail:0 skip:23 fi-kbl-7200u total:241 pass:219 dwarn:0 dfail:0 fail:0 skip:22 fi-skl-6260u total:241 pass:227 dwarn:0 dfail:0 fail:0 skip:14 fi-skl-6700hqtotal:241 pass:219 dwarn:1 dfail:0 fail:0 skip:21 fi-skl-6700k total:241 pass:219 dwarn:1 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:241 pass:227 dwarn:0 dfail:0 fail:0 skip:14 fi-snb-2520m total:241 pass:208 dwarn:0 dfail:0 fail:0 skip:33 fi-snb-2600 total:241 pass:207 dwarn:0 dfail:0 fail:0 skip:34 bbb625b5b79bdbdefd87e68e15edaa120fe70d4f drm-intel-nightly: 2016y-10m-29d-12h-45m-44s UTC integration manifest 5ac15f7 drm/i915: Mark up obj->mm.lock for shrinker == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2863/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/gen9+: Whitelist TIMESTAMP register from BLT ring (rev2)
On Fri, Oct 28, 2016 at 11:46:20AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/gen9+: Whitelist TIMESTAMP register from BLT ring (rev2) > URL : https://patchwork.freedesktop.org/series/14482/ > State : warning > > == Summary == > > Series 14482v2 drm/i915/gen9+: Whitelist TIMESTAMP register from BLT ring > https://patchwork.freedesktop.org/api/1.0/series/14482/revisions/2/mbox/ > > Test kms_flip: > Subgroup basic-flip-vs-wf_vblank: > fail -> SKIP (fi-ivb-3770) This result change is not connected to this commit. This is orginal fail: (kms_flip:8484) INFO: Expected frametime: 1us; measured 16717.2us +- 14.529us accuracy 0.52% (kms_flip:8484) CRITICAL: Test assertion failure function calibrate_ts, file kms_flip.c:1362: This is skip message: Expected frametime: 1us; measured 16717.3us +- 5.209us accuracy 0.19% Test requirement not met in function calibrate_ts, file kms_flip.c:1367: Test requirement: fabs(mean - expected) < 2*stddev vblank interval differs from modeline! expected 16665.6us, measured 16717us +- 5.209us, difference 51.7us (9.9 sigma) This looks like the same message but occured in different stages. > Test kms_pipe_crc_basic: > Subgroup nonblocking-crc-pipe-a: > pass -> DMESG-WARN (fi-ilk-650) > [ 326.380087] [drm:intel_pch_fifo_underrun_irq_handler [i915]] *ERROR* PCH transcoder B FIFO underrun This warning is not connected to this change. This is sporadic that we often see. > > fdc2de7ae3cf48c2eaee3fb05b63848790725361 drm-intel-nightly: > 2016y-10m-28d-10h-48m-07s UTC integration manifest > 8690c14 drm/i915: Whitelist TIMESTAMP register from BLT ring for gen9+ > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2846/ > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Mark up obj->mm.lock for shrinker
On Mon, Oct 31, 2016 at 01:01:52PM +, Tvrtko Ursulin wrote:
>
> On 31/10/2016 12:40, Chris Wilson wrote:
> >As we may allocate from within the obj->mm.lock we may enter the
> >shrinker for direct reclaim. Operating on the current object is
> >prevented by checking for obj->mm.pages (which is only set as the last
> >operation in the allocation path). However, we need to identity the
> >single recursion of accessing another object's obj->mm.lock as the two
> >locks have identical class and so appear to be the same to lockdep,
> >convincing it that a deadlock is possible. Use mutex_lock_nested() to
> >remove the false positive.
> >
> >[ 2165.945734] =
> >[ 2165.945749] [ INFO: inconsistent lock state ]
> >[ 2165.945765] 4.9.0-rc2+ #2 Tainted: GW
> >[ 2165.945781] -
> >[ 2165.945796] inconsistent {RECLAIM_FS-ON-W} -> {IN-RECLAIM_FS-W} usage.
> >[ 2165.945816] kswapd0/62 [HC0[0]:SC0[0]:HE1:SE1] takes:
> >(&obj->mm.lock){+.+.?.}, at: []
> >i915_gem_shrink+0x29f/0x500 [i915]
> >[ 2165.945904] {RECLAIM_FS-ON-W} state was registered at:
> >[ 2165.945931] [] mark_held_locks+0x6f/0xa0
> >[ 2165.945956] [] lockdep_trace_alloc+0x69/0xc0
> >[ 2165.945982] [] kmem_cache_alloc_trace+0x33/0x2a0
> >[ 2165.946019] []
> >i915_gem_object_get_pages_stolen+0x6a/0xd0 [i915]
> >[ 2165.946060] [] i915_gem_object_get_pages+0x20/0x60
> >[i915]
> >[ 2165.946098] [] __i915_gem_object_get_pages+0x58/0x70
> >[i915]
> >[ 2165.946138] []
> >_i915_gem_object_create_stolen+0xec/0x120 [i915]
> >[ 2165.946177] []
> >i915_gem_object_create_stolen_for_preallocated+0xf3/0x3f0 [i915]
> >[ 2165.946222] []
> >intel_alloc_initial_plane_obj.isra.125+0xd3/0x200 [i915]
> >[ 2165.946266] [] intel_modeset_init+0x931/0x1530
> >[i915]
> >[ 2165.946301] [] i915_driver_load+0xa14/0x14a0 [i915]
> >[ 2165.946335] [] i915_pci_probe+0x4f/0x70 [i915]
> >[ 2165.946362] [] local_pci_probe+0x42/0xa0
> >[ 2165.946386] [] pci_device_probe+0x103/0x150
> >[ 2165.946411] [] driver_probe_device+0x223/0x430
> >[ 2165.946436] [] __driver_attach+0xe3/0xf0
> >[ 2165.946461] [] bus_for_each_dev+0x73/0xc0
> >[ 2165.946485] [] driver_attach+0x1e/0x20
> >[ 2165.946508] [] bus_add_driver+0x173/0x270
> >[ 2165.946533] [] driver_register+0x60/0xe0
> >[ 2165.946557] [] __pci_register_driver+0x5d/0x60
> >[ 2165.946606] [] soundcore_open+0x17/0x230 [soundcore]
> >[ 2165.946636] [] do_one_initcall+0x50/0x180
> >[ 2165.946661] [] do_init_module+0x5f/0x1f1
> >[ 2165.946685] [] load_module+0x2174/0x2a80
> >[ 2165.946709] [] SYSC_finit_module+0xdf/0x110
> >[ 2165.946734] [] SyS_finit_module+0xe/0x10
> >[ 2165.946758] [] entry_SYSCALL_64_fastpath+0x18/0xad
> >[ 2165.946776] irq event stamp: 90871
> >[ 2165.946788] hardirqs last enabled at (90871):
> >[ 2165.946805] [] __mutex_unlock_slowpath+0x11a/0x1c0
> >[ 2165.946823] hardirqs last disabled at (90870):
> >[ 2165.946839] [] __mutex_unlock_slowpath+0x5b/0x1c0
> >[ 2165.946856] softirqs last enabled at (90858):
> >[ 2165.946872] [] __do_softirq+0x39a/0x4c6
> >[ 2165.946887] softirqs last disabled at (90671):
> >[ 2165.946902] [] irq_exit+0xea/0xf0
> >[ 2165.946916] other info that might help us debug this:
> >[ 2165.946936] Possible unsafe locking scenario:
> >[ 2165.946955]CPU0
> >[ 2165.946965]
> >[ 2165.946975] lock(&obj->mm.lock);
> >[ 2165.947000]
> >[ 2165.947010] lock(&obj->mm.lock);
> >[ 2165.947035] *** DEADLOCK ***
> >[ 2165.947054] 2 locks held by kswapd0/62:
> >[ 2165.947067] #0: (shrinker_rwsem){..}, at: []
> >shrink_slab.part.40+0x5e/0x5d0
> >[ 2165.947120] #1: (&dev->struct_mutex){+.+.+.}, at: []
> >i915_gem_shrinker_lock+0x1b/0x60 [i915]
> >[ 2165.948909] stack backtrace:
> >[ 2165.950650] CPU: 2 PID: 62 Comm: kswapd0 Tainted: GW 4.9.0-rc2+ #2
> >[ 2165.951587] Hardware name: LENOVO 80MX/Lenovo E31-80, BIOS
> >DCCN34WW(V2.03) 12/01/2015
> >[ 2165.952484] c9b5f8c8 b137f645 88016c5a2700
> >b25f20a0
> >[ 2165.953395] c9b5f918 b10bcecd
> >88010001
> >[ 2165.954305] 0001 000a 88016c5a2fd0
> >88016c5a2700
> >[ 2165.955240] Call Trace:
> >[ 2165.956170] [] dump_stack+0x68/0x93
> >[ 2165.957071] [] print_usage_bug+0x1dd/0x1f0
> >[ 2165.957979] [] mark_lock+0x559/0x5c0
> >[ 2165.958875] [] ?
> >print_shortest_lock_dependencies+0x1b0/0x1b0
> >[ 2165.959829] [] __lock_acquire+0x66d/0x12a0
> >[ 2165.960729] [] ? __slab_free+0xa1/0x340
> >[ 2165.961625] [] ? debug_lockdep_rcu_enabled+0x1d/0x20
> >[ 2165.962530] [] ? mark_held_locks+0x6f/0xa0
> >[ 2165.963457] [] lock_acquire+0xf0/0x1f0
> >[ 2165.964368] [] ? i915_gem_shrink+0x29f/0x500 [i915]
> >[ 2165.965269] [] ? i915_gem_shrink+0x29f/0x500 [i915]
> >[ 2165.966150] [] mutex_lock_nested+0x77/0x420
> >[ 2165.967030] [] ? i915_gem_shrink+0x29f/0x500 [i915]
> >[ 2165.967952] [] ?
> >__i915_gem_object_put_pages.part.58+0x161/0x1b0 [i
[Intel-gfx] [PATCH i-g-t] igt/gem_reg_read: update TIMESTAMP register address for gen9+
Since gen9 timestamp should be read from BLT ring (TIMESTAMP_BCSUNIT).
On gen9 reading timestamp from RENDER_RING is still working but is deprecated
with no guarantee to be supported in next steppings.
This commit require whitelist TIMESTAMP_BCSUNIT in kernel.
Cc: Chris Wilson
Signed-off-by: Andrzej Lawrynowicz
---
tests/gem_reg_read.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/tests/gem_reg_read.c b/tests/gem_reg_read.c
index 79facc1..6fdbfcb 100644
--- a/tests/gem_reg_read.c
+++ b/tests/gem_reg_read.c
@@ -43,7 +43,10 @@ struct local_drm_i915_reg_read {
#define REG_READ_IOCTL DRM_IOWR(DRM_COMMAND_BASE + 0x31, struct
local_drm_i915_reg_read)
-#define RENDER_RING_TIMESTAMP 0x2358
+#define RENDER_RING_BASE0x02000
+#define BLT_RING_BASE 0x22000
+
+#define RING_TIMESTAMP(base)(base)+0x358
static int read_register(int fd, uint64_t offset, uint64_t * val)
{
@@ -73,12 +76,20 @@ static bool check_kernel_x86_64(void)
return false;
}
+static uint64_t get_timestamp_offset(int fd)
+{
+ if (intel_gen(intel_get_drm_devid(fd)) < 9)
+ return RING_TIMESTAMP(RENDER_RING_BASE);
+ else
+ return RING_TIMESTAMP(BLT_RING_BASE);
+}
+
static bool check_timestamp(int fd)
{
int ret;
uint64_t val;
- ret = read_register(fd, RENDER_RING_TIMESTAMP | 1, &val);
+ ret = read_register(fd, get_timestamp_offset(fd) | 1, &val);
return ret == 0;
}
@@ -88,7 +99,7 @@ static int timer_query(int fd, uint64_t * val)
uint64_t offset;
int ret;
- offset = RENDER_RING_TIMESTAMP;
+ offset = get_timestamp_offset(fd);
if (has_proper_timestamp)
offset |= 1;
--
2.10.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Reorganize sprite init
On Thu, Oct 27, 2016 at 09:07:13AM +0200, Daniel Vetter wrote:
> On Tue, Oct 25, 2016 at 06:58:03PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Kill the switch statement from the sprite init code and replace with a
> > more straightforward if ladder. Now each significant evolution of the
> > sprite hardware is in its own neat box.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_sprite.c | 70
> > -
> > 1 file changed, 31 insertions(+), 39 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index 41ae7f562eec..70b50a27763e 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -1067,25 +1067,25 @@ intel_sprite_plane_create(struct drm_device *dev,
> > enum pipe pipe, int plane)
> > }
> > intel_plane->base.state = &state->base;
> >
> > - switch (INTEL_INFO(dev)->gen) {
> > - case 5:
> > - case 6:
> > + if (INTEL_GEN(dev_priv) >= 9) {
>
> Maybe do an s/dev/dev_priv/ on the function paramaters while at it? With
> or wihtout that:
I went without. Looks like the change would like to propagate quite a
bit further, so I figured I'd so a separate series for it.
>
> Reviewed-by: Daniel Vetter
Series pushed to dinq. Thanls for the review.
>
>
> > intel_plane->can_scale = true;
> > - intel_plane->max_downscale = 16;
> > - intel_plane->update_plane = ilk_update_plane;
> > - intel_plane->disable_plane = ilk_disable_plane;
> > + state->scaler_id = -1;
> >
> > - if (IS_GEN6(dev_priv)) {
> > - plane_formats = snb_plane_formats;
> > - num_plane_formats = ARRAY_SIZE(snb_plane_formats);
> > - } else {
> > - plane_formats = ilk_plane_formats;
> > - num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
> > - }
> > - break;
> > + intel_plane->update_plane = skl_update_plane;
> > + intel_plane->disable_plane = skl_disable_plane;
> > +
> > + plane_formats = skl_plane_formats;
> > + num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> > + } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> > + intel_plane->can_scale = false;
> > + intel_plane->max_downscale = 1;
> > +
> > + intel_plane->update_plane = vlv_update_plane;
> > + intel_plane->disable_plane = vlv_disable_plane;
> >
> > - case 7:
> > - case 8:
> > + plane_formats = vlv_plane_formats;
> > + num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
> > + } else if (INTEL_GEN(dev_priv) >= 7) {
> > if (IS_IVYBRIDGE(dev_priv)) {
> > intel_plane->can_scale = true;
> > intel_plane->max_downscale = 2;
> > @@ -1094,33 +1094,25 @@ intel_sprite_plane_create(struct drm_device *dev,
> > enum pipe pipe, int plane)
> > intel_plane->max_downscale = 1;
> > }
> >
> > - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> > - intel_plane->update_plane = vlv_update_plane;
> > - intel_plane->disable_plane = vlv_disable_plane;
> > + intel_plane->update_plane = ivb_update_plane;
> > + intel_plane->disable_plane = ivb_disable_plane;
> >
> > - plane_formats = vlv_plane_formats;
> > - num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
> > - } else {
> > - intel_plane->update_plane = ivb_update_plane;
> > - intel_plane->disable_plane = ivb_disable_plane;
> > + plane_formats = snb_plane_formats;
> > + num_plane_formats = ARRAY_SIZE(snb_plane_formats);
> > + } else {
> > + intel_plane->can_scale = true;
> > + intel_plane->max_downscale = 16;
> > +
> > + intel_plane->update_plane = ilk_update_plane;
> > + intel_plane->disable_plane = ilk_disable_plane;
> >
> > + if (IS_GEN6(dev_priv)) {
> > plane_formats = snb_plane_formats;
> > num_plane_formats = ARRAY_SIZE(snb_plane_formats);
> > + } else {
> > + plane_formats = ilk_plane_formats;
> > + num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
> > }
> > - break;
> > - case 9:
> > - intel_plane->can_scale = true;
> > - intel_plane->update_plane = skl_update_plane;
> > - intel_plane->disable_plane = skl_disable_plane;
> > - state->scaler_id = -1;
> > -
> > - plane_formats = skl_plane_formats;
> > - num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> > - break;
> > - default:
> > - MISSING_CASE(INTEL_INFO(dev)->gen);
> > - ret = -
[Intel-gfx] [PATCH 2/2] drm/i915/gtt: Mark tlbs dirty on clear
Now when clearing ptes can modify upper level pdp's,
we need to mark them dirty so that they will be flushed
correctly.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index cda263c..cbca332 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -707,6 +707,16 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
}
+/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
+ * the page table structures, we mark them dirty so that
+ * context switching/execlist queuing code takes extra steps
+ * to ensure that tlbs are flushed.
+ */
+static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
+{
+ ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
+}
+
/* Removes entries from a single page table, releasing it if it's empty.
* Caller can use the return value to update higher-level entries.
*/
@@ -810,6 +820,8 @@ static bool gen8_ppgtt_clear_pdp(struct i915_address_space
*vm,
}
}
+ mark_tlbs_dirty(ppgtt);
+
if (USES_FULL_48BIT_PPGTT(vm->dev) &&
bitmap_empty(pdp->used_pdpes, I915_PDPES_PER_PDP(vm->dev))) {
free_pdp(vm->dev, pdp);
@@ -1284,16 +1296,6 @@ int __must_check alloc_gen8_temp_bitmaps(unsigned long
**new_pds,
return -ENOMEM;
}
-/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
- * the page table structures, we mark them dirty so that
- * context switching/execlist queuing code takes extra steps
- * to ensure that tlbs are flushed.
- */
-static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
-{
- ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
-}
-
static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm,
struct i915_page_directory_pointer *pdp,
uint64_t start,
--
2.7.4
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[Intel-gfx] [PATCH 1/2] drm/i915/gtt: Fix pte clear range
Comparing pte index to a number of entries is wrong
when clearing a range of pte entries. Use end marker
of 'one past' to correctly point adequate number of
ptes to the scratch page.
Fixes: d209b9c3cd28 ("drm/i915/gtt: Split gen8_ppgtt_clear_pte_range")
References: https://bugs.freedesktop.org/show_bug.cgi?id=98282
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Michel Thierry
Cc: Michał Winiarski
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e7afad5..cda263c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -712,13 +712,13 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
*/
static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm,
struct i915_page_table *pt,
- uint64_t start,
- uint64_t length)
+ const uint64_t start,
+ const uint64_t length)
{
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
- unsigned int pte_start = gen8_pte_index(start);
- unsigned int num_entries = gen8_pte_count(start, length);
- uint64_t pte;
+ const unsigned int num_entries = gen8_pte_count(start, length);
+ unsigned int pte = gen8_pte_index(start);
+ unsigned int pte_end = pte + num_entries;
gen8_pte_t *pt_vaddr;
gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
I915_CACHE_LLC);
@@ -726,17 +726,20 @@ static bool gen8_ppgtt_clear_pt(struct i915_address_space
*vm,
if (WARN_ON(!px_page(pt)))
return false;
- bitmap_clear(pt->used_ptes, pte_start, num_entries);
+ bitmap_clear(pt->used_ptes, pte, num_entries);
if (bitmap_empty(pt->used_ptes, GEN8_PTES)) {
free_pt(vm->dev, pt);
return true;
}
+ if (WARN_ON_ONCE(pte_end > GEN8_PTES))
+ pte_end = GEN8_PTES;
+
pt_vaddr = kmap_px(pt);
- for (pte = pte_start; pte < num_entries; pte++)
- pt_vaddr[pte] = scratch_pte;
+ while (pte < pte_end)
+ pt_vaddr[pte++] = scratch_pte;
kunmap_px(ppgtt, pt_vaddr);
--
2.7.4
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Re: [Intel-gfx] [PATCH 5/6] drm/i915: Move the recently scanned objects to the tail after shrinking
On ma, 2016-10-31 at 10:26 +, Chris Wilson wrote: > During shrinking, we walk over the list of objects searching for > victims. Any that are not removed are put back into the global list. > Currently, they are put back in order (at the front) which means they > will be first to be scanned again. If we instead move them to the rear > of the list, we will scan new potential victims on the next pass and > waste less time rescanning unshrinkable objects. Normally the lists are > kept in rough order to shrinking (with object least frequently used at > the start), by moving just scanned objects to the rear we are > acknowledging that they are still in use. > > Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Export a function to flush the context upon pinning
On 30 October 2016 at 13:28, Chris Wilson wrote: > For legacy contexts we employ an optimisation to only flush the context > when binding into the global GTT. This avoids stalling onthe GPU when > reloading an active context. Wrap this detail up into a helper and > export it for a potential third user. (Longer term, context pinning > needs to be reworked as the current handling of switch context pins too > late and so risks eviction and corrupting the request. Plans, plans, plans.) > > Signed-off-by: Chris Wilson s/onthe/on the/ Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] tests/gem_userptr_blits: Test object invalidation more thoroughly
From: Tvrtko Ursulin
Verify that the userspace will get told if it changes to what the userptr
object backing store points to, *after* having created the GEM object.
Two variants are tested:
1. One where the object is used after it has been invalidated but while
the address space for the backing store is still invalid.
2. Second one where the backing store becomes valid immediately after the
object has been invalidated.
In both cases we want the kernel to give us -EFAULT on the buffer object in
question since the userspace is acting strangely so the driver does not want
to take part in corrupting memory.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
tests/gem_userptr_blits.c | 64 +++
1 file changed, 64 insertions(+)
diff --git a/tests/gem_userptr_blits.c b/tests/gem_userptr_blits.c
index f30e14360727..11a29ff5fdde 100644
--- a/tests/gem_userptr_blits.c
+++ b/tests/gem_userptr_blits.c
@@ -1151,6 +1151,58 @@ static void test_unmap_cycles(int fd, int expected)
test_unmap(fd, expected);
}
+/*
+ * Verify that the userspace will get told if it changes to what the userptr
+ * object backing store points to, *after* having created the GEM object.
+ *
+ * Two variants are tested:
+ * 1. One where the object is used after it has been invalidated but while
+ * the address space for the backing store is still invalid.
+ * 2. Second one where the backing store becomes valid immediately after the
+ * object has been invalidated.
+ *
+ * In both cases we want the kernel to give us -EFAULT on the buffer object in
+ * question since the userspace is acting strangely so the driver does not want
+ * to take part in corrupting memory.
+ */
+static void test_remap(int fd, bool midaccess, int expected)
+{
+ char *ptr, *ptr2, *bo_ptr;
+ uint32_t bo[2];
+ size_t map_size = sizeof(linear) + (PAGE_SIZE - 1);
+ int ret;
+
+ ptr = mmap(NULL, map_size, PROT_READ | PROT_WRITE,
+ MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
+ igt_assert(ptr != MAP_FAILED);
+
+ bo_ptr = (char *)ALIGN((unsigned long)ptr, PAGE_SIZE);
+ gem_userptr(fd, bo_ptr, sizeof(linear), 0, userptr_flags, &bo[0]);
+
+ bo[1] = create_bo(fd, 0);
+
+ copy(fd, bo[1], bo[0], 0);
+
+ ret = munmap(ptr, map_size);
+ igt_assert_eq(ret, 0);
+
+ if (midaccess)
+ copy(fd, bo[1], bo[0], expected);
+
+ ptr2 = mmap(ptr, map_size, PROT_READ | PROT_WRITE,
+ MAP_ANONYMOUS | MAP_PRIVATE | MAP_FIXED, -1, 0);
+ igt_assert(ptr2 != MAP_FAILED);
+ igt_assert(ptr2 == ptr);
+
+ copy(fd, bo[1], bo[0], expected);
+
+ gem_close(fd, bo[1]);
+ gem_close(fd, bo[0]);
+
+ ret = munmap(ptr, map_size);
+ igt_assert_eq(ret, 0);
+}
+
#define MM_STRESS_LOOPS 10
struct stress_thread_data {
@@ -1354,6 +1406,12 @@ int main(int argc, char **argv)
igt_subtest("unsync-unmap-after-close")
test_unmap_after_close(fd);
+ igt_subtest("unsync-remap")
+ test_remap(fd, false, 0);
+
+ igt_subtest("unsync-remap-access")
+ test_remap(fd, true, 0);
+
igt_subtest("coherency-unsync")
test_coherency(fd, count);
@@ -1452,6 +1510,12 @@ int main(int argc, char **argv)
igt_subtest("sync-unmap-after-close")
test_unmap_after_close(fd);
+ igt_subtest("sync-remap")
+ test_remap(fd, false, EFAULT);
+
+ igt_subtest("sync-remap-access")
+ test_remap(fd, true, EFAULT);
+
igt_subtest("stress-mm")
test_stress_mm(fd);
--
2.7.4
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/gtt: Fix pte clear range
On Mon, Oct 31, 2016 at 05:24:45PM +0200, Mika Kuoppala wrote:
> Comparing pte index to a number of entries is wrong
> when clearing a range of pte entries. Use end marker
> of 'one past' to correctly point adequate number of
> ptes to the scratch page.
>
> Fixes: d209b9c3cd28 ("drm/i915/gtt: Split gen8_ppgtt_clear_pte_range")
> References: https://bugs.freedesktop.org/show_bug.cgi?id=98282
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Michel Thierry
> Cc: Michał Winiarski
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 19 +++
> 1 file changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index e7afad5..cda263c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -712,13 +712,13 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt
> *ppgtt,
> */
> static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm,
> struct i915_page_table *pt,
> - uint64_t start,
> - uint64_t length)
> + const uint64_t start,
> + const uint64_t length)
> {
> struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
> - unsigned int pte_start = gen8_pte_index(start);
> - unsigned int num_entries = gen8_pte_count(start, length);
> - uint64_t pte;
> + const unsigned int num_entries = gen8_pte_count(start, length);
> + unsigned int pte = gen8_pte_index(start);
> + unsigned int pte_end = pte + num_entries;
> gen8_pte_t *pt_vaddr;
> gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
>I915_CACHE_LLC);
> @@ -726,17 +726,20 @@ static bool gen8_ppgtt_clear_pt(struct
> i915_address_space *vm,
> if (WARN_ON(!px_page(pt)))
> return false;
>
> - bitmap_clear(pt->used_ptes, pte_start, num_entries);
> + bitmap_clear(pt->used_ptes, pte, num_entries);
>
> if (bitmap_empty(pt->used_ptes, GEN8_PTES)) {
> free_pt(vm->dev, pt);
> return true;
> }
>
> + if (WARN_ON_ONCE(pte_end > GEN8_PTES))
> + pte_end = GEN8_PTES;
Internal programming error, if you hit all the upper layers are dead,
i.e. bug on. GEM_BUG_ON.
And the assert should be earlier since you have already used the invalid
values (i.e. pte+num_entries).
> +
> pt_vaddr = kmap_px(pt);
>
> - for (pte = pte_start; pte < num_entries; pte++)
Nice catch.
R-b on this part, less enamoured with the reset.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915/gtt: Fix pte clear range
== Series Details == Series: series starting with [1/2] drm/i915/gtt: Fix pte clear range URL : https://patchwork.freedesktop.org/series/14620/ State : warning == Summary == Series 14620v1 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/14620/revisions/1/mbox/ Test drv_module_reload_basic: pass -> DMESG-WARN (fi-kbl-7200u) dmesg-warn -> PASS (fi-ilk-650) dmesg-warn -> PASS (fi-bdw-5557u) Test gem_exec_suspend: Subgroup basic-s3: dmesg-warn -> PASS (fi-ilk-650) Test kms_force_connector_basic: Subgroup force-connector-state: pass -> DMESG-WARN (fi-snb-2520m) Subgroup force-edid: dmesg-warn -> PASS (fi-snb-2520m) Test kms_pipe_crc_basic: Subgroup bad-nb-words-3: dmesg-warn -> PASS (fi-ilk-650) Subgroup bad-source: dmesg-warn -> PASS (fi-ilk-650) Subgroup hang-read-crc-pipe-b: dmesg-warn -> PASS (fi-ilk-650) Subgroup nonblocking-crc-pipe-a-frame-sequence: pass -> DMESG-WARN (fi-ilk-650) Subgroup read-crc-pipe-b-frame-sequence: pass -> DMESG-WARN (fi-ilk-650) Subgroup suspend-read-crc-pipe-a: dmesg-warn -> PASS (fi-ilk-650) fi-bdw-5557u total:241 pass:226 dwarn:0 dfail:0 fail:0 skip:15 fi-bsw-n3050 total:241 pass:201 dwarn:0 dfail:0 fail:0 skip:40 fi-bxt-t5700 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28 fi-byt-j1900 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28 fi-byt-n2820 total:241 pass:209 dwarn:0 dfail:0 fail:0 skip:32 fi-hsw-4770 total:241 pass:221 dwarn:0 dfail:0 fail:0 skip:20 fi-hsw-4770r total:241 pass:220 dwarn:0 dfail:0 fail:0 skip:21 fi-ilk-650 total:241 pass:185 dwarn:2 dfail:0 fail:0 skip:54 fi-ivb-3520m total:241 pass:218 dwarn:0 dfail:0 fail:0 skip:23 fi-ivb-3770 total:241 pass:218 dwarn:0 dfail:0 fail:0 skip:23 fi-kbl-7200u total:241 pass:218 dwarn:1 dfail:0 fail:0 skip:22 fi-skl-6260u total:241 pass:227 dwarn:0 dfail:0 fail:0 skip:14 fi-skl-6700hqtotal:241 pass:220 dwarn:0 dfail:0 fail:0 skip:21 fi-skl-6700k total:241 pass:219 dwarn:1 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:241 pass:227 dwarn:0 dfail:0 fail:0 skip:14 fi-snb-2520m total:241 pass:207 dwarn:1 dfail:0 fail:0 skip:33 fi-snb-2600 total:241 pass:207 dwarn:0 dfail:0 fail:0 skip:34 6a1197bcb5cc18a56ad4ae8e6d706a212bc3db7d drm-intel-nightly: 2016y-10m-31d-14h-58m-16s UTC integration manifest d5c25c9 drm/i915/gtt: Mark tlbs dirty on clear a6d3d38 drm/i915/gtt: Fix pte clear range == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2864/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/gtt: Mark tlbs dirty on clear
On Mon, Oct 31, 2016 at 05:24:46PM +0200, Mika Kuoppala wrote: > Now when clearing ptes can modify upper level pdp's, > we need to mark them dirty so that they will be flushed > correctly. I suppose so. I think we could push this into the cleanup_px() (and alloc) but that is probably a fair chunk of work for immeasurable gain. Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/gtt: Fix pte clear range
Comparing pte index to a number of entries is wrong
when clearing a range of pte entries. Use end marker
of 'one past' to correctly point adequate number of
ptes to the scratch page.
v2: assert early instead of warning late (Chris)
Fixes: d209b9c3cd28 ("drm/i915/gtt: Split gen8_ppgtt_clear_pte_range")
References: https://bugs.freedesktop.org/show_bug.cgi?id=98282
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Michel Thierry
Cc: Michał Winiarski
Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e7afad5..5f5008f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -712,13 +712,13 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
*/
static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm,
struct i915_page_table *pt,
- uint64_t start,
- uint64_t length)
+ const uint64_t start,
+ const uint64_t length)
{
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
- unsigned int pte_start = gen8_pte_index(start);
- unsigned int num_entries = gen8_pte_count(start, length);
- uint64_t pte;
+ const unsigned int num_entries = gen8_pte_count(start, length);
+ unsigned int pte = gen8_pte_index(start);
+ unsigned int pte_end = pte + num_entries;
gen8_pte_t *pt_vaddr;
gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
I915_CACHE_LLC);
@@ -726,7 +726,9 @@ static bool gen8_ppgtt_clear_pt(struct i915_address_space
*vm,
if (WARN_ON(!px_page(pt)))
return false;
- bitmap_clear(pt->used_ptes, pte_start, num_entries);
+ GEM_BUG_ON(pte_end > GEN8_PTES);
+
+ bitmap_clear(pt->used_ptes, pte, num_entries);
if (bitmap_empty(pt->used_ptes, GEN8_PTES)) {
free_pt(vm->dev, pt);
@@ -735,8 +737,8 @@ static bool gen8_ppgtt_clear_pt(struct i915_address_space
*vm,
pt_vaddr = kmap_px(pt);
- for (pte = pte_start; pte < num_entries; pte++)
- pt_vaddr[pte] = scratch_pte;
+ while (pte < pte_end)
+ pt_vaddr[pte++] = scratch_pte;
kunmap_px(ppgtt, pt_vaddr);
--
2.7.4
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/gtt: Mark tlbs dirty on clear
Chris Wilson writes: > On Mon, Oct 31, 2016 at 05:24:46PM +0200, Mika Kuoppala wrote: >> Now when clearing ptes can modify upper level pdp's, >> we need to mark them dirty so that they will be flushed >> correctly. > > I suppose so. It is a bit iffy if we really do, but this way we gain symmetry with the alloc side. I pondered why this is missing from 4l side, but in there the topmost pointer is static. -Mika > I think we could push this into the cleanup_px() (and > alloc) but that is probably a fair chunk of work for immeasurable gain. > Reviewed-by: Chris Wilson > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/4] drm/i915: Set link status property for DP connector
On Sat, 29 Oct 2016, Manasi Navare wrote:
> This defines a helper function to set the property value.
> This will be used to set the link status to Bad in case
> of link training failures.
>
> v2:
> * Simplify the return value (Jani Nikula)
>
> Cc: dri-de...@lists.freedesktop.org
> Cc: Jani Nikula
> Cc: Daniel Vetter
> Cc: Ville Syrjala
> Cc: Chris Wilson
> Signed-off-by: Manasi Navare
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_dp.c | 11 +++
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1063afe..2b6f51c 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4640,6 +4640,17 @@ static int intel_dp_get_modes(struct drm_connector
> *connector)
> return 0;
> }
>
> +int
> +intel_dp_set_link_status_property(struct drm_connector *connector,
> + uint64_t val)
> +{
> + struct drm_device *dev = connector->dev;
> +
> + return drm_object_property_set_value(&connector->base,
> +
> dev->mode_config.link_status_property,
> + val);
> +}
> +
> static int
> intel_dp_connector_register(struct drm_connector *connector)
> {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 2616d92..3cb7481 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1391,6 +1391,8 @@ u32 skl_plane_stride(const struct drm_framebuffer *fb,
> int plane,
> bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port
> port);
> bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>struct intel_connector *intel_connector);
> +int intel_dp_set_link_status_property(struct drm_connector *connector,
> + uint64_t val);
> void intel_dp_set_link_params(struct intel_dp *intel_dp,
> int link_rate, uint8_t lane_count,
> bool link_mst);
--
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915/gtt: Fix pte clear range (rev2)
== Series Details == Series: series starting with [1/2] drm/i915/gtt: Fix pte clear range (rev2) URL : https://patchwork.freedesktop.org/series/14620/ State : warning == Summary == Series 14620v2 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/14620/revisions/2/mbox/ Test drv_module_reload_basic: dmesg-warn -> PASS (fi-bdw-5557u) pass -> SKIP (fi-skl-6770hq) dmesg-warn -> PASS (fi-ilk-650) Test gem_exec_suspend: Subgroup basic-s3: dmesg-warn -> PASS (fi-ilk-650) Test kms_cursor_legacy: Subgroup basic-flip-after-cursor-varying-size: pass -> DMESG-WARN (fi-ilk-650) Test kms_force_connector_basic: Subgroup force-edid: dmesg-warn -> PASS (fi-snb-2520m) Test kms_pipe_crc_basic: Subgroup bad-nb-words-3: dmesg-warn -> PASS (fi-ilk-650) Subgroup bad-source: dmesg-warn -> PASS (fi-ilk-650) Subgroup hang-read-crc-pipe-a: pass -> DMESG-WARN (fi-ilk-650) Subgroup hang-read-crc-pipe-b: dmesg-warn -> PASS (fi-ilk-650) Subgroup nonblocking-crc-pipe-b: pass -> DMESG-WARN (fi-ilk-650) Subgroup read-crc-pipe-b: pass -> DMESG-WARN (fi-ilk-650) Subgroup read-crc-pipe-b-frame-sequence: pass -> DMESG-WARN (fi-ilk-650) Subgroup suspend-read-crc-pipe-a: dmesg-warn -> PASS (fi-ilk-650) Subgroup suspend-read-crc-pipe-b: pass -> DMESG-WARN (fi-ilk-650) fi-bdw-5557u total:241 pass:226 dwarn:0 dfail:0 fail:0 skip:15 fi-bsw-n3050 total:241 pass:201 dwarn:0 dfail:0 fail:0 skip:40 fi-bxt-t5700 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28 fi-byt-j1900 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28 fi-byt-n2820 total:241 pass:209 dwarn:0 dfail:0 fail:0 skip:32 fi-hsw-4770 total:241 pass:221 dwarn:0 dfail:0 fail:0 skip:20 fi-hsw-4770r total:241 pass:220 dwarn:0 dfail:0 fail:0 skip:21 fi-ilk-650 total:241 pass:181 dwarn:6 dfail:0 fail:0 skip:54 fi-ivb-3520m total:241 pass:218 dwarn:0 dfail:0 fail:0 skip:23 fi-ivb-3770 total:241 pass:218 dwarn:0 dfail:0 fail:0 skip:23 fi-kbl-7200u total:241 pass:219 dwarn:0 dfail:0 fail:0 skip:22 fi-skl-6260u total:241 pass:227 dwarn:0 dfail:0 fail:0 skip:14 fi-skl-6700hqtotal:241 pass:220 dwarn:0 dfail:0 fail:0 skip:21 fi-skl-6700k total:241 pass:219 dwarn:1 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:241 pass:226 dwarn:0 dfail:0 fail:0 skip:15 fi-snb-2520m total:241 pass:208 dwarn:0 dfail:0 fail:0 skip:33 fi-snb-2600 total:241 pass:207 dwarn:0 dfail:0 fail:0 skip:34 6a1197bcb5cc18a56ad4ae8e6d706a212bc3db7d drm-intel-nightly: 2016y-10m-31d-14h-58m-16s UTC integration manifest e857e29 drm/i915/gtt: Mark tlbs dirty on clear c6d35e9 drm/i915/gtt: Fix pte clear range == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2865/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] tests/gem_userptr_blits: Test object invalidation more thoroughly
On Mon, Oct 31, 2016 at 03:36:15PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Verify that the userspace will get told if it changes to what the userptr
> object backing store points to, *after* having created the GEM object.
>
> Two variants are tested:
> 1. One where the object is used after it has been invalidated but while
> the address space for the backing store is still invalid.
> 2. Second one where the backing store becomes valid immediately after the
> object has been invalidated.
>
> In both cases we want the kernel to give us -EFAULT on the buffer object in
> question since the userspace is acting strangely so the driver does not want
> to take part in corrupting memory.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Chris Wilson
> ---
> tests/gem_userptr_blits.c | 64
> +++
> 1 file changed, 64 insertions(+)
>
> diff --git a/tests/gem_userptr_blits.c b/tests/gem_userptr_blits.c
> index f30e14360727..11a29ff5fdde 100644
> --- a/tests/gem_userptr_blits.c
> +++ b/tests/gem_userptr_blits.c
> @@ -1151,6 +1151,58 @@ static void test_unmap_cycles(int fd, int expected)
> test_unmap(fd, expected);
> }
>
> +/*
> + * Verify that the userspace will get told if it changes to what the userptr
> + * object backing store points to, *after* having created the GEM object.
> + *
> + * Two variants are tested:
> + * 1. One where the object is used after it has been invalidated but while
> + * the address space for the backing store is still invalid.
> + * 2. Second one where the backing store becomes valid immediately after
> the
> + * object has been invalidated.
We still end up with inconsistent behaviour because we do a deferred
gup, and only store ourselves in the mmu tree whilst we have pages. To
close that we would have to add ourselves to the mmutree during
creation (restructuring it to keep the lazy gup).
Current holes would be between creation and execbuf, or swap-out and
execbuf. What we currently check is that the location is valid at the
time of use, not that the contents match both clients expectations.
My concern with using the mmu invalidate notify was that it may kick a
legitimate object. I will have to go and check to see if that is a valid
concern.
> + * In both cases we want the kernel to give us -EFAULT on the buffer object
> in
> + * question since the userspace is acting strangely so the driver does not
> want
> + * to take part in corrupting memory.
> + */
> +static void test_remap(int fd, bool midaccess, int expected)
> +{
> + char *ptr, *ptr2, *bo_ptr;
> + uint32_t bo[2];
> + size_t map_size = sizeof(linear) + (PAGE_SIZE - 1);
> + int ret;
> +
> + ptr = mmap(NULL, map_size, PROT_READ | PROT_WRITE,
> +MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
> + igt_assert(ptr != MAP_FAILED);
> +
> + bo_ptr = (char *)ALIGN((unsigned long)ptr, PAGE_SIZE);
> + gem_userptr(fd, bo_ptr, sizeof(linear), 0, userptr_flags, &bo[0]);
> +
> + bo[1] = create_bo(fd, 0);
> +
if (gup)
> + copy(fd, bo[1], bo[0], 0);
if (force_swap)
mlock(all_memory);
> + ret = munmap(ptr, map_size);
> + igt_assert_eq(ret, 0);
> +
> + if (midaccess)
> + copy(fd, bo[1], bo[0], expected);
> +
> + ptr2 = mmap(ptr, map_size, PROT_READ | PROT_WRITE,
> + MAP_ANONYMOUS | MAP_PRIVATE | MAP_FIXED, -1, 0);
> + igt_assert(ptr2 != MAP_FAILED);
> + igt_assert(ptr2 == ptr);
> +
> + copy(fd, bo[1], bo[0], expected);
> +
> + gem_close(fd, bo[1]);
> + gem_close(fd, bo[0]);
> +
> + ret = munmap(ptr, map_size);
> + igt_assert_eq(ret, 0);
> +}
Basically the current attitude is that we didn't care for the client
games, our guarantee was that we didn't subvert the kernel. I do think
your proposed semantic is safer, we might as well try and catch all the
corner cases whilst here and just some pondering over if there are paths
that call invalidate range but we don't want to lose the object.
There are some fun tricks userspace could do with mmap(), such as
sparse textures (mapping the object to the zero page, then populating on
the fly), that don't fit well at all with our object-orientated approach
and would fall afoul of the above scheme. Oh well, we need to treat this
with all the care of an abi change and see if we can find more exotic
users.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH v8 02/12] drm/i915: Add i915 perf infrastructure
On Fri, Oct 28, 2016 at 3:27 PM, Matthew Auld <
matthew.william.a...@gmail.com> wrote:
> > +/* Note we copy the properties from userspace outside of the i915 perf
> > + * mutex to avoid an awkward lockdep with mmap_sem.
> > + *
> > + * Note this function only validates properties in isolation it doesn't
> > + * validate that the combination of properties makes sense or that all
> > + * properties necessary for a particular kind of stream have been set.
> > + */
> > +static int read_properties_unlocked(struct drm_i915_private *dev_priv,
> > + u64 __user *uprops,
> > + u32 n_props,
> > + struct perf_open_properties *props)
> > +{
> > + u64 __user *uprop = uprops;
> > + int i;
> > +
> > + memset(props, 0, sizeof(struct perf_open_properties));
> > +
> > + if (!n_props) {
> > + DRM_ERROR("No i915 perf properties given");
> > + return -EINVAL;
> > + }
> > +
> > + if (n_props > DRM_I915_PERF_PROP_MAX) {
> Ah but DRM_I915_PERF_PROP_MAX is not a property itself.
>
I'm not sure I follow what your implied concern is?
This is just a sanity check for the number properties given by userspace,
based on the assumption that there's currently no reason for multiple
values with a particular property id.
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Re: [Intel-gfx] [PATCH] drm/i915: rename preliminary_hw_support to alpha_support
I was about to put my rv-b here. I do believe we need to find a better
name and the patch was clear and correct. And indeed in a good timing.
However right before clicking the send button I had a vision that this
will bring another kind of confusion and miss leading.
Traditionally this tag has been removed from new platforms around (but
not tight to) "PV millestone", few months away from "Alpha milestone".
I understand that it is alpha quality from Alpha to PV, but people might
think that passing Alpha this is Beta or pre-PV and that the flag should
be removed right after alpha.
Also from PO to Alpha we cannot say it is alpha quality. It is just too
preliminary yet.
Maybe we just remove the "_hw_" and improve the texts?
Thanks,
Rodrigo.
On Mon, 2016-10-31 at 12:18 +0200, Jani Nikula wrote:
> The term "preliminary hardware support" has always caused confusion both
> among users and developers. It has always been about preliminary driver
> support for new hardware, and not so much about preliminary hardware. Of
> course, initially both the software and hardware are in early stages,
> but the distinction becomes more clear when the user picks up production
> hardware and an older kernel to go with it, with just the early support
> we had for the hardware at the time the kernel was released. The user
> has to specifically enable the alpha quality *driver* support for the
> hardware in that specific kernel version.
>
> Rename preliminary_hw_support to alpha_support to emphasize that the
> module parameter, config option, and flag are about software, not about
> hardware. Improve the language in help texts and debug logging as well.
>
> This appears to be a good time to do the change, as there are currently
> no platforms with preliminary^W alpha support.
>
> Cc: Rob Clark
> Cc: Dave Airlie
> Cc: Daniel Vetter
> Cc: Rodrigo Vivi
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/Kconfig | 17 +++--
> drivers/gpu/drm/i915/i915_drv.h| 4 ++--
> drivers/gpu/drm/i915/i915_params.c | 9 +
> drivers/gpu/drm/i915/i915_params.h | 2 +-
> drivers/gpu/drm/i915/i915_pci.c| 7 ---
> 5 files changed, 23 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
> index df96aed6975a..36941afba43f 100644
> --- a/drivers/gpu/drm/i915/Kconfig
> +++ b/drivers/gpu/drm/i915/Kconfig
> @@ -36,15 +36,20 @@ config DRM_I915
>
> If "M" is selected, the module will be called i915.
>
> -config DRM_I915_PRELIMINARY_HW_SUPPORT
> - bool "Enable preliminary support for prerelease Intel hardware by
> default"
> +config DRM_I915_ALPHA_SUPPORT
> + bool "Enable alpha quality support for new Intel hardware by default"
> depends on DRM_I915
> default n
> help
> - Choose this option if you have prerelease Intel hardware and want the
> - i915 driver to support it by default. You can enable such support at
> - runtime with the module option i915.preliminary_hw_support=1; this
> - option changes the default for that module option.
> + Choose this option if you have new Intel hardware and want to enable
> + the alpha quality i915 driver support for the hardware in this kernel
> + version. You can also enable the support at runtime using the module
> + parameter i915.alpha_support=1; this option changes the default for
> + that module parameter.
> +
> + It is recommended to upgrade to a kernel version with proper support
> + as soon as it is available. Generally fixes for platforms with alpha
> + support are not backported to older kernels.
>
> If in doubt, say "N".
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 42a499681966..abddafba6220 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -668,7 +668,7 @@ struct intel_csr {
> func(is_skylake); \
> func(is_broxton); \
> func(is_kabylake); \
> - func(is_preliminary); \
> + func(is_alpha_support); \
> /* Keep has_* in alphabetical order */ \
> func(has_csr); \
> func(has_ddi); \
> @@ -2782,7 +2782,7 @@ struct drm_i915_cmd_table {
> #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
>(INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
>
> -#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
> +#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
>
> #define SKL_REVID_A0 0x0
> #define SKL_REVID_B0 0x1
> diff --git a/drivers/gpu/drm/i915/i915_params.c
> b/drivers/gpu/drm/i915/i915_params.c
> index 629e4334719c..d46ffe7086bc 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -39,7 +39,7 @@ struct i915_params i915 __read_mostly = {
> .enable_hangcheck = true,
> .enable_ppgtt = -1,
> .enable_psr = -1
Re: [Intel-gfx] [PATCH] i915/GuC: Make GuC loads default
Could someone please ack this? We need this before getting HuC. GuC submission has regressions so the submission is not getting enabled. But we need to have GuC loaded to be able to use HuC. Thanks, Rodrigo. On Thu, Oct 6, 2016 at 11:08 AM, Rodrigo Vivi wrote: > I also asked that same question many times. Maybe they can be unified > later when we enable submission by default, but right now I believe > this is the way to go, so > > Reviewed-by: Rodrigo Vivi > > > On Thu, Oct 6, 2016 at 11:03 AM, Srivatsa, Anusha > wrote: >> >> >>>-Original Message- >>>From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] >>>Sent: Wednesday, October 5, 2016 11:57 PM >>>To: Srivatsa, Anusha >>>Cc: intel-gfx@lists.freedesktop.org >>>Subject: Re: [Intel-gfx] [PATCH] i915/GuC: Make GuC loads default >>> >>>On Wed, Oct 05, 2016 at 04:20:04PM -0700, Anusha Srivatsa wrote: Proper functioning of HuC requires GuC to be loaded. Make GuC loads default so that HuC works seemlessly. Also, note that GuC submission is not made default and still needs to be given as a kernel parameter. Once the issues around GuC submission is resolved it is intended to make it default as well. >>> >>>Why is this even a separate parameter? -Chris >> >> It is a separate parameter because HuC requires GuC to be loaded. It is ok >> if command submission is not happening through GuC but GuC "has to" be >> loaded for HuC to function. Guc_submission parameter enables the command >> submission through GUC. But, guc_loading parameter ensures not only that the >> GuC is loaded but also that HuC can now function. >> >> Anusha >>>-- >>>Chris Wilson, Intel Open Source Technology Centre >> ___ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > Rodrigo Vivi > Blog: http://blog.vivi.eng.br -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8 02/12] drm/i915: Add i915 perf infrastructure
On 31 October 2016 at 16:27, Robert Bragg wrote:
>
>
> On Fri, Oct 28, 2016 at 3:27 PM, Matthew Auld
> wrote:
>>
>> > +/* Note we copy the properties from userspace outside of the i915 perf
>> > + * mutex to avoid an awkward lockdep with mmap_sem.
>> > + *
>> > + * Note this function only validates properties in isolation it doesn't
>> > + * validate that the combination of properties makes sense or that all
>> > + * properties necessary for a particular kind of stream have been set.
>> > + */
>> > +static int read_properties_unlocked(struct drm_i915_private *dev_priv,
>> > + u64 __user *uprops,
>> > + u32 n_props,
>> > + struct perf_open_properties *props)
>> > +{
>> > + u64 __user *uprop = uprops;
>> > + int i;
>> > +
>> > + memset(props, 0, sizeof(struct perf_open_properties));
>> > +
>> > + if (!n_props) {
>> > + DRM_ERROR("No i915 perf properties given");
>> > + return -EINVAL;
>> > + }
>> > +
>> > + if (n_props > DRM_I915_PERF_PROP_MAX) {
>> Ah but DRM_I915_PERF_PROP_MAX is not a property itself.
>
>
> I'm not sure I follow what your implied concern is?
>
> This is just a sanity check for the number properties given by userspace,
> based on the assumption that there's currently no reason for multiple values
> with a particular property id.
>
All I meant was should it not be n_props >= DRM_I915_PERF_PROP_MAX ?
So with that fixed, or if I'm completely mad:
Reviewed-by: Matthew Auld
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/gtt: Mark tlbs dirty on clear
On Mon, Oct 31, 2016 at 05:58:15PM +0200, Mika Kuoppala wrote: > Chris Wilson writes: > > > On Mon, Oct 31, 2016 at 05:24:46PM +0200, Mika Kuoppala wrote: > >> Now when clearing ptes can modify upper level pdp's, > >> we need to mark them dirty so that they will be flushed > >> correctly. > > > > I suppose so. > > It is a bit iffy if we really do, but this way we gain symmetry > with the alloc side. If we assume correct behaviour on the client, no. They shouldn't be accessing any of the removed PTE, PDE, PDPE and so now follow the stale TLB to the old pages (now reused by the system and containing garbage -> GPU hang or carefully crafted redirection). However, on the same basis we fill the client address space with scratch pages, we also should prepare for random stray access which means we need to invalidate the TLB -- however, given that this is undefined behaviour a ncurrently executing batch may be accessing this page illegally and see the stale value long before a newly submitted batch flushes the TLB. So based on that we fix predictable TLB errors (such as the prefetcher crossing the page boundary, if it still does!) for correctly behaving batches. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/6] drm/i915: Use the full hammer when shutting down the rcu tasks
On 31/10/2016 10:26, Chris Wilson wrote:
To flush all call_rcu() tasks (here from i915_gem_free_object()) we need
to call rcu_barrier() (not synchronize_rcu()). If we don't then we may
still have objects being freed as we continue to teardown the driver -
in particular, the recently released rings may race with the memory
manager shutdown resulting in sporadic:
[ 142.217186] WARNING: CPU: 7 PID: 6185 at drivers/gpu/drm/drm_mm.c:932
drm_mm_takedown+0x2e/0x40
[ 142.217187] Memory manager not clean during takedown.
[ 142.217187] Modules linked in: i915(-) x86_pkg_temp_thermal intel_powerclamp
coretemp crct10dif_pclmul crc32_pclmul ghash_clmulni_intel lpc_ich
snd_hda_codec_realtek snd_hda_codec_generic mei_me mei snd_hda_codec_hdmi
snd_hda_codec snd_hwdep snd_hda_core snd_pcm e1000e ptp pps_core [last
unloaded: snd_hda_intel]
[ 142.217199] CPU: 7 PID: 6185 Comm: rmmod Not tainted
4.9.0-rc2-CI-Trybot_242+ #1
[ 142.217199] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS FBKT34AUS
04/24/2013
[ 142.217200] c90002ecfce0 8142dd65 c90002ecfd30
[ 142.217202] c90002ecfd20 8107e4e6 03a40778c2a8
880401355c48
[ 142.217204] 88040778c2a8 a040f3c0 a040f4a0
5621fbf8b1f0
[ 142.217206] Call Trace:
[ 142.217209] [] dump_stack+0x67/0x92
[ 142.217211] [] __warn+0xc6/0xe0
[ 142.217213] [] warn_slowpath_fmt+0x4a/0x50
[ 142.217214] [] drm_mm_takedown+0x2e/0x40
[ 142.217236] [] i915_gem_cleanup_stolen+0x1a/0x20 [i915]
[ 142.217246] [] i915_ggtt_cleanup_hw+0x31/0xb0 [i915]
[ 142.217253] [] i915_driver_cleanup_hw+0x31/0x40 [i915]
[ 142.217260] [] i915_driver_unload+0x141/0x1a0 [i915]
[ 142.217268] [] i915_pci_remove+0x14/0x20 [i915]
[ 142.217269] [] pci_device_remove+0x34/0xb0
[ 142.217271] [] __device_release_driver+0x9c/0x150
[ 142.217272] [] driver_detach+0xb6/0xc0
[ 142.217273] [] bus_remove_driver+0x53/0xd0
[ 142.217274] [] driver_unregister+0x27/0x50
[ 142.217276] [] pci_unregister_driver+0x25/0x70
[ 142.217287] [] i915_exit+0x1a/0x71 [i915]
[ 142.217289] [] SyS_delete_module+0x193/0x1e0
[ 142.217291] [] entry_SYSCALL_64_fastpath+0x1c/0xb1
[ 142.217292] ---[ end trace 6fd164859c154772 ]---
[ 142.217505] [drm:show_leaks] *ERROR* node [6b6b6b6b6b6b6b6b +
6b6b6b6b6b6b6b6b]: inserted at
[] save_stack.isra.1+0x53/0xa0
[]
drm_mm_insert_node_in_range_generic+0x2ad/0x360
[]
i915_gem_stolen_insert_node_in_range+0x93/0xe0 [i915]
[] i915_gem_object_create_stolen+0x75/0xb0
[i915]
[] intel_engine_create_ring+0x9a/0x140 [i915]
[] intel_init_ring_buffer+0xf1/0x440 [i915]
[] intel_init_render_ring_buffer+0xab/0x1b0
[i915]
[] intel_engines_init+0xc8/0x210 [i915]
[] i915_gem_init+0xac/0xf0 [i915]
[] i915_driver_load+0x9c4/0x1430 [i915]
[] i915_pci_probe+0x28/0x40 [i915]
[] pci_device_probe+0x85/0xf0
[] driver_probe_device+0x21f/0x430
[] __driver_attach+0xde/0xe0
In particular note that the node was being poisoned as we inspected the
list, a clear indication that the object is being freed as we make the
assertion.
Fixes: fbbd37b36fa5 ("drm/i915: Move object release to a freelist + worker")
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 839ce2ae38fa..ed01421e3be7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -544,8 +544,10 @@ static void i915_gem_fini(struct drm_i915_private
*dev_priv)
i915_gem_context_fini(&dev_priv->drm);
mutex_unlock(&dev_priv->drm.struct_mutex);
- synchronize_rcu();
- flush_work(&dev_priv->mm.free_work);
+ do {
+ rcu_barrier();
+ flush_work(&dev_priv->mm.free_work);
+ } while (!llist_empty(&dev_priv->mm.free_list));
WARN_ON(!list_empty(&dev_priv->context_list));
}
Not sure that the loop is required - after the rcu_barrier all the
queued up additions have been added to the list and workers queued. So
flush_work afterwards handles those and we are done, no?
If I am right it could be written as:
rcu_barrier();
flush_work(...);
WARN_ON(!llist_empty(...);
If I am not right then it sounds pretty fishy since it implies new
objects are being freed in parallel to i915_gem_fini. Hm?
It fixes the CI fire so r-b anyway if you want to merge it while
considering the above:
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 2/6] drm/i915: Avoid accessing request->timeline outside of its lifetime
On 31/10/2016 10:26, Chris Wilson wrote: Whilst waiting on a request, we may do so without holding any locks or any guards beyond a reference to the request. In order to avoid taking locks within request deallocation, we drop references to its timeline (via the context and ppgtt) upon retirement. We should avoid chasing Couldn't find that there is a reference taken (or dropped) on the timeline when stored in a request. It looks like a borrowed pointer to me? such pointers outside of their control, in particular we inspect the request->timeline to see if we may restore the RPS waitboost for a client. If we instead look at the engine->timeline, we will have similar behaviour on both full-ppgtt and !full-ppgtt systems and reduce the amount of reward we give towards stalling clients (i.e. only if the client stalls and the GPU is uncontended does it reclaim its boost). This restores behaviour back to pre-timelines, whilst fixing: [ 645.078485] BUG: KASAN: use-after-free in i915_gem_object_wait_fence+0x1ee/0x2e0 at addr 8802335643a0 [ 645.078577] Read of size 4 by task gem_exec_schedu/28408 [ 645.078638] CPU: 1 PID: 28408 Comm: gem_exec_schedu Not tainted 4.9.0-rc2+ #64 [ 645.078724] Hardware name: /, BIOS PYBSWCEL.86A.0027.2015.0507.1758 05/07/2015 [ 645.078816] 88022daef9a0 8143d059 880235402a80 880233564200 [ 645.078998] 88022daef9c8 81229c5c 88022daefa48 880233564200 [ 645.079172] 880235402a80 88022daefa38 81229ef0 8110a796 [ 645.079345] Call Trace: [ 645.079404] [] dump_stack+0x68/0x9f [ 645.079467] [] kasan_object_err+0x1c/0x70 [ 645.079534] [] kasan_report_error+0x1f0/0x4b0 [ 645.079601] [] kasan_report+0x34/0x40 [ 645.079676] [] ? i915_gem_object_wait_fence+0x1ee/0x2e0 [ 645.079741] [] __asan_load4+0x61/0x80 [ 645.079807] [] i915_gem_object_wait_fence+0x1ee/0x2e0 [ 645.079876] [] i915_gem_object_wait+0x19f/0x590 [ 645.079944] [] ? i915_gem_object_wait_priority+0x500/0x500 [ 645.080016] [] ? debug_show_all_locks+0x1e0/0x1e0 [ 645.080084] [] ? check_chain_key+0x14c/0x210 [ 645.080157] [] ? __lock_is_held+0x46/0xc0 [ 645.080226] [] ? i915_gem_set_domain_ioctl+0x141/0x690 [ 645.080296] [] i915_gem_set_domain_ioctl+0x1a2/0x690 [ 645.080366] [] ? __might_fault+0x75/0xe0 [ 645.080433] [] drm_ioctl+0x327/0x640 [ 645.080508] [] ? i915_gem_obj_prepare_shmem_write+0x3a0/0x3a0 [ 645.080603] [] ? drm_ioctl_permit+0x120/0x120 [ 645.080670] [] ? check_chain_key+0x14c/0x210 [ 645.080738] [] do_vfs_ioctl+0x127/0xa20 [ 645.080804] [] ? do_mmap+0x47c/0x580 [ 645.080871] [] ? vm_mmap_pgoff+0x117/0x140 [ 645.080938] [] ? ioctl_preallocate+0x150/0x150 [ 645.081011] [] ? up_write+0x23/0x50 [ 645.081078] [] ? vm_mmap_pgoff+0x117/0x140 [ 645.081145] [] ? vma_is_stack_for_current+0x90/0x90 [ 645.081214] [] ? mark_held_locks+0x23/0xc0 [ 645.082030] [] ? __fget+0x168/0x250 [ 645.082106] [] ? entry_SYSCALL_64_fastpath+0x5/0xb1 [ 645.082176] [] ? __fget_light+0xa2/0xc0 [ 645.082242] [] SyS_ioctl+0x3c/0x70 [ 645.082309] [] entry_SYSCALL_64_fastpath+0x1c/0xb1 [ 645.082374] Object at 880233564200, in cache kmalloc-8192 size: 8192 [ 645.082431] Allocated: [ 645.082480] PID = 28408 [ 645.082535] [ 645.082566] [] save_stack_trace+0x16/0x20 [ 645.082623] [ 645.082656] [] save_stack+0x46/0xd0 [ 645.082716] [ 645.082756] [] kasan_kmalloc+0xad/0xe0 [ 645.082817] [ 645.082848] [] i915_ppgtt_create+0x52/0x220 [ 645.082908] [ 645.082941] [] i915_gem_create_context+0x396/0x560 [ 645.083027] [ 645.083059] [] i915_gem_context_create_ioctl+0x97/0xf0 [ 645.083152] [ 645.083183] [] drm_ioctl+0x327/0x640 [ 645.083243] [ 645.083274] [] do_vfs_ioctl+0x127/0xa20 [ 645.083334] [ 645.083372] [] SyS_ioctl+0x3c/0x70 [ 645.083432] [ 645.083464] [] entry_SYSCALL_64_fastpath+0x1c/0xb1 [ 645.083551] Freed: [ 645.083599] PID = 27629 [ 645.083648] [ 645.083676] [] save_stack_trace+0x16/0x20 [ 645.083738] [ 645.083770] [] save_stack+0x46/0xd0 [ 645.083830] [ 645.083862] [] kasan_slab_free+0x73/0xc0 [ 645.083922] [ 645.083961] [] kfree+0xa9/0x170 [ 645.084021] [ 645.084053] [] i915_ppgtt_release+0x100/0x180 [ 645.084139] [ 645.084171] [] i915_gem_context_free+0x1b4/0x230 [ 645.084257] [ 645.084288] [] intel_lr_context_unpin+0x192/0x230 [ 645.084380] [ 645.084413] [] i915_gem_request_retire+0x620/0x630 [ 645.084500] [ 645.085226] [] i915_gem_retire_requests+0x181/0x280 [ 645.085313] [ 645.085352] [] i915_gem_retire_work_handler+0xca/0xe0 [ 645.085440] [ 645.085471] [] process_one_work+0x4fb/0x920 [ 645.085532] [ 645.085562] [] worker_thread+0x8d/0x840 [ 645.085622] [ 645.085653] [] kthread+0x185/0x1b0 [ 645.085718] [ 645.085750] [] ret_from_fork+0x27/0x40 [ 645.085811] Memory state around the buggy address: [ 645.085869] 880233564280: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 645.08
Re: [Intel-gfx] [PATCH] drm/i915: rename preliminary_hw_support to alpha_support
On Mon, 31 Oct 2016, "Vivi, Rodrigo" wrote:
> I was about to put my rv-b here. I do believe we need to find a better
> name and the patch was clear and correct. And indeed in a good timing.
>
> However right before clicking the send button I had a vision that this
> will bring another kind of confusion and miss leading.
>
> Traditionally this tag has been removed from new platforms around (but
> not tight to) "PV millestone", few months away from "Alpha milestone".
>
> I understand that it is alpha quality from Alpha to PV, but people might
> think that passing Alpha this is Beta or pre-PV and that the flag should
> be removed right after alpha.
> Also from PO to Alpha we cannot say it is alpha quality. It is just too
> preliminary yet.
I was mostly referring to what it looks on the outside, but it would be
great if it also made sense internally.
BR,
Jani.
>
> Maybe we just remove the "_hw_" and improve the texts?
>
> Thanks,
> Rodrigo.
>
>
> On Mon, 2016-10-31 at 12:18 +0200, Jani Nikula wrote:
>> The term "preliminary hardware support" has always caused confusion both
>> among users and developers. It has always been about preliminary driver
>> support for new hardware, and not so much about preliminary hardware. Of
>> course, initially both the software and hardware are in early stages,
>> but the distinction becomes more clear when the user picks up production
>> hardware and an older kernel to go with it, with just the early support
>> we had for the hardware at the time the kernel was released. The user
>> has to specifically enable the alpha quality *driver* support for the
>> hardware in that specific kernel version.
>
>
>>
>> Rename preliminary_hw_support to alpha_support to emphasize that the
>> module parameter, config option, and flag are about software, not about
>> hardware. Improve the language in help texts and debug logging as well.
>>
>> This appears to be a good time to do the change, as there are currently
>> no platforms with preliminary^W alpha support.
>>
>> Cc: Rob Clark
>> Cc: Dave Airlie
>> Cc: Daniel Vetter
>> Cc: Rodrigo Vivi
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/Kconfig | 17 +++--
>> drivers/gpu/drm/i915/i915_drv.h| 4 ++--
>> drivers/gpu/drm/i915/i915_params.c | 9 +
>> drivers/gpu/drm/i915/i915_params.h | 2 +-
>> drivers/gpu/drm/i915/i915_pci.c| 7 ---
>> 5 files changed, 23 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
>> index df96aed6975a..36941afba43f 100644
>> --- a/drivers/gpu/drm/i915/Kconfig
>> +++ b/drivers/gpu/drm/i915/Kconfig
>> @@ -36,15 +36,20 @@ config DRM_I915
>>
>>If "M" is selected, the module will be called i915.
>>
>> -config DRM_I915_PRELIMINARY_HW_SUPPORT
>> -bool "Enable preliminary support for prerelease Intel hardware by
>> default"
>> +config DRM_I915_ALPHA_SUPPORT
>> +bool "Enable alpha quality support for new Intel hardware by default"
>> depends on DRM_I915
>> default n
>> help
>> - Choose this option if you have prerelease Intel hardware and want the
>> - i915 driver to support it by default. You can enable such support at
>> - runtime with the module option i915.preliminary_hw_support=1; this
>> - option changes the default for that module option.
>> + Choose this option if you have new Intel hardware and want to enable
>> + the alpha quality i915 driver support for the hardware in this kernel
>> + version. You can also enable the support at runtime using the module
>> + parameter i915.alpha_support=1; this option changes the default for
>> + that module parameter.
>> +
>> + It is recommended to upgrade to a kernel version with proper support
>> + as soon as it is available. Generally fixes for platforms with alpha
>> + support are not backported to older kernels.
>>
>>If in doubt, say "N".
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 42a499681966..abddafba6220 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -668,7 +668,7 @@ struct intel_csr {
>> func(is_skylake); \
>> func(is_broxton); \
>> func(is_kabylake); \
>> -func(is_preliminary); \
>> +func(is_alpha_support); \
>> /* Keep has_* in alphabetical order */ \
>> func(has_csr); \
>> func(has_ddi); \
>> @@ -2782,7 +2782,7 @@ struct drm_i915_cmd_table {
>> #define IS_SKL_GT4(dev_priv)(IS_SKYLAKE(dev_priv) && \
>> (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
>>
>> -#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
>> +#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
>>
>> #define SKL_REVID_A00x0
>> #define SKL_REVID_B00x1
>> diff --git a/drivers/gpu/drm/i915/i915_params.c
>> b/drivers/gpu/drm/i915
Re: [Intel-gfx] [PATCH v4 1/8] drm/i915/skl+: use linetime latency instead of ddb size
Em Qui, 2016-10-13 às 16:28 +0530, Kumar, Mahesh escreveu:
> This patch make changes to use linetime latency instead of allocated
> DDB size during plane watermark calculation in switch case, This is
> required to implement new DDB allocation algorithm.
>
> In New Algorithm DDB is allocated based on WM values, because of
> which
> number of DDB blocks will not be available during WM calculation,
> So this "linetime latency" is suggested by SV/HW team to use during
> switch-case for WM blocks selection.
>
> Changes since v1:
> - Rebase on top of Paulo's patch series
> Changes since v2:
> - Fix if-else condition (pointed by Maarten)
>
> Signed-off-by: "Kumar, Mahesh"
> ---
> drivers/gpu/drm/i915/intel_pm.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 7f1748a..098336d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3616,10 +3616,14 @@ static int skl_compute_plane_wm(const struct
> drm_i915_private *dev_priv,
> fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
> selected_result = max(method2, y_tile_minimum);
> } else {
> + uint32_t linetime_us = 0;
> +
> + linetime_us = DIV_ROUND_UP(width * 1000,
> + skl_pipe_pixel_rate(cstate));
Can't we just call skl_compute_linetime_wm() here? I don't like having
two pieces of the code computing the same thing. My last round of bug
fixes included a fix for duplicated code that got out of sync after
spec changes.
> if ((cpp * cstate->base.adjusted_mode.crtc_htotal /
> 512 < 1) &&
> (plane_bytes_per_line / 512 < 1))
> selected_result = method2;
> - else if ((ddb_allocation / plane_blocks_per_line) >=
> 1)
> + else if (latency >= linetime_us)
Still doesn't match the spec. The "ddb_allocation /
planes_block_per_line" is still necessary.
> selected_result = min(method1, method2);
> else
> selected_result = method1;
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Re: [Intel-gfx] [PATCH v8 02/12] drm/i915: Add i915 perf infrastructure
On Mon, Oct 31, 2016 at 5:13 PM, Matthew Auld <
matthew.william.a...@gmail.com> wrote:
> On 31 October 2016 at 16:27, Robert Bragg wrote:
> >
> >
> > On Fri, Oct 28, 2016 at 3:27 PM, Matthew Auld
> > wrote:
> >>
> >> > +/* Note we copy the properties from userspace outside of the i915
> perf
> >> > + * mutex to avoid an awkward lockdep with mmap_sem.
> >> > + *
> >> > + * Note this function only validates properties in isolation it
> doesn't
> >> > + * validate that the combination of properties makes sense or that
> all
> >> > + * properties necessary for a particular kind of stream have been
> set.
> >> > + */
> >> > +static int read_properties_unlocked(struct drm_i915_private
> *dev_priv,
> >> > + u64 __user *uprops,
> >> > + u32 n_props,
> >> > + struct perf_open_properties
> *props)
> >> > +{
> >> > + u64 __user *uprop = uprops;
> >> > + int i;
> >> > +
> >> > + memset(props, 0, sizeof(struct perf_open_properties));
> >> > +
> >> > + if (!n_props) {
> >> > + DRM_ERROR("No i915 perf properties given");
> >> > + return -EINVAL;
> >> > + }
> >> > +
> >> > + if (n_props > DRM_I915_PERF_PROP_MAX) {
> >> Ah but DRM_I915_PERF_PROP_MAX is not a property itself.
> >
> >
> > I'm not sure I follow what your implied concern is?
> >
> > This is just a sanity check for the number properties given by userspace,
> > based on the assumption that there's currently no reason for multiple
> values
> > with a particular property id.
> >
> All I meant was should it not be n_props >= DRM_I915_PERF_PROP_MAX ?
> So with that fixed, or if I'm completely mad:
> Reviewed-by: Matthew Auld
>
Ah, I see. Actually tbh I think either is reasonable...
The check is mainly about ruling out the silly large values that could be
given, imposing a upper-bound to the number of properties expected from
userspace. It might help catch userspace giving garbage/undefined data, or
block attempts to get the kernel parsing huge amounts of property data
which should never be necessary for configuring a stream. It doesn't e.g.
stop userspace specifying duplicate property IDs even if they supply less
than the maximum allowed. So even if it allowed say 2x the number of
properties I think it would still pretty much do its job.
I could imagine in the future the same check might become much more fuzzy
if we have a case where userspace might need to legitimately specify the
same property ID multiple times (where the sequential order is relevant).
_PERF_PROP_MAX is the last in the enum whereby we can interpret it as an
upper bound on the number of properties while we don't currently expect to
see property IDs duplicated.
The detail here though is that ID 0 is reserved so _PERF_PROP_MAX is more
like ('the maximum number of properties' + 1) - and so this is what you're
essentially highlighting.
I can change this - maybe with a comment about ID 0 being reserved and
explaining the assumption that property ID duplicates aren't currently
expected
Thanks for the review!
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Re: [Intel-gfx] [PATCH 2/7] drm/i915/huc: Unified css_header struct for GuC and HuC
Reviewed-by: Jeff McGee
On Fri, Oct 28, 2016 at 05:05:41PM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine
>
> HuC firmware css header has almost exactly same definition as GuC
> firmware except for the sw_version. Also, add a new member fw_type
> into intel_uc_fw to indicate what kind of fw it is. So, the loader
> will pull right sw_version from header.
>
> v2: rebased on-top of drm-intel-nightly
> v3: rebased on-top of drm-intel-nightly (again).
> v4: rebased + spaces.
> v7: rebased.
> v8: rebased.
> v9: rebased. Rename device_id to guc_branch_client_version,
> make guc_sw_version a union. . Put UC_FW_TYPE_GUC
> and UC_FW_TYPE_HUC into an enum.
>
> Tested-by: Xiang Haihao
> Signed-off-by: Anusha Srivatsa
> Signed-off-by: Alex Dai
> Signed-off-by: Peter Antoine
> Reviewed-by: Dave Gordon
> ---
> drivers/gpu/drm/i915/intel_guc.h| 6 +
> drivers/gpu/drm/i915/intel_guc_fwif.h | 21 +
> drivers/gpu/drm/i915/intel_guc_loader.c | 41
> ++---
> 3 files changed, 51 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.h
> b/drivers/gpu/drm/i915/intel_guc.h
> index 186efa7..84ef2bf 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -98,6 +98,11 @@ enum intel_uc_fw_status {
> UC_FIRMWARE_SUCCESS
> };
>
> +enum {
> + UC_FW_TYPE_GUC,
> + UC_FW_TYPE_HUC
> +};
> +
> /*
> * This structure encapsulates all the data needed during the process
> * of fetching, caching, and loading the firmware image into the GuC.
> @@ -115,6 +120,7 @@ struct intel_uc_fw {
> uint16_t major_ver_found;
> uint16_t minor_ver_found;
>
> + uint32_t fw_type;
> uint32_t header_size;
> uint32_t header_offset;
> uint32_t rsa_size;
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
> b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index 324ea90..c2a7fdd 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -154,7 +154,7 @@
> * The GuC firmware layout looks like this:
> *
> * +---+
> - * |guc_css_header |
> + * | uc_css_header |
> * | |
> * | contains major/minor version |
> * +---+
> @@ -181,9 +181,16 @@
> * 3. Length info of each component can be found in header, in dwords.
> * 4. Modulus and exponent key are not required by driver. They may not
> appear
> *in fw. So driver will load a truncated firmware in this case.
> + *
> + * HuC firmware layout is same as GuC firmware.
> + *
> + * HuC firmware css header is different. However, the only difference is
> where
> + * the version information is saved. The uc_css_header is unified to support
> + * both. Driver should get HuC version from uc_css_header.huc_sw_version,
> while
> + * uc_css_header.guc_sw_version for GuC.
> */
>
> -struct guc_css_header {
> +struct uc_css_header {
> uint32_t module_type;
> /* header_size includes all non-uCode bits, including css_header, rsa
>* key, modulus key and exponent data. */
> @@ -214,8 +221,14 @@ struct guc_css_header {
>
> char username[8];
> char buildnumber[12];
> - uint32_t device_id;
> - uint32_t guc_sw_version;
> + union {
> + uint32_t guc_branch_client_version;
> + uint32_t huc_sw_version;
> + };
> + union {
> + uint32_t guc_sw_version;
> + uint32_t huc_reserved;
> + };
> uint32_t prod_preprod_fw;
> uint32_t reserved[12];
> uint32_t header_info;
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
> b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 6683a88..ff26d2c 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -593,7 +593,7 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct
> intel_uc_fw *uc_fw)
> struct pci_dev *pdev = dev->pdev;
> struct drm_i915_gem_object *obj;
> const struct firmware *fw;
> - struct guc_css_header *css;
> + struct uc_css_header *css;
> size_t size;
> int err;
>
> @@ -610,19 +610,19 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct
> intel_uc_fw *uc_fw)
> uc_fw->uc_fw_path, fw);
>
> /* Check the size of the blob before examining buffer contents */
> - if (fw->size < sizeof(struct guc_css_header)) {
> + if (fw->size < sizeof(struct uc_css_header)) {
> DRM_NOTE("Firmware header is missing\n");
> goto fail;
> }
>
> - css = (struct guc_css_header *)fw->data;
> + css = (struct uc_css_header *)fw->data;
>
> /* Firmware bits always start from header */
> uc_fw->header_offset = 0;
> uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
> css->key_size_dw - css->exponent_s
Re: [Intel-gfx] [PATCH 3/7] drm/i915/huc: Add HuC fw loading support
On Fri, Oct 28, 2016 at 05:05:42PM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine
>
> The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
> is used for both cases.
>
> HuC loading needs to be before GuC loading. The WOPCM setting must
> be done early before loading any of them.
>
> v2: rebased on-top of drm-intel-nightly.
> removed if(HAS_GUC()) before the guc call. (D.Gordon)
> update huc_version number of format.
> v3: rebased to drm-intel-nightly, changed the file name format to
> match the one in the huc package.
> Changed dev->dev_private to to_i915()
> v4: moved function back to where it was.
> change wait_for_atomic to wait_for.
> v5: rebased + comment changes.
> v7: rebased.
> v8: rebased.
> v9: rebased. Changed the year in the copyright message to reflect
> the right year.Correct the comments,remove the unwanted WARN message,
> replace drm_gem_object_unreference() with i915_gem_object_put().Make the
> prototypes in intel_huc.h non-extern.
>
> Tested-by: Xiang Haihao
> Signed-off-by: Anusha Srivatsa
> Signed-off-by: Alex Dai
> Signed-off-by: Peter Antoine
> Reviewed-by: Dave Gordon
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/i915_drv.c | 3 +
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> drivers/gpu/drm/i915/i915_guc_reg.h | 3 +
> drivers/gpu/drm/i915/intel_guc.h| 1 +
> drivers/gpu/drm/i915/intel_guc_loader.c | 6 +-
> drivers/gpu/drm/i915/intel_huc.h| 42 ++
> drivers/gpu/drm/i915/intel_huc_loader.c | 260
>
> 8 files changed, 317 insertions(+), 2 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/intel_huc.h
> create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 6123400..0528168 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -52,6 +52,7 @@ i915-y += i915_cmd_parser.o \
>
> # general-purpose microcontroller (GuC) support
> i915-y += intel_guc_loader.o \
> + intel_huc_loader.o \
> i915_guc_submission.o
>
> # autogenerated null render state
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index af3559d..2f36672 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -594,6 +594,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
>* working irqs for e.g. gmbus and dp aux transfers. */
> intel_modeset_init(dev);
>
> + intel_huc_init(dev);
> intel_guc_init(dev);
>
> ret = i915_gem_init(dev);
> @@ -621,6 +622,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
> DRM_ERROR("failed to idle hardware; continuing to unload!\n");
> i915_gem_fini(dev);
> cleanup_irq:
> + intel_huc_fini(dev);
> intel_guc_fini(dev);
> drm_irq_uninstall(dev);
> intel_teardown_gmbus(dev);
> @@ -1304,6 +1306,7 @@ void i915_driver_unload(struct drm_device *dev)
> /* Flush any outstanding unpin_work. */
> drain_workqueue(dev_priv->wq);
>
> + intel_huc_fini(dev);
> intel_guc_fini(dev);
> i915_gem_fini(dev);
> intel_fbc_cleanup_cfb(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 55afb66..b0376f0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -55,6 +55,7 @@
> #include "intel_bios.h"
> #include "intel_dpll_mgr.h"
> #include "intel_guc.h"
> +#include "intel_huc.h"
> #include "intel_lrc.h"
> #include "intel_ringbuffer.h"
>
> @@ -1786,6 +1787,7 @@ struct drm_i915_private {
>
> struct intel_gvt *gvt;
>
> + struct intel_huc huc;
> struct intel_guc guc;
>
> struct intel_csr csr;
> @@ -2837,6 +2839,7 @@ struct drm_i915_cmd_table {
> #define HAS_GUC(dev) (INTEL_INFO(dev)->has_guc)
> #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
> #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
> +#define HAS_HUC_UCODE(dev) (HAS_GUC(dev))
>
> #define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h
> b/drivers/gpu/drm/i915/i915_guc_reg.h
> index a47e1e4..64e942a 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -61,9 +61,12 @@
> #define DMA_ADDRESS_SPACE_GTT(8 << 16)
> #define DMA_COPY_SIZE_MMIO(0xc310)
> #define DMA_CTRL _MMIO(0xc314)
> +#define HUC_UKERNEL (1<<9)
> #define UOS_MOVE (1<<4)
> #define START_DMA(1<<0)
> #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
> +#define HUC_LOADING_AGENT_VCR(0<<1)
> +#define HUC_LOADING_AGENT_GUC(1<<1)
> #define GUC_WOPCM_OFFSET_VALUE 0x8 /*
Re: [Intel-gfx] [PATCH 5/7] drm/i915/huc: Support HuC authentication
Reviewed-by: Jeff McGee
On Fri, Oct 28, 2016 at 05:05:44PM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine
>
> The HuC authentication is done by host2guc call. The HuC RSA keys
> are sent to GuC for authentication.
>
> v2: rebased on top of drm-intel-nightly.
> changed name format and upped version 1.7.
> v3: rebased on top of drm-intel-nightly.
> v4: changed wait_for_automic to wait_for
> v5: rebased.
> v7: rebased.
> v8: rebased.
> v9: rebased. Rename intel_huc_auh() to intel_guc_auth_huc()
> and place the prototype in intel_guc.h,correct the comments.
>
> Tested-by: Xiang Haihao
> Signed-off-by: Anusha Srivatsa
> Signed-off-by: Alex Dai
> Signed-off-by: Peter Antoine
> Reviewed-by: Dave Gordon
> ---
> drivers/gpu/drm/i915/i915_guc_submission.c | 63
> ++
> drivers/gpu/drm/i915/intel_guc.h | 2 +-
> drivers/gpu/drm/i915/intel_guc_fwif.h | 1 +
> drivers/gpu/drm/i915/intel_guc_loader.c| 2 +
> 4 files changed, 67 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
> b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 99dc5d9..936eefc 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -27,6 +27,7 @@
> #include
> #include "i915_drv.h"
> #include "intel_guc.h"
> +#include "intel_huc.h"
>
> /**
> * DOC: GuC-based command submission
> @@ -1713,3 +1714,65 @@ int i915_guc_log_control(struct drm_i915_private
> *dev_priv, u64 control_val)
>
> return ret;
> }
> +
> +/**
> + * intel_guc_auth_huc() - authenticate ucode
> + * @dev: the drm device
> + *
> + * Triggers a HuC fw authentication request to the GuC via host-2-guc
> + * interface.
> + */
> +void intel_guc_auth_huc(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_guc *guc = &dev_priv->guc;
> + struct intel_huc *huc = &dev_priv->huc;
> + struct i915_vma *vma;
> + int ret;
> + u32 data[2];
> +
> + /* Bypass the case where there is no HuC firmware */
> + if (huc->huc_fw.fetch_status == UC_FIRMWARE_NONE ||
> + huc->huc_fw.load_status == UC_FIRMWARE_NONE)
> + return;
> +
> + if (guc->guc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> + DRM_ERROR("HuC: GuC fw wasn't loaded. Can't authenticate");
> + return;
> + }
> +
> + if (huc->huc_fw.load_status != UC_FIRMWARE_SUCCESS) {
> + DRM_ERROR("HuC: fw wasn't loaded. Nothing to authenticate");
> + return;
> + }
> +
> + vma = i915_gem_object_ggtt_pin(huc->huc_fw.uc_fw_obj, NULL, 0, 0, 0);
> + if (IS_ERR(vma)) {
> + DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
> + return;
> + }
> +
> +
> + /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
> + I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> +
> + /* Specify auth action and where public signature is. */
> + data[0] = HOST2GUC_ACTION_AUTHENTICATE_HUC;
> + data[1] = i915_ggtt_offset(vma) + huc->huc_fw.rsa_offset;
> +
> + ret = host2guc_action(guc, data, ARRAY_SIZE(data));
> + if (ret) {
> + DRM_ERROR("HuC: GuC did not ack Auth request\n");
> + goto out;
> + }
> +
> + /* Check authentication status, it should be done by now */
> + ret = wait_for((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) > 0, 50);
> + if (ret) {
> + DRM_ERROR("HuC: Authentication failed\n");
> + goto out;
> + }
> +
> +out:
> + i915_vma_unpin(vma);
> +}
> diff --git a/drivers/gpu/drm/i915/intel_guc.h
> b/drivers/gpu/drm/i915/intel_guc.h
> index 4647e41..ffdd5b9 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -197,5 +197,5 @@ void i915_guc_flush_logs(struct drm_i915_private
> *dev_priv);
> void i915_guc_register(struct drm_i915_private *dev_priv);
> void i915_guc_unregister(struct drm_i915_private *dev_priv);
> int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
> -
> +void intel_guc_auth_huc(struct drm_device *dev);
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
> b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index c2a7fdd..99a092d 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -513,6 +513,7 @@ enum host2guc_action {
> HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
> HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
> HOST2GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
> + HOST2GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
> HOST2GUC_ACTION_LIMIT
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
> b/drivers/gpu/drm/i915/intel_guc_loader.c
> index dc79968..11e3bbb 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -531,6 +531,8 @@ int intel_guc_setup(struct drm_device *dev)
>
Re: [Intel-gfx] [PATCH 6/7] drm/i915/huc: Add BXT HuC Loading Support
On Fri, Oct 28, 2016 at 05:05:45PM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine
>
> This patch adds the HuC Loading for the BXT.
> Version 1.7 of the HuC firmware.
>
> v2: rebased.
> v3: rebased.
> changed file name to match the install package format.
> v7: rebased.
> v8: rebased.
>
> Signed-off-by: Anusha Srivatsa
> Signed-off-by: Peter Antoine
> Reviewed-by: David Gordon
> ---
> drivers/gpu/drm/i915/intel_huc_loader.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c
> b/drivers/gpu/drm/i915/intel_huc_loader.c
> index dcd9970..0969bdf 100644
> --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -43,6 +43,9 @@
> #define I915_SKL_HUC_UCODE "i915/skl_huc_ver01_07_1398.bin"
> MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
>
> +#define I915_BXT_HUC_UCODE "i915/bxt_huc_ver01_07_1398.bin"
> +MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
> +
This will need updating if the newer firmware version/name macros in
intel_guc_loader.c are adopted.
-Jeff
> /**
> * huc_ucode_xfer() - DMA's the firmware
> * @dev_priv: the drm device
> @@ -150,6 +153,10 @@ void intel_huc_init(struct drm_device *dev)
> fw_path = I915_SKL_HUC_UCODE;
> huc_fw->major_ver_wanted = 1;
> huc_fw->minor_ver_wanted = 7;
> + } else if (IS_BROXTON(dev_priv)) {
> + fw_path = I915_BXT_HUC_UCODE;
> + huc_fw->major_ver_wanted = 1;
> + huc_fw->minor_ver_wanted = 7;
Use version macros here when that part is ready.
-Jeff
> }
>
> if (fw_path == NULL)
> --
> 2.7.4
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
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Re: [Intel-gfx] [PATCH 7/7] drm/i915/get_params: Add HuC status to getparams
Patch set header includes links to libva intent to use the interface. Thanks
Reviewed-by: Jeff McGee
On Fri, Oct 28, 2016 at 05:05:46PM -0700, Anusha Srivatsa wrote:
> From: Peter Antoine
>
> This patch will allow for getparams to return the status of the HuC.
> As the HuC has to be validated by the GuC this patch uses the validated
> status to show when the HuC is loaded and ready for use. You cannot use
> the loaded status as with the GuC as the HuC is verified after it is
> loaded and is not usable until it is verified.
>
> v2: removed the forewakes as the registers are already force-woken.
> (T.Ursulin)
> v4: rebased.
> v5: rebased.
> v6: rebased.
>
> Tested-by: Xiang Haihao
> Signed-off-by: Anusha Srivatsa
> Signed-off-by: Peter Antoine
> Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_drv.c | 5 +
> drivers/gpu/drm/i915/intel_huc.h| 1 +
> drivers/gpu/drm/i915/intel_huc_loader.c | 14 ++
> include/uapi/drm/i915_drm.h | 1 +
> 4 files changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 2f36672..038ed8d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -49,6 +49,8 @@
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> #include "intel_drv.h"
> +#include "intel_guc.h"
> +#include "intel_huc.h"
>
> static struct drm_driver driver;
>
> @@ -346,6 +348,9 @@ static int i915_getparam(struct drm_device *dev, void
> *data,
>*/
> value = 1;
> break;
> + case I915_PARAM_HAS_HUC:
> + value = intel_is_huc_valid(dev_priv);
> + break;
> default:
> DRM_DEBUG("Unknown parameter %d\n", param->param);
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/intel_huc.h
> b/drivers/gpu/drm/i915/intel_huc.h
> index 3ce0299..2e150be 100644
> --- a/drivers/gpu/drm/i915/intel_huc.h
> +++ b/drivers/gpu/drm/i915/intel_huc.h
> @@ -39,4 +39,5 @@ struct intel_huc {
> void intel_huc_init(struct drm_device *dev);
> void intel_huc_fini(struct drm_device *dev);
> int intel_huc_load(struct drm_device *dev);
> +extern int intel_is_huc_valid(struct drm_i915_private *dev_priv);
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c
> b/drivers/gpu/drm/i915/intel_huc_loader.c
> index 0969bdf..2f5d9d9 100644
> --- a/drivers/gpu/drm/i915/intel_huc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_huc_loader.c
> @@ -265,3 +265,17 @@ void intel_huc_fini(struct drm_device *dev)
>
> huc_fw->fetch_status = UC_FIRMWARE_NONE;
> }
> +
> +/**
> + * intel_is_huc_valid() - Check to see if the HuC is fully loaded.
> + * @dev_priv:drm device to check.
> + *
> + * This function will return true if the guc has been loaded and
> + * has valid firmware. The simplest way of doing this is to check
> + * if the HuC has been validated, if so it must have been loaded.
> + */
> +int intel_is_huc_valid(struct drm_i915_private *dev_priv)
> +{
> + return ((I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED) != 0);
> +}
> +
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 03725fe..aa7667e 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -388,6 +388,7 @@ typedef struct drm_i915_irq_wait {
> #define I915_PARAM_HAS_POOLED_EU 38
> #define I915_PARAM_MIN_EU_IN_POOL 39
> #define I915_PARAM_MMAP_GTT_VERSION 40
> +#define I915_PARAM_HAS_HUC42
>
> typedef struct drm_i915_getparam {
> __s32 param;
> --
> 2.7.4
>
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[Intel-gfx] [PATCH 02/26] drm/i915: Pass dev_priv to skl_init_scalers()
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
While at it let's do some house cleaning: s/intel_foo/foo/ and move
things into tighter scope.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 637c4fffd9f3..d626769b9d8b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -115,8 +115,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
const struct intel_crtc_state *pipe_config);
static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state
*);
static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state
*);
-static void skl_init_scalers(struct drm_device *dev, struct intel_crtc
*intel_crtc,
- struct intel_crtc_state *crtc_state);
+static void skl_init_scalers(struct drm_i915_private *dev_priv,
+struct intel_crtc *crtc,
+struct intel_crtc_state *crtc_state);
static void skylake_pfit_enable(struct intel_crtc *crtc);
static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
static void ironlake_pfit_enable(struct intel_crtc *crtc);
@@ -10735,10 +10736,8 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
if (INTEL_INFO(dev)->gen >= 9) {
- skl_init_scalers(dev, crtc, pipe_config);
- }
+ skl_init_scalers(dev_priv, crtc, pipe_config);
- if (INTEL_INFO(dev)->gen >= 9) {
pipe_config->scaler_state.scaler_id = -1;
pipe_config->scaler_state.scaler_users &= ~(1 <<
SKL_CRTC_INDEX);
}
@@ -15222,17 +15221,19 @@ intel_cursor_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
return ERR_PTR(ret);
}
-static void skl_init_scalers(struct drm_device *dev, struct intel_crtc
*intel_crtc,
- struct intel_crtc_state *crtc_state)
+static void skl_init_scalers(struct drm_i915_private *dev_priv,
+struct intel_crtc *crtc,
+struct intel_crtc_state *crtc_state)
{
+ struct intel_crtc_scaler_state *scaler_state =
+ &crtc_state->scaler_state;
int i;
- struct intel_scaler *intel_scaler;
- struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
- for (i = 0; i < intel_crtc->num_scalers; i++) {
- intel_scaler = &scaler_state->scalers[i];
- intel_scaler->in_use = 0;
- intel_scaler->mode = PS_SCALER_MODE_DYN;
+ for (i = 0; i < crtc->num_scalers; i++) {
+ struct intel_scaler *scaler = &scaler_state->scalers[i];
+
+ scaler->in_use = 0;
+ scaler->mode = PS_SCALER_MODE_DYN;
}
scaler_state->scaler_id = -1;
@@ -15267,7 +15268,7 @@ static int intel_crtc_init(struct drm_device *dev, enum
pipe pipe)
else
intel_crtc->num_scalers = SKL_NUM_SCALERS;
- skl_init_scalers(dev, intel_crtc, crtc_state);
+ skl_init_scalers(dev_priv, intel_crtc, crtc_state);
}
primary = intel_primary_plane_create(dev_priv, pipe);
--
2.7.4
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[Intel-gfx] [PATCH 03/26] drm/i915: Pass intel_crtc to intel_crtc_active()
From: Ville Syrjälä
Unify our approach to things by passing around intel_crtc instead of
drm_crtc.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 8 +++-
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 8
4 files changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d626769b9d8b..0dc72ba7fde7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1008,10 +1008,8 @@ bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state, int target_clock,
target_clock, refclk, NULL, best_clock);
}
-bool intel_crtc_active(struct drm_crtc *crtc)
+bool intel_crtc_active(struct intel_crtc *crtc)
{
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
/* Be paranoid as we can arrive here with only partial
* state retrieved from the hardware during setup.
*
@@ -1025,8 +1023,8 @@ bool intel_crtc_active(struct drm_crtc *crtc)
* crtc->state->active once we have proper CRTC states wired up
* for atomic.
*/
- return intel_crtc->active && crtc->primary->state->fb &&
- intel_crtc->config->base.adjusted_mode.crtc_clock;
+ return crtc->active && crtc->base.primary->state->fb &&
+ crtc->config->base.adjusted_mode.crtc_clock;
}
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 20ac79cff5c0..7e46453adb49 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1358,7 +1358,7 @@ bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state, int target_clock,
struct dpll *best_clock);
int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
-bool intel_crtc_active(struct drm_crtc *crtc);
+bool intel_crtc_active(struct intel_crtc *crtc);
void hsw_enable_ips(struct intel_crtc *crtc);
void hsw_disable_ips(struct intel_crtc *crtc);
enum intel_display_power_domain
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index cbe2ebda4c40..e230d480c5e6 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -1306,7 +1306,7 @@ void intel_fbc_init_pipe_state(struct drm_i915_private
*dev_priv)
return;
for_each_intel_crtc(&dev_priv->drm, crtc)
- if (intel_crtc_active(&crtc->base) &&
+ if (intel_crtc_active(crtc) &&
to_intel_plane_state(crtc->base.primary->state)->base.visible)
dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b544248cfdee..ba663889d8ea 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -629,7 +629,7 @@ static struct drm_crtc *single_enabled_crtc(struct
drm_device *dev)
struct drm_crtc *crtc, *enabled = NULL;
for_each_crtc(dev, crtc) {
- if (intel_crtc_active(crtc)) {
+ if (intel_crtc_active(to_intel_crtc(crtc))) {
if (enabled)
return NULL;
enabled = crtc;
@@ -724,7 +724,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
int entries, tlb_miss;
crtc = intel_get_crtc_for_plane(dev, plane);
- if (!intel_crtc_active(crtc)) {
+ if (!intel_crtc_active(to_intel_crtc(crtc))) {
*cursor_wm = cursor->guard_size;
*plane_wm = display->guard_size;
return false;
@@ -1537,7 +1537,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
fifo_size = dev_priv->display.get_fifo_size(dev, 0);
crtc = intel_get_crtc_for_plane(dev, 0);
- if (intel_crtc_active(crtc)) {
+ if (intel_crtc_active(to_intel_crtc(crtc))) {
const struct drm_display_mode *adjusted_mode;
int cpp =
drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
if (IS_GEN2(dev_priv))
@@ -1559,7 +1559,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
fifo_size = dev_priv->display.get_fifo_size(dev, 1);
crtc = intel_get_crtc_for_plane(dev, 1);
- if (intel_crtc_active(crtc)) {
+ if (intel_crtc_active(to_intel_crtc(crtc))) {
const struct drm_display_mode *adjusted_mode;
int cpp =
drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
if (IS_GEN2(dev_priv))
--
2.7.4
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[Intel-gfx] [PATCH 04/26] drm/i915: Pass intel_crtc to update_wm functions
From: Ville Syrjälä
Unify our approach to things by passing around intel_crtc instead of
drm_crtc.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 14 +-
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 50 +---
4 files changed, 33 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 19828460bbee..0342c874c2de 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -503,7 +503,7 @@ struct drm_i915_display_funcs {
void (*initial_watermarks)(struct intel_crtc_state *cstate);
void (*optimize_watermarks)(struct intel_crtc_state *cstate);
int (*compute_global_watermarks)(struct drm_atomic_state *state);
- void (*update_wm)(struct drm_crtc *crtc);
+ void (*update_wm)(struct intel_crtc *crtc);
int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
/* Returns the active state of the crtc, and if the crtc is active,
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 0dc72ba7fde7..59c94a0269f6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5073,7 +5073,7 @@ static void intel_post_plane_update(struct
intel_crtc_state *old_crtc_state)
crtc->wm.cxsr_allowed = true;
if (pipe_config->update_wm_post && pipe_config->base.active)
- intel_update_watermarks(&crtc->base);
+ intel_update_watermarks(crtc);
if (old_pri_state) {
struct intel_plane_state *primary_state =
@@ -5171,7 +5171,7 @@ static void intel_pre_plane_update(struct
intel_crtc_state *old_crtc_state)
if (dev_priv->display.initial_watermarks != NULL)
dev_priv->display.initial_watermarks(pipe_config);
else if (pipe_config->update_wm_pre)
- intel_update_watermarks(&crtc->base);
+ intel_update_watermarks(crtc);
}
static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned
plane_mask)
@@ -5491,7 +5491,7 @@ static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config,
if (dev_priv->display.initial_watermarks != NULL)
dev_priv->display.initial_watermarks(pipe_config);
else
- intel_update_watermarks(crtc);
+ intel_update_watermarks(intel_crtc);
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
@@ -6744,7 +6744,7 @@ static void valleyview_crtc_enable(struct
intel_crtc_state *pipe_config,
intel_color_load_luts(&pipe_config->base);
- intel_update_watermarks(crtc);
+ intel_update_watermarks(intel_crtc);
intel_enable_pipe(intel_crtc);
assert_vblank_disabled(crtc);
@@ -6797,7 +6797,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state
*pipe_config,
intel_color_load_luts(&pipe_config->base);
- intel_update_watermarks(crtc);
+ intel_update_watermarks(intel_crtc);
intel_enable_pipe(intel_crtc);
assert_vblank_disabled(crtc);
@@ -6913,7 +6913,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc)
encoder->base.crtc = NULL;
intel_fbc_disable(intel_crtc);
- intel_update_watermarks(crtc);
+ intel_update_watermarks(intel_crtc);
intel_disable_shared_dpll(intel_crtc);
domains = intel_crtc->enabled_power_domains;
@@ -14397,7 +14397,7 @@ static void intel_atomic_commit_tail(struct
drm_atomic_state *state)
intel_check_pch_fifo_underruns(dev_priv);
if (!crtc->state->active)
- intel_update_watermarks(crtc);
+ intel_update_watermarks(intel_crtc);
}
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7e46453adb49..64965976e32f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1718,7 +1718,7 @@ bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv, enum dpio_phy phy,
void intel_init_clock_gating(struct drm_device *dev);
void intel_suspend_hw(struct drm_device *dev);
int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
-void intel_update_watermarks(struct drm_crtc *crtc);
+void intel_update_watermarks(struct intel_crtc *crtc);
void intel_init_pm(struct drm_device *dev);
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
void intel_pm_setup(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ba663889d8ea..15ecda3d484d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/in
[Intel-gfx] [PATCH 00/26] drm/i915: A game of OCD dominoes
From: Ville Syrjälä
I pretty much just wanted to store struct intel_crtc * instead
of struct drm_crtc * in pipe_to_crtc_mapping[] & co. but to
achieve it cleanly I ended up chasing quite few different things
that were accepting the wrong kind of type. And once I had
sorted out those mappign arrays, I had ended up in the old
watermark code which kept me busy for another good while.
Eventually I was able to claw my way back to sanity and I
decided to stop.
I'm going to blame Daniel for getting me on this track by
suggesting that I should pass dev_priv to the plane
constructos. That was enough of a trigger to get me started.
Entire series available here:
git://github.com/vsyrjala/linux.git dev_priv_intel_crtc_cleanup
Ville Syrjälä (26):
drm/i915: Pass dev_priv to plane constructors
drm/i915: Pass dev_priv to skl_init_scalers()
drm/i915: Pass intel_crtc to intel_crtc_active()
drm/i915: Pass intel_crtc to update_wm functions
drm/i915: Use struct intel_crtc in legacy platform wm code
drm/i915: Store struct intel_crtc * in {pipe,plane}_to_crtc_mapping[]
drm/i915: Pass dev_priv to intel_wait_for_vblank()
drm/i915: Pass dev_priv to vlv force pll functions
drm/i915: Pass dev_priv to g4x wm functions
drm/i915: Pass dev_priv to intel_get_crtc_for_pipe()
drm/i915: Always use intel_get_crtc_for_pipe()
drm/i915: Pass dev_priv to intel_crtc_init()
drm/i915: Pass dev_priv to cdclk update funcs
drm/i915: Pass dev_priv to .get_display_clock_speed()
drm/i915: Pass dev_priv to IS_MOBILE()
drm/i915: Pass dev_priv to IS_PINEVIEW()
drm/i915: Pass dev_priv to i915_pineview_get_mem_freq() and
i915_ironlake_get_mem_freq()
drm/i915: Pass dev_priv to .get_fifo_size()
drm/i915: Pass dev_priv to HAS_FW_BLC
drm/i915: Pass dev_priv to IS_BROADWATER/IS_CRESTLINE
drm/i915: Pass dev_priv to rest of IS_FOO() macros for the old
platforms
drm/i915: Pass dev_priv to single_enabled_crtc()
drm/i915: Pass dev_priv to init_clock_gating
drm/i915: Pass dev_priv to intel_suspend_hw()
drm/i915: Pass dev_priv to ilk_setup_wm_latency() & co.
drm/i915: Pass dev_priv to intel_init_pm()
drivers/gpu/drm/i915/i915_debugfs.c| 13 +-
drivers/gpu/drm/i915/i915_drv.c| 8 +-
drivers/gpu/drm/i915/i915_drv.h| 32 +--
drivers/gpu/drm/i915/i915_gem.c| 3 +-
drivers/gpu/drm/i915/i915_gem_stolen.c | 4 +-
drivers/gpu/drm/i915/i915_irq.c| 19 +-
drivers/gpu/drm/i915/intel_crt.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 356 -
drivers/gpu/drm/i915/intel_dp.c| 25 +-
drivers/gpu/drm/i915/intel_drv.h | 37 ++-
drivers/gpu/drm/i915/intel_dvo.c | 6 +-
drivers/gpu/drm/i915/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/intel_fifo_underrun.c | 23 +-
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/intel_lvds.c | 6 +-
drivers/gpu/drm/i915/intel_pm.c| 408 +
drivers/gpu/drm/i915/intel_runtime_pm.c| 2 +-
drivers/gpu/drm/i915/intel_sdvo.c | 8 +-
drivers/gpu/drm/i915/intel_sprite.c| 12 +-
drivers/gpu/drm/i915/intel_tv.c| 6 +-
20 files changed, 455 insertions(+), 519 deletions(-)
--
2.7.4
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[Intel-gfx] [PATCH 01/26] drm/i915: Pass dev_priv to plane constructors
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 40 +---
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_sprite.c | 12 +--
4 files changed, 27 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 51360d199263..19828460bbee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -185,7 +185,7 @@ enum plane {
};
#define plane_name(p) ((p) + 'A')
-#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
+#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s)
+ 'A')
enum port {
PORT_NONE = -1,
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 740c68896672..637c4fffd9f3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14960,9 +14960,8 @@ const struct drm_plane_funcs intel_plane_funcs = {
};
static struct intel_plane *
-intel_primary_plane_create(struct drm_device *dev, enum pipe pipe)
+intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_plane *primary = NULL;
struct intel_plane_state *state = NULL;
const uint32_t *intel_primary_formats;
@@ -14986,7 +14985,7 @@ intel_primary_plane_create(struct drm_device *dev, enum
pipe pipe)
primary->can_scale = false;
primary->max_downscale = 1;
- if (INTEL_INFO(dev)->gen >= 9) {
+ if (INTEL_GEN(dev_priv) >= 9) {
primary->can_scale = true;
state->scaler_id = -1;
}
@@ -14994,10 +14993,10 @@ intel_primary_plane_create(struct drm_device *dev,
enum pipe pipe)
primary->plane = pipe;
primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
primary->check_plane = intel_check_primary_plane;
- if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
+ if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
primary->plane = !pipe;
- if (INTEL_INFO(dev)->gen >= 9) {
+ if (INTEL_GEN(dev_priv) >= 9) {
intel_primary_formats = skl_primary_formats;
num_formats = ARRAY_SIZE(skl_primary_formats);
@@ -15009,7 +15008,7 @@ intel_primary_plane_create(struct drm_device *dev, enum
pipe pipe)
primary->update_plane = ironlake_update_primary_plane;
primary->disable_plane = i9xx_disable_primary_plane;
- } else if (INTEL_INFO(dev)->gen >= 4) {
+ } else if (INTEL_GEN(dev_priv) >= 4) {
intel_primary_formats = i965_primary_formats;
num_formats = ARRAY_SIZE(i965_primary_formats);
@@ -15023,21 +15022,21 @@ intel_primary_plane_create(struct drm_device *dev,
enum pipe pipe)
primary->disable_plane = i9xx_disable_primary_plane;
}
- if (INTEL_INFO(dev)->gen >= 9)
- ret = drm_universal_plane_init(dev, &primary->base, 0,
- &intel_plane_funcs,
+ if (INTEL_GEN(dev_priv) >= 9)
+ ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
+ 0, &intel_plane_funcs,
intel_primary_formats,
num_formats,
DRM_PLANE_TYPE_PRIMARY,
"plane 1%c", pipe_name(pipe));
else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
- ret = drm_universal_plane_init(dev, &primary->base, 0,
- &intel_plane_funcs,
+ ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
+ 0, &intel_plane_funcs,
intel_primary_formats,
num_formats,
DRM_PLANE_TYPE_PRIMARY,
"primary %c", pipe_name(pipe));
else
- ret = drm_universal_plane_init(dev, &primary->base, 0,
- &intel_plane_funcs,
+ ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
+ 0, &intel_plane_funcs,
intel_primary_formats,
num_formats,
DRM_PLANE_TYPE_PRIMARY,
"plane %c",
plane_name(primary->plane));
@@ -15165,9 +15164,8 @@ intel_update_cursor_plane(struct drm_plane *plane,
}
static struct intel_plane *
-intel_cursor_plane_crea
[Intel-gfx] [PATCH 05/26] drm/i915: Use struct intel_crtc in legacy platform wm code
From: Ville Syrjälä
Unify our approach to things by using intel_crtc instead of drm_crtc.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 109
1 file changed, 67 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 15ecda3d484d..11bdc4b2c041 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -624,12 +624,12 @@ static unsigned long intel_calculate_wm(unsigned long
clock_in_khz,
return wm_size;
}
-static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
+static struct intel_crtc *single_enabled_crtc(struct drm_device *dev)
{
- struct drm_crtc *crtc, *enabled = NULL;
+ struct intel_crtc *crtc, *enabled = NULL;
- for_each_crtc(dev, crtc) {
- if (intel_crtc_active(to_intel_crtc(crtc))) {
+ for_each_intel_crtc(dev, crtc) {
+ if (intel_crtc_active(crtc)) {
if (enabled)
return NULL;
enabled = crtc;
@@ -643,7 +643,7 @@ static void pineview_update_wm(struct intel_crtc
*unused_crtc)
{
struct drm_device *dev = unused_crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_crtc *crtc;
+ struct intel_crtc *crtc;
const struct cxsr_latency *latency;
u32 reg;
unsigned long wm;
@@ -660,8 +660,11 @@ static void pineview_update_wm(struct intel_crtc
*unused_crtc)
crtc = single_enabled_crtc(dev);
if (crtc) {
- const struct drm_display_mode *adjusted_mode =
&to_intel_crtc(crtc)->config->base.adjusted_mode;
- int cpp =
drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
+ const struct drm_display_mode *adjusted_mode =
+ &crtc->config->base.adjusted_mode;
+ const struct drm_framebuffer *fb =
+ crtc->base.primary->state->fb;
+ int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
int clock = adjusted_mode->crtc_clock;
/* Display SR */
@@ -717,24 +720,26 @@ static bool g4x_compute_wm0(struct drm_device *dev,
int *plane_wm,
int *cursor_wm)
{
- struct drm_crtc *crtc;
+ struct intel_crtc *crtc;
const struct drm_display_mode *adjusted_mode;
+ const struct drm_framebuffer *fb;
int htotal, hdisplay, clock, cpp;
int line_time_us, line_count;
int entries, tlb_miss;
- crtc = intel_get_crtc_for_plane(dev, plane);
- if (!intel_crtc_active(to_intel_crtc(crtc))) {
+ crtc = to_intel_crtc(intel_get_crtc_for_plane(dev, plane));
+ if (!intel_crtc_active(crtc)) {
*cursor_wm = cursor->guard_size;
*plane_wm = display->guard_size;
return false;
}
- adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
+ adjusted_mode = &crtc->config->base.adjusted_mode;
+ fb = crtc->base.primary->state->fb;
clock = adjusted_mode->crtc_clock;
htotal = adjusted_mode->crtc_htotal;
- hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
- cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
+ hdisplay = crtc->config->pipe_src_w;
+ cpp = drm_format_plane_cpp(fb->pixel_format, 0);
/* Use the small buffer method to calculate plane watermark */
entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
@@ -749,7 +754,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
/* Use the large buffer method to calculate cursor watermark */
line_time_us = max(htotal * 1000 / clock, 1);
line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
- entries = line_count * crtc->cursor->state->crtc_w * cpp;
+ entries = line_count * crtc->base.cursor->state->crtc_w * cpp;
tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
if (tlb_miss > 0)
entries += tlb_miss;
@@ -803,8 +808,9 @@ static bool g4x_compute_srwm(struct drm_device *dev,
const struct intel_watermark_params *cursor,
int *display_wm, int *cursor_wm)
{
- struct drm_crtc *crtc;
+ struct intel_crtc *crtc;
const struct drm_display_mode *adjusted_mode;
+ const struct drm_framebuffer *fb;
int hdisplay, htotal, cpp, clock;
unsigned long line_time_us;
int line_count, line_size;
@@ -816,12 +822,13 @@ static bool g4x_compute_srwm(struct drm_device *dev,
return false;
}
- crtc = intel_get_crtc_for_plane(dev, plane);
- adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
+ crtc = to_intel_crtc(intel_get_crtc_for_plane(dev, plane))
[Intel-gfx] [PATCH 14/26] drm/i915: Pass dev_priv to .get_display_clock_speed()
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_display.c| 77 +++--
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
3 files changed, 38 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e9d7f3242185..0bb4751c645f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -494,7 +494,7 @@ struct intel_limit;
struct dpll;
struct drm_i915_display_funcs {
- int (*get_display_clock_speed)(struct drm_device *dev);
+ int (*get_display_clock_speed)(struct drm_i915_private *dev_priv);
int (*get_fifo_size)(struct drm_device *dev, int plane);
int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
int (*compute_intermediate_wm)(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a8cdd2ef1dd6..033422e7ab34 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5903,7 +5903,7 @@ static void intel_update_max_cdclk(struct
drm_i915_private *dev_priv)
static void intel_update_cdclk(struct drm_i915_private *dev_priv)
{
- dev_priv->cdclk_freq =
dev_priv->display.get_display_clock_speed(&dev_priv->drm);
+ dev_priv->cdclk_freq =
dev_priv->display.get_display_clock_speed(dev_priv);
if (INTEL_GEN(dev_priv) >= 9)
DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz,
ref: %d kHz\n",
@@ -6421,7 +6421,7 @@ static void valleyview_set_cdclk(struct drm_device *dev,
int cdclk)
struct drm_i915_private *dev_priv = to_i915(dev);
u32 val, cmd;
- WARN_ON(dev_priv->display.get_display_clock_speed(dev)
+ WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
!= dev_priv->cdclk_freq);
if (cdclk >= 32) /* jump to highest voltage for 400MHz too */
@@ -6486,7 +6486,7 @@ static void cherryview_set_cdclk(struct drm_device *dev,
int cdclk)
struct drm_i915_private *dev_priv = to_i915(dev);
u32 val, cmd;
- WARN_ON(dev_priv->display.get_display_clock_speed(dev)
+ WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
!= dev_priv->cdclk_freq);
switch (cdclk) {
@@ -7245,10 +7245,9 @@ static int intel_crtc_compute_config(struct intel_crtc
*crtc,
return 0;
}
-static int skylake_get_display_clock_speed(struct drm_device *dev)
+static int skylake_get_display_clock_speed(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
- uint32_t cdctl;
+ u32 cdctl;
skl_dpll0_update(dev_priv);
@@ -7307,9 +7306,8 @@ static void bxt_de_pll_update(struct drm_i915_private
*dev_priv)
dev_priv->cdclk_pll.ref;
}
-static int broxton_get_display_clock_speed(struct drm_device *dev)
+static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
u32 divider;
int div, vco;
@@ -7342,9 +7340,8 @@ static int broxton_get_display_clock_speed(struct
drm_device *dev)
return DIV_ROUND_CLOSEST(vco, div);
}
-static int broadwell_get_display_clock_speed(struct drm_device *dev)
+static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
uint32_t lcpll = I915_READ(LCPLL_CTL);
uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
@@ -7362,9 +7359,8 @@ static int broadwell_get_display_clock_speed(struct
drm_device *dev)
return 675000;
}
-static int haswell_get_display_clock_speed(struct drm_device *dev)
+static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
uint32_t lcpll = I915_READ(LCPLL_CTL);
uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
@@ -7380,35 +7376,35 @@ static int haswell_get_display_clock_speed(struct
drm_device *dev)
return 54;
}
-static int valleyview_get_display_clock_speed(struct drm_device *dev)
+static int valleyview_get_display_clock_speed(struct drm_i915_private
*dev_priv)
{
- return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
+ return vlv_get_cck_clock_hpll(dev_priv, "cdclk",
CCK_DISPLAY_CLOCK_CONTROL);
}
-static int ilk_get_display_clock_speed(struct drm_device *dev)
+static int ilk_get_display_clock_speed(struct drm_i915_private *dev_priv)
{
return 45;
}
-static int i945_get_display_clock_speed(struct drm_device *dev)
+static int i945_get_display_clock_speed(struct drm_i915_private *dev_priv)
{
return
[Intel-gfx] [PATCH 20/26] drm/i915: Pass dev_priv to IS_BROADWATER/IS_CRESTLINE
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.c | 3 +--
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_gem.c | 3 ++-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6a99544c98d3..c98e92ea43c2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -981,7 +981,6 @@ static void intel_sanitize_options(struct drm_i915_private
*dev_priv)
static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
- struct drm_device *dev = &dev_priv->drm;
int ret;
if (i915_inject_load_failure())
@@ -1039,7 +1038,7 @@ static int i915_driver_init_hw(struct drm_i915_private
*dev_priv)
* behaviour if any general state is accessed within a page above 4GB,
* which also needs to be handled carefully.
*/
- if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) {
+ if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv)) {
ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
if (ret) {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d0deb24b0f6e..bb170f32dce0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2722,8 +2722,8 @@ struct drm_i915_cmd_table {
#define IS_I915GM(dev_priv)(INTEL_DEVID(dev_priv) == 0x2592)
#define IS_I945G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2772)
#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
-#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
-#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
+#define IS_BROADWATER(dev_priv)((dev_priv)->info.is_broadwater)
+#define IS_CRESTLINE(dev_priv) ((dev_priv)->info.is_crestline)
#define IS_GM45(dev_priv) (INTEL_DEVID(dev_priv) == 0x2A42)
#define IS_G4X(dev_priv) ((dev_priv)->info.is_g4x)
#define IS_PINEVIEW_G(dev_priv)(INTEL_DEVID(dev_priv) == 0xa001)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1e5d2bf777e4..e84951d6a720 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4150,6 +4150,7 @@ static const struct drm_i915_gem_object_ops
i915_gem_object_ops = {
struct drm_i915_gem_object *
i915_gem_object_create(struct drm_device *dev, u64 size)
{
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_i915_gem_object *obj;
struct address_space *mapping;
gfp_t mask;
@@ -4175,7 +4176,7 @@ i915_gem_object_create(struct drm_device *dev, u64 size)
goto fail;
mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
- if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
+ if (IS_CRESTLINE(dev_priv) || IS_BROADWATER(dev_priv)) {
/* 965gm cannot relocate objects above 4GiB. */
mask &= ~__GFP_HIGHMEM;
mask |= __GFP_DMA32;
--
2.7.4
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 21/26] drm/i915: Pass dev_priv to rest of IS_FOO() macros for the old platforms
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h| 8
drivers/gpu/drm/i915/i915_gem_stolen.c | 4 ++--
drivers/gpu/drm/i915/intel_pm.c| 2 +-
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bb170f32dce0..c142fd07a7a3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2716,12 +2716,12 @@ struct drm_i915_cmd_table {
#define IS_I830(dev_priv) (INTEL_DEVID(dev_priv) == 0x3577)
#define IS_845G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2562)
-#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
+#define IS_I85X(dev_priv) ((dev_priv)->info.is_i85x)
#define IS_I865G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2572)
-#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
+#define IS_I915G(dev_priv) ((dev_priv)->info.is_i915g)
#define IS_I915GM(dev_priv)(INTEL_DEVID(dev_priv) == 0x2592)
#define IS_I945G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2772)
-#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
+#define IS_I945GM(dev_priv)((dev_priv)->info.is_i945gm)
#define IS_BROADWATER(dev_priv)((dev_priv)->info.is_broadwater)
#define IS_CRESTLINE(dev_priv) ((dev_priv)->info.is_crestline)
#define IS_GM45(dev_priv) (INTEL_DEVID(dev_priv) == 0x2A42)
@@ -2729,7 +2729,7 @@ struct drm_i915_cmd_table {
#define IS_PINEVIEW_G(dev_priv)(INTEL_DEVID(dev_priv) == 0xa001)
#define IS_PINEVIEW_M(dev_priv)(INTEL_DEVID(dev_priv) == 0xa011)
#define IS_PINEVIEW(dev_priv) ((dev_priv)->info.is_pineview)
-#define IS_G33(dev)(INTEL_INFO(dev)->is_g33)
+#define IS_G33(dev_priv) ((dev_priv)->info.is_g33)
#define IS_IRONLAKE_M(dev_priv)(INTEL_DEVID(dev_priv) == 0x0046)
#define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.is_ivybridge)
#define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 1a63ffa4d189..3725a1d3b254 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -109,7 +109,7 @@ static unsigned long i915_stolen_to_physical(struct
drm_device *dev)
*
*/
base = 0;
- if (INTEL_INFO(dev)->gen >= 3) {
+ if (INTEL_GEN(dev_priv) >= 3) {
u32 bsm;
pci_read_config_dword(pdev, INTEL_BSM, &bsm);
@@ -138,7 +138,7 @@ static unsigned long i915_stolen_to_physical(struct
drm_device *dev)
I865_TOUD, &toud);
base = (toud << 16) + tseg_size;
- } else if (IS_I85X(dev)) {
+ } else if (IS_I85X(dev_priv)) {
u32 tseg_size = 0;
u32 tom;
u8 tmp;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4cdfd881ab05..70c2aa6b9ac0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1529,7 +1529,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
int planea_wm, planeb_wm;
struct intel_crtc *crtc, *enabled = NULL;
- if (IS_I945GM(dev))
+ if (IS_I945GM(dev_priv))
wm_info = &i945_wm_info;
else if (!IS_GEN2(dev_priv))
wm_info = &i915_wm_info;
--
2.7.4
___
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[Intel-gfx] [PATCH 11/26] drm/i915: Always use intel_get_crtc_for_pipe()
From: Ville Syrjälä
Replace the open coded dev_priv->pipe_to_crtc_mapping[] usage with
intel_get_crtc_for_pipe().
Mostly done with coccinelle, with a few manual tweaks
@@
expression E1, E2;
@@
(
- E1->pipe_to_crtc_mapping[E2]
+ intel_get_crtc_for_pipe(E1, E2)
|
- E1->plane_to_crtc_mapping[E2]
+ intel_get_crtc_for_plane(E1, E2)
)
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_debugfs.c| 5 +++--
drivers/gpu/drm/i915/i915_irq.c| 6 --
drivers/gpu/drm/i915/intel_display.c | 21 -
drivers/gpu/drm/i915/intel_fifo_underrun.c | 11 ++-
drivers/gpu/drm/i915/intel_pm.c| 2 +-
5 files changed, 26 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a4090a5237a6..0bdfae5d77bf 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4066,7 +4066,7 @@ static void hsw_trans_edp_pipe_A_crc_wa(struct
drm_i915_private *dev_priv,
bool enable)
{
struct drm_device *dev = &dev_priv->drm;
- struct intel_crtc *crtc = dev_priv->pipe_to_crtc_mapping[PIPE_A];
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
struct intel_crtc_state *pipe_config;
struct drm_atomic_state *state;
int ret = 0;
@@ -4204,7 +4204,8 @@ static int pipe_crc_set_source(struct drm_i915_private
*dev_priv,
/* real source -> none transition */
if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
struct intel_pipe_crc_entry *entries;
- struct intel_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
+ pipe);
DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
pipe_name(pipe));
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ed3175f34a52..67ab4c7043a8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -725,7 +725,8 @@ static u32 i915_get_vblank_counter(struct drm_device *dev,
unsigned int pipe)
struct drm_i915_private *dev_priv = to_i915(dev);
i915_reg_t high_frame, low_frame;
u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
- struct intel_crtc *intel_crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+ struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
+ pipe);
const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
htotal = mode->crtc_htotal;
@@ -830,7 +831,8 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev,
unsigned int pipe,
const struct drm_display_mode *mode)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+ struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
+ pipe);
int position;
int vbl_start, vbl_end, hsync_start, htotal, vtotal;
bool in_vbl = true;
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 07764b2ffbb1..176bea047eed 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1030,7 +1030,7 @@ bool intel_crtc_active(struct intel_crtc *crtc)
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
- struct intel_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
return crtc->config->cpu_transcoder;
}
@@ -1785,7 +1785,8 @@ void vlv_wait_port_ready(struct drm_i915_private
*dev_priv,
static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
- struct intel_crtc *intel_crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+ struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
+ pipe);
i915_reg_t reg;
uint32_t val, pipeconf_val;
@@ -11662,7 +11663,7 @@ static bool pageflip_finished(struct intel_crtc *crtc,
void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
{
struct drm_device *dev = &dev_priv->drm;
- struct intel_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
struct intel_flip_work *work;
unsigned long flags;
@@ -11688,7 +11689,7 @@ void intel_finish_page_flip_cs(struct drm_i915_private
*dev_priv, int p
[Intel-gfx] [PATCH 16/26] drm/i915: Pass dev_priv to IS_PINEVIEW()
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 19 +--
drivers/gpu/drm/i915/intel_pm.c | 9 -
3 files changed, 14 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f4d3d08b0c3a..9f99be91d0af 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2728,7 +2728,7 @@ struct drm_i915_cmd_table {
#define IS_G4X(dev_priv) ((dev_priv)->info.is_g4x)
#define IS_PINEVIEW_G(dev_priv)(INTEL_DEVID(dev_priv) == 0xa001)
#define IS_PINEVIEW_M(dev_priv)(INTEL_DEVID(dev_priv) == 0xa011)
-#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
+#define IS_PINEVIEW(dev_priv) ((dev_priv)->info.is_pineview)
#define IS_G33(dev)(INTEL_INFO(dev)->is_g33)
#define IS_IRONLAKE_M(dev_priv)(INTEL_DEVID(dev_priv) == 0x0046)
#define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.is_ivybridge)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index df359edbc87b..df58a155a6e4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7721,10 +7721,10 @@ static void i9xx_update_pll_dividers(struct intel_crtc
*crtc,
struct intel_crtc_state *crtc_state,
struct dpll *reduced_clock)
{
- struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 fp, fp2 = 0;
- if (IS_PINEVIEW(dev)) {
+ if (IS_PINEVIEW(dev_priv)) {
fp = pnv_dpll_compute_fp(&crtc_state->dpll);
if (reduced_clock)
fp2 = pnv_dpll_compute_fp(reduced_clock);
@@ -8143,8 +8143,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state,
struct dpll *reduced_clock)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 dpll;
struct dpll *clock = &crtc_state->dpll;
@@ -8170,7 +8169,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
dpll |= DPLL_SDVO_HIGH_SPEED;
/* compute bitmask from p1 value */
- if (IS_PINEVIEW(dev))
+ if (IS_PINEVIEW(dev_priv))
dpll |= (1 << (clock->p1 - 1)) <<
DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
else {
dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
@@ -8191,7 +8190,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
break;
}
- if (INTEL_INFO(dev)->gen >= 4)
+ if (INTEL_GEN(dev_priv) >= 4)
dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
if (crtc_state->sdvo_tv_clock)
@@ -8205,7 +8204,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
dpll |= DPLL_VCO_ENABLE;
crtc_state->dpll_hw_state.dpll = dpll;
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_GEN(dev_priv) >= 4) {
u32 dpll_md = (crtc_state->pixel_multiplier - 1)
<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
crtc_state->dpll_hw_state.dpll_md = dpll_md;
@@ -11353,7 +11352,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
fp = pipe_config->dpll_hw_state.fp1;
clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
- if (IS_PINEVIEW(dev)) {
+ if (IS_PINEVIEW(dev_priv)) {
clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT)
- 1;
clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
} else {
@@ -11362,7 +11361,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
}
if (!IS_GEN2(dev_priv)) {
- if (IS_PINEVIEW(dev))
+ if (IS_PINEVIEW(dev_priv))
clock.p1 = ffs((dpll &
DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
else
@@ -11384,7 +11383,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
return;
}
- if (IS_PINEVIEW(dev))
+ if (IS_PINEVIEW(dev_priv))
port_clock = pnv_calc_dpll_params(refclk, &clock);
else
port_clock = i9xx_calc_dpll_params(refclk, &clock);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 871685f3fd26..5a5c4b96d9e4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -319,7 +319
[Intel-gfx] [PATCH 07/26] drm/i915: Pass dev_priv to intel_wait_for_vblank()
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/intel_crt.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 30 --
drivers/gpu/drm/i915/intel_dp.c | 18 +-
drivers/gpu/drm/i915/intel_drv.h | 10 +-
drivers/gpu/drm/i915/intel_hdmi.c| 2 +-
drivers/gpu/drm/i915/intel_sdvo.c| 4 ++--
drivers/gpu/drm/i915/intel_tv.c | 6 +++---
8 files changed, 38 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 7a18cdc9e29e..324ea7d87237 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4212,7 +4212,7 @@ static int pipe_crc_set_source(struct drm_i915_private
*dev_priv,
drm_modeset_lock(&crtc->base.mutex, NULL);
if (crtc->base.state->active)
- intel_wait_for_vblank(dev, pipe);
+ intel_wait_for_vblank(dev_priv, pipe);
drm_modeset_unlock(&crtc->base.mutex);
spin_lock_irq(&pipe_crc->lock);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index a97151fcb9f4..30eb95b54dcf 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -573,7 +573,7 @@ intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
POSTING_READ(pipeconf_reg);
/* Wait for next Vblank to substitue
* border color for Color info */
- intel_wait_for_vblank(dev, pipe);
+ intel_wait_for_vblank(dev_priv, pipe);
st00 = I915_READ8(_VGA_MSR_WRITE);
status = ((st00 & (1 << 4)) != 0) ?
connector_status_connected :
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9637dccd47e6..2de5371e4e35 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4249,6 +4249,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
bool intel_has_pending_fb_unpin(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *crtc;
/* Note that we don't need to be called with mode_config.lock here
@@ -4263,7 +4264,7 @@ bool intel_has_pending_fb_unpin(struct drm_device *dev)
continue;
if (crtc->flip_work)
- intel_wait_for_vblank(dev, crtc->pipe);
+ intel_wait_for_vblank(dev_priv, crtc->pipe);
return true;
}
@@ -4940,7 +4941,7 @@ void hsw_disable_ips(struct intel_crtc *crtc)
}
/* We need to wait for a vblank before we can disable the plane. */
- intel_wait_for_vblank(dev, crtc->pipe);
+ intel_wait_for_vblank(dev_priv, crtc->pipe);
}
static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
@@ -5052,7 +5053,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
if (HAS_GMCH_DISPLAY(dev_priv)) {
intel_set_memory_cxsr(dev_priv, false);
dev_priv->wm.vlv.cxsr = false;
- intel_wait_for_vblank(dev, pipe);
+ intel_wait_for_vblank(dev_priv, pipe);
}
}
@@ -5129,7 +5130,7 @@ static void intel_pre_plane_update(struct
intel_crtc_state *old_crtc_state)
if (old_crtc_state->base.active) {
intel_set_memory_cxsr(dev_priv, false);
dev_priv->wm.vlv.cxsr = false;
- intel_wait_for_vblank(dev, crtc->pipe);
+ intel_wait_for_vblank(dev_priv, crtc->pipe);
}
}
@@ -5142,7 +5143,7 @@ static void intel_pre_plane_update(struct
intel_crtc_state *old_crtc_state)
*/
if (pipe_config->disable_lp_wm) {
ilk_disable_lp_wm(dev);
- intel_wait_for_vblank(dev, crtc->pipe);
+ intel_wait_for_vblank(dev_priv, crtc->pipe);
}
/*
@@ -5397,7 +5398,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state
*pipe_config,
/* Must wait for vblank to avoid spurious PCH FIFO underruns */
if (intel_crtc->config->has_pch_encoder)
- intel_wait_for_vblank(dev, pipe);
+ intel_wait_for_vblank(dev_priv, pipe);
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
}
@@ -5507,8 +5508,8 @@ static void haswell_crtc_enable(struct intel_crtc_state
*pipe_config,
intel_encoders_enable(crtc, pipe_config, old_state);
if (intel_crtc->config->has_pch_encoder) {
- intel_wait_for_vblank(dev, pipe);
- intel_wait_for_vblank(dev, pipe);
+
[Intel-gfx] [PATCH 26/26] drm/i915: Pass dev_priv to intel_init_pm()
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 8 +++-
3 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ddda01361e3b..093af6e4ab40 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -16419,7 +16419,7 @@ int intel_modeset_init(struct drm_device *dev)
intel_init_quirks(dev);
- intel_init_pm(dev);
+ intel_init_pm(dev_priv);
if (INTEL_INFO(dev)->num_pipes == 0)
return 0;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 71d394609f73..9174b0c7e3db 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1716,7 +1716,7 @@ void intel_init_clock_gating(struct drm_i915_private
*dev_priv);
void intel_suspend_hw(struct drm_i915_private *dev_priv);
int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
void intel_update_watermarks(struct intel_crtc *crtc);
-void intel_init_pm(struct drm_device *dev);
+void intel_init_pm(struct drm_i915_private *dev_priv);
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
void intel_pm_setup(struct drm_device *dev);
void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 477dee881df8..abe82edd3c45 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7693,10 +7693,8 @@ void intel_init_clock_gating_hooks(struct
drm_i915_private *dev_priv)
}
/* Set up chip specific power management-related functions */
-void intel_init_pm(struct drm_device *dev)
+void intel_init_pm(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
intel_fbc_init(dev_priv);
/* For cxsr */
@@ -7706,7 +7704,7 @@ void intel_init_pm(struct drm_device *dev)
i915_ironlake_get_mem_freq(dev_priv);
/* For FIFO watermark updates */
- if (INTEL_INFO(dev)->gen >= 9) {
+ if (INTEL_GEN(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
dev_priv->display.update_wm = skl_update_wm;
dev_priv->display.compute_global_watermarks = skl_compute_wm;
@@ -7757,7 +7755,7 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
} else if (IS_GEN2(dev_priv)) {
- if (INTEL_INFO(dev)->num_pipes == 1) {
+ if (INTEL_INFO(dev_priv)->num_pipes == 1) {
dev_priv->display.update_wm = i845_update_wm;
dev_priv->display.get_fifo_size = i845_get_fifo_size;
} else {
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 18/26] drm/i915: Pass dev_priv to .get_fifo_size()
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 22 +-
2 files changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9f99be91d0af..3d3331ed70e6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -495,7 +495,7 @@ struct dpll;
struct drm_i915_display_funcs {
int (*get_display_clock_speed)(struct drm_i915_private *dev_priv);
- int (*get_fifo_size)(struct drm_device *dev, int plane);
+ int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
int (*compute_intermediate_wm)(struct drm_device *dev,
struct intel_crtc *intel_crtc,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index edd708af1564..6c98f83f2694 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -374,10 +374,9 @@ static const int pessimal_latency_ns = 5000;
#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
dsparb) >> (lo_shift)) & 0xff) | dsparb2) >> (hi_shift)) & 0x1)
<< 8))
-static int vlv_get_fifo_size(struct drm_device *dev,
+static int vlv_get_fifo_size(struct drm_i915_private *dev_priv,
enum pipe pipe, int plane)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
int sprite0_start, sprite1_start, size;
switch (pipe) {
@@ -426,9 +425,8 @@ static int vlv_get_fifo_size(struct drm_device *dev,
return size;
}
-static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
+static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
uint32_t dsparb = I915_READ(DSPARB);
int size;
@@ -442,9 +440,8 @@ static int i9xx_get_fifo_size(struct drm_device *dev, int
plane)
return size;
}
-static int i830_get_fifo_size(struct drm_device *dev, int plane)
+static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
uint32_t dsparb = I915_READ(DSPARB);
int size;
@@ -459,9 +456,8 @@ static int i830_get_fifo_size(struct drm_device *dev, int
plane)
return size;
}
-static int i845_get_fifo_size(struct drm_device *dev, int plane)
+static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
uint32_t dsparb = I915_READ(DSPARB);
int size;
@@ -1540,7 +1536,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
else
wm_info = &i830_a_wm_info;
- fifo_size = dev_priv->display.get_fifo_size(dev, 0);
+ fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
crtc = intel_get_crtc_for_plane(dev_priv, 0);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *adjusted_mode =
@@ -1567,7 +1563,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
if (IS_GEN2(dev_priv))
wm_info = &i830_bc_wm_info;
- fifo_size = dev_priv->display.get_fifo_size(dev, 1);
+ fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
crtc = intel_get_crtc_for_plane(dev_priv, 1);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *adjusted_mode =
@@ -1685,7 +1681,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
adjusted_mode = &crtc->config->base.adjusted_mode;
planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
&i845_wm_info,
- dev_priv->display.get_fifo_size(dev, 0),
+
dev_priv->display.get_fifo_size(dev_priv, 0),
4, pessimal_latency_ns);
fwater_lo = I915_READ(FW_BLC) & ~0xfff;
fwater_lo |= (3<<8) | planea_wm;
@@ -4572,11 +4568,11 @@ void vlv_wm_get_hw_state(struct drm_device *dev)
plane->wm.fifo_size = 63;
break;
case DRM_PLANE_TYPE_PRIMARY:
- plane->wm.fifo_size = vlv_get_fifo_size(dev,
plane->pipe, 0);
+ plane->wm.fifo_size = vlv_get_fifo_size(dev_priv,
plane->pipe, 0);
break;
case DRM_PLANE_TYPE_OVERLAY:
sprite = plane->plane;
- plane->wm.fifo_size = vlv_get_fifo_size(dev,
plane->pipe, sprite + 1);
+ plane->wm.fifo_size = vlv_get_fifo_size(dev_priv,
plane->pipe, sprite + 1);
break;
[Intel-gfx] [PATCH 17/26] drm/i915: Pass dev_priv to i915_pineview_get_mem_freq() and i915_ironlake_get_mem_freq()
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5a5c4b96d9e4..edd708af1564 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -107,9 +107,8 @@ static void bxt_init_clock_gating(struct drm_device *dev)
PWM1_GATING_DIS | PWM2_GATING_DIS);
}
-static void i915_pineview_get_mem_freq(struct drm_device *dev)
+static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
u32 tmp;
tmp = I915_READ(CLKCFG);
@@ -146,9 +145,8 @@ static void i915_pineview_get_mem_freq(struct drm_device
*dev)
dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
}
-static void i915_ironlake_get_mem_freq(struct drm_device *dev)
+static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
u16 ddrpll, csipll;
ddrpll = I915_READ16(DDRMPLL1);
@@ -7760,9 +7758,9 @@ void intel_init_pm(struct drm_device *dev)
/* For cxsr */
if (IS_PINEVIEW(dev_priv))
- i915_pineview_get_mem_freq(dev);
+ i915_pineview_get_mem_freq(dev_priv);
else if (IS_GEN5(dev_priv))
- i915_ironlake_get_mem_freq(dev);
+ i915_ironlake_get_mem_freq(dev_priv);
/* For FIFO watermark updates */
if (INTEL_INFO(dev)->gen >= 9) {
--
2.7.4
___
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[Intel-gfx] [PATCH 13/26] drm/i915: Pass dev_priv to cdclk update funcs
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 35 +++
1 file changed, 15 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9614eed206df..a8cdd2ef1dd6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5842,10 +5842,8 @@ static int intel_compute_max_dotclk(struct
drm_i915_private *dev_priv)
static int skl_calc_cdclk(int max_pixclk, int vco);
-static void intel_update_max_cdclk(struct drm_device *dev)
+static void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
int max_cdclk, vco;
@@ -5903,11 +5901,9 @@ static void intel_update_max_cdclk(struct drm_device
*dev)
dev_priv->max_dotclk_freq);
}
-static void intel_update_cdclk(struct drm_device *dev)
+static void intel_update_cdclk(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
- dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
+ dev_priv->cdclk_freq =
dev_priv->display.get_display_clock_speed(&dev_priv->drm);
if (INTEL_GEN(dev_priv) >= 9)
DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz,
ref: %d kHz\n",
@@ -6068,14 +6064,14 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv, int cdclk)
return;
}
- intel_update_cdclk(&dev_priv->drm);
+ intel_update_cdclk(dev_priv);
}
static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
{
u32 cdctl, expected;
- intel_update_cdclk(&dev_priv->drm);
+ intel_update_cdclk(dev_priv);
if (dev_priv->cdclk_pll.vco == 0 ||
dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
@@ -6208,7 +6204,7 @@ void skl_set_preferred_cdclk_vco(struct drm_i915_private
*dev_priv, int vco)
dev_priv->skl_preferred_vco_freq = vco;
if (changed)
- intel_update_max_cdclk(&dev_priv->drm);
+ intel_update_max_cdclk(dev_priv);
}
static void
@@ -6294,7 +6290,6 @@ static bool skl_cdclk_wait_for_pcu_ready(struct
drm_i915_private *dev_priv)
static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int
vco)
{
- struct drm_device *dev = &dev_priv->drm;
u32 freq_select, pcu_ack;
WARN_ON((cdclk == 24000) != (vco == 0));
@@ -6345,7 +6340,7 @@ static void skl_set_cdclk(struct drm_i915_private
*dev_priv, int cdclk, int vco)
sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
mutex_unlock(&dev_priv->rps.hw_lock);
- intel_update_cdclk(dev);
+ intel_update_cdclk(dev_priv);
}
static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
@@ -6392,7 +6387,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private
*dev_priv)
if ((I915_READ(SWF_ILK(0x18)) & 0x00FF) == 0)
goto sanitize;
- intel_update_cdclk(&dev_priv->drm);
+ intel_update_cdclk(dev_priv);
/* Is PLL enabled and locked ? */
if (dev_priv->cdclk_pll.vco == 0 ||
dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
@@ -6483,7 +6478,7 @@ static void valleyview_set_cdclk(struct drm_device *dev,
int cdclk)
mutex_unlock(&dev_priv->sb_lock);
- intel_update_cdclk(dev);
+ intel_update_cdclk(dev_priv);
}
static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
@@ -6524,7 +6519,7 @@ static void cherryview_set_cdclk(struct drm_device *dev,
int cdclk)
}
mutex_unlock(&dev_priv->rps.hw_lock);
- intel_update_cdclk(dev);
+ intel_update_cdclk(dev_priv);
}
static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
@@ -10188,7 +10183,7 @@ static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv)
}
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
- intel_update_cdclk(&dev_priv->drm);
+ intel_update_cdclk(dev_priv);
}
/*
@@ -10368,7 +10363,7 @@ static void broadwell_set_cdclk(struct drm_device *dev,
int cdclk)
I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
- intel_update_cdclk(dev);
+ intel_update_cdclk(dev_priv);
WARN(cdclk != dev_priv->cdclk_freq,
"cdclk requested %d kHz but got %d kHz\n",
@@ -16323,7 +16318,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- intel_update_cdclk(dev);
+ intel_update_cdclk(dev_priv);
dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
@@ -16494,12 +16489,12
[Intel-gfx] [PATCH 15/26] drm/i915: Pass dev_priv to IS_MOBILE()
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 8 +++-
drivers/gpu/drm/i915/intel_sdvo.c| 4 ++--
3 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0bb4751c645f..f4d3d08b0c3a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2742,7 +2742,7 @@ struct drm_i915_cmd_table {
#define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
#define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
#define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
-#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
+#define IS_MOBILE(dev_priv)((dev_priv)->info.is_mobile)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 033422e7ab34..df359edbc87b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15374,11 +15374,9 @@ static int intel_encoder_clones(struct intel_encoder
*encoder)
return index_mask;
}
-static bool has_edp_a(struct drm_device *dev)
+static bool has_edp_a(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
- if (!IS_MOBILE(dev))
+ if (!IS_MOBILE(dev_priv))
return false;
if ((I915_READ(DP_A) & DP_DETECTED) == 0)
@@ -15518,7 +15516,7 @@ static void intel_setup_outputs(struct drm_device *dev)
int found;
dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
- if (has_edp_a(dev))
+ if (has_edp_a(dev_priv))
intel_dp_init(dev, DP_A, PORT_A);
if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c
b/drivers/gpu/drm/i915/intel_sdvo.c
index 5d59a48e3249..3990c805a5b5 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -2411,10 +2411,10 @@ static void
intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
struct intel_sdvo_connector *connector)
{
- struct drm_device *dev = connector->base.base.dev;
+ struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev);
intel_attach_force_audio_property(&connector->base.base);
- if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
+ if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) {
intel_attach_broadcast_rgb_property(&connector->base.base);
intel_sdvo->color_range_auto = true;
}
--
2.7.4
___
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[Intel-gfx] [PATCH 12/26] drm/i915: Pass dev_priv to intel_crtc_init()
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 176bea047eed..9614eed206df 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15236,9 +15236,8 @@ static void skl_init_scalers(struct drm_i915_private
*dev_priv,
scaler_state->scaler_id = -1;
}
-static int intel_crtc_init(struct drm_device *dev, enum pipe pipe)
+static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc;
struct intel_crtc_state *crtc_state = NULL;
struct intel_plane *primary = NULL;
@@ -15259,7 +15258,7 @@ static int intel_crtc_init(struct drm_device *dev, enum
pipe pipe)
crtc_state->base.crtc = &intel_crtc->base;
/* initialize shared scalers */
- if (INTEL_INFO(dev)->gen >= 9) {
+ if (INTEL_GEN(dev_priv) >= 9) {
if (pipe == PIPE_C)
intel_crtc->num_scalers = 1;
else
@@ -15290,7 +15289,7 @@ static int intel_crtc_init(struct drm_device *dev, enum
pipe pipe)
goto fail;
}
- ret = drm_crtc_init_with_planes(dev, &intel_crtc->base,
+ ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
&primary->base, &cursor->base,
&intel_crtc_funcs,
"pipe %c", pipe_name(pipe));
@@ -15303,7 +15302,7 @@ static int intel_crtc_init(struct drm_device *dev, enum
pipe pipe)
*/
intel_crtc->pipe = pipe;
intel_crtc->plane = (enum plane) pipe;
- if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
+ if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) {
DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
intel_crtc->plane = !pipe;
}
@@ -16487,7 +16486,7 @@ int intel_modeset_init(struct drm_device *dev)
for_each_pipe(dev_priv, pipe) {
int ret;
- ret = intel_crtc_init(dev, pipe);
+ ret = intel_crtc_init(dev_priv, pipe);
if (ret) {
drm_mode_config_cleanup(dev);
return ret;
--
2.7.4
___
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[Intel-gfx] [PATCH 06/26] drm/i915: Store struct intel_crtc * in {pipe, plane}_to_crtc_mapping[]
From: Ville Syrjälä
A lot of users of the {pipe,plane}_to_crtc_mapping[] will end up
casting the result to intel_crtc, so let's just store the intel_crtc
pointer in the first place.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_debugfs.c| 9 ++--
drivers/gpu/drm/i915/i915_drv.h| 4 +-
drivers/gpu/drm/i915/i915_irq.c| 12 +++---
drivers/gpu/drm/i915/intel_display.c | 68 ++
drivers/gpu/drm/i915/intel_drv.h | 7 ++-
drivers/gpu/drm/i915/intel_dvo.c | 4 +-
drivers/gpu/drm/i915/intel_fifo_underrun.c | 22 +-
drivers/gpu/drm/i915/intel_lvds.c | 4 +-
drivers/gpu/drm/i915/intel_pm.c| 10 ++---
9 files changed, 64 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9bef6f55f99d..7a18cdc9e29e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4066,8 +4066,7 @@ static void hsw_trans_edp_pipe_A_crc_wa(struct
drm_i915_private *dev_priv,
bool enable)
{
struct drm_device *dev = &dev_priv->drm;
- struct intel_crtc *crtc =
- to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
+ struct intel_crtc *crtc = dev_priv->pipe_to_crtc_mapping[PIPE_A];
struct intel_crtc_state *pipe_config;
struct drm_atomic_state *state;
int ret = 0;
@@ -4135,8 +4134,7 @@ static int pipe_crc_set_source(struct drm_i915_private
*dev_priv,
{
struct drm_device *dev = &dev_priv->drm;
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
- struct intel_crtc *crtc =
- to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev, pipe);
enum intel_display_power_domain power_domain;
u32 val = 0; /* shut up gcc */
int ret;
@@ -4207,8 +4205,7 @@ static int pipe_crc_set_source(struct drm_i915_private
*dev_priv,
/* real source -> none transition */
if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
struct intel_pipe_crc_entry *entries;
- struct intel_crtc *crtc =
- to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
+ struct intel_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
pipe_name(pipe));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0342c874c2de..e9d7f3242185 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1935,8 +1935,8 @@ struct drm_i915_private {
/* Kernel Modesetting */
- struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
- struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
+ struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
+ struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
wait_queue_head_t pending_flip_queue;
#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 90d0905592f2..f22fceff3a26 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -725,8 +725,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev,
unsigned int pipe)
struct drm_i915_private *dev_priv = to_i915(dev);
i915_reg_t high_frame, low_frame;
u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
- struct intel_crtc *intel_crtc =
- to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
+ struct intel_crtc *intel_crtc = dev_priv->pipe_to_crtc_mapping[pipe];
const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
htotal = mode->crtc_htotal;
@@ -831,8 +830,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev,
unsigned int pipe,
const struct drm_display_mode *mode)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_crtc *intel_crtc = dev_priv->pipe_to_crtc_mapping[pipe];
int position;
int vbl_start, vbl_end, hsync_start, htotal, vtotal;
bool in_vbl = true;
@@ -967,7 +965,7 @@ static int i915_get_vblank_timestamp(struct drm_device
*dev, unsigned int pipe,
struct timeval *vblank_time,
unsigned flags)
{
- struct drm_crtc *crtc;
+ struct intel_crtc *crtc;
if (pipe >= INTEL_INFO(dev)->num_pipes) {
DRM_ERROR("Invalid crtc %u\n", pipe);
@@ -981,7 +979,7 @@ static int i915_get_vblank_timestamp(struct drm_device
*dev, unsigned int pipe,
return -EINVAL;
}
-
[Intel-gfx] [PATCH 24/26] drm/i915: Pass dev_priv to intel_suspend_hw()
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 10 --
3 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e5e6831fa30d..c2c8bd168d55 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1435,7 +1435,7 @@ static int i915_drm_suspend(struct drm_device *dev)
intel_suspend_encoders(dev_priv);
- intel_suspend_hw(dev);
+ intel_suspend_hw(dev_priv);
i915_gem_suspend_gtt_mappings(dev);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 245911b19495..71d394609f73 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1713,7 +1713,7 @@ bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv, enum dpio_phy phy,
/* intel_pm.c */
void intel_init_clock_gating(struct drm_i915_private *dev_priv);
-void intel_suspend_hw(struct drm_device *dev);
+void intel_suspend_hw(struct drm_i915_private *dev_priv);
int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
void intel_update_watermarks(struct intel_crtc *crtc);
void intel_init_pm(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 756ba81116a3..e8e0f54b829d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7155,10 +7155,8 @@ static void lpt_init_clock_gating(struct
drm_i915_private *dev_priv)
TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
}
-static void lpt_suspend_hw(struct drm_device *dev)
+static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
if (HAS_PCH_LPT_LP(dev_priv)) {
uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
@@ -7642,10 +7640,10 @@ void intel_init_clock_gating(struct drm_i915_private
*dev_priv)
dev_priv->display.init_clock_gating(dev_priv);
}
-void intel_suspend_hw(struct drm_device *dev)
+void intel_suspend_hw(struct drm_i915_private *dev_priv)
{
- if (HAS_PCH_LPT(to_i915(dev)))
- lpt_suspend_hw(dev);
+ if (HAS_PCH_LPT(dev_priv))
+ lpt_suspend_hw(dev_priv);
}
static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
--
2.7.4
___
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[Intel-gfx] [PATCH 10/26] drm/i915: Pass dev_priv to intel_get_crtc_for_pipe()
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +--
drivers/gpu/drm/i915/i915_irq.c | 5 +++--
drivers/gpu/drm/i915/intel_display.c | 6 +++---
drivers/gpu/drm/i915/intel_drv.h | 8 +++-
drivers/gpu/drm/i915/intel_dvo.c | 2 +-
drivers/gpu/drm/i915/intel_lvds.c| 2 +-
drivers/gpu/drm/i915/intel_pm.c | 11 +--
7 files changed, 17 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 324ea7d87237..a4090a5237a6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4132,9 +4132,8 @@ static int pipe_crc_set_source(struct drm_i915_private
*dev_priv,
enum pipe pipe,
enum intel_pipe_crc_source source)
{
- struct drm_device *dev = &dev_priv->drm;
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
- struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev, pipe);
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
enum intel_display_power_domain power_domain;
u32 val = 0; /* shut up gcc */
int ret;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f22fceff3a26..ed3175f34a52 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -965,15 +965,16 @@ static int i915_get_vblank_timestamp(struct drm_device
*dev, unsigned int pipe,
struct timeval *vblank_time,
unsigned flags)
{
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *crtc;
- if (pipe >= INTEL_INFO(dev)->num_pipes) {
+ if (pipe >= INTEL_INFO(dev_priv)->num_pipes) {
DRM_ERROR("Invalid crtc %u\n", pipe);
return -EINVAL;
}
/* Get drm_crtc to timestamp: */
- crtc = intel_get_crtc_for_pipe(dev, pipe);
+ crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
if (crtc == NULL) {
DRM_ERROR("Invalid crtc %u\n", pipe);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index b9a9139d7359..07764b2ffbb1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7072,7 +7072,7 @@ static int ironlake_check_fdi_lanes(struct drm_device
*dev, enum pipe pipe,
if (pipe_config->fdi_lanes <= 2)
return 0;
- other_crtc = intel_get_crtc_for_pipe(dev, PIPE_C);
+ other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
other_crtc_state =
intel_atomic_get_crtc_state(state, other_crtc);
if (IS_ERR(other_crtc_state))
@@ -7091,7 +7091,7 @@ static int ironlake_check_fdi_lanes(struct drm_device
*dev, enum pipe pipe,
return -EINVAL;
}
- other_crtc = intel_get_crtc_for_pipe(dev, PIPE_B);
+ other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
other_crtc_state =
intel_atomic_get_crtc_state(state, other_crtc);
if (IS_ERR(other_crtc_state))
@@ -8106,7 +8106,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
const struct dpll *dpll)
{
- struct intel_crtc *crtc = intel_get_crtc_for_pipe(&dev_priv->drm, pipe);
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
struct intel_crtc_state *pipe_config;
pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index af28fbce49cb..13c9c78c4b09 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1038,16 +1038,14 @@ vlv_pipe_to_channel(enum pipe pipe)
}
static inline struct intel_crtc *
-intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
+intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
return dev_priv->pipe_to_crtc_mapping[pipe];
}
static inline struct intel_crtc *
-intel_get_crtc_for_plane(struct drm_device *dev, int plane)
+intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
return dev_priv->plane_to_crtc_mapping[plane];
}
@@ -1260,7 +1258,7 @@ intel_wait_for_vblank(struct drm_i915_private *dev_priv,
enum pipe pipe)
static inline void
intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
{
- const struct intel_crtc *crtc = intel_get_crtc_for_pipe
[Intel-gfx] [PATCH 19/26] drm/i915: Pass dev_priv to HAS_FW_BLC
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3d3331ed70e6..d0deb24b0f6e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2886,7 +2886,7 @@ struct drm_i915_cmd_table {
#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
-#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
+#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6c98f83f2694..4cdfd881ab05 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1611,7 +1611,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
intel_set_memory_cxsr(dev_priv, false);
/* Calc sr entries for one plane configs */
- if (HAS_FW_BLC(dev) && enabled) {
+ if (HAS_FW_BLC(dev_priv) && enabled) {
/* self-refresh has much higher latency */
static const int sr_latency_ns = 6000;
const struct drm_display_mode *adjusted_mode =
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 23/26] drm/i915: Pass dev_priv to init_clock_gating
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.c | 3 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 129 ---
5 files changed, 49 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c98e92ea43c2..e5e6831fa30d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2264,7 +2264,6 @@ static int vlv_suspend_complete(struct drm_i915_private
*dev_priv)
static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
bool rpm_resume)
{
- struct drm_device *dev = &dev_priv->drm;
int err;
int ret;
@@ -2289,7 +2288,7 @@ static int vlv_resume_prepare(struct drm_i915_private
*dev_priv,
vlv_check_no_gt_access(dev_priv);
if (rpm_resume)
- intel_init_clock_gating(dev);
+ intel_init_clock_gating(dev_priv);
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c142fd07a7a3..248893731ba0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -525,7 +525,7 @@ struct drm_i915_display_funcs {
const struct drm_display_mode
*adjusted_mode);
void (*audio_codec_disable)(struct intel_encoder *encoder);
void (*fdi_link_train)(struct drm_crtc *crtc);
- void (*init_clock_gating)(struct drm_device *dev);
+ void (*init_clock_gating)(struct drm_i915_private *dev_priv);
int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
struct drm_framebuffer *fb,
struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index df58a155a6e4..ddda01361e3b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -16314,7 +16314,7 @@ void intel_modeset_init_hw(struct drm_device *dev)
dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
- intel_init_clock_gating(dev);
+ intel_init_clock_gating(dev_priv);
}
/*
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 13c9c78c4b09..245911b19495 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1712,7 +1712,7 @@ bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv, enum dpio_phy phy,
/* intel_pm.c */
-void intel_init_clock_gating(struct drm_device *dev);
+void intel_init_clock_gating(struct drm_i915_private *dev_priv);
void intel_suspend_hw(struct drm_device *dev);
int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
void intel_update_watermarks(struct intel_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e840feba7eca..756ba81116a3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -55,10 +55,8 @@
#define INTEL_RC6p_ENABLE (1<<1)
#define INTEL_RC6pp_ENABLE (1<<2)
-static void gen9_init_clock_gating(struct drm_device *dev)
+static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
-
/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
I915_WRITE(CHICKEN_PAR1_1,
I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
@@ -81,11 +79,9 @@ static void gen9_init_clock_gating(struct drm_device *dev)
ILK_DPFC_DISABLE_DUMMY0);
}
-static void bxt_init_clock_gating(struct drm_device *dev)
+static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
- gen9_init_clock_gating(dev);
+ gen9_init_clock_gating(dev_priv);
/* WaDisableSDEUnitClockGating:bxt */
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
@@ -6873,10 +6869,8 @@ void intel_autoenable_gt_powersave(struct
drm_i915_private *dev_priv)
}
}
-static void ibx_init_clock_gating(struct drm_device *dev)
+static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
/*
* On Ibex Peak and Cougar Point, we need to disable clock
* gating for the panel power sequencer or it will fail to
@@ -6885,9 +6879,8 @@ static void ibx_init_clock_gating(struct drm_device *dev)
I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
}
-static void g4x_disable_trickle_feed(struct drm_device *dev)
+static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
{
-
[Intel-gfx] [PATCH 22/26] drm/i915: Pass dev_priv to single_enabled_crtc()
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 22 +-
1 file changed, 9 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 70c2aa6b9ac0..e840feba7eca 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -617,11 +617,11 @@ static unsigned long intel_calculate_wm(unsigned long
clock_in_khz,
return wm_size;
}
-static struct intel_crtc *single_enabled_crtc(struct drm_device *dev)
+static struct intel_crtc *single_enabled_crtc(struct drm_i915_private
*dev_priv)
{
struct intel_crtc *crtc, *enabled = NULL;
- for_each_intel_crtc(dev, crtc) {
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
if (intel_crtc_active(crtc)) {
if (enabled)
return NULL;
@@ -634,8 +634,7 @@ static struct intel_crtc *single_enabled_crtc(struct
drm_device *dev)
static void pineview_update_wm(struct intel_crtc *unused_crtc)
{
- struct drm_device *dev = unused_crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
struct intel_crtc *crtc;
const struct cxsr_latency *latency;
u32 reg;
@@ -651,7 +650,7 @@ static void pineview_update_wm(struct intel_crtc
*unused_crtc)
return;
}
- crtc = single_enabled_crtc(dev);
+ crtc = single_enabled_crtc(dev_priv);
if (crtc) {
const struct drm_display_mode *adjusted_mode =
&crtc->config->base.adjusted_mode;
@@ -1442,15 +1441,14 @@ static void g4x_update_wm(struct intel_crtc *crtc)
static void i965_update_wm(struct intel_crtc *unused_crtc)
{
- struct drm_device *dev = unused_crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
struct intel_crtc *crtc;
int srwm = 1;
int cursor_sr = 16;
bool cxsr_enabled;
/* Calc sr entries for one plane configs */
- crtc = single_enabled_crtc(dev);
+ crtc = single_enabled_crtc(dev_priv);
if (crtc) {
/* self-refresh has much higher latency */
static const int sr_latency_ns = 12000;
@@ -1519,8 +1517,7 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
static void i9xx_update_wm(struct intel_crtc *unused_crtc)
{
- struct drm_device *dev = unused_crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
const struct intel_watermark_params *wm_info;
uint32_t fwater_lo;
uint32_t fwater_hi;
@@ -1667,14 +1664,13 @@ static void i9xx_update_wm(struct intel_crtc
*unused_crtc)
static void i845_update_wm(struct intel_crtc *unused_crtc)
{
- struct drm_device *dev = unused_crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
struct intel_crtc *crtc;
const struct drm_display_mode *adjusted_mode;
uint32_t fwater_lo;
int planea_wm;
- crtc = single_enabled_crtc(dev);
+ crtc = single_enabled_crtc(dev_priv);
if (crtc == NULL)
return;
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 25/26] drm/i915: Pass dev_priv to ilk_setup_wm_latency() & co.
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 38 +++---
1 file changed, 15 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e8e0f54b829d..477dee881df8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -934,10 +934,8 @@ static unsigned int vlv_wm_method2(unsigned int pixel_rate,
return ret;
}
-static void vlv_setup_wm_latency(struct drm_device *dev)
+static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
/* all latencies in usec */
dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
@@ -2086,10 +2084,9 @@ hsw_compute_linetime_wm(const struct intel_crtc_state
*cstate)
PIPE_WM_LINETIME_TIME(linetime);
}
-static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
+static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
+ uint16_t wm[8])
{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
if (IS_GEN9(dev_priv)) {
uint32_t val;
int ret, i;
@@ -2175,14 +2172,14 @@ static void intel_read_wm_latency(struct drm_device
*dev, uint16_t wm[8])
wm[2] = (sskpd >> 12) & 0xFF;
wm[3] = (sskpd >> 20) & 0x1FF;
wm[4] = (sskpd >> 32) & 0x1FF;
- } else if (INTEL_INFO(dev)->gen >= 6) {
+ } else if (INTEL_GEN(dev_priv) >= 6) {
uint32_t sskpd = I915_READ(MCH_SSKPD);
wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
- } else if (INTEL_INFO(dev)->gen >= 5) {
+ } else if (INTEL_GEN(dev_priv) >= 5) {
uint32_t mltr = I915_READ(MLTR_ILK);
/* ILK primary LP0 latency is 700 ns */
@@ -2270,9 +2267,8 @@ static bool ilk_increase_wm_latency(struct
drm_i915_private *dev_priv,
return true;
}
-static void snb_wm_latency_quirk(struct drm_device *dev)
+static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
bool changed;
/*
@@ -2292,11 +2288,9 @@ static void snb_wm_latency_quirk(struct drm_device *dev)
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
}
-static void ilk_setup_wm_latency(struct drm_device *dev)
+static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
- intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
+ intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
sizeof(dev_priv->wm.pri_latency));
@@ -2311,14 +2305,12 @@ static void ilk_setup_wm_latency(struct drm_device *dev)
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
if (IS_GEN6(dev_priv))
- snb_wm_latency_quirk(dev);
+ snb_wm_latency_quirk(dev_priv);
}
-static void skl_setup_wm_latency(struct drm_device *dev)
+static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
- intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
+ intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
intel_print_wm_latency(dev_priv, "Gen9 Plane",
dev_priv->wm.skl_latency);
}
@@ -7715,11 +7707,11 @@ void intel_init_pm(struct drm_device *dev)
/* For FIFO watermark updates */
if (INTEL_INFO(dev)->gen >= 9) {
- skl_setup_wm_latency(dev);
+ skl_setup_wm_latency(dev_priv);
dev_priv->display.update_wm = skl_update_wm;
dev_priv->display.compute_global_watermarks = skl_compute_wm;
} else if (HAS_PCH_SPLIT(dev_priv)) {
- ilk_setup_wm_latency(dev);
+ ilk_setup_wm_latency(dev_priv);
if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
dev_priv->wm.spr_latency[1] &&
dev_priv->wm.cur_latency[1]) ||
@@ -7737,10 +7729,10 @@ void intel_init_pm(struct drm_device *dev)
"Disable CxSR\n");
}
} else if (IS_CHERRYVIEW(dev_priv)) {
- vlv_setup_wm_latency(dev);
+ vlv_setup_wm_latency(dev_priv);
dev_priv->display.update_wm = vlv_update_wm;
} else if (IS_VALLEYVIEW(dev_priv)) {
- vlv_setup_wm_latency(dev);
+ vlv_setup_wm_latency(dev_priv);
[Intel-gfx] [PATCH 09/26] drm/i915: Pass dev_priv to g4x wm functions
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b2f085b04bfc..45aefb662408 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -711,7 +711,7 @@ static void pineview_update_wm(struct intel_crtc
*unused_crtc)
}
}
-static bool g4x_compute_wm0(struct drm_device *dev,
+static bool g4x_compute_wm0(struct drm_i915_private *dev_priv,
int plane,
const struct intel_watermark_params *display,
int display_latency_ns,
@@ -727,7 +727,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
int line_time_us, line_count;
int entries, tlb_miss;
- crtc = intel_get_crtc_for_plane(dev, plane);
+ crtc = intel_get_crtc_for_plane(&dev_priv->drm, plane);
if (!intel_crtc_active(crtc)) {
*cursor_wm = cursor->guard_size;
*plane_wm = display->guard_size;
@@ -773,7 +773,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
* can be programmed into the associated watermark register, that watermark
* must be disabled.
*/
-static bool g4x_check_srwm(struct drm_device *dev,
+static bool g4x_check_srwm(struct drm_i915_private *dev_priv,
int display_wm, int cursor_wm,
const struct intel_watermark_params *display,
const struct intel_watermark_params *cursor)
@@ -801,7 +801,7 @@ static bool g4x_check_srwm(struct drm_device *dev,
return true;
}
-static bool g4x_compute_srwm(struct drm_device *dev,
+static bool g4x_compute_srwm(struct drm_i915_private *dev_priv,
int plane,
int latency_ns,
const struct intel_watermark_params *display,
@@ -822,7 +822,7 @@ static bool g4x_compute_srwm(struct drm_device *dev,
return false;
}
- crtc = intel_get_crtc_for_plane(dev, plane);
+ crtc = intel_get_crtc_for_plane(&dev_priv->drm, plane);
adjusted_mode = &crtc->config->base.adjusted_mode;
fb = crtc->base.primary->state->fb;
clock = adjusted_mode->crtc_clock;
@@ -846,7 +846,7 @@ static bool g4x_compute_srwm(struct drm_device *dev,
entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
*cursor_wm = entries + cursor->guard_size;
- return g4x_check_srwm(dev,
+ return g4x_check_srwm(dev_priv,
*display_wm, *cursor_wm,
display, cursor);
}
@@ -1400,20 +1400,20 @@ static void g4x_update_wm(struct intel_crtc *crtc)
unsigned int enabled = 0;
bool cxsr_enabled;
- if (g4x_compute_wm0(dev, PIPE_A,
+ if (g4x_compute_wm0(dev_priv, PIPE_A,
&g4x_wm_info, pessimal_latency_ns,
&g4x_cursor_wm_info, pessimal_latency_ns,
&planea_wm, &cursora_wm))
enabled |= 1 << PIPE_A;
- if (g4x_compute_wm0(dev, PIPE_B,
+ if (g4x_compute_wm0(dev_priv, PIPE_B,
&g4x_wm_info, pessimal_latency_ns,
&g4x_cursor_wm_info, pessimal_latency_ns,
&planeb_wm, &cursorb_wm))
enabled |= 1 << PIPE_B;
if (single_plane_enabled(enabled) &&
- g4x_compute_srwm(dev, ffs(enabled) - 1,
+ g4x_compute_srwm(dev_priv, ffs(enabled) - 1,
sr_latency_ns,
&g4x_wm_info,
&g4x_cursor_wm_info,
--
2.7.4
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[Intel-gfx] [PATCH 08/26] drm/i915: Pass dev_priv to vlv force pll functions
From: Ville Syrjälä
Unify our approach to things by passing around dev_priv instead of dev.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 14 +++---
drivers/gpu/drm/i915/intel_dp.c | 7 +++
drivers/gpu/drm/i915/intel_drv.h | 4 ++--
3 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2de5371e4e35..b9a9139d7359 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8103,10 +8103,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
* in cases where we need the PLL enabled even when @pipe is not going to
* be enabled.
*/
-int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
+int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
const struct dpll *dpll)
{
- struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev, pipe);
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(&dev_priv->drm, pipe);
struct intel_crtc_state *pipe_config;
pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
@@ -8117,7 +8117,7 @@ int vlv_force_pll_on(struct drm_device *dev, enum pipe
pipe,
pipe_config->pixel_multiplier = 1;
pipe_config->dpll = *dpll;
- if (IS_CHERRYVIEW(to_i915(dev))) {
+ if (IS_CHERRYVIEW(dev_priv)) {
chv_compute_dpll(crtc, pipe_config);
chv_prepare_pll(crtc, pipe_config);
chv_enable_pll(crtc, pipe_config);
@@ -8140,12 +8140,12 @@ int vlv_force_pll_on(struct drm_device *dev, enum pipe
pipe,
* Disable the PLL for @pipe. To be used in cases where we need
* the PLL enabled even when @pipe is not going to be enabled.
*/
-void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
+void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
{
- if (IS_CHERRYVIEW(to_i915(dev)))
- chv_disable_pll(to_i915(dev), pipe);
+ if (IS_CHERRYVIEW(dev_priv))
+ chv_disable_pll(dev_priv, pipe);
else
- vlv_disable_pll(to_i915(dev), pipe);
+ vlv_disable_pll(dev_priv, pipe);
}
static void i9xx_compute_dpll(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9c1921a2e239..9df331b3305b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -395,8 +395,7 @@ static void
vlv_power_sequencer_kick(struct intel_dp *intel_dp)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct drm_device *dev = intel_dig_port->base.base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv =
to_i915(intel_dig_port->base.base.dev);
enum pipe pipe = intel_dp->pps_pipe;
bool pll_enabled, release_cl_override = false;
enum dpio_phy phy = DPIO_PHY(pipe);
@@ -434,7 +433,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
release_cl_override = IS_CHERRYVIEW(dev_priv) &&
!chv_phy_powergate_ch(dev_priv, phy, ch, true);
- if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev_priv) ?
+ if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
&chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
DRM_ERROR("Failed to force on pll for pipe %c!\n",
pipe_name(pipe));
@@ -458,7 +457,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
POSTING_READ(intel_dp->output_reg);
if (!pll_enabled) {
- vlv_force_pll_off(dev, pipe);
+ vlv_force_pll_off(dev_priv, pipe);
if (release_cl_override)
chv_phy_powergate_ch(dev_priv, phy, ch, false);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d05e445e087d..af28fbce49cb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1310,9 +1310,9 @@ unsigned int intel_tile_height(const struct
drm_i915_private *dev_priv,
void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
enum pipe pipe);
-int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
+int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
const struct dpll *dpll);
-void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
+void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
int lpt_get_iclkip(struct drm_i915_private *dev_priv);
/* modesetting asserts */
--
2.7.4
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Re: [Intel-gfx] [PATCH 00/26] drm/i915: A game of OCD dominoes
On Mon, Oct 31, 2016 at 10:36:59PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> I pretty much just wanted to store struct intel_crtc * instead
> of struct drm_crtc * in pipe_to_crtc_mapping[] & co. but to
> achieve it cleanly I ended up chasing quite few different things
> that were accepting the wrong kind of type. And once I had
> sorted out those mappign arrays, I had ended up in the old
> watermark code which kept me busy for another good while.
> Eventually I was able to claw my way back to sanity and I
> decided to stop.
>
> I'm going to blame Daniel for getting me on this track by
> suggesting that I should pass dev_priv to the plane
> constructos. That was enough of a trigger to get me started.
>
> Entire series available here:
> git://github.com/vsyrjala/linux.git dev_priv_intel_crtc_cleanup
>
> Ville Syrjälä (26):
> drm/i915: Pass dev_priv to plane constructors
> drm/i915: Pass dev_priv to skl_init_scalers()
> drm/i915: Pass intel_crtc to intel_crtc_active()
> drm/i915: Pass intel_crtc to update_wm functions
> drm/i915: Use struct intel_crtc in legacy platform wm code
> drm/i915: Store struct intel_crtc * in {pipe,plane}_to_crtc_mapping[]
> drm/i915: Pass dev_priv to intel_wait_for_vblank()
> drm/i915: Pass dev_priv to vlv force pll functions
> drm/i915: Pass dev_priv to g4x wm functions
> drm/i915: Pass dev_priv to intel_get_crtc_for_pipe()
> drm/i915: Always use intel_get_crtc_for_pipe()
> drm/i915: Pass dev_priv to intel_crtc_init()
> drm/i915: Pass dev_priv to cdclk update funcs
> drm/i915: Pass dev_priv to .get_display_clock_speed()
> drm/i915: Pass dev_priv to IS_MOBILE()
> drm/i915: Pass dev_priv to IS_PINEVIEW()
> drm/i915: Pass dev_priv to i915_pineview_get_mem_freq() and
> i915_ironlake_get_mem_freq()
> drm/i915: Pass dev_priv to .get_fifo_size()
> drm/i915: Pass dev_priv to HAS_FW_BLC
> drm/i915: Pass dev_priv to IS_BROADWATER/IS_CRESTLINE
> drm/i915: Pass dev_priv to rest of IS_FOO() macros for the old
> platforms
> drm/i915: Pass dev_priv to single_enabled_crtc()
> drm/i915: Pass dev_priv to init_clock_gating
> drm/i915: Pass dev_priv to intel_suspend_hw()
> drm/i915: Pass dev_priv to ilk_setup_wm_latency() & co.
> drm/i915: Pass dev_priv to intel_init_pm()
All looked reasonable and beguiling in their simplicty. Nice trimming.
Reviewed-by: Chris Wilson
Are we still trimming the odd byte from object size?
-Chris
--
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Re: [Intel-gfx] [PATCH 2/6] drm/i915: Avoid accessing request->timeline outside of its lifetime
On Mon, Oct 31, 2016 at 05:35:50PM +, Tvrtko Ursulin wrote:
>
> On 31/10/2016 10:26, Chris Wilson wrote:
> >Whilst waiting on a request, we may do so without holding any locks or
> >any guards beyond a reference to the request. In order to avoid taking
> >locks within request deallocation, we drop references to its timeline
> >(via the context and ppgtt) upon retirement. We should avoid chasing
>
> Couldn't find that there is a reference taken (or dropped) on the
> timeline when stored in a request. It looks like a borrowed pointer
> to me?
The timeline is owned by the address space which is owned by either the
context or the device. The request holds a reference on the context (and
so indirectly onto the timeline, except for the device's which outlives
the request) up until we retire the request. (Retiring holds
struct_mutex so is earlier than freeing.)
> >+static inline u32 intel_engine_last_submit(struct intel_engine_cs *engine)
> >+{
> >+return READ_ONCE(engine->timeline->last_submitted_seqno);
> >+}
> >+
>
> Don't like that READ_ONCE gets sprinkled all over the place via call
> sites. It should be extremely well defined and controlled from where
> it is used. Otherwise it suggests READ_ONCE is not really
> appropriate.
It actually is appropriate. last_submitted_seqno is under the timeline
spinlock, none of the callers take the appropriate guard. This is
trying to document that these callers don't call about fully
synchronising the last_submitted_seqno with the request list or last
request pointer. And we don't care to go full seqlock, since we really
are only peeking.
-Chris
--
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Re: [Intel-gfx] [PATCH] i915/GuC: Make GuC loads default
I agree that the parameter controls could use a clean-up, which could include eventual removal of the enable_guc_loading parameter. But for now loading parameter should be auto by default. Might be a good idea to temporarily set the has_guc parameter to 0 for BXT and KBL since those firmwares have not yet been made available (I don't see them on 01.org). In either case... Reviewed-by: Jeff McGee On Mon, Oct 31, 2016 at 10:06:27AM -0700, Rodrigo Vivi wrote: > Could someone please ack this? We need this before getting HuC. > > GuC submission has regressions so the submission is not getting enabled. > But we need to have GuC loaded to be able to use HuC. > > Thanks, > Rodrigo. > > On Thu, Oct 6, 2016 at 11:08 AM, Rodrigo Vivi wrote: > > I also asked that same question many times. Maybe they can be unified > > later when we enable submission by default, but right now I believe > > this is the way to go, so > > > > Reviewed-by: Rodrigo Vivi > > > > > > On Thu, Oct 6, 2016 at 11:03 AM, Srivatsa, Anusha > > wrote: > >> > >> > >>>-Original Message- > >>>From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] > >>>Sent: Wednesday, October 5, 2016 11:57 PM > >>>To: Srivatsa, Anusha > >>>Cc: intel-gfx@lists.freedesktop.org > >>>Subject: Re: [Intel-gfx] [PATCH] i915/GuC: Make GuC loads default > >>> > >>>On Wed, Oct 05, 2016 at 04:20:04PM -0700, Anusha Srivatsa wrote: > Proper functioning of HuC requires GuC to be loaded. Make GuC loads > default so that HuC works seemlessly. > Also, note that GuC submission is not made default and still needs to > be given as a kernel parameter. > Once the issues around GuC submission is resolved it is intended to > make it default as well. > >>> > >>>Why is this even a separate parameter? -Chris > >> > >> It is a separate parameter because HuC requires GuC to be loaded. It is ok > >> if command submission is not happening through GuC but GuC "has to" be > >> loaded for HuC to function. Guc_submission parameter enables the command > >> submission through GUC. But, guc_loading parameter ensures not only that > >> the GuC is loaded but also that HuC can now function. > >> > >> Anusha > >>>-- > >>>Chris Wilson, Intel Open Source Technology Centre > >> ___ > >> Intel-gfx mailing list > >> Intel-gfx@lists.freedesktop.org > >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > > > > -- > > Rodrigo Vivi > > Blog: http://blog.vivi.eng.br > > > > -- > Rodrigo Vivi > Blog: http://blog.vivi.eng.br > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/6] drm/i915: Use the full hammer when shutting down the rcu tasks
On Mon, Oct 31, 2016 at 05:15:45PM +, Tvrtko Ursulin wrote:
>
> On 31/10/2016 10:26, Chris Wilson wrote:
> >To flush all call_rcu() tasks (here from i915_gem_free_object()) we need
> >to call rcu_barrier() (not synchronize_rcu()). If we don't then we may
> >still have objects being freed as we continue to teardown the driver -
> >in particular, the recently released rings may race with the memory
> >manager shutdown resulting in sporadic:
> >
> >[ 142.217186] WARNING: CPU: 7 PID: 6185 at drivers/gpu/drm/drm_mm.c:932
> >drm_mm_takedown+0x2e/0x40
> >[ 142.217187] Memory manager not clean during takedown.
> >[ 142.217187] Modules linked in: i915(-) x86_pkg_temp_thermal
> >intel_powerclamp coretemp crct10dif_pclmul crc32_pclmul ghash_clmulni_intel
> >lpc_ich snd_hda_codec_realtek snd_hda_codec_generic mei_me mei
> >snd_hda_codec_hdmi snd_hda_codec snd_hwdep snd_hda_core snd_pcm e1000e ptp
> >pps_core [last unloaded: snd_hda_intel]
> >[ 142.217199] CPU: 7 PID: 6185 Comm: rmmod Not tainted
> >4.9.0-rc2-CI-Trybot_242+ #1
> >[ 142.217199] Hardware name: LENOVO 10AGS00601/SHARKBAY, BIOS FBKT34AUS
> >04/24/2013
> >[ 142.217200] c90002ecfce0 8142dd65 c90002ecfd30
> >
> >[ 142.217202] c90002ecfd20 8107e4e6 03a40778c2a8
> >880401355c48
> >[ 142.217204] 88040778c2a8 a040f3c0 a040f4a0
> >5621fbf8b1f0
> >[ 142.217206] Call Trace:
> >[ 142.217209] [] dump_stack+0x67/0x92
> >[ 142.217211] [] __warn+0xc6/0xe0
> >[ 142.217213] [] warn_slowpath_fmt+0x4a/0x50
> >[ 142.217214] [] drm_mm_takedown+0x2e/0x40
> >[ 142.217236] [] i915_gem_cleanup_stolen+0x1a/0x20 [i915]
> >[ 142.217246] [] i915_ggtt_cleanup_hw+0x31/0xb0 [i915]
> >[ 142.217253] [] i915_driver_cleanup_hw+0x31/0x40 [i915]
> >[ 142.217260] [] i915_driver_unload+0x141/0x1a0 [i915]
> >[ 142.217268] [] i915_pci_remove+0x14/0x20 [i915]
> >[ 142.217269] [] pci_device_remove+0x34/0xb0
> >[ 142.217271] [] __device_release_driver+0x9c/0x150
> >[ 142.217272] [] driver_detach+0xb6/0xc0
> >[ 142.217273] [] bus_remove_driver+0x53/0xd0
> >[ 142.217274] [] driver_unregister+0x27/0x50
> >[ 142.217276] [] pci_unregister_driver+0x25/0x70
> >[ 142.217287] [] i915_exit+0x1a/0x71 [i915]
> >[ 142.217289] [] SyS_delete_module+0x193/0x1e0
> >[ 142.217291] [] entry_SYSCALL_64_fastpath+0x1c/0xb1
> >[ 142.217292] ---[ end trace 6fd164859c154772 ]---
> >[ 142.217505] [drm:show_leaks] *ERROR* node [6b6b6b6b6b6b6b6b +
> >6b6b6b6b6b6b6b6b]: inserted at
> >[] save_stack.isra.1+0x53/0xa0
> >[]
> > drm_mm_insert_node_in_range_generic+0x2ad/0x360
> >[]
> > i915_gem_stolen_insert_node_in_range+0x93/0xe0 [i915]
> >[] i915_gem_object_create_stolen+0x75/0xb0
> > [i915]
> >[] intel_engine_create_ring+0x9a/0x140
> > [i915]
> >[] intel_init_ring_buffer+0xf1/0x440 [i915]
> >[]
> > intel_init_render_ring_buffer+0xab/0x1b0 [i915]
> >[] intel_engines_init+0xc8/0x210 [i915]
> >[] i915_gem_init+0xac/0xf0 [i915]
> >[] i915_driver_load+0x9c4/0x1430 [i915]
> >[] i915_pci_probe+0x28/0x40 [i915]
> >[] pci_device_probe+0x85/0xf0
> >[] driver_probe_device+0x21f/0x430
> >[] __driver_attach+0xde/0xe0
> >
> >In particular note that the node was being poisoned as we inspected the
> >list, a clear indication that the object is being freed as we make the
> >assertion.
> >
> >Fixes: fbbd37b36fa5 ("drm/i915: Move object release to a freelist + worker")
> >Signed-off-by: Chris Wilson
> >Cc: Joonas Lahtinen
> >---
> > drivers/gpu/drm/i915/i915_drv.c | 6 --
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_drv.c
> >b/drivers/gpu/drm/i915/i915_drv.c
> >index 839ce2ae38fa..ed01421e3be7 100644
> >--- a/drivers/gpu/drm/i915/i915_drv.c
> >+++ b/drivers/gpu/drm/i915/i915_drv.c
> >@@ -544,8 +544,10 @@ static void i915_gem_fini(struct drm_i915_private
> >*dev_priv)
> > i915_gem_context_fini(&dev_priv->drm);
> > mutex_unlock(&dev_priv->drm.struct_mutex);
> >
> >-synchronize_rcu();
> >-flush_work(&dev_priv->mm.free_work);
> >+do {
> >+rcu_barrier();
> >+flush_work(&dev_priv->mm.free_work);
> >+} while (!llist_empty(&dev_priv->mm.free_list));
> >
> > WARN_ON(!list_empty(&dev_priv->context_list));
> > }
> >
>
> Not sure that the loop is required - after the rcu_barrier all the
> queued up additions have been added to the list and workers queued.
> So flush_work afterwards handles those and we are done, no?
We don't need the loop, it was an overreaction. A subsequent WARN would
be good enough to detect futher issues. That WARN would be better in
front of freeing the object kmem_cache.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_
[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: A game of OCD dominoes
== Series Details ==
Series: drm/i915: A game of OCD dominoes
URL : https://patchwork.freedesktop.org/series/14634/
State : warning
== Summary ==
Series 14634v1 drm/i915: A game of OCD dominoes
https://patchwork.freedesktop.org/api/1.0/series/14634/revisions/1/mbox/
Test drv_module_reload_basic:
pass -> SKIP (fi-ivb-3520m)
dmesg-warn -> PASS (fi-ilk-650)
Test gem_exec_suspend:
Subgroup basic-s3:
dmesg-warn -> PASS (fi-ilk-650)
Test kms_cursor_legacy:
Subgroup basic-flip-after-cursor-varying-size:
pass -> DMESG-WARN (fi-ilk-650)
Test kms_force_connector_basic:
Subgroup force-connector-state:
pass -> DMESG-WARN (fi-snb-2520m)
Subgroup force-edid:
dmesg-warn -> PASS (fi-snb-2520m)
Test kms_pipe_crc_basic:
Subgroup bad-nb-words-3:
dmesg-warn -> PASS (fi-ilk-650)
Subgroup bad-source:
dmesg-warn -> PASS (fi-ilk-650)
Subgroup hang-read-crc-pipe-b:
dmesg-warn -> PASS (fi-ilk-650)
Subgroup nonblocking-crc-pipe-a-frame-sequence:
pass -> DMESG-WARN (fi-ilk-650)
Subgroup nonblocking-crc-pipe-b:
pass -> DMESG-WARN (fi-ilk-650)
Subgroup read-crc-pipe-b:
pass -> DMESG-WARN (fi-ilk-650)
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS (fi-ilk-650)
fi-bdw-5557u total:241 pass:225 dwarn:1 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:241 pass:201 dwarn:0 dfail:0 fail:0 skip:40
fi-bxt-t5700 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-j1900 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28
fi-byt-n2820 total:241 pass:209 dwarn:0 dfail:0 fail:0 skip:32
fi-hsw-4770 total:241 pass:221 dwarn:0 dfail:0 fail:0 skip:20
fi-hsw-4770r total:241 pass:220 dwarn:0 dfail:0 fail:0 skip:21
fi-ilk-650 total:241 pass:183 dwarn:4 dfail:0 fail:0 skip:54
fi-ivb-3520m total:241 pass:217 dwarn:0 dfail:0 fail:0 skip:24
fi-ivb-3770 total:241 pass:218 dwarn:0 dfail:0 fail:0 skip:23
fi-kbl-7200u total:241 pass:219 dwarn:0 dfail:0 fail:0 skip:22
fi-skl-6260u total:241 pass:227 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hqtotal:241 pass:220 dwarn:0 dfail:0 fail:0 skip:21
fi-skl-6700k total:241 pass:219 dwarn:1 dfail:0 fail:0 skip:21
fi-skl-6770hqtotal:241 pass:227 dwarn:0 dfail:0 fail:0 skip:14
fi-snb-2520m total:241 pass:207 dwarn:1 dfail:0 fail:0 skip:33
fi-snb-2600 total:241 pass:207 dwarn:0 dfail:0 fail:0 skip:34
6a1197bcb5cc18a56ad4ae8e6d706a212bc3db7d drm-intel-nightly:
2016y-10m-31d-14h-58m-16s UTC integration manifest
dbc57d2 drm/i915: Pass dev_priv to intel_init_pm()
d04110e drm/i915: Pass dev_priv to ilk_setup_wm_latency() & co.
5eaa68f drm/i915: Pass dev_priv to intel_suspend_hw()
5a175ed drm/i915: Pass dev_priv to init_clock_gating
6c0abe8 drm/i915: Pass dev_priv to single_enabled_crtc()
26b36df drm/i915: Pass dev_priv to rest of IS_FOO() macros for the old platforms
0ad6d6f drm/i915: Pass dev_priv to IS_BROADWATER/IS_CRESTLINE
668c4b7 drm/i915: Pass dev_priv to HAS_FW_BLC
57938fc drm/i915: Pass dev_priv to .get_fifo_size()
7986e23 drm/i915: Pass dev_priv to i915_pineview_get_mem_freq() and
i915_ironlake_get_mem_freq()
e8ab27f drm/i915: Pass dev_priv to IS_PINEVIEW()
24a984a drm/i915: Pass dev_priv to IS_MOBILE()
7bd297f drm/i915: Pass dev_priv to .get_display_clock_speed()
1e92456 drm/i915: Pass dev_priv to cdclk update funcs
a255a740 drm/i915: Pass dev_priv to intel_crtc_init()
1eaf7f4 drm/i915: Always use intel_get_crtc_for_pipe()
5092a6d drm/i915: Pass dev_priv to intel_get_crtc_for_pipe()
79be1d8 drm/i915: Pass dev_priv to g4x wm functions
6a842c7 drm/i915: Pass dev_priv to vlv force pll functions
4880d18 drm/i915: Pass dev_priv to intel_wait_for_vblank()
2b91deb drm/i915: Store struct intel_crtc * in {pipe, plane}_to_crtc_mapping[]
11a09c3 drm/i915: Use struct intel_crtc in legacy platform wm code
e2b8725 drm/i915: Pass intel_crtc to update_wm functions
ac31287 drm/i915: Pass intel_crtc to intel_crtc_active()
23e10d1 drm/i915: Pass dev_priv to skl_init_scalers()
16f12e9 drm/i915: Pass dev_priv to plane constructors
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2866/
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[Intel-gfx] [PATCH v3 1/4] drm: Add a new connector property for link status
A new default connector property is added for keeping
track of whether the link is good (link training passed) or
link is bad (link training failed). If the link status property
is not good, then userspace should fire off a new modeset at the current
mode even if there have not been any changes in the mode list
or connector status.
Also add link status connector member corersponding to the
decoded value of link status property.
v3:
* Drop "link training" from description since this is
not specific to DP (Jani Nikula)
* Add link status member to store property value locally
(Ville Syrjala)
v2:
* Make this a default connector property (Daniel Vetter)
Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Daniel Vetter
Cc: Ville Syrjala
Cc: Chris Wilson
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/drm_connector.c | 17 +
include/drm/drm_connector.h | 7 ++-
include/drm/drm_crtc.h | 5 +
include/uapi/drm/drm_mode.h | 4
4 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 2db7fb5..d4e852f 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -243,6 +243,10 @@ int drm_connector_init(struct drm_device *dev,
drm_object_attach_property(&connector->base,
config->dpms_property, 0);
+ drm_object_attach_property(&connector->base,
+ config->link_status_property,
+ 0);
+
if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
drm_object_attach_property(&connector->base,
config->prop_crtc_id, 0);
}
@@ -506,6 +510,12 @@ const char *drm_get_subpixel_order_name(enum
subpixel_order order)
};
DRM_ENUM_NAME_FN(drm_get_dpms_name, drm_dpms_enum_list)
+static const struct drm_prop_enum_list drm_link_status_enum_list[] = {
+ { DRM_MODE_LINK_STATUS_GOOD, "Good" },
+ { DRM_MODE_LINK_STATUS_BAD, "Bad" },
+};
+DRM_ENUM_NAME_FN(drm_get_link_status_name, drm_link_status_enum_list)
+
/**
* drm_display_info_set_bus_formats - set the supported bus formats
* @info: display info to store bus formats in
@@ -622,6 +632,13 @@ int drm_connector_create_standard_properties(struct
drm_device *dev)
return -ENOMEM;
dev->mode_config.tile_property = prop;
+ prop = drm_property_create_enum(dev, 0, "link-status",
+ drm_link_status_enum_list,
+ ARRAY_SIZE(drm_link_status_enum_list));
+ if (!prop)
+ return -ENOMEM;
+ dev->mode_config.link_status_property = prop;
+
return 0;
}
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index ac9d7d8..5c335e8 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -682,6 +682,12 @@ struct drm_connector {
uint8_t num_h_tile, num_v_tile;
uint8_t tile_h_loc, tile_v_loc;
uint16_t tile_h_size, tile_v_size;
+
+ /* Connector Link status
+* 0: If the link is Good
+* 1: If the link is Bad
+*/
+ int link_status;
};
#define obj_to_connector(x) container_of(x, struct drm_connector, base)
@@ -754,7 +760,6 @@ int drm_mode_create_tv_properties(struct drm_device *dev,
int drm_mode_create_scaling_mode_property(struct drm_device *dev);
int drm_mode_create_aspect_ratio_property(struct drm_device *dev);
int drm_mode_create_suggested_offset_properties(struct drm_device *dev);
-
int drm_mode_connector_set_path_property(struct drm_connector *connector,
const char *path);
int drm_mode_connector_set_tile_property(struct drm_connector *connector);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index fa1aa21..737f4d3 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1151,6 +1151,11 @@ struct drm_mode_config {
*/
struct drm_property *tile_property;
/**
+* @link_status_property: Default connector property for link status
+* of a connector
+*/
+ struct drm_property *link_status_property;
+ /**
* @plane_type_property: Default plane property to differentiate
* CURSOR, PRIMARY and OVERLAY legacy uses of planes.
*/
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 084b50a..f1b0afd 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -121,6 +121,10 @@
#define DRM_MODE_DIRTY_ON 1
#define DRM_MODE_DIRTY_ANNOTATE 2
+/* Link Status options */
+#define DRM_MODE_LINK_STATUS_GOOD 0
+#define DRM_MODE_LINK_STATUS_BAD 1
+
struct drm_mode_modeinfo {
__u32 clock;
__u16 hdisplay;
--
1.9.1
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Re: [Intel-gfx] [PATCH v8 07/12] drm/i915: Enable i915 perf stream for Haswell OA unit
On 28 October 2016 at 03:14, Robert Bragg wrote:
> Gen graphics hardware can be set up to periodically write snapshots of
> performance counters into a circular buffer via its Observation
> Architecture and this patch exposes that capability to userspace via the
> i915 perf interface.
>
> v2:
>Make sure to initialize ->specific_ctx_id when opening, without
>relying on _pin_notify hook, in case ctx already pinned.
> v3:
>Revert back to pinning ctx upfront when opening stream, removing
>need to hook in to pinning and to update OACONTROL on the fly.
>
> Cc: Chris Wilson
> Signed-off-by: Robert Bragg
> Signed-off-by: Zhenyu Wang
> ---
> drivers/gpu/drm/i915/i915_drv.h | 66 ++-
> drivers/gpu/drm/i915/i915_perf.c | 1036
> +-
> drivers/gpu/drm/i915/i915_reg.h | 338 +
> include/uapi/drm/i915_drm.h | 71 ++-
> 4 files changed, 1482 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f22adc4..dd2b4d3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1767,6 +1767,11 @@ struct intel_wm_config {
> bool sprites_scaled;
> };
>
> +struct i915_oa_format {
> + u32 format;
> + int size;
> +};
> +
> struct i915_oa_reg {
> i915_reg_t addr;
> u32 value;
> @@ -1787,11 +1792,6 @@ struct i915_perf_stream_ops {
> */
> void (*disable)(struct i915_perf_stream *stream);
>
> - /* Return: true if any i915 perf records are ready to read()
> -* for this stream.
> -*/
> - bool (*can_read)(struct i915_perf_stream *stream);
> -
> /* Call poll_wait, passing a wait queue that will be woken
> * once there is something ready to read() for the stream
> */
> @@ -1801,9 +1801,7 @@ struct i915_perf_stream_ops {
>
> /* For handling a blocking read, wait until there is something
> * to ready to read() for the stream. E.g. wait on the same
> -* wait queue that would be passed to poll_wait() until
> -* ->can_read() returns true (if its safe to call ->can_read()
> -* without the i915 perf lock held).
> +* wait queue that would be passed to poll_wait().
> */
> int (*wait_unlocked)(struct i915_perf_stream *stream);
>
> @@ -1843,11 +1841,28 @@ struct i915_perf_stream {
> struct list_head link;
>
> u32 sample_flags;
> + int sample_size;
>
> struct i915_gem_context *ctx;
> bool enabled;
>
> - struct i915_perf_stream_ops *ops;
> + const struct i915_perf_stream_ops *ops;
> +};
> +
> +struct i915_oa_ops {
> + void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
> + int (*enable_metric_set)(struct drm_i915_private *dev_priv);
> + void (*disable_metric_set)(struct drm_i915_private *dev_priv);
> + void (*oa_enable)(struct drm_i915_private *dev_priv);
> + void (*oa_disable)(struct drm_i915_private *dev_priv);
> + void (*update_oacontrol)(struct drm_i915_private *dev_priv);
> + void (*update_hw_ctx_id_locked)(struct drm_i915_private *dev_priv,
> + u32 ctx_id);
> + int (*read)(struct i915_perf_stream *stream,
> + char __user *buf,
> + size_t count,
> + size_t *offset);
> + bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv);
> };
>
> struct drm_i915_private {
> @@ -2154,16 +2169,47 @@ struct drm_i915_private {
>
> struct {
> bool initialized;
> +
> struct mutex lock;
> struct list_head streams;
>
> + spinlock_t hook_lock;
We can get rid of this now, or at least rename it ?
> +
> struct {
> - u32 metrics_set;
> + struct i915_perf_stream *exclusive_stream;
> +
> + u32 specific_ctx_id;
> + struct i915_vma *pinned_rcs_vma;
> +
> + struct hrtimer poll_check_timer;
> + wait_queue_head_t poll_wq;
> + bool pollin;
> +
> + bool periodic;
> + int period_exponent;
> + int timestamp_frequency;
> +
> + int tail_margin;
> +
> + int metrics_set;
>
> const struct i915_oa_reg *mux_regs;
> int mux_regs_len;
> const struct i915_oa_reg *b_counter_regs;
> int b_counter_regs_len;
> +
> + struct {
> + struct i915_vma *vma;
> + u8 *vaddr;
> + int format;
> + int format_size;
> + } oa_buffer;
> +
> +
[Intel-gfx] ✗ Fi.CI.BAT: failure for Handle link training failure during modeset for DDI (rev2)
== Series Details == Series: Handle link training failure during modeset for DDI (rev2) URL : https://patchwork.freedesktop.org/series/14556/ State : failure == Summary == Series 14556v2 Handle link training failure during modeset for DDI https://patchwork.freedesktop.org/api/1.0/series/14556/revisions/2/mbox/ Test drv_module_reload_basic: dmesg-warn -> PASS (fi-ilk-650) dmesg-warn -> PASS (fi-bdw-5557u) pass -> INCOMPLETE (fi-skl-6770hq) dmesg-warn -> INCOMPLETE (fi-skl-6700k) Test kms_cursor_legacy: Subgroup basic-busy-flip-before-cursor-legacy: pass -> DMESG-WARN (fi-ilk-650) Subgroup basic-flip-before-cursor-varying-size: pass -> DMESG-WARN (fi-ilk-650) Test kms_force_connector_basic: Subgroup force-edid: dmesg-warn -> PASS (fi-snb-2520m) Test kms_pipe_crc_basic: Subgroup bad-nb-words-1: pass -> DMESG-WARN (fi-ilk-650) Subgroup bad-nb-words-3: dmesg-warn -> PASS (fi-ilk-650) Subgroup nonblocking-crc-pipe-a-frame-sequence: pass -> DMESG-WARN (fi-ilk-650) Subgroup suspend-read-crc-pipe-a: dmesg-warn -> PASS (fi-ilk-650) fi-bdw-5557u total:241 pass:226 dwarn:0 dfail:0 fail:0 skip:15 fi-bsw-n3050 total:241 pass:201 dwarn:0 dfail:0 fail:0 skip:40 fi-bxt-t5700 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28 fi-byt-j1900 total:241 pass:213 dwarn:0 dfail:0 fail:0 skip:28 fi-byt-n2820 total:241 pass:209 dwarn:0 dfail:0 fail:0 skip:32 fi-hsw-4770 total:241 pass:221 dwarn:0 dfail:0 fail:0 skip:20 fi-hsw-4770r total:241 pass:220 dwarn:0 dfail:0 fail:0 skip:21 fi-ilk-650 total:241 pass:180 dwarn:7 dfail:0 fail:0 skip:54 fi-ivb-3520m total:241 pass:218 dwarn:0 dfail:0 fail:0 skip:23 fi-ivb-3770 total:241 pass:218 dwarn:0 dfail:0 fail:0 skip:23 fi-kbl-7200u total:241 pass:219 dwarn:0 dfail:0 fail:0 skip:22 fi-skl-6260u total:241 pass:227 dwarn:0 dfail:0 fail:0 skip:14 fi-skl-6700hqtotal:241 pass:220 dwarn:0 dfail:0 fail:0 skip:21 fi-skl-6700k total:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-skl-6770hqtotal:6pass:5dwarn:0 dfail:0 fail:0 skip:0 fi-snb-2520m total:241 pass:208 dwarn:0 dfail:0 fail:0 skip:33 fi-snb-2600 total:241 pass:207 dwarn:0 dfail:0 fail:0 skip:34 6a1197bcb5cc18a56ad4ae8e6d706a212bc3db7d drm-intel-nightly: 2016y-10m-31d-14h-58m-16s UTC integration manifest d3c54ba drm/i915: Implement Link Rate fallback on Link training failure 14102d8 drm/i915: Find fallback link rate/lane count 8705bee drm/i915: Set link status property for DP connector cd53886 drm: Add a new connector property for link status == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2867/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/huc: Update the construction of file path for HuC similar to that of GuC
Update the file construction and specifying the required version
similar to that of GuC.Add an extra field for the build number.
Adopted the approach used in
https://patchwork.freedesktop.org/patch/104355/
Cc: Jeff Mcgee
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_huc_loader.c | 25 +++--
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c
b/drivers/gpu/drm/i915/intel_huc_loader.c
index 2f5d9d9..419caae 100644
--- a/drivers/gpu/drm/i915/intel_huc_loader.c
+++ b/drivers/gpu/drm/i915/intel_huc_loader.c
@@ -39,11 +39,24 @@
*
* Note that HuC firmware loading must be done before GuC loading.
*/
+#define SKL_FW_MAJOR 01
+#define SKL_FW_MINOR 07
+#define SKL_BLD_NUM 1398
-#define I915_SKL_HUC_UCODE "i915/skl_huc_ver01_07_1398.bin"
+#define BXT_FW_MAJOR 01
+#define BXT_FW_MINOR 07
+#define BXT_BLD_NUM 1398
+
+#define HUC_FW_PATH(platform, major, minor, bld_num) \
+ "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
+ __stringify(minor) "_" __stringify(bld_num) ".bin"
+
+#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_FW_MAJOR, \
+ SKL_FW_MINOR, SKL_BLD_NUM)
MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
-#define I915_BXT_HUC_UCODE "i915/bxt_huc_ver01_07_1398.bin"
+#define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_FW_MAJOR, \
+ BXT_FW_MINOR, BXT_BLD_NUM)
MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
/**
@@ -151,12 +164,12 @@ void intel_huc_init(struct drm_device *dev)
if (IS_SKYLAKE(dev_priv)) {
fw_path = I915_SKL_HUC_UCODE;
- huc_fw->major_ver_wanted = 1;
- huc_fw->minor_ver_wanted = 7;
+ huc_fw->major_ver_wanted = SKL_FW_MAJOR;
+ huc_fw->minor_ver_wanted = SKL_FW_MINOR;
} else if (IS_BROXTON(dev_priv)) {
fw_path = I915_BXT_HUC_UCODE;
- huc_fw->major_ver_wanted = 1;
- huc_fw->minor_ver_wanted = 7;
+ huc_fw->major_ver_wanted = BXT_FW_MAJOR;
+ huc_fw->minor_ver_wanted = BXT_FW_MINOR;
}
if (fw_path == NULL)
--
2.7.4
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Re: [Intel-gfx] [PATCH 0/2] drm/i915/opregion: proper handling of DIDL and CADL
Your patches fixed the problem in my Asus X450LCP. I'm also looking further to see these patches to land in master. Thanks, On Mon, Oct 31, 2016 at 10:32 AM Jani Nikula wrote: > On Mon, 31 Oct 2016, Jani Nikula wrote: > > On Mon, 31 Oct 2016, Rainer Koenig wrote: > >> Hi Jani, > >> > >> one quick questions: What happened to those CADL patches. I was > >> expecting them to showup in the mainstream kernel.org kernel some day, > >> but even in 4.9rc3 I cant't find them. > > > > Basically [1] and [2] happened, no idea what went wrong, and no time to > > debug. > > Those, and virtually no positive feedback. > > > > > BR, > > Jani. > > > > [1] > http://mid.mail-archive.com/1472151415.3037046.706208097.7301895A@webmail.messagingengine.com > > [2] > http://mid.mail-archive.com/34dfe08b-7646-8ea5-018e-549dc67564f2@skynet.be > > > > > >> > >> Best regards > >> Rainer > >> > >> Am 25.08.2016 um 14:53 schrieb Jani Nikula: > >>> This is the next iteration of [1] and [2]. Please review and/or test, > >>> according to your abilities. > >>> > >>> Thanks, > >>> Jani. > >>> > >>> Cc: Peter Wu > >>> Cc: Rainer Koenig > >>> Cc: Jan-Marek Glogowski > >>> Cc: Maarten Lankhorst > >>> Cc: Marcos Paulo de Souza > >>> Cc: Paolo Stivanin > >>> > >>> [1] > http://mid.mail-archive.com/cover.1467214151.git.jani.nikula@intel.com > >>> [2] > http://mid.mail-archive.com/1471315782-925-1-git-send-email-marcos.souza.org@gmail.com > >>> > >>> Jani Nikula (2): > >>> drm/i915: make i915 the source of acpi device ids for _DOD > >>> drm/i915/opregion: update cadl based on actually active outputs > >>> > >>> drivers/gpu/drm/i915/i915_drv.h | 4 + > >>> drivers/gpu/drm/i915/intel_display.c | 6 ++ > >>> drivers/gpu/drm/i915/intel_drv.h | 3 + > >>> drivers/gpu/drm/i915/intel_opregion.c | 157 > +- > >>> 4 files changed, 74 insertions(+), 96 deletions(-) > >>> > > -- > Jani Nikula, Intel Open Source Technology Center > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [i-g-t PATCH v2] tests: do snd_hda_intel unbind before unload in module reload test
Reviewed-by: Libin Yang
Regards,
Libin
> -Original Message-
> From: Nikula, Jani
> Sent: Monday, October 31, 2016 7:00 PM
> To: Nikula, Jani ; intel-gfx@lists.freedesktop.org
> Cc: Zhang, Keqiao ; Yang, Libin
>
> Subject: [i-g-t PATCH v2] tests: do snd_hda_intel unbind before unload in
> module reload test
>
> Try to make sure the snd_hda_intel module is not in use, and can be
> unloaded.
>
> v2: unbind all cards (Libin)
>
> Cc: Keqiao Zhang
> Cc: Libin Yang
> Signed-off-by: Jani Nikula
>
> ---
>
> Keqiao, Libin, here's the script this patch is against:
>
> https://cgit.freedesktop.org/drm/igt-gpu-
> tools/tree/tests/drv_module_reload_basic
> ---
> tests/drv_module_reload_basic | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/tests/drv_module_reload_basic b/tests/drv_module_reload_basic
> index b8cad88133e9..105852a56b46 100755
> --- a/tests/drv_module_reload_basic
> +++ b/tests/drv_module_reload_basic
> @@ -33,6 +33,11 @@ function reload() {
> pkill alsactl
> snd_hda_intel_unloaded=0
> if mod_loaded snd_hda_intel; then
> + # unbind sound cards
> + for card in $(find /sys/bus/pci/drivers/snd_hda_intel -name
> ":*" -printf "%f\n"); do
> + echo $card >
> /sys/bus/pci/drivers/snd_hda_intel/unbind
> + done
> +
> if rmmod snd_hda_intel; then
> snd_hda_intel_unloaded=1
> else
> --
> 2.1.4
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Re: [Intel-gfx] [i-g-t PATCH v2] tests: do snd_hda_intel unbind before unload in module reload test
On Tue, 01 Nov 2016, "Yang, Libin" wrote:
> Reviewed-by: Libin Yang
Pushed both patches to igt, thanks for the review.
BR,
Jani.
>
> Regards,
> Libin
>
>
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Monday, October 31, 2016 7:00 PM
>> To: Nikula, Jani ; intel-gfx@lists.freedesktop.org
>> Cc: Zhang, Keqiao ; Yang, Libin
>>
>> Subject: [i-g-t PATCH v2] tests: do snd_hda_intel unbind before unload in
>> module reload test
>>
>> Try to make sure the snd_hda_intel module is not in use, and can be
>> unloaded.
>>
>> v2: unbind all cards (Libin)
>>
>> Cc: Keqiao Zhang
>> Cc: Libin Yang
>> Signed-off-by: Jani Nikula
>>
>> ---
>>
>> Keqiao, Libin, here's the script this patch is against:
>>
>> https://cgit.freedesktop.org/drm/igt-gpu-
>> tools/tree/tests/drv_module_reload_basic
>> ---
>> tests/drv_module_reload_basic | 5 +
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/tests/drv_module_reload_basic b/tests/drv_module_reload_basic
>> index b8cad88133e9..105852a56b46 100755
>> --- a/tests/drv_module_reload_basic
>> +++ b/tests/drv_module_reload_basic
>> @@ -33,6 +33,11 @@ function reload() {
>> pkill alsactl
>> snd_hda_intel_unloaded=0
>> if mod_loaded snd_hda_intel; then
>> +# unbind sound cards
>> +for card in $(find /sys/bus/pci/drivers/snd_hda_intel -name
>> ":*" -printf "%f\n"); do
>> +echo $card >
>> /sys/bus/pci/drivers/snd_hda_intel/unbind
>> +done
>> +
>> if rmmod snd_hda_intel; then
>> snd_hda_intel_unloaded=1
>> else
>> --
>> 2.1.4
>
--
Jani Nikula, Intel Open Source Technology Center
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