Re: [Intel-gfx] [PATCH v2 8/14] drm/i915/dp: Move max. vswing check to it's own function
On Tue, 2016-09-06 at 17:13 -0700, Manasi Navare wrote:
> From: Dhinakaran Pandiyan
>
> Wrap the max. vswing check in a separate function.
> This makes the clock recovery phase of DP link training cleaner
>
> v2:
> Fixed the Compiler warning (Mika Kahola)
>
> Signed-off-by: Dhinakaran Pandiyan
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/intel_dp_link_training.c | 17 +
> 1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index 0deebed..b1eee5b 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -112,6 +112,18 @@ intel_dp_update_link_train(struct intel_dp
> *intel_dp)
> return ret == intel_dp->lane_count;
> }
>
> +static bool intel_dp_link_max_vswing_reached(struct intel_dp
> *intel_dp)
> +{
> + int lane;
> +
> + for (lane = 0; lane < intel_dp->lane_count; lane++)
> + if (intel_dp->train_set[lane] &
> + (DP_TRAIN_MAX_SWING_REACHED == 0))
> + return false;
It seems that the parenthesis a misplaced here. I think you meant
if ((intel_dp->train_set[lane] &
DP_TRAIN_MAX_SWING_REACHED) == 0)
> +
> + return true;
> +}
> +
> /* Enable corresponding port and start training pattern 1 */
> static void
> intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
> @@ -170,10 +182,7 @@ intel_dp_link_training_clock_recovery(struct
> intel_dp *intel_dp)
> }
>
> /* Check to see if we've tried the max voltage */
> - for (i = 0; i < intel_dp->lane_count; i++)
> - if ((intel_dp->train_set[i] &
> DP_TRAIN_MAX_SWING_REACHED) == 0)
> - break;
> - if (i == intel_dp->lane_count) {
> + if (intel_dp_link_max_vswing_reached(intel_dp)) {
> ++loop_tries;
> if (loop_tries == 5) {
> DRM_ERROR("too many full retries,
> give up\n");
--
Mika Kahola - Intel OTC
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Re: [Intel-gfx] [PATCH] drm: squash lines for simple wrapper functions
Am 07.09.2016 um 01:04 schrieb Masahiro Yamada:
Remove unneeded variables and assignments.
Signed-off-by: Masahiro Yamada
Tom StDenis was working on a similar patch for amdgpu as well, please
make sure that your work doesn't conflict with his.
Apart from that looks good to me. But I would prefer this to be split up
per driver, cause I can't really give my rb on this patch when it
touches drivers all over the place.
On the other hand feel free to add my Acked-by and merge it as general
cleanup through Dave directly.
Regards,
Christian.
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c| 6 +-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c| 6 +-
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 20
drivers/gpu/drm/drm_dp_mst_topology.c | 7 ++-
drivers/gpu/drm/i915/i915_drv.c | 8 +---
drivers/gpu/drm/qxl/qxl_draw.c| 7 ++-
drivers/gpu/drm/qxl/qxl_release.c | 7 ++-
drivers/gpu/drm/radeon/cik.c | 6 +-
drivers/gpu/drm/radeon/r100.c | 6 +-
drivers/gpu/drm/radeon/r600.c | 6 +-
11 files changed, 17 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index b818461..0d5307a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5854,11 +5854,7 @@ static int gfx_v8_0_set_clockgating_state(void *handle,
static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
{
- u32 rptr;
-
- rptr = ring->adev->wb.wb[ring->rptr_offs];
-
- return rptr;
+ return ring->adev->wb.wb[ring->rptr_offs];
}
static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index a64715d..b165c78 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -190,12 +190,8 @@ out:
*/
static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
{
- u32 rptr;
-
/* XXX check if swapping is necessary on BE */
- rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
-
- return rptr;
+ return ring->adev->wb.wb[ring->rptr_offs] >> 2;
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 653ce5e..cf253b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -335,12 +335,8 @@ out:
*/
static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
{
- u32 rptr;
-
/* XXX check if swapping is necessary on BE */
- rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
-
- return rptr;
+ return ring->adev->wb.wb[ring->rptr_offs] >> 2;
}
/**
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 48030f0..d37d112 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -1073,34 +1073,22 @@ void analogix_dp_set_lane3_link_training(struct
analogix_dp_device *dp,
u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
{
- u32 reg;
-
- reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
- return reg;
+ return readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
}
u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
{
- u32 reg;
-
- reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
- return reg;
+ return readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
}
u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
{
- u32 reg;
-
- reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
- return reg;
+ return readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
}
u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
{
- u32 reg;
-
- reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
- return reg;
+ return readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
}
void analogix_dp_reset_macro(struct analogix_dp_device *dp)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 04e4571..302bdcb 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -737,16 +737,13 @@ static void drm_dp_mst_put_payload_id(struct
drm_dp_mst_topology_mgr *mgr,
static bool check_txmsg_state(struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_sideband_msg_tx *txmsg)
{
- bool ret;
-
/*
* All updates
Re: [Intel-gfx] [PATCH v2 9/14] drm/dp/i915: Make clock recovery in the link training compliant with DP Spec 1.2
On Tue, 2016-09-06 at 17:13 -0700, Manasi Navare wrote:
> From: Dhinakaran Pandiyan
>
> This function cleans up clock recovery loop in link training
> compliant
> tp Dp Spec 1.2. It tries the clock recovery 5 times for the same
> voltage
> or until max voltage swing is reached and removes the additional non
> compliant retries. This function now returns a boolean values based
> on
> if clock recovery passed or failed.
>
> v2:
> * Rebased on top of new revision of vswing patch (Manasi Navare)
>
> Signed-off-by: Dhinakaran Pandiyan
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/intel_dp_link_training.c | 56 -
> --
> 1 file changed, 24 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index b1eee5b..fbdb2e4 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -125,12 +125,11 @@ static bool
> intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
> }
>
> /* Enable corresponding port and start training pattern 1 */
> -static void
> +static bool
> intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
> {
> - int i;
> uint8_t voltage;
> - int voltage_tries, loop_tries;
> + int voltage_tries, max_vswing_tries;
> uint8_t link_config[2];
> uint8_t link_bw, rate_select;
>
> @@ -146,6 +145,7 @@ intel_dp_link_training_clock_recovery(struct
> intel_dp *intel_dp)
> if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET,
> link_config, 2);
> +
> if (intel_dp->num_sink_rates)
> drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> &rate_select, 1);
> @@ -161,58 +161,50 @@ intel_dp_link_training_clock_recovery(struct
> intel_dp *intel_dp)
> DP_TRAINING_PATTERN_1 |
> DP_LINK_SCRAMBLING_DISABLE))
> {
> DRM_ERROR("failed to enable link training\n");
> - return;
> + return false;
> }
>
> - voltage = 0xff;
> - voltage_tries = 0;
> - loop_tries = 0;
> + voltage_tries = 1;
> + max_vswing_tries = 0;
> for (;;) {
> uint8_t link_status[DP_LINK_STATUS_SIZE];
>
> drm_dp_link_train_clock_recovery_delay(intel_dp-
> >dpcd);
> +
> if (!intel_dp_get_link_status(intel_dp,
> link_status)) {
> DRM_ERROR("failed to get link status\n");
> - break;
> + return false;
> }
>
> if (drm_dp_clock_recovery_ok(link_status, intel_dp-
> >lane_count)) {
> DRM_DEBUG_KMS("clock recovery OK\n");
> - break;
> + return true;
> }
>
> - /* Check to see if we've tried the max voltage */
> - if (intel_dp_link_max_vswing_reached(intel_dp)) {
> - ++loop_tries;
> - if (loop_tries == 5) {
> - DRM_ERROR("too many full retries,
> give up\n");
> - intel_dp_dump_link_status(link_statu
> s);
> - break;
> - }
> - intel_dp_reset_link_train(intel_dp,
> - DP_TRAINING_PATTER
> N_1 |
> - DP_LINK_SCRAMBLING
> _DISABLE);
> - voltage_tries = 0;
> - continue;
> + if (voltage_tries == 5 || max_vswing_tries == 1) {
> + DRM_DEBUG_KMS("Max. vswing reached or same
> voltage "
> + "tried 5 times\n");
> + return false;
> }
I would split this debug message in two parts so we could separate
which one we actually hit. Did we try voltage for 5 times or did we
reach max vswing. This separation might be useful if or when we need to
debug this one.
>
> - /* Check to see if we've tried the same voltage 5
> times */
> - if ((intel_dp->train_set[0] &
> DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
> - ++voltage_tries;
> - if (voltage_tries == 5) {
> - DRM_ERROR("too many voltage retries,
> give up\n");
> - break;
> - }
> - } else
> - voltage_tries = 0;
> voltage = intel_dp->train_set[0] &
> DP_TRAIN_VOLTAGE_SWING_MASK;
>
> /* Update training set as requested by target */
> intel_get_adjust_train(intel_dp, link_status);
> if (!intel_dp_update_link_train(intel_dp)) {
>
Re: [Intel-gfx] [PATCH 10/14] drm/i915: Make DP link training channel equalization DP 1.2 Spec compliant
Reviewed-by: Mika Kahola
On Fri, 2016-09-02 at 22:05 +0300, Pandiyan, Dhinakaran wrote:
> On Fri, 2016-09-02 at 14:20 +0300, Mika Kahola wrote:
> >
> > On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote:
> > >
> > > Fix the number of tries in channel euqalization link training
> > > sequence
> > > according to DP 1.2 Spec. It returns a boolean depending on
> > > channel
> > > equalization pass or failure.
> > >
> > > Signed-off-by: Dhinakaran Pandiyan > > >
> > > Signed-off-by: Manasi Navare
> > > ---
> > > drivers/gpu/drm/i915/intel_dp_link_training.c | 57 ++---
> > >
> > > --
> > > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > > 2 files changed, 22 insertions(+), 36 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c
> > > b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > > index 13a0341..07f0159 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > > @@ -240,12 +240,12 @@ static u32 intel_dp_training_pattern(struct
> > > intel_dp *intel_dp)
> > > return training_pattern;
> > > }
> > >
> > > -static void
> > > +static bool
> > > intel_dp_link_training_channel_equalization(struct intel_dp
> > > *intel_dp)
> > > {
> > > - bool channel_eq = false;
> > > - int tries, cr_tries;
> > > + int tries;
> > > u32 training_pattern;
> > > + uint8_t link_status[DP_LINK_STATUS_SIZE];
> > >
> > > training_pattern = intel_dp_training_pattern(intel_dp);
> > >
> > > @@ -254,20 +254,11 @@
> > > intel_dp_link_training_channel_equalization(struct intel_dp
> > > *intel_dp)
> > > training_pattern |
> > > DP_LINK_SCRAMBLING_DISABLE)
> > > ) {
> > > DRM_ERROR("failed to start channel
> > > equalization\n");
> > > - return;
> > > + return false;
> > > }
> > >
> > > - tries = 0;
> > > - cr_tries = 0;
> > > - channel_eq = false;
> > > - for (;;) {
> > > - uint8_t link_status[DP_LINK_STATUS_SIZE];
> > > -
> > > - if (cr_tries > 5) {
> > > - DRM_ERROR("failed to train DP,
> > > aborting\n");
> > > - intel_dp_dump_link_status(link_status);
> > > - break;
> > > - }
> > > + intel_dp->channel_eq_status = false;
> > > + for (tries = 0; tries < 5; tries++) {
> > >
> > > drm_dp_link_train_channel_eq_delay(intel_dp-
> > > >dpcd);
> > > if (!intel_dp_get_link_status(intel_dp,
> > > link_status)) {
> > > @@ -278,44 +269,38 @@
> > > intel_dp_link_training_channel_equalization(struct intel_dp
> > > *intel_dp)
> > > /* Make sure clock is still ok */
> > > if (!drm_dp_clock_recovery_ok(link_status,
> > > intel_dp-
> > > >lane_count))
> > > {
> > > - intel_dp_link_training_clock_recovery(in
> > > tel_
> > > dp);
> > > - intel_dp_set_link_train(intel_dp,
> > > - training_pattern
> > > |
> > > - DP_LINK_SCRAMBLI
> > > NG_D
> > > ISABLE);
> > > - cr_tries++;
> > > - continue;
> > > + intel_dp_dump_link_status(link_status);
> > > + DRM_DEBUG_KMS("Clock recovery check
> > > failed,
> > > cannot "
> > > + "continue channel
> > > equalization\n");
> > > + break;
> > > }
> > This clock recovery check got me thinking. Do we really need to
> > check
> > if clock recovery is still ok within a loop? Could we move this
> > outside
> > the loop and return early if we have failed in clock recovery? One
> > idea
> > that I have in mind is that we wouldn't need to enter in channel
> > equalization if we have failed with clock recovery earlier.
> >
> Looks like we do. This check helps us to break out of the loop for
> link
> rate reduction after adjusting drive setting.
You're right we do that.
>
>
> >
> > >
> > >
> > > if (drm_dp_channel_eq_ok(link_status,
> > > intel_dp->lane_count))
> > > {
> > > - channel_eq = true;
> > > + intel_dp->channel_eq_status = true;
> > > + DRM_DEBUG_KMS("Channel EQ done. DP
> > > Training
> > > "
> > > + "successful\n");
> > > break;
> > > }
> > >
> > > - /* Try 5 times, then try clock recovery if that
> > > fails */
> > > - if (tries > 5) {
> > > - intel_dp_link_training_clock_recovery(in
> > > tel_
> > > dp);
> > > - intel_dp_set_link_train(intel_dp,
> > > - training_pattern
> > > |
> > > - DP_LINK_SCRAMBLI
> > > NG_D
> > > ISABLE);
> > > - tries = 0;
> > > - cr_tries++;
> > > -
Re: [Intel-gfx] [PATCH] tools/intel_guc_logger: Utility for capturing GuC firmware logs in a file
On 9/6/2016 9:22 PM, Tvrtko Ursulin wrote:
On 06/09/16 16:33, Goel, Akash wrote:
On 9/6/2016 6:47 PM, Tvrtko Ursulin wrote:
Hi,
On 06/09/16 11:43, akash.g...@intel.com wrote:
From: Akash Goel
This patch provides a test utility which helps capture GuC firmware
logs and
then dump them to file.
The logs are pulled from a debugfs file
'/sys/kernel/debug/dri/guc_log' and
stored into a file '/tmp/guc_log_dump.dat', the name of the output
file can
be changed through a command line argument.
The utility goes into an infinite loop where it waits for the arrival
of new
logs and as soon as new set of logs are produced it captures them in
its local
buffer which is then flushed out to the file on disk.
Any time when logging needs to be ended, User can stop this utility
(CTRL+C).
Before entering into a loop, it first discards whatever logs are
present in
the debugfs file.
This way User can first launch this utility and then start a
workload/activity
for which GuC firmware logs are to be actually captured and keep
running the
utility for as long as its needed, like once the workload is over this
utility
can be forcefully stopped.
If the logging wasn't enabled on GuC side by the Driver at boot time,
utility
will first enable the logging and later on when it is stopped (CTRL+C)
it will
also pause the logging on GuC side.
Signed-off-by: Akash Goel
---
tools/Makefile.sources | 1 +
tools/intel_guc_logger.c | 441
+++
2 files changed, 442 insertions(+)
create mode 100644 tools/intel_guc_logger.c
diff --git a/tools/Makefile.sources b/tools/Makefile.sources
index 2bb6c8e..be58871 100644
--- a/tools/Makefile.sources
+++ b/tools/Makefile.sources
@@ -19,6 +19,7 @@ tools_prog_lists =\
intel_gpu_time\
intel_gpu_top\
intel_gtt\
+intel_guc_logger\
intel_infoframes\
intel_l3_parity\
intel_lid\
diff --git a/tools/intel_guc_logger.c b/tools/intel_guc_logger.c
new file mode 100644
index 000..92172fa
--- /dev/null
+++ b/tools/intel_guc_logger.c
@@ -0,0 +1,441 @@
+
+#define _GNU_SOURCE /* For using O_DIRECT */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "igt.h"
+
+#define MB(x) ((uint64_t)(x) * 1024 * 1024)
+#ifndef PAGE_SIZE
+ #define PAGE_SIZE 4096
+#endif
+#define SUBBUF_SIZE (19*PAGE_SIZE)
+/* Need large buffering from logger side to hide the DISK IO latency,
Driver
+ * can only store 8 snapshots of GuC log buffer in relay.
+ */
+#define NUM_SUBBUFS 100
+
+#define RELAY_FILE_NAME "guc_log"
+#define CONTROL_FILE_NAME "i915_guc_log_control"
+
+char *read_buffer;
+char *out_filename;
+int poll_timeout = 2; /* by default 2ms timeout */
+pthread_mutex_t mutex;
+pthread_t flush_thread;
+int verbosity_level = 3; /* by default capture logs at max
verbosity */
+uint32_t produced, consumed;
+uint64_t total_bytes_written;
+int num_buffers = NUM_SUBBUFS;
+int relay_fd, outfile_fd = -1;
+bool stop_logging, discard_oldlogs;
+uint32_t test_duration, max_filesize;
+pthread_cond_t underflow_cond, overflow_cond;
+
+static void guc_log_control(bool enable_logging)
+{
+int control_fd;
+char data[19];
+uint64_t val;
+int ret;
+
+control_fd = igt_debugfs_open(CONTROL_FILE_NAME, O_WRONLY);
+if (control_fd < 0)
+igt_assert_f(0, "Couldn't open the guc log control file");
+
+val = enable_logging ? ((verbosity_level << 4) | 0x1) : 0;
+
+snprintf(data, sizeof(data), "0x%" PRIx64, val);
+ret = write(control_fd, data, strlen(data) + 1);
Minor: It looks safe like it is but something like below would maybe be
more robust?
ret = snprintf(data, sizeof(data), "0x%" PRIx64, val);
igt_assert(ret > 2 && ret < sizeof(data));
ok will add, but possibility of failure will be really remote here.
but igt_assert(ret > 0) should suffice.
Yes there is no possibility for failure as it stands, just more robust
implementation should someone change something in the future. That's why
I said you could also decide to keep it as is. My version also avoided
the strlen since snprintf already tells you that.
fine, will use your version then.
ret = write(control_fd, data, ret);
igt_assert(ret > 0); // assuming short writes can't happen
Up to you.
+if (ret < 0)
+igt_assert_f(0, "Couldn't write to the log control file");
+
+close(control_fd);
+}
+
+static void int_sig_handler(int sig)
+{
+igt_info("Received signal %d\n", sig);
+
+stop_logging = true;
+}
+
+static void pull_leftover_data(void)
+{
+unsigned int bytes_read = 0;
+int ret;
+
+while (1) {
+/* Read the logs from relay buffer */
+ret = read(relay_fd, read_buffer, SUBBUF_SIZE);
+if (!ret)
+break;
+else if (ret < 0)
+igt_assert_f(0, "Failed to read from the guc lo
[Intel-gfx] [PATCH v4 00/25] Add support for GuC-based SLPC
SLPC (Single Loop Power Controller) is a replacement for some host-based power management features. The SLPC implementation runs in firmware on GuC. This series has been tested with SKL GuC firmware version 9.18 which is yet to be released. Performance and power testing with these patches and 9.18 firmware is at parity and in some cases better than host solution today on various Linux benchmarks. The graphics power management features in SLPC in this version are called GTPERF, BALANCER, and DCC. GTPERF is a combination of DFPS (Dynamic FPS) and Turbo. DFPS adjusts requested graphics frequency to maintain target framerate. Turbo adjusts requested graphics frequency to maintain target GT busyness; this includes an adaptive boost turbo method. BALANCER adjusts balance between power budgets for IA and GT in power limited scenarios. BALANCER is only active when all display pipes are in "game" mode. DCC (Duty Cycle Control) adjusts requested graphics frequency and stalls guc-scheduler to maintain actual graphics frequency in efficient range. The last series can be found in the archive at "[Intel-gfx] [PATCH v4 00/21] Add support for GuC-based SLPC" https://lists.freedesktop.org/archives/intel-gfx/2016-April/094445.html This series incorporates feedback from code reviews on earlier series. It drops the display mode notification patches as it is not needed for Turbo part of GTPERF. This series also adds new interface changes for SLPC support on 9.18 GuC Firmware which is not yet published. Will like to get review started prior to firmware is published. With SLPC disabled by default, this series should be safe to merge now and it can be enabled once 9.18 firmware is released. v2: Addressed review comments on v1. Removed patch to enable SLPC by default. v3: Addressed WARNING in igt@drv_module_reload_basic flagged by trybot BAT. Added change for sanitizing GT PM during reset. Added separate patch for sysfs interface to know HW requested frequency. Also, earlier patches did not go as series hence were not correctly picked up by BAT. v4: Changes to multiple patches. CI BAT is passing. Performance run on SKL GT2 done and shows perf at parity with Host Turbo. For BXT, SLPC improves performance when GuC is enabled compared to Host Turbo. This series keeps only support of 9.18 firmware for better readability. If needed, other SLPC interfaces for different GuC version will be added later. VIZ-6773, VIZ-6889, VIZ-6890 Cc: Chris Wilson Cc: Daniel Vetter Cc: Beuchat, Marc Cc: Jeff McGee Cc: Paulo Zanoni Sagar Arun Kamble (7): drm/i915: Remove RPM suspend dependency on rps.enabled and related changes drm/i915/slpc: Only Enable GTPERF, Disable DCC, Balancer, IBC, FPS Stall drm/i915/slpc: Update freq min/max softlimits drm/i915/slpc: Check GuC load status in SLPC active check drm/i915/slpc: Keep RP SW Mode enabled while disabling rps drm/i915: Add sysfs interface to know the HW requested frequency drm/i915: Mark GuC load status as PENDING in i915_drm_resume_early Tom O'Rourke (18): drm/i915/slpc: Expose guc functions for use with SLPC drm/i915/slpc: Add has_slpc capability flag drm/i915/slpc: Add SKL SLPC Support drm/i915/slpc: Add enable_slpc module parameter drm/i915/slpc: Sanitize SLPC version drm/i915/slpc: Use intel_slpc_* functions if supported drm/i915/slpc: Enable SLPC in guc if supported drm/i915/slpc: If using SLPC, do not set frequency drm/i915/slpc: Allocate/Release/Initialize SLPC shared data drm/i915/slpc: Update sysfs/debugfs interfaces for frequency parameters drm/i915/slpc: Send reset event drm/i915/slpc: Send shutdown event drm/i915/slpc: Add slpc_status enum values drm/i915/slpc: Add parameter unset/set/get functions drm/i915/slpc: Add slpc support for max/min freq drm/i915/slpc: Add enable/disable debugfs for slpc drm/i915/slpc: Add i915_slpc_info to debugfs drm/i915/slpc: Add Broxton SLPC support drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915_debugfs.c| 491 - drivers/gpu/drm/i915/i915_drv.c| 21 +- drivers/gpu/drm/i915/i915_drv.h| 4 +- drivers/gpu/drm/i915/i915_guc_submission.c | 16 +- drivers/gpu/drm/i915/i915_params.c | 6 + drivers/gpu/drm/i915/i915_params.h | 1 + drivers/gpu/drm/i915/i915_pci.c| 3 + drivers/gpu/drm/i915/i915_sysfs.c | 49 +++ drivers/gpu/drm/i915/intel_drv.h | 13 + drivers/gpu/drm/i915/intel_guc.h | 12 + drivers/gpu/drm/i915/intel_guc_loader.c| 30 ++ drivers/gpu/drm/i915/intel_pm.c| 133 ++-- drivers/gpu/drm/i915/intel_runtime_pm.c| 3 +- drivers/gpu/drm/i915/intel_slpc.c | 389 +++ drivers/gpu/drm/i915/intel_slpc.h | 215 + 16 files changed, 1335 insertions(+), 54 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_slpc.c create mode 100644 drivers/g
[Intel-gfx] [PATCH v4 01/25] drm/i915: Remove RPM suspend dependency on rps.enabled and related changes
For Gen9, RPM suspend is dependent on rps.enabled. This is needed for
other platforms as RC6 and RPS enabling is indicated by rps.enabled. RPM
Suspend depends only on RC6, so we need to remove the check of rps.enabled.
For Gen9 RC6 and RPS enabling is separated hence do rps.enabled check only
for non-Gen9 platforms. Once RC6 and RPS enabling is separated for other
GENs this check can be completely removed.
Moved setting of rps.enabled to platform level functions as there is case
of disabling of RPS in gen9_enable_rps.
v2: Changing parameter to dev_priv for IS_GEN9 and HAS_RUNTIME_PM and line
spacing changes. (David)
and commit message update for checkpatch issues.
v3: Rebase.
v4: Commit message update.
Reviewed-by: David Weinehall
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c | 14 +++---
drivers/gpu/drm/i915/intel_pm.c | 20 ++--
drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
3 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 02c34d6..1f677a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2284,10 +2284,18 @@ static int intel_runtime_suspend(struct device *kdev)
struct drm_i915_private *dev_priv = to_i915(dev);
int ret;
- if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(
+ if (WARN_ON_ONCE(!intel_enable_rc6()))
return -ENODEV;
- if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
+ /*
+* Once RC6 and RPS enabling is separated for non-GEN9 platforms
+* below check should be removed.
+ */
+ if (!IS_GEN9(dev_priv))
+ if (WARN_ON_ONCE(!dev_priv->rps.enabled))
+ return -ENODEV;
+
+ if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
return -ENODEV;
DRM_DEBUG_KMS("Suspending device\n");
@@ -2391,7 +2399,7 @@ static int intel_runtime_resume(struct device *kdev)
struct drm_i915_private *dev_priv = to_i915(dev);
int ret = 0;
- if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
+ if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
return -ENODEV;
DRM_DEBUG_KMS("Resuming device\n");
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4f833a0..b9c460c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5061,6 +5061,8 @@ static void gen9_disable_rc6(struct drm_i915_private
*dev_priv)
static void gen9_disable_rps(struct drm_i915_private *dev_priv)
{
I915_WRITE(GEN6_RP_CONTROL, 0);
+
+ dev_priv->rps.enabled = false;
}
static void gen6_disable_rps(struct drm_i915_private *dev_priv)
@@ -5068,11 +5070,15 @@ static void gen6_disable_rps(struct drm_i915_private
*dev_priv)
I915_WRITE(GEN6_RC_CONTROL, 0);
I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
I915_WRITE(GEN6_RP_CONTROL, 0);
+
+ dev_priv->rps.enabled = false;
}
static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
{
I915_WRITE(GEN6_RC_CONTROL, 0);
+
+ dev_priv->rps.enabled = false;
}
static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
@@ -5084,6 +5090,8 @@ static void valleyview_disable_rps(struct
drm_i915_private *dev_priv)
I915_WRITE(GEN6_RC_CONTROL, 0);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ dev_priv->rps.enabled = false;
}
static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
@@ -5301,6 +5309,8 @@ static void gen9_enable_rps(struct drm_i915_private
*dev_priv)
reset_rps(dev_priv, gen6_set_rps);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ dev_priv->rps.enabled = true;
}
static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
@@ -5444,6 +5454,8 @@ static void gen8_enable_rps(struct drm_i915_private
*dev_priv)
reset_rps(dev_priv, gen6_set_rps);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ dev_priv->rps.enabled = true;
}
static void gen6_enable_rps(struct drm_i915_private *dev_priv)
@@ -5540,6 +5552,8 @@ static void gen6_enable_rps(struct drm_i915_private
*dev_priv)
}
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ dev_priv->rps.enabled = true;
}
static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
@@ -6014,6 +6028,8 @@ static void cherryview_enable_rps(struct drm_i915_private
*dev_priv)
reset_rps(dev_priv, valleyview_set_rps);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ dev_priv->rps.enabled = true;
}
static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
@@ -6094,6 +6110,8 @@ static void valleyview_enable_rps(struct drm_i915_private
*dev_priv)
reset_rps(dev_priv, valleyview_set_rps);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_AL
[Intel-gfx] [PATCH v4 08/25] drm/i915/slpc: Enable SLPC in guc if supported
From: Tom O'Rourke
If slpc enabled, then add enable SLPC flag to guc
control parameter during guc load.
v1: Use intel_slpc_enabled() (Paulo)
Reviewed-by: David Weinehall
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 500b0b6..2dda771 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -213,6 +213,9 @@ static void set_guc_init_params(struct drm_i915_private
*dev_priv)
params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
GUC_CTL_VCS2_ENABLED;
+ if (intel_slpc_enabled())
+ params[GUC_CTL_FEATURE] |= GUC_CTL_ENABLE_SLPC;
+
if (i915.guc_log_level >= 0) {
params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
params[GUC_CTL_DEBUG] =
--
1.9.1
___
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[Intel-gfx] [PATCH v4 03/25] drm/i915/slpc: Add has_slpc capability flag
From: Tom O'Rourke
Add has_slpc capablity flag to indicate GuC firmware
supports single loop power control (SLPC). SLPC is
a replacement for some host-based power management
features.
v1: fix whitespace (Sagar)
Reviewed-by: David Weinehall
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ecfd8e9..b86f658 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -664,7 +664,8 @@ struct intel_csr {
func(has_snoop) sep \
func(has_ddi) sep \
func(has_fpga_dbg) sep \
- func(has_pooled_eu)
+ func(has_pooled_eu) sep \
+ func(has_slpc)
#define DEFINE_FLAG(name) u8 name:1
#define SEP_SEMICOLON ;
@@ -2804,6 +2805,7 @@ struct drm_i915_cmd_table {
#define HAS_GUC(dev) (IS_GEN9(dev))
#define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
#define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
+#define HAS_SLPC(dev) (INTEL_INFO(dev)->has_slpc)
#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
INTEL_INFO(dev)->gen >= 8)
--
1.9.1
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[Intel-gfx] [PATCH v4 09/25] drm/i915/slpc: If using SLPC, do not set frequency
From: Tom O'Rourke
When frequency requests are made by SLPC, host driver
should not attempt to make frequency requests due to
potential conflicts.
Host-based turbo operations are already avoided when
SLPC is used. This change covers other frequency
requests such as from sysfs or debugfs interfaces.
A later patch in this series updates sysfs/debugfs
interfaces for setting max/min frequencies with SLPC.
v1: Use intel_slpc_active instead of HAS_SLPC (Paulo)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index db5c4ef..d187066 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5047,6 +5047,9 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
{
+ if (intel_slpc_active(dev_priv))
+ return;
+
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
valleyview_set_rps(dev_priv, val);
else
--
1.9.1
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[Intel-gfx] [PATCH v4 07/25] drm/i915/slpc: Use intel_slpc_* functions if supported
From: Tom O'Rourke
On platforms with SLPC support: call intel_slpc_*()
functions from corresponding intel_*_gt_powersave()
functions; and do not use rps functions.
v1: Return void instead of ignored error code (Paulo)
enable/disable RC6 in SLPC flows (Sagar)
replace HAS_SLPC() use with intel_slpc_enabled()
or intel_slpc_active() (Paulo)
Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
"drm/i915/bxt: Explicitly clear the Turbo control register"
Defer RC6 and SLPC enabling to intel_gen6_powersave_work. (Sagar)
Performance drop with SLPC was happening as ring frequency table
was not programmed when SLPC was enabled. This patch programs ring
frequency table with SLPC. Initial reset of SLPC is based on kernel
parameter as planning to add slpc state in intel_slpc_active. Cleanup
is also based on kernel parameter as SLPC gets disabled in
disable/suspend.(Sagar)
v2: Usage of INTEL_GEN instead of INTEL_INFO->gen (David)
Checkpatch update.
v3: Rebase
v4: Removed reset functions to comply with *_gt_powersave routines.
(Sagar)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/intel_drv.h | 4 ++
drivers/gpu/drm/i915/intel_guc.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 96 +++
drivers/gpu/drm/i915/intel_slpc.c | 46 +++
drivers/gpu/drm/i915/intel_slpc.h | 34 ++
6 files changed, 153 insertions(+), 31 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
create mode 100644 drivers/gpu/drm/i915/intel_slpc.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a7da246..229290d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -52,7 +52,8 @@ i915-y += i915_cmd_parser.o \
# general-purpose microcontroller (GuC) support
i915-y += intel_guc_loader.o \
- i915_guc_submission.o
+ i915_guc_submission.o \
+ intel_slpc.o
# autogenerated null render state
i915-y += intel_renderstate_gen6.o \
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 570a7ca..6f9480b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1712,6 +1712,10 @@ void chv_phy_powergate_lanes(struct intel_encoder
*encoder,
bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
enum dpio_channel ch, bool override);
+static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
+{
+ return 0;
+}
/* intel_pm.c */
void intel_init_clock_gating(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index d73e4ed..83dec66 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -27,6 +27,7 @@
#include "intel_guc_fwif.h"
#include "i915_guc_reg.h"
#include "intel_ringbuffer.h"
+#include "intel_slpc.h"
struct drm_i915_gem_request;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 56bde62..db5c4ef 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4988,7 +4988,8 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
* our rpm wakeref. And then disable the interrupts to stop any
* futher RPS reclocking whilst we are asleep.
*/
- gen6_disable_rps_interrupts(dev_priv);
+ if (!intel_slpc_active(dev_priv))
+ gen6_disable_rps_interrupts(dev_priv);
mutex_lock(&dev_priv->rps.hw_lock);
if (dev_priv->rps.enabled) {
@@ -6641,6 +6642,9 @@ void intel_init_gt_powersave(struct drm_i915_private
*dev_priv)
/* Finally allow us to boost to max by default */
dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
+ if (intel_slpc_enabled())
+ intel_slpc_init(dev_priv);
+
mutex_unlock(&dev_priv->rps.hw_lock);
mutex_unlock(&dev_priv->drm.struct_mutex);
@@ -6649,7 +6653,9 @@ void intel_init_gt_powersave(struct drm_i915_private
*dev_priv)
void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
{
- if (IS_VALLEYVIEW(dev_priv))
+ if (intel_slpc_enabled())
+ intel_slpc_cleanup(dev_priv);
+ else if (IS_VALLEYVIEW(dev_priv))
valleyview_cleanup_gt_powersave(dev_priv);
if (!i915.enable_rc6)
@@ -6673,24 +6679,38 @@ void intel_suspend_gt_powersave(struct drm_i915_private
*dev_priv)
intel_runtime_pm_put(dev_priv);
/* gen6_rps_idle() will be called later to disable interrupts */
+
+ if (intel_slpc_active(dev_priv))
+ intel_slpc_suspend(dev_priv);
}
void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
{
- dev_priv->rps.enabled = true; /* force disabling */
- intel_disable_gt_powersave(dev_priv);
+ if (intel
[Intel-gfx] [PATCH v4 02/25] drm/i915/slpc: Expose guc functions for use with SLPC
From: Tom O'Rourke
Expose host2guc_action for use by SLPC in intel_slpc.c.
Expose functions to allocate and release objects used
by GuC to be used for SLPC shared memory object.
v1: Updated function names as they need to be made extern. (ChrisW)
Reviewed-by: David Weinehall
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_guc_submission.c | 16
drivers/gpu/drm/i915/intel_guc.h | 2 ++
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 77526d7..5f80751 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -47,7 +47,7 @@
* Firmware writes a success/fail code back to the action register after
* processes the request. The kernel driver polls waiting for this update and
* then proceeds.
- * See host2guc_action()
+ * See i915_guc_action()
*
* Doorbells:
* Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
@@ -75,7 +75,7 @@ static inline bool host2guc_action_response(struct
drm_i915_private *dev_priv,
return GUC2HOST_IS_RESPONSE(val);
}
-static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
+int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
u32 status;
@@ -139,7 +139,7 @@ static int host2guc_allocate_doorbell(struct intel_guc *guc,
data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
data[1] = client->ctx_index;
- return host2guc_action(guc, data, 2);
+ return i915_guc_action(guc, data, 2);
}
static int host2guc_release_doorbell(struct intel_guc *guc,
@@ -150,7 +150,7 @@ static int host2guc_release_doorbell(struct intel_guc *guc,
data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
data[1] = client->ctx_index;
- return host2guc_action(guc, data, 2);
+ return i915_guc_action(guc, data, 2);
}
static int host2guc_sample_forcewake(struct intel_guc *guc,
@@ -167,7 +167,7 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
/* bit 0 and 1 are for Render and Media domain separately */
data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
- return host2guc_action(guc, data, ARRAY_SIZE(data));
+ return i915_guc_action(guc, data, ARRAY_SIZE(data));
}
/*
@@ -620,7 +620,7 @@ static void i915_guc_submit(struct drm_i915_gem_request *rq)
*
* Return: A i915_vma if successful, otherwise an ERR_PTR.
*/
-static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
+struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct drm_i915_gem_object *obj;
@@ -1064,7 +1064,7 @@ int intel_guc_suspend(struct drm_device *dev)
/* first page is shared data with GuC */
data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
- return host2guc_action(guc, data, ARRAY_SIZE(data));
+ return i915_guc_action(guc, data, ARRAY_SIZE(data));
}
@@ -1089,5 +1089,5 @@ int intel_guc_resume(struct drm_device *dev)
/* first page is shared data with GuC */
data[2] = i915_ggtt_offset(ctx->engine[RCS].state);
- return host2guc_action(guc, data, ARRAY_SIZE(data));
+ return i915_guc_action(guc, data, ARRAY_SIZE(data));
}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index c973262..9e6b948 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -155,9 +155,11 @@ extern int intel_guc_suspend(struct drm_device *dev);
extern int intel_guc_resume(struct drm_device *dev);
/* i915_guc_submission.c */
+int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len);
int i915_guc_submission_init(struct drm_i915_private *dev_priv);
int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
int i915_guc_wq_check_space(struct drm_i915_gem_request *rq);
+struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size);
void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
--
1.9.1
___
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[Intel-gfx] [PATCH v4 04/25] drm/i915/slpc: Add SKL SLPC Support
From: Tom O'Rourke
This patch adds has_slpc to skylake info.
The SLPC interface has changed and could continue to
change. Only GuC versions known to be compatible are
supported here.
On Skylake, GuC firmware v6 is supported. Other
platforms and versions can be added here later.
v1: Move slpc_version_check to intel_guc_ucode_init.
fix whitespace (Sagar)
Moved version check to different patch as has_slpc
should not be updated based on it. Instead module parameter
should be updated based on version check. (Sagar)
Added support to skylake_gt3 as well. (Sagar)
Reviewed-by: David Weinehall
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 2587b1b..e678051 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -322,12 +322,14 @@ static const struct intel_device_info intel_skylake_info
= {
BDW_FEATURES,
.is_skylake = 1,
.gen = 9,
+ .has_slpc = 1,
};
static const struct intel_device_info intel_skylake_gt3_info = {
BDW_FEATURES,
.is_skylake = 1,
.gen = 9,
+ .has_slpc = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
--
1.9.1
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[Intel-gfx] [PATCH v4 05/25] drm/i915/slpc: Add enable_slpc module parameter
From: Tom O'Rourke
i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.
slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1.
Interpretation of default value is based on HAS_SLPC(), after
slpc_version_check(). This function also enforces the requirement
that guc_submission is required for slpc.
intel_slpc_enabled() returns 1 if SLPC should be used.
v1: Add early call to sanitize enable_slpc in intel_guc_ucode_init
Remove sanitize enable_slpc call before firmware version check
is performed. (ChrisW)
Version check is added in next patch and that will be done as
part of slpc_enable_sanitize function in the next patch. (Sagar)
Updated slpc option sanitize function call for platforms without
GuC support. This was caught by CI BAT.
v2: Changed parameter to dev_priv for HAS_SLPC macro. (David)
Code indentation based on checkpatch.
v3: Rebase.
v4: Moved sanitization of SLPC option post GuC load.
Suggested-by: Paulo Zanoni
Reviewed-by: David Weinehall
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_params.c | 6 ++
drivers/gpu/drm/i915/i915_params.h | 1 +
drivers/gpu/drm/i915/intel_guc.h| 7 +++
drivers/gpu/drm/i915/intel_guc_loader.c | 19 +++
drivers/gpu/drm/i915/intel_pm.c | 2 ++
5 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 768ad89..72b3097 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -36,6 +36,7 @@ struct i915_params i915 __read_mostly = {
.enable_dc = -1,
.enable_fbc = -1,
.enable_execlists = -1,
+ .enable_slpc = 0,
.enable_hangcheck = true,
.enable_ppgtt = -1,
.enable_psr = -1,
@@ -131,6 +132,11 @@ MODULE_PARM_DESC(enable_execlists,
"Override execlists usage. "
"(-1=auto [default], 0=disabled, 1=enabled)");
+module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
+MODULE_PARM_DESC(enable_slpc,
+ "Override single-loop-power-controller (slpc) usage. "
+ "(-1=auto, 0=disabled [default], 1=enabled)");
+
module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
MODULE_PARM_DESC(enable_psr, "Enable PSR "
"(0=disabled, 1=enabled - link mode chosen per-platform,
2=force link-standby mode, 3=force link-off mode) "
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 3a0dd78..391c471 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -39,6 +39,7 @@ struct i915_params {
int enable_fbc;
int enable_ppgtt;
int enable_execlists;
+ int enable_slpc;
int enable_psr;
unsigned int preliminary_hw_support;
int disable_power_well;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 9e6b948..d73e4ed 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -146,6 +146,12 @@ struct intel_guc {
uint32_t last_seqno[I915_NUM_ENGINES];
};
+static inline int intel_slpc_enabled(void)
+{
+ WARN_ON(i915.enable_slpc < 0);
+ return i915.enable_slpc;
+}
+
/* intel_guc_loader.c */
extern void intel_guc_init(struct drm_device *dev);
extern int intel_guc_setup(struct drm_device *dev);
@@ -153,6 +159,7 @@ extern void intel_guc_fini(struct drm_device *dev);
extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
extern int intel_guc_suspend(struct drm_device *dev);
extern int intel_guc_resume(struct drm_device *dev);
+extern void sanitize_slpc_option(struct drm_i915_private *dev_priv);
/* i915_guc_submission.c */
int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 853928f..fb38018 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -144,6 +144,25 @@ static void direct_interrupts_to_guc(struct
drm_i915_private *dev_priv)
}
}
+void sanitize_slpc_option(struct drm_i915_private *dev_priv)
+{
+ /* Handle default case */
+ if (i915.enable_slpc < 0)
+ i915.enable_slpc = HAS_SLPC(dev_priv);
+
+ /* slpc requires hardware support and compatible firmware */
+ if (!HAS_SLPC(dev_priv))
+ i915.enable_slpc = 0;
+
+ /* slpc requires guc loaded */
+ if (!i915.enable_guc_loading)
+ i915.enable_slpc = 0;
+
+ /* slpc requires guc submission */
+ if (!i915.enable_guc_submission)
+ i915.enable_slpc = 0;
+}
+
static u32 get_gttype(struct drm_i915_private *dev_priv)
{
/* XXX: GT type based on PCI device ID? field seems unused by fw */
diff --git a/drivers/gpu/d
[Intel-gfx] [PATCH v4 12/25] drm/i915/slpc: Send reset event
From: Tom O'Rourke
Add host2guc SLPC reset event and send reset event
during enable.
v1: Extract host2guc_slpc to handle slpc status code
coding style changes (Paulo)
Removed WARN_ON for checking msb of gtt address of
shared gem obj. (ChrisW)
host2guc_action to i915_guc_action change.(Sagar)
Updating SLPC enabled status. (Sagar)
v2: Commit message update. (David)
v3: Rebase.
v4: Added DRM_INFO message when SLPC is enabled.
Reviewed-by: David Weinehall
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_slpc.c | 29 +
drivers/gpu/drm/i915/intel_slpc.h | 14 ++
2 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_slpc.c
b/drivers/gpu/drm/i915/intel_slpc.c
index 67236a1..eb3358a 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -26,6 +26,32 @@
#include "i915_drv.h"
#include "intel_guc.h"
+static void host2guc_slpc(struct drm_i915_private *dev_priv, u32 *data, u32
len)
+{
+ int ret = i915_guc_action(&dev_priv->guc, data, len);
+
+ if (!ret) {
+ ret = I915_READ(SOFT_SCRATCH(1));
+ ret &= SLPC_EVENT_STATUS_MASK;
+ }
+
+ if (ret)
+ DRM_ERROR("event 0x%x status %d\n", (data[1] >> 8), ret);
+}
+
+static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
+{
+ u32 data[4];
+ u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+ data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+ data[1] = SLPC_EVENT(SLPC_EVENT_RESET, 2);
+ data[2] = shared_data_gtt_offset;
+ data[3] = 0;
+
+ host2guc_slpc(dev_priv, data, 4);
+}
+
static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
{
enum slpc_platform_sku platform_sku;
@@ -131,4 +157,7 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
void intel_slpc_enable(struct drm_i915_private *dev_priv)
{
+ host2guc_slpc_reset(dev_priv);
+ DRM_INFO("SLPC Enabled\n");
+ dev_priv->guc.slpc.enabled = true;
}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h
b/drivers/gpu/drm/i915/intel_slpc.h
index 6cdbc96..a96f365 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -24,6 +24,20 @@
#ifndef _INTEL_SLPC_H_
#define _INTEL_SLPC_H_
+enum slpc_event_id {
+ SLPC_EVENT_RESET = 0,
+ SLPC_EVENT_SHUTDOWN = 1,
+ SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
+ SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
+ SLPC_EVENT_FLIP_COMPLETE = 4,
+ SLPC_EVENT_QUERY_TASK_STATE = 5,
+ SLPC_EVENT_PARAMETER_SET = 6,
+ SLPC_EVENT_PARAMETER_UNSET = 7,
+};
+
+#define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
+#define SLPC_EVENT_STATUS_MASK 0xFF
+
enum slpc_global_state {
SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
SLPC_GLOBAL_STATE_INITIALIZING = 1,
--
1.9.1
___
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[Intel-gfx] [PATCH v4 13/25] drm/i915/slpc: Send shutdown event
From: Tom O'Rourke
Send SLPC shutdown event during disable, suspend, and reset
operations. Sending shutdown event while already shutdown
is OK.
v1: Return void instead of ignored error code (Paulo)
Removed WARN_ON for checking msb of gtt address of
shared gem obj. (ChrisW)
Added SLPC state update during disable, suspend and reset.
Changed semantics of reset. It is supposed to just disable. (Sagar)
Reviewed-by: David Weinehall
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 6 --
drivers/gpu/drm/i915/intel_slpc.c | 17 +
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2211f7b..70e08d9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6691,7 +6691,7 @@ void intel_suspend_gt_powersave(struct drm_i915_private
*dev_priv)
void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
{
if (intel_slpc_enabled()) {
- /* TODO: Set SLPC enabled forcefully */
+ dev_priv->guc.slpc.enabled = true;
intel_disable_gt_powersave(dev_priv);
} else {
dev_priv->rps.enabled = true; /* force disabling */
@@ -6704,8 +6704,10 @@ void intel_sanitize_gt_powersave(struct drm_i915_private
*dev_priv)
void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
{
if (intel_slpc_enabled()) {
- if (!intel_slpc_active(dev_priv))
+ if (!intel_slpc_active(dev_priv)) {
+ dev_priv->guc.slpc.enabled = false;
return;
+ }
} else if (!READ_ONCE(dev_priv->rps.enabled))
return;
diff --git a/drivers/gpu/drm/i915/intel_slpc.c
b/drivers/gpu/drm/i915/intel_slpc.c
index eb3358a..f9d32c1 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -52,6 +52,19 @@ static void host2guc_slpc_reset(struct drm_i915_private
*dev_priv)
host2guc_slpc(dev_priv, data, 4);
}
+static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv)
+{
+ u32 data[4];
+ u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+ data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+ data[1] = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2);
+ data[2] = shared_data_gtt_offset;
+ data[3] = 0;
+
+ host2guc_slpc(dev_priv, data, 4);
+}
+
static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
{
enum slpc_platform_sku platform_sku;
@@ -149,10 +162,14 @@ void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
void intel_slpc_suspend(struct drm_i915_private *dev_priv)
{
+ host2guc_slpc_shutdown(dev_priv);
+ dev_priv->guc.slpc.enabled = false;
}
void intel_slpc_disable(struct drm_i915_private *dev_priv)
{
+ host2guc_slpc_shutdown(dev_priv);
+ dev_priv->guc.slpc.enabled = false;
}
void intel_slpc_enable(struct drm_i915_private *dev_priv)
--
1.9.1
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[Intel-gfx] [PATCH v4 10/25] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
From: Tom O'Rourke
SLPC shared data is used to pass information
to/from SLPC in GuC firmware.
For Skylake, platform sku type and slice count
are identified from device id and fuse values.
Support for other platforms needs to be added.
v1: Update for SLPC interface version 2015.2.4
intel_slpc_active() returns 1 if slpc initialized (Paulo)
change default host_os to "Windows"
Spelling fixes (Sagar Kamble and Nick Hoath)
Added WARN for checking if upper 32bits of GTT offset
of shared object are zero. (ChrisW)
Changed function call from gem_allocate/release_guc_obj to
i915_guc_allocate/release_gem_obj. (Sagar)
Updated commit message and moved POWER_PLAN and POWER_SOURCE
definition from later patch. (Akash)
Add struct_mutex locking while allocating/releasing slpc shared
object. This was caught by CI BAT. Adding SLPC state variable
to determine if it is active as it not just dependent on shared
data setup.
Rebase with guc_allocate_vma related changes.
v2: WARN_ON for platform_sku validity and space changes. (David)
Checkpatch update.
v3: Fixing WARNING in igt@drv_module_reload_basic found in trybot BAT
with SLPC Enabled.
v4: Updated support for GuC v9.
Reviewed-by: David Weinehall
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_drv.h | 7 ++-
drivers/gpu/drm/i915/intel_guc.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 6 ++-
drivers/gpu/drm/i915/intel_slpc.c | 88 ++
drivers/gpu/drm/i915/intel_slpc.h | 99 +++
5 files changed, 199 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6f9480b..99b19ae 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1714,7 +1714,12 @@ bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv, enum dpio_phy phy,
static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
{
- return 0;
+ int ret = 0;
+
+ if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
+ ret = 1;
+
+ return ret;
}
/* intel_pm.c */
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 83dec66..6e24e60 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -145,6 +145,8 @@ struct intel_guc {
uint64_t submissions[I915_NUM_ENGINES];
uint32_t last_seqno[I915_NUM_ENGINES];
+
+ struct intel_slpc slpc;
};
static inline int intel_slpc_enabled(void)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d187066..2211f7b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6656,7 +6656,8 @@ void intel_init_gt_powersave(struct drm_i915_private
*dev_priv)
void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
{
- if (intel_slpc_enabled())
+ if (intel_slpc_enabled() &&
+ dev_priv->guc.slpc.vma)
intel_slpc_cleanup(dev_priv);
else if (IS_VALLEYVIEW(dev_priv))
valleyview_cleanup_gt_powersave(dev_priv);
@@ -6746,7 +6747,8 @@ void intel_enable_gt_powersave(struct drm_i915_private
*dev_priv)
mutex_lock(&dev_priv->rps.hw_lock);
- if (intel_slpc_enabled()) {
+ if (intel_slpc_enabled() &&
+ dev_priv->guc.slpc.vma) {
gen9_enable_rc6(dev_priv);
intel_slpc_enable(dev_priv);
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_slpc.c
b/drivers/gpu/drm/i915/intel_slpc.c
index be9e84c..67236a1 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -22,15 +22,103 @@
*
*/
#include
+#include
#include "i915_drv.h"
#include "intel_guc.h"
+static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
+{
+ enum slpc_platform_sku platform_sku;
+
+ if (IS_SKL_ULX(dev_priv))
+ platform_sku = SLPC_PLATFORM_SKU_ULX;
+ else if (IS_SKL_ULT(dev_priv))
+ platform_sku = SLPC_PLATFORM_SKU_ULT;
+ else
+ platform_sku = SLPC_PLATFORM_SKU_DT;
+
+ WARN_ON(platform_sku > 0xFF);
+
+ return platform_sku;
+}
+
+static unsigned int slpc_get_slice_count(struct drm_i915_private *dev_priv)
+{
+ unsigned int slice_count = 1;
+
+ if (IS_SKYLAKE(dev_priv))
+ slice_count = INTEL_INFO(dev_priv)->slice_total;
+
+ return slice_count;
+}
+
+static void slpc_shared_data_init(struct drm_i915_private *dev_priv)
+{
+ struct drm_i915_gem_object *obj;
+ struct page *page;
+ struct slpc_shared_data *data;
+ u64 msr_value;
+
+ if (!dev_priv->guc.slpc.vma)
+ return;
+
+ obj = dev_priv->guc.slpc.vma->obj;
+
+ page = i915_gem_object_get_page(obj, 0);
+ i
[Intel-gfx] [PATCH v4 06/25] drm/i915/slpc: Sanitize SLPC version
From: Tom O'Rourke
The SLPC interface has changed and could continue to
change. Only GuC versions known to be compatible are
supported here.
On Skylake, GuC firmware v9 is supported. Other
platforms and versions can be added here later.
v1: Updated with modified sanitize_slpc_option in earlier patch.
v2-v3: Rebase.
v4: Updated support for GuC firmware v9.
Reviewed-by: David Weinehall
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_guc_loader.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index fb38018..500b0b6 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -146,6 +146,8 @@ static void direct_interrupts_to_guc(struct
drm_i915_private *dev_priv)
void sanitize_slpc_option(struct drm_i915_private *dev_priv)
{
+ struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
+
/* Handle default case */
if (i915.enable_slpc < 0)
i915.enable_slpc = HAS_SLPC(dev_priv);
@@ -161,6 +163,9 @@ void sanitize_slpc_option(struct drm_i915_private *dev_priv)
/* slpc requires guc submission */
if (!i915.enable_guc_submission)
i915.enable_slpc = 0;
+
+ if (IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 9))
+ i915.enable_slpc = 0;
}
static u32 get_gttype(struct drm_i915_private *dev_priv)
--
1.9.1
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[Intel-gfx] [PATCH v4 11/25] drm/i915/slpc: Update sysfs/debugfs interfaces for frequency parameters
From: Tom O'Rourke
When SLPC is controlling requested frequency, the rps.cur_freq
value is not used to make the frequency request.
Requested frequency from register RPNSWREQ has the value
most recently requested by SLPC firmware. Adding new sysfs
interface gt_req_freq_mhz to know this value.
SLPC requested value needs to be made available to i915 without
reading RPNSWREQ.
v1: Replace HAS_SLPC with intel_slpc_active (Paulo)
Avoid magic numbers (Nick)
Use a function for repeated code (Jon)
v2: Add "SLPC Active" to i915_frequency_info output and
don't update cur_freq as it is driver internal request. (Chris)
v3: Removing sysfs interface gt_req_freq_mhz out of this patch
for proper division of functionality. (Sagar)
v4: idle_freq, boost_freq are also not used with SLPC.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 24 ++--
drivers/gpu/drm/i915/i915_sysfs.c | 3 +++
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 3fde507..7641778 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1083,6 +1083,9 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
intel_runtime_pm_get(dev_priv);
+ if (intel_slpc_active(dev_priv))
+ seq_puts(m, "SLPC Active\n");
+
if (IS_GEN5(dev_priv)) {
u16 rgvswctl = I915_READ16(MEMSWCTL);
u16 rgvstat = I915_READ16(MEMSTAT_ILK);
@@ -1250,15 +1253,21 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
seq_printf(m, "Max overclocked frequency: %dMHz\n",
intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
- seq_printf(m, "Current freq: %d MHz\n",
- intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
+ if (!intel_slpc_active(dev_priv)) {
+ seq_printf(m, "Current freq: %d MHz\n",
+ intel_gpu_freq(dev_priv,
+ dev_priv->rps.cur_freq));
+ seq_printf(m, "Idle freq: %d MHz\n",
+ intel_gpu_freq(dev_priv,
+ dev_priv->rps.idle_freq));
+ seq_printf(m, "Boost freq: %d MHz\n",
+ intel_gpu_freq(dev_priv,
+ dev_priv->rps.boost_freq));
+ }
+
seq_printf(m, "Actual freq: %d MHz\n", cagf);
- seq_printf(m, "Idle freq: %d MHz\n",
- intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
seq_printf(m, "Min freq: %d MHz\n",
intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
- seq_printf(m, "Boost freq: %d MHz\n",
- intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
seq_printf(m, "Max freq: %d MHz\n",
intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
seq_printf(m,
@@ -2315,6 +2324,9 @@ static int i915_rps_boost_info(struct seq_file *m, void
*data)
struct drm_device *dev = &dev_priv->drm;
struct drm_file *file;
+ if (intel_slpc_active(dev_priv))
+ return -ENODEV;
+
seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
seq_printf(m, "GPU busy? %s [%x]\n",
yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index 1012eee..020d64e 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -299,6 +299,9 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
{
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+ if (intel_slpc_active(dev_priv))
+ return -ENODEV;
+
return snprintf(buf, PAGE_SIZE, "%d\n",
intel_gpu_freq(dev_priv,
dev_priv->rps.cur_freq));
--
1.9.1
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[Intel-gfx] [PATCH v4 14/25] drm/i915/slpc: Add slpc_status enum values
From: Tom O'Rourke
v1: fix whitespace (Sagar)
v2-v3: Rebase.
v4: Updated with GuC firmware v9.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_slpc.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h
b/drivers/gpu/drm/i915/intel_slpc.h
index a96f365..4838e1e 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -24,6 +24,32 @@
#ifndef _INTEL_SLPC_H_
#define _INTEL_SLPC_H_
+enum slpc_status {
+ SLPC_STATUS_OK = 0,
+ SLPC_STATUS_ERROR = 1,
+ SLPC_STATUS_ILLEGAL_COMMAND = 2,
+ SLPC_STATUS_INVALID_ARGS = 3,
+ SLPC_STATUS_INVALID_PARAMS = 4,
+ SLPC_STATUS_INVALID_DATA = 5,
+ SLPC_STATUS_OUT_OF_RANGE = 6,
+ SLPC_STATUS_NOT_SUPPORTED = 7,
+ SLPC_STATUS_NOT_IMPLEMENTED = 8,
+ SLPC_STATUS_NO_DATA = 9,
+ SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
+ SLPC_STATUS_REGISTER_LOCKED = 11,
+ SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
+ SLPC_STATUS_VALUE_ALREADY_SET = 13,
+ SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
+ SLPC_STATUS_VALUE_NOT_CHANGED = 15,
+ SLPC_STATUS_MEMIO_ERROR = 16,
+ SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 17,
+ SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 18,
+ SLPC_STATUS_NO_EVENT_QUEUED = 19,
+ SLPC_STATUS_OUT_OF_SPACE = 20,
+ SLPC_STATUS_TIMEOUT = 21,
+ SLPC_STATUS_NO_LOCK = 22,
+};
+
enum slpc_event_id {
SLPC_EVENT_RESET = 0,
SLPC_EVENT_SHUTDOWN = 1,
--
1.9.1
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[Intel-gfx] [PATCH v4 18/25] drm/i915/slpc: Add i915_slpc_info to debugfs
From: Tom O'Rourke
i915_slpc_info shows the contents of SLPC shared data
parsed into text format.
v1: Reformat slpc info (Radek)
squashed query task state info
in slpc info, kunmap before seq_print (Paulo)
return void instead of ignored return value (Paulo)
Avoid magic numbers and use local variables (Jon Bloomfield)
Removed WARN_ON for checking msb of gtt address of
shared gem obj. (ChrisW)
Moved definition of power plan and power source to earlier
patch in the series.
drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
(Akash)
v2-v3: Rebase.
v4: Updated with GuC firmware v9.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 197
drivers/gpu/drm/i915/intel_slpc.c | 19
drivers/gpu/drm/i915/intel_slpc.h | 1 +
3 files changed, 217 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a51fee3..9efae32 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1324,6 +1324,202 @@ static const struct file_operations i915_slpc_dcc_fops
= {
.llseek = seq_lseek
};
+static int i915_slpc_info(struct seq_file *m, void *unused)
+{
+ struct drm_info_node *node = m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_gem_object *obj;
+ struct page *page;
+ void *pv = NULL;
+ struct slpc_shared_data data;
+ struct slpc_task_state_data *task_data;
+ int i, value;
+ enum slpc_global_state global_state;
+ enum slpc_platform_sku platform_sku;
+ enum slpc_power_plan power_plan;
+ enum slpc_power_source power_source;
+
+ if (!intel_slpc_active(dev_priv))
+ return -ENODEV;
+
+ obj = dev_priv->guc.slpc.vma->obj;
+ if (obj) {
+ intel_slpc_query_task_state(dev_priv);
+
+ page = i915_gem_object_get_page(obj, 0);
+ if (page)
+ pv = kmap_atomic(page);
+ }
+
+ if (pv) {
+ data = *(struct slpc_shared_data *) pv;
+ kunmap_atomic(pv);
+
+ seq_printf(m, "shared data size: %d\n", data.shared_data_size);
+
+ global_state = (enum slpc_global_state) data.global_state;
+ seq_printf(m, "global state: %d (", global_state);
+ switch (global_state) {
+ case SLPC_GLOBAL_STATE_NOT_RUNNING:
+ seq_puts(m, "not running)\n");
+ break;
+ case SLPC_GLOBAL_STATE_INITIALIZING:
+ seq_puts(m, "initializing)\n");
+ break;
+ case SLPC_GLOBAL_STATE_RESETTING:
+ seq_puts(m, "resetting)\n");
+ break;
+ case SLPC_GLOBAL_STATE_RUNNING:
+ seq_puts(m, "running)\n");
+ break;
+ case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
+ seq_puts(m, "shutting down)\n");
+ break;
+ case SLPC_GLOBAL_STATE_ERROR:
+ seq_puts(m, "error)\n");
+ break;
+ default:
+ seq_puts(m, "unknown)\n");
+ break;
+ }
+
+ platform_sku = (enum slpc_platform_sku)
+ data.platform_info.platform_sku;
+ seq_printf(m, "sku: %d (", platform_sku);
+ switch (platform_sku) {
+ case SLPC_PLATFORM_SKU_UNDEFINED:
+ seq_puts(m, "undefined)\n");
+ break;
+ case SLPC_PLATFORM_SKU_ULX:
+ seq_puts(m, "ULX)\n");
+ break;
+ case SLPC_PLATFORM_SKU_ULT:
+ seq_puts(m, "ULT)\n");
+ break;
+ case SLPC_PLATFORM_SKU_T:
+ seq_puts(m, "T)\n");
+ break;
+ case SLPC_PLATFORM_SKU_MOBL:
+ seq_puts(m, "Mobile)\n");
+ break;
+ case SLPC_PLATFORM_SKU_DT:
+ seq_puts(m, "DT)\n");
+ break;
+ case SLPC_PLATFORM_SKU_UNKNOWN:
+ default:
+ seq_puts(m, "unknown)\n");
+ break;
+ }
+ seq_printf(m, "slice count: %d\n",
+ data.platform_info.slice_count);
+
+ seq_printf(m, "power plan/source: 0x%x\n\tplan:\t",
+ data.platform_info.power_plan_source);
+ power_plan = (enum slpc_power_plan) SLPC_POWER_PLAN(
+ data.platform_info
[Intel-gfx] [PATCH v4 23/25] drm/i915/slpc: Keep RP SW Mode enabled while disabling rps
With SLPC, only RP SW Mode control should be left enabled by i915.
Else, SLPC requests through through RPNSWREQ will not be granted.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 70e08d9..d06c9bb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5064,7 +5064,13 @@ static void gen9_disable_rc6(struct drm_i915_private
*dev_priv)
static void gen9_disable_rps(struct drm_i915_private *dev_priv)
{
- I915_WRITE(GEN6_RP_CONTROL, 0);
+ uint32_t rp_ctl = 0;
+
+ /* RP SW Mode Control will be needed for SLPC, Hence not clearing.*/
+ if (i915.enable_slpc)
+ rp_ctl = I915_READ(GEN6_RP_CONTROL) & GEN6_RP_MEDIA_MODE_MASK;
+
+ I915_WRITE(GEN6_RP_CONTROL, rp_ctl);
dev_priv->rps.enabled = false;
}
--
1.9.1
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[Intel-gfx] [PATCH v4 15/25] drm/i915/slpc: Add parameter unset/set/get functions
From: Tom O'Rourke
Add slpc_param_id enum values.
Add events for setting/unsetting parameters.
v1: Use host2guc_slpc
update slcp_param_id enum values for SLPC 2015.2.4
return void instead of ignored error code (Paulo)
v2: Checkpatch update.
v3: Rebase.
v4: Updated with GuC firmware v9.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_slpc.c | 102 ++
drivers/gpu/drm/i915/intel_slpc.h | 32 +++-
2 files changed, 133 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_slpc.c
b/drivers/gpu/drm/i915/intel_slpc.c
index f9d32c1..8ab5d9f 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -65,6 +65,108 @@ static void host2guc_slpc_shutdown(struct drm_i915_private
*dev_priv)
host2guc_slpc(dev_priv, data, 4);
}
+static void host2guc_slpc_set_param(struct drm_i915_private *dev_priv,
+ enum slpc_param_id id, u32 value)
+{
+ u32 data[4];
+
+ data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+ data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2);
+ data[2] = (u32) id;
+ data[3] = value;
+
+ host2guc_slpc(dev_priv, data, 4);
+}
+
+static void host2guc_slpc_unset_param(struct drm_i915_private *dev_priv,
+ enum slpc_param_id id)
+{
+ u32 data[3];
+
+ data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+ data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1);
+ data[2] = (u32) id;
+
+ host2guc_slpc(dev_priv, data, 3);
+}
+
+void intel_slpc_unset_param(struct drm_i915_private *dev_priv,
+ enum slpc_param_id id)
+{
+ struct drm_i915_gem_object *obj;
+ struct page *page;
+ struct slpc_shared_data *data = NULL;
+
+ obj = dev_priv->guc.slpc.vma->obj;
+ if (obj) {
+ page = i915_gem_object_get_page(obj, 0);
+ if (page)
+ data = kmap_atomic(page);
+ }
+
+ if (data) {
+ data->override_parameters_set_bits[id >> 5]
+ &= (~(1 << (id % 32)));
+ data->override_parameters_values[id] = 0;
+ kunmap_atomic(data);
+
+ host2guc_slpc_unset_param(dev_priv, id);
+ }
+}
+
+void intel_slpc_set_param(struct drm_i915_private *dev_priv,
+ enum slpc_param_id id,
+ u32 value)
+{
+ struct drm_i915_gem_object *obj;
+ struct page *page;
+ struct slpc_shared_data *data = NULL;
+
+ obj = dev_priv->guc.slpc.vma->obj;
+ if (obj) {
+ page = i915_gem_object_get_page(obj, 0);
+ if (page)
+ data = kmap_atomic(page);
+ }
+
+ if (data) {
+ data->override_parameters_set_bits[id >> 5]
+ |= (1 << (id % 32));
+ data->override_parameters_values[id] = value;
+ kunmap_atomic(data);
+
+ host2guc_slpc_set_param(dev_priv, id, value);
+ }
+}
+
+void intel_slpc_get_param(struct drm_i915_private *dev_priv,
+ enum slpc_param_id id,
+ int *overriding, u32 *value)
+{
+ struct drm_i915_gem_object *obj;
+ struct page *page;
+ struct slpc_shared_data *data = NULL;
+ u32 bits;
+
+ obj = dev_priv->guc.slpc.vma->obj;
+ if (obj) {
+ page = i915_gem_object_get_page(obj, 0);
+ if (page)
+ data = kmap_atomic(page);
+ }
+
+ if (data) {
+ if (overriding) {
+ bits = data->override_parameters_set_bits[id >> 5];
+ *overriding = (0 != (bits & (1 << (id % 32;
+ }
+ if (value)
+ *value = data->override_parameters_values[id];
+
+ kunmap_atomic(data);
+ }
+}
+
static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
{
enum slpc_platform_sku platform_sku;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h
b/drivers/gpu/drm/i915/intel_slpc.h
index 4838e1e..b0a627d 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -64,6 +64,29 @@ enum slpc_event_id {
#define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
#define SLPC_EVENT_STATUS_MASK 0xFF
+enum slpc_param_id {
+ SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
+ SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
+ SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
+ SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
+ SLPC_PARAM_TASK_ENABLE_DCC = 4,
+ SLPC_PARAM_TASK_DISABLE_DCC = 5,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
+ SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
+ SLPC_PARAM_GLOBAL_M
[Intel-gfx] [PATCH v4 17/25] drm/i915/slpc: Add enable/disable debugfs for slpc
From: Tom O'Rourke
Adds debugfs hooks for each slpc task.
The enable/disable debugfs files are
i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc.
Each of these can take the values:
"default", "enabled", or "disabled"
v1: update for SLPC v2015.2.4
dfps and turbo merged and renamed "gtperf"
ibc split out and renamed "balancer"
Avoid magic numbers (Jon Bloomfield)
v2-v3: Rebase.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 252
drivers/gpu/drm/i915/intel_slpc.h | 5 +
2 files changed, 257 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index c8aa525..a51fee3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1075,6 +1075,255 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
i915_next_seqno_get, i915_next_seqno_set,
"0x%llx\n");
+static int slpc_enable_disable_get(struct drm_device *dev, u64 *val,
+ enum slpc_param_id enable_id,
+ enum slpc_param_id disable_id)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int override_enable, override_disable;
+ u32 value_enable, value_disable;
+ int ret = 0;
+
+ if (!intel_slpc_active(dev_priv)) {
+ ret = -ENODEV;
+ } else if (val) {
+ intel_slpc_get_param(dev_priv, enable_id, &override_enable,
+&value_enable);
+ intel_slpc_get_param(dev_priv, disable_id, &override_disable,
+&value_disable);
+
+ /* set the output value:
+ * 0: default
+ * 1: enabled
+ * 2: disabled
+ * 3: unknown (should not happen)
+ */
+ if (override_disable && (value_disable == 1))
+ *val = SLPC_PARAM_TASK_DISABLED;
+ else if (override_enable && (value_enable == 1))
+ *val = SLPC_PARAM_TASK_ENABLED;
+ else if (!override_enable && !override_disable)
+ *val = SLPC_PARAM_TASK_DEFAULT;
+ else
+ *val = SLPC_PARAM_TASK_UNKNOWN;
+
+ } else {
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+ enum slpc_param_id enable_id,
+ enum slpc_param_id disable_id)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int ret = 0;
+
+ if (!intel_slpc_active(dev_priv)) {
+ ret = -ENODEV;
+ } else if (val == SLPC_PARAM_TASK_DEFAULT) {
+ /* set default */
+ intel_slpc_unset_param(dev_priv, enable_id);
+ intel_slpc_unset_param(dev_priv, disable_id);
+ } else if (val == SLPC_PARAM_TASK_ENABLED) {
+ /* set enable */
+ intel_slpc_set_param(dev_priv, enable_id, 1);
+ intel_slpc_unset_param(dev_priv, disable_id);
+ } else if (val == SLPC_PARAM_TASK_DISABLED) {
+ /* set disable */
+ intel_slpc_set_param(dev_priv, disable_id, 1);
+ intel_slpc_unset_param(dev_priv, enable_id);
+ } else {
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static void slpc_param_show(struct seq_file *m, enum slpc_param_id enable_id,
+ enum slpc_param_id disable_id)
+{
+ struct drm_device *dev = m->private;
+ const char *status;
+ u64 val;
+ int ret;
+
+ ret = slpc_enable_disable_get(dev, &val, enable_id, disable_id);
+
+ if (ret) {
+ seq_printf(m, "error %d\n", ret);
+ } else {
+ switch (val) {
+ case SLPC_PARAM_TASK_DEFAULT:
+ status = "default\n";
+ break;
+
+ case SLPC_PARAM_TASK_ENABLED:
+ status = "enabled\n";
+ break;
+
+ case SLPC_PARAM_TASK_DISABLED:
+ status = "disabled\n";
+ break;
+
+ default:
+ status = "unknown\n";
+ break;
+ }
+
+ seq_puts(m, status);
+ }
+}
+
+static int slpc_param_write(struct seq_file *m, const char __user *ubuf,
+ size_t len, enum slpc_param_id enable_id,
+ enum slpc_param_id disable_id)
+{
+ struct drm_device *dev = m->private;
+ u64 val;
+ int ret = 0;
+ char buf[10];
+
+ if (len >= sizeof(buf))
+ ret = -EINVAL;
+ else if (copy_from_user(buf, ubuf, len))
+ ret = -EFAULT
[Intel-gfx] [PATCH v4 19/25] drm/i915/slpc: Add Broxton SLPC support
From: Tom O'Rourke
Adds has_slpc to broxton info and adds broxton firmware version check
to sanitize_slpc_option.
v1: Adjusted slpc version check for major version 8.
Added message if version mismatch happens for easier debug. (Sagar)
v2-v3: Rebase.
v4: Commit message update.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e678051..60a5eb5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -342,6 +342,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_ddi = 1,
.has_fpga_dbg = 1,
.has_fbc = 1,
+ .has_slpc = 1,
.has_pooled_eu = 0,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 2dda771..f0101a8 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -164,8 +164,11 @@ void sanitize_slpc_option(struct drm_i915_private
*dev_priv)
if (!i915.enable_guc_submission)
i915.enable_slpc = 0;
- if (IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 9))
+ if ((IS_SKYLAKE(dev_priv) && (guc_fw->guc_fw_major_found != 9))
+|| (IS_BROXTON(dev_priv) && (guc_fw->guc_fw_major_found != 9))) {
+ DRM_INFO("SLPC not supported with current GuC firmware\n");
i915.enable_slpc = 0;
+ }
}
static u32 get_gttype(struct drm_i915_private *dev_priv)
--
1.9.1
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[Intel-gfx] [PATCH v4 16/25] drm/i915/slpc: Add slpc support for max/min freq
From: Tom O'Rourke
Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.
v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
Replace HAS_SLPC with intel_slpc_active() (Paulo)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 18 ++
drivers/gpu/drm/i915/i915_sysfs.c | 18 ++
2 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 7641778..c8aa525 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4873,6 +4873,15 @@ i915_max_freq_set(void *data, u64 val)
dev_priv->rps.max_freq_softlimit = val;
+ if (intel_slpc_active(dev_priv)) {
+ intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv, val));
+ }
+
intel_set_rps(dev_priv, val);
mutex_unlock(&dev_priv->rps.hw_lock);
@@ -4928,6 +4937,15 @@ i915_min_freq_set(void *data, u64 val)
dev_priv->rps.min_freq_softlimit = val;
+ if (intel_slpc_active(dev_priv)) {
+ intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv, val));
+ }
+
intel_set_rps(dev_priv, val);
mutex_unlock(&dev_priv->rps.hw_lock);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index 020d64e..ab161ca 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -391,6 +391,15 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
dev_priv->rps.max_freq_softlimit = val;
+ if (intel_slpc_active(dev_priv)) {
+ intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv, val));
+ }
+
val = clamp_t(int, dev_priv->rps.cur_freq,
dev_priv->rps.min_freq_softlimit,
dev_priv->rps.max_freq_softlimit);
@@ -444,6 +453,15 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
dev_priv->rps.min_freq_softlimit = val;
+ if (intel_slpc_active(dev_priv)) {
+ intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv, val));
+ }
+
val = clamp_t(int, dev_priv->rps.cur_freq,
dev_priv->rps.min_freq_softlimit,
dev_priv->rps.max_freq_softlimit);
--
1.9.1
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[Intel-gfx] [PATCH v4 21/25] drm/i915/slpc: Update freq min/max softlimits
v2: Removing checks for vma obj and kmap_atomic validity. (Chris)
v3: Rebase.
v4: Updated to make sure SLPC enable keeps min/max freq softlimits
unchanged after initializing once. (Chris)
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_slpc.c | 47 +++
drivers/gpu/drm/i915/intel_slpc.h | 1 +
2 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_slpc.c
b/drivers/gpu/drm/i915/intel_slpc.c
index 60b3aaf..1a3a515 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -269,6 +269,7 @@ void intel_slpc_init(struct drm_i915_private *dev_priv)
}
slpc_shared_data_init(dev_priv);
+ dev_priv->guc.slpc.first_enable = false;
}
void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
@@ -279,6 +280,8 @@ void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
mutex_lock(&dev_priv->drm.struct_mutex);
i915_vma_unpin_and_release(&guc->slpc.vma);
mutex_unlock(&dev_priv->drm.struct_mutex);
+
+ dev_priv->guc.slpc.first_enable = false;
}
void intel_slpc_suspend(struct drm_i915_private *dev_priv)
@@ -339,4 +342,48 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv)
intel_slpc_set_param(dev_priv,
SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
0);
+
+ if (!dev_priv->guc.slpc.first_enable) {
+ struct drm_i915_gem_object *obj;
+ void *pv = NULL;
+ struct slpc_shared_data data;
+
+ obj = dev_priv->guc.slpc.vma->obj;
+ intel_slpc_query_task_state(dev_priv);
+
+ pv = kmap_atomic(i915_gem_object_get_page(obj, 0));
+ data = *(struct slpc_shared_data *) pv;
+ kunmap_atomic(pv);
+
+ /*
+* TODO: Define separate variables for slice and unslice
+* frequencies for driver state variable.
+*/
+ dev_priv->rps.max_freq_softlimit =
+ data.task_state_data.freq_unslice_max;
+ dev_priv->rps.min_freq_softlimit =
+ data.task_state_data.freq_unslice_min;
+
+ dev_priv->rps.max_freq_softlimit *= GEN9_FREQ_SCALER;
+ dev_priv->rps.min_freq_softlimit *= GEN9_FREQ_SCALER;
+ dev_priv->guc.slpc.first_enable = true;
+ } else {
+ /* Ask SLPC to operate within min/max freq softlimits */
+ intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv,
+ dev_priv->rps.max_freq_softlimit));
+ intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv,
+ dev_priv->rps.max_freq_softlimit));
+ intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv,
+ dev_priv->rps.min_freq_softlimit));
+ intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+(u32) intel_gpu_freq(dev_priv,
+ dev_priv->rps.min_freq_softlimit));
+ }
}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h
b/drivers/gpu/drm/i915/intel_slpc.h
index 8436965..9a8602a 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -189,6 +189,7 @@ struct slpc_shared_data {
struct intel_slpc {
struct i915_vma *vma;
bool enabled;
+ bool first_enable;
};
/* intel_slpc.c */
--
1.9.1
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[Intel-gfx] [PATCH v4 25/25] drm/i915: Mark GuC load status as PENDING in i915_drm_resume_early
This will help avoid Host to GuC actions being called till GuC gets
loaded during i915_drm_resume.
v2-v3: Rebase.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1f677a9..aeb97ac 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1627,6 +1627,7 @@ static int i915_drm_resume(struct drm_device *dev)
static int i915_drm_resume_early(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
struct pci_dev *pdev = dev_priv->drm.pdev;
int ret;
@@ -1684,6 +1685,12 @@ static int i915_drm_resume_early(struct drm_device *dev)
DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
ret);
+ /*
+* Mark GuC FW load status as PENDING to avoid any Host to GuC actions
+* invoked till GuC gets loaded in i915_drm_resume.
+ */
+ guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
+
intel_uncore_early_sanitize(dev_priv, true);
if (IS_BROXTON(dev_priv)) {
--
1.9.1
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[Intel-gfx] [PATCH v4 22/25] drm/i915/slpc: Check GuC load status in SLPC active check
SLPC status has to be linked with GuC load status to make sure
SLPC actions get invoked when GuC is loaded.
v2: Space and function return convention issues. (Deepak)
v3: Rebase.
v4: Limiting the check for SLPC actions.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_drv.h | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 99b19ae..64950bc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1714,8 +1714,12 @@ bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv, enum dpio_phy phy,
static inline int intel_slpc_active(struct drm_i915_private *dev_priv)
{
+ struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
int ret = 0;
+ if (guc_fw->guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
+ return ret;
+
if (dev_priv->guc.slpc.vma && dev_priv->guc.slpc.enabled)
ret = 1;
--
1.9.1
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[Intel-gfx] [PATCH v4 20/25] drm/i915/slpc: Only Enable GTPERF, Disable DCC, Balancer, IBC, FPS Stall
v1: Updated tasks and frequency post reset.
Added DFPS param update for MAX_FPS and FPS Stall.
v2-v3: Rebase.
v4: Updated with GuC firmware v9.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/intel_slpc.c | 41 +
drivers/gpu/drm/i915/intel_slpc.h | 5 +
3 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9efae32..522e49d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1114,7 +1114,7 @@ static int slpc_enable_disable_get(struct drm_device
*dev, u64 *val,
return ret;
}
-static int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+int slpc_enable_disable_set(struct drm_device *dev, u64 val,
enum slpc_param_id enable_id,
enum slpc_param_id disable_id)
{
diff --git a/drivers/gpu/drm/i915/intel_slpc.c
b/drivers/gpu/drm/i915/intel_slpc.c
index 4683294..60b3aaf 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -295,7 +295,48 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
void intel_slpc_enable(struct drm_i915_private *dev_priv)
{
+ u64 val;
+
host2guc_slpc_reset(dev_priv);
DRM_INFO("SLPC Enabled\n");
dev_priv->guc.slpc.enabled = true;
+
+ /* Enable only GTPERF task, Disable others */
+ val = SLPC_PARAM_TASK_ENABLED;
+ slpc_enable_disable_set(&dev_priv->drm, val,
+ SLPC_PARAM_TASK_ENABLE_GTPERF,
+ SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+ val = SLPC_PARAM_TASK_DISABLED;
+ slpc_enable_disable_set(&dev_priv->drm, val,
+ SLPC_PARAM_TASK_ENABLE_BALANCER,
+ SLPC_PARAM_TASK_DISABLE_BALANCER);
+
+ slpc_enable_disable_set(&dev_priv->drm, val,
+ SLPC_PARAM_TASK_ENABLE_DCC,
+ SLPC_PARAM_TASK_DISABLE_DCC);
+
+ intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING,
+0);
+
+ intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS,
+0);
+
+ intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING,
+0);
+
+ intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO,
+0);
+
+ intel_slpc_set_param(dev_priv,
+SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE,
+0);
+
+ intel_slpc_set_param(dev_priv,
+
SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
+0);
}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h
b/drivers/gpu/drm/i915/intel_slpc.h
index cc43194..8436965 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -206,4 +206,9 @@ void intel_slpc_get_param(struct drm_i915_private *dev_priv,
enum slpc_param_id id,
int *overriding, u32 *value);
void intel_slpc_query_task_state(struct drm_i915_private *dev_priv);
+
+/* i915_debugfs.c */
+int slpc_enable_disable_set(struct drm_device *dev, u64 val,
+ enum slpc_param_id enable_id,
+ enum slpc_param_id disable_id);
#endif
--
1.9.1
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[Intel-gfx] [PATCH v4 24/25] drm/i915: Add sysfs interface to know the HW requested frequency
With SLPC, user can read this value to know SLPC requested frequency.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_sysfs.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index ab161ca..7bff742 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -307,6 +307,32 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
dev_priv->rps.cur_freq));
}
+static ssize_t gt_req_freq_mhz_show(struct device *kdev,
+ struct device_attribute *attr, char *buf)
+{
+ struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+ u32 reqf;
+
+ if (!intel_runtime_pm_get_if_in_use(dev_priv))
+ return -ENODEV;
+
+ reqf = I915_READ(GEN6_RPNSWREQ);
+ intel_runtime_pm_put(dev_priv);
+
+ if (IS_GEN9(dev_priv))
+ reqf >>= 23;
+ else {
+ reqf &= ~GEN6_TURBO_DISABLE;
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+ reqf >>= 24;
+ else
+ reqf >>= 25;
+ }
+ reqf = intel_gpu_freq(dev_priv, reqf);
+
+ return snprintf(buf, PAGE_SIZE, "%d\n", reqf);
+}
+
static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct
device_attribute *attr, char *buf)
{
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
@@ -481,6 +507,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL);
static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
+static DEVICE_ATTR(gt_req_freq_mhz, S_IRUGO, gt_req_freq_mhz_show, NULL);
static DEVICE_ATTR(gt_boost_freq_mhz, S_IRUGO, gt_boost_freq_mhz_show,
gt_boost_freq_mhz_store);
static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show,
gt_max_freq_mhz_store);
static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show,
gt_min_freq_mhz_store);
@@ -513,6 +540,7 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct
device_attribute *attr
static const struct attribute *gen6_attrs[] = {
&dev_attr_gt_act_freq_mhz.attr,
&dev_attr_gt_cur_freq_mhz.attr,
+ &dev_attr_gt_req_freq_mhz.attr,
&dev_attr_gt_boost_freq_mhz.attr,
&dev_attr_gt_max_freq_mhz.attr,
&dev_attr_gt_min_freq_mhz.attr,
--
1.9.1
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Re: [Intel-gfx] [PATCH] drm: squash lines for simple wrapper functions
On Wed, 07 Sep 2016, Masahiro Yamada wrote:
> Remove unneeded variables and assignments.
>
> Signed-off-by: Masahiro Yamada
...
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 95ddd56..59d029d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1361,13 +1361,7 @@ void i915_driver_unload(struct drm_device *dev)
>
> static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
> {
> - int ret;
> -
> - ret = i915_gem_open(dev, file);
> - if (ret)
> - return ret;
> -
> - return 0;
> + return i915_gem_open(dev, file);
> }
Seems to me the whole function could be replaced by a direct use of
i915_gem_open().
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH] tools/intel_guc_logger: Utility for capturing GuC firmware logs in a file
On Wed, Sep 07, 2016 at 01:40:27PM +0530, Goel, Akash wrote:
>
>
> On 9/6/2016 9:22 PM, Tvrtko Ursulin wrote:
> >
> >On 06/09/16 16:33, Goel, Akash wrote:
> >>On 9/6/2016 6:47 PM, Tvrtko Ursulin wrote:
> >>>Hi,
> >>>
> >>>On 06/09/16 11:43, akash.g...@intel.com wrote:
> From: Akash Goel
>
> This patch provides a test utility which helps capture GuC firmware
> logs and
> then dump them to file.
> The logs are pulled from a debugfs file
> '/sys/kernel/debug/dri/guc_log' and
> stored into a file '/tmp/guc_log_dump.dat', the name of the output
> file can
> be changed through a command line argument.
>
> The utility goes into an infinite loop where it waits for the arrival
> of new
> logs and as soon as new set of logs are produced it captures them in
> its local
> buffer which is then flushed out to the file on disk.
> Any time when logging needs to be ended, User can stop this utility
> (CTRL+C).
>
> Before entering into a loop, it first discards whatever logs are
> present in
> the debugfs file.
> This way User can first launch this utility and then start a
> workload/activity
> for which GuC firmware logs are to be actually captured and keep
> running the
> utility for as long as its needed, like once the workload is over this
> utility
> can be forcefully stopped.
>
> If the logging wasn't enabled on GuC side by the Driver at boot time,
> utility
> will first enable the logging and later on when it is stopped (CTRL+C)
> it will
> also pause the logging on GuC side.
>
> Signed-off-by: Akash Goel
> ---
> tools/Makefile.sources | 1 +
> tools/intel_guc_logger.c | 441
> +++
> 2 files changed, 442 insertions(+)
> create mode 100644 tools/intel_guc_logger.c
>
> diff --git a/tools/Makefile.sources b/tools/Makefile.sources
> index 2bb6c8e..be58871 100644
> --- a/tools/Makefile.sources
> +++ b/tools/Makefile.sources
> @@ -19,6 +19,7 @@ tools_prog_lists =\
> intel_gpu_time\
> intel_gpu_top\
> intel_gtt\
> +intel_guc_logger\
> intel_infoframes\
> intel_l3_parity\
> intel_lid\
> diff --git a/tools/intel_guc_logger.c b/tools/intel_guc_logger.c
> new file mode 100644
> index 000..92172fa
> --- /dev/null
> +++ b/tools/intel_guc_logger.c
> @@ -0,0 +1,441 @@
> +
> +#define _GNU_SOURCE /* For using O_DIRECT */
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "igt.h"
> +
> +#define MB(x) ((uint64_t)(x) * 1024 * 1024)
> +#ifndef PAGE_SIZE
> + #define PAGE_SIZE 4096
> +#endif
> +#define SUBBUF_SIZE (19*PAGE_SIZE)
> +/* Need large buffering from logger side to hide the DISK IO latency,
> Driver
> + * can only store 8 snapshots of GuC log buffer in relay.
> + */
> +#define NUM_SUBBUFS 100
> +
> +#define RELAY_FILE_NAME "guc_log"
> +#define CONTROL_FILE_NAME "i915_guc_log_control"
> +
> +char *read_buffer;
> +char *out_filename;
> +int poll_timeout = 2; /* by default 2ms timeout */
> +pthread_mutex_t mutex;
> +pthread_t flush_thread;
> +int verbosity_level = 3; /* by default capture logs at max
> verbosity */
> +uint32_t produced, consumed;
> +uint64_t total_bytes_written;
> +int num_buffers = NUM_SUBBUFS;
> +int relay_fd, outfile_fd = -1;
> +bool stop_logging, discard_oldlogs;
> +uint32_t test_duration, max_filesize;
> +pthread_cond_t underflow_cond, overflow_cond;
> +
> +static void guc_log_control(bool enable_logging)
> +{
> +int control_fd;
> +char data[19];
> +uint64_t val;
> +int ret;
> +
> +control_fd = igt_debugfs_open(CONTROL_FILE_NAME, O_WRONLY);
> +if (control_fd < 0)
> +igt_assert_f(0, "Couldn't open the guc log control file");
> +
> +val = enable_logging ? ((verbosity_level << 4) | 0x1) : 0;
> +
> +snprintf(data, sizeof(data), "0x%" PRIx64, val);
> +ret = write(control_fd, data, strlen(data) + 1);
> >>>
> >>>Minor: It looks safe like it is but something like below would maybe be
> >>>more robust?
> >>>
> >>>ret = snprintf(data, sizeof(data), "0x%" PRIx64, val);
> >>>igt_assert(ret > 2 && ret < sizeof(data));
> >>
> >>ok will add, but possibility of failure will be really remote here.
> >>but igt_assert(ret > 0) should suffice.
> >
> >Yes there is no possibility for failure as it stands, just more robust
> >implementati
[Intel-gfx] [PATCH] drm: squash lines for simple wrapper functions
Remove unneeded variables and assignments.
Signed-off-by: Masahiro Yamada
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c| 6 +-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c| 6 +-
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 20
drivers/gpu/drm/drm_dp_mst_topology.c | 7 ++-
drivers/gpu/drm/i915/i915_drv.c | 8 +---
drivers/gpu/drm/qxl/qxl_draw.c| 7 ++-
drivers/gpu/drm/qxl/qxl_release.c | 7 ++-
drivers/gpu/drm/radeon/cik.c | 6 +-
drivers/gpu/drm/radeon/r100.c | 6 +-
drivers/gpu/drm/radeon/r600.c | 6 +-
11 files changed, 17 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index b818461..0d5307a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5854,11 +5854,7 @@ static int gfx_v8_0_set_clockgating_state(void *handle,
static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
{
- u32 rptr;
-
- rptr = ring->adev->wb.wb[ring->rptr_offs];
-
- return rptr;
+ return ring->adev->wb.wb[ring->rptr_offs];
}
static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index a64715d..b165c78 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -190,12 +190,8 @@ out:
*/
static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
{
- u32 rptr;
-
/* XXX check if swapping is necessary on BE */
- rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
-
- return rptr;
+ return ring->adev->wb.wb[ring->rptr_offs] >> 2;
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 653ce5e..cf253b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -335,12 +335,8 @@ out:
*/
static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
{
- u32 rptr;
-
/* XXX check if swapping is necessary on BE */
- rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
-
- return rptr;
+ return ring->adev->wb.wb[ring->rptr_offs] >> 2;
}
/**
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 48030f0..d37d112 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -1073,34 +1073,22 @@ void analogix_dp_set_lane3_link_training(struct
analogix_dp_device *dp,
u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
{
- u32 reg;
-
- reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
- return reg;
+ return readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
}
u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
{
- u32 reg;
-
- reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
- return reg;
+ return readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
}
u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
{
- u32 reg;
-
- reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
- return reg;
+ return readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
}
u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
{
- u32 reg;
-
- reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
- return reg;
+ return readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
}
void analogix_dp_reset_macro(struct analogix_dp_device *dp)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 04e4571..302bdcb 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -737,16 +737,13 @@ static void drm_dp_mst_put_payload_id(struct
drm_dp_mst_topology_mgr *mgr,
static bool check_txmsg_state(struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_sideband_msg_tx *txmsg)
{
- bool ret;
-
/*
* All updates to txmsg->state are protected by mgr->qlock, and the two
* cases we check here are terminal states. For those the barriers
* provided by the wake_up/wait_event pair are enough.
*/
- ret = (txmsg->state == DRM_DP_SIDEBAND_TX_RX ||
- txmsg->state == DRM_DP_SIDEBAND_TX_TIMEOUT);
- return ret;
+ return txmsg->state == DRM_DP_SIDEBAND_TX_RX ||
+ txmsg->state == DRM_DP_SIDEBAND_TX_TIMEOUT;
}
static int drm_dp_mst_wait_tx_reply(struct drm_dp_mst_branch *mstb,
diff --gi
[Intel-gfx] [PATCH] drm: Move property validation to a helper.
Property lifetimes are equal to the device lifetime, so the separate
drm_property_find is not needed. The pointer can be retrieved from
the properties member, which saves us some locking and a extra lookup.
The lifetime for properties is until the device is destroyed, which
happens late in the device unload path.
Testcase: kms_properties
Suggested-by: Ville Syrjälä
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/drm_atomic.c| 16
drivers/gpu/drm/drm_crtc_internal.h | 2 ++
drivers/gpu/drm/drm_mode_object.c | 31 ---
3 files changed, 22 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index fac156c43506..8bec8466781c 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -1609,7 +1609,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
struct drm_crtc_state *crtc_state;
unsigned plane_mask;
int ret = 0;
- unsigned int i, j, k;
+ unsigned int i, j;
/* disallow for drivers not supporting atomic: */
if (!drm_core_check_feature(dev, DRIVER_ATOMIC))
@@ -1691,19 +1691,11 @@ retry:
goto out;
}
- for (k = 0; k < obj->properties->count; k++)
- if (obj->properties->properties[k]->base.id ==
prop_id)
- break;
-
- if (k == obj->properties->count) {
- ret = -EINVAL;
- goto out;
- }
-
- prop = drm_property_find(dev, prop_id);
+ prop = drm_mode_obj_find_prop_id(obj, prop_id);
if (!prop) {
drm_mode_object_unreference(obj);
- ret = -ENOENT;
+ DRM_DEBUG_ATOMIC("cannot find property %u for
obj %u\n", prop_id, obj_id);
+ ret = -EINVAL;
goto out;
}
diff --git a/drivers/gpu/drm/drm_crtc_internal.h
b/drivers/gpu/drm/drm_crtc_internal.h
index a3622644bccf..444e609078cc 100644
--- a/drivers/gpu/drm/drm_crtc_internal.h
+++ b/drivers/gpu/drm/drm_crtc_internal.h
@@ -115,6 +115,8 @@ int drm_mode_object_get_properties(struct drm_mode_object
*obj, bool atomic,
uint32_t __user *prop_ptr,
uint64_t __user *prop_values,
uint32_t *arg_count_props);
+struct drm_property *drm_mode_obj_find_prop_id(struct drm_mode_object *obj,
+ uint32_t prop_id);
/* IOCTL */
diff --git a/drivers/gpu/drm/drm_mode_object.c
b/drivers/gpu/drm/drm_mode_object.c
index 6edda8382a4c..9f17085b1fdd 100644
--- a/drivers/gpu/drm/drm_mode_object.c
+++ b/drivers/gpu/drm/drm_mode_object.c
@@ -372,14 +372,25 @@ out:
return ret;
}
+struct drm_property *drm_mode_obj_find_prop_id(struct drm_mode_object *obj,
+ uint32_t prop_id)
+{
+ int i;
+
+ for (i = 0; i < obj->properties->count; i++)
+ if (obj->properties->properties[i]->base.id == prop_id)
+ return obj->properties->properties[i];
+
+ return NULL;
+}
+
int drm_mode_obj_set_property_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
struct drm_mode_obj_set_property *arg = data;
struct drm_mode_object *arg_obj;
- struct drm_mode_object *prop_obj;
struct drm_property *property;
- int i, ret = -EINVAL;
+ int ret = -EINVAL;
struct drm_mode_object *ref;
if (!drm_core_check_feature(dev, DRIVER_MODESET))
@@ -392,23 +403,13 @@ int drm_mode_obj_set_property_ioctl(struct drm_device
*dev, void *data,
ret = -ENOENT;
goto out;
}
- if (!arg_obj->properties)
- goto out_unref;
-
- for (i = 0; i < arg_obj->properties->count; i++)
- if (arg_obj->properties->properties[i]->base.id == arg->prop_id)
- break;
- if (i == arg_obj->properties->count)
+ if (!arg_obj->properties)
goto out_unref;
- prop_obj = drm_mode_object_find(dev, arg->prop_id,
- DRM_MODE_OBJECT_PROPERTY);
- if (!prop_obj) {
- ret = -ENOENT;
+ property = drm_mode_obj_find_prop_id(arg_obj, arg->prop_id);
+ if (!property)
goto out_unref;
- }
- property = obj_to_property(prop_obj);
if (!drm_property_change_valid_get(property, arg->value, &ref))
goto out_unref;
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lis
[Intel-gfx] [PATCH 2/6] drm/i915: Pass atomic state to intel_audio_codec_enable
drm_select_eld requires mode_config.mutex and connection_mutex
because it looks at the connector list and at the legacy encoders.
This is not required, because when we call audio_codec_enable we know
which connector it was called for, so pass the state.
This also removes having to look at crtc->config.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_audio.c | 15 +--
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_dp.c| 11 ++-
drivers/gpu/drm/i915/intel_drv.h | 4 +++-
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
5 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index 6c70a5bfd7d8..fd49c32c514c 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -480,15 +480,18 @@ static void ilk_audio_codec_enable(struct drm_connector
*connector,
/**
* intel_audio_codec_enable - Enable the audio codec for HD audio
* @intel_encoder: encoder on which to enable audio
+ * @crtc_state: pointer to the current crtc state.
+ * @conn_state: pointer to the current connector state.
*
* The enable sequences may only be performed after enabling the transcoder and
* port, and after completed link training.
*/
-void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
+void intel_audio_codec_enable(struct intel_encoder *intel_encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
struct drm_encoder *encoder = &intel_encoder->base;
- struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
- const struct drm_display_mode *adjusted_mode =
&crtc->config->base.adjusted_mode;
+ const struct drm_display_mode *adjusted_mode =
&crtc_state->base.adjusted_mode;
struct drm_connector *connector;
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -496,8 +499,8 @@ void intel_audio_codec_enable(struct intel_encoder
*intel_encoder)
struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
enum port port = intel_dig_port->port;
- connector = drm_select_eld(encoder);
- if (!connector)
+ connector = conn_state->connector;
+ if (!connector || !connector->eld[0])
return;
DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
@@ -508,7 +511,7 @@ void intel_audio_codec_enable(struct intel_encoder
*intel_encoder)
/* ELD Conn_Type */
connector->eld[5] &= ~(3 << 2);
- if (intel_crtc_has_dp_encoder(crtc->config))
+ if (intel_crtc_has_dp_encoder(crtc_state))
connector->eld[5] |= (1 << 2);
connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ce369c2e96a0..e3aed539d932 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1783,7 +1783,7 @@ static void intel_enable_ddi(struct intel_encoder
*intel_encoder,
if (intel_crtc->config->has_audio) {
intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
- intel_audio_codec_enable(intel_encoder);
+ intel_audio_codec_enable(intel_encoder, pipe_config,
conn_state);
}
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e4a25668ccf6..1402387a47a3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2654,7 +2654,8 @@ static void intel_dp_enable_port(struct intel_dp
*intel_dp,
}
static void intel_enable_dp(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config)
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state)
{
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
struct drm_device *dev = encoder->base.dev;
@@ -2696,7 +2697,7 @@ static void intel_enable_dp(struct intel_encoder *encoder,
if (pipe_config->has_audio) {
DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
pipe_name(pipe));
- intel_audio_codec_enable(encoder);
+ intel_audio_codec_enable(encoder, pipe_config, conn_state);
}
}
@@ -2706,7 +2707,7 @@ static void g4x_enable_dp(struct intel_encoder *encoder,
{
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
- intel_enable_dp(encoder, pipe_config);
+ intel_enable_dp(encoder, pipe_config, conn_state);
intel_edp_backlight_on(intel_dp);
}
@@ -2843,7 +2844,7 @@ static void vlv_pre_enable_dp(struct intel_encoder
*encoder,
{
vlv_phy_pre_encoder_enable(encoder);
- intel_enable_dp(encoder, pipe_config)
[Intel-gfx] [PATCH 5/6] drm/i915: Pass atomic state to verify_connector_state
This gets rid of a warning that the connectors are used without locking
when doing a nonblocking modeset.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index cd1f3fec5547..7a66a4252ee0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13479,11 +13479,15 @@ static void verify_wm_state(struct drm_crtc *crtc,
}
static void
-verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
+verify_connector_state(struct drm_device *dev,
+ struct drm_atomic_state *state,
+ struct drm_crtc *crtc)
{
struct drm_connector *connector;
+ struct drm_connector_state *old_conn_state;
+ int i;
- drm_for_each_connector(connector, dev) {
+ for_each_connector_in_state(state, connector, old_conn_state, i) {
struct drm_encoder *encoder = connector->encoder;
struct drm_connector_state *state = connector->state;
@@ -13691,15 +13695,16 @@ verify_shared_dpll_state(struct drm_device *dev,
struct drm_crtc *crtc,
static void
intel_modeset_verify_crtc(struct drm_crtc *crtc,
-struct drm_crtc_state *old_state,
-struct drm_crtc_state *new_state)
+ struct drm_atomic_state *state,
+ struct drm_crtc_state *old_state,
+ struct drm_crtc_state *new_state)
{
if (!needs_modeset(new_state) &&
!to_intel_crtc_state(new_state)->update_pipe)
return;
verify_wm_state(crtc, new_state);
- verify_connector_state(crtc->dev, crtc);
+ verify_connector_state(crtc->dev, state, crtc);
verify_crtc_state(crtc, old_state, new_state);
verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
}
@@ -13715,10 +13720,11 @@ verify_disabled_dpll_state(struct drm_device *dev)
}
static void
-intel_modeset_verify_disabled(struct drm_device *dev)
+intel_modeset_verify_disabled(struct drm_device *dev,
+ struct drm_atomic_state *state)
{
verify_encoder_state(dev);
- verify_connector_state(dev, NULL);
+ verify_connector_state(dev, state, NULL);
verify_disabled_dpll_state(dev);
}
@@ -14373,7 +14379,7 @@ static void intel_atomic_commit_tail(struct
drm_atomic_state *state)
if (IS_SKYLAKE(dev_priv) && !skl_can_enable_sagv(state))
skl_disable_sagv(dev_priv);
- intel_modeset_verify_disabled(dev);
+ intel_modeset_verify_disabled(dev, state);
}
/* Complete the events for pipes that have now been disabled */
@@ -14425,7 +14431,7 @@ static void intel_atomic_commit_tail(struct
drm_atomic_state *state)
if (put_domains[i])
modeset_put_power_domains(dev_priv, put_domains[i]);
- intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
+ intel_modeset_verify_crtc(crtc, state, old_crtc_state,
crtc->state);
}
if (IS_SKYLAKE(dev_priv) && intel_state->modeset &&
--
2.7.4
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[Intel-gfx] [PATCH 0/6] drm/i915: Enable support for nonblocking modesets.
This fixes a few places where we emit warnings on nonblocking modesets, then flips the switch and enables it. Tested on my BDW and SKL, but SKL still fails on the detection whether nonblocking modesets are supported with some WM related issue. Fixing this and support for atomic connector properties are the last things required for flipping the switch and always setting DRIVER_ATOMIC. Maarten Lankhorst (6): drm/i915: Convert intel_hdmi to use atomic state drm/i915: Pass atomic state to intel_audio_codec_enable drm/edid: Remove drm_select_eld drm/i915: Update atomic modeset state synchronously drm/i915: Pass atomic state to verify_connector_state drm/i915: Enable support for nonblocking modeset drivers/gpu/drm/drm_edid.c | 26 --- drivers/gpu/drm/i915/intel_audio.c | 15 ++- drivers/gpu/drm/i915/intel_ddi.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 48 +- drivers/gpu/drm/i915/intel_dp.c | 11 drivers/gpu/drm/i915/intel_drv.h | 4 ++- drivers/gpu/drm/i915/intel_hdmi.c| 50 include/drm/drm_edid.h | 1 - 8 files changed, 64 insertions(+), 93 deletions(-) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/6] drm/edid: Remove drm_select_eld
The only user was i915, which is now gone.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/drm_edid.c | 26 --
include/drm/drm_edid.h | 1 -
2 files changed, 27 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 50541324a4ab..ce0caccfe384 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3581,32 +3581,6 @@ int drm_av_sync_delay(struct drm_connector *connector,
EXPORT_SYMBOL(drm_av_sync_delay);
/**
- * drm_select_eld - select one ELD from multiple HDMI/DP sinks
- * @encoder: the encoder just changed display mode
- *
- * It's possible for one encoder to be associated with multiple HDMI/DP sinks.
- * The policy is now hard coded to simply use the first HDMI/DP sink's ELD.
- *
- * Return: The connector associated with the first HDMI/DP sink that has ELD
- * attached to it.
- */
-struct drm_connector *drm_select_eld(struct drm_encoder *encoder)
-{
- struct drm_connector *connector;
- struct drm_device *dev = encoder->dev;
-
- WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
- WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
-
- drm_for_each_connector(connector, dev)
- if (connector->encoder == encoder && connector->eld[0])
- return connector;
-
- return NULL;
-}
-EXPORT_SYMBOL(drm_select_eld);
-
-/**
* drm_detect_hdmi_monitor - detect whether monitor is HDMI
* @edid: monitor EDID information
*
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index 919933d1beb4..f5278f813b61 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -327,7 +327,6 @@ int drm_edid_to_sad(struct edid *edid, struct cea_sad
**sads);
int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb);
int drm_av_sync_delay(struct drm_connector *connector,
const struct drm_display_mode *mode);
-struct drm_connector *drm_select_eld(struct drm_encoder *encoder);
#ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
int drm_load_edid_firmware(struct drm_connector *connector);
--
2.7.4
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[Intel-gfx] [PATCH 6/6] drm/i915: Enable support for nonblocking modeset
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7a66a4252ee0..9fe8873d82cb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14494,10 +14494,6 @@ static void intel_atomic_track_fbs(struct
drm_atomic_state *state)
* This function commits a top-level state object that has been validated
* with drm_atomic_helper_check().
*
- * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
- * nonblocking commits are only safe for pure plane updates. Everything else
- * should work though.
- *
* RETURNS
* Zero for success or -errno.
*/
@@ -14509,11 +14505,6 @@ static int intel_atomic_commit(struct drm_device *dev,
struct drm_i915_private *dev_priv = to_i915(dev);
int ret = 0;
- if (intel_state->modeset && nonblock) {
- DRM_DEBUG_KMS("nonblocking commit for modeset not yet
implemented.\n");
- return -EINVAL;
- }
-
ret = drm_atomic_helper_setup_commit(state, nonblock);
if (ret)
return ret;
--
2.7.4
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[Intel-gfx] [PATCH 4/6] drm/i915: Update atomic modeset state synchronously
All of this state should be updated as soon as possible. It shouldn't be
done later because then future updates may not depend on it.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index b79a20ff2dbe..cd1f3fec5547 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14315,14 +14315,8 @@ static void intel_atomic_commit_tail(struct
drm_atomic_state *state)
drm_atomic_helper_wait_for_dependencies(state);
- if (intel_state->modeset) {
- memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
- sizeof(intel_state->min_pixclk));
- dev_priv->active_crtcs = intel_state->active_crtcs;
- dev_priv->atomic_cdclk_freq = intel_state->cdclk;
-
+ if (intel_state->modeset)
intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
- }
for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -14532,6 +14526,13 @@ static int intel_atomic_commit(struct drm_device *dev,
intel_shared_dpll_commit(state);
intel_atomic_track_fbs(state);
+ if (intel_state->modeset) {
+ memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
+ sizeof(intel_state->min_pixclk));
+ dev_priv->active_crtcs = intel_state->active_crtcs;
+ dev_priv->atomic_cdclk_freq = intel_state->cdclk;
+ }
+
if (nonblock)
queue_work(system_unbound_wq, &state->commit_work);
else
--
2.7.4
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[Intel-gfx] [PATCH 1/6] drm/i915: Convert intel_hdmi to use atomic state
This is the last connector still looking at crtc->config. Fix this.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_hdmi.c | 48 +--
1 file changed, 21 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 1a116a6a1817..40f6e1b47eb3 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -975,7 +975,9 @@ static void intel_hdmi_get_config(struct intel_encoder
*encoder,
pipe_config->lane_count = 4;
}
-static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
+static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state)
{
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
@@ -991,21 +993,20 @@ static void g4x_enable_hdmi(struct intel_encoder *encoder,
{
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
u32 temp;
temp = I915_READ(intel_hdmi->hdmi_reg);
temp |= SDVO_ENABLE;
- if (crtc->config->has_audio)
+ if (pipe_config->has_audio)
temp |= SDVO_AUDIO_ENABLE;
I915_WRITE(intel_hdmi->hdmi_reg, temp);
POSTING_READ(intel_hdmi->hdmi_reg);
- if (crtc->config->has_audio)
- intel_enable_hdmi_audio(encoder);
+ if (pipe_config->has_audio)
+ intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
}
static void ibx_enable_hdmi(struct intel_encoder *encoder,
@@ -1040,8 +1041,8 @@ static void ibx_enable_hdmi(struct intel_encoder *encoder,
* FIXME: BSpec says this should be done at the end of
* of the modeset sequence, so not sure if this isn't too soon.
*/
- if (crtc->config->pipe_bpp > 24 &&
- crtc->config->pixel_multiplier > 1) {
+ if (pipe_config->pipe_bpp > 24 &&
+ pipe_config->pixel_multiplier > 1) {
I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
POSTING_READ(intel_hdmi->hdmi_reg);
@@ -1055,8 +1056,8 @@ static void ibx_enable_hdmi(struct intel_encoder *encoder,
POSTING_READ(intel_hdmi->hdmi_reg);
}
- if (crtc->config->has_audio)
- intel_enable_hdmi_audio(encoder);
+ if (pipe_config->has_audio)
+ intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
}
static void cpt_enable_hdmi(struct intel_encoder *encoder,
@@ -1073,7 +1074,7 @@ static void cpt_enable_hdmi(struct intel_encoder *encoder,
temp = I915_READ(intel_hdmi->hdmi_reg);
temp |= SDVO_ENABLE;
- if (crtc->config->has_audio)
+ if (pipe_config->has_audio)
temp |= SDVO_AUDIO_ENABLE;
/*
@@ -1086,7 +1087,7 @@ static void cpt_enable_hdmi(struct intel_encoder *encoder,
* 4. enable HDMI clock gating
*/
- if (crtc->config->pipe_bpp > 24) {
+ if (pipe_config->pipe_bpp > 24) {
I915_WRITE(TRANS_CHICKEN1(pipe),
I915_READ(TRANS_CHICKEN1(pipe)) |
TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
@@ -1098,7 +1099,7 @@ static void cpt_enable_hdmi(struct intel_encoder *encoder,
I915_WRITE(intel_hdmi->hdmi_reg, temp);
POSTING_READ(intel_hdmi->hdmi_reg);
- if (crtc->config->pipe_bpp > 24) {
+ if (pipe_config->pipe_bpp > 24) {
temp &= ~SDVO_COLOR_FORMAT_MASK;
temp |= HDMI_COLOR_FORMAT_12bpc;
@@ -1110,8 +,8 @@ static void cpt_enable_hdmi(struct intel_encoder *encoder,
~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
}
- if (crtc->config->has_audio)
- intel_enable_hdmi_audio(encoder);
+ if (pipe_config->has_audio)
+ intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
}
static void vlv_enable_hdmi(struct intel_encoder *encoder,
@@ -1178,9 +1179,7 @@ static void g4x_disable_hdmi(struct intel_encoder
*encoder,
struct intel_crtc_state *old_crtc_state,
struct drm_connector_state *old_conn_state)
{
- struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
-
- if (crtc->config->has_audio)
+ if (old_crtc_state->has_audio)
intel_audio_codec_disable(encoder);
intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
@@ -1190,9 +1189,7 @@ static void pch_disable_hdmi(struct intel_encoder
*encoder,
struct intel_crtc_state *old_crtc_state,
struct drm_connector_state *old_conn_state)
{
- struct intel
Re: [Intel-gfx] [PATCH] drm: Move property validation to a helper.
Op 07-09-16 om 10:58 schreef Maarten Lankhorst:
> Property lifetimes are equal to the device lifetime, so the separate
> drm_property_find is not needed. The pointer can be retrieved from
> the properties member, which saves us some locking and a extra lookup.
>
> The lifetime for properties is until the device is destroyed, which
> happens late in the device unload path.
>
> Testcase: kms_properties
> Suggested-by: Ville Syrjälä
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/drm_atomic.c| 16
> drivers/gpu/drm/drm_crtc_internal.h | 2 ++
> drivers/gpu/drm/drm_mode_object.c | 31 ---
> 3 files changed, 22 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index fac156c43506..8bec8466781c 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -1609,7 +1609,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
> struct drm_crtc_state *crtc_state;
> unsigned plane_mask;
> int ret = 0;
> - unsigned int i, j, k;
> + unsigned int i, j;
>
> /* disallow for drivers not supporting atomic: */
> if (!drm_core_check_feature(dev, DRIVER_ATOMIC))
> @@ -1691,19 +1691,11 @@ retry:
> goto out;
> }
>
> - for (k = 0; k < obj->properties->count; k++)
> - if (obj->properties->properties[k]->base.id ==
> prop_id)
> - break;
> -
> - if (k == obj->properties->count) {
> - ret = -EINVAL;
> - goto out;
> - }
> -
> - prop = drm_property_find(dev, prop_id);
> + prop = drm_mode_obj_find_prop_id(obj, prop_id);
> if (!prop) {
> drm_mode_object_unreference(obj);
> - ret = -ENOENT;
> + DRM_DEBUG_ATOMIC("cannot find property %u for
> obj %u\n", prop_id, obj_id);
> + ret = -EINVAL;
This needs to stay -ENOENT it seems. kms_atomic testcase relies on it.
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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm: squash lines for simple wrapper functions
== Series Details == Series: drm: squash lines for simple wrapper functions URL : https://patchwork.freedesktop.org/series/12096/ State : warning == Summary == Series 12096v1 drm: squash lines for simple wrapper functions http://patchwork.freedesktop.org/api/1.0/series/12096/revisions/1/mbox/ Test drv_module_reload_basic: pass -> SKIP (fi-skl-6260u) Test gem_exec_gttfill: Subgroup basic: pass -> SKIP (fi-snb-2600) Test kms_pipe_crc_basic: Subgroup nonblocking-crc-pipe-c: pass -> SKIP (fi-hsw-4770r) Subgroup suspend-read-crc-pipe-b: pass -> SKIP (fi-hsw-4770k) fi-bdw-5557u total:252 pass:233 dwarn:2 dfail:1 fail:1 skip:15 fi-bsw-n3050 total:252 pass:203 dwarn:1 dfail:1 fail:1 skip:46 fi-byt-n2820 total:252 pass:206 dwarn:2 dfail:1 fail:2 skip:41 fi-hsw-4770k total:252 pass:225 dwarn:2 dfail:1 fail:1 skip:23 fi-hsw-4770r total:252 pass:221 dwarn:2 dfail:1 fail:1 skip:27 fi-ivb-3520m total:252 pass:217 dwarn:2 dfail:1 fail:1 skip:31 fi-skl-6260u total:252 pass:233 dwarn:2 dfail:1 fail:1 skip:15 fi-skl-6700k total:252 pass:219 dwarn:3 dfail:1 fail:1 skip:28 fi-snb-2520m total:252 pass:204 dwarn:2 dfail:1 fail:2 skip:43 fi-snb-2600 total:252 pass:204 dwarn:2 dfail:1 fail:1 skip:44 Results at /archive/results/CI_IGT_test/Patchwork_2480/ 980cf7a5d9c420afbaf52a339a2005339f9f8319 drm-intel-nightly: 2016y-09m-06d-18h-01m-33s UTC integration manifest 7c846de drm: squash lines for simple wrapper functions ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] tools/intel_guc_logger: Utility for capturing GuC firmware logs in a file
On 07/09/16 09:44, Chris Wilson wrote:
On Wed, Sep 07, 2016 at 01:40:27PM +0530, Goel, Akash wrote:
On 9/6/2016 9:22 PM, Tvrtko Ursulin wrote:
[snip]
+while (!stop_logging)
+{
+if (test_duration && (igt_seconds_elapsed(&start) >
test_duration)) {
If you agree to allow no poll period the this would not work right? In
that case you would need to use alarm(2) or something.
Can calculate the timeout value for poll call as,
if (poll_timeout < 0) {
timeout = test_duration - igt_seconds_elapsed(&start))
}
My point was that with indefinite poll loop will not run if there is not
log data so timeout will not work implemented like this.
I understood your concern in first place but probably didn't put
forth my point clearly.
For more clarity, this is how think it can be addressed.
--- a/tools/intel_guc_logger.c
+++ b/tools/intel_guc_logger.c
@@ -370,6 +370,8 @@ int main(int argc, char **argv)
{
struct pollfd relay_poll_fd;
struct timespec start={};
+ uint32_t time_elapsed;
+ int timeout;
int nfds;
int ret;
@@ -395,10 +397,17 @@ int main(int argc, char **argv)
while (!stop_logging)
{
- if (test_duration && (igt_seconds_elapsed(&start) >
test_duration)) {
- igt_debug("Ran for stipulated %d seconds, exit now\n",
test_duration);
- stop_logging = true;
- break;
+ timeout = poll_timeout;
+ if (test_duration) {
+ time_elapsed = igt_seconds_elapsed(&start);
+ if (time_elapsed >= test_duration) {
+ igt_debug("Ran for stipulated %d seconds, exit
now\n", test_duration);
+ stop_logging = true;
+ break;
+ }
+ if (poll_timeout < 0)
+ timeout = (test_duration - time_elapsed) * 1000;
}
/* Wait/poll for the new data to be available, relay doesn't
@@ -412,7 +421,7 @@ int main(int argc, char **argv)
* than a jiffy gap between 2 flush interrupts) and relay runs
* out of sub buffers to store the new logs.
*/
- ret = poll(&relay_poll_fd, nfds, poll_timeout);
+ ret = poll(&relay_poll_fd, nfds, timeout);
if (ret < 0) {
if (errno == EINTR)
break;
So will not do polling with indefinite timeout and adjust the
timeout value as per test's duration.
Does it look ok ?
Since the comment still refers to a kernel bug that you've fixed, it can
just go. The timeout calculation is indeed more simply expressed as
alarm(timeout).
Yes I wrote privately that's especially true since there is already a
handler for SIGINT which would do the right thing for SIGALRM as well. I
don't feel so strongly about this but now that we both think the same
maybe go for the simpler implementation if you don't mind Akash?
And fixing the blocking read() is about 10 lines in the kernel...
Haven't checked but if that is the case, since we are already fixing
relayfs issues, it would be good to do that one as well since it would
simplify the logger. Because if we do it straight away then we know
logger can use it, and if we leave it for later then it gets uglier for
the logger.
But if we cannot make the fix go in the same kernel version (or earlier)
than the GuC logging then I think we don't need to block on that.
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH] tools/intel_guc_logger: Utility for capturing GuC firmware logs in a file
On Wed, Sep 07, 2016 at 10:37:07AM +0100, Tvrtko Ursulin wrote: > > On 07/09/16 09:44, Chris Wilson wrote: > >And fixing the blocking read() is about 10 lines in the kernel... > > Haven't checked but if that is the case, since we are already fixing > relayfs issues, it would be good to do that one as well since it > would simplify the logger. Because if we do it straight away then we > know logger can use it, and if we leave it for later then it gets > uglier for the logger. > > But if we cannot make the fix go in the same kernel version (or > earlier) than the GuC logging then I think we don't need to block on > that. Totally agree. I think the poll() example is more useful anyway, since that is more likely to fit into the event loop of a real client. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 11/14] drm/i915: Fallback to lower link rate and lane count during link training
On Tue, 2016-09-06 at 17:13 -0700, Manasi Navare wrote:
> According to the DisplayPort Spec, in case of Clock Recovery failure
> the link training sequence should fall back to the lower link rate
> followed by lower lane count until CR succeeds.
> On CR success, the sequence proceeds with Channel EQ.
> In case of Channel EQ failures, it should fallback to
> lower link rate and lane count and start the CR phase again.
>
> v2:
> * Add a helper function to return index of requested link rate
> into common_rates array
> * Changed the link rate fallback loop to make use
> of common_rates array (Mika Kahola)
> * Changed INTEL_INFO to INTEL_GEN (David Weinehall)
>
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 125
> +++---
> drivers/gpu/drm/i915/intel_dp.c | 15
> drivers/gpu/drm/i915/intel_dp_link_training.c | 12 ++-
> drivers/gpu/drm/i915/intel_drv.h | 7 +-
> 4 files changed, 145 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 67a6a0b..e38bf4b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1634,19 +1634,18 @@ void intel_ddi_clk_select(struct
> intel_encoder *encoder,
> }
> }
>
> -static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> +static void intel_ddi_pre_enable_edp(struct intel_encoder *encoder,
> int link_rate, uint32_t
> lane_count,
> - struct intel_shared_dpll *pll,
> - bool link_mst)
> + struct intel_shared_dpll *pll)
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> enum port port = intel_ddi_get_encoder_port(encoder);
>
> intel_dp_set_link_params(intel_dp, link_rate, lane_count,
> - link_mst);
> - if (encoder->type == INTEL_OUTPUT_EDP)
> - intel_edp_panel_on(intel_dp);
> + false);
> +
> + intel_edp_panel_on(intel_dp);
>
> intel_ddi_clk_select(encoder, pll);
> intel_prepare_dp_ddi_buffers(encoder);
> @@ -1657,6 +1656,29 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
> intel_dp_stop_link_train(intel_dp);
> }
>
> +static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> + int link_rate, uint32_t
> lane_count,
> + struct intel_shared_dpll *pll,
> + bool link_mst)
> +{
> + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> + struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> + struct intel_shared_dpll_config tmp_pll_config;
> +
> + /* Disable the PLL and obtain the PLL for Link Training
> + * that starts with highest link rate and lane count.
> + */
> + tmp_pll_config = pll->config;
> + pll->funcs.disable(dev_priv, pll);
> + pll->config.crtc_mask = 0;
> +
> + /* If Link Training fails, send a uevent to generate a
> hotplug */
> + if (!(intel_ddi_link_train(intel_dp, link_rate, lane_count,
> link_mst,
> + false)))
> + drm_kms_helper_hotplug_event(encoder->base.dev);
> + pll->config = tmp_pll_config;
> +}
> +
> static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
> bool has_hdmi_sink,
> struct drm_display_mode
> *adjusted_mode,
> @@ -1690,20 +1712,26 @@ static void intel_ddi_pre_enable(struct
> intel_encoder *intel_encoder,
> struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
> int type = intel_encoder->type;
>
> - if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
> + if (type == INTEL_OUTPUT_EDP)
> + intel_ddi_pre_enable_edp(intel_encoder,
> + crtc->config->port_clock,
> + crtc->config->lane_count,
> + crtc->config->shared_dpll);
> +
> + if (type == INTEL_OUTPUT_DP)
> intel_ddi_pre_enable_dp(intel_encoder,
> crtc->config->port_clock,
> crtc->config->lane_count,
> crtc->config->shared_dpll,
> intel_crtc_has_type(crtc-
> >config,
> INTEL_OU
> TPUT_DP_MST));
> - }
> - if (type == INTEL_OUTPUT_HDMI) {
> +
> + if (type == INTEL_OUTPUT_HDMI)
> intel_ddi_pre_enable_hdmi(intel_encoder,
> crtc->config-
> >has_hdmi_sink,
>
[Intel-gfx] [PATCH i-g-t] demo/Makefile.source: Compile intel_sprite_on when HAVE_LIBDRM_INTEL.
Introduced with commit cd86866dec. Signed-off-by: Marius Vlad CC: Robert Foss --- demos/Makefile.sources | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/demos/Makefile.sources b/demos/Makefile.sources index 31f7f83..aea363f 100644 --- a/demos/Makefile.sources +++ b/demos/Makefile.sources @@ -1,7 +1,7 @@ demos_prog_list = \ $(NULL) -HAVE_LIBDRM_INTEL_BIN =\ +LIBDRM_INTEL_BIN = \ intel_sprite_on \ $(NULL) -- 2.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] demo/Makefile.source: Compile intel_sprite_on when HAVE_LIBDRM_INTEL.
Thanks for catching this Marius. Reviewed-by Robert Foss Rob. On 2016-09-07 05:59 AM, Marius Vlad wrote: Introduced with commit cd86866dec. Signed-off-by: Marius Vlad CC: Robert Foss --- demos/Makefile.sources | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/demos/Makefile.sources b/demos/Makefile.sources index 31f7f83..aea363f 100644 --- a/demos/Makefile.sources +++ b/demos/Makefile.sources @@ -1,7 +1,7 @@ demos_prog_list = \ $(NULL) -HAVE_LIBDRM_INTEL_BIN =\ +LIBDRM_INTEL_BIN = \ intel_sprite_on \ $(NULL) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable support for nonblocking modesets.
== Series Details == Series: drm/i915: Enable support for nonblocking modesets. URL : https://patchwork.freedesktop.org/series/12098/ State : success == Summary == Series 12098v1 drm/i915: Enable support for nonblocking modesets. http://patchwork.freedesktop.org/api/1.0/series/12098/revisions/1/mbox/ fi-bdw-5557u total:252 pass:233 dwarn:2 dfail:1 fail:1 skip:15 fi-bsw-n3050 total:252 pass:203 dwarn:1 dfail:1 fail:1 skip:46 fi-byt-n2820 total:252 pass:206 dwarn:2 dfail:1 fail:2 skip:41 fi-hsw-4770r total:252 pass:222 dwarn:2 dfail:1 fail:1 skip:26 fi-ivb-3520m total:252 pass:217 dwarn:2 dfail:1 fail:1 skip:31 fi-skl-6260u total:252 pass:234 dwarn:2 dfail:1 fail:1 skip:14 fi-skl-6700k total:252 pass:219 dwarn:3 dfail:1 fail:1 skip:28 fi-snb-2520m total:252 pass:204 dwarn:2 dfail:1 fail:2 skip:43 fi-snb-2600 total:252 pass:205 dwarn:2 dfail:1 fail:1 skip:43 Results at /archive/results/CI_IGT_test/Patchwork_2481/ 980cf7a5d9c420afbaf52a339a2005339f9f8319 drm-intel-nightly: 2016y-09m-06d-18h-01m-33s UTC integration manifest c4e9529 drm/i915: Enable support for nonblocking modeset 710ad6b drm/i915: Pass atomic state to verify_connector_state 7c9da4f drm/i915: Update atomic modeset state synchronously 12080be drm/edid: Remove drm_select_eld 9c6281c drm/i915: Pass atomic state to intel_audio_codec_enable e5730b4 drm/i915: Convert intel_hdmi to use atomic state ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 1/4] drm/i915/debugfs: Move out pipe CRC code
In preparation to using a generic API in the DRM core for continuous CRC
generation, move the related code out of i915_debugfs.c into a new file.
Eventually, only the Intel-specific code will remain in this new file.
v2: Rebased.
v6: Rebased.
Signed-off-by: Tomeu Vizoso
---
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 886 +--
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 5 +
drivers/gpu/drm/i915/intel_pipe_crc.c | 944 ++
6 files changed, 956 insertions(+), 885 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_pipe_crc.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a7da24640e88..6238f8042426 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -23,7 +23,7 @@ i915-y := i915_drv.o \
intel_runtime_pm.o
i915-$(CONFIG_COMPAT) += i915_ioc32.o
-i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o
+i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o
# GEM code
i915-y += i915_cmd_parser.o \
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 7d7b4d9280e9..d8073cddffeb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -26,19 +26,9 @@
*
*/
-#include
-#include
-#include
#include
-#include
-#include
#include
-#include
-#include
#include "intel_drv.h"
-#include "intel_ringbuffer.h"
-#include
-#include "i915_drv.h"
static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
{
@@ -3401,12 +3391,6 @@ static int i915_drrs_status(struct seq_file *m, void
*unused)
return 0;
}
-struct pipe_crc_info {
- const char *name;
- struct drm_i915_private *dev_priv;
- enum pipe pipe;
-};
-
static int i915_dp_mst_info(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -3436,848 +3420,6 @@ static int i915_dp_mst_info(struct seq_file *m, void
*unused)
return 0;
}
-static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
-{
- struct pipe_crc_info *info = inode->i_private;
- struct drm_i915_private *dev_priv = info->dev_priv;
- struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
-
- if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
- return -ENODEV;
-
- spin_lock_irq(&pipe_crc->lock);
-
- if (pipe_crc->opened) {
- spin_unlock_irq(&pipe_crc->lock);
- return -EBUSY; /* already open */
- }
-
- pipe_crc->opened = true;
- filep->private_data = inode->i_private;
-
- spin_unlock_irq(&pipe_crc->lock);
-
- return 0;
-}
-
-static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
-{
- struct pipe_crc_info *info = inode->i_private;
- struct drm_i915_private *dev_priv = info->dev_priv;
- struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
-
- spin_lock_irq(&pipe_crc->lock);
- pipe_crc->opened = false;
- spin_unlock_irq(&pipe_crc->lock);
-
- return 0;
-}
-
-/* (6 fields, 8 chars each, space separated (5) + '\n') */
-#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
-/* account for \'0' */
-#define PIPE_CRC_BUFFER_LEN(PIPE_CRC_LINE_LEN + 1)
-
-static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
-{
- assert_spin_locked(&pipe_crc->lock);
- return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
- INTEL_PIPE_CRC_ENTRIES_NR);
-}
-
-static ssize_t
-i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
- loff_t *pos)
-{
- struct pipe_crc_info *info = filep->private_data;
- struct drm_i915_private *dev_priv = info->dev_priv;
- struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
- char buf[PIPE_CRC_BUFFER_LEN];
- int n_entries;
- ssize_t bytes_read;
-
- /*
-* Don't allow user space to provide buffers not big enough to hold
-* a line of data.
-*/
- if (count < PIPE_CRC_LINE_LEN)
- return -EINVAL;
-
- if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
- return 0;
-
- /* nothing to read */
- spin_lock_irq(&pipe_crc->lock);
- while (pipe_crc_data_count(pipe_crc) == 0) {
- int ret;
-
- if (filep->f_flags & O_NONBLOCK) {
- spin_unlock_irq(&pipe_crc->lock);
- return -EAGAIN;
- }
-
- ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
- pipe_crc_data_count(pipe_crc), pipe_crc->lock);
- if (ret) {
- spin_unlock_irq(&pipe_crc->lock);
- return ret;
-
[Intel-gfx] [PATCH v6 3/4] drm/i915: Use new CRC debugfs API
The core provides now an ABI to userspace for generation of frame CRCs,
so implement the ->set_crc_source() callback and reuse as much code as
possible with the previous ABI implementation.
v2:
- Leave the legacy implementation in place as the ABI implementation
in the core is incompatible with it.
v3:
- Use the "cooked" vblank counter so we have a whole 32 bits.
- Make sure we don't mess with the state of the legacy CRC capture
ABI implementation.
v4:
- Keep use of get_vblank_counter as in the legacy code, will be
changed in a followup commit.
v5:
- Skip first frame or two as it's known that they contain wrong
data.
- A few fixes suggested by Emil Velikov.
v6:
- Rework programming of the HW registers to preserve previous
behavior.
Signed-off-by: Tomeu Vizoso
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 83 +++--
drivers/gpu/drm/i915/intel_display.c | 1 +
drivers/gpu/drm/i915/intel_drv.h | 2 +
drivers/gpu/drm/i915/intel_pipe_crc.c | 98 ++-
5 files changed, 145 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 403c074a29f4..77d05807adc6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1672,6 +1672,7 @@ struct intel_pipe_crc {
enum intel_pipe_crc_source source;
int head, tail;
wait_queue_head_t wq;
+ int skipped;
};
struct i915_frontbuffer_tracking {
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7610eca4f687..413667497ce0 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1485,41 +1485,72 @@ static void display_pipe_crc_irq_handler(struct
drm_i915_private *dev_priv,
{
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
struct intel_pipe_crc_entry *entry;
- int head, tail;
+ struct drm_crtc *crtc = intel_get_crtc_for_pipe(&dev_priv->drm, pipe);
+ struct drm_driver *driver = dev_priv->drm.driver;
+ uint32_t crcs[5];
+ int head, tail, ret;
+ u32 frame;
spin_lock(&pipe_crc->lock);
+ if (pipe_crc->source) {
+ if (!pipe_crc->entries) {
+ spin_unlock(&pipe_crc->lock);
+ DRM_DEBUG_KMS("spurious interrupt\n");
+ return;
+ }
- if (!pipe_crc->entries) {
- spin_unlock(&pipe_crc->lock);
- DRM_DEBUG_KMS("spurious interrupt\n");
- return;
- }
-
- head = pipe_crc->head;
- tail = pipe_crc->tail;
+ head = pipe_crc->head;
+ tail = pipe_crc->tail;
- if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
- spin_unlock(&pipe_crc->lock);
- DRM_ERROR("CRC buffer overflowing\n");
- return;
- }
+ if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
+ spin_unlock(&pipe_crc->lock);
+ DRM_ERROR("CRC buffer overflowing\n");
+ return;
+ }
- entry = &pipe_crc->entries[head];
+ entry = &pipe_crc->entries[head];
- entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm,
-pipe);
- entry->crc[0] = crc0;
- entry->crc[1] = crc1;
- entry->crc[2] = crc2;
- entry->crc[3] = crc3;
- entry->crc[4] = crc4;
+ entry->frame = driver->get_vblank_counter(&dev_priv->drm, pipe);
+ entry->crc[0] = crc0;
+ entry->crc[1] = crc1;
+ entry->crc[2] = crc2;
+ entry->crc[3] = crc3;
+ entry->crc[4] = crc4;
- head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
- pipe_crc->head = head;
+ head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
+ pipe_crc->head = head;
- spin_unlock(&pipe_crc->lock);
+ spin_unlock(&pipe_crc->lock);
- wake_up_interruptible(&pipe_crc->wq);
+ wake_up_interruptible(&pipe_crc->wq);
+ } else {
+ /*
+* For some not yet identified reason, the first CRC is
+* bonkers. So let's just wait for the next vblank and read
+* out the buggy result.
+*
+* On CHV sometimes the second CRC is bonkers as well, so
+* don't trust that one either.
+*/
+ if (pipe_crc->skipped == 0 ||
+ (IS_CHERRYVIEW(dev_priv) && pipe_crc->skipped == 1)) {
+ pipe_crc->skipped++;
+ spin_unlock(&pipe_crc->lock);
+ return;
+ }
+
[Intel-gfx] [PATCH v6 4/4] drm/i915: Put "cooked" vlank counters in frame CRC lines
Use drm_accurate_vblank_count so we have the full 32 bit to represent
the frame counter and userspace has a simpler way of knowing when the
counter wraps around.
Signed-off-by: Tomeu Vizoso
---
drivers/gpu/drm/i915/i915_irq.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 413667497ce0..32a5f4634d6d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1489,7 +1489,6 @@ static void display_pipe_crc_irq_handler(struct
drm_i915_private *dev_priv,
struct drm_driver *driver = dev_priv->drm.driver;
uint32_t crcs[5];
int head, tail, ret;
- u32 frame;
spin_lock(&pipe_crc->lock);
if (pipe_crc->source) {
@@ -1545,8 +1544,9 @@ static void display_pipe_crc_irq_handler(struct
drm_i915_private *dev_priv,
crcs[2] = crc2;
crcs[3] = crc3;
crcs[4] = crc4;
- frame = driver->get_vblank_counter(&dev_priv->drm, pipe);
- ret = drm_crtc_add_crc_entry(crtc, true, frame, crcs);
+ ret = drm_crtc_add_crc_entry(crtc, true,
+drm_accurate_vblank_count(crtc),
+crcs);
spin_unlock(&crtc->crc.lock);
if (!ret)
wake_up_interruptible(&crtc->crc.wq);
--
2.7.4
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[Intel-gfx] [PATCH v6 0/4] New debugfs API for capturing CRC of frames
Hi, this series basically takes the facility for continuously capturing CRCs of frames from the i915 driver and into the DRM core. The idea is that test suites such as IGT use this information to check that frames that are exected to be identical, also have identical CRC values. Other drivers for hardware that can provide frame CRCs (including eDP panels that support self-refresh) can easily implement the new callback and provide userspace with the CRC values. Thanks, Tomeu Tomeu Vizoso (4): drm/i915/debugfs: Move out pipe CRC code drm: Add API for capturing frame CRCs drm/i915: Use new CRC debugfs API drm/i915: Put "cooked" vlank counters in frame CRC lines Documentation/gpu/drm-uapi.rst|6 + drivers/gpu/drm/Makefile |3 +- drivers/gpu/drm/drm_crtc.c| 29 +- drivers/gpu/drm/drm_debugfs.c | 34 +- drivers/gpu/drm/drm_debugfs_crc.c | 351 drivers/gpu/drm/drm_drv.c | 15 + drivers/gpu/drm/drm_internal.h| 10 + drivers/gpu/drm/i915/Makefile |2 +- drivers/gpu/drm/i915/i915_debugfs.c | 886 +--- drivers/gpu/drm/i915/i915_drv.c |2 +- drivers/gpu/drm/i915/i915_drv.h |3 +- drivers/gpu/drm/i915/i915_irq.c | 83 ++- drivers/gpu/drm/i915/intel_display.c |1 + drivers/gpu/drm/i915/intel_drv.h |7 + drivers/gpu/drm/i915/intel_pipe_crc.c | 1014 + include/drm/drm_crtc.h| 41 ++ include/drm/drm_debugfs_crc.h | 78 +++ 17 files changed, 1651 insertions(+), 914 deletions(-) create mode 100644 drivers/gpu/drm/drm_debugfs_crc.c create mode 100644 drivers/gpu/drm/i915/intel_pipe_crc.c create mode 100644 include/drm/drm_debugfs_crc.h -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] assembler, lib, overlay, tools, tests/: Fix warnings about unused variables.
Signed-off-by: Marius Vlad
---
assembler/gen8_disasm.c | 5 -
lib/intel_device_info.c | 6 --
overlay/igfx.c| 7 ---
tests/testdisplay.c | 1 -
tools/intel_bios_reader.c | 22 --
5 files changed, 41 deletions(-)
diff --git a/assembler/gen8_disasm.c b/assembler/gen8_disasm.c
index 7fc7a65..68bc033 100644
--- a/assembler/gen8_disasm.c
+++ b/assembler/gen8_disasm.c
@@ -138,11 +138,6 @@ static const char *const m_dep_ctrl[4] = {
"NoDDClr,NoDDChk",
};
-static const char *const m_mask_ctrl[4] = {
- "",
- "nomask",
-};
-
static const char *const m_access_mode[2] = { "align1", "align16" };
static const char *const m_reg_type[8] = {
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index 5aab684..6a03b09 100644
--- a/lib/intel_device_info.c
+++ b/lib/intel_device_info.c
@@ -9,12 +9,6 @@ static const struct intel_device_info intel_generic_info = {
.gen = 0,
};
-static const struct intel_device_info intel_i81x_info = {
- .gen = BIT(0),
- .is_whitney = true,
- .codename = "solano" /* 815 == "whitney" ? or vice versa? */
-};
-
static const struct intel_device_info intel_i830_info = {
.gen = BIT(1),
.is_almador = true,
diff --git a/overlay/igfx.c b/overlay/igfx.c
index fa046e7..55f0edf 100644
--- a/overlay/igfx.c
+++ b/overlay/igfx.c
@@ -35,16 +35,9 @@ static const struct igfx_info generic_info = {
.gen = -1,
};
-static const struct igfx_info i81x_info = {
- .gen = 010,
-};
-
static const struct igfx_info i830_info = {
.gen = 020,
};
-static const struct igfx_info i845_info = {
- .gen = 020,
-};
static const struct igfx_info i855_info = {
.gen = 021,
};
diff --git a/tests/testdisplay.c b/tests/testdisplay.c
index a974f42..f2a41fa 100644
--- a/tests/testdisplay.c
+++ b/tests/testdisplay.c
@@ -96,7 +96,6 @@ unsigned int plane_fb_id;
unsigned int plane_crtc_id;
unsigned int plane_id;
int plane_width, plane_height;
-static const uint32_t SPRITE_COLOR_KEY = 0x00aa;
/*
* Mode setting with the kernel interfaces is a bit of a chore.
diff --git a/tools/intel_bios_reader.c b/tools/intel_bios_reader.c
index e3daa74..9e8e5ba 100644
--- a/tools/intel_bios_reader.c
+++ b/tools/intel_bios_reader.c
@@ -372,28 +372,6 @@ static const char *efp_port(uint8_t type)
return "unknown";
}
-static const struct {
- unsigned short type;
- const char *name;
-} efp_conn_info[] = {
- { DEVICE_INFO_NONE, "N/A" },
- { DEVICE_INFO_HDMI_CERT, "HDMI certified" },
- { DEVICE_INFO_DP, "DisplayPort" },
- { DEVICE_INFO_DVI, "DVI" },
-};
-static const int num_efp_conn_info = sizeof(efp_conn_info) /
sizeof(efp_conn_info[0]);
-
-static const char *efp_conn(uint8_t type)
-{
- int i;
-
- for (i = 0; i < num_efp_conn_info; i++)
- if (efp_conn_info[i].type == type)
- return efp_conn_info[i].name;
-
- return "unknown";
-}
-
static void dump_child_device(struct context *context,
struct child_device_config *child)
{
--
2.8.1
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Re: [Intel-gfx] [PATCH] tools/intel_guc_logger: Utility for capturing GuC firmware logs in a file
On 9/7/2016 3:07 PM, Tvrtko Ursulin wrote:
On 07/09/16 09:44, Chris Wilson wrote:
On Wed, Sep 07, 2016 at 01:40:27PM +0530, Goel, Akash wrote:
On 9/6/2016 9:22 PM, Tvrtko Ursulin wrote:
[snip]
+while (!stop_logging)
+{
+if (test_duration && (igt_seconds_elapsed(&start) >
test_duration)) {
If you agree to allow no poll period the this would not work
right? In
that case you would need to use alarm(2) or something.
Can calculate the timeout value for poll call as,
if (poll_timeout < 0) {
timeout = test_duration - igt_seconds_elapsed(&start))
}
My point was that with indefinite poll loop will not run if there is
not
log data so timeout will not work implemented like this.
I understood your concern in first place but probably didn't put
forth my point clearly.
For more clarity, this is how think it can be addressed.
--- a/tools/intel_guc_logger.c
+++ b/tools/intel_guc_logger.c
@@ -370,6 +370,8 @@ int main(int argc, char **argv)
{
struct pollfd relay_poll_fd;
struct timespec start={};
+uint32_t time_elapsed;
+int timeout;
int nfds;
int ret;
@@ -395,10 +397,17 @@ int main(int argc, char **argv)
while (!stop_logging)
{
-if (test_duration && (igt_seconds_elapsed(&start) >
test_duration)) {
-igt_debug("Ran for stipulated %d seconds, exit now\n",
test_duration);
-stop_logging = true;
-break;
+timeout = poll_timeout;
+if (test_duration) {
+time_elapsed = igt_seconds_elapsed(&start);
+if (time_elapsed >= test_duration) {
+igt_debug("Ran for stipulated %d seconds, exit
now\n", test_duration);
+stop_logging = true;
+break;
+}
+if (poll_timeout < 0)
+timeout = (test_duration - time_elapsed) * 1000;
}
/* Wait/poll for the new data to be available, relay doesn't
@@ -412,7 +421,7 @@ int main(int argc, char **argv)
* than a jiffy gap between 2 flush interrupts) and relay runs
* out of sub buffers to store the new logs.
*/
-ret = poll(&relay_poll_fd, nfds, poll_timeout);
+ret = poll(&relay_poll_fd, nfds, timeout);
if (ret < 0) {
if (errno == EINTR)
break;
So will not do polling with indefinite timeout and adjust the
timeout value as per test's duration.
Does it look ok ?
Since the comment still refers to a kernel bug that you've fixed, it can
just go. The timeout calculation is indeed more simply expressed as
alarm(timeout).
Yes I wrote privately that's especially true since there is already a
handler for SIGINT which would do the right thing for SIGALRM as well. I
don't feel so strongly about this but now that we both think the same
maybe go for the simpler implementation if you don't mind Akash?
Thanks much for suggestion.
Will use 'alarm(timeout)', its definitely much simpler.
And fixing the blocking read() is about 10 lines in the kernel...
Haven't checked but if that is the case, since we are already fixing
relayfs issues, it would be good to do that one as well since it would
simplify the logger. Because if we do it straight away then we know
logger can use it, and if we leave it for later then it gets uglier for
the logger.
But if we cannot make the fix go in the same kernel version (or earlier)
than the GuC logging then I think we don't need to block on that.
Sorry not sure that whether we would gain much by trying to add the
support for blocking read in relay.
For a regular disk file, which is of a fixed size, it makes sense to
have a provision to block the reader until file's data is paged in from
the disk into RAM.
But for relay, data to be read would invariably be generated dynamically
which can stop at anytime and thus the reader could get blocked for ever.
I think the current relay semantics are fine that if there is no data
left to be read in channel buffers zero will be returned and Clients
can get to know about the generation of new data through poll (using a
timeout).
Best regards
Akash
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH v2 14/14] drm/i915/dp/mst: Add support for upfront link training for DP MST
On Tue, 2016-09-06 at 17:13 -0700, Manasi Navare wrote:
> From: Jim Bride
>
> Add upfront link training to intel_dp_mst_mode_valid() so that we
> know
> topology constraints before we validate the legality of modes to be
> checked.
> Call the function that loops through the link rates and lane counts
> starting from highest supported link rate and lane count for training
> the link in compliance with DP spec
>
> v2:
> * Rebased on new revision of link training patch (Manasi Navare)
>
> Signed-off-by: Manasi Navare
> Signed-off-by: Jim Bride
> ---
> drivers/gpu/drm/i915/intel_dp.c | 9 ++---
> drivers/gpu/drm/i915/intel_dp_mst.c | 74
> +++--
> drivers/gpu/drm/i915/intel_drv.h| 3 ++
> 3 files changed, 61 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index 7794180..0c7674f 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -131,7 +131,7 @@ static void vlv_steal_power_sequencer(struct
> drm_device *dev,
> enum pipe pipe);
> static void intel_dp_unset_edid(struct intel_dp *intel_dp);
>
> -static int
> +int
> intel_dp_max_link_bw(struct intel_dp *intel_dp)
> {
> int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
> @@ -150,7 +150,7 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
> return max_link_bw;
> }
>
> -static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
> +u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
> {
> struct intel_digital_port *intel_dig_port =
> dp_to_dig_port(intel_dp);
> u8 temp, source_max, sink_max;
> @@ -312,8 +312,7 @@ static int intersect_rates(const int
> *source_rates, int source_len,
> return k;
> }
>
> -static int intel_dp_common_rates(struct intel_dp *intel_dp,
> - int *common_rates)
> +int intel_dp_common_rates(struct intel_dp *intel_dp, int
> *common_rates)
> {
> const int *source_rates, *sink_rates;
> int source_len, sink_len;
> @@ -336,7 +335,7 @@ static int intel_dp_common_rates(struct intel_dp
> *intel_dp,
> common_rates);
> }
>
> -static bool intel_dp_upfront_link_train(struct intel_dp *intel_dp)
> +bool intel_dp_upfront_link_train(struct intel_dp *intel_dp)
> {
> struct intel_digital_port *intel_dig_port =
> dp_to_dig_port(intel_dp);
> struct intel_encoder *intel_encoder = &intel_dig_port->base;
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 54a9d76..98d45a4 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -41,21 +41,30 @@ static bool intel_dp_mst_compute_config(struct
> intel_encoder *encoder,
> int bpp;
> int lane_count, slots;
> const struct drm_display_mode *adjusted_mode = &pipe_config-
> >base.adjusted_mode;
> - int mst_pbn;
> + int mst_pbn, common_len;
> + int common_rates[DP_MAX_SUPPORTED_RATES] = {};
>
> pipe_config->dp_encoder_is_mst = true;
> pipe_config->has_pch_encoder = false;
> - bpp = 24;
> +
> /*
> - * for MST we always configure max link bw - the spec
> doesn't
> - * seem to suggest we should do otherwise.
> + * For MST we always configure for the maximum trainable
> link bw -
> + * the spec doesn't seem to suggest we should do
> otherwise. The
> + * calls to intel_dp_max_lane_count() and
> intel_dp_common_rates()
> + * both take successful upfront link training into account,
> and
> + * return the DisplayPort max supported values in the event
> that
> + * upfront link training was not done.
> */
> - lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
> + lane_count = intel_dp_max_lane_count(intel_dp);
>
> pipe_config->lane_count = lane_count;
>
> - pipe_config->pipe_bpp = 24;
> - pipe_config->port_clock = intel_dp_max_link_rate(intel_dp);
> + pipe_config->pipe_bpp = bpp = 24;
> + common_len = intel_dp_common_rates(intel_dp, common_rates);
> + pipe_config->port_clock = common_rates[common_len - 1];
> +
> + DRM_DEBUG_KMS("DP MST link configured for %d lanes @ %d.\n",
> + pipe_config->lane_count, pipe_config-
> >port_clock);
>
> state = pipe_config->base.state;
>
> @@ -137,6 +146,8 @@ static void intel_mst_pre_enable_dp(struct
> intel_encoder *encoder,
> enum port port = intel_dig_port->port;
> struct intel_connector *connector =
> to_intel_connector(conn_state->connector);
> + struct intel_shared_dpll *pll = pipe_config->shared_dpll;
> + struct intel_shared_dpll_config tmp_pll_config;
> int ret;
> uint32_t temp;
> int slots;
> @@ -150,21 +161,23 @@ static void intel_mst_pre_enable_dp(struct
> intel_encoder *encoder,
> DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
>
> if (intel_
Re: [Intel-gfx] [PATCH i-g-t] benchmarks/gem_busy: Fix compile error
Applied. Thanks!
On Tue, Sep 06, 2016 at 03:55:41PM +0100, Derek Morton wrote:
> The benchmark was failing with:
> gem_busy.c:158:8: error: implicit declaration of function 'intel_gen'
> is invalid in C99 [-Werror,-Wimplicit-function-declaration]
> gen = intel_gen(intel_get_drm_devid(fd));
>
> The root cause was due to the local lib directory not being specified
> in benchmarks/Android.mk, resulting in intel_chipset.h from drm being
> used instead.
>
> This patch adds the lib path to the LOCAL_C_INCLUDES
>
> Signed-off-by: Derek Morton
> ---
> benchmarks/Android.mk | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/benchmarks/Android.mk b/benchmarks/Android.mk
> index 147f5db..c0fa09f 100644
> --- a/benchmarks/Android.mk
> +++ b/benchmarks/Android.mk
> @@ -1,6 +1,7 @@
> LOCAL_PATH := $(call my-dir)
>
> include $(LOCAL_PATH)/Makefile.sources
> +IGT_LOCAL_C_INCLUDES = $(LOCAL_PATH)/../lib
>
> ##
>
> @@ -9,6 +10,7 @@ define add_benchmark
>
> LOCAL_SRC_FILES := $1.c
>
> +LOCAL_C_INCLUDES = ${IGT_LOCAL_C_INCLUDES}
> LOCAL_CFLAGS += -DHAVE_STRUCT_SYSINFO_TOTALRAM
> LOCAL_CFLAGS += -DANDROID -UNDEBUG -include "check-ndebug.h"
> LOCAL_CFLAGS += -std=gnu99
> --
> 1.9.1
>
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Re: [Intel-gfx] [PATCH] Revert "drm/i915: Check live status before reading edid"
On Fri, 19 Aug 2016, David Weinehall wrote:
> On Thu, Aug 18, 2016 at 10:29:43AM +0300, David Weinehall wrote:
>> On Wed, Aug 17, 2016 at 04:43:36PM +0300, Jani Nikula wrote:
>> > On Wed, 17 Aug 2016, Chris Wilson wrote:
>> > > On Wed, Aug 17, 2016 at 03:47:48PM +0300, David Weinehall wrote:
>> > >> This reverts commit 237ed86c693d8a8e4db476976aeb30df4deac74b.
>> > >>
>> > >> Our current implementation of live status check (repeat 9 times
>> > >> with 10ms delays between each attempt as a workaround for
>> > >> buggy displays) imposes a rather serious penalty, time wise,
>> > >> on intel_hdmi_detect(). Since we we already skip live status
>> > >> checks on platforms before gen 7, and since we seem to have
>> > >> coped quite well before the live status check was introduced
>> > >> for newer platforms too, the previous behaviour is probably
>> > >> preferable, at least unless someone can point to a use-case
>> > >> that the live status check improves (apart from "Bspec says so".
>> > >>
>> > >> Signed-off-by: David Weinehall
>> > >
>> > > Fixes: 237ed86c693d ("drm/i915: Check live status before reading edid")
>> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97139
>> > > Acked-by: Chris Wilson
>> > > Cc: sta...@vger.kernel.org
>> >
>> > And we've come full circle on live status. Again.
>> >
>> > References:
>> > https://upload.wikimedia.org/wikipedia/commons/3/3b/Paris_Tuileries_Garden_Facepalm_statue.jpg
>>
>> Actually, we might have to take (at least) one more
>> lap around the circle.
>>
>> I did some more benchmarks, this time on Cherryview,
>> and two different Skylake models (one ThinkPad 13,
>> one NUC i5).
>>
>> The results are rather frustrating:
>>
>> On Skylake gmbus_wait_hw_status() seems to be
>> really expensive[1].
>
> [snip]
>
> Actually, I think it's safe to do the revert.
> A bit more testing yields that it's not a generic
> issue for Skylake, it seems to be specific to
> ThinkPads (or even a subset of them; I haven't
> got more than one model to test on).
>
> The gmbus never sends a NAK if there's nothing connected,
> so eventually gmbus_wait_for_status() gives up and we fall
> back to using the bitbanging method instead.
>
> Since things still work (albeit with reduced performance)
> on ThinkPads, and other platforms don't exhibit this
> behaviour, I suggest we move forward and revert
> the live status check.
>
> Chris has a partial fix for the problem; it fixes
> the first port (which is purely an HDMI-port), but
> the second port -- which I believe is routed through
> the dock connector and/or the type C USB-port,
> still remains problematic.
Pushed to drm-intel-next-queued after procrastination, thanks for the
patch.
BR,
Jani.
--
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Re: [Intel-gfx] FIFO underruns
On Tue, 06 Sep 2016, t s wrote: > I know that this is not the latest general kernel, but I wonder if this is > a known problem and what can be done about it. Try drm-intel-nightly branch of [1], and if the problem persists, file a bug at [2]. BR, Jani. [1] http://cgit.freedesktop.org/drm-intel [2] https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=DRM/Intel -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Regression in v4.8-rc4: i915 flickering since commit 1c80c25fb6
On Sun, 04 Sep 2016, Dominik Brodowski wrote: > Hi! > > Since commit 1c80c25fb6 (determined by git bisect, and confirmed by > reverting this patch on top of 9ca581b50d), the sceen on my DELL XPS 13 > is flickering every once in a while (sometimes multiple times per > second, sometimes only every few seconds). *sigh* another PSR issue. commit 1c80c25fb622973dd135878e98d172be20859049 Author: Daniel Vetter Date: Wed May 18 18:47:12 2016 +0200 drm/i915/psr: Make idle_frames sensible again Please file a bug at [1]. BR, Jani. [1] https://bugs.freedesktop.org/enter_bug.cgi?product=DRI&component=DRM/Intel > > That's for > > 00:02.0 VGA compatible controller: Intel Corporation Broadwell-U Integrated > Graphics (rev 09) (prog-if 00 [VGA controller]) > Subsystem: Dell Device 0665 > Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- > Stepping- SERR- FastB2B- DisINTx+ > Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- > SERR- Latency: 0 > Interrupt: pin A routed to IRQ 42 > Region 0: Memory at f600 (64-bit, non-prefetchable) [size=16M] > Region 2: Memory at e000 (64-bit, prefetchable) [size=256M] > Region 4: I/O ports at f000 [size=64] > [virtual] Expansion ROM at 000c [disabled] [size=128K] > Capabilities: > Kernel driver in use: i915 > > and Debian Jessie userland. > > Best, > Dominik -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 10/25] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
Hi Tom,
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20160907]
[cannot apply to v4.8-rc5]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
[Suggest to use git(>=2.9.0) format-patch --base= (or --base=auto for
convenience) to record what (public, well-known) commit your patch series was
built on]
[Check https://git-scm.com/docs/git-format-patch for more information]
url:
https://github.com/0day-ci/linux/commits/Sagar-Arun-Kamble/Add-support-for-GuC-based-SLPC/20160907-201335
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/intel_slpc.c: In function 'slpc_get_slice_count':
>> drivers/gpu/drm/i915/intel_slpc.c:50:37: error: 'const struct
>> intel_device_info' has no member named 'slice_total'
slice_count = INTEL_INFO(dev_priv)->slice_total;
^~
vim +50 drivers/gpu/drm/i915/intel_slpc.c
44
45 static unsigned int slpc_get_slice_count(struct drm_i915_private
*dev_priv)
46 {
47 unsigned int slice_count = 1;
48
49 if (IS_SKYLAKE(dev_priv))
> 50 slice_count = INTEL_INFO(dev_priv)->slice_total;
51
52 return slice_count;
53 }
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: Binary data
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[Intel-gfx] [PATCH v2 07/22] drm/i915: Separate out reset flags from the reset counter
In preparation for introducing a per-engine reset, we can first separate
the mixing of the reset state from the global reset counter.
The loss of atomicity in updating the reset state poses a small problem
for handling the waiters. For requests, this is solved by advancing the
seqno so that a waiter waking up after the reset knows the request is
complete. For pending flips, we still rely on the increment of the
global reset epoch (as well as the reset-in-progress flag) to signify
when the hardware was reset.
The advantage, now that we do not inspect the reset state during reset
itself i.e. we no longer emit requests during reset, is that we can use
the atomic updates of the state flags to ensure that only one reset
worker is active.
v2: Mika spotted that I transformed the i915_gem_wait_for_error() wakeup
into a waiter wakeup.
Signed-off-by: Chris Wilson
Cc: Arun Siluvery
Cc: Mika Kuoppala
Link:
http://patchwork.freedesktop.org/patch/msgid/1470414607-32453-6-git-send-email-arun.siluv...@linux.intel.com
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_debugfs.c | 9 +++
drivers/gpu/drm/i915/i915_drv.c | 16 ++---
drivers/gpu/drm/i915/i915_drv.h | 46 +-
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_gem_request.c | 13 ++--
drivers/gpu/drm/i915/i915_irq.c | 103 ++--
drivers/gpu/drm/i915/intel_display.c| 25 +---
drivers/gpu/drm/i915/intel_drv.h| 4 +-
8 files changed, 101 insertions(+), 117 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a54fc05b9512..5a6d8f171305 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1287,6 +1287,15 @@ static int i915_hangcheck_info(struct seq_file *m, void
*unused)
enum intel_engine_id id;
int j;
+ if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
+ seq_printf(m, "Wedged\n");
+ if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags))
+ seq_printf(m, "Reset in progress\n");
+ if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
+ seq_printf(m, "Waiter holding struct mutex\n");
+ if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
+ seq_printf(m, "struct_mutex blocked for reset\n");
+
if (!i915.enable_hangcheck) {
seq_printf(m, "Hangcheck disabled\n");
return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 02c34d6996ea..47a676d859db 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1579,7 +1579,7 @@ static int i915_drm_resume(struct drm_device *dev)
mutex_lock(&dev->struct_mutex);
if (i915_gem_init_hw(dev)) {
DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
- atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
+ set_bit(I915_WEDGED, &dev_priv->gpu_error.flags);
}
mutex_unlock(&dev->struct_mutex);
@@ -1741,20 +1741,13 @@ int i915_reset(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = &dev_priv->drm;
struct i915_gpu_error *error = &dev_priv->gpu_error;
- unsigned reset_counter;
int ret;
mutex_lock(&dev->struct_mutex);
/* Clear any previous failed attempts at recovery. Time to try again. */
- atomic_andnot(I915_WEDGED, &error->reset_counter);
-
- /* Clear the reset-in-progress flag and increment the reset epoch. */
- reset_counter = atomic_inc_return(&error->reset_counter);
- if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
- ret = -EIO;
- goto error;
- }
+ __clear_bit(I915_WEDGED, &error->flags);
+ error->reset_count++;
pr_notice("drm/i915: Resetting chip after gpu hang\n");
@@ -1791,6 +1784,7 @@ int i915_reset(struct drm_i915_private *dev_priv)
goto error;
}
+ clear_bit(I915_RESET_IN_PROGRESS, &error->flags);
mutex_unlock(&dev->struct_mutex);
/*
@@ -1805,7 +1799,7 @@ int i915_reset(struct drm_i915_private *dev_priv)
return 0;
error:
- atomic_or(I915_WEDGED, &error->reset_counter);
+ set_bit(I915_WEDGED, &error->flags);
mutex_unlock(&dev->struct_mutex);
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ecfd8e9726b5..994495e7a1c4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1392,9 +1392,10 @@ struct i915_gpu_error {
* State variable controlling the reset flow and count
*
* This is a counter which gets incremented when reset is triggered,
-* and again when reset has been handled. So odd values (lowest bit set)
-* means that reset is in progress
[Intel-gfx] [PATCH v2 01/22] drm/i915: Add a sw fence for collecting up dma fences
This is really a core kernel struct in disguise until we can finally
place it in kernel/. There is an immediate need for a fence collection
mechanism that is more flexible than fence-array, in particular being
able to easily drive request submission via events (and not just
interrupt driven). The same mechanism would be useful for handling
nonblocking and asynchronous atomic modesets, parallel execution and
more, but for the time being just create a local sw fence for execbuf.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/i915_sw_fence.c | 326 +++
drivers/gpu/drm/i915/i915_sw_fence.h | 62 +++
3 files changed, 389 insertions(+)
create mode 100644 drivers/gpu/drm/i915/i915_sw_fence.c
create mode 100644 drivers/gpu/drm/i915/i915_sw_fence.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a7da24640e88..a998c2bce70a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -16,6 +16,7 @@ i915-y := i915_drv.o \
i915_params.o \
i915_pci.o \
i915_suspend.o \
+ i915_sw_fence.o \
i915_sysfs.o \
intel_csr.o \
intel_device_info.o \
diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c
b/drivers/gpu/drm/i915/i915_sw_fence.c
new file mode 100644
index ..08b095e6e3be
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_sw_fence.c
@@ -0,0 +1,326 @@
+/*
+ * (C) Copyright 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2
+ * of the License.
+ */
+
+#include
+#include
+#include
+
+#include "i915_sw_fence.h"
+
+static DEFINE_SPINLOCK(i915_sw_fence_lock);
+
+static int __i915_sw_fence_notify(struct i915_sw_fence *fence,
+ enum i915_sw_fence_notify state)
+{
+ i915_sw_fence_notify_t fn;
+
+ fn = (i915_sw_fence_notify_t)(fence->flags & I915_SW_FENCE_MASK);
+ return fn(fence, state);
+}
+
+static void i915_sw_fence_free(struct kref *kref)
+{
+ struct i915_sw_fence *fence = container_of(kref, typeof(*fence), kref);
+
+ WARN_ON(atomic_read(&fence->pending) > 0);
+
+ if (fence->flags & I915_SW_FENCE_MASK)
+ __i915_sw_fence_notify(fence, FENCE_FREE);
+ else
+ kfree(fence);
+}
+
+static void i915_sw_fence_put(struct i915_sw_fence *fence)
+{
+ kref_put(&fence->kref, i915_sw_fence_free);
+}
+
+static struct i915_sw_fence *i915_sw_fence_get(struct i915_sw_fence *fence)
+{
+ kref_get(&fence->kref);
+ return fence;
+}
+
+static void __i915_sw_fence_wake_up_all(struct i915_sw_fence *fence,
+ struct list_head *continuation)
+{
+ wait_queue_head_t *x = &fence->wait;
+ wait_queue_t *pos, *next;
+ unsigned long flags;
+
+ smp_wmb();
+ atomic_set(&fence->pending, -1); /* 0 -> -1 [done] */
+
+ /*
+* To prevent unbounded recursion as we traverse the graph of
+* i915_sw_fences, we move the task_list from this, the next ready
+* fence, to the tail of the original fence's task_list
+* (and so added to the list to be woken).
+*/
+
+ spin_lock_irqsave_nested(&x->lock, flags, 1 + !!continuation);
+ if (continuation) {
+ list_for_each_entry_safe(pos, next, &x->task_list, task_list) {
+ if (pos->func == autoremove_wake_function)
+ pos->func(pos, TASK_NORMAL, 0, continuation);
+ else
+ list_move_tail(&pos->task_list, continuation);
+ }
+ } else {
+ LIST_HEAD(extra);
+
+ do {
+ list_for_each_entry_safe(pos, next,
+&x->task_list, task_list)
+ pos->func(pos, TASK_NORMAL, 0, &extra);
+
+ if (list_empty(&extra))
+ break;
+
+ list_splice_tail_init(&extra, &x->task_list);
+ } while (1);
+ }
+ spin_unlock_irqrestore(&x->lock, flags);
+}
+
+static void __i915_sw_fence_complete(struct i915_sw_fence *fence,
+struct list_head *continuation)
+{
+ if (!atomic_dec_and_test(&fence->pending))
+ return;
+
+ if (fence->flags & I915_SW_FENCE_MASK &&
+ __i915_sw_fence_notify(fence, FENCE_COMPLETE) != NOTIFY_DONE)
+ return;
+
+ __i915_sw_fence_wake_up_all(fence, continuation);
+}
+
+static void i915_sw_fence_complete(struct i915_sw_fence *fence)
+{
+ if (WARN_ON(i915_sw_fence_done(fence)))
+ return;
+
+ __i915_sw_fence_complete(fence, NULL);
+}
[Intel-gfx] [PATCH v2 03/22] drm/i915: Record the position of the workarounds in the tail of the request
Rather than blindly assuming we need to advance the tail for
resubmitting the request via the ELSP, record the position.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_request.h | 15 +--
drivers/gpu/drm/i915/intel_lrc.c| 4 ++--
2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h
b/drivers/gpu/drm/i915/i915_gem_request.h
index 91014de8bfbc..2faa3bb4c39b 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -88,20 +88,23 @@ struct drm_i915_gem_request {
*/
u32 previous_seqno;
- /** Position in the ringbuffer of the start of the request */
+ /** Position in the ring of the start of the request */
u32 head;
/**
-* Position in the ringbuffer of the start of the postfix.
-* This is required to calculate the maximum available ringbuffer
-* space without overwriting the postfix.
+* Position in the ring of the start of the postfix.
+* This is required to calculate the maximum available ring space
+* without overwriting the postfix.
*/
u32 postfix;
- /** Position in the ringbuffer of the end of the whole request */
+ /** Position in the ring of the end of the whole request */
u32 tail;
- /** Preallocate space in the ringbuffer for the emitting the request */
+ /** Position in the ring of the end of any workarounds after the tail */
+ u32 wa_tail;
+
+ /** Preallocate space in the ring for the emitting the request */
u32 reserved_space;
/**
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 9bfe304c5256..d7fa9b3a55c3 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -482,8 +482,7 @@ static void execlists_unqueue(struct intel_engine_cs
*engine)
* resubmit the request. See gen8_emit_request() for where we
* prepare the padding after the end of the request.
*/
- req0->tail += 8;
- req0->tail &= req0->ring->size - 1;
+ req0->tail = req0->wa_tail;
}
execlists_elsp_submit_contexts(req0, req1);
@@ -711,6 +710,7 @@ intel_logical_ring_advance(struct drm_i915_gem_request
*request)
intel_ring_emit(ring, MI_NOOP);
intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
+ request->wa_tail = ring->tail;
/* We keep the previous context alive until we retire the following
* request. This ensures that any the context object is still pinned
--
2.9.3
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 08/22] drm/i915: Drop local struct_mutex around intel_init_emon[ilk]
Access to intel_init_emon() is strictly ordered by gt_powersave, using
struct_mutex around it is overkill (and will conflict with the caller
holding struct_mutex themselves).
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_pm.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4f833a077089..6af438ffef9a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6773,9 +6773,7 @@ void intel_autoenable_gt_powersave(struct
drm_i915_private *dev_priv)
if (IS_IRONLAKE_M(dev_priv)) {
ironlake_enable_drps(dev_priv);
- mutex_lock(&dev_priv->drm.struct_mutex);
intel_init_emon(dev_priv);
- mutex_unlock(&dev_priv->drm.struct_mutex);
} else if (INTEL_INFO(dev_priv)->gen >= 6) {
/*
* PCU communication is slow and this doesn't need to be
--
2.9.3
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 18/22] drm/i915: Ignore valid but unknown semaphores
If we find a ring waiting on a semaphore for another assigned but not yet
emitted request, treat it as valid and waiting.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_irq.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 699ee2c7a3e4..ed74f2d8141d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2832,10 +2832,10 @@ semaphore_wait_to_signaller_ring(struct intel_engine_cs
*engine, u32 ipehr,
}
}
- DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset
0x%016llx\n",
- engine->id, ipehr, offset);
+ DRM_DEBUG_DRIVER("No signaller ring found for ring %i, ipehr 0x%08x,
offset 0x%016llx\n",
+engine->id, ipehr, offset);
- return NULL;
+ return ERR_PTR(-ENODEV);
}
static struct intel_engine_cs *
@@ -2923,6 +2923,9 @@ static int semaphore_passed(struct intel_engine_cs
*engine)
if (signaller == NULL)
return -1;
+ if (IS_ERR(signaller))
+ return 0;
+
/* Prevent pathological recursion due to driver bugs */
if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
return -1;
--
2.9.3
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 04/22] drm/i915: Compute the ELSP register location once
Similar to the issue with reading from the context status buffer,
see commit 26720ab97fea ("drm/i915: Move CSB MMIO reads out of the
execlists lock"), we frequently write to the ELSP register (4 writes per
interrupt) and know we hold the required spinlock and forcewake throughout.
We can further reduce the cost of writing these registers beyond the
I915_WRITE_FW() by precomputing the address of the ELSP register. We also
note that the subsequent read serves no purpose here, and are happy to
see it go.
v2: Address I915_WRITE mistakes in changelog
textdata bss dec hex filename
12597844581 576 1264941 134d2d drivers/gpu/drm/i915/i915.ko
12597204581 576 1264877 134ced drivers/gpu/drm/i915/i915.ko
Saves 64 bytes of address recomputation.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d7fa9b3a55c3..a6b9033203e5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -331,10 +331,11 @@ uint64_t intel_lr_context_descriptor(struct
i915_gem_context *ctx,
static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
struct drm_i915_gem_request *rq1)
{
-
struct intel_engine_cs *engine = rq0->engine;
struct drm_i915_private *dev_priv = rq0->i915;
- uint64_t desc[2];
+ u32 __iomem *elsp =
+ dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine));
+ u64 desc[2];
if (rq1) {
desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine);
@@ -347,15 +348,12 @@ static void execlists_elsp_write(struct
drm_i915_gem_request *rq0,
rq0->elsp_submitted++;
/* You must always write both descriptors in the order below. */
- I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[1]));
- I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[1]));
+ writel(upper_32_bits(desc[1]), elsp);
+ writel(lower_32_bits(desc[1]), elsp);
- I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[0]));
+ writel(upper_32_bits(desc[0]), elsp);
/* The context is automatically loaded after the following */
- I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[0]));
-
- /* ELSP is a wo register, use another nearby reg for posting */
- POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine));
+ writel(lower_32_bits(desc[0]), elsp);
}
static void
--
2.9.3
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 06/22] drm/i915: Simplify ELSP queue request tracking
Emulate HW to track and manage ELSP queue. A set of SW ports are defined
and requests are assigned to these ports before submitting them to HW. This
helps in cleaning up incomplete requests during reset recovery easier
especially after engine reset by decoupling elsp queue management. This
will become more clear in the next patch.
In the engine reset case we want to resume where we left-off after skipping
the incomplete batch which requires checking the elsp queue, removing
element and fixing elsp_submitted counts in some cases. Instead of directly
manipulating the elsp queue from reset path we can examine these ports, fix
up ringbuffer pointers using the incomplete request and restart submissions
again after reset.
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Arun Siluvery
Signed-off-by: Chris Wilson
Link:
http://patchwork.freedesktop.org/patch/msgid/1470414607-32453-3-git-send-email-arun.siluv...@linux.intel.com
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 13 +-
drivers/gpu/drm/i915/i915_gem_request.c | 1 -
drivers/gpu/drm/i915/i915_gem_request.h | 21 +-
drivers/gpu/drm/i915/intel_lrc.c| 402 +---
drivers/gpu/drm/i915/intel_lrc.h| 2 -
drivers/gpu/drm/i915/intel_ringbuffer.h | 7 +-
7 files changed, 184 insertions(+), 264 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 3fde5079b536..a54fc05b9512 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2051,7 +2051,7 @@ static int i915_execlists(struct seq_file *m, void *data)
status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
- read_pointer = engine->next_context_status_buffer;
+ read_pointer = GEN8_CSB_READ_PTR(status_pointer);
write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
if (read_pointer > write_pointer)
write_pointer += GEN8_CSB_ENTRIES;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2401818171f5..b00fb8548d50 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2575,6 +2575,9 @@ static void i915_gem_reset_engine_cleanup(struct
intel_engine_cs *engine)
struct drm_i915_gem_request *request;
struct intel_ring *ring;
+ /* Ensure irq handler finishes, and not run again. */
+ tasklet_kill(&engine->irq_tasklet);
+
/* Mark all pending requests as complete so that any concurrent
* (lockless) lookup doesn't try and wait upon the request as we
* reset it.
@@ -2588,10 +2591,12 @@ static void i915_gem_reset_engine_cleanup(struct
intel_engine_cs *engine)
*/
if (i915.enable_execlists) {
- /* Ensure irq handler finishes or is cancelled. */
- tasklet_kill(&engine->irq_tasklet);
-
- intel_execlists_cancel_requests(engine);
+ spin_lock(&engine->execlist_lock);
+ INIT_LIST_HEAD(&engine->execlist_queue);
+ i915_gem_request_put(engine->execlist_port[0].request);
+ i915_gem_request_put(engine->execlist_port[1].request);
+ memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
+ spin_unlock(&engine->execlist_lock);
}
/*
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 9cc08a1e43c6..ec613fd5e01c 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -402,7 +402,6 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
req->previous_context = NULL;
req->file_priv = NULL;
req->batch = NULL;
- req->elsp_submitted = 0;
/*
* Reserve space in the ring buffer for all the commands required to
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h
b/drivers/gpu/drm/i915/i915_gem_request.h
index 2faa3bb4c39b..a231bd318ef0 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -137,27 +137,8 @@ struct drm_i915_gem_request {
/** file_priv list entry for this request */
struct list_head client_list;
- /**
-* The ELSP only accepts two elements at a time, so we queue
-* context/tail pairs on a given queue (ring->execlist_queue) until the
-* hardware is available. The queue serves a double purpose: we also use
-* it to keep track of the up to 2 contexts currently in the hardware
-* (usually one in execution and the other queued up by the GPU): We
-* only remove elements from the head of the queue when the hardware
-* informs us that an element has been completed.
-*
-* All accesses
[Intel-gfx] [PATCH v2 10/22] drm/i915: Mark up all locked waiters
In the next patch we want to handle reset directly by a locked waiter in
order to avoid issues with returning before the reset is handled. To
handle the reset, we must first know whether we hold the struct_mutex.
If we do not hold the struct_mtuex we can not perform the reset, but we do
not block the reset worker either (and so we can just continue to wait for
request completion) - otherwise we must relinquish the mutex.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +++-
drivers/gpu/drm/i915/i915_gem.c | 7 +--
drivers/gpu/drm/i915/i915_gem_evict.c| 8 ++--
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gem_request.c | 15 ---
drivers/gpu/drm/i915/i915_gem_request.h | 11 ---
drivers/gpu/drm/i915/i915_gem_shrinker.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++-
8 files changed, 38 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index f61d7d584f3f..8ea64aa0a282 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4803,7 +4803,9 @@ i915_drop_caches_set(void *data, u64 val)
return ret;
if (val & DROP_ACTIVE) {
- ret = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE);
+ ret = i915_gem_wait_for_idle(dev_priv,
+I915_WAIT_INTERRUPTIBLE |
+I915_WAIT_LOCKED);
if (ret)
goto unlock;
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4617250c3000..23069a2d2850 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2802,7 +2802,8 @@ __i915_gem_object_sync(struct drm_i915_gem_request *to,
if (!i915.semaphores) {
ret = i915_wait_request(from,
- from->i915->mm.interruptible,
+ from->i915->mm.interruptible |
+ I915_WAIT_LOCKED,
NULL,
NO_WAITBOOST);
if (ret)
@@ -4304,7 +4305,9 @@ int i915_gem_suspend(struct drm_device *dev)
if (ret)
goto err;
- ret = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE);
+ ret = i915_gem_wait_for_idle(dev_priv,
+I915_WAIT_INTERRUPTIBLE |
+I915_WAIT_LOCKED);
if (ret)
goto err;
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index 103085246975..5b6f81c1dbca 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -170,7 +170,9 @@ search_again:
if (ret)
return ret;
- ret = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE);
+ ret = i915_gem_wait_for_idle(dev_priv,
+I915_WAIT_INTERRUPTIBLE |
+I915_WAIT_LOCKED);
if (ret)
return ret;
@@ -275,7 +277,9 @@ int i915_gem_evict_vm(struct i915_address_space *vm, bool
do_idle)
return ret;
}
- ret = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE);
+ ret = i915_gem_wait_for_idle(dev_priv,
+I915_WAIT_INTERRUPTIBLE |
+I915_WAIT_LOCKED);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 9bcac52b8268..f3c6876da521 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2683,7 +2683,7 @@ void i915_gem_gtt_finish_object(struct
drm_i915_gem_object *obj)
struct i915_ggtt *ggtt = &dev_priv->ggtt;
if (unlikely(ggtt->do_idle_maps)) {
- if (i915_gem_wait_for_idle(dev_priv, 0)) {
+ if (i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED)) {
DRM_ERROR("Failed to wait for idle; VT'd may hang.\n");
/* Wait a bit, in hopes it avoids the hang */
udelay(10);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index f4c15f319d08..5f89801e6a16 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -260,7 +260,9 @@ static int i915_gem_init_seqno(struct drm_i915_private
*dev_priv, u32 seqno)
/* Carefully retire all requests without writing to the rings */
for_each_engine(engine, dev_priv) {
- ret = intel_engine
[Intel-gfx] [PATCH v2 02/22] drm/i915: Only queue requests during execlists submission
Leave the more complicated request dequeueing to the tasklet and instead
just kick start the tasklet if we detect we are adding the first
request.
v2: Play around with list operators until we agree upon something
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 28
1 file changed, 4 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 92bfe47ad33c..9bfe304c5256 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -609,35 +609,15 @@ static void intel_lrc_irq_handler(unsigned long data)
static void execlists_submit_request(struct drm_i915_gem_request *request)
{
struct intel_engine_cs *engine = request->engine;
- struct drm_i915_gem_request *cursor;
- int num_elements = 0;
spin_lock_bh(&engine->execlist_lock);
- list_for_each_entry(cursor, &engine->execlist_queue, execlist_link)
- if (++num_elements > 2)
- break;
-
- if (num_elements > 2) {
- struct drm_i915_gem_request *tail_req;
-
- tail_req = list_last_entry(&engine->execlist_queue,
- struct drm_i915_gem_request,
- execlist_link);
-
- if (request->ctx == tail_req->ctx) {
- WARN(tail_req->elsp_submitted != 0,
- "More than 2 already-submitted reqs queued\n");
- list_del(&tail_req->execlist_link);
- i915_gem_request_put(tail_req);
- }
- }
-
i915_gem_request_get(request);
- list_add_tail(&request->execlist_link, &engine->execlist_queue);
request->ctx_hw_id = request->ctx->hw_id;
- if (num_elements == 0)
- execlists_unqueue(engine);
+
+ if (list_empty(&engine->execlist_queue))
+ tasklet_hi_schedule(&engine->irq_tasklet);
+ list_add_tail(&request->execlist_link, &engine->execlist_queue);
spin_unlock_bh(&engine->execlist_lock);
}
--
2.9.3
___
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[Intel-gfx] [PATCH v2 15/22] drm/i915: Reorder i915_add_request to separate the phases better
Let's avoid mixing sealing the hardware commands for the request and adding the request to the software tracking. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_request.c | 28 ++-- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index c39dd40fb3b9..fe33acb615db 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -492,6 +492,8 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches) u32 reserved_tail; int ret; + trace_i915_gem_request_add(request); + /* * To ensure that this call will not fail, space for its emissions * should already have been reserved in the ring buffer. Let the ring @@ -515,20 +517,6 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches) WARN(ret, "engine->emit_flush() failed: %d!\n", ret); } - trace_i915_gem_request_add(request); - - /* Seal the request and mark it as pending execution. Note that -* we may inspect this state, without holding any locks, during -* hangcheck. Hence we apply the barrier to ensure that we do not -* see a more recent value in the hws than we are tracking. -*/ - request->emitted_jiffies = jiffies; - request->previous_seqno = engine->last_submitted_seqno; - engine->last_submitted_seqno = request->fence.seqno; - i915_gem_active_set(&engine->last_request, request); - list_add_tail(&request->link, &engine->request_list); - list_add_tail(&request->ring_link, &ring->request_list); - /* Record the position of the start of the breadcrumb so that * should we detect the updated seqno part-way through the * GPU processing the request, we never over-estimate the @@ -549,6 +537,18 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches) "for adding the request (%d bytes)\n", reserved_tail, ret); + /* Seal the request and mark it as pending execution. Note that +* we may inspect this state, without holding any locks, during +* hangcheck. Hence we apply the barrier to ensure that we do not +* see a more recent value in the hws than we are tracking. +*/ + request->emitted_jiffies = jiffies; + request->previous_seqno = engine->last_submitted_seqno; + engine->last_submitted_seqno = request->fence.seqno; + i915_gem_active_set(&engine->last_request, request); + list_add_tail(&request->link, &engine->request_list); + list_add_tail(&request->ring_link, &ring->request_list); + i915_gem_mark_busy(engine); local_bh_disable(); -- 2.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 21/22] drm/i915: Enable userspace to opt-out of implicit fencing
Userspace is faced with a dilemma. The kernel requires implicit fencing
to manage resource usage (we always must wait for the GPU to finish
before releasing its PTE) and for third parties. However, userspace may
wish to avoid this serialisation if it is either using explicit fencing
between parties and wants more fine-grained access to buffers (e.g. it
may partition the buffer between uses and track fences on ranges rather
than the implicit fences tracking the whole object). It follows that
userspace needs a mechanism to avoid the kernel's serialisation on its
implicit fences before execbuf execution.
The next question is whether this is an object, execbuf or context flag.
Hybrid users (such as using explicit EGL_ANDROID_native_sync fencing on
shared winsys buffers, but implicit fencing on internal surfaces)
require a per-object level flag. Given that this flag need to be only
set once for the lifetime of the object, this reduces the convenience of
having an execbuf or context level flag (and avoids having multiple
pieces of uABI controlling the same feature).
Incorrect use of this flag will result in rendering corruption and GPU
hangs - but will not result in use-after-free or similar resource
tracking issues.
Serious caveat: write ordering is not strictly correct after setting
this flag on a render target on multiple engines. This affects all
subsequent GEM operations (execbuf, set-domain, pread) and shared
dma-buf operations. A fix is possible - but costly (both in terms of
further ABI changes and runtime overhead).
Testcase: igt/gem_exec_async
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.c| 1 +
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 +++
include/uapi/drm/i915_drm.h| 27 ++-
3 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2b0727d1467d..caa852521bbd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -332,6 +332,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
case I915_PARAM_HAS_EXEC_HANDLE_LUT:
case I915_PARAM_HAS_COHERENT_PHYS_GTT:
case I915_PARAM_HAS_EXEC_SOFTPIN:
+ case I915_PARAM_HAS_EXEC_ASYNC:
/* For the time being all of these are always true;
* if some supported hardware does not have one of these
* features this value needs to be provided from
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 2c5de906315c..a8722abcd7ac 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1133,6 +1133,9 @@ i915_gem_execbuffer_move_to_gpu(struct
drm_i915_gem_request *req,
struct drm_i915_gem_object *obj = vma->obj;
struct reservation_object *resv;
+ if (vma->exec_entry->flags & EXEC_OBJECT_ASYNC)
+ continue;
+
if (obj->flags & other_rings) {
ret = i915_gem_request_await_object
(req, obj, obj->base.pending_write_domain);
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 03725fe89859..a2fa511b46b3 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -388,6 +388,10 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_HAS_POOLED_EU38
#define I915_PARAM_MIN_EU_IN_POOL 39
#define I915_PARAM_MMAP_GTT_VERSION 40
+/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
+ * synchronisation with implicit fencing on individual objects.
+ */
+#define I915_PARAM_HAS_EXEC_ASYNC 41
typedef struct drm_i915_getparam {
__s32 param;
@@ -729,8 +733,29 @@ struct drm_i915_gem_exec_object2 {
#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
#define EXEC_OBJECT_PINNED (1<<4)
#define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
+/* The kernel implicitly tracks GPU activity on all GEM objects, and
+ * synchronises operations with outstanding rendering. This includes
+ * rendering on other devices if exported via dma-buf. However, sometimes
+ * this tracking is too coarse and the user knows better. For example,
+ * if the object is split into non-overlapping ranges shared between different
+ * clients or engines (i.e. suballocating objects), the implicit tracking
+ * by kernel assumes that each operation affects the whole object rather
+ * than an individual range, causing needless synchronisation between clients.
+ * The kernel will also forgo any CPU cache flushes prior to rendering from
+ * the object as the client is expected to be also handling such domain
+ * tracking.
+ *
+ * The kernel maintains the implicit tracking in order to manage resources
+ * used by the GPU - this flag only disables the synchronisation prior to
+ *
[Intel-gfx] [PATCH v2 09/22] drm/i915: Expand bool interruptible to pass flags to i915_wait_request()
We need finer control over wakeup behaviour during i915_wait_request(),
so expand the current bool interruptible to a bitmask.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 16 +---
drivers/gpu/drm/i915/i915_gem_evict.c| 4 ++--
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gem_request.c | 9 +
drivers/gpu/drm/i915/i915_gem_request.h | 13 +++--
drivers/gpu/drm/i915/i915_gem_shrinker.c | 4 ++--
drivers/gpu/drm/i915/i915_gem_userptr.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 8
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++-
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 ++--
12 files changed, 37 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5a6d8f171305..f61d7d584f3f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4803,7 +4803,7 @@ i915_drop_caches_set(void *data, u64 val)
return ret;
if (val & DROP_ACTIVE) {
- ret = i915_gem_wait_for_idle(dev_priv, true);
+ ret = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE);
if (ret)
goto unlock;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 994495e7a1c4..dd73c00cd774 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3269,7 +3269,7 @@ int __must_check i915_gem_init_hw(struct drm_device *dev);
void i915_gem_init_swizzling(struct drm_device *dev);
void i915_gem_cleanup_engines(struct drm_device *dev);
int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
- bool interruptible);
+ unsigned int flags);
int __must_check i915_gem_suspend(struct drm_device *dev);
void i915_gem_resume(struct drm_device *dev);
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 87a4f3543f0b..4617250c3000 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -386,7 +386,8 @@ __unsafe_wait_rendering(struct drm_i915_gem_object *obj,
int ret;
ret = i915_gem_active_wait_unlocked(&active[idx],
- true, NULL, rps);
+ I915_WAIT_INTERRUPTIBLE,
+ NULL, rps);
if (ret)
return ret;
}
@@ -2026,7 +2027,7 @@ static int i915_gem_object_create_mmap_offset(struct
drm_i915_gem_object *obj)
* to claim that space for ourselves, we need to take the big
* struct_mutex to free the requests+objects and allocate our slot.
*/
- err = i915_gem_wait_for_idle(dev_priv, true);
+ err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE);
if (err)
return err;
@@ -2779,7 +2780,8 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
active = __I915_BO_ACTIVE(obj);
for_each_active(active, idx) {
s64 *timeout = args->timeout_ns >= 0 ? &args->timeout_ns : NULL;
- ret = i915_gem_active_wait_unlocked(&obj->last_read[idx], true,
+ ret = i915_gem_active_wait_unlocked(&obj->last_read[idx],
+ I915_WAIT_INTERRUPTIBLE,
timeout, rps);
if (ret)
break;
@@ -2982,7 +2984,7 @@ destroy:
}
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
- bool interruptible)
+ unsigned int flags)
{
struct intel_engine_cs *engine;
int ret;
@@ -2991,7 +2993,7 @@ int i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv,
if (engine->last_context == NULL)
continue;
- ret = intel_engine_idle(engine, interruptible);
+ ret = intel_engine_idle(engine, flags);
if (ret)
return ret;
}
@@ -3746,7 +3748,7 @@ i915_gem_ring_throttle(struct drm_device *dev, struct
drm_file *file)
if (target == NULL)
return 0;
- ret = i915_wait_request(target, true, NULL, NULL);
+ ret = i915_wait_request(target, I915_WAIT_INTERRUPTIBLE, NULL, NULL);
i915_gem_request_put(target);
return ret;
@@ -4302,7 +4304,7 @@ int i915_gem_suspend(struct drm_device *dev)
if (ret)
goto err;
- ret = i915_gem
[Intel-gfx] [PATCH v2 17/22] drm/i915/guc: Prepare for nonblocking execbuf submission
Currently the presumption is that the request construction and its
submission to the GuC are all under the same holding of struct_mutex. We
wish to relax this to separate the request construction and the later
submission to the GuC. This requires us to reserve some space in the
GuC command queue for the future submission. For flexibility to handle
out-of-order request submission we do not preallocate the next slot in
the GuC command queue during request construction, just ensuring that
there is enough space later.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_guc_submission.c | 35 --
drivers/gpu/drm/i915/intel_guc.h | 3 +++
2 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 0eb6b71935cf..55db82190969 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -432,20 +432,23 @@ int i915_guc_wq_check_space(struct drm_i915_gem_request
*request)
{
const size_t wqi_size = sizeof(struct guc_wq_item);
struct i915_guc_client *gc = request->i915->guc.execbuf_client;
- struct guc_process_desc *desc;
+ struct guc_process_desc *desc = gc->client_base + gc->proc_desc_offset;
u32 freespace;
+ int ret;
- GEM_BUG_ON(gc == NULL);
-
- desc = gc->client_base + gc->proc_desc_offset;
-
+ spin_lock(&gc->lock);
freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size);
- if (likely(freespace >= wqi_size))
- return 0;
-
- gc->no_wq_space += 1;
+ freespace -= gc->wq_rsvd;
+ if (likely(freespace >= wqi_size)) {
+ gc->wq_rsvd += wqi_size;
+ ret = 0;
+ } else {
+ gc->no_wq_space++;
+ ret = -EAGAIN;
+ }
+ spin_unlock(&gc->lock);
- return -EAGAIN;
+ return ret;
}
static void guc_add_workqueue_item(struct i915_guc_client *gc,
@@ -480,12 +483,14 @@ static void guc_add_workqueue_item(struct i915_guc_client
*gc,
* workqueue buffer dw by dw.
*/
BUILD_BUG_ON(wqi_size != 16);
+ GEM_BUG_ON(gc->wq_rsvd < wqi_size);
/* postincrement WQ tail for next time */
wq_off = gc->wq_tail;
+ GEM_BUG_ON(wq_off & (wqi_size - 1));
gc->wq_tail += wqi_size;
gc->wq_tail &= gc->wq_size - 1;
- GEM_BUG_ON(wq_off & (wqi_size - 1));
+ gc->wq_rsvd -= wqi_size;
/* WQ starts from the page after doorbell / process_desc */
wq_page = (wq_off + GUC_DB_SIZE) >> PAGE_SHIFT;
@@ -589,6 +594,7 @@ static void i915_guc_submit(struct drm_i915_gem_request *rq)
struct i915_guc_client *client = guc->execbuf_client;
int b_ret;
+ spin_lock(&client->lock);
guc_add_workqueue_item(client, rq);
b_ret = guc_ring_doorbell(client);
@@ -599,6 +605,7 @@ static void i915_guc_submit(struct drm_i915_gem_request *rq)
guc->submissions[engine_id] += 1;
guc->last_seqno[engine_id] = rq->fence.seqno;
+ spin_unlock(&client->lock);
}
/*
@@ -768,6 +775,8 @@ guc_client_alloc(struct drm_i915_private *dev_priv,
if (!client)
return NULL;
+ spin_lock_init(&client->lock);
+
client->owner = ctx;
client->guc = guc;
client->engines = engines;
@@ -1015,9 +1024,11 @@ int i915_guc_submission_enable(struct drm_i915_private
*dev_priv)
engine->submit_request = i915_guc_submit;
/* Replay the current set of previously submitted requests */
- list_for_each_entry(request, &engine->request_list, link)
+ list_for_each_entry(request, &engine->request_list, link) {
+ client->wq_rsvd += sizeof(struct guc_wq_item);
if (i915_sw_fence_done(&request->submit))
i915_guc_submit(request);
+ }
}
return 0;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index c97326269588..27a622824b54 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -68,6 +68,8 @@ struct i915_guc_client {
struct i915_gem_context *owner;
struct intel_guc *guc;
+ spinlock_t lock;
+
uint32_t engines; /* bitmap of (host) engine ids */
uint32_t priority;
uint32_t ctx_index;
@@ -81,6 +83,7 @@ struct i915_guc_client {
uint32_t wq_offset;
uint32_t wq_size;
uint32_t wq_tail;
+ uint32_t wq_rsvd;
uint32_t no_wq_space;
uint32_t b_fail;
int retcode;
--
2.9.3
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[Intel-gfx] [PATCH v2 19/22] drm/i915: Nonblocking request submission
Now that we have fences in place to drive request submission, we can
employ those to queue requests after their dependencies as opposed to
stalling in the middle of an execbuf ioctl. (However, we still choose to
spin before enabling the IRQ as that is faster - though contentious.)
v2: Do the fence ordering first, where we can still fail.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_request.c | 21 +++--
drivers/gpu/drm/i915/i915_gem_request.h | 1 +
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 158f9afca3e8..8b854492afd5 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -475,12 +475,13 @@ i915_gem_request_await_request(struct
drm_i915_gem_request *to,
trace_i915_gem_ring_sync_to(to, from);
if (!i915.semaphores) {
- ret = i915_wait_request(from,
- I915_WAIT_INTERRUPTIBLE |
- I915_WAIT_LOCKED,
- NULL, NO_WAITBOOST);
- if (ret)
- return ret;
+ if (!i915_spin_request(from, TASK_INTERRUPTIBLE, 2)) {
+ ret = i915_sw_fence_await_dma_fence(&to->submit,
+ &from->fence,
+ GFP_KERNEL);
+ if (ret < 0)
+ return ret;
+ }
} else {
ret = to->engine->semaphore.sync_to(to, from);
if (ret)
@@ -575,6 +576,7 @@ void __i915_add_request(struct drm_i915_gem_request
*request, bool flush_caches)
{
struct intel_engine_cs *engine = request->engine;
struct intel_ring *ring = request->ring;
+ struct drm_i915_gem_request *prev;
u32 request_start;
u32 reserved_tail;
int ret;
@@ -629,6 +631,13 @@ void __i915_add_request(struct drm_i915_gem_request
*request, bool flush_caches)
* hangcheck. Hence we apply the barrier to ensure that we do not
* see a more recent value in the hws than we are tracking.
*/
+
+ prev = i915_gem_active_raw(&engine->last_request,
+ &request->i915->drm.struct_mutex);
+ if (prev)
+ i915_sw_fence_await_sw_fence(&request->submit, &prev->submit,
+&request->submitq);
+
request->emitted_jiffies = jiffies;
request->previous_seqno = engine->last_submitted_seqno;
engine->last_submitted_seqno = request->fence.seqno;
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h
b/drivers/gpu/drm/i915/i915_gem_request.h
index 883df3bdb381..974bd7bcc801 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -84,6 +84,7 @@ struct drm_i915_gem_request {
struct intel_signal_node signaling;
struct i915_sw_fence submit;
+ wait_queue_t submitq;
/** GEM sequence number associated with the previous request,
* when the HWS breadcrumb is equal to this the GPU is processing
--
2.9.3
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[Intel-gfx] [PATCH v2 12/22] drm/i915: Replace wait-on-mutex with wait-on-bit in reset worker
Since we have a cooperative mode now with a direct reset, we can avoid
the contention on struct_mutex and instead try then sleep on the
I915_RESET_IN_PROGRESS bit. If the mutex is held and that bit is
cleared, all is fine. Otherwise, we sleep for a bit and try again. In
the worst case we sleep for an extra second waiting for the mutex to be
released (no one touching the GPU is allowed the struct_mutex whilst the
I915_RESET_IN_PROGRESS bit is set). But when we have a direct reset,
this allows us to clean up the reset worker faster.
v2: Remember to call wake_up_bit() after changing (for the faster wakeup
as promised)
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 6 --
drivers/gpu/drm/i915/i915_irq.c | 30 ++
2 files changed, 22 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ff4173e6e298..c1b890dbd6cc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1798,11 +1798,13 @@ int i915_reset(struct drm_i915_private *dev_priv)
intel_sanitize_gt_powersave(dev_priv);
intel_autoenable_gt_powersave(dev_priv);
- return 0;
+out:
+ wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
+ return ret;
error:
set_bit(I915_WEDGED, &error->flags);
- return ret;
+ goto out;
}
static int i915_pm_suspend(struct device *kdev)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2c7cb5041511..699ee2c7a3e4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2497,7 +2497,7 @@ static void i915_reset_and_wakeup(struct drm_i915_private
*dev_priv)
char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
- int ret;
+ int ret = -EAGAIN;
kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
@@ -2512,21 +2512,27 @@ static void i915_reset_and_wakeup(struct
drm_i915_private *dev_priv)
* simulated reset via debugs, so get an RPM reference.
*/
intel_runtime_pm_get(dev_priv);
-
intel_prepare_reset(dev_priv);
- /*
-* All state reset _must_ be completed before we update the
-* reset counter, for otherwise waiters might miss the reset
-* pending state and not properly drop locks, resulting in
-* deadlocks with the reset work.
-*/
- mutex_lock(&dev_priv->drm.struct_mutex);
- ret = i915_reset(dev_priv);
- mutex_unlock(&dev_priv->drm.struct_mutex);
+ do {
+ /*
+* All state reset _must_ be completed before we update the
+* reset counter, for otherwise waiters might miss the reset
+* pending state and not properly drop locks, resulting in
+* deadlocks with the reset work.
+*/
+ if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
+ ret = i915_reset(dev_priv);
+ mutex_unlock(&dev_priv->drm.struct_mutex);
+ }
- intel_finish_reset(dev_priv);
+ /* We need to wait for anyone holding the lock to wakeup */
+ } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags,
+I915_RESET_IN_PROGRESS,
+TASK_UNINTERRUPTIBLE,
+HZ));
+ intel_finish_reset(dev_priv);
intel_runtime_pm_put(dev_priv);
if (ret == 0)
--
2.9.3
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 14/22] drm/i915: Drive request submission through fence callbacks
Drive final request submission from a callback from the fence. This way
the request is queued until all dependencies are resolved, at which
point it is handed to the backend for queueing to hardware. At this
point, no dependencies are set on the request, so the callback is
immediate.
A side-effect of imposing a heavier-irqsafe spinlock for execlist
submission is that we lose the softirq enabling after scheduling the
execlists tasklet. To compensate, we manually kickstart the softirq by
disabling and enabling the bh around the fence signaling.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/i915_gem.c| 3 +++
drivers/gpu/drm/i915/i915_gem_request.c| 25 -
drivers/gpu/drm/i915/i915_gem_request.h| 3 +++
drivers/gpu/drm/i915/i915_guc_submission.c | 3 ++-
drivers/gpu/drm/i915/intel_breadcrumbs.c | 3 +++
drivers/gpu/drm/i915/intel_lrc.c | 5 +++--
drivers/gpu/drm/i915/intel_ringbuffer.h| 8
7 files changed, 46 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 65a69bbe021d..62fcc33325d9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2549,6 +2549,9 @@ i915_gem_find_active_request(struct intel_engine_cs
*engine)
if (i915_gem_request_completed(request))
continue;
+ if (!i915_sw_fence_done(&request->submit))
+ break;
+
return request;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 64c370681a81..c39dd40fb3b9 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -318,6 +318,24 @@ static int i915_gem_get_seqno(struct drm_i915_private
*dev_priv, u32 *seqno)
return 0;
}
+static int __i915_sw_fence_call
+submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
+{
+ struct drm_i915_gem_request *request =
+ container_of(fence, typeof(*request), submit);
+
+ switch (state) {
+ case FENCE_COMPLETE:
+ request->engine->submit_request(request);
+ break;
+
+ case FENCE_FREE:
+ break;
+ }
+
+ return NOTIFY_DONE;
+}
+
/**
* i915_gem_request_alloc - allocate a request structure
*
@@ -396,6 +414,8 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
engine->fence_context,
seqno);
+ i915_sw_fence_init(&req->submit, submit_notify);
+
INIT_LIST_HEAD(&req->active_list);
req->i915 = dev_priv;
req->engine = engine;
@@ -530,7 +550,10 @@ void __i915_add_request(struct drm_i915_gem_request
*request, bool flush_caches)
reserved_tail, ret);
i915_gem_mark_busy(engine);
- engine->submit_request(request);
+
+ local_bh_disable();
+ i915_sw_fence_commit(&request->submit);
+ local_bh_enable(); /* Kick the execlists tasklet if just scheduled */
}
static void reset_wait_queue(wait_queue_head_t *q, wait_queue_t *wait)
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h
b/drivers/gpu/drm/i915/i915_gem_request.h
index def35721e9ed..e141b1cca16a 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -28,6 +28,7 @@
#include
#include "i915_gem.h"
+#include "i915_sw_fence.h"
struct intel_wait {
struct rb_node node;
@@ -82,6 +83,8 @@ struct drm_i915_gem_request {
struct intel_ring *ring;
struct intel_signal_node signaling;
+ struct i915_sw_fence submit;
+
/** GEM sequence number associated with the previous request,
* when the HWS breadcrumb is equal to this the GPU is processing
* this request.
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index d5a4e9edccc5..0eb6b71935cf 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1016,7 +1016,8 @@ int i915_guc_submission_enable(struct drm_i915_private
*dev_priv)
/* Replay the current set of previously submitted requests */
list_for_each_entry(request, &engine->request_list, link)
- i915_guc_submit(request);
+ if (i915_sw_fence_done(&request->submit))
+ i915_guc_submit(request);
}
return 0;
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 2491e4c1eaf0..9bad14d22c95 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -462,7 +462,10 @@ static int intel_breadcrumbs_signaler(void *arg)
*/
intel_engine_remove_wait(
[Intel-gfx] [PATCH v2 05/22] drm/i915: Reorder submitting the requests to ELSP
Just rearrange the code to reduce churn in the next patch.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 76
1 file changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index a6b9033203e5..7bb743f79d18 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -328,32 +328,18 @@ uint64_t intel_lr_context_descriptor(struct
i915_gem_context *ctx,
return ctx->engine[engine->id].lrc_desc;
}
-static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
-struct drm_i915_gem_request *rq1)
+static inline void
+execlists_context_status_change(struct drm_i915_gem_request *rq,
+ unsigned long status)
{
- struct intel_engine_cs *engine = rq0->engine;
- struct drm_i915_private *dev_priv = rq0->i915;
- u32 __iomem *elsp =
- dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine));
- u64 desc[2];
-
- if (rq1) {
- desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine);
- rq1->elsp_submitted++;
- } else {
- desc[1] = 0;
- }
-
- desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->engine);
- rq0->elsp_submitted++;
-
- /* You must always write both descriptors in the order below. */
- writel(upper_32_bits(desc[1]), elsp);
- writel(lower_32_bits(desc[1]), elsp);
+ /*
+* Only used when GVT-g is enabled now. When GVT-g is disabled,
+* The compiler should eliminate this function as dead-code.
+*/
+ if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
+ return;
- writel(upper_32_bits(desc[0]), elsp);
- /* The context is automatically loaded after the following */
- writel(lower_32_bits(desc[0]), elsp);
+ atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq);
}
static void
@@ -382,6 +368,34 @@ static void execlists_update_context(struct
drm_i915_gem_request *rq)
execlists_update_context_pdps(ppgtt, reg_state);
}
+static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
+struct drm_i915_gem_request *rq1)
+{
+ struct intel_engine_cs *engine = rq0->engine;
+ struct drm_i915_private *dev_priv = rq0->i915;
+ u32 __iomem *elsp =
+ dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine));
+ u64 desc[2];
+
+ if (rq1) {
+ desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine);
+ rq1->elsp_submitted++;
+ } else {
+ desc[1] = 0;
+ }
+
+ desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->engine);
+ rq0->elsp_submitted++;
+
+ /* You must always write both descriptors in the order below. */
+ writel(upper_32_bits(desc[1]), elsp);
+ writel(lower_32_bits(desc[1]), elsp);
+
+ writel(upper_32_bits(desc[0]), elsp);
+ /* The context is automatically loaded after the following */
+ writel(lower_32_bits(desc[0]), elsp);
+}
+
static void execlists_elsp_submit_contexts(struct drm_i915_gem_request *rq0,
struct drm_i915_gem_request *rq1)
{
@@ -402,20 +416,6 @@ static void execlists_elsp_submit_contexts(struct
drm_i915_gem_request *rq0,
spin_unlock_irq(&dev_priv->uncore.lock);
}
-static inline void execlists_context_status_change(
- struct drm_i915_gem_request *rq,
- unsigned long status)
-{
- /*
-* Only used when GVT-g is enabled now. When GVT-g is disabled,
-* The compiler should eliminate this function as dead-code.
-*/
- if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
- return;
-
- atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq);
-}
-
static void execlists_unqueue(struct intel_engine_cs *engine)
{
struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
--
2.9.3
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 13/22] drm/i915: Update reset path to fix incomplete requests
Update reset path in preparation for engine reset which requires
identification of incomplete requests and associated context and fixing
their state so that engine can resume correctly after reset.
The request that caused the hang will be skipped and head is reset to the
start of breadcrumb. This allows us to resume from where we left-off.
Since this request didn't complete normally we also need to cleanup elsp
queue manually. This is vital if we employ nonblocking request
submission where we may have a web of dependencies upon the hung request
and so advancing the seqno manually is no longer trivial.
ABI: gem_reset_stats / DRM_IOCTL_I915_GET_RESET_STATS
We change the way we count pending batches. Only the active context
involved in the reset is marked as either innocent or guilty, and not
mark the entire world as pending. By inspection this only affects
igt/gem_reset_stats (which assumes implementation details) and not
piglit.
ARB_robustness gives this guide on how we expect the user of this
interface to behave:
* Provide a mechanism for an OpenGL application to learn about
graphics resets that affect the context. When a graphics reset
occurs, the OpenGL context becomes unusable and the application
must create a new context to continue operation. Detecting a
graphics reset happens through an inexpensive query.
And with regards to the actual meaning of the reset values:
Certain events can result in a reset of the GL context. Such a reset
causes all context state to be lost. Recovery from such events
requires recreation of all objects in the affected context. The
current status of the graphics reset state is returned by
enum GetGraphicsResetStatusARB();
The symbolic constant returned indicates if the GL context has been
in a reset state at any point since the last call to
GetGraphicsResetStatusARB. NO_ERROR indicates that the GL context
has not been in a reset state since the last call.
GUILTY_CONTEXT_RESET_ARB indicates that a reset has been detected
that is attributable to the current GL context.
INNOCENT_CONTEXT_RESET_ARB indicates a reset has been detected that
is not attributable to the current GL context.
UNKNOWN_CONTEXT_RESET_ARB indicates a detected graphics reset whose
cause is unknown.
The language here is explicit in that we must mark up the guilty batch,
but is loose enough for us to relax the innocent (i.e. pending)
accounting as only the active batches are involved with the reset.
In the future, we are looking towards single engine resetting (with
minimal locking), where it seems inappropriate to mark the entire world
as innocent since the reset occurred on a different engine. Reducing the
information available means we only have to encounter the pain once, and
also reduces the information leaking from one context to another.
v2: Legacy ringbuffer submission required a reset following hibernation,
or else we restore stale values to the RING_HEAD and walked over
stolen garbage.
v3: GuC requires replaying the requests after a reset.
v4: Restore engine IRQ after reset (so waiters will be woken!)
Rearm hangcheck if resetting with a waiter.
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Arun Siluvery
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c| 8 +-
drivers/gpu/drm/i915/i915_drv.h| 5 +-
drivers/gpu/drm/i915/i915_gem.c| 123 +
drivers/gpu/drm/i915/i915_gem_context.c| 16
drivers/gpu/drm/i915/i915_guc_submission.c | 8 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 15 +++-
drivers/gpu/drm/i915/intel_lrc.c | 49 ++--
drivers/gpu/drm/i915/intel_lrc.h | 3 +-
drivers/gpu/drm/i915/intel_ringbuffer.c| 47 +++
drivers/gpu/drm/i915/intel_ringbuffer.h| 7 +-
10 files changed, 183 insertions(+), 98 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c1b890dbd6cc..2b0727d1467d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -559,7 +559,6 @@ static void i915_gem_fini(struct drm_device *dev)
}
mutex_lock(&dev->struct_mutex);
- i915_gem_reset(dev);
i915_gem_cleanup_engines(dev);
i915_gem_context_fini(dev);
mutex_unlock(&dev->struct_mutex);
@@ -1579,7 +1578,7 @@ static int i915_drm_resume(struct drm_device *dev)
mutex_lock(&dev->struct_mutex);
if (i915_gem_init_hw(dev)) {
DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
- set_bit(I915_WEDGED, &dev_priv->gpu_error.flags);
+ i915_gem_set_wedged(dev_priv);
}
mutex_unlock(&dev->struct_mutex);
@@ -1756,8 +1755,6 @@ int i915_reset(struct drm_i915_private *dev_priv)
pr_notice("drm/i915: Resetting chip after gpu hang\n");
- i915_gem_reset(dev);
-
ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
[Intel-gfx] [PATCH v2 20/22] drm/i915: Serialise execbuf operation after a dma-buf reservation object
Now that we can wait upon fences before emitting the request, it becomes
trivial to wait upon any implicit fence provided by the dma-buf
reservation object.
Testcase: igt/prime_vgem/fence-wait
Signed-off-by: Chris Wilson
Reviewed-by: John Harrison
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index ccaf15ba4e32..2c5de906315c 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1131,6 +1131,7 @@ i915_gem_execbuffer_move_to_gpu(struct
drm_i915_gem_request *req,
list_for_each_entry(vma, vmas, exec_list) {
struct drm_i915_gem_object *obj = vma->obj;
+ struct reservation_object *resv;
if (obj->flags & other_rings) {
ret = i915_gem_request_await_object
@@ -1139,6 +1140,16 @@ i915_gem_execbuffer_move_to_gpu(struct
drm_i915_gem_request *req,
return ret;
}
+ resv = i915_gem_object_get_dmabuf_resv(obj);
+ if (resv) {
+ ret = i915_sw_fence_await_reservation
+ (&req->submit, resv, &i915_fence_ops,
+obj->base.pending_write_domain,
+GFP_KERNEL | __GFP_NOWARN);
+ if (ret < 0)
+ return ret;
+ }
+
if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
i915_gem_clflush_object(obj, false);
}
--
2.9.3
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 16/22] drm/i915: Prepare object synchronisation for asynchronicity
We are about to specialize object synchronisation to enable nonblocking
execbuf submission. First we make a copy of the current object
synchronisation for execbuffer. The general i915_gem_object_sync() will
be removed following the removal of CS flips in the near future.
Signed-off-by: Chris Wilson
Reviewed-by: John Harrison
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h| 2 -
drivers/gpu/drm/i915/i915_gem.c| 91 --
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 +-
drivers/gpu/drm/i915/i915_gem_request.c| 87
drivers/gpu/drm/i915/i915_gem_request.h| 5 ++
drivers/gpu/drm/i915/intel_display.c | 2 +-
6 files changed, 95 insertions(+), 95 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a63bf820aa8f..70b2446c9075 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3220,8 +3220,6 @@ i915_gem_obj_finish_shmem_access(struct
drm_i915_gem_object *obj)
}
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
-int i915_gem_object_sync(struct drm_i915_gem_object *obj,
-struct drm_i915_gem_request *to);
void i915_vma_move_to_active(struct i915_vma *vma,
struct drm_i915_gem_request *req,
unsigned int flags);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 62fcc33325d9..743518f5b49f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2816,97 +2816,6 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
return ret;
}
-static int
-__i915_gem_object_sync(struct drm_i915_gem_request *to,
- struct drm_i915_gem_request *from)
-{
- int ret;
-
- if (to->engine == from->engine)
- return 0;
-
- if (!i915.semaphores) {
- ret = i915_wait_request(from,
- from->i915->mm.interruptible |
- I915_WAIT_LOCKED,
- NULL,
- NO_WAITBOOST);
- if (ret)
- return ret;
- } else {
- int idx = intel_engine_sync_index(from->engine, to->engine);
- if (from->fence.seqno <=
from->engine->semaphore.sync_seqno[idx])
- return 0;
-
- trace_i915_gem_ring_sync_to(to, from);
- ret = to->engine->semaphore.sync_to(to, from);
- if (ret)
- return ret;
-
- from->engine->semaphore.sync_seqno[idx] = from->fence.seqno;
- }
-
- return 0;
-}
-
-/**
- * i915_gem_object_sync - sync an object to a ring.
- *
- * @obj: object which may be in use on another ring.
- * @to: request we are wishing to use
- *
- * This code is meant to abstract object synchronization with the GPU.
- * Conceptually we serialise writes between engines inside the GPU.
- * We only allow one engine to write into a buffer at any time, but
- * multiple readers. To ensure each has a coherent view of memory, we must:
- *
- * - If there is an outstanding write request to the object, the new
- * request must wait for it to complete (either CPU or in hw, requests
- * on the same ring will be naturally ordered).
- *
- * - If we are a write request (pending_write_domain is set), the new
- * request must wait for outstanding read requests to complete.
- *
- * Returns 0 if successful, else propagates up the lower layer error.
- */
-int
-i915_gem_object_sync(struct drm_i915_gem_object *obj,
-struct drm_i915_gem_request *to)
-{
- struct i915_gem_active *active;
- unsigned long active_mask;
- int idx;
-
- lockdep_assert_held(&obj->base.dev->struct_mutex);
-
- active_mask = i915_gem_object_get_active(obj);
- if (!active_mask)
- return 0;
-
- if (obj->base.pending_write_domain) {
- active = obj->last_read;
- } else {
- active_mask = 1;
- active = &obj->last_write;
- }
-
- for_each_active(active_mask, idx) {
- struct drm_i915_gem_request *request;
- int ret;
-
- request = i915_gem_active_peek(&active[idx],
- &obj->base.dev->struct_mutex);
- if (!request)
- continue;
-
- ret = __i915_gem_object_sync(to, request);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
static void __i915_vma_iounmap(struct i915_vma *vma)
{
GEM_BUG_ON(i915_vma_is_pinned(vma));
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 9432d4ce9ffb..ccaf15ba
[Intel-gfx] [PATCH v2 11/22] drm/i915: Perform a direct reset of the GPU from the waiter
If a waiter is holding the struct_mutex, then the reset worker cannot
reset the GPU until the waiter returns. We do not want to return -EAGAIN
form i915_wait_request as that breaks delicate operations like
i915_vma_unbind() which often cannot be restarted easily, and returning
-EIO is just as useless (and has in the past proven dangerous). The
remaining WARN_ON(i915_wait_request) serve as a valuable reminder that
handling errors from an indefinite wait are tricky.
We can keep the current semantic that knowing after a reset is complete,
so is the request, by performing the reset ourselves if we hold the
mutex.
uevent emission is still handled by the reset worker, so it may appear
slightly out of order with respect to the actual reset (and concurrent
use of the device).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 11 ++-
drivers/gpu/drm/i915/i915_drv.h | 15 +++
drivers/gpu/drm/i915/i915_gem_request.c | 29 +
drivers/gpu/drm/i915/i915_irq.c | 2 ++
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ---
5 files changed, 40 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 47a676d859db..ff4173e6e298 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1729,6 +1729,8 @@ int i915_resume_switcheroo(struct drm_device *dev)
* Reset the chip. Useful if a hang is detected. Returns zero on successful
* reset or otherwise an error code.
*
+ * Caller must hold the struct_mutex.
+ *
* Procedure is fairly simple:
* - reset the chip using the reset reg
* - re-init context state
@@ -1743,7 +1745,10 @@ int i915_reset(struct drm_i915_private *dev_priv)
struct i915_gpu_error *error = &dev_priv->gpu_error;
int ret;
- mutex_lock(&dev->struct_mutex);
+ lockdep_assert_held(&dev->struct_mutex);
+
+ if (!test_and_clear_bit(I915_RESET_IN_PROGRESS, &error->flags))
+ return test_bit(I915_WEDGED, &error->flags) ? -EIO : 0;
/* Clear any previous failed attempts at recovery. Time to try again. */
__clear_bit(I915_WEDGED, &error->flags);
@@ -1784,9 +1789,6 @@ int i915_reset(struct drm_i915_private *dev_priv)
goto error;
}
- clear_bit(I915_RESET_IN_PROGRESS, &error->flags);
- mutex_unlock(&dev->struct_mutex);
-
/*
* rps/rc6 re-init is necessary to restore state lost after the
* reset and the re-install of gt irqs. Skip for ironlake per
@@ -1800,7 +1802,6 @@ int i915_reset(struct drm_i915_private *dev_priv)
error:
set_bit(I915_WEDGED, &error->flags);
- mutex_unlock(&dev->struct_mutex);
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dd73c00cd774..2e2fd8a77233 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3862,7 +3862,9 @@ wait_remaining_ms_from_jiffies(unsigned long
timestamp_jiffies, int to_wait_ms)
schedule_timeout_uninterruptible(remaining_jiffies);
}
}
-static inline bool __i915_request_irq_complete(struct drm_i915_gem_request
*req)
+
+static inline bool
+__i915_request_irq_complete(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
@@ -3924,17 +3926,6 @@ static inline bool __i915_request_irq_complete(struct
drm_i915_gem_request *req)
return true;
}
- /* We need to check whether any gpu reset happened in between
-* the request being submitted and now. If a reset has occurred,
-* the seqno will have been advance past ours and our request
-* is complete. If we are in the process of handling a reset,
-* the request is effectively complete as the rendering will
-* be discarded, but we need to return in order to drop the
-* struct_mutex.
-*/
- if (i915_reset_in_progress(&req->i915->gpu_error))
- return true;
-
return false;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 5f89801e6a16..64c370681a81 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -533,6 +533,16 @@ void __i915_add_request(struct drm_i915_gem_request
*request, bool flush_caches)
engine->submit_request(request);
}
+static void reset_wait_queue(wait_queue_head_t *q, wait_queue_t *wait)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&q->lock, flags);
+ if (list_empty(&wait->task_list))
+ __add_wait_queue(q, wait);
+ spin_unlock_irqrestore(&q->lock, flags);
+}
+
static unsigned long local_clock_us(unsigned int *cpu)
{
unsigned long t;
@@ -710,6 +720,25 @@ wakeup:
if (__i915_request_irq_complete(req))
break;
+
Re: [Intel-gfx] i915 WARNING: Missing switch case (16) in gen6_check_mailbox_status
On Mon, 29 Aug 2016, Meelis Roos wrote: > Tried 4.8-rc4 on my i5-2400 PC, got this warning: Fixed in drm-intel-fixes by commit fc2780b66b15092ac68272644a522c1624c48547 Author: Chris Wilson Date: Fri Aug 26 11:59:26 2016 +0100 drm/i915: Add GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE to SNB BR, Jani. > > [ 14.579557] i915 :00:02.0: fb0: inteldrmfb frame buffer device > [ 15.847321] [ cut here ] > [ 15.847346] WARNING: CPU: 0 PID: 208 at > drivers/gpu/drm/i915/intel_pm.c:7866 sandybridge_pcode_write+0x109/0x1f0 > [i915] > [ 15.847348] Missing switch case (16) in gen6_check_mailbox_status > [ 15.847349] Modules linked in: cpufreq_powersave cpufreq_userspace > cpufreq_conservative joydev hid_generic usbhid hid x86_pkg_temp_thermal > kvm_intel kvm irqbypass crc32c_intel aesni_intel snd_hda_codec_realtek > snd_hda_codec_generic iTCO_wdt i915 aes_x86_64 iTCO_vendor_support > glue_helper lrw ablk_helper cryptd video i2c_algo_bit drm_kms_helper psmouse > pcspkr syscopyarea sysfillrect sysimgblt fb_sys_fops ehci_pci ehci_hcd > snd_hda_intel xhci_pci xhci_hcd e1000e snd_hda_codec snd_hwdep usbcore drm > snd_hda_core usb_common i2c_i801 ptp pps_core i2c_smbus snd_pcm_oss > snd_mixer_oss snd_pcm snd_timer evdev snd tpm_tis lpc_ich parport_pc > tpm_tis_core mfd_core parport nuvoton_cir rc_core tpm soundcore floppy > w83627ehf hwmon_vid coretemp hwmon eeprom i2c_core loop ip_tables x_tables > autofs4 > [ 15.847395] CPU: 0 PID: 208 Comm: kworker/0:2 Not tainted 4.8.0-rc4 #213 > [ 15.847396] Hardware name: /DQ67OW, BIOS > SWQ6710H.86A.0066.2012.1105.1504 11/05/2012 > [ 15.847412] Workqueue: events intel_gen6_powersave_work [i915] > [ 15.847414] 812d8198 88023191fd70 > > [ 15.847417] 81056d1e 88022ea4 88023191fdc0 > > [ 15.847419] 88022ea4a3c8 88022ea487c0 088023e21ba0 > 81056d8f > [ 15.847422] Call Trace: > [ 15.847427] [] ? dump_stack+0x46/0x5e > [ 15.847429] [] ? __warn+0xbe/0xe0 > [ 15.847431] [] ? warn_slowpath_fmt+0x4f/0x60 > [ 15.847446] [] ? sandybridge_pcode_write+0x109/0x1f0 > [i915] > [ 15.847459] [] ? intel_gen6_powersave_work+0x2a8/0x1400 > [i915] > [ 15.847462] [] ? process_one_work+0x1eb/0x480 > [ 15.847465] [] ? worker_thread+0x47/0x4c0 > [ 15.847467] [] ? __schedule+0x1d7/0x660 > [ 15.847469] [] ? process_one_work+0x480/0x480 > [ 15.847472] [] ? kthread+0xbd/0xe0 > [ 15.847475] [] ? ret_from_fork+0x1f/0x40 > [ 15.847478] [] ? kthread_worker_fn+0x160/0x160 > [ 15.847487] ---[ end trace ad9e991297d99be1 ]--- -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 22/22] drm/i915: Support explicit fencing for execbuf
Now that the user can opt-out of implicit fencing, we need to give them
back control over the fencing. We employ sync_file to wrap our
drm_i915_gem_request and provide an fd that userspace can merge with
other sync_file fds and pass back to the kernel to wait upon before
future execution.
Testcase: igt/gem_exec_fence
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/i915_drv.c| 3 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 53 +++---
drivers/gpu/drm/i915/i915_gem_request.c| 36
drivers/gpu/drm/i915/i915_gem_request.h| 2 ++
include/uapi/drm/i915_drm.h| 36 +++-
6 files changed, 124 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 7769e469118f..319ca27ea719 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -18,6 +18,7 @@ config DRM_I915
select INPUT if ACPI
select ACPI_VIDEO if ACPI
select ACPI_BUTTON if ACPI
+ select SYNC_FILE
help
Choose this option if you have a system that has "Intel Graphics
Media Accelerator" or "HD Graphics" integrated graphics,
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index caa852521bbd..2b9f483edc31 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -333,6 +333,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
case I915_PARAM_HAS_COHERENT_PHYS_GTT:
case I915_PARAM_HAS_EXEC_SOFTPIN:
case I915_PARAM_HAS_EXEC_ASYNC:
+ case I915_PARAM_HAS_EXEC_FENCE:
/* For the time being all of these are always true;
* if some supported hardware does not have one of these
* features this value needs to be provided from
@@ -2529,7 +2530,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
- DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2,
DRM_AUTH|DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2,
DRM_AUTH|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl,
DRM_AUTH|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl,
DRM_AUTH|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl,
DRM_AUTH|DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index a8722abcd7ac..102a99d150df 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -28,6 +28,7 @@
#include
#include
+#include
#include
#include
@@ -1632,6 +1633,9 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
struct i915_execbuffer_params *params = ¶ms_master;
const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
u32 dispatch_flags;
+ struct fence *in_fence = NULL;
+ struct sync_file *out_fence = NULL;
+ int out_fence_fd = -1;
int ret;
bool need_relocs;
@@ -1675,6 +1679,23 @@ i915_gem_do_execbuffer(struct drm_device *dev, void
*data,
dispatch_flags |= I915_DISPATCH_RS;
}
+ if (args->flags & I915_EXEC_FENCE_IN) {
+ in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
+ if (!in_fence) {
+ ret = -EINVAL;
+ goto pre_mutex_err;
+ }
+ }
+
+ if (args->flags & I915_EXEC_FENCE_OUT) {
+ out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
+ if (out_fence_fd < 0) {
+ ret = out_fence_fd;
+ out_fence_fd = -1;
+ goto pre_mutex_err;
+ }
+ }
+
/* Take a local wakeref for preparing to dispatch the execbuf as
* we expect to access the hardware fairly frequently in the
* process. Upon first dispatch, we acquire another prolonged
@@ -1819,6 +1840,20 @@ i915_gem_do_execbuffer(struct drm_device *dev, void
*data,
goto err_batch_unpin;
}
+ if (in_fence) {
+ ret = i915_gem_request_await_fence(params->request, in_fence);
+ if (ret < 0)
+ goto err_request;
+ }
+
+ if (out_fence_fd != -1) {
+ out_fence =
sync_file_create(fence_get(¶ms->request->fence));
+ if (!out_fence) {
+ ret = -ENOMEM;
+ goto err_request;
+ }
+ }
+
Re: [Intel-gfx] [RFC] Idleness DRRS test
On Wed, Aug 31, 2016 at 01:46:03PM +0530, Nautiyal Ankit wrote:
> From: aknautiy
>
> Idleness DRRS:
> By default the DRRS state will be at DRRS_HIGH_RR. When a Display
> content is Idle for more than 1Sec Idleness will be declared and
> DRRS_LOW_RR will be invoked, changing the refresh rate to the
> lower most refresh rate supported by the panel. As soon as there
> is a display content change there will be a DRRS state transition
> as DRRS_LOW_RR--> DRRS_HIGH_RR, changing the refresh rate to the
> highest refresh rate supported by the panel.
>
> To test this, Idleness DRRS IGT will probe the DRRS state at below
> instances and compare with the expected state.
>
> InstanceExpected State
> 1. Immediately after rendering the still imageDRRS_HIGH_RR
> 2. After a delay of 1.2SecDRRS_LOW_RR
> 3. After changing the frame bufferDRRS_HIGH_RR
> 4. After a delay of 1.2SecDRRS_LOW_RR
> 5. After changing the frame bufferDRRS_HIGH_RR
> 6. After a delay of 1.2SecDRRS_LOW_RR
>
> The test checks the driver DRRS state from the debugfs entry. To check the
> actual refresh-rate, a separate thread counts the number of vblanks
> received per sec. The refresh-rate calculated is checked against the
> expected refresh-rate with a tolerance value of 2.
>
> This patch is a continuation of the earlier work
> https://patchwork.freedesktop.org/patch/45472/ towards igt for idleness
>
> DRRS. The code is tested on Broxton BXT_T platform.
>
> Signed-off-by: aknautiy
> ---
> tests/Makefile.sources | 1 +
> tests/kms_drrs.c | 614
> +
> 2 files changed, 615 insertions(+)
> create mode 100644 tests/kms_drrs.c
>
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> index a837977..5f31521 100644
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -91,6 +91,7 @@ TESTS_progs_M = \
> kms_cursor_crc \
> kms_cursor_legacy \
> kms_draw_crc \
> + kms_drrs \
> kms_fbc_crc \
> kms_fbcon_fbt \
> kms_flip \
> diff --git a/tests/kms_drrs.c b/tests/kms_drrs.c
> new file mode 100644
> index 000..fbe78c5
> --- /dev/null
> +++ b/tests/kms_drrs.c
> @@ -0,0 +1,614 @@
> +/*
> + * Copyright © 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include "drmtest.h"
> +#include "igt_debugfs.h"
> +#include "igt_kms.h"
> +#include "intel_chipset.h"
> +#include "intel_batchbuffer.h"
> +#include "ioctl_wrappers.h"
> +#include
> +#include
> +#include
> +#include
> +IGT_TEST_DESCRIPTION(
> +"Performs write operations and then waits for DRRS to invoke the"
> +"Low Refresh Rate and then disturbs the contents of the screen once"
> +"again hence DRRS revert back to High Refresh Rate(Default).");
> +
> +#define DRRS_STATUS_BYTES_CNT1000
> +#define SET 1
> +#define RESET0
> +
> +/*
> + * Structure to store data to create 2 framebuffers, fb[0] and fb[1] on a
> given
> + * display. To disturb the content of the screen, we replace fb[0] by fb[1]
> and
> + * vice versa.
> + */
> +typedef struct {
> + int drm_fd;
> + uint32_t devid;
> + uint32_t handle[2];
> + igt_display_t display;
> + igt_output_t *output;
> + enum pipe pipe;
> + igt_plane_t *primary;
> + struct igt_fb fb[2];
> + uint32_t fb_id[2];
> +} data_t;
> +
> +/*
> + * Structure to count vblank and note the starting time of the counter
> + */
> +typedef struct {
> + unsigned int vbl_count;
> + struct timeval start;
> +} vbl_info;
> +
> +/*
> + * Condition variables,mutex, and shared variables for thread synchronization
> + */
> +pthread_mutex_t rr_mutex;
> +
Re: [Intel-gfx] [PATCH v4 10/25] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
On 07/09/16 14:52, kbuild test robot wrote:
Hi Tom,
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20160907]
[cannot apply to v4.8-rc5]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
[Suggest to use git(>=2.9.0) format-patch --base= (or --base=auto for
convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]
url:
https://github.com/0day-ci/linux/commits/Sagar-Arun-Kamble/Add-support-for-GuC-based-SLPC/20160907-201335
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/intel_slpc.c: In function 'slpc_get_slice_count':
drivers/gpu/drm/i915/intel_slpc.c:50:37: error: 'const struct
intel_device_info' has no member named 'slice_total'
slice_count = INTEL_INFO(dev_priv)->slice_total;
^~
vim +50 drivers/gpu/drm/i915/intel_slpc.c
44
45 static unsigned int slpc_get_slice_count(struct drm_i915_private
*dev_priv)
46 {
47 unsigned int slice_count = 1;
48
49 if (IS_SKYLAKE(dev_priv))
> 50 slice_count = INTEL_INFO(dev_priv)->slice_total;
51
52 return slice_count;
53 }
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Is this the right fix?
diff --git a/drivers/gpu/drm/i915/intel_slpc.c
b/drivers/gpu/drm/i915/intel_slpc.c
index 1a3a515..77a316e 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -207,7 +207,7 @@ static unsigned int slpc_get_slice_count(struct
drm_i915_private *dev_priv)
unsigned int slice_count = 1;
if (IS_SKYLAKE(dev_priv))
- slice_count = INTEL_INFO(dev_priv)->slice_total;
+ slice_count =
hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
return slice_count;
}
.Dave.
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Linux 4.8-rc?: WARNING: at drivers/gpu/drm/i915/intel_pm.c:7866 sandybridge_pcode_write Missing switch case (16) in gen6_check_mailbox_status
On Tue, 06 Sep 2016, li...@eikelenboom.it wrote: > On 2016-09-06 11:25, Jani Nikula wrote: >> On Tue, 06 Sep 2016, li...@eikelenboom.it wrote: >>> L.S., >>> >>> Since one of the last 4.8 RC's i'm getting the warning below when >>> booting on my sandybridge based thinkpad. >>> From what it seems the machine still works fine though. >> >> What does 'lspci -nns 2' say for you? > > 00:02.0 VGA compatible controller [0300]: Intel Corporation 2nd > Generation Core Processor Family Integrated Graphics Controller > [8086:0126] (rev 09) Fixed in drm-intel-fixes by commit fc2780b66b15092ac68272644a522c1624c48547 Author: Chris Wilson Date: Fri Aug 26 11:59:26 2016 +0100 drm/i915: Add GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE to SNB BR, Jani. -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm: squash lines for simple wrapper functions
Hi Jani,
2016-09-07 17:34 GMT+09:00 Jani Nikula :
> On Wed, 07 Sep 2016, Masahiro Yamada wrote:
>> Remove unneeded variables and assignments.
>>
>> Signed-off-by: Masahiro Yamada
>
> ...
>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>> b/drivers/gpu/drm/i915/i915_drv.c
>> index 95ddd56..59d029d 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -1361,13 +1361,7 @@ void i915_driver_unload(struct drm_device *dev)
>>
>> static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
>> {
>> - int ret;
>> -
>> - ret = i915_gem_open(dev, file);
>> - if (ret)
>> - return ret;
>> -
>> - return 0;
>> + return i915_gem_open(dev, file);
>> }
>
> Seems to me the whole function could be replaced by a direct use of
> i915_gem_open().
Good catch.
Shall I send v2?
Or, should it be done in a separate follow-up patch?
(I hope you can do it in this case.)
--
Best Regards
Masahiro Yamada
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[Intel-gfx] [PATCH v2] tools/intel_guc_logger: Utility for capturing GuC firmware logs in a file
From: Akash Goel
This patch provides a test utility which helps capture GuC firmware logs and
then dump them to file.
The logs are pulled from a debugfs file '/sys/kernel/debug/dri/guc_log' and
stored into a file '/tmp/guc_log_dump.dat', the name of the output file can
be changed through a command line argument.
The utility goes into an infinite loop where it waits for the arrival of new
logs and as soon as new set of logs are produced it captures them in its local
buffer which is then flushed out to the file on disk.
Any time when logging needs to be ended, User can stop this utility (CTRL+C).
Before entering into a loop, it first discards whatever logs are present in
the debugfs file.
This way User can first launch this utility and then start a workload/activity
for which GuC firmware logs are to be actually captured and keep running the
utility for as long as its needed, like once the workload is over this utility
can be forcefully stopped.
If the logging wasn't enabled on GuC side by the Driver at boot time, utility
will first enable the logging and later on when it is stopped (CTRL+C) it will
also pause the logging on GuC side.
v2:
- Use combination of alarm system call & SIGALRM signal to run the utility
for required duration. (Tvrtko)
- Fix inconsistencies, do minor cleanup and refactoring. (Tvrtko)
Cc: Tvrtko Ursulin
Signed-off-by: Akash Goel
---
tools/Makefile.sources | 1 +
tools/intel_guc_logger.c | 425 +++
2 files changed, 426 insertions(+)
create mode 100644 tools/intel_guc_logger.c
diff --git a/tools/Makefile.sources b/tools/Makefile.sources
index 2bb6c8e..be58871 100644
--- a/tools/Makefile.sources
+++ b/tools/Makefile.sources
@@ -19,6 +19,7 @@ tools_prog_lists =\
intel_gpu_time \
intel_gpu_top \
intel_gtt \
+ intel_guc_logger\
intel_infoframes\
intel_l3_parity \
intel_lid \
diff --git a/tools/intel_guc_logger.c b/tools/intel_guc_logger.c
new file mode 100644
index 000..6e03282
--- /dev/null
+++ b/tools/intel_guc_logger.c
@@ -0,0 +1,425 @@
+
+#define _GNU_SOURCE /* For using O_DIRECT */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "igt.h"
+
+#define MB(x) ((uint64_t)(x) * 1024 * 1024)
+#ifndef PAGE_SIZE
+ #define PAGE_SIZE 4096
+#endif
+#define SUBBUF_SIZE (19*PAGE_SIZE)
+/* Need large buffering from logger side to hide the DISK IO latency, Driver
+ * can only store 8 snapshots of GuC log buffer in relay.
+ */
+#define NUM_SUBBUFS 100
+
+#define RELAY_FILE_NAME "guc_log"
+#define DEFAULT_OUTPUT_FILE_NAME "guc_log_dump.dat"
+#define CONTROL_FILE_NAME "i915_guc_log_control"
+
+char *read_buffer;
+char *out_filename;
+int poll_timeout = 2; /* by default 2ms timeout */
+pthread_mutex_t mutex;
+pthread_t flush_thread;
+int verbosity_level = 3; /* by default capture logs at max verbosity */
+uint32_t produced, consumed;
+uint64_t total_bytes_written;
+int num_buffers = NUM_SUBBUFS;
+int relay_fd, outfile_fd = -1;
+bool stop_logging, discard_oldlogs;
+uint32_t test_duration, max_filesize;
+pthread_cond_t underflow_cond, overflow_cond;
+
+static void guc_log_control(bool enable_logging)
+{
+ int control_fd;
+ char data[19];
+ uint64_t val;
+ int ret;
+
+ control_fd = igt_debugfs_open(CONTROL_FILE_NAME, O_WRONLY);
+ igt_assert_f(control_fd >= 0, "couldn't open the guc log control file");
+
+ val = enable_logging ? ((verbosity_level << 4) | 0x1) : 0;
+
+ ret = snprintf(data, sizeof(data), "0x%" PRIx64, val);
+ igt_assert(ret > 2 && ret < sizeof(data));
+
+ ret = write(control_fd, data, ret);
+ igt_assert_f(ret > 0, "couldn't write to the log control file");
+
+ close(control_fd);
+}
+
+static void int_sig_handler(int sig)
+{
+ igt_info("received signal %d\n", sig);
+
+ stop_logging = true;
+}
+
+static void pull_leftover_data(void)
+{
+ unsigned int bytes_read = 0;
+ int ret;
+
+ do {
+ /* Read the logs from relay buffer */
+ ret = read(relay_fd, read_buffer, SUBBUF_SIZE);
+ if (!ret)
+ break;
+
+ igt_assert_f(ret > 0, "failed to read from the guc log file");
+ igt_assert_f(ret == SUBBUF_SIZE, "invalid read from relay
file");
+
+ bytes_read += ret;
+
+ if (outfile_fd >= 0) {
+ ret = write(outfile_fd, read_buffer, SUBBUF_SIZE);
+ igt_assert_f(ret == SUBBUF_SIZE, "couldn't dump the
logs in a file");
+ total_bytes_written += ret;
+ }
+ } while(1);
+
+ igt_debug("%u bytes flushed\n", bytes_read);
+}
+
+static int num_filled_bufs(void)
+{
+
Re: [Intel-gfx] [PATCH] drm: squash lines for simple wrapper functions
> -Original Message-
> From: Masahiro Yamada [mailto:yamada.masah...@socionext.com]
> Sent: Tuesday, September 06, 2016 7:04 PM
> To: David Airlie; dri-de...@lists.freedesktop.org
> Cc: Masahiro Yamada; Gustavo Padovan; Yakir Yang; Huang, Ray; Deucher,
> Alexander; Liu, Monk; Zhou, David(ChunMing); Daniel Vetter; Heiko
> Stuebner; Huang, JinHuiEric; Cui, Flora; Inki Dae; Krzysztof Kozlowski; Dave
> Airlie; Jani Nikula; intel-gfx@lists.freedesktop.org; Frediano Ziglio; Li,
> Samuel;
> Koenig, Christian; Tomasz Figa; Sumit Semwal; linux-ker...@vger.kernel.org;
> StDenis, Tom; Dan Carpenter
> Subject: [PATCH] drm: squash lines for simple wrapper functions
>
> Remove unneeded variables and assignments.
>
> Signed-off-by: Masahiro Yamada
Please split these up per driver.
Alex
> ---
>
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c| 6 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c| 6 +-
> drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 20
> drivers/gpu/drm/drm_dp_mst_topology.c | 7 ++-
> drivers/gpu/drm/i915/i915_drv.c | 8 +---
> drivers/gpu/drm/qxl/qxl_draw.c| 7 ++-
> drivers/gpu/drm/qxl/qxl_release.c | 7 ++-
> drivers/gpu/drm/radeon/cik.c | 6 +-
> drivers/gpu/drm/radeon/r100.c | 6 +-
> drivers/gpu/drm/radeon/r600.c | 6 +-
> 11 files changed, 17 insertions(+), 68 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index b818461..0d5307a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -5854,11 +5854,7 @@ static int gfx_v8_0_set_clockgating_state(void
> *handle,
>
> static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
> {
> - u32 rptr;
> -
> - rptr = ring->adev->wb.wb[ring->rptr_offs];
> -
> - return rptr;
> + return ring->adev->wb.wb[ring->rptr_offs];
> }
>
> static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> index a64715d..b165c78 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> @@ -190,12 +190,8 @@ out:
> */
> static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
> {
> - u32 rptr;
> -
> /* XXX check if swapping is necessary on BE */
> - rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
> -
> - return rptr;
> + return ring->adev->wb.wb[ring->rptr_offs] >> 2;
> }
>
> /**
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 653ce5e..cf253b9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -335,12 +335,8 @@ out:
> */
> static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
> {
> - u32 rptr;
> -
> /* XXX check if swapping is necessary on BE */
> - rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
> -
> - return rptr;
> + return ring->adev->wb.wb[ring->rptr_offs] >> 2;
> }
>
> /**
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> index 48030f0..d37d112 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -1073,34 +1073,22 @@ void analogix_dp_set_lane3_link_training(struct
> analogix_dp_device *dp,
>
> u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
> {
> - u32 reg;
> -
> - reg = readl(dp->reg_base +
> ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
> - return reg;
> + return readl(dp->reg_base +
> ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
> }
>
> u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
> {
> - u32 reg;
> -
> - reg = readl(dp->reg_base +
> ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
> - return reg;
> + return readl(dp->reg_base +
> ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
> }
>
> u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
> {
> - u32 reg;
> -
> - reg = readl(dp->reg_base +
> ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
> - return reg;
> + return readl(dp->reg_base +
> ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
> }
>
> u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
> {
> - u32 reg;
> -
> - reg = readl(dp->reg_base +
> ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
> - return reg;
> + return readl(dp->reg_base +
> ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
> }
>
> void analogix_dp_reset_macro(struct analogix_dp_device *dp)
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 04e4571..302bdcb 100644
> --- a/drivers/gp
Re: [Intel-gfx] [PATCH v2] tools/intel_guc_logger: Utility for capturing GuC firmware logs in a file
On 07/09/16 16:27, akash.g...@intel.com wrote:
From: Akash Goel
This patch provides a test utility which helps capture GuC firmware logs and
then dump them to file.
The logs are pulled from a debugfs file '/sys/kernel/debug/dri/guc_log' and
stored into a file '/tmp/guc_log_dump.dat', the name of the output file can
be changed through a command line argument.
The utility goes into an infinite loop where it waits for the arrival of new
logs and as soon as new set of logs are produced it captures them in its local
buffer which is then flushed out to the file on disk.
Any time when logging needs to be ended, User can stop this utility (CTRL+C).
Before entering into a loop, it first discards whatever logs are present in
the debugfs file.
This way User can first launch this utility and then start a workload/activity
for which GuC firmware logs are to be actually captured and keep running the
utility for as long as its needed, like once the workload is over this utility
can be forcefully stopped.
If the logging wasn't enabled on GuC side by the Driver at boot time, utility
will first enable the logging and later on when it is stopped (CTRL+C) it will
also pause the logging on GuC side.
v2:
- Use combination of alarm system call & SIGALRM signal to run the utility
for required duration. (Tvrtko)
- Fix inconsistencies, do minor cleanup and refactoring. (Tvrtko)
Cc: Tvrtko Ursulin
Signed-off-by: Akash Goel
---
tools/Makefile.sources | 1 +
tools/intel_guc_logger.c | 425 +++
2 files changed, 426 insertions(+)
create mode 100644 tools/intel_guc_logger.c
diff --git a/tools/Makefile.sources b/tools/Makefile.sources
index 2bb6c8e..be58871 100644
--- a/tools/Makefile.sources
+++ b/tools/Makefile.sources
@@ -19,6 +19,7 @@ tools_prog_lists =\
intel_gpu_time \
intel_gpu_top \
intel_gtt \
+ intel_guc_logger\
intel_infoframes\
intel_l3_parity \
intel_lid \
diff --git a/tools/intel_guc_logger.c b/tools/intel_guc_logger.c
new file mode 100644
index 000..6e03282
--- /dev/null
+++ b/tools/intel_guc_logger.c
@@ -0,0 +1,425 @@
+
+#define _GNU_SOURCE /* For using O_DIRECT */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "igt.h"
+
+#define MB(x) ((uint64_t)(x) * 1024 * 1024)
+#ifndef PAGE_SIZE
+ #define PAGE_SIZE 4096
+#endif
+#define SUBBUF_SIZE (19*PAGE_SIZE)
+/* Need large buffering from logger side to hide the DISK IO latency, Driver
+ * can only store 8 snapshots of GuC log buffer in relay.
+ */
+#define NUM_SUBBUFS 100
+
+#define RELAY_FILE_NAME "guc_log"
+#define DEFAULT_OUTPUT_FILE_NAME "guc_log_dump.dat"
+#define CONTROL_FILE_NAME "i915_guc_log_control"
+
+char *read_buffer;
+char *out_filename;
+int poll_timeout = 2; /* by default 2ms timeout */
+pthread_mutex_t mutex;
+pthread_t flush_thread;
+int verbosity_level = 3; /* by default capture logs at max verbosity */
+uint32_t produced, consumed;
+uint64_t total_bytes_written;
+int num_buffers = NUM_SUBBUFS;
+int relay_fd, outfile_fd = -1;
+bool stop_logging, discard_oldlogs;
+uint32_t test_duration, max_filesize;
+pthread_cond_t underflow_cond, overflow_cond;
+
+static void guc_log_control(bool enable_logging)
+{
+ int control_fd;
+ char data[19];
+ uint64_t val;
+ int ret;
+
+ control_fd = igt_debugfs_open(CONTROL_FILE_NAME, O_WRONLY);
+ igt_assert_f(control_fd >= 0, "couldn't open the guc log control file");
+
+ val = enable_logging ? ((verbosity_level << 4) | 0x1) : 0;
+
+ ret = snprintf(data, sizeof(data), "0x%" PRIx64, val);
+ igt_assert(ret > 2 && ret < sizeof(data));
+
+ ret = write(control_fd, data, ret);
+ igt_assert_f(ret > 0, "couldn't write to the log control file");
+
+ close(control_fd);
+}
+
+static void int_sig_handler(int sig)
+{
+ igt_info("received signal %d\n", sig);
+
+ stop_logging = true;
+}
+
+static void pull_leftover_data(void)
+{
+ unsigned int bytes_read = 0;
+ int ret;
+
+ do {
+ /* Read the logs from relay buffer */
+ ret = read(relay_fd, read_buffer, SUBBUF_SIZE);
+ if (!ret)
+ break;
+
+ igt_assert_f(ret > 0, "failed to read from the guc log file");
+ igt_assert_f(ret == SUBBUF_SIZE, "invalid read from relay
file");
+
+ bytes_read += ret;
+
+ if (outfile_fd >= 0) {
+ ret = write(outfile_fd, read_buffer, SUBBUF_SIZE);
+ igt_assert_f(ret == SUBBUF_SIZE, "couldn't dump the logs in
a file");
+ total_bytes_written += ret;
+ }
+ } while(1);
+
+ igt_debug("%u bytes flushed\n", by
[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [01/21] drm/i915: Add a sw fence for collecting up dma fences (rev22)
== Series Details == Series: series starting with [01/21] drm/i915: Add a sw fence for collecting up dma fences (rev22) URL : https://patchwork.freedesktop.org/series/12007/ State : warning == Summary == Series 12007v22 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/12007/revisions/22/mbox/ Test drv_module_reload_basic: pass -> SKIP (fi-skl-6260u) Test kms_flip: Subgroup basic-flip-vs-wf_vblank: pass -> DMESG-WARN (fi-snb-2520m) Test prime_vgem: Subgroup basic-fence-wait-default: fail -> PASS (fi-bdw-5557u) fail -> PASS (fi-ilk-650) fail -> PASS (fi-snb-2600) fail -> PASS (fi-hsw-4770r) fail -> PASS (fi-snb-2520m) fail -> PASS (fi-skl-6260u) fail -> PASS (fi-ivb-3520m) fail -> PASS (fi-ivb-3770) fail -> PASS (fi-skl-6700k) fail -> PASS (fi-bsw-n3050) fail -> PASS (fi-hsw-4770k) fi-bdw-5557u total:252 pass:234 dwarn:2 dfail:1 fail:0 skip:15 fi-bsw-n3050 total:252 pass:204 dwarn:1 dfail:1 fail:0 skip:46 fi-hsw-4770k total:252 pass:227 dwarn:2 dfail:1 fail:0 skip:22 fi-hsw-4770r total:252 pass:223 dwarn:2 dfail:1 fail:0 skip:26 fi-ilk-650 total:252 pass:180 dwarn:2 dfail:1 fail:2 skip:67 fi-ivb-3520m total:252 pass:218 dwarn:2 dfail:1 fail:0 skip:31 fi-ivb-3770 total:252 pass:218 dwarn:2 dfail:1 fail:0 skip:31 fi-skl-6260u total:252 pass:234 dwarn:2 dfail:1 fail:0 skip:15 fi-skl-6700k total:252 pass:220 dwarn:3 dfail:1 fail:0 skip:28 fi-snb-2520m total:252 pass:205 dwarn:2 dfail:1 fail:1 skip:43 fi-snb-2600 total:252 pass:206 dwarn:2 dfail:1 fail:0 skip:43 Results at /archive/results/CI_IGT_test/Patchwork_2482/ 7f8bc957b96e7e5f4923a8d0eed2875869073c2a drm-intel-nightly: 2016y-09m-07d-14h-47m-42s UTC integration manifest 2bbcac4 drm/i915: Support explicit fencing for execbuf 1a71554 drm/i915: Enable userspace to opt-out of implicit fencing 6d4853f drm/i915: Serialise execbuf operation after a dma-buf reservation object e34818d drm/i915: Nonblocking request submission 280495b drm/i915: Ignore valid but unknown semaphores 1cb0e0b drm/i915/guc: Prepare for nonblocking execbuf submission 90759cf drm/i915: Prepare object synchronisation for asynchronicity 9d34d3c2 drm/i915: Reorder i915_add_request to separate the phases better ca30a1c drm/i915: Drive request submission through fence callbacks 084b64d drm/i915: Update reset path to fix incomplete requests 0ef1626 drm/i915: Replace wait-on-mutex with wait-on-bit in reset worker 672bfce drm/i915: Perform a direct reset of the GPU from the waiter 56b1c0f drm/i915: Mark up all locked waiters 9d37b18 drm/i915: Expand bool interruptible to pass flags to i915_wait_request() fb95b85 drm/i915: Drop local struct_mutex around intel_init_emon[ilk] afab442 drm/i915: Separate out reset flags from the reset counter b13638d drm/i915: Simplify ELSP queue request tracking 0c8a3b0 drm/i915: Reorder submitting the requests to ELSP b57153e drm/i915: Compute the ELSP register location once 6920df1 drm/i915: Record the position of the workarounds in the tail of the request aa0a9ed drm/i915: Only queue requests during execlists submission 55e1738 drm/i915: Add a sw fence for collecting up dma fences ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/1] drm/i915/dsi: silence a warning about uninitialized return value
On 06/09/16 21:36, Nicolas Iooss wrote:
On 06/09/16 12:21, Dave Gordon wrote:
On 04/09/16 19:58, Nicolas Iooss wrote:
When building the kernel with clang and some warning flags, the compiler
reports that the return value of dcs_get_backlight() may be
uninitialized:
drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c:53:2: error: variable
'data' is used uninitialized whenever 'for' loop exits because its
condition is false [-Werror,-Wsometimes-uninitialized]
for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) {
^~~
drivers/gpu/drm/i915/intel_dsi.h:126:49: note: expanded from macro
'for_each_dsi_port'
#define for_each_dsi_port(__port, __ports_mask)
for_each_port_masked(__port,
__ports_mask)
^~
drivers/gpu/drm/i915/i915_drv.h:322:26: note: expanded from macro
'for_each_port_masked'
for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
^
drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c:60:9: note:
uninitialized use occurs here
return data;
^~~~
As intel_dsi->dcs_backlight_ports seems to be always initialized to a
non-null value, the content of the for loop is always executed and there
is no bug in the current code. Nevertheless the compiler has no way of
knowing that assumption, so initialize variable 'data' to silence the
warning here.
Signed-off-by: Nicolas Iooss
Interesting ... there are two things that could lead to this (possibly)
incorrect analysis. Either it thinks the loop could be executed zero
times, which would be a deficiency in the compiler, as the initialiser
and loop bound are both known (different) constants:
enum port {
PORT_A = 0,
PORT_B,
PORT_C,
PORT_D,
PORT_E,
I915_MAX_PORTS
};
or, it doesn't understand that because we've passed &data to another
function, it can have been set by the callee. It may be extra confusing
that the callee takes (void *); or it may be being ultra-sophisticated
in its analysis and noted that in one error path data is *not* set (and
we then discard the error and use data anyway). As an experiment, you
could try:
The code that the compiler sees is not a simple loop other enum 'port'
but "for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) {", which
is expanded [1] to:
for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++)
if (!((intel_dsi->dcs_backlight_ports) & (1 << (port {} else {
This is why I spoke of intel_dsi->dcs_backlight_ports in my description:
if it is zero, the body of the loop is never run.
As for the analyses of calls using &data, clang does not warn about the
variable being maybe uninitialized following a call. This is quite
expected as this would lead to too many false positives, even though it
may miss some bugs.
static u8 mipi_dsi_dcs_read1(struct mipi_dsi_device *dsi_device, u8 cmd)
{
u8 data = 0;
mipi_dsi_dcs_read(dsi_device, cmd, &data, sizeof(data));
return data;
}
static u32 dcs_get_backlight(struct intel_connector *connector)
{
struct intel_encoder *encoder = connector->encoder;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
struct mipi_dsi_device *dsi_device;
enum port port;
u8 data;
/* FIXME: Need to take care of 16 bit brightness level */
for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) {
dsi_device = intel_dsi->dsi_hosts[port]->device;
data = mipi_dsi_dcs_read1(dsi_device,
MIPI_DCS_GET_DISPLAY_BRIGHTNESS);
break;
}
return data;
}
If it complains about that then it's a shortcoming in the loop analysis.
It complains (in dcs_get_backlight), because for_each_dsi_port() still
hides an 'if' condition.
So it does, In that case the complaint is really quite reasonable.
If not you could try:
static u8 mipi_dsi_dcs_read1(struct mipi_dsi_device *dsi_device, u8 cmd)
{
u8 data;
ssize_t nbytes = sizeof(data);
nbytes = mipi_dsi_dcs_read(dsi_device, cmd, &data, nbytes);
return nbytes == sizeof(data) ? data : 0;
}
and if complains about that then it doesn't understand that passing
&data allows it to be set. If it doesn't complain about this version,
then the original error was actually correct, in the sense that data can
indeed be used uninitialised if certain error paths can be taken.
clang did not complain with this last case.
It probably should have, since the (hidden) if() could still result in
this function never being called. Oh well ...
.Dave.
Here's an R-b for your fix anyway ...
Reviewed-by: Dave Gordon
Thanks!
Nicolas
[1] I used "make drivers/gpu/drm/i915/intel_dsi_dcs_backlight.i" to see
the output of the preprocessor.
___
Re: [Intel-gfx] [PATCH 1/8] drm/i915: SAGV is not SKL-only, so rename a few things
My only thought is that it seems like we prefix functions skl_, kbl_,
etc. just to indicate which generation introduced the feature. Skl uses
quite a few sandybridge and haswell functions. If this is a little
closer to what most intel devs would expect the naming to be though
then:
Reviewed-by: Lyude
going through the other patches now as well
On Tue, 2016-09-06 at 21:52 -0300, Paulo Zanoni wrote:
> The plan is to introduce intel_has_sagv() and then use it to discover
> which platforms actually support it.
>
> I thought about keeping the functions with their current skl names,
> but found two problems: (i) skl_has_sagv() would become a very
> confusing name, and (ii) intel_atomic_commit_tail() doesn't seem to
> be
> calling any functions whose name start with a platform name, so the
> "intel_" naming scheme seems make more sense than the "firstplatorm_"
> naming scheme here.
>
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/i915_drv.h | 10 +-
> drivers/gpu/drm/i915/intel_display.c | 8
> drivers/gpu/drm/i915/intel_drv.h | 6 +++---
> drivers/gpu/drm/i915/intel_pm.c | 26 +-
> 4 files changed, 25 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 053a347..503c69d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1972,11 +1972,11 @@ struct drm_i915_private {
> struct vlv_s0ix_state vlv_s0ix_state;
>
> enum {
> - I915_SKL_SAGV_UNKNOWN = 0,
> - I915_SKL_SAGV_DISABLED,
> - I915_SKL_SAGV_ENABLED,
> - I915_SKL_SAGV_NOT_CONTROLLED
> - } skl_sagv_status;
> + I915_SAGV_UNKNOWN = 0,
> + I915_SAGV_DISABLED,
> + I915_SAGV_ENABLED,
> + I915_SAGV_NOT_CONTROLLED
> + } sagv_status;
>
> struct {
> /*
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 6b4d7ac..4dd4961 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14379,8 +14379,8 @@ static void intel_atomic_commit_tail(struct
> drm_atomic_state *state)
> * SKL workaround: bspec recommends we disable the
> SAGV when we
> * have more then one pipe enabled
> */
> - if (IS_SKYLAKE(dev_priv) &&
> !skl_can_enable_sagv(state))
> - skl_disable_sagv(dev_priv);
> + if (IS_SKYLAKE(dev_priv) &&
> !intel_can_enable_sagv(state))
> + intel_disable_sagv(dev_priv);
>
> intel_modeset_verify_disabled(dev);
> }
> @@ -14438,8 +14438,8 @@ static void intel_atomic_commit_tail(struct
> drm_atomic_state *state)
> }
>
> if (IS_SKYLAKE(dev_priv) && intel_state->modeset &&
> - skl_can_enable_sagv(state))
> - skl_enable_sagv(dev_priv);
> + intel_can_enable_sagv(state))
> + intel_enable_sagv(dev_priv);
>
> drm_atomic_helper_commit_hw_done(state);
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index d084c1b..bb55b61 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1741,9 +1741,9 @@ void ilk_wm_get_hw_state(struct drm_device
> *dev);
> void skl_wm_get_hw_state(struct drm_device *dev);
> void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> struct skl_ddb_allocation *ddb /* out */);
> -bool skl_can_enable_sagv(struct drm_atomic_state *state);
> -int skl_enable_sagv(struct drm_i915_private *dev_priv);
> -int skl_disable_sagv(struct drm_i915_private *dev_priv);
> +bool intel_can_enable_sagv(struct drm_atomic_state *state);
> +int intel_enable_sagv(struct drm_i915_private *dev_priv);
> +int intel_disable_sagv(struct drm_i915_private *dev_priv);
> bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
> const struct skl_ddb_allocation *new,
> enum pipe pipe);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 4f833a0..32588e3 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2896,12 +2896,12 @@ skl_wm_plane_id(const struct intel_plane
> *plane)
> * - We're not using an interlaced display configuration
> */
> int
> -skl_enable_sagv(struct drm_i915_private *dev_priv)
> +intel_enable_sagv(struct drm_i915_private *dev_priv)
> {
> int ret;
>
> - if (dev_priv->skl_sagv_status ==
> I915_SKL_SAGV_NOT_CONTROLLED ||
> - dev_priv->skl_sagv_status == I915_SKL_SAGV_ENABLED)
> + if (dev_priv->sagv_status == I915_SAGV_NOT_CONTROLLED ||
> + dev_priv->sagv_status == I915_SAGV_ENABLED)
> return 0;
>
> DRM_DEBUG_KMS("Enabling the SAGV\n");
> @@ -2919,19 +2919,19 @@ skl_ena
Re: [Intel-gfx] [PATCH 3/8] drm/i915/kbl: KBL also needs to run the SAGV code
On Tue, Sep 06, 2016 at 09:52:14PM -0300, Paulo Zanoni wrote:
> According to BSpec, it's the "core CPUs" that need the code, which
> means SKL and KBL, but not BXT.
>
> I don't have a KBL to test this patch on it.
IIRC bspec doesn't specify the sagv latency for anything but
SKL, and the relevant w/a was only listed for SKL as well. So not sure
this is correct.
>
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index af75011..baacd95 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2887,7 +2887,7 @@ skl_wm_plane_id(const struct intel_plane *plane)
> static bool
> intel_has_sagv(struct drm_i915_private *dev_priv)
> {
> - return IS_SKYLAKE(dev_priv);
> + return IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv);
> }
>
> /*
> --
> 2.7.4
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/8] drm/i915: introduce intel_has_sagv()
On Tue, 2016-09-06 at 21:52 -0300, Paulo Zanoni wrote:
> And use it to move knowledge about the SAGV-supporting platforms from
> the callers to the SAGV code.
>
> We'll add more platforms to intel_has_sagv(), so IMHO it makes more
> sense to move all this to a single function instead of patching all
> the callers every time we add SAGV support to a new platform.
>
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_display.c | 5 ++---
> drivers/gpu/drm/i915/intel_pm.c | 15 +++
> 2 files changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 4dd4961..2442ab2 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14379,7 +14379,7 @@ static void intel_atomic_commit_tail(struct
> drm_atomic_state *state)
> * SKL workaround: bspec recommends we disable the
> SAGV when we
> * have more then one pipe enabled
> */
> - if (IS_SKYLAKE(dev_priv) &&
> !intel_can_enable_sagv(state))
> + if (!intel_can_enable_sagv(state))
> intel_disable_sagv(dev_priv);
>
> intel_modeset_verify_disabled(dev);
> @@ -14437,8 +14437,7 @@ static void intel_atomic_commit_tail(struct
> drm_atomic_state *state)
> intel_modeset_verify_crtc(crtc, old_crtc_state,
> crtc->state);
> }
>
> - if (IS_SKYLAKE(dev_priv) && intel_state->modeset &&
> - intel_can_enable_sagv(state))
> + if (intel_state->modeset && intel_can_enable_sagv(state))
> intel_enable_sagv(dev_priv);
>
> drm_atomic_helper_commit_hw_done(state);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 32588e3..af75011 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2884,6 +2884,12 @@ skl_wm_plane_id(const struct intel_plane
> *plane)
> }
> }
>
> +static bool
> +intel_has_sagv(struct drm_i915_private *dev_priv)
> +{
> + return IS_SKYLAKE(dev_priv);
> +}
> +
Not sure I agree on this one. Even if a system is skylake or kabylake,
there's a couple of very early skylake machines that don't actually
have an SAGV on them. Hence the I915_SAGV_NOT_CONTROLLED value we set
if we get mailbox errors.
So if we're going to split SAGV detection into a different function, I
would also move the dev_priv->sagv_status == I915_SAGV_NOT_CONTROLLED
check into there:
if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
return false;
if (dev_priv->sagv_status == I915_SAGV_NOT_CONTROLLED)
return false;
return true;
> /*
> * SAGV dynamically adjusts the system agent voltage and clock
> frequencies
> * depending on power and performance requirements. The display
> engine access
> @@ -2900,6 +2906,9 @@ intel_enable_sagv(struct drm_i915_private
> *dev_priv)
> {
> int ret;
>
> + if (!intel_has_sagv(dev_priv))
> + return 0;
> +
> if (dev_priv->sagv_status == I915_SAGV_NOT_CONTROLLED ||
> dev_priv->sagv_status == I915_SAGV_ENABLED)
> return 0;
> @@ -2949,6 +2958,9 @@ intel_disable_sagv(struct drm_i915_private
> *dev_priv)
> {
> int ret, result;
>
> + if (!intel_has_sagv(dev_priv))
> + return 0;
> +
> if (dev_priv->sagv_status == I915_SAGV_NOT_CONTROLLED ||
> dev_priv->sagv_status == I915_SAGV_DISABLED)
> return 0;
> @@ -2991,6 +3003,9 @@ bool intel_can_enable_sagv(struct
> drm_atomic_state *state)
> enum pipe pipe;
> int level, plane;
>
> + if (!intel_has_sagv(dev_priv))
> + return false;
> +
> /*
> * SKL workaround: bspec recommends we disable the SAGV when
> we have
> * more then one pipe enabled
--
Cheers,
Lyude
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/8] drm/i915/kbl: KBL also needs to run the SAGV code
I'm not sure that kbl has this either. The kbl machine I've been
working with thus-far has passed a few modesetting stress tests with
the chameleon, and I don't have anything trying to control sagv stuff
on it.
This being said though the sagv for skylake did happen to get added
right before release and wasn't in any SDPs, so even so we should keep
our eyes out when kbl starts shipping…
On Wed, 2016-09-07 at 19:11 +0300, Ville Syrjälä wrote:
> On Tue, Sep 06, 2016 at 09:52:14PM -0300, Paulo Zanoni wrote:
> >
> > According to BSpec, it's the "core CPUs" that need the code, which
> > means SKL and KBL, but not BXT.
> >
> > I don't have a KBL to test this patch on it.
>
> IIRC bspec doesn't specify the sagv latency for anything but
> SKL, and the relevant w/a was only listed for SKL as well. So not
> sure
> this is correct.
>
> >
> >
> > Signed-off-by: Paulo Zanoni
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index af75011..baacd95 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -2887,7 +2887,7 @@ skl_wm_plane_id(const struct intel_plane
> > *plane)
> > static bool
> > intel_has_sagv(struct drm_i915_private *dev_priv)
> > {
> > - return IS_SKYLAKE(dev_priv);
> > + return IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv);
> > }
> >
> > /*
> > --
> > 2.7.4
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
--
Cheers,
Lyude
___
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Re: [Intel-gfx] [PATCH v2 14/14] drm/i915/dp/mst: Add support for upfront link training for DP MST
On Wed, Sep 07, 2016 at 01:53:31PM +0300, Mika Kahola wrote:
> On Tue, 2016-09-06 at 17:13 -0700, Manasi Navare wrote:
> > From: Jim Bride
> >
> > Add upfront link training to intel_dp_mst_mode_valid() so that we
> > know
> > topology constraints before we validate the legality of modes to be
> > checked.
> > Call the function that loops through the link rates and lane counts
> > starting from highest supported link rate and lane count for training
> > the link in compliance with DP spec
> >
> > v2:
> > * Rebased on new revision of link training patch (Manasi Navare)
> >
> > Signed-off-by: Manasi Navare
> > Signed-off-by: Jim Bride
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 9 ++---
> > drivers/gpu/drm/i915/intel_dp_mst.c | 74
> > +++--
> > drivers/gpu/drm/i915/intel_drv.h| 3 ++
> > 3 files changed, 61 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 7794180..0c7674f 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -131,7 +131,7 @@ static void vlv_steal_power_sequencer(struct
> > drm_device *dev,
> > enum pipe pipe);
> > static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> >
> > -static int
> > +int
> > intel_dp_max_link_bw(struct intel_dp *intel_dp)
> > {
> > int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
> > @@ -150,7 +150,7 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
> > return max_link_bw;
> > }
> >
> > -static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
> > +u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
> > {
> > struct intel_digital_port *intel_dig_port =
> > dp_to_dig_port(intel_dp);
> > u8 temp, source_max, sink_max;
> > @@ -312,8 +312,7 @@ static int intersect_rates(const int
> > *source_rates, int source_len,
> > return k;
> > }
> >
> > -static int intel_dp_common_rates(struct intel_dp *intel_dp,
> > - int *common_rates)
> > +int intel_dp_common_rates(struct intel_dp *intel_dp, int
> > *common_rates)
> > {
> > const int *source_rates, *sink_rates;
> > int source_len, sink_len;
> > @@ -336,7 +335,7 @@ static int intel_dp_common_rates(struct intel_dp
> > *intel_dp,
> > common_rates);
> > }
> >
> > -static bool intel_dp_upfront_link_train(struct intel_dp *intel_dp)
> > +bool intel_dp_upfront_link_train(struct intel_dp *intel_dp)
> > {
> > struct intel_digital_port *intel_dig_port =
> > dp_to_dig_port(intel_dp);
> > struct intel_encoder *intel_encoder = &intel_dig_port->base;
> > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/intel_dp_mst.c
> > index 54a9d76..98d45a4 100644
> > --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> > @@ -41,21 +41,30 @@ static bool intel_dp_mst_compute_config(struct
> > intel_encoder *encoder,
> > int bpp;
> > int lane_count, slots;
> > const struct drm_display_mode *adjusted_mode = &pipe_config-
> > >base.adjusted_mode;
> > - int mst_pbn;
> > + int mst_pbn, common_len;
> > + int common_rates[DP_MAX_SUPPORTED_RATES] = {};
> >
> > pipe_config->dp_encoder_is_mst = true;
> > pipe_config->has_pch_encoder = false;
> > - bpp = 24;
> > +
> > /*
> > - * for MST we always configure max link bw - the spec
> > doesn't
> > - * seem to suggest we should do otherwise.
> > + * For MST we always configure for the maximum trainable
> > link bw -
> > + * the spec doesn't seem to suggest we should do
> > otherwise. The
> > + * calls to intel_dp_max_lane_count() and
> > intel_dp_common_rates()
> > + * both take successful upfront link training into account,
> > and
> > + * return the DisplayPort max supported values in the event
> > that
> > + * upfront link training was not done.
> > */
> > - lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
> > + lane_count = intel_dp_max_lane_count(intel_dp);
> >
> > pipe_config->lane_count = lane_count;
> >
> > - pipe_config->pipe_bpp = 24;
> > - pipe_config->port_clock = intel_dp_max_link_rate(intel_dp);
> > + pipe_config->pipe_bpp = bpp = 24;
> > + common_len = intel_dp_common_rates(intel_dp, common_rates);
> > + pipe_config->port_clock = common_rates[common_len - 1];
> > +
> > + DRM_DEBUG_KMS("DP MST link configured for %d lanes @ %d.\n",
> > + pipe_config->lane_count, pipe_config-
> > >port_clock);
> >
> > state = pipe_config->base.state;
> >
> > @@ -137,6 +146,8 @@ static void intel_mst_pre_enable_dp(struct
> > intel_encoder *encoder,
> > enum port port = intel_dig_port->port;
> > struct intel_connector *connector =
> > to_intel_connector(conn_state->connector);
> > + struct intel_shared_dpll *pll = pipe_config->shared_dpll;
> > + struct intel_shared_dpll_config tmp_pll_config;
> >
Re: [Intel-gfx] [PATCH v2 11/14] drm/i915: Fallback to lower link rate and lane count during link training
On Wed, Sep 07, 2016 at 12:47:49PM +0300, Mika Kahola wrote:
> On Tue, 2016-09-06 at 17:13 -0700, Manasi Navare wrote:
> > According to the DisplayPort Spec, in case of Clock Recovery failure
> > the link training sequence should fall back to the lower link rate
> > followed by lower lane count until CR succeeds.
> > On CR success, the sequence proceeds with Channel EQ.
> > In case of Channel EQ failures, it should fallback to
> > lower link rate and lane count and start the CR phase again.
> >
> > v2:
> > * Add a helper function to return index of requested link rate
> > into common_rates array
> > * Changed the link rate fallback loop to make use
> > of common_rates array (Mika Kahola)
> > * Changed INTEL_INFO to INTEL_GEN (David Weinehall)
> >
> > Signed-off-by: Manasi Navare
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 125
> > +++---
> > drivers/gpu/drm/i915/intel_dp.c | 15
> > drivers/gpu/drm/i915/intel_dp_link_training.c | 12 ++-
> > drivers/gpu/drm/i915/intel_drv.h | 7 +-
> > 4 files changed, 145 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index 67a6a0b..e38bf4b 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1634,19 +1634,18 @@ void intel_ddi_clk_select(struct
> > intel_encoder *encoder,
> > }
> > }
> >
> > -static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> > +static void intel_ddi_pre_enable_edp(struct intel_encoder *encoder,
> > int link_rate, uint32_t
> > lane_count,
> > - struct intel_shared_dpll *pll,
> > - bool link_mst)
> > + struct intel_shared_dpll *pll)
> > {
> > struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> > struct drm_i915_private *dev_priv = to_i915(encoder-
> > >base.dev);
> > enum port port = intel_ddi_get_encoder_port(encoder);
> >
> > intel_dp_set_link_params(intel_dp, link_rate, lane_count,
> > - link_mst);
> > - if (encoder->type == INTEL_OUTPUT_EDP)
> > - intel_edp_panel_on(intel_dp);
> > + false);
> > +
> > + intel_edp_panel_on(intel_dp);
> >
> > intel_ddi_clk_select(encoder, pll);
> > intel_prepare_dp_ddi_buffers(encoder);
> > @@ -1657,6 +1656,29 @@ static void intel_ddi_pre_enable_dp(struct
> > intel_encoder *encoder,
> > intel_dp_stop_link_train(intel_dp);
> > }
> >
> > +static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> > + int link_rate, uint32_t
> > lane_count,
> > + struct intel_shared_dpll *pll,
> > + bool link_mst)
> > +{
> > + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> > + struct drm_i915_private *dev_priv = to_i915(encoder-
> > >base.dev);
> > + struct intel_shared_dpll_config tmp_pll_config;
> > +
> > + /* Disable the PLL and obtain the PLL for Link Training
> > + * that starts with highest link rate and lane count.
> > + */
> > + tmp_pll_config = pll->config;
> > + pll->funcs.disable(dev_priv, pll);
> > + pll->config.crtc_mask = 0;
> > +
> > + /* If Link Training fails, send a uevent to generate a
> > hotplug */
> > + if (!(intel_ddi_link_train(intel_dp, link_rate, lane_count,
> > link_mst,
> > + false)))
> > + drm_kms_helper_hotplug_event(encoder->base.dev);
> > + pll->config = tmp_pll_config;
> > +}
> > +
> > static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
> > bool has_hdmi_sink,
> > struct drm_display_mode
> > *adjusted_mode,
> > @@ -1690,20 +1712,26 @@ static void intel_ddi_pre_enable(struct
> > intel_encoder *intel_encoder,
> > struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
> > int type = intel_encoder->type;
> >
> > - if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
> > + if (type == INTEL_OUTPUT_EDP)
> > + intel_ddi_pre_enable_edp(intel_encoder,
> > + crtc->config->port_clock,
> > + crtc->config->lane_count,
> > + crtc->config->shared_dpll);
> > +
> > + if (type == INTEL_OUTPUT_DP)
> > intel_ddi_pre_enable_dp(intel_encoder,
> > crtc->config->port_clock,
> > crtc->config->lane_count,
> > crtc->config->shared_dpll,
> > intel_crtc_has_type(crtc-
> > >config,
> > INTEL_OU
> > TPUT_DP_MST));
> > - }
> > - if (type == INTEL_OUTPUT_HDMI) {
> > +
