Re: [Intel-gfx] ✓ Ro.CI.BAT: success for series starting with [1/2] drm/i915/debug: Select PREEMPT_COUNT when enabling debugging (rev3)
On 28/06/16 20:59, Chris Wilson wrote: On Tue, Jun 28, 2016 at 05:03:20PM -, Patchwork wrote: == Series Details == Series: series starting with [1/2] drm/i915/debug: Select PREEMPT_COUNT when enabling debugging (rev3) URL : https://patchwork.freedesktop.org/series/9226/ State : success == Summary == Series 9226v3 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/9226/revisions/3/mbox Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-c: dmesg-warn -> SKIP (ro-bdw-i5-5250u) Should we ask QA to enable CONFIG_I915_DEBUG and spend some time fire fighting? Yes why not, we can always backtrack if it uncovers too much. :) I will respin with the __builtin_constant_p since I was considering that myself. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Removing PCI IDs that are no longer listed as Kabylake.
On Fri, 24 Jun 2016, Rodrigo Vivi wrote: > This is unusual. Usually IDs listed on early stages of platform > definition are kept there as reserved for later use. > > However these IDs here are not listed anymore in any of steppings > and devices IDs tables for Kabylake on configurations overview > section of BSpec. > > So it is better removing them before they become used in any > other future platform. > > Signed-off-by: Rodrigo Vivi Please reply to the list when you actually push. Both of these could have used cc: drm-intel-fixes because we support kbl starting v4.7. I've picked them to fixes now. BR, Jani. > --- > include/drm/i915_pciids.h | 9 ++--- > 1 file changed, 2 insertions(+), 7 deletions(-) > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h > index 87dde1c..33466bf 100644 > --- a/include/drm/i915_pciids.h > +++ b/include/drm/i915_pciids.h > @@ -325,15 +325,10 @@ > #define INTEL_KBL_GT3_IDS(info) \ > INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \ > INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \ > - INTEL_VGA_DEVICE(0x5927, info), /* ULT GT3 */ \ > - INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \ > - INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */ > + INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */ > > #define INTEL_KBL_GT4_IDS(info) \ > - INTEL_VGA_DEVICE(0x5932, info), /* DT GT4 */ \ > - INTEL_VGA_DEVICE(0x593B, info), /* Halo GT4 */ \ > - INTEL_VGA_DEVICE(0x593A, info), /* SRV GT4 */ \ > - INTEL_VGA_DEVICE(0x593D, info) /* WKS GT4 */ > + INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */ > > #define INTEL_KBL_IDS(info) \ > INTEL_KBL_GT1_IDS(info), \ -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC] drm/i915: hybrid wait-for macro
On 28/06/16 17:56, Dave Gordon wrote:
Part spin-wait, part sleep-wait.
Plus one example of where it might be used.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_guc_submission.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 10 ++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 355b647..ff99910 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -98,7 +98,7 @@ static int host2guc_action(struct intel_guc *guc, u32 *data,
u32 len)
I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER);
/* No HOST2GUC command should take longer than 10ms */
- ret = wait_for_atomic(host2guc_action_response(dev_priv, &status), 10);
+ ret = wait_for_hybrid(host2guc_action_response(dev_priv, &status), 10,
10);
if (status != GUC2HOST_STATUS_SUCCESS) {
/*
* Either the GuC explicitly returned an error (which
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3156d8d..096e07c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -103,6 +103,16 @@
#define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000)
#define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US))
+/* Hybrid wait:
+ * first spin-wait for up to microseconds,
+ * if still not true, sleep-wait for MS milliseconds
+ */
+#definewait_for_hybrid(COND, US, MS) ({
\
+ int ret__ = wait_for_atomic_us(COND, US); \
+ if (ret__) ret__ = wait_for(COND, MS); \
+ ret__; \
+ })
+
#define KHz(x) (1000 * (x))
#define MHz(x) KHz(1000 * (x))
Wouldn't harm anything if you know typical GuC response time is under
10us and 10ms timeout is backed with some documentation.
Another idea could be a wait_for variant which takes those values, so
typical and maximum response time, and then it could decide statically
in the macro what to do.
Regards,
Tvrtko
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[Intel-gfx] [PATCH v4] drm/i915: Use atomic waits for short non-atomic ones
From: Tvrtko Ursulin
usleep_range is not recommended for waits shorten than 10us.
Make the wait_for_us use the atomic variant for such waits.
To do so we need to reimplement the _wait_for_atomic macro to
be safe with regards to preemption and interrupts.
v2: Reimplement _wait_for_atomic to be irq and preemption safe.
(Chris Wilson and Imre Deak)
v3: Fixed in_atomic check due rebase error.
v4: Build bug on non-constant timeouts.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Imre Deak
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_drv.h | 57 ++--
1 file changed, 38 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3156d8df7921..21fb296dbba7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -69,39 +69,58 @@
})
#define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
-#define wait_for_us(COND, US) _wait_for((COND), (US), 1)
/* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
#if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
-# define _WAIT_FOR_ATOMIC_CHECK WARN_ON_ONCE(!in_atomic())
+# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
#else
-# define _WAIT_FOR_ATOMIC_CHECK do { } while (0)
+# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
#endif
-#define _wait_for_atomic(COND, US) ({ \
- unsigned long end__; \
- int ret__ = 0; \
- _WAIT_FOR_ATOMIC_CHECK; \
+#define _wait_for_atomic(COND, US, ATOMIC) \
+({ \
+ int cpu, ret, timeout = (US) * 1000; \
+ u64 base; \
+ _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
BUILD_BUG_ON((US) > 5); \
- end__ = (local_clock() >> 10) + (US) + 1; \
- while (!(COND)) { \
- if (time_after((unsigned long)(local_clock() >> 10), end__)) { \
- /* Unlike the regular wait_for(), this atomic variant \
-* cannot be preempted (and we'll just ignore the issue\
-* of irq interruptions) and so we know that no time \
-* has passed since the last check of COND and can \
-* immediately report the timeout. \
-*/ \
- ret__ = -ETIMEDOUT; \
+ preempt_disable(); \
+ cpu = smp_processor_id(); \
+ base = local_clock(); \
+ for (;;) { \
+ u64 now = local_clock(); \
+ preempt_enable(); \
+ if (COND) { \
+ ret = 0; \
+ break; \
+ } \
+ if (now - base >= timeout) { \
+ ret = -ETIMEDOUT; \
break; \
} \
cpu_relax(); \
+ preempt_disable(); \
+ if (unlikely(cpu != smp_processor_id())) { \
+ timeout -= now - base; \
+ cpu = smp_processor_id(); \
+ base = local_clock(); \
+ } \
} \
+ ret; \
+})
+
+#define wait_for_us(COND, US) \
+({ \
+ int ret__; \
+ BUILD_BUG_ON(!__builtin_constant_p(US)); \
+ if ((US) > 10) \
+ ret__ = _wait_for((COND), (US), 10); \
+ else \
+ ret__ = _wait_for_atomic((COND), (US), 0); \
ret__; \
})
-#define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000)
-#define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US))
+#define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000, 1)
+#define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US), 1)
#define KHz(x) (1000 * (x))
#define MHz(x) KHz(1000 * (x))
--
1.9.1
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[Intel-gfx] [PATCH i-g-t 3/3] tools/intel_reg: add initial reg spec for broxton
Mostly just copy SKL, which is probably partly bogus for BXT, but better
than nothing. Add the defs for BXT DSI, but don't dump them by default
because reading them without proper power well and/or DSI PLL may hang
the machine.
Signed-off-by: Jani Nikula
---
tools/registers/broxton | 6 +++
tools/registers/bxt_dsi.txt | 119
2 files changed, 125 insertions(+)
create mode 100644 tools/registers/broxton
create mode 100644 tools/registers/bxt_dsi.txt
diff --git a/tools/registers/broxton b/tools/registers/broxton
new file mode 100644
index ..4d6345baddbf
--- /dev/null
+++ b/tools/registers/broxton
@@ -0,0 +1,6 @@
+gen8_interrupt.txt
+gen8_other.txt
+skl_powerwells.txt
+skl_display.txt
+# Skip DSI for now.
+# bxt_dsi.txt
diff --git a/tools/registers/bxt_dsi.txt b/tools/registers/bxt_dsi.txt
new file mode 100644
index ..f0687082b6c8
--- /dev/null
+++ b/tools/registers/bxt_dsi.txt
@@ -0,0 +1,119 @@
+# NOTE: many of these are problematic, hard hanging the machine when they're
+# read without proper power domain or dsi pll enable.
+
+('MIPI_CLOCK_CTL', '0x46090', '')
+('MIPI_DSI_PLL_CTL', '0x161000', '')
+('MIPI_DSI_PLL_ENABLE, '0x46080', '')
+
+('MIPIA_TRANS_HACTIVE','0x6B0F8', '')
+('MIPIA_TRANS_VACTIVE','0x6B0FC', '')
+('MIPIA_TRANS_VTOTAL', '0x6B100', '')
+('MIPIA_PORT_CTRL','0x6B0C0', '')
+('MIPIA_DEVICE_READY', '0x6B000', '')
+('MIPIA_INTR_STAT','0x6B004', '')
+('MIPIA_INTR_EN', '0x6B008', '')
+('MIPIA_DSI_FUNC_PRG', '0x6B00C', '')
+('MIPIA_HS_TX_TIMEOUT','0x6B010', '')
+('MIPIA_LP_RX_TIMEOUT','0x6B014', '')
+('MIPIA_TURN_AROUND_TIMEOUT', '0x6B018', '')
+('MIPIA_DEVICE_RESET_TIMER', '0x6B01C', '')
+('MIPIA_DPI_RESOLUTION', '0x6B020', '')
+('MIPIA_DBI_FIFO_THROTTLE','0x6B024', '')
+('MIPIA_HSYNC_PADDING_COUNT', '0x6B028', '')
+('MIPIA_HBP_COUNT','0x6B02C', '')
+('MIPIA_HFP_COUNT','0x6B030', '')
+('MIPIA_HACTIVE_AREA_COUNT', '0x6B034', '')
+('MIPIA_VSYNC_PADDING_COUNT', '0x6B038', '')
+('MIPIA_VBP_COUNT','0x6B03C', '')
+('MIPIA_VFP_COUNT','0x6B040', '')
+('MIPIA_HIGH_LOW_SWITCH_COUNT','0x6B044', '')
+('MIPIA_DPI_CONTROL', '0x6B048', '')
+('MIPIA_DPI_DATA', '0x6B04C', '')
+('MIPIA_INIT_COUNT', '0x6B050', '')
+('MIPIA_MAX_RETURN_PKT_SIZE', '0x6B054', '')
+('MIPIA_VIDEO_MODE_FORMAT','0x6B058', '')
+('MIPIA_EOT_DISABLE', '0x6B05C', '')
+('MIPIA_LP_BYTECLK', '0x6B060', '')
+('MIPIA_LP_GEN_DATA', '0x6B064', '')
+('MIPIA_HS_GEN_DATA', '0x6B068', '')
+('MIPIA_LP_GEN_CTRL', '0x6B06C', '')
+('MIPIA_HS_GEN_CTRL', '0x6B070', '')
+('MIPIA_GEN_FIFO_STAT','0x6B074', '')
+('MIPIA_HS_LS_DBI_ENABLE', '0x6B078', '')
+('MIPIA_DPHY_PARAM', '0x6B080', '')
+('MIPIA_DBI_BW_CTRL', '0x6B084', '')
+('MIPIA_CLK_LANE_SWITCH_TIME_CNT', '0x6B088', '')
+('MIPIA_STOP_STATE_STALL', '0x6B08C', '')
+('MIPIA_INTR_STAT_REG_1', '0x6B090', '')
+('MIPIA_INTR_EN_REG_1','0x6B094', '')
+('MIPIA_DBI_TYPEC_CTRL', '0x6B100', '')
+('MIPIA_CTRL', '0x6B104', '')
+('MIPIA_DATA_ADDRESS', '0x6B108', '')
+('MIPIA_DATA_LENGTH', '0x6B10C', '')
+('MIPIA_COMMAND_ADDRESS', '0x6B110', '')
+('MIPIA_COMMAND_LENGTH', '0x6B114', '')
+('MIPIA_READ_DATA_RETURN0','0x6B118', '')
+('MIPIA_READ_DATA_RETURN1','0x6B11C', '')
+('MIPIA_READ_DATA_RETURN2','0x6B120', '')
+('MIPIA_READ_DATA_RETURN3','0x6B124', '')
+('MIPIA_READ_DATA_RETURN4','0x6B128', '')
+('MIPIA_READ_DATA_RETURN5','0x6B12C', '')
+('MIPIA_READ_DATA_RETURN6','0x6B130', '')
+('MIPIA_READ_DATA_RETURN7','0x6B134', '')
+('MIPIA_READ_DATA_VALID', '0x6B138', '')
+
+('MIPIC_TRANS_HACTIVE','0x6B8F8', '')
+('MIPIC_TRANS_VACTIVE','0x6B8FC', '')
+('MIPIC_TRANS_VTOTAL', '0x6B900', '')
+('MIPIC_PORT_CTRL','0x6B8C0', '')
+('MIPIC_DEVICE_READY', '0x6B800', '')
+('MIPIC_INTR_STAT','0x6B804', '')
+('MIPIC_INTR_EN', '0x6B808', '')
+('MIPIC_DSI_FUNC_PRG', '0x6B80C', '')
+('MIPIC_HS_TX_TIMEOUT','0x6B810', '')
+('MIPIC_LP_RX_TIMEOUT','0x6B
[Intel-gfx] [PATCH i-g-t 1/3] tools/intel_reg: add kabylake register spec file
Just do whatever skylake does. Signed-off-by: Jani Nikula --- tools/registers/kabylake | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 tools/registers/kabylake diff --git a/tools/registers/kabylake b/tools/registers/kabylake new file mode 100644 index ..ac923295a8b2 --- /dev/null +++ b/tools/registers/kabylake @@ -0,0 +1,2 @@ +# close enough +skylake -- 2.1.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 2/3] tools/intel_reg: try to find broxton register spec by codename
Signed-off-by: Jani Nikula --- tools/intel_reg.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/intel_reg.c b/tools/intel_reg.c index 92be1ce7719f..46745b6efc64 100644 --- a/tools/intel_reg.c +++ b/tools/intel_reg.c @@ -671,6 +671,8 @@ static const char *get_codename(uint32_t devid) return "skylake"; else if (IS_KABYLAKE(devid)) return "kabylake"; + else if (IS_BROXTON(devid)) + return "broxton"; else if (IS_CHERRYVIEW(devid)) return "cherryview"; else if (IS_VALLEYVIEW(devid)) -- 2.1.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [1/2] drm/i915/debug: Select PREEMPT_COUNT when enabling debugging (rev4)
== Series Details == Series: series starting with [1/2] drm/i915/debug: Select PREEMPT_COUNT when enabling debugging (rev4) URL : https://patchwork.freedesktop.org/series/9226/ State : failure == Summary == Series 9226v4 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/9226/revisions/4/mbox Test drv_module_reload_basic: dmesg-warn -> PASS (ro-byt-n2820) Test kms_flip: Subgroup basic-flip-vs-wf_vblank: pass -> FAIL (ro-bdw-i5-5250u) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: dmesg-warn -> SKIP (ro-bdw-i5-5250u) Subgroup suspend-read-crc-pipe-b: dmesg-warn -> SKIP (ro-bdw-i7-5557U) fi-hsw-i7-4770k total:229 pass:194 dwarn:0 dfail:0 fail:2 skip:33 fi-kbl-qkkr total:229 pass:161 dwarn:29 dfail:0 fail:0 skip:39 fi-skl-i5-6260u total:229 pass:202 dwarn:0 dfail:0 fail:2 skip:25 fi-skl-i7-6700k total:229 pass:188 dwarn:0 dfail:0 fail:2 skip:39 fi-snb-i7-2600 total:229 pass:174 dwarn:0 dfail:0 fail:2 skip:53 ro-bdw-i5-5250u total:229 pass:201 dwarn:2 dfail:1 fail:3 skip:22 ro-bdw-i7-5557U total:229 pass:202 dwarn:1 dfail:1 fail:2 skip:23 ro-bdw-i7-5600u total:229 pass:190 dwarn:0 dfail:1 fail:0 skip:38 ro-byt-n2820 total:229 pass:178 dwarn:0 dfail:1 fail:5 skip:45 ro-hsw-i3-4010u total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-hsw-i7-4770r total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-ilk-i7-620lm total:229 pass:155 dwarn:0 dfail:1 fail:3 skip:70 ro-ilk1-i5-650 total:224 pass:155 dwarn:0 dfail:1 fail:3 skip:65 ro-ivb-i7-3770 total:229 pass:186 dwarn:0 dfail:1 fail:2 skip:40 ro-ivb2-i7-3770 total:229 pass:190 dwarn:0 dfail:1 fail:2 skip:36 ro-skl3-i5-6260u total:229 pass:206 dwarn:1 dfail:1 fail:2 skip:19 ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48 ro-bsw-n3050 failed to connect after reboot Results at /archive/results/CI_IGT_test/RO_Patchwork_1326/ a90c989 drm-intel-nightly: 2016y-06m-29d-09h-24m-21s UTC integration manifest f47ea06 drm/i915: Use atomic waits for short non-atomic ones 5d6ee68 drm/i915/debug: Select PREEMPT_COUNT when enabling debugging ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PACTH i-g-t v4 00/13] Remove compile time depencencies on libdrm_intel.
On 23 June 2016 at 10:34, wrote: > From: Robert Foss > > > Hey, > > I've been looking at the possibilty of removing the compile time depency on > libdrm_intel. There are two technical solutions to this problem as far as > I can see; stubs and conditional compilation. > > This series uses the stubbing approach. > > Changes since v1: > - Replaced the automake flags HAVE_VC4/NOUVEAU/INTEL with HAVE_LIBDRM_XXX. > - Move conditionals from Makefile.sources to Arduino.mk/Makefile.am. > - Removed duplicated i915_drm.h symbols from intel_drm_stubs.h. > - Replaced igt_require with igt_require_f to communicate stubs being the cause > of failure. > - Rename intel_drm_stubs to intel_bufmgr. > - Moved intel_bufmgr to lib/stubs/drm. > - Remove header inclusion changes in favor for inclusion of stubs in > lib/stubs/drm using build scripts. > - Rebased on trunk. > > Changes since v2: > - Removed conditional compilation from intel_bufmgr.h. > - Enable HAVE_LIBDRM_INTEL on android platforms. > - Remove unnecessary whitespace. > - Remove unnecessary inclusion of C files. > - De-duplicated intel_bufmgr.c error string. > - Changed Makefile.sources variable names to be non-automake specific > > Changes since v3: > - Added signoff to two commits. > - Changed automake if not statement. > - Removed accidental space character. > - Copied in new copy of intel_bufmgr.h > - Improved wording of lib/stubs/drm/README. > Just an idea/suggestion for the future, not sure if it's normal approach in IGT: Adding the detailed change log to the respective patch (be that before or after the --- line) as opposed to here is better IMHO. It provides provides direct, quick and easy feedback to the reviewer. Something that just hit me - 1/13 should only do "check for libdrm_intel and error otherwise. set the AC_CONDITIONAL()" with the actual "allow libdrm_intel less systems to build IGT" patch coming after the stubs were introduced. As-is building w/o libdrm_intel will be allowed, yet broken through the series, which shouldn't be an issue here. Just something worth mentioning for future work. As-is the series is Reviewed-by: Emil Velikov -Emil ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PACTH i-g-t] lib/igt_kms: Fix different order of properties and their name strings
From: Robert Foss
igt_crtc_prop_names and igt_atomic_crtc_properties have different orders of
properties, which is fixed in this patch.
Signed-off-by: Robert Foss
---
lib/igt_kms.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index af72b90..dd4eb84 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -164,8 +164,8 @@ static const char
*igt_plane_prop_names[IGT_NUM_PLANE_PROPS] = {
static const char *igt_crtc_prop_names[IGT_NUM_CRTC_PROPS] = {
"background_color",
- "DEGAMMA_LUT",
"CTM",
+ "DEGAMMA_LUT",
"GAMMA_LUT",
};
--
2.7.4
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[Intel-gfx] [PATCH v5] drm/i915: Use atomic waits for short non-atomic ones
From: Tvrtko Ursulin
usleep_range is not recommended for waits shorten than 10us.
Make the wait_for_us use the atomic variant for such waits.
To do so we need to reimplement the _wait_for_atomic macro to
be safe with regards to preemption and interrupts.
v2: Reimplement _wait_for_atomic to be irq and preemption safe.
(Chris Wilson and Imre Deak)
v3: Fixed in_atomic check due rebase error.
v4: Build bug on non-constant timeouts.
v5: Compile away cpu migration code in atomic paths.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
Cc: Imre Deak
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_drv.h | 62
1 file changed, 43 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3156d8df7921..98a5be4ec8c5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -69,39 +69,63 @@
})
#define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
-#define wait_for_us(COND, US) _wait_for((COND), (US), 1)
/* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
#if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
-# define _WAIT_FOR_ATOMIC_CHECK WARN_ON_ONCE(!in_atomic())
+# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
#else
-# define _WAIT_FOR_ATOMIC_CHECK do { } while (0)
+# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
#endif
-#define _wait_for_atomic(COND, US) ({ \
- unsigned long end__; \
- int ret__ = 0; \
- _WAIT_FOR_ATOMIC_CHECK; \
+#define _wait_for_atomic(COND, US, ATOMIC) \
+({ \
+ int cpu, ret, timeout = (US) * 1000; \
+ u64 base; \
+ _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
BUILD_BUG_ON((US) > 5); \
- end__ = (local_clock() >> 10) + (US) + 1; \
- while (!(COND)) { \
- if (time_after((unsigned long)(local_clock() >> 10), end__)) { \
- /* Unlike the regular wait_for(), this atomic variant \
-* cannot be preempted (and we'll just ignore the issue\
-* of irq interruptions) and so we know that no time \
-* has passed since the last check of COND and can \
-* immediately report the timeout. \
-*/ \
- ret__ = -ETIMEDOUT; \
+ if (!(ATOMIC)) { \
+ preempt_disable(); \
+ cpu = smp_processor_id(); \
+ } \
+ base = local_clock(); \
+ for (;;) { \
+ u64 now = local_clock(); \
+ if (!(ATOMIC)) \
+ preempt_enable(); \
+ if (COND) { \
+ ret = 0; \
+ break; \
+ } \
+ if (now - base >= timeout) { \
+ ret = -ETIMEDOUT; \
break; \
} \
cpu_relax(); \
+ if (!(ATOMIC)) { \
+ preempt_disable(); \
+ if (unlikely(cpu != smp_processor_id())) { \
+ timeout -= now - base; \
+ cpu = smp_processor_id(); \
+ base = local_clock(); \
+ } \
+ } \
} \
+ ret; \
+})
+
+#define wait_for_us(COND, US) \
+({ \
+ int ret__; \
+ BUILD_BUG_ON(!__builtin_constant_p(US)); \
+ if ((US) > 10) \
+ ret__ = _wait_for((COND), (US), 10); \
+ else \
+ ret__ = _wait_for_atomic((COND), (US), 0); \
ret__; \
})
-#define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000)
-#define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US))
+#define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000, 1)
+#define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US), 1)
#define KHz(x) (1000 * (x))
#define MHz(x) KHz(1000 * (x))
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5] drm/i915: Use atomic waits for short non-atomic ones
On Wed, Jun 29, 2016 at 12:27:22PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > usleep_range is not recommended for waits shorten than 10us. > > Make the wait_for_us use the atomic variant for such waits. > > To do so we need to reimplement the _wait_for_atomic macro to > be safe with regards to preemption and interrupts. > > v2: Reimplement _wait_for_atomic to be irq and preemption safe. > (Chris Wilson and Imre Deak) > > v3: Fixed in_atomic check due rebase error. > v4: Build bug on non-constant timeouts. > v5: Compile away cpu migration code in atomic paths. > > Signed-off-by: Tvrtko Ursulin > Cc: Chris Wilson > Cc: Imre Deak > Cc: Mika Kuoppala I like the polish. Reviewed-by: Chris Wilson Using wait_for_hybrid() is really tempting, just need to kick Mika to finish intel_wait_for_register()... -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 02/17] intel_chipset: Convert IS_MOBILE to intel_device_info
Signed-off-by: Chris Wilson --- lib/intel_chipset.h | 12 ++-- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 69c878b..ce130ed 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -273,16 +273,6 @@ void intel_check_pch(void); #endif /* __GTK_DOC_IGNORE__ */ -#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ -(devid) == PCI_CHIP_I915_GM || \ -(devid) == PCI_CHIP_I945_GM || \ -(devid) == PCI_CHIP_I945_GME || \ -(devid) == PCI_CHIP_I965_GM || \ -(devid) == PCI_CHIP_I965_GME || \ -(devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \ -(devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \ -(devid) == PCI_CHIP_IVYBRIDGE_M_GT2) - #define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \ (devid) == PCI_CHIP_Q45_G || \ (devid) == PCI_CHIP_G45_G || \ @@ -490,6 +480,8 @@ void intel_check_pch(void); #define IS_GEN8(devid) IS_GEN(devid, 8) #define IS_GEN9(devid) IS_GEN(devid, 9) +#define IS_MOBILE(devid) (intel_device_info(devid)->is_mobile) + #define HAS_BSD_RING(devid)AT_LEAST_GEN(devid, 5) #define HAS_BLT_RING(devid)AT_LEAST_GEN(devid, 6) -- 2.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 16/17] intel_chipset: Replace lookup of GT size with computation
Instead of a large if-chain for matching devid to GT, we can just
compute it directly from the encoded devid.
Signed-off-by: Chris Wilson
---
debugger/eudb.c | 14 +++---
lib/intel_chipset.h | 109 +-
lib/intel_device_info.c | 23 ++
tools/intel_l3_parity.c | 15 +++
tools/intel_reg_checker.c | 19
5 files changed, 46 insertions(+), 134 deletions(-)
diff --git a/debugger/eudb.c b/debugger/eudb.c
index 47d5d92..866d4b5 100644
--- a/debugger/eudb.c
+++ b/debugger/eudb.c
@@ -351,16 +351,14 @@ die(int reason) {
static int
identify_device(int devid) {
- switch(devid) {
- case PCI_CHIP_SANDYBRIDGE_GT1:
- case PCI_CHIP_SANDYBRIDGE_M_GT1:
- case PCI_CHIP_SANDYBRIDGE_S:
+ if (!IS_SANDYBRIDGE(devid))
+ return -ENODEV;
+
+ switch (intel_gt(devid)) {
+ case 0:
eu_info = >1;
break;
- case PCI_CHIP_SANDYBRIDGE_GT2:
- case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
- case PCI_CHIP_SANDYBRIDGE_M_GT2:
- case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
+ case 1:
eu_info = >2;
break;
default:
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index e3e97ff..4234361 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -67,6 +67,7 @@ const struct intel_device_info {
} *intel_device_info(uint16_t devid) __attribute__((pure));
unsigned intel_gen(uint16_t devid) __attribute__((pure));
+unsigned intel_gt(uint16_t devid) __attribute__((pure));
extern enum pch_type intel_pch;
@@ -269,114 +270,6 @@ void intel_check_pch(void);
#endif /* __GTK_DOC_IGNORE__ */
-#define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
-(devid) == PCI_CHIP_HASWELL_M_GT1 || \
-(devid) == PCI_CHIP_HASWELL_S_GT1 || \
-(devid) == PCI_CHIP_HASWELL_B_GT1 || \
-(devid) == PCI_CHIP_HASWELL_E_GT1 || \
-(devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
-(devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
-(devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
-(devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
-(devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
-(devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
-(devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
-(devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
-(devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
-(devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
-(devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
-(devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
-(devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
-(devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
-(devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
-#define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \
-(devid) == PCI_CHIP_HASWELL_M_GT2 || \
-(devid) == PCI_CHIP_HASWELL_S_GT2 || \
-(devid) == PCI_CHIP_HASWELL_B_GT2 || \
-(devid) == PCI_CHIP_HASWELL_E_GT2 || \
-(devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
-(devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
-(devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
-(devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
-(devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
-(devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
-(devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
-(devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
-(devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
-(devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
-(devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
-(devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
-(devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
-(devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
-(devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
-#define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \
-(devid) == PCI_CHIP_HASWELL_M_GT3 || \
-(devid) == PCI_CHIP_HASWELL_S_GT3 || \
-(devid) == PCI_CHIP_HASWELL_B_GT3 || \
-
[Intel-gfx] [PATCH igt 01/17] lib: Start weaning off defunct intel_chipset.h
Several years ago we made the plan of only having one canonical source for i915_pciids.h, the kernel and everyone importing their definitions from that. For consistency, we style the intel_device_info after the kernel, most notably using a generation mask and a per-codename bitfield. This first step converts looking up the generation for a devid tree from a massive if(devid)-chain to a (cached) table lookup. Signed-off-by: Chris Wilson --- lib/Makefile.sources | 3 +- lib/drmtest.c | 2 +- lib/i915_pciids.h | 132 +- lib/intel_chipset.c| 31 - lib/intel_chipset.h| 116 +++- lib/intel_device_info.c| 288 ++ overlay/i915_pciids.h | 339 - overlay/igfx.c | 2 +- tools/intel_audio_dump.c | 12 +- tools/intel_error_decode.c | 2 +- tools/intel_reg.c | 21 +-- 11 files changed, 476 insertions(+), 472 deletions(-) create mode 100644 lib/intel_device_info.c delete mode 100644 overlay/i915_pciids.h diff --git a/lib/Makefile.sources b/lib/Makefile.sources index 3589e26..8cad9d5 100644 --- a/lib/Makefile.sources +++ b/lib/Makefile.sources @@ -26,11 +26,12 @@ libintel_tools_la_SOURCES = \ instdone.h \ intel_batchbuffer.c \ intel_batchbuffer.h \ + intel_chipset.c \ intel_chipset.h \ + intel_device_info.c \ intel_os.c \ intel_io.h \ intel_mmio.c\ - intel_chipset.c \ intel_reg.h \ ioctl_wrappers.c\ ioctl_wrappers.h\ diff --git a/lib/drmtest.c b/lib/drmtest.c index 884fe7c..62dd042 100644 --- a/lib/drmtest.c +++ b/lib/drmtest.c @@ -127,7 +127,7 @@ static bool has_known_intel_chipset(int fd) if (ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp))) return false; - if (!IS_INTEL(devid)) + if (!intel_gen(devid)) return false; __drm_device_id = devid; diff --git a/lib/i915_pciids.h b/lib/i915_pciids.h index 8a10f5c..33466bf 100644 --- a/lib/i915_pciids.h +++ b/lib/i915_pciids.h @@ -191,8 +191,8 @@ INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \ INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ - INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \ - INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \ + INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \ + INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \ INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \ INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \ INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \ @@ -208,4 +208,132 @@ #define INTEL_VLV_D_IDS(info) \ INTEL_VGA_DEVICE(0x0155, info) +#define INTEL_BDW_GT12M_IDS(info) \ + INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \ + INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \ + INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \ + INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \ + INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \ + INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \ + INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \ + INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */ + +#define INTEL_BDW_GT12D_IDS(info) \ + INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \ + INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \ + INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \ + INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */ + +#define INTEL_BDW_GT3M_IDS(info) \ + INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \ + INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \ + INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \ + INTEL_VGA_DEVICE(0x162E, info) /* ULX */ + +#define INTEL_BDW_GT3D_IDS(info) \ + INTEL_VGA_DEVICE(0x162A, info), /* Server */ \ + INTEL_VGA_DEVICE(0x162D, info) /* Workstation */ + +#define INTEL_BDW_RSVDM_IDS(info) \ + INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \ + INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \ + INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \ + INTEL_VGA_DEVICE(0x163E, info) /* ULX */ + +#define INTEL_BDW_RSVDD_IDS(info) \ + INTEL_VGA_DEVICE(0x163A, info), /* Server */ \ + INTEL_VGA_DEVICE(0x163D, info) /* Workstation */ + +#define INTEL_BDW_M_IDS(info) \ + INTEL_BDW_GT12M_IDS(info), \ + INTEL_BDW_GT3M_IDS(info), \ + INTEL_BDW_RSVDM_IDS(info) + +#define INTEL_BDW_D_IDS(info) \ + INTEL_BDW_GT12D_IDS(info), \ + INTEL_BDW_GT3D_IDS(info), \ + INTEL_BDW_RSVDD_IDS(info) + +#define INTEL_CHV_IDS(info) \ + INTEL_VGA_DEVICE(0x22b0, info), \ + INTEL_VGA_DEVICE(0x22b1, info), \ +
[Intel-gfx] [PATCH igt 10/17] intel_chipset: Convert IS_VALLEYVIEW to device info
Signed-off-by: Chris Wilson --- lib/intel_chipset.h | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 162216e..1c167f0 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -306,11 +306,6 @@ void intel_check_pch(void); (devid) == PCI_CHIP_IVYBRIDGE_S || \ (devid) == PCI_CHIP_IVYBRIDGE_S_GT2) -#define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \ -(devid) == PCI_CHIP_VALLEYVIEW_1 || \ -(devid) == PCI_CHIP_VALLEYVIEW_2 || \ -(devid) == PCI_CHIP_VALLEYVIEW_3) - #define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \ (devid) == PCI_CHIP_HASWELL_M_GT1 || \ (devid) == PCI_CHIP_HASWELL_S_GT1 || \ @@ -419,6 +414,7 @@ void intel_check_pch(void); #define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4) +#define IS_VALLEYVIEW(devid) (intel_device_info(devid)->is_valleyview) #define IS_HASWELL(devid) (intel_device_info(devid)->is_haswell) #define IS_BROADWELL(devid)(intel_device_info(devid)->is_broadwell) #define IS_CHERRYVIEW(devid) (intel_device_info(devid)->is_cherryview) -- 2.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 06/17] intel_chipset: Convert IS_SKYLAKE to device info
Signed-off-by: Chris Wilson --- lib/intel_chipset.h | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 37f8ed0..146c650 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -442,11 +442,7 @@ void intel_check_pch(void); IS_KBL_GT3(devid) || \ IS_KBL_GT4(devid)) -#define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ -IS_SKL_GT2(devid) || \ -IS_SKL_GT3(devid) || \ -IS_SKL_GT4(devid)) - +#define IS_SKYLAKE(devid) (intel_device_info(devid)->is_skylake) #define IS_BROXTON(devid) (intel_device_info(devid)->is_broxton) #define IS_BROADWATER(devid) (intel_device_info(devid)->is_broadwater) -- 2.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 09/17] intel_chipset: Convert IS_HASWELL to device info
Signed-off-by: Chris Wilson --- lib/intel_chipset.h | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index b56457a..162216e 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -372,10 +372,6 @@ void intel_check_pch(void); (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \ (devid) == PCI_CHIP_HASWELL_CRW_E_GT3) -#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ -IS_HSW_GT2(devid) || \ -IS_HSW_GT3(devid)) - #define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1|| \ (devid) == PCI_CHIP_SKYLAKE_ULX_GT1|| \ (devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \ @@ -423,6 +419,7 @@ void intel_check_pch(void); #define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4) +#define IS_HASWELL(devid) (intel_device_info(devid)->is_haswell) #define IS_BROADWELL(devid)(intel_device_info(devid)->is_broadwell) #define IS_CHERRYVIEW(devid) (intel_device_info(devid)->is_cherryview) #define IS_KABYLAKE(devid) (intel_device_info(devid)->is_kabylake) -- 2.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 11/17] intel_chipset: Convert IS_IRONALKE to device info
Signed-off-by: Chris Wilson --- lib/intel_chipset.h | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 1c167f0..f516d8e 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -299,13 +299,6 @@ void intel_check_pch(void); (devid) == PCI_CHIP_Q33_G || \ (devid) == PCI_CHIP_Q35_G || IS_IGD(devid)) -#define IS_IVYBRIDGE(devid)((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \ -(devid) == PCI_CHIP_IVYBRIDGE_GT2 || \ -(devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \ -(devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \ -(devid) == PCI_CHIP_IVYBRIDGE_S || \ -(devid) == PCI_CHIP_IVYBRIDGE_S_GT2) - #define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \ (devid) == PCI_CHIP_HASWELL_M_GT1 || \ (devid) == PCI_CHIP_HASWELL_S_GT1 || \ @@ -414,6 +407,7 @@ void intel_check_pch(void); #define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4) +#define IS_IVYBRIDGE(devid)(intel_device_info(devid)->is_ivybridge) #define IS_VALLEYVIEW(devid) (intel_device_info(devid)->is_valleyview) #define IS_HASWELL(devid) (intel_device_info(devid)->is_haswell) #define IS_BROADWELL(devid)(intel_device_info(devid)->is_broadwell) -- 2.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 04/17] intel_chipset: Convert IS_BROADWATER, IS_CRESTLINE to device info
Signed-off-by: Chris Wilson --- lib/intel_chipset.h | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 8f159ea..6f7f26d 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -453,13 +453,8 @@ void intel_check_pch(void); (devid) == PCI_CHIP_BROXTON_3 || \ (devid) == PCI_CHIP_BROXTON_4) -#define IS_BROADWATER(devid) ((devid) == PCI_CHIP_I946_GZ || \ -(devid) == PCI_CHIP_I965_G_1 || \ -(devid) == PCI_CHIP_I965_Q || \ -(devid) == PCI_CHIP_I965_G) - -#define IS_CRESTLINE(devid)((devid) == PCI_CHIP_I965_GM || \ -(devid) == PCI_CHIP_I965_GME) +#define IS_BROADWATER(devid) (intel_device_info(devid)->is_broadwater) +#define IS_CRESTLINE(devid)(intel_device_info(devid)->is_crestline) #define IS_GEN(devid, x) (intel_device_info(devid)->gen & (1u << ((x)-1))) #define AT_LEAST_GEN(devid, x) (intel_device_info(devid)->gen & -(1u << ((x)-1))) -- 2.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 14/17] intel_chipset: Convert IS_915, IS_945 to device info
Signed-off-by: Chris Wilson --- lib/intel_chipset.h | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index a40a857..9806f2f 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -276,18 +276,6 @@ void intel_check_pch(void); #define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM) #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid)) -#define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \ -(devid) == PCI_CHIP_E7221_G || \ -(devid) == PCI_CHIP_I915_GM) - -#define IS_945GM(devid)((devid) == PCI_CHIP_I945_GM || \ -(devid) == PCI_CHIP_I945_GME) - -#define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \ -(devid) == PCI_CHIP_I945_GM || \ -(devid) == PCI_CHIP_I945_GME || \ -IS_G33(devid)) - #define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \ (devid) == PCI_CHIP_HASWELL_M_GT1 || \ (devid) == PCI_CHIP_HASWELL_S_GT1 || \ @@ -396,6 +384,18 @@ void intel_check_pch(void); #define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4) +#define IS_915G(devid) (intel_device_info(devid)->is_grantsdale) +#define IS_915GM(devid)(intel_device_info(devid)->is_alviso) + +#define IS_915(devid) (IS_915G(devid) || IS_915GM(devid)) + +#define IS_945G(devid) (intel_device_info(devid)->is_lakeport) +#define IS_945GM(devid)(intel_device_info(devid)->is_calistoga) + +#define IS_945(devid) (IS_945G(devid) || \ +IS_945GM(devid) || \ +IS_G33(devid)) + #define IS_PINEVIEW(devid) (intel_device_info(devid)->is_pineview) #define IS_G33(devid) (intel_device_info(devid)->is_bearlake || \ intel_device_info(devid)->is_pineview) -- 2.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 07/17] intel_chipset: Convert IS_CHERRYVIEW to device info
Signed-off-by: Chris Wilson --- lib/intel_chipset.h | 12 ++-- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 146c650..c4f64dc 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -385,11 +385,6 @@ void intel_check_pch(void); (((devid) & 0x000f) == BDW_WORKSTATION) ? 1 : \ (((devid) & 0x000f) == BDW_ULX) ? 1 : 0) -#define IS_CHERRYVIEW(devid) ((devid) == PCI_CHIP_CHERRYVIEW_0 || \ -(devid) == PCI_CHIP_CHERRYVIEW_1 || \ -(devid) == PCI_CHIP_CHERRYVIEW_2 || \ -(devid) == PCI_CHIP_CHERRYVIEW_3) - #define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1|| \ (devid) == PCI_CHIP_SKYLAKE_ULX_GT1|| \ (devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \ @@ -437,11 +432,8 @@ void intel_check_pch(void); #define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4) -#define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \ -IS_KBL_GT2(devid) || \ -IS_KBL_GT3(devid) || \ -IS_KBL_GT4(devid)) - +#define IS_CHERRYVIEW(devid) (intel_device_info(devid)->is_cherryview) +#define IS_KABYLAKE(devid) (intel_device_info(devid)->is_kabylake) #define IS_SKYLAKE(devid) (intel_device_info(devid)->is_skylake) #define IS_BROXTON(devid) (intel_device_info(devid)->is_broxton) -- 2.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 03/17] intel_chipset: Convert IS_965 to use intel_gen()
Signed-off-by: Chris Wilson --- lib/intel_chipset.h | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index ce130ed..8f159ea 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -453,13 +453,6 @@ void intel_check_pch(void); (devid) == PCI_CHIP_BROXTON_3 || \ (devid) == PCI_CHIP_BROXTON_4) -#define IS_965(devid) (IS_GEN4(devid) || \ -IS_GEN5(devid) || \ -IS_GEN6(devid) || \ -IS_GEN7(devid) || \ -IS_GEN8(devid) || \ -IS_GEN9(devid)) - #define IS_BROADWATER(devid) ((devid) == PCI_CHIP_I946_GZ || \ (devid) == PCI_CHIP_I965_G_1 || \ (devid) == PCI_CHIP_I965_Q || \ @@ -481,6 +474,7 @@ void intel_check_pch(void); #define IS_GEN9(devid) IS_GEN(devid, 9) #define IS_MOBILE(devid) (intel_device_info(devid)->is_mobile) +#define IS_965(devid) AT_LEAST_GEN(devid, 4) #define HAS_BSD_RING(devid)AT_LEAST_GEN(devid, 5) #define HAS_BLT_RING(devid)AT_LEAST_GEN(devid, 6) -- 2.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 05/17] intel_chipset: Convert IS_BROXTON to device info
Signed-off-by: Chris Wilson --- lib/intel_chipset.h | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 6f7f26d..37f8ed0 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -447,11 +447,7 @@ void intel_check_pch(void); IS_SKL_GT3(devid) || \ IS_SKL_GT4(devid)) -#define IS_BROXTON(devid) ((devid) == PCI_CHIP_BROXTON_0 || \ -(devid) == PCI_CHIP_BROXTON_1 || \ -(devid) == PCI_CHIP_BROXTON_2 || \ -(devid) == PCI_CHIP_BROXTON_3 || \ -(devid) == PCI_CHIP_BROXTON_4) +#define IS_BROXTON(devid) (intel_device_info(devid)->is_broxton) #define IS_BROADWATER(devid) (intel_device_info(devid)->is_broadwater) #define IS_CRESTLINE(devid)(intel_device_info(devid)->is_crestline) -- 2.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 15/17] intel_chipset: Convert IS_G4X to device info
Signed-off-by: Chris Wilson --- lib/intel_chipset.h | 17 +++-- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 9806f2f..e3e97ff 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -269,13 +269,6 @@ void intel_check_pch(void); #endif /* __GTK_DOC_IGNORE__ */ -#define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \ -(devid) == PCI_CHIP_Q45_G || \ -(devid) == PCI_CHIP_G45_G || \ -(devid) == PCI_CHIP_G41_G) -#define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM) -#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid)) - #define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \ (devid) == PCI_CHIP_HASWELL_M_GT1 || \ (devid) == PCI_CHIP_HASWELL_S_GT1 || \ @@ -400,6 +393,13 @@ void intel_check_pch(void); #define IS_G33(devid) (intel_device_info(devid)->is_bearlake || \ intel_device_info(devid)->is_pineview) +#define IS_BROADWATER(devid) (intel_device_info(devid)->is_broadwater) +#define IS_CRESTLINE(devid)(intel_device_info(devid)->is_crestline) + +#define IS_GM45(devid) (intel_device_info(devid)->is_cantiga) +#define IS_G45(devid) (intel_device_info(devid)->is_eaglelake) +#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid)) + #define IS_IRONLAKE(devid) (intel_device_info(devid)->is_ironlake) #define IS_ARRANDALE(devid)(intel_device_info(devid)->is_arrandale) #define IS_IVYBRIDGE(devid)(intel_device_info(devid)->is_ivybridge) @@ -411,9 +411,6 @@ void intel_check_pch(void); #define IS_SKYLAKE(devid) (intel_device_info(devid)->is_skylake) #define IS_BROXTON(devid) (intel_device_info(devid)->is_broxton) -#define IS_BROADWATER(devid) (intel_device_info(devid)->is_broadwater) -#define IS_CRESTLINE(devid)(intel_device_info(devid)->is_crestline) - #define IS_GEN(devid, x) (intel_device_info(devid)->gen & (1u << ((x)-1))) #define AT_LEAST_GEN(devid, x) (intel_device_info(devid)->gen & -(1u << ((x)-1))) -- 2.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 08/17] intel_chipset: Convert IS_BROADWELL to device info
Signed-off-by: Chris Wilson --- lib/intel_chipset.h | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index c4f64dc..b56457a 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -376,15 +376,6 @@ void intel_check_pch(void); IS_HSW_GT2(devid) || \ IS_HSW_GT3(devid)) -#define IS_BROADWELL(devid)devid) & 0xff00) != 0x1600) ? 0 : \ - devid) & 0x00f0) >> 4) > 3) ? 0 : \ -(((devid) & 0x000f) == BDW_SPARE) ? 1 : \ -(((devid) & 0x000f) == BDW_ULT) ? 1 : \ -(((devid) & 0x000f) == BDW_HALO) ? 1 : \ -(((devid) & 0x000f) == BDW_SERVER) ? 1 : \ -(((devid) & 0x000f) == BDW_WORKSTATION) ? 1 : \ -(((devid) & 0x000f) == BDW_ULX) ? 1 : 0) - #define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1|| \ (devid) == PCI_CHIP_SKYLAKE_ULX_GT1|| \ (devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \ @@ -432,6 +423,7 @@ void intel_check_pch(void); #define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4) +#define IS_BROADWELL(devid)(intel_device_info(devid)->is_broadwell) #define IS_CHERRYVIEW(devid) (intel_device_info(devid)->is_cherryview) #define IS_KABYLAKE(devid) (intel_device_info(devid)->is_kabylake) #define IS_SKYLAKE(devid) (intel_device_info(devid)->is_skylake) -- 2.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 12/17] intel_chipset: Convert IS_IRONLAKE to device info
Signed-off-by: Chris Wilson --- lib/intel_chipset.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index f516d8e..4f532a9 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -280,9 +280,6 @@ void intel_check_pch(void); #define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM) #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid)) -#define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G) -#define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G) - #define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \ (devid) == PCI_CHIP_E7221_G || \ (devid) == PCI_CHIP_I915_GM) @@ -407,6 +404,8 @@ void intel_check_pch(void); #define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4) +#define IS_IRONLAKE(devid) (intel_device_info(devid)->is_ironlake) +#define IS_ARRANDALE(devid)(intel_device_info(devid)->is_arrandale) #define IS_IVYBRIDGE(devid)(intel_device_info(devid)->is_ivybridge) #define IS_VALLEYVIEW(devid) (intel_device_info(devid)->is_valleyview) #define IS_HASWELL(devid) (intel_device_info(devid)->is_haswell) -- 2.8.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 13/17] intel_chipset: Convert IS_PINEVIEW to device info
Signed-off-by: Chris Wilson
---
lib/intel_chipset.h | 12
tools/intel_reg_decode.c | 4 ++--
tools/intel_watermark.c | 2 +-
3 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 4f532a9..a40a857 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -111,10 +111,6 @@ void intel_check_pch(void);
#define PCI_CHIP_IGD_GM0xA011
#define PCI_CHIP_IGD_G 0xA001
-#define IS_IGDGM(devid)((devid) == PCI_CHIP_IGD_GM)
-#define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G)
-#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
-
#define PCI_CHIP_I965_G0x29A2
#define PCI_CHIP_I965_Q0x2992
#define PCI_CHIP_I965_G_1 0x2982
@@ -292,10 +288,6 @@ void intel_check_pch(void);
(devid) == PCI_CHIP_I945_GME || \
IS_G33(devid))
-#define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \
-(devid) == PCI_CHIP_Q33_G || \
-(devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
-
#define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
(devid) == PCI_CHIP_HASWELL_M_GT1 || \
(devid) == PCI_CHIP_HASWELL_S_GT1 || \
@@ -404,6 +396,10 @@ void intel_check_pch(void);
#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4)
+#define IS_PINEVIEW(devid) (intel_device_info(devid)->is_pineview)
+#define IS_G33(devid) (intel_device_info(devid)->is_bearlake || \
+intel_device_info(devid)->is_pineview)
+
#define IS_IRONLAKE(devid) (intel_device_info(devid)->is_ironlake)
#define IS_ARRANDALE(devid)(intel_device_info(devid)->is_arrandale)
#define IS_IVYBRIDGE(devid)(intel_device_info(devid)->is_ivybridge)
diff --git a/tools/intel_reg_decode.c b/tools/intel_reg_decode.c
index 2536554..71f3ead 100644
--- a/tools/intel_reg_decode.c
+++ b/tools/intel_reg_decode.c
@@ -392,7 +392,7 @@ DEBUGSTRING(i830_debug_vgacntrl)
DEBUGSTRING(i830_debug_fp)
{
- if (IS_IGD(devid)) {
+ if (IS_PINEVIEW(devid)) {
snprintf(result, len, "n = %d, m1 = %d, m2 = %d",
ffs((val & FP_N_IGD_DIV_MASK) >>
FP_N_DIV_SHIFT) - 1,
@@ -496,7 +496,7 @@ DEBUGSTRING(i830_debug_dpll)
}
#endif
} else {
- if (IS_IGD(devid)) {
+ if (IS_PINEVIEW(devid)) {
p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
} else {
diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
index 133c058..68bd8ec 100644
--- a/tools/intel_watermark.c
+++ b/tools/intel_watermark.c
@@ -909,7 +909,7 @@ int main(int argc, char *argv[])
g4x_wm_dump();
} else if (IS_GEN4(devid)) {
gen4_wm_dump();
- } else if (IS_IGD(devid)) {
+ } else if (IS_PINEVIEW(devid)) {
pnv_wm_dump();
} else if (IS_GEN3(devid)) {
gen3_wm_dump();
--
2.8.1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH igt 17/17] intel_chipset: Remove unused PCI_CHIP ids
These are now taken from i915_pciids.h. However, some of the older ids are still used explicitly for per-devid information, and so are not yet removable. Signed-off-by: Chris Wilson --- lib/intel_chipset.h | 150 1 file changed, 150 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 4234361..1716b83 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -105,13 +105,6 @@ void intel_check_pch(void); #define PCI_CHIP_I945_GM 0x27A2 #define PCI_CHIP_I945_GME 0x27AE -#define PCI_CHIP_Q35_G 0x29B2 -#define PCI_CHIP_G33_G 0x29C2 -#define PCI_CHIP_Q33_G 0x29D2 - -#define PCI_CHIP_IGD_GM0xA011 -#define PCI_CHIP_IGD_G 0xA001 - #define PCI_CHIP_I965_G0x29A2 #define PCI_CHIP_I965_Q0x2992 #define PCI_CHIP_I965_G_1 0x2982 @@ -121,153 +114,10 @@ void intel_check_pch(void); #define PCI_CHIP_GM45_GM 0x2A42 -#define PCI_CHIP_IGD_E_G 0x2E02 #define PCI_CHIP_Q45_G 0x2E12 #define PCI_CHIP_G45_G 0x2E22 #define PCI_CHIP_G41_G 0x2E32 -#define PCI_CHIP_ILD_G 0x0042 -#define PCI_CHIP_ILM_G 0x0046 - -#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */ -#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112 -#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122 -#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */ -#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116 -#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS0x0126 -#define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */ - -#define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */ -#define PCI_CHIP_IVYBRIDGE_GT2 0x0162 -#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */ -#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 -#define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */ -#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */ - -#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ -#define PCI_CHIP_HASWELL_GT2 0x0412 -#define PCI_CHIP_HASWELL_GT3 0x0422 -#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ -#define PCI_CHIP_HASWELL_M_GT2 0x0416 -#define PCI_CHIP_HASWELL_M_GT3 0x0426 -#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ -#define PCI_CHIP_HASWELL_S_GT2 0x041A -#define PCI_CHIP_HASWELL_S_GT3 0x042A -#define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */ -#define PCI_CHIP_HASWELL_B_GT2 0x041B -#define PCI_CHIP_HASWELL_B_GT3 0x042B -#define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */ -#define PCI_CHIP_HASWELL_E_GT2 0x041E -#define PCI_CHIP_HASWELL_E_GT3 0x042E -#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */ -#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12 -#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22 -#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */ -#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 -#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26 -#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */ -#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A -#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A -#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */ -#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B -#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B -#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */ -#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E -#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E -#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */ -#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12 -#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22 -#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */ -#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 -#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26 -#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ -#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A -#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A -#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */ -#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B -#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B -#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */ -#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E -#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E -#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */ -#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12 -#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22 -#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */ -#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 -#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26 -#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */ -#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A -#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A -#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */ -#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B -#define
[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [1/2] drm/i915/debug: Select PREEMPT_COUNT when enabling debugging (rev5)
== Series Details == Series: series starting with [1/2] drm/i915/debug: Select PREEMPT_COUNT when enabling debugging (rev5) URL : https://patchwork.freedesktop.org/series/9226/ State : failure == Summary == Series 9226v5 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/9226/revisions/5/mbox Test drv_module_reload_basic: dmesg-warn -> PASS (ro-byt-n2820) Test gem_exec_suspend: Subgroup basic-s3: pass -> INCOMPLETE (fi-hsw-i7-4770k) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: dmesg-warn -> SKIP (ro-bdw-i5-5250u) Subgroup suspend-read-crc-pipe-c: dmesg-warn -> SKIP (ro-bdw-i5-5250u) fi-hsw-i7-4770k total:103 pass:86 dwarn:0 dfail:0 fail:0 skip:16 fi-kbl-qkkr total:229 pass:161 dwarn:29 dfail:0 fail:0 skip:39 fi-skl-i5-6260u total:229 pass:202 dwarn:0 dfail:0 fail:2 skip:25 fi-skl-i7-6700k total:229 pass:188 dwarn:0 dfail:0 fail:2 skip:39 fi-snb-i7-2600 total:229 pass:174 dwarn:0 dfail:0 fail:2 skip:53 ro-bdw-i5-5250u total:229 pass:202 dwarn:1 dfail:1 fail:2 skip:23 ro-bdw-i7-5600u total:229 pass:190 dwarn:0 dfail:1 fail:0 skip:38 ro-bsw-n3050 total:229 pass:177 dwarn:0 dfail:1 fail:2 skip:49 ro-byt-n2820 total:229 pass:178 dwarn:0 dfail:1 fail:5 skip:45 ro-hsw-i3-4010u total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-hsw-i7-4770r total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-ilk-i7-620lm total:229 pass:154 dwarn:0 dfail:1 fail:4 skip:70 ro-ilk1-i5-650 total:224 pass:155 dwarn:0 dfail:1 fail:3 skip:65 ro-ivb-i7-3770 total:229 pass:186 dwarn:0 dfail:1 fail:2 skip:40 ro-ivb2-i7-3770 total:229 pass:190 dwarn:0 dfail:1 fail:2 skip:36 ro-skl3-i5-6260u total:229 pass:206 dwarn:1 dfail:1 fail:2 skip:19 ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48 ro-bdw-i7-5557U failed to connect after reboot Results at /archive/results/CI_IGT_test/RO_Patchwork_1327/ a90c989 drm-intel-nightly: 2016y-06m-29d-09h-24m-21s UTC integration manifest d5eba7b drm/i915: Use atomic waits for short non-atomic ones 41208f4 drm/i915/debug: Select PREEMPT_COUNT when enabling debugging ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC v2] drm/i915/chv: Clip cursor for CHV pipe C HW Cursor pos < 0
From: Shobhit Kumar
CHV pipe C hits underrun when we get negative crtc_x values of cursor.
To avoid this we clip and shift the cursor image by negative crtc_x
value.
v2: Make a copy of cursor plane state and allocate new gem object and fb
for clipped cursor and use that in case of negative cursor position
v3: Updated error handling
Pin the gem object before use.
Signed-off-by: Akshu Agrawal
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 7 ++
drivers/gpu/drm/i915/intel_display.c | 131 ++-
2 files changed, 137 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 724d34b..1e59c02 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2041,6 +2041,13 @@ struct drm_i915_private {
struct intel_encoder *dig_port_map[I915_MAX_PORTS];
/*
+ * Temporary copy of cursor plane state for CHV PIPE_C
+ * Will be initialized only when crtc_x < 0 as there is a
+ * HW bug causing pipe underrun
+ */
+ struct intel_plane_state *cursor_state;
+
+ /*
* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
* will be rejected. Instead look for a better place.
*/
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c3b5dc8..e6c103a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14456,6 +14456,132 @@ intel_update_cursor_plane(struct drm_plane *plane,
intel_crtc_update_cursor(crtc, state);
}
+static void
+intel_update_chv_pipe_c_cursor_plane(struct drm_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *state)
+{
+ struct drm_crtc *crtc = crtc_state->base.crtc;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct drm_device *dev = plane->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
+ struct drm_i915_gem_object *cur_obj = NULL, *use_obj = NULL;
+ uint32_t addr;
+ struct intel_plane_state *cursor_state = dev_priv->cursor_state;
+ const struct intel_plane_state *use_state;
+ char __iomem *src, *dst;
+ bool pinned = true;
+
+ if (state->visible && state->base.crtc_x < 0) {
+ int bytes_per_pixel = state->base.fb->bits_per_pixel / 8;
+ int x = state->base.crtc_x;
+ int width = state->base.crtc_w;
+ int height = state->base.crtc_h;
+ struct drm_mode_fb_cmd2 mode_cmd = { 0 };
+ int i;
+
+ if (!cursor_state) {
+ cursor_state = kzalloc(sizeof(*cursor_state),
GFP_KERNEL);
+ if (!cursor_state) {
+ use_state = state;
+ use_obj = obj;
+ goto update;
+ }
+
+ memcpy(cursor_state, state, sizeof(*state));
+
+ /* Allocate new gem object */
+ cur_obj = i915_gem_object_create(dev, obj->base.size);
+ if (IS_ERR(cur_obj))
+ goto gem_err;
+
+ mode_cmd.width = cursor_state->base.fb->width;
+ mode_cmd.height = cursor_state->base.fb->height;
+ mode_cmd.pitches[0] = cursor_state->base.fb->pitches[0];
+ mode_cmd.pixel_format =
cursor_state->base.fb->pixel_format;
+
+ cursor_state->base.fb = intel_framebuffer_create(dev,
&mode_cmd, cur_obj);
+ if (IS_ERR(cursor_state->base.fb)) {
+
drm_gem_object_unreference_unlocked(&cur_obj->base);
+ goto gem_err;
+ }
+
+ if (i915_gem_obj_ggtt_pin(cur_obj, 0, 0) < 0) {
+
drm_gem_object_unreference_unlocked(&cur_obj->base);
+ pinned = false;
+ goto cleanup;
+ }
+
+ dev_priv->cursor_state = cursor_state;
+ } else
+ cur_obj = intel_fb_obj(cursor_state->base.fb);
+
+ src = ioremap_wc(dev_priv->ggtt.mappable_base +
+ i915_gem_obj_ggtt_offset(obj),
+ obj->base.size);
+
+ dst = ioremap_wc(dev_priv->ggtt.mappable_base +
+ i915_gem_obj_ggtt_offset(cur_obj),
+ cur_obj->base.size);
+
+ /* shift the original cusrsor in to copy buffer offsetting -ive
pos */
+ x = -x;
+ for (i = 0; i < height;
Re: [Intel-gfx] [RFC v2] drm/i915/chv: Clip cursor for CHV pipe C HW Cursor pos < 0
On 06/29/2016 06:24 PM, Shobhit Kumar wrote:
From: Shobhit Kumar
CHV pipe C hits underrun when we get negative crtc_x values of cursor.
To avoid this we clip and shift the cursor image by negative crtc_x
value.
v2: Make a copy of cursor plane state and allocate new gem object and fb
for clipped cursor and use that in case of negative cursor position
v3: Updated error handling
Pin the gem object before use.
I tested a modified version of this on 3.18 kernel on ChromeOS. Does
work fine, but few WARN dumps from might_sleep() in atomic context while
allocating cursor gem bo. I can allocate it one time during plane
creation but how do I know the size of incoming bo ? If I allocate for
say large cursor 256x256, ioremap_wc also has same WARN dumps. Need to
remap in update function. Any hints how to go about it ? Maybe I should
do this hack in check_plane rather than update plane ?
Regards
Shobhit
Signed-off-by: Akshu Agrawal
Signed-off-by: Shobhit Kumar
---
drivers/gpu/drm/i915/i915_drv.h | 7 ++
drivers/gpu/drm/i915/intel_display.c | 131 ++-
2 files changed, 137 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 724d34b..1e59c02 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2041,6 +2041,13 @@ struct drm_i915_private {
struct intel_encoder *dig_port_map[I915_MAX_PORTS];
/*
+ * Temporary copy of cursor plane state for CHV PIPE_C
+ * Will be initialized only when crtc_x < 0 as there is a
+ * HW bug causing pipe underrun
+ */
+ struct intel_plane_state *cursor_state;
+
+ /*
* NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
* will be rejected. Instead look for a better place.
*/
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c3b5dc8..e6c103a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14456,6 +14456,132 @@ intel_update_cursor_plane(struct drm_plane *plane,
intel_crtc_update_cursor(crtc, state);
}
+static void
+intel_update_chv_pipe_c_cursor_plane(struct drm_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *state)
+{
+ struct drm_crtc *crtc = crtc_state->base.crtc;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct drm_device *dev = plane->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
+ struct drm_i915_gem_object *cur_obj = NULL, *use_obj = NULL;
+ uint32_t addr;
+ struct intel_plane_state *cursor_state = dev_priv->cursor_state;
+ const struct intel_plane_state *use_state;
+ char __iomem *src, *dst;
+ bool pinned = true;
+
+ if (state->visible && state->base.crtc_x < 0) {
+ int bytes_per_pixel = state->base.fb->bits_per_pixel / 8;
+ int x = state->base.crtc_x;
+ int width = state->base.crtc_w;
+ int height = state->base.crtc_h;
+ struct drm_mode_fb_cmd2 mode_cmd = { 0 };
+ int i;
+
+ if (!cursor_state) {
+ cursor_state = kzalloc(sizeof(*cursor_state),
GFP_KERNEL);
+ if (!cursor_state) {
+ use_state = state;
+ use_obj = obj;
+ goto update;
+ }
+
+ memcpy(cursor_state, state, sizeof(*state));
+
+ /* Allocate new gem object */
+ cur_obj = i915_gem_object_create(dev, obj->base.size);
+ if (IS_ERR(cur_obj))
+ goto gem_err;
+
+ mode_cmd.width = cursor_state->base.fb->width;
+ mode_cmd.height = cursor_state->base.fb->height;
+ mode_cmd.pitches[0] = cursor_state->base.fb->pitches[0];
+ mode_cmd.pixel_format =
cursor_state->base.fb->pixel_format;
+
+ cursor_state->base.fb = intel_framebuffer_create(dev,
&mode_cmd, cur_obj);
+ if (IS_ERR(cursor_state->base.fb)) {
+
drm_gem_object_unreference_unlocked(&cur_obj->base);
+ goto gem_err;
+ }
+
+ if (i915_gem_obj_ggtt_pin(cur_obj, 0, 0) < 0) {
+
drm_gem_object_unreference_unlocked(&cur_obj->base);
+ pinned = false;
+ goto cleanup;
+ }
+
+ dev_priv->cursor_state = cursor_state;
+ } else
+ cur_obj = intel
[Intel-gfx] ✓ Ro.CI.BAT: success for series starting with [1/2] Revert "drm/i915: Workaround CHV pipe C cursor fail" (rev3)
== Series Details == Series: series starting with [1/2] Revert "drm/i915: Workaround CHV pipe C cursor fail" (rev3) URL : https://patchwork.freedesktop.org/series/8431/ State : success == Summary == Series 8431v3 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/8431/revisions/3/mbox Test drv_module_reload_basic: dmesg-warn -> PASS (ro-byt-n2820) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: dmesg-warn -> SKIP (ro-bdw-i5-5250u) Subgroup suspend-read-crc-pipe-c: dmesg-warn -> SKIP (ro-bdw-i5-5250u) fi-hsw-i7-4770k total:229 pass:194 dwarn:0 dfail:0 fail:2 skip:33 fi-kbl-qkkr total:229 pass:160 dwarn:29 dfail:0 fail:0 skip:40 fi-skl-i5-6260u total:229 pass:202 dwarn:0 dfail:0 fail:2 skip:25 fi-skl-i7-6700k total:229 pass:188 dwarn:0 dfail:0 fail:2 skip:39 fi-snb-i7-2600 total:229 pass:174 dwarn:0 dfail:0 fail:2 skip:53 ro-bdw-i5-5250u total:229 pass:202 dwarn:1 dfail:1 fail:2 skip:23 ro-bdw-i7-5600u total:229 pass:190 dwarn:0 dfail:1 fail:0 skip:38 ro-byt-n2820 total:229 pass:178 dwarn:0 dfail:1 fail:5 skip:45 ro-hsw-i3-4010u total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-hsw-i7-4770r total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-ilk-i7-620lm total:229 pass:155 dwarn:0 dfail:1 fail:3 skip:70 ro-ilk1-i5-650 total:224 pass:155 dwarn:0 dfail:1 fail:3 skip:65 ro-ivb2-i7-3770 total:229 pass:190 dwarn:0 dfail:1 fail:2 skip:36 ro-skl3-i5-6260u total:229 pass:206 dwarn:1 dfail:1 fail:2 skip:19 ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48 ro-bdw-i7-5557U failed to connect after reboot ro-bsw-n3050 failed to connect after reboot ro-ivb-i7-3770 failed to connect after reboot Results at /archive/results/CI_IGT_test/RO_Patchwork_1328/ a90c989 drm-intel-nightly: 2016y-06m-29d-09h-24m-21s UTC integration manifest 9cc39c6 drm/i915/chv: Clip cursor for CHV pipe C HW Cursor pos < 0 3f44ddb Revert "drm/i915: Workaround CHV pipe C cursor fail" ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Brightness and "touchpad dis-/enable" keys not working for Fujitsu e7x6
On Mon, 27 Jun 2016, Jan-Marek Glogowski wrote: > Am 25.06.2016 um 11:15 schrieb Michał Kępień: ...though if you think about it, the whole thing is absolutely hideous: an *ACPI* driver requires cooperation from a *video* driver to notify the operating system about a *key press*. >>> >>> Yeah. On one hand I'm utterly amazed. On the other, I've seen and read >>> about other really bizarre things which go on in the BIOSes of computers >>> over the years, so nothing really surprises me anymore. :-) >> >> Yes, I am a rookie in this field, so perhaps I simply have not seen >> enough weirdness yet to just get over something like this. >> >>> My understanding based on this latest information is that the patch to the >>> i915 driver fixes the brightness control on these laptops and that no >>> changes to fujitsu-laptop are required for this. Is this correct? >> >> This is my understanding as well. > > Yup. AFAIK the patchset registers the active output ports of the graphic > chip within ACPI, and this is checked by the brightness keys EC, so if > the port of the display is disabled, the keys don't work. I take it you refer to series at [1]. Sadly, I haven't had the time to figure out a proper solution to patch 5/5 yet. Maarten, if you have a moment of inspiration, go for it! ;) Anyway, someone somewhere thought it's a great idea to filter out backlight key events at the firmware (possibly AML) level if the flat panel is not active. It's not a decision in in either i915 or ACPI driver. In Linux, the obvious thing to have done is to defer all such policy to userspace. Just provide the mechanism, and the userspace will figure out what to do with the keypress. Seriously, someone could have used that information to change the brightness of the *external* display. But can't have that. . So in the driver we'll just have to tell ACPI what outputs are active. That's what the patches are about. BR, Jani. [1] http://mid.gmane.org/cover.1465810007.git.jani.nik...@intel.com > > So no additional change is needed, as long as it just has to work in X11. > > And I just realized the events are generated on key release, which feels > strange, but since we don't get press and release events, stuff like > auto-repeat for brightness wouldn't work. > >>> As to >>> the touch keys, it sounds like this might be a BIOS thing to - is it? >> >> Are you referring to the "touchpad toggle" key? If you are, I will soon >> post a patch adding support for this key so that Jan-Marek can test it. >> I just need to find some time to actually write it. > > This needs a small patch. But getting the keycode into X11 seems to be > impossible, as X / xev can't handle keycodes > 255 (KEY_TOUCHPAD_TOGGLE). > > I'm currently running evrouter, to call a script on the event, which > dis-/enables the input device using xinput. I would definitely prefer > any HW or kernel driver solution. I couldn't find a way to map the 530 > keycode to something < 255 to suit xev and skip the evrouter. Maybe > Fujitsu will offer a better solution. > > Regards, > > Jan-Marek -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/6] drm/i915/huc: Add HuC fw loading support
On 29/06/16 00:03, Rodrigo Vivi wrote: I don't believe we need to be that extreme here. Daniel asked a cleaner version, but we don't need to block the huc on a full rework of an unified fw loader. Oh, I agree, we should take this "mostly" as-is and then reunify them after. .Dave. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Remove request->reset_counter
Since commit 2ed53a94d8cb ("drm/i915: On GPU reset, set the HWS
breadcrumb to the last seqno") once a hang is completed, the seqno is
advanced past all current requests. With this we know that if we wake up
on waiting for a request, if a hang has occurred and reset completed,
our request will be considered complete (i.e.
i915_gem_request_completed() returns true). Therefore we only need to
worry about the situation where a hang has occurred, but not yet reset,
where we may need to release our struct_mutex. Since we don't need to
detect the competed reset using the global gpu_error->reset_counter
anymore, we do not need to track the reset_counter epoch inside the
request.
Signed-off-by: Chris Wilson
Cc: Arun Siluvery
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_gem.c | 16
2 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index def011811421..485ab1148181 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2368,7 +2368,6 @@ struct drm_i915_gem_request {
/** On Which ring this request was generated */
struct drm_i915_private *i915;
struct intel_engine_cs *engine;
- unsigned reset_counter;
/** GEM sequence number associated with the previous request,
* when the HWS breadcrumb is equal to this the GPU is processing
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 51191b879747..1d9878258103 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1506,12 +1506,13 @@ int __i915_wait_request(struct drm_i915_gem_request
*req,
/* We need to check whether any gpu reset happened in between
* the request being submitted and now. If a reset has occurred,
-* the request is effectively complete (we either are in the
-* process of or have discarded the rendering and completely
-* reset the GPU. The results of the request are lost and we
-* are free to continue on with the original operation.
+* the seqno will have been advance past ours and our request
+* is complete. If we are in the process of handling a reset,
+* the request is effectively complete as the rendering will
+* be discarded, but we need to return in order to drop the
+* struct_mutex.
*/
- if (req->reset_counter !=
i915_reset_counter(&dev_priv->gpu_error)) {
+ if (i915_reset_in_progress(&dev_priv->gpu_error)) {
ret = 0;
break;
}
@@ -1685,7 +1686,7 @@ i915_wait_request(struct drm_i915_gem_request *req)
return ret;
/* If the GPU hung, we want to keep the requests to find the guilty. */
- if (req->reset_counter == i915_reset_counter(&dev_priv->gpu_error))
+ if (!i915_reset_in_progress(&dev_priv->gpu_error))
__i915_gem_request_retire__upto(req);
return 0;
@@ -1746,7 +1747,7 @@ i915_gem_object_retire_request(struct drm_i915_gem_object
*obj,
else if (obj->last_write_req == req)
i915_gem_object_retire__write(obj);
- if (req->reset_counter == i915_reset_counter(&req->i915->gpu_error))
+ if (!i915_reset_in_progress(&req->i915->gpu_error))
__i915_gem_request_retire__upto(req);
}
@@ -3021,7 +3022,6 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
kref_init(&req->ref);
req->i915 = dev_priv;
req->engine = engine;
- req->reset_counter = reset_counter;
req->ctx = ctx;
i915_gem_context_reference(req->ctx);
--
2.8.1
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Re: [Intel-gfx] [PATCH v2 3/5] drm/i915/opregion: handle missing connector types for acpi display types
On Mon, 13 Jun 2016, Jani Nikula wrote:
> Most notably eDP, DSI, and TV. Add MISSING_CASE handling so we won't
> miss this in the future.
>
> Reviewed-and-tested-by: Peter Wu
> Signed-off-by: Jani Nikula
Pushed up to and including this patch to drm-intel-next-queued, as
they're fairly benign changes. Patches 4 and 5 should probably go in
hand-in-hand.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/intel_opregion.c | 13 -
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_opregion.c
> b/drivers/gpu/drm/i915/intel_opregion.c
> index 108cfbf65931..82e687dd09c3 100644
> --- a/drivers/gpu/drm/i915/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/intel_opregion.c
> @@ -676,7 +676,7 @@ static void set_did(struct intel_opregion *opregion, int
> i, u32 val)
>
> static u32 acpi_display_type(struct drm_connector *connector)
> {
> - u32 display_type = ACPI_DISPLAY_TYPE_OTHER;
> + u32 display_type;
>
> switch (connector->connector_type) {
> case DRM_MODE_CONNECTOR_VGA:
> @@ -687,6 +687,7 @@ static u32 acpi_display_type(struct drm_connector
> *connector)
> case DRM_MODE_CONNECTOR_SVIDEO:
> case DRM_MODE_CONNECTOR_Component:
> case DRM_MODE_CONNECTOR_9PinDIN:
> + case DRM_MODE_CONNECTOR_TV:
> display_type = ACPI_DISPLAY_TYPE_TV;
> break;
> case DRM_MODE_CONNECTOR_DVII:
> @@ -697,8 +698,18 @@ static u32 acpi_display_type(struct drm_connector
> *connector)
> display_type = ACPI_DISPLAY_TYPE_EXTERNAL_DIGITAL;
> break;
> case DRM_MODE_CONNECTOR_LVDS:
> + case DRM_MODE_CONNECTOR_eDP:
> + case DRM_MODE_CONNECTOR_DSI:
> display_type = ACPI_DISPLAY_TYPE_INTERNAL_DIGITAL;
> break;
> + case DRM_MODE_CONNECTOR_Unknown:
> + case DRM_MODE_CONNECTOR_VIRTUAL:
> + display_type = ACPI_DISPLAY_TYPE_OTHER;
> + break;
> + default:
> + MISSING_CASE(connector->connector_type);
> + display_type = ACPI_DISPLAY_TYPE_OTHER;
> + break;
> }
>
> return display_type;
--
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [1/2] drm/i915/debug: Select PREEMPT_COUNT when enabling debugging (rev5)
On 29/06/16 12:50, Patchwork wrote: == Series Details == Series: series starting with [1/2] drm/i915/debug: Select PREEMPT_COUNT when enabling debugging (rev5) URL : https://patchwork.freedesktop.org/series/9226/ State : failure == Summary == Series 9226v5 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/9226/revisions/5/mbox Test drv_module_reload_basic: dmesg-warn -> PASS (ro-byt-n2820) Test gem_exec_suspend: Subgroup basic-s3: pass -> INCOMPLETE (fi-hsw-i7-4770k) Sporadic known failure, can't find the BAT. Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: dmesg-warn -> SKIP (ro-bdw-i5-5250u) Subgroup suspend-read-crc-pipe-c: dmesg-warn -> SKIP (ro-bdw-i5-5250u) fi-hsw-i7-4770k total:103 pass:86 dwarn:0 dfail:0 fail:0 skip:16 fi-kbl-qkkr total:229 pass:161 dwarn:29 dfail:0 fail:0 skip:39 fi-skl-i5-6260u total:229 pass:202 dwarn:0 dfail:0 fail:2 skip:25 fi-skl-i7-6700k total:229 pass:188 dwarn:0 dfail:0 fail:2 skip:39 fi-snb-i7-2600 total:229 pass:174 dwarn:0 dfail:0 fail:2 skip:53 ro-bdw-i5-5250u total:229 pass:202 dwarn:1 dfail:1 fail:2 skip:23 ro-bdw-i7-5600u total:229 pass:190 dwarn:0 dfail:1 fail:0 skip:38 ro-bsw-n3050 total:229 pass:177 dwarn:0 dfail:1 fail:2 skip:49 ro-byt-n2820 total:229 pass:178 dwarn:0 dfail:1 fail:5 skip:45 ro-hsw-i3-4010u total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-hsw-i7-4770r total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-ilk-i7-620lm total:229 pass:154 dwarn:0 dfail:1 fail:4 skip:70 ro-ilk1-i5-650 total:224 pass:155 dwarn:0 dfail:1 fail:3 skip:65 ro-ivb-i7-3770 total:229 pass:186 dwarn:0 dfail:1 fail:2 skip:40 ro-ivb2-i7-3770 total:229 pass:190 dwarn:0 dfail:1 fail:2 skip:36 ro-skl3-i5-6260u total:229 pass:206 dwarn:1 dfail:1 fail:2 skip:19 ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48 ro-bdw-i7-5557U failed to connect after reboot Results at /archive/results/CI_IGT_test/RO_Patchwork_1327/ a90c989 drm-intel-nightly: 2016y-06m-29d-09h-24m-21s UTC integration manifest d5eba7b drm/i915: Use atomic waits for short non-atomic ones 41208f4 drm/i915/debug: Select PREEMPT_COUNT when enabling debugging Merged to dinq. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/13] drm/i915: Consolidate get and put irq vfuncs
From: Tvrtko Ursulin
v2: Consistent INTEL_GEN vs IS_GEN usage. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 46 -
1 file changed, 17 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a4391cbbb2b6..8d9e2e24f67d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2884,6 +2884,23 @@ static void intel_ring_default_vfuncs(struct
drm_i915_private *dev_priv,
} else {
engine->add_request = i9xx_add_request;
}
+
+ if (INTEL_GEN(dev_priv) >= 8) {
+ engine->irq_get = gen8_ring_get_irq;
+ engine->irq_put = gen8_ring_put_irq;
+ } else if (INTEL_GEN(dev_priv) >= 6) {
+ engine->irq_get = gen6_ring_get_irq;
+ engine->irq_put = gen6_ring_put_irq;
+ } else if (INTEL_GEN(dev_priv) >= 5) {
+ engine->irq_get = gen5_ring_get_irq;
+ engine->irq_put = gen5_ring_put_irq;
+ } else if (INTEL_GEN(dev_priv) >= 3) {
+ engine->irq_get = i9xx_ring_get_irq;
+ engine->irq_put = i9xx_ring_put_irq;
+ } else {
+ engine->irq_get = i8xx_ring_get_irq;
+ engine->irq_put = i8xx_ring_put_irq;
+ }
}
int intel_init_render_ring_buffer(struct drm_device *dev)
@@ -2922,8 +2939,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->init_context = intel_rcs_ctx_init;
engine->add_request = gen8_render_add_request;
engine->flush = gen8_render_ring_flush;
- engine->irq_get = gen8_ring_get_irq;
- engine->irq_put = gen8_ring_put_irq;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
@@ -2938,8 +2953,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->flush = gen7_render_ring_flush;
if (IS_GEN6(dev_priv))
engine->flush = gen6_render_ring_flush;
- engine->irq_get = gen6_ring_get_irq;
- engine->irq_put = gen6_ring_put_irq;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
@@ -2969,8 +2982,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->flush = gen4_render_ring_flush;
engine->get_seqno = pc_render_get_seqno;
engine->set_seqno = pc_render_set_seqno;
- engine->irq_get = gen5_ring_get_irq;
- engine->irq_put = gen5_ring_put_irq;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
} else {
@@ -2980,13 +2991,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->flush = gen4_render_ring_flush;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
- if (IS_GEN2(dev_priv)) {
- engine->irq_get = i8xx_ring_get_irq;
- engine->irq_put = i8xx_ring_put_irq;
- } else {
- engine->irq_get = i9xx_ring_get_irq;
- engine->irq_put = i9xx_ring_put_irq;
- }
engine->irq_enable_mask = I915_USER_INTERRUPT;
}
@@ -3060,8 +3064,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
if (INTEL_GEN(dev_priv) >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
- engine->irq_get = gen8_ring_get_irq;
- engine->irq_put = gen8_ring_put_irq;
engine->dispatch_execbuffer =
gen8_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
@@ -3071,8 +3073,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
}
} else {
engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
- engine->irq_get = gen6_ring_get_irq;
- engine->irq_put = gen6_ring_put_irq;
engine->dispatch_execbuffer =
gen6_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
@@ -3097,12 +3097,8 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
engine->set_seqno = ring_set_seqno;
if (IS_GEN5(dev_priv)) {
engine->irq_enable_mask =
[Intel-gfx] [PATCH 08/13] drm/i915: Consolidate semaphore vfuncs init
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 48 +
1 file changed, 18 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a961b095680b..d0401bb800a6 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2873,6 +2873,22 @@ static int gen6_ring_flush(struct drm_i915_gem_request
*req,
return 0;
}
+static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
+ struct intel_engine_cs *engine)
+{
+ if (!i915_semaphore_is_enabled(dev_priv))
+ return;
+
+ if (INTEL_GEN(dev_priv) >= 8) {
+ engine->semaphore.sync_to = gen8_ring_sync;
+ engine->semaphore.signal = gen8_xcs_signal;
+ GEN8_RING_SEMAPHORE_INIT(engine);
+ } else if (INTEL_GEN(dev_priv) >= 6) {
+ engine->semaphore.sync_to = gen6_ring_sync;
+ engine->semaphore.signal = gen6_signal;
+ }
+}
+
static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
struct intel_engine_cs *engine)
{
@@ -2908,6 +2924,8 @@ static void intel_ring_default_vfuncs(struct
drm_i915_private *dev_priv,
engine->irq_get = i8xx_ring_get_irq;
engine->irq_put = i8xx_ring_put_irq;
}
+
+ intel_ring_init_semaphores(dev_priv, engine);
}
int intel_init_render_ring_buffer(struct drm_device *dev)
@@ -2949,9 +2967,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
if (i915_semaphore_is_enabled(dev_priv)) {
WARN_ON(!dev_priv->semaphore_obj);
- engine->semaphore.sync_to = gen8_ring_sync;
engine->semaphore.signal = gen8_rcs_signal;
- GEN8_RING_SEMAPHORE_INIT(engine);
}
} else if (INTEL_GEN(dev_priv) >= 6) {
engine->init_context = intel_rcs_ctx_init;
@@ -2960,8 +2976,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->flush = gen6_render_ring_flush;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
if (i915_semaphore_is_enabled(dev_priv)) {
- engine->semaphore.sync_to = gen6_ring_sync;
- engine->semaphore.signal = gen6_signal;
/*
* The current semaphore is only applied on pre-gen8
* platform. And there is no VCS2 ring on the pre-gen8
@@ -3057,16 +3071,9 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
if (INTEL_GEN(dev_priv) >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
- if (i915_semaphore_is_enabled(dev_priv)) {
- engine->semaphore.sync_to = gen8_ring_sync;
- engine->semaphore.signal = gen8_xcs_signal;
- GEN8_RING_SEMAPHORE_INIT(engine);
- }
} else {
engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
if (i915_semaphore_is_enabled(dev_priv)) {
- engine->semaphore.sync_to = gen6_ring_sync;
- engine->semaphore.signal = gen6_signal;
engine->semaphore.mbox.wait[RCS] =
MI_SEMAPHORE_SYNC_VR;
engine->semaphore.mbox.wait[VCS] =
MI_SEMAPHORE_SYNC_INVALID;
engine->semaphore.mbox.wait[BCS] =
MI_SEMAPHORE_SYNC_VB;
@@ -3111,11 +3118,6 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
engine->flush = gen6_bsd_ring_flush;
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
- if (i915_semaphore_is_enabled(dev_priv)) {
- engine->semaphore.sync_to = gen8_ring_sync;
- engine->semaphore.signal = gen8_xcs_signal;
- GEN8_RING_SEMAPHORE_INIT(engine);
- }
return intel_init_ring_buffer(dev, engine);
}
@@ -3137,16 +3139,9 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
if (INTEL_GEN(dev_priv) >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
- if (i915_semaphore_is_enabled(dev_priv)) {
- engine->semaphore.sync_to = gen8_ring_sync;
- engine->semaphore.signal = gen8_xcs_signal;
- GEN8_RING_SEMAPHORE_INIT(engine);
- }
} else {
[Intel-gfx] [PATCH 06/13] drm/i915: Consolidate init_hw vfunc
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e0e90b99bbca..dcacf17c525f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2876,6 +2876,7 @@ static int gen6_ring_flush(struct drm_i915_gem_request
*req,
static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
struct intel_engine_cs *engine)
{
+ engine->init_hw = init_ring_common;
engine->write_tail = ring_write_tail;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
@@ -3094,7 +3095,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
}
engine->dispatch_execbuffer = i965_dispatch_execbuffer;
}
- engine->init_hw = init_ring_common;
return intel_init_ring_buffer(dev, engine);
}
@@ -3125,7 +3125,6 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
engine->semaphore.signal = gen8_xcs_signal;
GEN8_RING_SEMAPHORE_INIT(engine);
}
- engine->init_hw = init_ring_common;
return intel_init_ring_buffer(dev, engine);
}
@@ -3178,7 +3177,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
}
}
- engine->init_hw = init_ring_common;
return intel_init_ring_buffer(dev, engine);
}
@@ -3227,7 +3225,6 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
}
}
- engine->init_hw = init_ring_common;
return intel_init_ring_buffer(dev, engine);
}
--
1.9.1
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[Intel-gfx] [PATCH 07/13] drm/i915: Consolidate dispatch_execbuffer vfunc
From: Tvrtko Ursulin
v2: Put dispatch_execbuffer before add_request. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 25 ++---
1 file changed, 6 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index dcacf17c525f..a961b095680b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2881,10 +2881,14 @@ static void intel_ring_default_vfuncs(struct
drm_i915_private *dev_priv,
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
- if (INTEL_GEN(dev_priv) >= 6) {
+ if (INTEL_GEN(dev_priv) >= 8) {
+ engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
+ } else if (INTEL_GEN(dev_priv) >= 6) {
+ engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
engine->add_request = gen6_add_request;
engine->irq_seqno_barrier = gen6_seqno_barrier;
} else {
+ engine->dispatch_execbuffer = i965_dispatch_execbuffer;
engine->add_request = i9xx_add_request;
}
@@ -2993,15 +2997,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
if (IS_HASWELL(dev_priv))
engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
- else if (IS_GEN8(dev_priv))
- engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
- else if (INTEL_GEN(dev_priv) >= 6)
- engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
- else if (INTEL_GEN(dev_priv) >= 4)
- engine->dispatch_execbuffer = i965_dispatch_execbuffer;
else if (IS_I830(dev_priv) || IS_845G(dev_priv))
engine->dispatch_execbuffer = i830_dispatch_execbuffer;
- else
+ else if (INTEL_GEN(dev_priv) <= 3)
engine->dispatch_execbuffer = i915_dispatch_execbuffer;
engine->init_hw = init_render_ring;
engine->cleanup = render_ring_cleanup;
@@ -3059,8 +3057,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
if (INTEL_GEN(dev_priv) >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
- engine->dispatch_execbuffer =
- gen8_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen8_ring_sync;
engine->semaphore.signal = gen8_xcs_signal;
@@ -3068,8 +3064,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
}
} else {
engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
- engine->dispatch_execbuffer =
- gen6_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen6_ring_sync;
engine->semaphore.signal = gen6_signal;
@@ -3093,7 +3087,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
} else {
engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
}
- engine->dispatch_execbuffer = i965_dispatch_execbuffer;
}
return intel_init_ring_buffer(dev, engine);
@@ -3118,8 +3111,6 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
engine->flush = gen6_bsd_ring_flush;
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
- engine->dispatch_execbuffer =
- gen8_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen8_ring_sync;
engine->semaphore.signal = gen8_xcs_signal;
@@ -3146,7 +3137,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
if (INTEL_GEN(dev_priv) >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
- engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen8_ring_sync;
engine->semaphore.signal = gen8_xcs_signal;
@@ -3154,7 +3144,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
}
} else {
engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
- engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.signal = gen6_signal;
engine->se
[Intel-gfx] [PATCH 10/13] drm/i915: Compact Gen8 semaphore initialization
From: Tvrtko Ursulin
Replace the macro initializer with a programatic loop which
results in smaller code and hopefully just as clear.
v2: Rebase.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 16 ++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 12
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 77d663fcdff1..14218d893d7b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2877,7 +2877,7 @@ static void intel_ring_init_semaphores(struct
drm_i915_private *dev_priv,
struct intel_engine_cs *engine)
{
struct drm_i915_gem_object *obj;
- int ret;
+ int ret, i;
if (!i915_semaphore_is_enabled(dev_priv))
return;
@@ -2904,9 +2904,21 @@ static void intel_ring_init_semaphores(struct
drm_i915_private *dev_priv,
return;
if (INTEL_GEN(dev_priv) >= 8) {
+ u64 offset = i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj);
+
engine->semaphore.sync_to = gen8_ring_sync;
engine->semaphore.signal = gen8_xcs_signal;
- GEN8_RING_SEMAPHORE_INIT(engine);
+
+ for (i = 0; i < I915_NUM_ENGINES; i++) {
+ u64 ring_offset;
+
+ if (i != engine->id)
+ ring_offset = offset +
GEN8_SEMAPHORE_OFFSET(engine->id, i);
+ else
+ ring_offset = MI_SEMAPHORE_SYNC_INVALID;
+
+ engine->semaphore.signal_ggtt[i] = ring_offset;
+ }
} else if (INTEL_GEN(dev_priv) >= 6) {
engine->semaphore.sync_to = gen6_ring_sync;
engine->semaphore.signal = gen6_signal;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index b33c876fed20..113d5230a6de 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -62,18 +62,6 @@ struct intel_hw_status_page {
(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
GEN8_SEMAPHORE_OFFSET(from, (__ring)->id))
-#define GEN8_RING_SEMAPHORE_INIT(e) do { \
- if (!dev_priv->semaphore_obj) { \
- break; \
- } \
- (e)->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET((e), RCS); \
- (e)->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET((e), VCS); \
- (e)->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET((e), BCS); \
- (e)->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET((e), VECS); \
- (e)->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET((e), VCS2); \
- (e)->semaphore.signal_ggtt[(e)->id] = MI_SEMAPHORE_SYNC_INVALID; \
- } while(0)
-
enum intel_ring_hangcheck_action {
HANGCHECK_IDLE = 0,
HANGCHECK_WAIT,
--
1.9.1
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Re: [Intel-gfx] [PATCH] drm/i915: Remove request->reset_counter
On 29/06/2016 15:51, Chris Wilson wrote:
Since commit 2ed53a94d8cb ("drm/i915: On GPU reset, set the HWS
breadcrumb to the last seqno") once a hang is completed, the seqno is
advanced past all current requests. With this we know that if we wake up
on waiting for a request, if a hang has occurred and reset completed,
our request will be considered complete (i.e.
i915_gem_request_completed() returns true). Therefore we only need to
worry about the situation where a hang has occurred, but not yet reset,
where we may need to release our struct_mutex. Since we don't need to
detect the competed reset using the global gpu_error->reset_counter
s/competed/completed
anymore, we do not need to track the reset_counter epoch inside the
request.
Signed-off-by: Chris Wilson
Cc: Arun Siluvery
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_gem.c | 16
2 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index def011811421..485ab1148181 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2368,7 +2368,6 @@ struct drm_i915_gem_request {
/** On Which ring this request was generated */
struct drm_i915_private *i915;
struct intel_engine_cs *engine;
- unsigned reset_counter;
/** GEM sequence number associated with the previous request,
* when the HWS breadcrumb is equal to this the GPU is processing
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 51191b879747..1d9878258103 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1506,12 +1506,13 @@ int __i915_wait_request(struct drm_i915_gem_request
*req,
/* We need to check whether any gpu reset happened in between
* the request being submitted and now. If a reset has occurred,
-* the request is effectively complete (we either are in the
-* process of or have discarded the rendering and completely
-* reset the GPU. The results of the request are lost and we
-* are free to continue on with the original operation.
+* the seqno will have been advance past ours and our request
+* is complete. If we are in the process of handling a reset,
+* the request is effectively complete as the rendering will
+* be discarded, but we need to return in order to drop the
+* struct_mutex.
*/
- if (req->reset_counter !=
i915_reset_counter(&dev_priv->gpu_error)) {
+ if (i915_reset_in_progress(&dev_priv->gpu_error)) {
ret = 0;
break;
}
@@ -1685,7 +1686,7 @@ i915_wait_request(struct drm_i915_gem_request *req)
return ret;
/* If the GPU hung, we want to keep the requests to find the guilty. */
- if (req->reset_counter == i915_reset_counter(&dev_priv->gpu_error))
+ if (!i915_reset_in_progress(&dev_priv->gpu_error))
__i915_gem_request_retire__upto(req);
return 0;
@@ -1746,7 +1747,7 @@ i915_gem_object_retire_request(struct drm_i915_gem_object
*obj,
else if (obj->last_write_req == req)
i915_gem_object_retire__write(obj);
- if (req->reset_counter == i915_reset_counter(&req->i915->gpu_error))
+ if (!i915_reset_in_progress(&req->i915->gpu_error))
__i915_gem_request_retire__upto(req);
}
@@ -3021,7 +3022,6 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
kref_init(&req->ref);
req->i915 = dev_priv;
req->engine = engine;
- req->reset_counter = reset_counter;
req->ctx = ctx;
i915_gem_context_reference(req->ctx);
this looks good to me,
Reviewed-by: Arun Siluvery
regards
Arun
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[Intel-gfx] [PATCH 02/13] drm/i915: Consolidate add_request vfunc
From: Tvrtko Ursulin
All engines apart from render select this based on Gen.
Move it to the common helper as well.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b715707947d8..d82eb12ed6b6 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2877,6 +2877,11 @@ static void intel_ring_default_vfuncs(struct
drm_i915_private *dev_priv,
struct intel_engine_cs *engine)
{
engine->write_tail = ring_write_tail;
+
+ if (INTEL_GEN(dev_priv) >= 6)
+ engine->add_request = gen6_add_request;
+ else
+ engine->add_request = i9xx_add_request;
}
int intel_init_render_ring_buffer(struct drm_device *dev)
@@ -2928,7 +2933,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
}
} else if (INTEL_GEN(dev_priv) >= 6) {
engine->init_context = intel_rcs_ctx_init;
- engine->add_request = gen6_add_request;
engine->flush = gen7_render_ring_flush;
if (IS_GEN6(dev_priv))
engine->flush = gen6_render_ring_flush;
@@ -2969,7 +2973,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
} else {
- engine->add_request = i9xx_add_request;
if (INTEL_GEN(dev_priv) < 4)
engine->flush = gen2_render_ring_flush;
else
@@ -3051,7 +3054,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
if (IS_GEN6(dev_priv))
engine->write_tail = gen6_bsd_ring_write_tail;
engine->flush = gen6_bsd_ring_flush;
- engine->add_request = gen6_add_request;
engine->irq_seqno_barrier = gen6_seqno_barrier;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
@@ -3091,7 +3093,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
} else {
engine->mmio_base = BSD_RING_BASE;
engine->flush = bsd_ring_flush;
- engine->add_request = i9xx_add_request;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
if (IS_GEN5(dev_priv)) {
@@ -3127,7 +3128,6 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
intel_ring_default_vfuncs(dev_priv, engine);
engine->flush = gen6_bsd_ring_flush;
- engine->add_request = gen6_add_request;
engine->irq_seqno_barrier = gen6_seqno_barrier;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
@@ -3161,7 +3161,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
intel_ring_default_vfuncs(dev_priv, engine);
engine->flush = gen6_ring_flush;
- engine->add_request = gen6_add_request;
engine->irq_seqno_barrier = gen6_seqno_barrier;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
@@ -3222,7 +3221,6 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
intel_ring_default_vfuncs(dev_priv, engine);
engine->flush = gen6_ring_flush;
- engine->add_request = gen6_add_request;
engine->irq_seqno_barrier = gen6_seqno_barrier;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
--
1.9.1
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[Intel-gfx] [PATCH 11/13] drm/i915: Compact gen8_ring_sync
From: Tvrtko Ursulin
Store the semaphore offset in a temporary variable to avoid
having to get the VMA offset twice.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 14218d893d7b..648ddee60c24 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1542,6 +1542,7 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
{
struct intel_engine_cs *waiter = waiter_req->engine;
struct drm_i915_private *dev_priv = waiter_req->i915;
+ u64 offset = GEN8_WAIT_OFFSET(waiter, signaller->id);
struct i915_hw_ppgtt *ppgtt;
int ret;
@@ -1553,10 +1554,8 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
MI_SEMAPHORE_GLOBAL_GTT |
MI_SEMAPHORE_SAD_GTE_SDD);
intel_ring_emit(waiter, seqno);
- intel_ring_emit(waiter,
- lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
- intel_ring_emit(waiter,
- upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
+ intel_ring_emit(waiter, lower_32_bits(offset));
+ intel_ring_emit(waiter, upper_32_bits(offset));
intel_ring_advance(waiter);
/* When the !RCS engines idle waiting upon a semaphore, they lose their
--
1.9.1
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[Intel-gfx] [PATCH 03/13] drm/i915: Consolidate seqno_barrier vfunc
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d82eb12ed6b6..a4391cbbb2b6 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2878,10 +2878,12 @@ static void intel_ring_default_vfuncs(struct
drm_i915_private *dev_priv,
{
engine->write_tail = ring_write_tail;
- if (INTEL_GEN(dev_priv) >= 6)
+ if (INTEL_GEN(dev_priv) >= 6) {
engine->add_request = gen6_add_request;
- else
+ engine->irq_seqno_barrier = gen6_seqno_barrier;
+ } else {
engine->add_request = i9xx_add_request;
+ }
}
int intel_init_render_ring_buffer(struct drm_device *dev)
@@ -2939,7 +2941,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->irq_get = gen6_ring_get_irq;
engine->irq_put = gen6_ring_put_irq;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
- engine->irq_seqno_barrier = gen6_seqno_barrier;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
if (i915_semaphore_is_enabled(dev_priv)) {
@@ -3054,7 +3055,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
if (IS_GEN6(dev_priv))
engine->write_tail = gen6_bsd_ring_write_tail;
engine->flush = gen6_bsd_ring_flush;
- engine->irq_seqno_barrier = gen6_seqno_barrier;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
if (INTEL_GEN(dev_priv) >= 8) {
@@ -3128,7 +3128,6 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
intel_ring_default_vfuncs(dev_priv, engine);
engine->flush = gen6_bsd_ring_flush;
- engine->irq_seqno_barrier = gen6_seqno_barrier;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
engine->irq_enable_mask =
@@ -3161,7 +3160,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
intel_ring_default_vfuncs(dev_priv, engine);
engine->flush = gen6_ring_flush;
- engine->irq_seqno_barrier = gen6_seqno_barrier;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
if (INTEL_GEN(dev_priv) >= 8) {
@@ -3221,7 +3219,6 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
intel_ring_default_vfuncs(dev_priv, engine);
engine->flush = gen6_ring_flush;
- engine->irq_seqno_barrier = gen6_seqno_barrier;
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
--
1.9.1
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[Intel-gfx] [PATCH 12/13] drm/i915: Consolidate legacy semaphore initialization
From: Tvrtko Ursulin
Replace per-engine initialization with a common half-programatic,
half-data driven code for ease of maintenance and compactness.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 110 ++--
1 file changed, 48 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 648ddee60c24..7bbc59eef267 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2921,6 +2921,54 @@ static void intel_ring_init_semaphores(struct
drm_i915_private *dev_priv,
} else if (INTEL_GEN(dev_priv) >= 6) {
engine->semaphore.sync_to = gen6_ring_sync;
engine->semaphore.signal = gen6_signal;
+
+ /*
+* The current semaphore is only applied on pre-gen8
+* platform. And there is no VCS2 ring on the pre-gen8
+* platform. So the semaphore between RCS and VCS2 is
+* initialized as INVALID. Gen8 will initialize the
+* sema between VCS2 and RCS later.
+*/
+ for (i = 0; i < I915_NUM_ENGINES; i++) {
+ static const struct {
+ u32 wait_mbox;
+ i915_reg_t mbox_reg;
+ } sem_data[I915_NUM_ENGINES][I915_NUM_ENGINES] = {
+ [RCS] = {
+ [VCS] = { .wait_mbox =
MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC },
+ [BCS] = { .wait_mbox =
MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC },
+ [VECS] = { .wait_mbox =
MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC },
+ },
+ [VCS] = {
+ [RCS] = { .wait_mbox =
MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC },
+ [BCS] = { .wait_mbox =
MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC },
+ [VECS] = { .wait_mbox =
MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC },
+ },
+ [BCS] = {
+ [RCS] = { .wait_mbox =
MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC },
+ [VCS] = { .wait_mbox =
MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC },
+ [VECS] = { .wait_mbox =
MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC },
+ },
+ [VECS] = {
+ [RCS] = { .wait_mbox =
MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC },
+ [VCS] = { .wait_mbox =
MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC },
+ [BCS] = { .wait_mbox =
MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC },
+ },
+ };
+ u32 wait_mbox;
+ i915_reg_t mbox_reg;
+
+ if (i == engine->id || i == VCS2) {
+ wait_mbox = MI_SEMAPHORE_SYNC_INVALID;
+ mbox_reg = GEN6_NOSYNC;
+ } else {
+ wait_mbox = sem_data[engine->id][i].wait_mbox;
+ mbox_reg = sem_data[engine->id][i].mbox_reg;
+ }
+
+ engine->semaphore.mbox.wait[i] = wait_mbox;
+ engine->semaphore.mbox.signal[i] = mbox_reg;
+ }
}
}
@@ -2991,25 +3039,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
if (IS_GEN6(dev_priv))
engine->flush = gen6_render_ring_flush;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
- if (i915_semaphore_is_enabled(dev_priv)) {
- /*
-* The current semaphore is only applied on pre-gen8
-* platform. And there is no VCS2 ring on the pre-gen8
-* platform. So the semaphore between RCS and VCS2 is
-* initialized as INVALID. Gen8 will initialize the
-* sema between VCS2 and RCS later.
-*/
- engine->semaphore.mbox.wait[RCS] =
MI_SEMAPHORE_SYNC_INVALID;
- engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
- engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
- engine->semaphore.mbox.wait[VECS] =
MI_SEMAPHORE_SYNC_RVE;
- engine->semaphore.mbox.wait[VCS2] =
MI_SEMAPHORE_SYNC_INVALID
[Intel-gfx] [PATCH 01/13] drm/i915: Consolidate write_tail vfunc initializer
From: Tvrtko Ursulin
Introduce a function which initializes vfuncs mostly common
across engines and move write_tail initialization in it since
only one engine overrides the default.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 27 +++
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 04a2d141e690..b715707947d8 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2873,6 +2873,12 @@ static int gen6_ring_flush(struct drm_i915_gem_request
*req,
return 0;
}
+static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
+ struct intel_engine_cs *engine)
+{
+ engine->write_tail = ring_write_tail;
+}
+
int intel_init_render_ring_buffer(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2886,6 +2892,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->hw_id = 0;
engine->mmio_base = RENDER_RING_BASE;
+ intel_ring_default_vfuncs(dev_priv, engine);
+
if (INTEL_GEN(dev_priv) >= 8) {
if (i915_semaphore_is_enabled(dev_priv)) {
obj = i915_gem_object_create(dev, 4096);
@@ -2977,7 +2985,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
}
engine->irq_enable_mask = I915_USER_INTERRUPT;
}
- engine->write_tail = ring_write_tail;
if (IS_HASWELL(dev_priv))
engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
@@ -3036,7 +3043,8 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
engine->exec_id = I915_EXEC_BSD;
engine->hw_id = 1;
- engine->write_tail = ring_write_tail;
+ intel_ring_default_vfuncs(dev_priv, engine);
+
if (INTEL_GEN(dev_priv) >= 6) {
engine->mmio_base = GEN6_BSD_RING_BASE;
/* gen6 bsd needs a special wa for tail updates */
@@ -3114,9 +3122,10 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
engine->id = VCS2;
engine->exec_id = I915_EXEC_BSD;
engine->hw_id = 4;
-
- engine->write_tail = ring_write_tail;
engine->mmio_base = GEN8_BSD2_RING_BASE;
+
+ intel_ring_default_vfuncs(dev_priv, engine);
+
engine->flush = gen6_bsd_ring_flush;
engine->add_request = gen6_add_request;
engine->irq_seqno_barrier = gen6_seqno_barrier;
@@ -3147,9 +3156,10 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
engine->id = BCS;
engine->exec_id = I915_EXEC_BLT;
engine->hw_id = 2;
-
engine->mmio_base = BLT_RING_BASE;
- engine->write_tail = ring_write_tail;
+
+ intel_ring_default_vfuncs(dev_priv, engine);
+
engine->flush = gen6_ring_flush;
engine->add_request = gen6_add_request;
engine->irq_seqno_barrier = gen6_seqno_barrier;
@@ -3207,9 +3217,10 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
engine->id = VECS;
engine->exec_id = I915_EXEC_VEBOX;
engine->hw_id = 3;
-
engine->mmio_base = VEBOX_RING_BASE;
- engine->write_tail = ring_write_tail;
+
+ intel_ring_default_vfuncs(dev_priv, engine);
+
engine->flush = gen6_ring_flush;
engine->add_request = gen6_add_request;
engine->irq_seqno_barrier = gen6_seqno_barrier;
--
1.9.1
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[Intel-gfx] [PATCH 13/13] drm/i915: Trim some if-else braces
From: Tvrtko Ursulin
Just a bit of cleanup after the previous refactoring.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 7bbc59eef267..0df7a13c0992 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -3113,20 +3113,18 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
if (IS_GEN6(dev_priv))
engine->write_tail = gen6_bsd_ring_write_tail;
engine->flush = gen6_bsd_ring_flush;
- if (INTEL_GEN(dev_priv) >= 8) {
+ if (INTEL_GEN(dev_priv) >= 8)
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
- } else {
+ else
engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
- }
} else {
engine->mmio_base = BSD_RING_BASE;
engine->flush = bsd_ring_flush;
- if (IS_GEN5(dev_priv)) {
+ if (IS_GEN5(dev_priv))
engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
- } else {
+ else
engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
- }
}
return intel_init_ring_buffer(dev, engine);
@@ -3169,12 +3167,11 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
intel_ring_default_vfuncs(dev_priv, engine);
engine->flush = gen6_ring_flush;
- if (INTEL_GEN(dev_priv) >= 8) {
+ if (INTEL_GEN(dev_priv) >= 8)
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
- } else {
+ else
engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
- }
return intel_init_ring_buffer(dev, engine);
}
--
1.9.1
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[Intel-gfx] [PATCH 09/13] drm/i915: Move semaphore object creation into intel_ring_init_semaphores
From: Tvrtko Ursulin
The object needs to be created before semaphores can be initialized
on any ring and it makes sense to pull it out to this semaphore
dedicated helper.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 45 ++---
1 file changed, 25 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d0401bb800a6..77d663fcdff1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2876,6 +2876,30 @@ static int gen6_ring_flush(struct drm_i915_gem_request
*req,
static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
struct intel_engine_cs *engine)
{
+ struct drm_i915_gem_object *obj;
+ int ret;
+
+ if (!i915_semaphore_is_enabled(dev_priv))
+ return;
+
+ if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore_obj) {
+ obj = i915_gem_object_create(dev_priv->dev, 4096);
+ if (IS_ERR(obj)) {
+ DRM_ERROR("Failed to allocate semaphore bo. Disabling
semaphores\n");
+ i915.semaphores = 0;
+ } else {
+ i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
+ ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
+ if (ret != 0) {
+ drm_gem_object_unreference(&obj->base);
+ DRM_ERROR("Failed to pin semaphore bo.
Disabling semaphores\n");
+ i915.semaphores = 0;
+ } else {
+ dev_priv->semaphore_obj = obj;
+ }
+ }
+ }
+
if (!i915_semaphore_is_enabled(dev_priv))
return;
@@ -2944,31 +2968,12 @@ int intel_init_render_ring_buffer(struct drm_device
*dev)
intel_ring_default_vfuncs(dev_priv, engine);
if (INTEL_GEN(dev_priv) >= 8) {
- if (i915_semaphore_is_enabled(dev_priv)) {
- obj = i915_gem_object_create(dev, 4096);
- if (IS_ERR(obj)) {
- DRM_ERROR("Failed to allocate semaphore bo.
Disabling semaphores\n");
- i915.semaphores = 0;
- } else {
- i915_gem_object_set_cache_level(obj,
I915_CACHE_LLC);
- ret = i915_gem_obj_ggtt_pin(obj, 0,
PIN_NONBLOCK);
- if (ret != 0) {
- drm_gem_object_unreference(&obj->base);
- DRM_ERROR("Failed to pin semaphore bo.
Disabling semaphores\n");
- i915.semaphores = 0;
- } else
- dev_priv->semaphore_obj = obj;
- }
- }
-
engine->init_context = intel_rcs_ctx_init;
engine->add_request = gen8_render_add_request;
engine->flush = gen8_render_ring_flush;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
- if (i915_semaphore_is_enabled(dev_priv)) {
- WARN_ON(!dev_priv->semaphore_obj);
+ if (i915_semaphore_is_enabled(dev_priv))
engine->semaphore.signal = gen8_rcs_signal;
- }
} else if (INTEL_GEN(dev_priv) >= 6) {
engine->init_context = intel_rcs_ctx_init;
engine->flush = gen7_render_ring_flush;
--
1.9.1
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[Intel-gfx] [PATCH 05/13] drm/i915: Consolidate get/set_seqno
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 18 ++
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8d9e2e24f67d..e0e90b99bbca 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2877,6 +2877,8 @@ static void intel_ring_default_vfuncs(struct
drm_i915_private *dev_priv,
struct intel_engine_cs *engine)
{
engine->write_tail = ring_write_tail;
+ engine->get_seqno = ring_get_seqno;
+ engine->set_seqno = ring_set_seqno;
if (INTEL_GEN(dev_priv) >= 6) {
engine->add_request = gen6_add_request;
@@ -2940,8 +2942,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->add_request = gen8_render_add_request;
engine->flush = gen8_render_ring_flush;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
- engine->get_seqno = ring_get_seqno;
- engine->set_seqno = ring_set_seqno;
if (i915_semaphore_is_enabled(dev_priv)) {
WARN_ON(!dev_priv->semaphore_obj);
engine->semaphore.sync_to = gen8_ring_sync;
@@ -2954,8 +2954,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
if (IS_GEN6(dev_priv))
engine->flush = gen6_render_ring_flush;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
- engine->get_seqno = ring_get_seqno;
- engine->set_seqno = ring_set_seqno;
if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen6_ring_sync;
engine->semaphore.signal = gen6_signal;
@@ -2989,8 +2987,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
engine->flush = gen2_render_ring_flush;
else
engine->flush = gen4_render_ring_flush;
- engine->get_seqno = ring_get_seqno;
- engine->set_seqno = ring_set_seqno;
engine->irq_enable_mask = I915_USER_INTERRUPT;
}
@@ -3059,8 +3055,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
if (IS_GEN6(dev_priv))
engine->write_tail = gen6_bsd_ring_write_tail;
engine->flush = gen6_bsd_ring_flush;
- engine->get_seqno = ring_get_seqno;
- engine->set_seqno = ring_set_seqno;
if (INTEL_GEN(dev_priv) >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
@@ -3093,8 +3087,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
} else {
engine->mmio_base = BSD_RING_BASE;
engine->flush = bsd_ring_flush;
- engine->get_seqno = ring_get_seqno;
- engine->set_seqno = ring_set_seqno;
if (IS_GEN5(dev_priv)) {
engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
} else {
@@ -3124,8 +3116,6 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
intel_ring_default_vfuncs(dev_priv, engine);
engine->flush = gen6_bsd_ring_flush;
- engine->get_seqno = ring_get_seqno;
- engine->set_seqno = ring_set_seqno;
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
engine->dispatch_execbuffer =
@@ -3154,8 +3144,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
intel_ring_default_vfuncs(dev_priv, engine);
engine->flush = gen6_ring_flush;
- engine->get_seqno = ring_get_seqno;
- engine->set_seqno = ring_set_seqno;
if (INTEL_GEN(dev_priv) >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
@@ -3209,8 +3197,6 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
intel_ring_default_vfuncs(dev_priv, engine);
engine->flush = gen6_ring_flush;
- engine->get_seqno = ring_get_seqno;
- engine->set_seqno = ring_set_seqno;
if (INTEL_GEN(dev_priv) >= 8) {
engine->irq_enable_mask =
--
1.9.1
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Re: [Intel-gfx] [PATCH 09/13] drm/i915: Move semaphore object creation into intel_ring_init_semaphores
On Wed, Jun 29, 2016 at 04:09:28PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> The object needs to be created before semaphores can be initialized
> on any ring and it makes sense to pull it out to this semaphore
> dedicated helper.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 45
> ++---
> 1 file changed, 25 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index d0401bb800a6..77d663fcdff1 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2876,6 +2876,30 @@ static int gen6_ring_flush(struct drm_i915_gem_request
> *req,
> static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
> struct intel_engine_cs *engine)
> {
> + struct drm_i915_gem_object *obj;
> + int ret;
> +
> + if (!i915_semaphore_is_enabled(dev_priv))
> + return;
> +
> + if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore_obj) {
struct drm_i915_gem_object *obj;
Probably best to scope this object locally since we don't carry it
forward into the next loop.
Reviewed-by: Chris Wilson
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH 10/13] drm/i915: Compact Gen8 semaphore initialization
On Wed, Jun 29, 2016 at 04:09:29PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > Replace the macro initializer with a programatic loop which > results in smaller code and hopefully just as clear. > > v2: Rebase. > > Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson We could just trivially compute these in the semaphore vfuncs! -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 11/13] drm/i915: Compact gen8_ring_sync
On Wed, Jun 29, 2016 at 04:09:30PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > Store the semaphore offset in a temporary variable to avoid > having to get the VMA offset twice. > > Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson The lookup will be gone very soon, and interesting, the offset can only be 32bits (since we know this code will not run on any future gen that may have more than 4GiB GGTT). -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 12/13] drm/i915: Consolidate legacy semaphore initialization
On Wed, Jun 29, 2016 at 04:09:31PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > Replace per-engine initialization with a common half-programatic, > half-data driven code for ease of maintenance and compactness. > > Signed-off-by: Tvrtko Ursulin This is the biggest pill to swallow (since our 5x5 table is only sparsely populated), but it looks correct, and more importantly easier to read. Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 13/13] drm/i915: Trim some if-else braces
On Wed, Jun 29, 2016 at 04:09:32PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > Just a bit of cleanup after the previous refactoring. > > Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson And for any earlier patches I may have skipped. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 0/2] drm/i915/opregion: proper handling of DIDL and CADL
This is v4 of [1]. The first three have already been pushed to drm-intel-next-queued. The only change here is the atomic commit. Review and testing would be much appreciated to move this forward. For testing, I've pushed this to opregion-didl-v4 branch of my repo at [2]. Maarten, please check the hunk touching the atomic code in patch 2. BR, Jani. [1] http://mid.gmane.org/cover.1465810007.git.jani.nik...@intel.com [2] https://cgit.freedesktop.org/~jani/drm/ Jani Nikula (2): drm/i915: make i915 the source of acpi device ids for _DOD drm/i915/opregion: update cadl based on actually active outputs drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/intel_display.c | 4 + drivers/gpu/drm/i915/intel_drv.h | 3 + drivers/gpu/drm/i915/intel_opregion.c | 155 +- 4 files changed, 69 insertions(+), 95 deletions(-) -- 2.1.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 2/2] drm/i915/opregion: update cadl based on actually active outputs
Previously we've just shoved the first eight devices in DIDL to CADL
(list of active outputs). Some of the active outputs may have been left
outside of CADL. The problem is, some BIOS implementations prevent
laptop brightness hotkey propagation if the flat panel is not active.
Now that we have connector to acpi device id mapping covered, we can
update CADL based on which outputs are actually active.
v3: actually git add the dev->dev_priv change.
v4: update cadl in intel_shared_dpll_commit() if intel_state->modeset
(Maarten)
Cc: Maarten Lankhorst
Reviewed-and-tested-by: Peter Wu
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_display.c | 4 ++
drivers/gpu/drm/i915/intel_opregion.c | 70 ++-
3 files changed, 43 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 724d34b00196..64ab52529be8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3692,6 +3692,7 @@ extern int intel_opregion_notify_encoder(struct
intel_encoder *intel_encoder,
extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
pci_power_t state);
extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
+extern void intel_opregion_update_cadl(struct drm_i915_private *dev_priv);
#else
static inline int intel_opregion_setup(struct drm_i915_private *dev) { return
0; }
static inline void intel_opregion_register(struct drm_i915_private *dev_priv)
{ }
@@ -3713,6 +3714,7 @@ static inline int intel_opregion_get_panel_type(struct
drm_i915_private *dev)
{
return -ENODEV;
}
+static inline void intel_opregion_update_cadl(struct drm_i915_private
*dev_priv) { }
#endif
/* intel_acpi.c */
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d902a70edb84..4f404900f610 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13953,6 +13953,10 @@ static int intel_atomic_commit(struct drm_device *dev,
dev_priv->wm.distrust_bios_wm = false;
dev_priv->wm.skl_results = intel_state->wm_results;
intel_shared_dpll_commit(state);
+
+ if (intel_state->modeset)
+ intel_opregion_update_cadl(dev_priv);
+
intel_atomic_track_fbs(state);
if (nonblock)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opregion.c
index 632f0178c2b0..8b3f7e6ae4bb 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -642,24 +642,6 @@ static struct notifier_block intel_opregion_notifier = {
* (version 3)
*/
-static u32 get_did(struct intel_opregion *opregion, int i)
-{
- u32 did;
-
- if (i < ARRAY_SIZE(opregion->acpi->didl)) {
- did = opregion->acpi->didl[i];
- } else {
- i -= ARRAY_SIZE(opregion->acpi->didl);
-
- if (WARN_ON(i >= ARRAY_SIZE(opregion->acpi->did2)))
- return 0;
-
- did = opregion->acpi->did2[i];
- }
-
- return did;
-}
-
static void set_did(struct intel_opregion *opregion, int i, u32 val)
{
if (i < ARRAY_SIZE(opregion->acpi->didl)) {
@@ -674,6 +656,14 @@ static void set_did(struct intel_opregion *opregion, int
i, u32 val)
}
}
+static void set_cad(struct intel_opregion *opregion, int i, u32 val)
+{
+ if (WARN_ON(i >= ARRAY_SIZE(opregion->acpi->cadl)))
+ return;
+
+ opregion->acpi->cadl[i] = val;
+}
+
static u32 acpi_display_type(struct intel_connector *connector)
{
u32 display_type;
@@ -759,22 +749,36 @@ static void intel_didl_outputs(struct drm_i915_private
*dev_priv)
set_did(opregion, i, 0);
}
-static void intel_setup_cadls(struct drm_i915_private *dev_priv)
+/* Update CADL to reflect active outputs. */
+void intel_opregion_update_cadl(struct drm_i915_private *dev_priv)
{
struct intel_opregion *opregion = &dev_priv->opregion;
- int i = 0;
- u32 disp_id;
-
- /* Initialize the CADL field by duplicating the DIDL values.
-* Technically, this is not always correct as display outputs may exist,
-* but not active. This initialization is necessary for some Clevo
-* laptops that check this field before processing the brightness and
-* display switching hotkeys. Just like DIDL, CADL is NULL-terminated if
-* there are less than eight devices. */
- do {
- disp_id = get_did(opregion, i);
- opregion->acpi->cadl[i] = disp_id;
- } while (++i < 8 && disp_id != 0);
+ struct intel_crtc *crtc;
+ int i = 0, max_active = ARRAY_SIZE(opregion->acpi->cadl);
+
+ for_each_intel_crtc(dev_priv->dev, crtc) {
+ struct intel_encoder *encoder;
+
+ if (!crtc->acti
Re: [Intel-gfx] Brightness and "touchpad dis-/enable" keys not working for Fujitsu e7x6
On Wed, 29 Jun 2016, Jani Nikula wrote: > On Mon, 27 Jun 2016, Jan-Marek Glogowski wrote: >> Am 25.06.2016 um 11:15 schrieb Michał Kępień: > ...though if you think about it, the whole thing is absolutely hideous: > an *ACPI* driver requires cooperation from a *video* driver to notify > the operating system about a *key press*. Yeah. On one hand I'm utterly amazed. On the other, I've seen and read about other really bizarre things which go on in the BIOSes of computers over the years, so nothing really surprises me anymore. :-) >>> >>> Yes, I am a rookie in this field, so perhaps I simply have not seen >>> enough weirdness yet to just get over something like this. >>> My understanding based on this latest information is that the patch to the i915 driver fixes the brightness control on these laptops and that no changes to fujitsu-laptop are required for this. Is this correct? >>> >>> This is my understanding as well. >> >> Yup. AFAIK the patchset registers the active output ports of the graphic >> chip within ACPI, and this is checked by the brightness keys EC, so if >> the port of the display is disabled, the keys don't work. > > I take it you refer to series at [1]. Sadly, I haven't had the time to > figure out a proper solution to patch 5/5 yet. Maarten, if you have a > moment of inspiration, go for it! ;) Okay, I pushed the first three patches, and updated the other two [1]. Please test. BR, Jani. [1] https://patchwork.freedesktop.org/series/4783/ > > Anyway, someone somewhere thought it's a great idea to filter out > backlight key events at the firmware (possibly AML) level if the flat > panel is not active. It's not a decision in in either i915 or ACPI > driver. In Linux, the obvious thing to have done is to defer all such > policy to userspace. Just provide the mechanism, and the userspace will > figure out what to do with the keypress. Seriously, someone could have > used that information to change the brightness of the *external* > display. But can't have that. . So in the driver we'll just have > to tell ACPI what outputs are active. That's what the patches are about. > > BR, > Jani. > > > [1] http://mid.gmane.org/cover.1465810007.git.jani.nik...@intel.com > > > >> >> So no additional change is needed, as long as it just has to work in X11. >> >> And I just realized the events are generated on key release, which feels >> strange, but since we don't get press and release events, stuff like >> auto-repeat for brightness wouldn't work. >> As to the touch keys, it sounds like this might be a BIOS thing to - is it? >>> >>> Are you referring to the "touchpad toggle" key? If you are, I will soon >>> post a patch adding support for this key so that Jan-Marek can test it. >>> I just need to find some time to actually write it. >> >> This needs a small patch. But getting the keycode into X11 seems to be >> impossible, as X / xev can't handle keycodes > 255 (KEY_TOUCHPAD_TOGGLE). >> >> I'm currently running evrouter, to call a script on the event, which >> dis-/enables the input device using xinput. I would definitely prefer >> any HW or kernel driver solution. I couldn't find a way to map the 530 >> keycode to something < 255 to suit xev and skip the evrouter. Maybe >> Fujitsu will offer a better solution. >> >> Regards, >> >> Jan-Marek -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 12/13] drm/i915: Consolidate legacy semaphore initialization
On 29/06/16 16:34, Chris Wilson wrote: On Wed, Jun 29, 2016 at 04:09:31PM +0100, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Replace per-engine initialization with a common half-programatic, half-data driven code for ease of maintenance and compactness. Signed-off-by: Tvrtko Ursulin This is the biggest pill to swallow (since our 5x5 table is only sparsely populated), but it looks correct, and more importantly easier to read. Yeah I was out of ideas on how to improve it. Fresh mind needed to try and spot a pattern in how MI_SEMAPHORE_SYNC_* and GEN6_*SYNC map to bits and registers respectively, and write it as a function. Reviewed-by: Chris Wilson Thanks! Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 1/2] drm/i915: make i915 the source of acpi device ids for _DOD
The graphics driver is supposed to define the DIDL, which are used for
_DOD, not the BIOS. Restore that behaviour.
This is basically a revert of
commit 3143751ff51a163b77f7efd389043e038f3e008e
Author: Zhang Rui
Date: Mon Mar 29 15:12:16 2010 +0800
drm/i915: set DIDL using the ACPI video output device _ADR method return.
which went out of its way to cater to a specific BIOS, setting up DIDL
based on _ADR method. Perhaps that approach worked on that specific
machine, but on the machines I checked the _ADR method invents the
device identifiers out of thin air if DIDL has not been set. The source
for _ADR is also supposed to be the DIDL set by the driver, not the
other way around.
With this, we'll also limit the number of outputs to what the driver
actually has.
v2: do not set ACPI_DEVICE_ID_SCHEME in the device id (Peter Wu)
Reviewed-and-tested-by: Peter Wu
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_drv.h | 3 ++
drivers/gpu/drm/i915/intel_opregion.c | 87 ++-
2 files changed, 27 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 98a5be4ec8c5..2fbd0a34c9f5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -263,6 +263,9 @@ struct intel_connector {
*/
struct intel_encoder *encoder;
+ /* ACPI device id for ACPI and driver cooperation */
+ u32 acpi_device_id;
+
/* Reads out the current hw, returning true if the connector is enabled
* and active (i.e. dpms ON state). */
bool (*get_hw_state)(struct intel_connector *);
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opregion.c
index 82e687dd09c3..632f0178c2b0 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -674,11 +674,11 @@ static void set_did(struct intel_opregion *opregion, int
i, u32 val)
}
}
-static u32 acpi_display_type(struct drm_connector *connector)
+static u32 acpi_display_type(struct intel_connector *connector)
{
u32 display_type;
- switch (connector->connector_type) {
+ switch (connector->base.connector_type) {
case DRM_MODE_CONNECTOR_VGA:
case DRM_MODE_CONNECTOR_DVIA:
display_type = ACPI_DISPLAY_TYPE_VGA;
@@ -707,7 +707,7 @@ static u32 acpi_display_type(struct drm_connector
*connector)
display_type = ACPI_DISPLAY_TYPE_OTHER;
break;
default:
- MISSING_CASE(connector->connector_type);
+ MISSING_CASE(connector->base.connector_type);
display_type = ACPI_DISPLAY_TYPE_OTHER;
break;
}
@@ -718,34 +718,9 @@ static u32 acpi_display_type(struct drm_connector
*connector)
static void intel_didl_outputs(struct drm_i915_private *dev_priv)
{
struct intel_opregion *opregion = &dev_priv->opregion;
- struct pci_dev *pdev = dev_priv->dev->pdev;
- struct drm_connector *connector;
- acpi_handle handle;
- struct acpi_device *acpi_dev, *acpi_cdev, *acpi_video_bus = NULL;
- unsigned long long device_id;
- acpi_status status;
- u32 temp, max_outputs;
- int i = 0;
-
- handle = ACPI_HANDLE(&pdev->dev);
- if (!handle || acpi_bus_get_device(handle, &acpi_dev))
- return;
-
- if (acpi_is_video_device(handle))
- acpi_video_bus = acpi_dev;
- else {
- list_for_each_entry(acpi_cdev, &acpi_dev->children, node) {
- if (acpi_is_video_device(acpi_cdev->handle)) {
- acpi_video_bus = acpi_cdev;
- break;
- }
- }
- }
-
- if (!acpi_video_bus) {
- DRM_DEBUG_KMS("No ACPI video bus found\n");
- return;
- }
+ struct intel_connector *connector;
+ int i = 0, max_outputs;
+ int display_index[16] = {};
/*
* In theory, did2, the extended didl, gets added at opregion version
@@ -757,45 +732,31 @@ static void intel_didl_outputs(struct drm_i915_private
*dev_priv)
max_outputs = ARRAY_SIZE(opregion->acpi->didl) +
ARRAY_SIZE(opregion->acpi->did2);
- list_for_each_entry(acpi_cdev, &acpi_video_bus->children, node) {
- if (i >= max_outputs) {
- DRM_DEBUG_KMS("More than %u outputs detected via
ACPI\n",
- max_outputs);
- return;
- }
- status = acpi_evaluate_integer(acpi_cdev->handle, "_ADR",
- NULL, &device_id);
- if (ACPI_SUCCESS(status)) {
- if (!device_id)
- goto blind_set;
- set_did(opregion, i++, (u32)(device_id & 0x0f0f));
-
[Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915: Remove request->reset_counter
== Series Details == Series: drm/i915: Remove request->reset_counter URL : https://patchwork.freedesktop.org/series/9278/ State : failure == Summary == Series 9278v1 drm/i915: Remove request->reset_counter http://patchwork.freedesktop.org/api/1.0/series/9278/revisions/1/mbox Test gem_exec_flush: Subgroup basic-batch-kernel-default-cmd: pass -> FAIL (ro-byt-n2820) Test gem_exec_suspend: Subgroup basic-s3: pass -> INCOMPLETE (fi-hsw-i7-4770k) fi-hsw-i7-4770k total:103 pass:86 dwarn:0 dfail:0 fail:0 skip:16 fi-kbl-qkkr total:229 pass:161 dwarn:29 dfail:0 fail:0 skip:39 fi-skl-i5-6260u total:229 pass:202 dwarn:0 dfail:0 fail:2 skip:25 fi-snb-i7-2600 total:229 pass:174 dwarn:0 dfail:0 fail:2 skip:53 ro-bdw-i5-5250u total:229 pass:202 dwarn:1 dfail:1 fail:2 skip:23 ro-bdw-i7-5557U total:229 pass:202 dwarn:1 dfail:1 fail:2 skip:23 ro-bdw-i7-5600u total:229 pass:190 dwarn:0 dfail:1 fail:0 skip:38 ro-bsw-n3050 total:229 pass:177 dwarn:0 dfail:1 fail:2 skip:49 ro-byt-n2820 total:229 pass:178 dwarn:0 dfail:1 fail:5 skip:45 ro-hsw-i3-4010u total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-hsw-i7-4770r total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-ilk-i7-620lm total:229 pass:155 dwarn:0 dfail:1 fail:3 skip:70 ro-ilk1-i5-650 total:224 pass:155 dwarn:0 dfail:1 fail:3 skip:65 ro-ivb-i7-3770 total:229 pass:186 dwarn:0 dfail:1 fail:2 skip:40 ro-ivb2-i7-3770 total:229 pass:190 dwarn:0 dfail:1 fail:2 skip:36 ro-skl3-i5-6260u total:229 pass:206 dwarn:1 dfail:1 fail:2 skip:19 ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48 Results at /archive/results/CI_IGT_test/RO_Patchwork_1331/ 63f6b6c drm-intel-nightly: 2016y-06m-29d-14h-53m-39s UTC integration manifest 4738005 drm/i915: Remove request->reset_counter ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] Revert "drm/i915/kbl: drm/i915: Avoid GuC loading for now on Kabylake."
Reviewed-by: Rodrigo Vivi
On Thu, Jun 2, 2016 at 10:01 AM, Peter Antoine wrote:
> This reverts commit 2b81b84471b9
>
> Signed-off-by: Peter Antoine
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 96d5034..fa4b96e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2812,7 +2812,7 @@ struct drm_i915_cmd_table {
> * command submission once loaded. But these are logically independent
> * properties, so we have separate macros to test them.
> */
> -#define HAS_GUC(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
> +#define HAS_GUC(dev) (IS_GEN9(dev))
> #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
> #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
>
> --
> 1.9.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] i915/guc: Add Kabylake GuC Loading
With the commit message updated feel free to use
Reviewed-by: Rodrigo Vivi
On Fri, Jun 3, 2016 at 2:14 AM, Antoine, Peter wrote:
> I'll remove the comment. :)
>
> -Original Message-
> From: Thierry, Michel
> Sent: Friday, June 3, 2016 9:44 AM
> To: Antoine, Peter ; intel-gfx@lists.freedesktop.org
> Cc: Gordon, David S
> Subject: Re: [PATCH 2/2] i915/guc: Add Kabylake GuC Loading
>
> On 6/2/2016 6:01 PM, Peter Antoine wrote:
>> This patch added the loading of the GuC for Kabylake.
>> It loads a 2.4 firmware.
>^^ not anymore
> Either we update the commit msg to say 9.14 (and let people know how many
> releases we had), or just keep silent about it ;)
>
>>
>> Signed-off-by: Peter Antoine
>> Signed-off-by: Michel Thierry
>> ---
>> drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
>> b/drivers/gpu/drm/i915/intel_guc_loader.c
>> index f2b88c7..413af19 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
>> @@ -65,6 +65,9 @@ MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
>> #define I915_BXT_GUC_UCODE "i915/bxt_guc_ver8_7.bin"
>> MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
>>
>> +#define I915_KBL_GUC_UCODE "i915/kbl_guc_ver9.bin"
>> +MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
>> +
>> /* User-friendly representation of an enum */ const char
>> *intel_guc_fw_status_repr(enum intel_guc_fw_status status) { @@
>> -696,6 +699,10 @@ void intel_guc_init(struct drm_device *dev)
>> fw_path = I915_BXT_GUC_UCODE;
>> guc_fw->guc_fw_major_wanted = 8;
>> guc_fw->guc_fw_minor_wanted = 7;
>> + } else if (IS_KABYLAKE(dev)) {
>> + fw_path = I915_KBL_GUC_UCODE;
>> + guc_fw->guc_fw_major_wanted = 9;
>> + guc_fw->guc_fw_minor_wanted = 14;
>> } else {
>> fw_path = ""; /* unknown device */
>> }
>>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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Re: [Intel-gfx] [PATCH 12/13] drm/i915: Consolidate legacy semaphore initialization
On Wed, Jun 29, 2016 at 04:41:58PM +0100, Tvrtko Ursulin wrote: > > On 29/06/16 16:34, Chris Wilson wrote: > >On Wed, Jun 29, 2016 at 04:09:31PM +0100, Tvrtko Ursulin wrote: > >>From: Tvrtko Ursulin > >> > >>Replace per-engine initialization with a common half-programatic, > >>half-data driven code for ease of maintenance and compactness. > >> > >>Signed-off-by: Tvrtko Ursulin > > > >This is the biggest pill to swallow (since our 5x5 table is only > >sparsely populated), but it looks correct, and more importantly easier to > >read. > > Yeah I was out of ideas on how to improve it. Fresh mind needed to > try and spot a pattern in how MI_SEMAPHORE_SYNC_* and GEN6_*SYNC map > to bits and registers respectively, and write it as a function. It's actually a very simple cyclic function based on register offset = base + (signaler hw_id - waiter hw_id - 1) % num_rings. (The only real challenge is picking the direction.) commit c8c99b0f0dea1ced5d0e10cdb9143356cc16b484 Author: Ben Widawsky Date: Wed Sep 14 20:32:47 2011 -0700 drm/i915: Dumb down the semaphore logic While I think the previous code is correct, it was hard to follow and hard to debug. Since we already have a ring abstraction, might as well use it to handle the semaphore updates and compares. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [01/13] drm/i915: Consolidate write_tail vfunc initializer
== Series Details == Series: series starting with [01/13] drm/i915: Consolidate write_tail vfunc initializer URL : https://patchwork.freedesktop.org/series/9279/ State : failure == Summary == Series 9279v1 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/9279/revisions/1/mbox Test core_auth: Subgroup basic-auth: pass -> INCOMPLETE (ro-bdw-i7-5600u) Test gem_exec_flush: Subgroup basic-batch-kernel-default-cmd: pass -> FAIL (ro-byt-n2820) Test kms_flip: Subgroup basic-flip-vs-wf_vblank: pass -> FAIL (ro-bdw-i5-5250u) fi-hsw-i7-4770k total:229 pass:194 dwarn:0 dfail:0 fail:2 skip:33 fi-kbl-qkkr total:229 pass:160 dwarn:29 dfail:0 fail:0 skip:40 fi-skl-i5-6260u total:229 pass:202 dwarn:0 dfail:0 fail:2 skip:25 fi-skl-i7-6700k total:103 pass:79 dwarn:0 dfail:0 fail:0 skip:23 fi-snb-i7-2600 total:229 pass:174 dwarn:0 dfail:0 fail:2 skip:53 ro-bdw-i5-5250u total:229 pass:201 dwarn:1 dfail:1 fail:3 skip:23 ro-bdw-i7-5557U total:229 pass:202 dwarn:1 dfail:1 fail:2 skip:23 ro-bdw-i7-5600u total:1pass:0dwarn:0 dfail:0 fail:0 skip:0 ro-byt-n2820 total:229 pass:178 dwarn:0 dfail:1 fail:5 skip:45 ro-hsw-i3-4010u total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-hsw-i7-4770r total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-ilk-i7-620lm total:229 pass:155 dwarn:0 dfail:1 fail:3 skip:70 ro-ilk1-i5-650 total:224 pass:155 dwarn:0 dfail:1 fail:3 skip:65 ro-ivb-i7-3770 total:229 pass:186 dwarn:0 dfail:1 fail:2 skip:40 ro-ivb2-i7-3770 total:229 pass:190 dwarn:0 dfail:1 fail:2 skip:36 ro-skl3-i5-6260u total:229 pass:206 dwarn:1 dfail:1 fail:2 skip:19 ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48 ro-bsw-n3050 failed to connect after reboot Results at /archive/results/CI_IGT_test/RO_Patchwork_1332/ 63f6b6c drm-intel-nightly: 2016y-06m-29d-14h-53m-39s UTC integration manifest 571fe9c drm/i915: Trim some if-else braces eda8e1b drm/i915: Consolidate legacy semaphore initialization 27fd9b9 drm/i915: Compact gen8_ring_sync 8382a5e drm/i915: Compact Gen8 semaphore initialization e6df407 drm/i915: Move semaphore object creation into intel_ring_init_semaphores 93df019 drm/i915: Consolidate semaphore vfuncs init 57af58e drm/i915: Consolidate dispatch_execbuffer vfunc 4d2069f drm/i915: Consolidate init_hw vfunc 638e9cf drm/i915: Consolidate get/set_seqno 96f9f94 drm/i915: Consolidate get and put irq vfuncs 403479a drm/i915: Consolidate seqno_barrier vfunc f791cd5 drm/i915: Consolidate add_request vfunc 9056f6d drm/i915: Consolidate write_tail vfunc initializer ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915: Remove request->reset_counter
On Wed, Jun 29, 2016 at 03:45:27PM -, Patchwork wrote: > == Series Details == > > Series: drm/i915: Remove request->reset_counter > URL : https://patchwork.freedesktop.org/series/9278/ > State : failure > > == Summary == > > Series 9278v1 drm/i915: Remove request->reset_counter > http://patchwork.freedesktop.org/api/1.0/series/9278/revisions/1/mbox > > Test gem_exec_flush: > Subgroup basic-batch-kernel-default-cmd: > pass -> FAIL (ro-byt-n2820) > Test gem_exec_suspend: > Subgroup basic-s3: > pass -> INCOMPLETE (fi-hsw-i7-4770k) ... is just failing for everyone today. If anyone could see what was wrong with the machine, that would make for a mighty impressive bug fix. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Removing PCI IDs that are no longer listed as Kabylake.
On Wed, 2016-06-29 at 12:24 +0300, Jani Nikula wrote: > On Fri, 24 Jun 2016, Rodrigo Vivi wrote: > > > > This is unusual. Usually IDs listed on early stages of platform > > definition are kept there as reserved for later use. > > > > However these IDs here are not listed anymore in any of steppings > > and devices IDs tables for Kabylake on configurations overview > > section of BSpec. > > > > So it is better removing them before they become used in any > > other future platform. > > > > Signed-off-by: Rodrigo Vivi > Please reply to the list when you actually push. ops. I merged yesterday but forgot to reply, sorry. > > Both of these could have used cc: drm-intel-fixes because we support > kbl > starting v4.7. I've picked them to fixes now. Thanks > > BR, > Jani. > > > > > --- > > include/drm/i915_pciids.h | 9 ++--- > > 1 file changed, 2 insertions(+), 7 deletions(-) > > > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h > > index 87dde1c..33466bf 100644 > > --- a/include/drm/i915_pciids.h > > +++ b/include/drm/i915_pciids.h > > @@ -325,15 +325,10 @@ > > #define INTEL_KBL_GT3_IDS(info) \ > > INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \ > > INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \ > > - INTEL_VGA_DEVICE(0x5927, info), /* ULT GT3 */ \ > > - INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \ > > - INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */ > > + INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */ > > > > #define INTEL_KBL_GT4_IDS(info) \ > > - INTEL_VGA_DEVICE(0x5932, info), /* DT GT4 */ \ > > - INTEL_VGA_DEVICE(0x593B, info), /* Halo GT4 */ \ > > - INTEL_VGA_DEVICE(0x593A, info), /* SRV GT4 */ \ > > - INTEL_VGA_DEVICE(0x593D, info) /* WKS GT4 */ > > + INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */ > > > > #define INTEL_KBL_IDS(info) \ > > INTEL_KBL_GT1_IDS(info), \ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] i915/guc: Add Kabylake GuC Loading
Thanks.
Rodrigo will sin a new patch now.
Peter.
On Wed, 29 Jun 2016, Rodrigo Vivi wrote:
With the commit message updated feel free to use
Reviewed-by: Rodrigo Vivi
On Fri, Jun 3, 2016 at 2:14 AM, Antoine, Peter wrote:
I'll remove the comment. :)
-Original Message-
From: Thierry, Michel
Sent: Friday, June 3, 2016 9:44 AM
To: Antoine, Peter ; intel-gfx@lists.freedesktop.org
Cc: Gordon, David S
Subject: Re: [PATCH 2/2] i915/guc: Add Kabylake GuC Loading
On 6/2/2016 6:01 PM, Peter Antoine wrote:
This patch added the loading of the GuC for Kabylake.
It loads a 2.4 firmware.
^^ not anymore
Either we update the commit msg to say 9.14 (and let people know how many
releases we had), or just keep silent about it ;)
Signed-off-by: Peter Antoine
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index f2b88c7..413af19 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -65,6 +65,9 @@ MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
#define I915_BXT_GUC_UCODE "i915/bxt_guc_ver8_7.bin"
MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
+#define I915_KBL_GUC_UCODE "i915/kbl_guc_ver9.bin"
+MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
+
/* User-friendly representation of an enum */ const char
*intel_guc_fw_status_repr(enum intel_guc_fw_status status) { @@
-696,6 +699,10 @@ void intel_guc_init(struct drm_device *dev)
fw_path = I915_BXT_GUC_UCODE;
guc_fw->guc_fw_major_wanted = 8;
guc_fw->guc_fw_minor_wanted = 7;
+ } else if (IS_KABYLAKE(dev)) {
+ fw_path = I915_KBL_GUC_UCODE;
+ guc_fw->guc_fw_major_wanted = 9;
+ guc_fw->guc_fw_minor_wanted = 14;
} else {
fw_path = ""; /* unknown device */
}
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--
Peter Antoine (Android Graphics Driver Software Engineer)
-
Intel Corporation (UK) Limited
Registered No. 1134945 (England)
Registered Office: Pipers Way, Swindon SN3 1RJ
VAT No: 860 2173 47
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[Intel-gfx] [PATCH 2/2] drm/i915/bxt: Fix sanity check for BIOS RC6 setup
BXT BIOS has two options related to GPU power management: "RC6(Render
Standby)" and "GT PM Support". The assumption so far was that disabling
either of these options would leave RC6 uninitialized. According to my
tests this isn't so: for a proper RC6 setup we only need the "GT PM
Support" option to be enabled while the "RC6" option only controls
whether RC6 is left enabled or not by BIOS. OTOH we were missing a few
checks to ensure a proper RC6 setup. Add these now and don't fail the
sanity check if RC6 is disabled. This fixes a problem where RC6 remains
disabled after reloading the driver, since we explicitly disable RC6
during unloading.
CC: Sagar Arun Kamble
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_pm.c | 19 ++-
2 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c6bfbf8..92b4046 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7085,12 +7085,17 @@ enum {
#define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
#define GEN6_PMINTRMSK _MMIO(0xA168)
#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
+#define GEN8_MISC_CTRL0_MMIO(0xA180)
#define VLV_PWRDWNUPCTL_MMIO(0xA294)
#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
#define GEN9_PG_ENABLE _MMIO(0xA210)
#define GEN9_RENDER_PG_ENABLE (1<<0)
#define GEN9_MEDIA_PG_ENABLE (1<<1)
+#define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
+#define GEN8_PUSHBUS_ENABLE_MMIO(0xA250)
+#define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
+
#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE +
0x7040C)
#define PIXEL_OVERLAP_CNT_MASK(3 << 30)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5dce264..fe76991 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5015,11 +5015,20 @@ static bool bxt_check_bios_rc6_setup(struct
drm_i915_private *dev_priv)
enable_rc6 = false;
}
- if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
- GEN6_RC_CTL_HW_ENABLE)) &&
- ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
-!(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
- DRM_DEBUG_DRIVER("HW/SW RC6 is not enabled by BIOS.\n");
+ if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
+ !I915_READ(GEN8_PUSHBUS_ENABLE) ||
+ !I915_READ(GEN8_PUSHBUS_SHIFT)) {
+ DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
+ enable_rc6 = false;
+ }
+
+ if (!I915_READ(GEN6_GFXPAUSE)) {
+ DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
+ enable_rc6 = false;
+ }
+
+ if (!I915_READ(GEN8_MISC_CTRL0)) {
+ DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
enable_rc6 = false;
}
--
2.5.0
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[Intel-gfx] [PATCH 1/2] drm/i915: Fix log type for RC6 debug messages
RC6 isn't really a KMS feature, so use the more proper DRIVER log type
for RC6 related debug messages.
CC: Sagar Arun Kamble
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_pm.c | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d7f8ba8..5dce264 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4973,14 +4973,15 @@ static void intel_print_rc6_info(struct
drm_i915_private *dev_priv, u32 mode)
mode = 0;
}
if (HAS_RC6p(dev_priv))
- DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
- onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
- onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
- onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
+ DRM_DEBUG_DRIVER("Enabling RC6 states: "
+"RC6 %s RC6p %s RC6pp %s\n",
+onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
+onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
+onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
else
- DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
- onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
+ DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
+onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
}
static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
@@ -4990,7 +4991,7 @@ static bool bxt_check_bios_rc6_setup(struct
drm_i915_private *dev_priv)
unsigned long rc6_ctx_base;
if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
- DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
+ DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
enable_rc6 = false;
}
@@ -5002,7 +5003,7 @@ static bool bxt_check_bios_rc6_setup(struct
drm_i915_private *dev_priv)
if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
(rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
ggtt->stolen_reserved_size))) {
- DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
+ DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
enable_rc6 = false;
}
@@ -5010,7 +5011,7 @@ static bool bxt_check_bios_rc6_setup(struct
drm_i915_private *dev_priv)
((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
- DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
+ DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
enable_rc6 = false;
}
@@ -5018,7 +5019,7 @@ static bool bxt_check_bios_rc6_setup(struct
drm_i915_private *dev_priv)
GEN6_RC_CTL_HW_ENABLE)) &&
((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
!(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
- DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
+ DRM_DEBUG_DRIVER("HW/SW RC6 is not enabled by BIOS.\n");
enable_rc6 = false;
}
@@ -5050,8 +5051,9 @@ int sanitize_rc6_option(struct drm_i915_private
*dev_priv, int enable_rc6)
mask = INTEL_RC6_ENABLE;
if ((enable_rc6 & mask) != enable_rc6)
- DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d,
valid %d)\n",
- enable_rc6 & mask, enable_rc6, mask);
+ DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
+"(requested %d, valid %d)\n",
+enable_rc6 & mask, enable_rc6, mask);
return enable_rc6 & mask;
}
--
2.5.0
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Re: [Intel-gfx] [PATCH 12/13] drm/i915: Consolidate legacy semaphore initialization
On 29/06/16 17:00, Chris Wilson wrote: On Wed, Jun 29, 2016 at 04:41:58PM +0100, Tvrtko Ursulin wrote: On 29/06/16 16:34, Chris Wilson wrote: On Wed, Jun 29, 2016 at 04:09:31PM +0100, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Replace per-engine initialization with a common half-programatic, half-data driven code for ease of maintenance and compactness. Signed-off-by: Tvrtko Ursulin This is the biggest pill to swallow (since our 5x5 table is only sparsely populated), but it looks correct, and more importantly easier to read. Yeah I was out of ideas on how to improve it. Fresh mind needed to try and spot a pattern in how MI_SEMAPHORE_SYNC_* and GEN6_*SYNC map to bits and registers respectively, and write it as a function. It's actually a very simple cyclic function based on register offset = base + (signaler hw_id - waiter hw_id - 1) % num_rings. (The only real challenge is picking the direction.) commit c8c99b0f0dea1ced5d0e10cdb9143356cc16b484 Author: Ben Widawsky Date: Wed Sep 14 20:32:47 2011 -0700 drm/i915: Dumb down the semaphore logic While I think the previous code is correct, it was hard to follow and hard to debug. Since we already have a ring abstraction, might as well use it to handle the semaphore updates and compares. Should I try to go back to that then? Since I am not too happy with the sparse table... This has passed CI so we could merge some of it if that would help your series, or wait until I rework this patch. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Ro.CI.BAT: failure for drm/i915/opregion: proper handling of DIDL and CADL (rev4)
== Series Details == Series: drm/i915/opregion: proper handling of DIDL and CADL (rev4) URL : https://patchwork.freedesktop.org/series/4783/ State : failure == Summary == Series 4783v4 drm/i915/opregion: proper handling of DIDL and CADL http://patchwork.freedesktop.org/api/1.0/series/4783/revisions/4/mbox Test drv_module_reload_basic: pass -> SKIP (fi-skl-i5-6260u) Test gem_exec_flush: Subgroup basic-batch-kernel-default-cmd: pass -> FAIL (ro-byt-n2820) Test kms_pipe_crc_basic: Subgroup nonblocking-crc-pipe-a-frame-sequence: pass -> FAIL (ro-bdw-i7-5557U) fi-kbl-qkkr total:229 pass:161 dwarn:29 dfail:0 fail:0 skip:39 fi-skl-i5-6260u total:229 pass:201 dwarn:0 dfail:0 fail:2 skip:26 fi-snb-i7-2600 total:229 pass:174 dwarn:0 dfail:0 fail:2 skip:53 ro-bdw-i5-5250u total:229 pass:202 dwarn:1 dfail:1 fail:2 skip:23 ro-bdw-i7-5557U total:229 pass:201 dwarn:1 dfail:1 fail:3 skip:23 ro-bdw-i7-5600u total:229 pass:190 dwarn:0 dfail:1 fail:0 skip:38 ro-bsw-n3050 total:229 pass:177 dwarn:0 dfail:1 fail:2 skip:49 ro-byt-n2820 total:229 pass:178 dwarn:0 dfail:1 fail:5 skip:45 ro-hsw-i3-4010u total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-hsw-i7-4770r total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-ilk-i7-620lm total:229 pass:155 dwarn:0 dfail:1 fail:3 skip:70 ro-ilk1-i5-650 total:224 pass:155 dwarn:0 dfail:1 fail:3 skip:65 ro-skl3-i5-6260u total:229 pass:206 dwarn:1 dfail:1 fail:2 skip:19 ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48 fi-hsw-i7-4770k failed to connect after reboot fi-skl-i7-6700k failed to connect after reboot ro-ivb2-i7-3770 failed to connect after reboot ro-ivb-i7-3770 failed to connect after reboot Results at /archive/results/CI_IGT_test/RO_Patchwork_1333/ 63f6b6c drm-intel-nightly: 2016y-06m-29d-14h-53m-39s UTC integration manifest 538feac drm/i915/opregion: update cadl based on actually active outputs 2d1aff8 drm/i915: make i915 the source of acpi device ids for _DOD ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 12/13] drm/i915: Consolidate legacy semaphore initialization
On Wed, Jun 29, 2016 at 05:14:11PM +0100, Tvrtko Ursulin wrote: > > On 29/06/16 17:00, Chris Wilson wrote: > >On Wed, Jun 29, 2016 at 04:41:58PM +0100, Tvrtko Ursulin wrote: > >> > >>On 29/06/16 16:34, Chris Wilson wrote: > >>>On Wed, Jun 29, 2016 at 04:09:31PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > Replace per-engine initialization with a common half-programatic, > half-data driven code for ease of maintenance and compactness. > > Signed-off-by: Tvrtko Ursulin > >>> > >>>This is the biggest pill to swallow (since our 5x5 table is only > >>>sparsely populated), but it looks correct, and more importantly easier to > >>>read. > >> > >>Yeah I was out of ideas on how to improve it. Fresh mind needed to > >>try and spot a pattern in how MI_SEMAPHORE_SYNC_* and GEN6_*SYNC map > >>to bits and registers respectively, and write it as a function. > > > >It's actually a very simple cyclic function based on register > >offset = base + (signaler hw_id - waiter hw_id - 1) % num_rings. > > > >(The only real challenge is picking the direction.) > > > >commit c8c99b0f0dea1ced5d0e10cdb9143356cc16b484 > >Author: Ben Widawsky > >Date: Wed Sep 14 20:32:47 2011 -0700 > > > > drm/i915: Dumb down the semaphore logic > > > > While I think the previous code is correct, it was hard to follow and > > hard to debug. Since we already have a ring abstraction, might as well > > use it to handle the semaphore updates and compares. > > Should I try to go back to that then? Since I am not too happy with > the sparse table... > > This has passed CI so we could merge some of it if that would help > your series, or wait until I rework this patch. The rule of thumb is incremental improvements tell a better story and should be easier to find a misstep. (My personal experience says the longer I play with a patch the larger it gets...) In short, you've already consolidated a lot of duplication in the vfuncs that will make my life easier (after some rebasing joy). Anything more is just icing on the cake. :) -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 12/13] drm/i915: Consolidate legacy semaphore initialization
On 29/06/16 17:24, Chris Wilson wrote: On Wed, Jun 29, 2016 at 05:14:11PM +0100, Tvrtko Ursulin wrote: On 29/06/16 17:00, Chris Wilson wrote: On Wed, Jun 29, 2016 at 04:41:58PM +0100, Tvrtko Ursulin wrote: On 29/06/16 16:34, Chris Wilson wrote: On Wed, Jun 29, 2016 at 04:09:31PM +0100, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Replace per-engine initialization with a common half-programatic, half-data driven code for ease of maintenance and compactness. Signed-off-by: Tvrtko Ursulin This is the biggest pill to swallow (since our 5x5 table is only sparsely populated), but it looks correct, and more importantly easier to read. Yeah I was out of ideas on how to improve it. Fresh mind needed to try and spot a pattern in how MI_SEMAPHORE_SYNC_* and GEN6_*SYNC map to bits and registers respectively, and write it as a function. It's actually a very simple cyclic function based on register offset = base + (signaler hw_id - waiter hw_id - 1) % num_rings. (The only real challenge is picking the direction.) commit c8c99b0f0dea1ced5d0e10cdb9143356cc16b484 Author: Ben Widawsky Date: Wed Sep 14 20:32:47 2011 -0700 drm/i915: Dumb down the semaphore logic While I think the previous code is correct, it was hard to follow and hard to debug. Since we already have a ring abstraction, might as well use it to handle the semaphore updates and compares. Should I try to go back to that then? Since I am not too happy with the sparse table... This has passed CI so we could merge some of it if that would help your series, or wait until I rework this patch. The rule of thumb is incremental improvements tell a better story and should be easier to find a misstep. (My personal experience says the longer I play with a patch the larger it gets...) In short, you've already consolidated a lot of duplication in the vfuncs that will make my life easier (after some rebasing joy). Anything more is just icing on the cake. :) It also looks like I have broke something, wonder how CI did not catch it or I am imagining things. "drm/i915: Consolidate dispatch_execbuffer vfunc" looks wrong wrt add_request and dispatch_execbuffer for gen8+. Leaving it for tomorrow. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/2] i915/guc: Add Kabylake GuC Loading
This patch added the loading of the GuC for Kabylake.
It loads a 9.14 firmware.
Signed-off-by: Peter Antoine
Signed-off-by: Michel Thierry
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 51d108e..4862d58 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -65,6 +65,9 @@ MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
#define I915_BXT_GUC_UCODE "i915/bxt_guc_ver8.7.bin"
MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
+#define I915_KBL_GUC_UCODE "i915/kbl_guc_ver9_14.bin"
+MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
+
/* User-friendly representation of an enum */
const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
{
@@ -701,6 +704,10 @@ void intel_guc_ucode_init(struct drm_device *dev)
fw_path = I915_BXT_GUC_UCODE;
guc_fw->major_ver_wanted = 8;
guc_fw->minor_ver_wanted = 0;
+ } else if (IS_KABYLAKE(dev)) {
+ fw_path = I915_KBL_GUC_UCODE;
+ guc_fw->major_ver_wanted = 9;
+ guc_fw->minor_ver_wanted = 14;
}
if (fw_path == NULL)
--
1.9.1
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[Intel-gfx] [PATCH v3] drm/i915: Consolidate dispatch_execbuffer vfunc
From: Tvrtko Ursulin
v2: Put dispatch_execbuffer before add_request. (Chris Wilson)
v3: Fix add_request and irq_seqno_barrier for gen8+.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 27 ---
1 file changed, 8 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index dcacf17c525f..15f8ded6325d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2881,10 +2881,16 @@ static void intel_ring_default_vfuncs(struct
drm_i915_private *dev_priv,
engine->get_seqno = ring_get_seqno;
engine->set_seqno = ring_set_seqno;
- if (INTEL_GEN(dev_priv) >= 6) {
+ if (INTEL_GEN(dev_priv) >= 8) {
+ engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
+ engine->add_request = gen6_add_request;
+ engine->irq_seqno_barrier = gen6_seqno_barrier;
+ } else if (INTEL_GEN(dev_priv) >= 6) {
+ engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
engine->add_request = gen6_add_request;
engine->irq_seqno_barrier = gen6_seqno_barrier;
} else {
+ engine->dispatch_execbuffer = i965_dispatch_execbuffer;
engine->add_request = i9xx_add_request;
}
@@ -2993,15 +2999,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
if (IS_HASWELL(dev_priv))
engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
- else if (IS_GEN8(dev_priv))
- engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
- else if (INTEL_GEN(dev_priv) >= 6)
- engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
- else if (INTEL_GEN(dev_priv) >= 4)
- engine->dispatch_execbuffer = i965_dispatch_execbuffer;
else if (IS_I830(dev_priv) || IS_845G(dev_priv))
engine->dispatch_execbuffer = i830_dispatch_execbuffer;
- else
+ else if (INTEL_GEN(dev_priv) <= 3)
engine->dispatch_execbuffer = i915_dispatch_execbuffer;
engine->init_hw = init_render_ring;
engine->cleanup = render_ring_cleanup;
@@ -3059,8 +3059,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
if (INTEL_GEN(dev_priv) >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
- engine->dispatch_execbuffer =
- gen8_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen8_ring_sync;
engine->semaphore.signal = gen8_xcs_signal;
@@ -3068,8 +3066,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
}
} else {
engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
- engine->dispatch_execbuffer =
- gen6_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen6_ring_sync;
engine->semaphore.signal = gen6_signal;
@@ -3093,7 +3089,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
} else {
engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
}
- engine->dispatch_execbuffer = i965_dispatch_execbuffer;
}
return intel_init_ring_buffer(dev, engine);
@@ -3118,8 +3113,6 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
engine->flush = gen6_bsd_ring_flush;
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
- engine->dispatch_execbuffer =
- gen8_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen8_ring_sync;
engine->semaphore.signal = gen8_xcs_signal;
@@ -3146,7 +3139,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
if (INTEL_GEN(dev_priv) >= 8) {
engine->irq_enable_mask =
GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
- engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
if (i915_semaphore_is_enabled(dev_priv)) {
engine->semaphore.sync_to = gen8_ring_sync;
engine->semaphore.signal = gen8_xcs_signal;
@@ -3154,7 +3146,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
}
} else {
engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
- engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
Re: [Intel-gfx] [PATCH 12/13] drm/i915: Consolidate legacy semaphore initialization
On Wed, Jun 29, 2016 at 05:34:27PM +0100, Tvrtko Ursulin wrote: > It also looks like I have broke something, wonder how CI did not > catch it or I am imagining things. "drm/i915: Consolidate > dispatch_execbuffer vfunc" looks wrong wrt add_request and > dispatch_execbuffer for gen8+. Leaving it for tomorrow. Ah, should also include i915.enable_execlists=0 when sending to trybot. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 0/2] drm/i915/opregion: proper handling of DIDL and CADL
Hi Jani, I just tested your branch (2f9a317) and can confirm that the fix is still valid. evtest reports brightness up/down events. Kind regards, Peter https://lekensteyn.nl (pardon my brevity, top-posting and formatting, sent from my phone) On 29 June 2016 17:36:40 CEST, Jani Nikula wrote: >This is v4 of [1]. The first three have already been pushed to >drm-intel-next-queued. The only change here is the atomic commit. > >Review and testing would be much appreciated to move this forward. For >testing, I've pushed this to opregion-didl-v4 branch of my repo at [2]. > >Maarten, please check the hunk touching the atomic code in patch 2. > >BR, >Jani. > > >[1] http://mid.gmane.org/cover.1465810007.git.jani.nik...@intel.com >[2] https://cgit.freedesktop.org/~jani/drm/ > >Jani Nikula (2): > drm/i915: make i915 the source of acpi device ids for _DOD > drm/i915/opregion: update cadl based on actually active outputs > > drivers/gpu/drm/i915/i915_drv.h | 2 + > drivers/gpu/drm/i915/intel_display.c | 4 + > drivers/gpu/drm/i915/intel_drv.h | 3 + >drivers/gpu/drm/i915/intel_opregion.c | 155 >+- > 4 files changed, 69 insertions(+), 95 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Ro.CI.BAT: success for series starting with [1/2] drm/i915: Fix log type for RC6 debug messages
== Series Details == Series: series starting with [1/2] drm/i915: Fix log type for RC6 debug messages URL : https://patchwork.freedesktop.org/series/9285/ State : success == Summary == Series 9285v1 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/9285/revisions/1/mbox Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-c: dmesg-warn -> SKIP (ro-bdw-i5-5250u) fi-skl-i5-6260u total:229 pass:202 dwarn:0 dfail:0 fail:2 skip:25 fi-snb-i7-2600 total:229 pass:174 dwarn:0 dfail:0 fail:2 skip:53 ro-bdw-i5-5250u total:229 pass:202 dwarn:2 dfail:1 fail:2 skip:22 ro-bdw-i7-5557U total:229 pass:202 dwarn:1 dfail:1 fail:2 skip:23 ro-bdw-i7-5600u total:229 pass:190 dwarn:0 dfail:1 fail:0 skip:38 ro-byt-n2820 total:229 pass:178 dwarn:0 dfail:1 fail:5 skip:45 ro-hsw-i3-4010u total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-hsw-i7-4770r total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-ilk-i7-620lm total:229 pass:155 dwarn:0 dfail:1 fail:3 skip:70 ro-ilk1-i5-650 total:224 pass:155 dwarn:0 dfail:1 fail:3 skip:65 ro-ivb-i7-3770 total:229 pass:186 dwarn:0 dfail:1 fail:2 skip:40 ro-ivb2-i7-3770 total:229 pass:190 dwarn:0 dfail:1 fail:2 skip:36 ro-skl3-i5-6260u total:229 pass:206 dwarn:1 dfail:1 fail:2 skip:19 ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48 fi-kbl-qkkr failed to connect after reboot fi-skl-i7-6700k failed to connect after reboot ro-bsw-n3050 failed to connect after reboot Results at /archive/results/CI_IGT_test/RO_Patchwork_1334/ 8a6521c drm-intel-nightly: 2016y-06m-29d-16h-08m-16s UTC integration manifest 4595c784 drm/i915/bxt: Fix sanity check for BIOS RC6 setup 52064d0 drm/i915: Fix log type for RC6 debug messages ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/6] drm/i915/huc: Add HuC fw loading support
But the merge on hug/guc loading is just the minor thing Daniel asked. The major request is to stop using the fetch_status, but errnos instead. so, maybe one extra patch that simplifies this right now before this series would be the ideal so we could speed up the merge and maybe later to the unified firmware loading solution. On Wed, Jun 29, 2016 at 7:31 AM, Dave Gordon wrote: > On 29/06/16 00:03, Rodrigo Vivi wrote: >> >> I don't believe we need to be that extreme here. >> >> Daniel asked a cleaner version, but we don't need to block the huc on >> a full rework of an unified fw loader. > > > Oh, I agree, we should take this "mostly" as-is and then reunify them after. > > .Dave. > -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC] i915: Add fence fds to execbuffer2 uapi
On Mon 27 Jun 2016, Chris Wilson wrote: > On Mon, Jun 27, 2016 at 01:18:59PM -0700, Chad Versace wrote: > > On Mon 27 Jun 2016, Chad Versace wrote: > > > Let the hight 32 bits of drm_i915_gem_execbuffer2::rsvd1 contain an > > > input and/or output fence fd, whose presence is controlled by flags. > > > Also add I915_PARAM_HAS_FENCE_FD. > > > > > > Signed-off-by: Chad Versace > > > --- > > > include/uapi/drm/i915_drm.h | 24 ++-- > > > 1 file changed, 22 insertions(+), 2 deletions(-) > > > > Oops. git-send-email stripped the notes to the patch. Here's the notes: > > > > This RFC proposes a uapi that integrates execbuf with Android sync fds. Of > > course, this is *only* an RFC because other devs are working on the i915 > > internals, and this patch depends on that work. > > Why not just use the earlier patches for the uAPI as well? I examined all the patches that John Harrison sent to the list, and they contained no uapi. Is there another patchset, from someone else (possibly you), that proposes a uapi? > > Why am I sending an RFC this early? I will soon begin prototyping Intel's > > Mesa implementation of EGL_ANDROID_native_fence_sync, and that prototype > > will > > be easier to write if I have a rough expectation of i915's eventual fence fd > > uapi. > > > > Please provide feedback: Does this roughly look like the uapi that the i915 > > devs expect? > > Not quite. You have to use separate in/out dwords (i.e. rsvd2) in order > to ensure that we don't overwite the in-fence when dealing with error > paths (i.e. so that userspace can feed in the same execbuf parameters > following EINTR, and you don't have confusion between in/out parameters). Right. I forgot about resubmission on EINTR. > You have to also mark the ioctl as writing the new structures which is an > ABI break and so requires a new identifier (otherwise you break userspace > passing in the args from read-only memory). Thanks for explaining the obvious ABI break to this kernel noob. > Playind devil's advocate, an alternative to every driver implementing > their own fence extension for execbuf/cmdsubmit would be to add support > for explicit sync_fences to be added via dmabuf. (Instead of setting the > fence on the execbuf, you would set the fence on the batch buffer obj, > or surface of interest - though for CreateSync, it would have to be the > batch. Extracting the fence is then supplied by querying the batch buffer > dmabuf. It's not as explicit, but I suspect such uABI will be added to > dmabuf and will be required to be supported in the driver to handle > implicit fencing between PRIME anyway.) If I were arguing with the devil, I would claim that uapi that attached fence fds to dma_bufs seems more elegant, but API that attaches fence fds to batch bos prevents an optimized use case in Vulkan's submission model. In Vulkan, the user submits work by compiling a VkCommandBuffer (which is closely related to Intel's batch bo) and then submitting it to a VkQueue (which is related to a GPU ring). For repetive rendering tasks, the Vulkan API encourages the user to re-use the compiled VkCommandBuffer by re-submitting it to the VkQueue. When the user resubmits a VkCommandBuffer, the Vulkan spec doesn't *require* the driver to resubmit the same exact batch buffer; but that's the spec's *intent*. And Mesa does that today; when the user compiles a VkCommandBuffer, we compile the batch buffer immediately, and resubmit that exact batch buffer each time the user submits the VkCommandBuffer. Vulkan doesn't use fence fds today, but it will someday. If the kernel doesn't add fence fds to the execbuffer ioctl, but instead requires that the fences be associated with a batch buffer, then that would prevents the natural batch buffer re-use in Vulkan. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC] i915: Add fence fds to execbuffer2 uapi
On Tue 28 Jun 2016, John Harrison wrote: > The latest set of patches (including changes from feedback about rsvd > fields) never actually got posted to the mailing list due to the above issue > with de-staging. I have just updated my FDO git account with them instead. > The kernel patch is: > https://cgit.freedesktop.org/~johnharr/scheduler/commit/?h=all&id=b7cd5e85edce4af9d7d4c34bb640cd49e31236a8 > > The userland LibDRM patch is: > https://cgit.freedesktop.org/~johnharr/scheduler/commit/?h=LibDRM&id=f11b2d577904b1a096d5b36384a9cc83ba51cbb8 Thanks for the sharing the code. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PACTH i-g-t v1] lib/igt_gt: Fix unused variable warning for non-x86 targets
On Mon, Jun 27, 2016 at 06:58:24AM -0400, robert.f...@collabora.com wrote: > From: Robert Foss > > Moved variable declaration inside #if case to avoid unused variable warnings > on non-x86 targets. > > Signed-off-by: Robert Foss Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: tidy up request alloc
Return the allocated request pointer directly to remove
the double pointer parameter.
Signed-off-by: Hong Liu
---
drivers/gpu/drm/i915/i915_gem.c | 25 +++--
1 file changed, 7 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1d98782..9881455 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2988,32 +2988,26 @@ void i915_gem_request_free(struct kref *req_ref)
kmem_cache_free(req->i915->requests, req);
}
-static inline int
+static inline struct drm_i915_gem_request *
__i915_gem_request_alloc(struct intel_engine_cs *engine,
-struct i915_gem_context *ctx,
-struct drm_i915_gem_request **req_out)
+struct i915_gem_context *ctx)
{
struct drm_i915_private *dev_priv = engine->i915;
unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error);
struct drm_i915_gem_request *req;
int ret;
- if (!req_out)
- return -EINVAL;
-
- *req_out = NULL;
-
/* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
* EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex
* and restart.
*/
ret = i915_gem_check_wedge(reset_counter, dev_priv->mm.interruptible);
if (ret)
- return ret;
+ return ERR_PTR(ret);
req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
if (req == NULL)
- return -ENOMEM;
+ return ERR_PTR(-ENOMEM);
ret = i915_gem_get_seqno(engine->i915, &req->seqno);
if (ret)
@@ -3041,14 +3035,13 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
if (ret)
goto err_ctx;
- *req_out = req;
- return 0;
+ return req;
err_ctx:
i915_gem_context_unreference(ctx);
err:
kmem_cache_free(dev_priv->requests, req);
- return ret;
+ return ERR_PTR(ret);
}
/**
@@ -3067,13 +3060,9 @@ struct drm_i915_gem_request *
i915_gem_request_alloc(struct intel_engine_cs *engine,
struct i915_gem_context *ctx)
{
- struct drm_i915_gem_request *req;
- int err;
-
if (ctx == NULL)
ctx = engine->i915->kernel_context;
- err = __i915_gem_request_alloc(engine, ctx, &req);
- return err ? ERR_PTR(err) : req;
+ return __i915_gem_request_alloc(engine, ctx);
}
struct drm_i915_gem_request *
--
2.7.4
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[Intel-gfx] ✗ Ro.CI.BAT: warning for series starting with [01/13] drm/i915: Consolidate write_tail vfunc initializer (rev2)
== Series Details == Series: series starting with [01/13] drm/i915: Consolidate write_tail vfunc initializer (rev2) URL : https://patchwork.freedesktop.org/series/9279/ State : warning == Summary == Series 9279v2 Series without cover letter http://patchwork.freedesktop.org/api/1.0/series/9279/revisions/2/mbox Test gem_exec_flush: Subgroup basic-batch-kernel-default-cmd: fail -> PASS (ro-byt-n2820) Test kms_flip: Subgroup basic-flip-vs-dpms: pass -> DMESG-WARN (ro-byt-n2820) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: dmesg-warn -> SKIP (ro-bdw-i5-5250u) Subgroup suspend-read-crc-pipe-c: dmesg-warn -> SKIP (ro-bdw-i5-5250u) fi-skl-i5-6260u total:229 pass:202 dwarn:0 dfail:0 fail:2 skip:25 fi-snb-i7-2600 total:229 pass:174 dwarn:0 dfail:0 fail:2 skip:53 ro-bdw-i5-5250u total:229 pass:202 dwarn:1 dfail:1 fail:2 skip:23 ro-bdw-i7-5600u total:229 pass:190 dwarn:0 dfail:1 fail:0 skip:38 ro-bsw-n3050 total:229 pass:176 dwarn:1 dfail:1 fail:2 skip:49 ro-byt-n2820 total:229 pass:178 dwarn:1 dfail:1 fail:4 skip:45 ro-hsw-i3-4010u total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-hsw-i7-4770r total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-ilk-i7-620lm total:229 pass:155 dwarn:0 dfail:1 fail:3 skip:70 ro-ilk1-i5-650 total:224 pass:155 dwarn:0 dfail:1 fail:3 skip:65 ro-ivb-i7-3770 total:229 pass:186 dwarn:0 dfail:1 fail:2 skip:40 ro-ivb2-i7-3770 total:229 pass:190 dwarn:0 dfail:1 fail:2 skip:36 ro-skl3-i5-6260u total:229 pass:206 dwarn:1 dfail:1 fail:2 skip:19 ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48 fi-kbl-qkkr failed to connect after reboot fi-skl-i7-6700k failed to connect after reboot ro-bdw-i7-5557U failed to connect after reboot Results at /archive/results/CI_IGT_test/RO_Patchwork_1335/ 8a6521c drm-intel-nightly: 2016y-06m-29d-16h-08m-16s UTC integration manifest 5a0b3b6 drm/i915: Trim some if-else braces 6546565 drm/i915: Consolidate legacy semaphore initialization 7cd391c drm/i915: Compact gen8_ring_sync c36607f drm/i915: Compact Gen8 semaphore initialization e862990 drm/i915: Move semaphore object creation into intel_ring_init_semaphores 2168bca drm/i915: Consolidate semaphore vfuncs init af5b4cc drm/i915: Consolidate dispatch_execbuffer vfunc 0c72cfa drm/i915: Consolidate init_hw vfunc 2cb2fab drm/i915: Consolidate get/set_seqno 6e3bbdc drm/i915: Consolidate get and put irq vfuncs 24b7851 drm/i915: Consolidate seqno_barrier vfunc 0bd03a1 drm/i915: Consolidate add_request vfunc 42e13b2 drm/i915: Consolidate write_tail vfunc initializer ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Ro.CI.BAT: success for drm/i915: tidy up request alloc
== Series Details == Series: drm/i915: tidy up request alloc URL : https://patchwork.freedesktop.org/series/9300/ State : success == Summary == Series 9300v1 drm/i915: tidy up request alloc http://patchwork.freedesktop.org/api/1.0/series/9300/revisions/1/mbox Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: dmesg-warn -> SKIP (ro-bdw-i5-5250u) Subgroup suspend-read-crc-pipe-c: dmesg-warn -> SKIP (ro-bdw-i5-5250u) fi-kbl-qkkr total:229 pass:161 dwarn:27 dfail:0 fail:0 skip:41 fi-skl-i5-6260u total:229 pass:202 dwarn:0 dfail:0 fail:2 skip:25 fi-snb-i7-2600 total:229 pass:174 dwarn:0 dfail:0 fail:2 skip:53 ro-bdw-i5-5250u total:229 pass:202 dwarn:1 dfail:1 fail:2 skip:23 ro-bdw-i7-5557U total:229 pass:202 dwarn:1 dfail:1 fail:2 skip:23 ro-bdw-i7-5600u total:229 pass:190 dwarn:0 dfail:1 fail:0 skip:38 ro-bsw-n3050 total:229 pass:177 dwarn:0 dfail:1 fail:2 skip:49 ro-byt-n2820 total:229 pass:178 dwarn:0 dfail:1 fail:5 skip:45 ro-hsw-i3-4010u total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-hsw-i7-4770r total:229 pass:195 dwarn:0 dfail:1 fail:2 skip:31 ro-ilk-i7-620lm total:229 pass:155 dwarn:0 dfail:1 fail:3 skip:70 ro-ilk1-i5-650 total:224 pass:155 dwarn:0 dfail:1 fail:3 skip:65 ro-ivb-i7-3770 total:229 pass:186 dwarn:0 dfail:1 fail:2 skip:40 ro-ivb2-i7-3770 total:229 pass:190 dwarn:0 dfail:1 fail:2 skip:36 ro-skl3-i5-6260u total:229 pass:206 dwarn:1 dfail:1 fail:2 skip:19 ro-snb-i7-2620M total:229 pass:179 dwarn:0 dfail:1 fail:1 skip:48 Results at /archive/results/CI_IGT_test/RO_Patchwork_1336/ 8a6521c drm-intel-nightly: 2016y-06m-29d-16h-08m-16s UTC integration manifest 0c7486c7 drm/i915: tidy up request alloc ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
