[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/vlv: Enable/disable VGA hotplugging properly
== Series Details == Series: drm/i915/vlv: Enable/disable VGA hotplugging properly URL : https://patchwork.freedesktop.org/series/5012/ State : failure == Summary == Series 5012v1 drm/i915/vlv: Enable/disable VGA hotplugging properly http://patchwork.freedesktop.org/api/1.0/series/5012/revisions/1/mbox/ Test drv_module_reload_basic: dmesg-warn -> DMESG-FAIL (ilk-hp8440p) Test gem_ctx_switch: Subgroup basic-default: pass -> FAIL (bdw-ultra) Test gem_exec_nop: Subgroup basic: fail -> PASS (snb-x220t) pass -> FAIL (bdw-ultra) Test gem_exec_suspend: Subgroup basic-s4: skip -> FAIL (bdw-ultra) Test gem_exec_whisper: Subgroup basic: pass -> FAIL (bdw-ultra) Test gem_mmap_gtt: Subgroup basic-read-write-distinct: incomplete -> PASS (snb-x220t) Test gem_ringfill: Subgroup basic-default-hang: pass -> INCOMPLETE (snb-dellxps) Test gem_sync: Subgroup basic-all: fail -> PASS (snb-x220t) pass -> FAIL (bdw-ultra) Subgroup basic-blt: pass -> FAIL (bdw-ultra) Subgroup basic-bsd: pass -> FAIL (bdw-ultra) Subgroup basic-default: pass -> FAIL (bdw-ultra) Subgroup basic-render: pass -> FAIL (bdw-ultra) UNSTABLE Subgroup basic-vebox: pass -> FAIL (bdw-ultra) Test kms_flip: Subgroup basic-flip-vs-dpms: pass -> DMESG-WARN (ilk-hp8440p) UNSTABLE Subgroup basic-flip-vs-wf_vblank: pass -> FAIL (byt-nuc) Test kms_force_connector_basic: Subgroup force-load-detect: pass -> SKIP (ilk-hp8440p) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-c: dmesg-fail -> SKIP (snb-x220t) pass -> DMESG-WARN (bsw-nuc-2) Test pm_rpm: Subgroup basic-pci-d3-state: pass -> DMESG-WARN (bsw-nuc-2) pass -> DMESG-WARN (byt-nuc) Subgroup basic-rte: dmesg-warn -> PASS (byt-nuc) UNSTABLE Test prime_self_import: Subgroup basic-with_fd_dup: incomplete -> PASS (snb-x220t) bdw-nuci7total:195 pass:181 dwarn:1 dfail:0 fail:1 skip:12 bdw-ultratotal:195 pass:162 dwarn:1 dfail:0 fail:12 skip:20 bsw-nuc-2total:195 pass:154 dwarn:3 dfail:0 fail:1 skip:37 byt-nuc total:195 pass:156 dwarn:2 dfail:0 fail:2 skip:35 hsw-brixbox total:195 pass:171 dwarn:1 dfail:0 fail:1 skip:22 hsw-gt2 total:195 pass:176 dwarn:1 dfail:0 fail:1 skip:17 ilk-hp8440p total:195 pass:127 dwarn:1 dfail:1 fail:1 skip:65 ivb-t430stotal:195 pass:168 dwarn:1 dfail:0 fail:1 skip:25 skl-i7k-2total:195 pass:170 dwarn:1 dfail:0 fail:1 skip:23 snb-dellxps total:116 pass:96 dwarn:0 dfail:0 fail:1 skip:18 snb-x220ttotal:195 pass:159 dwarn:1 dfail:0 fail:2 skip:33 Results at /archive/results/CI_IGT_test/Patchwork_1738/ 2702045fbd4188c1c26bd890bc43976fd10937ad drm-intel-nightly: 2016y-03m-29d-12h-21m-19s UTC integration manifest edf6cf0dff7e26f6695c35399197dc36813833a1 drm/i915/vlv: Enable/disable VGA hotplugging properly ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/2] drm/i915: Rename hw state checker to hw state verifier.
Check functions are used by atomic to see if the new state will
be allowed. There's also a hw state checker which checks afterwards
that the committed state is correct. Rename it to hw state verifier
to reduce some confusion.
Suggested-by: Matt Roper
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 60 ++--
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9e63720428fc..8b423cdd5295 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6283,7 +6283,7 @@ void intel_encoder_destroy(struct drm_encoder *encoder)
/* Cross check the actual hw state with our own modeset state tracking (and
it's
* internal consistency). */
-static void intel_connector_check_state(struct intel_connector *connector)
+static void intel_connector_verify_state(struct intel_connector *connector)
{
struct drm_crtc *crtc = connector->base.state->crtc;
@@ -12752,8 +12752,8 @@ static void intel_pipe_config_sanity_check(struct
drm_i915_private *dev_priv,
}
}
-static void check_wm_state(struct drm_crtc *crtc,
- struct drm_crtc_state *new_state)
+static void verify_wm_state(struct drm_crtc *crtc,
+ struct drm_crtc_state *new_state)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -12798,7 +12798,7 @@ static void check_wm_state(struct drm_crtc *crtc,
}
static void
-check_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
+verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
{
struct drm_connector *connector;
@@ -12809,7 +12809,7 @@ check_connector_state(struct drm_device *dev, struct
drm_crtc *crtc)
if (state->crtc != crtc)
continue;
- intel_connector_check_state(to_intel_connector(connector));
+ intel_connector_verify_state(to_intel_connector(connector));
I915_STATE_WARN(state->best_encoder != encoder,
"connector's atomic encoder doesn't match legacy
encoder\n");
@@ -12817,7 +12817,7 @@ check_connector_state(struct drm_device *dev, struct
drm_crtc *crtc)
}
static void
-check_encoder_state(struct drm_device *dev)
+verify_encoder_state(struct drm_device *dev)
{
struct intel_encoder *encoder;
struct intel_connector *connector;
@@ -12857,9 +12857,9 @@ check_encoder_state(struct drm_device *dev)
}
static void
-check_crtc_state(struct drm_crtc *crtc,
-struct drm_crtc_state *old_crtc_state,
-struct drm_crtc_state *new_crtc_state)
+verify_crtc_state(struct drm_crtc *crtc,
+ struct drm_crtc_state *old_crtc_state,
+ struct drm_crtc_state *new_crtc_state)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -12926,10 +12926,10 @@ check_crtc_state(struct drm_crtc *crtc,
}
static void
-check_single_dpll_state(struct drm_i915_private *dev_priv,
- struct intel_shared_dpll *pll,
- struct drm_crtc *crtc,
- struct drm_crtc_state *new_state)
+verify_single_dpll_state(struct drm_i915_private *dev_priv,
+struct intel_shared_dpll *pll,
+struct drm_crtc *crtc,
+struct drm_crtc_state *new_state)
{
struct intel_dpll_hw_state dpll_hw_state;
unsigned crtc_mask;
@@ -12981,16 +12981,16 @@ check_single_dpll_state(struct drm_i915_private
*dev_priv,
}
static void
-check_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
- struct drm_crtc_state *old_crtc_state,
- struct drm_crtc_state *new_crtc_state)
+verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
+struct drm_crtc_state *old_crtc_state,
+struct drm_crtc_state *new_crtc_state)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc_state *old_state =
to_intel_crtc_state(old_crtc_state);
struct intel_crtc_state *new_state =
to_intel_crtc_state(new_crtc_state);
if (new_state->shared_dpll)
- check_single_dpll_state(dev_priv, new_state->shared_dpll, crtc,
new_crtc_state);
+ verify_single_dpll_state(dev_priv, new_state->shared_dpll,
crtc, new_crtc_state);
if (old_state->shared_dpll &&
old_state->shared_dpll != new_state->shared_dpll) {
@@ -13007,7 +13007,7 @@ check_shared_dpll_state(struct drm_device *dev, struct
drm_crtc *crtc,
}
static void
-intel_modeset_check_crtc(struct drm_crtc *crtc,
+intel_modeset_verify_crtc(struct drm_crtc *crtc,
struct drm_crtc_state *old_sta
Re: [Intel-gfx] [PATCH i-g-t v3 5/6] tests/gem_scheduler: Add subtests to test batch priority behaviour
>
>
>-Original Message-
>From: Ceraolo Spurio, Daniele
>Sent: Thursday, March 17, 2016 8:58 AM
>To: Morton, Derek J ; intel-gfx@lists.freedesktop.org
>Subject: Re: [PATCH i-g-t v3 5/6] tests/gem_scheduler: Add subtests to test
>batch priority behaviour
>
>
>
>On 10/03/16 11:03, Derek Morton wrote:
>> Add subtests to test each ring to check batch buffers of a higher
>> priority will be executed before batch buffers of a lower priority.
>>
>> v2: Addressed review comments from Daniele Ceraolo Spurio
>>
>> Signed-off-by: Derek Morton
>> ---
>> tests/gem_scheduler.c | 53
>> +++
>> 1 file changed, 45 insertions(+), 8 deletions(-)
>>
>> diff --git a/tests/gem_scheduler.c b/tests/gem_scheduler.c index
>> 436440a..126ee97 100644
>> --- a/tests/gem_scheduler.c
>> +++ b/tests/gem_scheduler.c
>> @@ -39,7 +39,8 @@
>>
>> IGT_TEST_DESCRIPTION("Check scheduler behaviour. Basic tests ensure
>> independant "
>>"batch buffers of the same priority are executed in "
>> - "submission order. Read-read tests ensure "
>> + "submission order. Priority tests ensure higher
>> priority "
>> + "batch buffers are executed first. Read-read tests
>> ensure "
>>"batch buffers with a read dependency to the same
>> buffer "
>>"object do not block each other. Write-write
>> dependency "
>>"tests ensure batch buffers with a write dependency
>> to a "
>> @@ -136,11 +137,23 @@ static void init_context(int *fd, drm_intel_bufmgr
>> **bufmgr, int ringid)
>> intel_batchbuffer_free(noop_bb);
>> }
>>
>> -/* Basic test. Check batch buffers of the same priority and with no
>> dependencies
>> - * are executed in the order they are submitted.
>> +static void set_priority(int fd, int value) {
>> +struct local_i915_gem_context_param param;
>> +param.context = 0; /* Default context */
>> +param.size = 0;
>> +param.param = LOCAL_CONTEXT_PARAM_PRIORITY;
>> +param.value = (uint64_t)value;
>> +gem_context_set_param(fd, ¶m);
>> +}
>> +
>> +/* If 'priority' is 0, check batch buffers of the same priority and
>> +with
>> + * no dependencies are executed in the order they are submitted.
>> + * If 'priority' is set !0, check batch buffers of higher priority
>> +are
>> + * executed before batch buffers of lower priority.
>>*/
>> #define NBR_BASIC_FDs (3)
>> -static void run_test_basic(int in_flight, int ringid)
>> +static void run_test_basic(int in_flight, int ringid, int priority)
>> {
>> int fd[NBR_BASIC_FDs];
>> int loop;
>> @@ -160,6 +173,13 @@ static void run_test_basic(int in_flight, int ringid)
>> for(loop=0; loop < NBR_BASIC_FDs; loop++)
>> init_context(&(fd[loop]), &(bufmgr[loop]), ringid);
>>
>> +/* For high priority set priority of second context to overtake first
>> + * For low priority set priority of first context to be overtaxen by
>> second
>> + */
>> +if(priority > 0)
>> +set_priority(fd[2], priority);
>> +else if(priority < 0)
>> +set_priority(fd[1], priority);
>>
>> /* Create buffer objects */
>> delay_bo = create_and_check_bo(bufmgr[0], "delay bo"); @@ -209,9
>> +229,14 @@ static void run_test_basic(int in_flight, int ringid)
>> igt_assert_f(igt_compare_timestamps(delay_buf[2], ts1_buf[0]),
>> "Delay ts (0x%08" PRIx32 ") > TS1 ts (0x%08" PRIx32 ")\n",
>> delay_buf[2], ts1_buf[0]);
>> -igt_assert_f(igt_compare_timestamps(ts1_buf[0], ts2_buf[0]),
>> - "TS1 ts (0x%08" PRIx32 ") > TS2 ts (0x%08" PRIx32 ")\n",
>> - ts1_buf[0], ts2_buf[0]);
>> +if(priority)
>> +igt_assert_f(igt_compare_timestamps(ts2_buf[0], ts1_buf[0]),
>> + "TS2 ts (0x%08" PRIx32 ") > TS1 ts (0x%08" PRIx32
>> ")\n",
>> + ts2_buf[0], ts1_buf[0]);
>> +else
>> +igt_assert_f(igt_compare_timestamps(ts1_buf[0], ts2_buf[0]),
>> + "TS1 ts (0x%08" PRIx32 ") > TS2 ts (0x%08" PRIx32
>> ")\n",
>> + ts1_buf[0], ts2_buf[0]);
>>
>> /* Cleanup */
>> for(loop = 0; loop < in_flight; loop++) @@ -438,7 +463,19 @@
>> igt_main
>> for (loop=0; loop < NBR_RINGS; loop++)
>> igt_subtest_f("%s-basic", rings[loop].name) {
>> gem_require_ring(fd, rings[loop].id);
>> -run_test_basic(in_flight, rings[loop].id);
>> +run_test_basic(in_flight, rings[loop].id, false);
>> +}
>> +
>> +for (loop=0; loop < NBR_RINGS; loop++)
>> +igt_subtest_f("%s-priority-high", rings[loop].name) {
>> +gem_require_ring(fd, rings[loop].id);
>> +run_test_basic(in_flight, rings[loop].id, 1000);
>
>1000 is a very high pri
Re: [Intel-gfx] [intelddx] TearFree still status "Experimental support"?
On Thu, Mar 24, 2016 at 12:19 PM, Sedat Dilek wrote: > On Thu, Mar 24, 2016 at 11:56 AM, Sedat Dilek wrote: >> Hi Chris, >> >> is TearFree feature still "experimental" in current >> xf86-video-intel.git#master? >> It is enabled by default! >> >> [ configure-log ] >> ... >> xf86-video-intel 2.99.917 will be compiled with: >> Xorg Video ABI version: 15.0 (xorg-server-1.15.1) >> pixman version: pixman-1-0.30.2 >> Acceleration backends: none *sna uxa >> Additional debugging support? valgrind >> Support for Kernel Mode Setting? yes >> Support for legacy User Mode Setting (for i810)? yes >> Support for Direct Rendering Infrastructure: *DRI2 >> Support for Xv motion compensation (XvMC and libXvMC): yes >> Support for display hotplug notifications (udev): yes >> Build additional tools and utilities? xf86-video-intel-backlight-helper >> Experimental support: TearFree <--- XXX >> ... >> >> [ configure.ac ] >> ... >> AC_ARG_ENABLE(tear-free, >> AS_HELP_STRING([--enable-tear-free], >> [Enable use of TearFree by default [default=no]]), >> [TEARFREE="$enableval"], >> [TEARFREE="no"]) >> if test "x$TEARFREE" = "xyes"; then >> AC_DEFINE(TEARFREE,1,[Enable "TearFree" by default]) >> xp_msg="$xp_msg TearFree" <--- Line needs to be killed ??? >> fi >> ... >> if test -n "$xp_msg"; then >> echo " Experimental support:$xp_msg" >> fi >> ... >> >> Thanks. >> >> - Sedat - >> >> [1] >> https://cgit.freedesktop.org/xorg/driver/xf86-video-intel/tree/configure.ac#n742 >> [2] >> https://cgit.freedesktop.org/xorg/driver/xf86-video-intel/tree/configure.ac#n927 > > See attached patch. > Looks like I misread in configure.ac, TearFree is not enabled by default. [ configure.ac ] AC_ARG_ENABLE(tear-free, AS_HELP_STRING([--enable-tear-free], [Enable use of TearFree by default [default=no]]), [TEARFREE="$enableval"], [TEARFREE="no"]) if test "x$TEARFREE" = "xyes"; then AC_DEFINE(TEARFREE,1,[Enable "TearFree" by default]) xp_msg="$xp_msg TearFree" fi So forget this braino. - Sedat - [1] https://cgit.freedesktop.org/xorg/driver/xf86-video-intel/tree/configure.ac#n742 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] i915 4.5 bugfix backport and release management issue?
On Tue, Mar 29, 2016 at 6:16 PM, Andy Lutomirski wrote: > On Tue, Mar 29, 2016 at 12:49 AM, Andy Lutomirski wrote: >> On Tue, Mar 29, 2016 at 12:43 AM, Daniel Vetter >> wrote: >>> On Tue, Mar 29, 2016 at 4:39 AM, Andy Lutomirski >>> wrote: AFAICT something got rather screwed up in i915 land for 4.5. $ git log --oneline --grep='Pretend cursor is always on' v4.5 drivers/gpu/drm/i915/ e2e407dc093f drm/i915: Pretend cursor is always on for ILK-style WM calculations (v2) $ git log --oneline --grep='Pretend cursor is always on' v4.6-rc1 drivers/gpu/drm/i915/ e2e407dc093f drm/i915: Pretend cursor is always on for ILK-style WM calculations (v2) b2435692dbb7 drm/i915: Pretend cursor is always on for ILK-style WM calculations (v2) The two patches there are almost, but not quite, the same thing, which makes me wonder how they both ended up in Linus' tree without an obvious merge conflict. I have no idea what caused this. However, I think (on very little inspection, but it's consistent with problems I have with 4.5 on my laptop) that the first one is an *incorrect* fix for a regression in 4.5 and the second is a correct fix for the same regression. 4.6-rc1 seems okay. I reported the regression and everyone involved has known about it for weeks. Nonetheless, 4.5 final is busted. >>> >>> Quoting from e2e407dc093f >>> >>> "(cherry picked from commit b2435692dbb709d4c8ff3b2f2815c9b8423b72bb)" >>> >>> i.e. this is intentionally twice in the history. We started to soak >>> bugfixes in -next and then cherry pick them because we had too much >>> fun with things blowing up, and also too much fun with really messy >>> conflicts. It's not a botched patch in 4.5 or anything else nefarious >>> at all. >> >> Bah, sorry, I read it wrong. They have the same final state but they >> were on different bases. I somehow reversed this in my head and >> thought they had the same initial state and different final states. >> > > Also, sorry for the excessive diatribe. I plead sleepiness and > mis-reading of code. Thanks. We really appreciate friendly discussions here on intel-gfx, the technical challenges are hard enough as is. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] Updated drm-intel-testing
Hi all, New -testing cycle with cool stuff: - VBT code refactor for a clean split between parsing&using of firmware information (Jani) - untangle the pll computation code, and splitting up the monster i9xx_crtc_compute_clocks (Ander) - dsi support for bxt (Jani, Shashank Sharma and others) - color manager (i.e. de-gamma, color conversion matrix & gamma support) from Lionel Landwerlin - Vulkan hsw support in the command parser (Jordan Justen) - large-scale renaming of intel_engine_cs variables/parameters to avoid the epic ring vs. engine confusion introduced in gen8 (Tvrtko Ursulin) - few atomic patches from Maarten&Matt, big one is two-stage wm programming on ilk-bdw - refactor driver load and add infrastructure to inject load failures for testing, from Imre - various small things all over Happy testing! Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Rename GGTT init functions
On Tue, Mar 29, 2016 at 03:25:38PM +0100, Chris Wilson wrote: > On Tue, Mar 29, 2016 at 04:15:54PM +0300, Joonas Lahtinen wrote: > > On to, 2016-03-24 at 16:47 +0200, Joonas Lahtinen wrote: > > > Rename and document the GGTT init functions to give a better > > > idea of the context where they are called from. > > > > > > i915_gem_gtt_init => i915_ggtt_init_hw > > > i915_gem_init_global_gtt => i915_gem_init_ggtt > > > i915_global_gtt_cleanup => i915_ggtt_cleanup_hw > > > > > > Cc: Tvrtko Ursulin > > > Cc: Mika Kuoppala > > > Cc: Ville Syrjälä > > > Acked-by: Chris Wilson > > > > Chris, accidentally did not remove you A-b for v2. You can retake your > > position here. > > > > This is the best balance between general naming logic and consistency > > with ppgtt I could come up. How about I merge this? > > I don't have any better names to suggest, and the init_hw should help a > lot. Go for it. Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: fix deadlock on lid open
commit e2c8b8701e2d moved modeset locking inside resume/suspend
functions, but missed a code path only executed on lid close/open
on older hardware. The result was a deadlock when closing and
opening the lid without suspending on such hardware:
=
[ INFO: possible recursive locking detected ]
4.6.0-rc1 #385 Not tainted
-
kworker/0:3/88 is trying to acquire lock:
(&dev->mode_config.mutex){+.+.+.}, at: []
intel_display_resume+0x4a/0x12f [i915]
but task is already holding lock:
(&dev->mode_config.mutex){+.+.+.}, at: []
drm_modeset_lock_all+0x3e/0xa6 [drm]
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0
lock(&dev->mode_config.mutex);
lock(&dev->mode_config.mutex);
*** DEADLOCK ***
May be due to missing lock nesting notation
7 locks held by kworker/0:3/88:
#0: ("kacpi_notify"){.+}, at: []
process_one_work+0x14a/0x50b
#1: ((&dpc->work)#2){+.+.+.}, at: []
process_one_work+0x14a/0x50b
#2: ((acpi_lid_notifier).rwsem){.+}, at: []
__blocking_notifier_call_chain+0x34/0x65
#3: (&dev_priv->modeset_restore_lock){+.+.+.}, at: []
intel_lid_notify+0x3c/0xd9 [i915]
#4: (&dev->mode_config.mutex){+.+.+.}, at: []
drm_modeset_lock_all+0x3e/0xa6 [drm]
#5: (crtc_ww_class_acquire){+.+.+.}, at: []
drm_modeset_lock_all+0x48/0xa6 [drm]
#6: (crtc_ww_class_mutex){+.+.+.}, at: []
modeset_lock+0x13c/0x1cd [drm]
stack backtrace:
CPU: 0 PID: 88 Comm: kworker/0:3 Not tainted 4.6.0-rc1 #385
Hardware name: LENOVO 2776LEG/2776LEG, BIOS 6EET55WW (3.15 ) 12/19/2011
Workqueue: kacpi_notify acpi_os_execute_deferred
88022fd5f990 8124af06 825b39c0
825b39c0 88022fd5fa60 8108f547 88022fd5fa70
8108e817 880230236cc0 825b39c0
Call Trace:
[] dump_stack+0x67/0x90
[] __lock_acquire+0xdb5/0xf71
[] ? look_up_lock_class+0xbe/0x10a
[] lock_acquire+0x137/0x1cb
[] ? lock_acquire+0x137/0x1cb
[] ? intel_display_resume+0x4a/0x12f [i915]
[] mutex_lock_nested+0x7e/0x3a4
[] ? intel_display_resume+0x4a/0x12f [i915]
[] ? intel_display_resume+0x4a/0x12f [i915]
[] ? modeset_lock+0x13c/0x1cd [drm]
[] intel_display_resume+0x4a/0x12f [i915]
[] ? intel_display_resume+0x4a/0x12f [i915]
[] ? modeset_lock+0x13c/0x1cd [drm]
[] ? modeset_lock+0x13c/0x1cd [drm]
[] ? drm_modeset_lock+0x17/0x24 [drm]
[] ? drm_modeset_lock_all_ctx+0x87/0xa1 [drm]
[] intel_lid_notify+0xb0/0xd9 [i915]
[] notifier_call_chain+0x4a/0x6c
[] __blocking_notifier_call_chain+0x4d/0x65
[] blocking_notifier_call_chain+0x14/0x16
[] acpi_lid_send_state+0x83/0xad [button]
[] acpi_button_notify+0x41/0x132 [button]
[] acpi_device_notify+0x19/0x1b
[] acpi_ev_notify_dispatch+0x49/0x64
[] acpi_os_execute_deferred+0x14/0x20
[] process_one_work+0x265/0x50b
[] worker_thread+0x1fc/0x2dd
[] ? rescuer_thread+0x309/0x309
[] ? rescuer_thread+0x309/0x309
[] kthread+0xe0/0xe8
[] ? local_clock+0x19/0x22
[] ret_from_fork+0x22/0x40
[] ? kthread_create_on_node+0x1b5/0x1b5
Fixes: e2c8b8701e2d ("drm/i915: Use atomic helpers for suspend, v2.")
Cc: Maarten Lankhorst
Signed-off-by: Bjørn Mork
---
drivers/gpu/drm/i915/intel_lvds.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lvds.c
b/drivers/gpu/drm/i915/intel_lvds.c
index 30a8403a8f4f..cd9fe609aefb 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -478,11 +478,8 @@ static int intel_lid_notify(struct notifier_block *nb,
unsigned long val,
* and as part of the cleanup in the hw state restore we also redisable
* the vga plane.
*/
- if (!HAS_PCH_SPLIT(dev)) {
- drm_modeset_lock_all(dev);
+ if (!HAS_PCH_SPLIT(dev))
intel_display_resume(dev);
- drm_modeset_unlock_all(dev);
- }
dev_priv->modeset_restore = MODESET_DONE;
--
2.1.4
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[Intel-gfx] [PATCH] vgacon: dummy implementation for vgacon_text_force
This allows us to ditch a ton of ugly #ifdefs from a bunch of drm modeset
drivers.
v2: Make the dummy function actually return a sane value, spotted by
Ville.
v3: Because the patch is still in limbo there's no more drivers to
convert, noticed by Emil.
v4: Rebase once more, because hooray. I'll just go ahead an apply this
one later on to drm-misc.
Cc: Emil Velikov
Cc: Ville Syrjälä
Cc: Andrew Morton
Cc: Greg Kroah-Hartman
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 --
drivers/gpu/drm/ast/ast_drv.c | 2 --
drivers/gpu/drm/cirrus/cirrus_drv.c | 2 --
drivers/gpu/drm/i915/i915_drv.c | 2 --
drivers/gpu/drm/mgag200/mgag200_drv.c | 2 --
drivers/gpu/drm/nouveau/nouveau_drm.c | 2 --
drivers/gpu/drm/qxl/qxl_drv.c | 2 --
drivers/gpu/drm/radeon/radeon_drv.c | 2 --
drivers/gpu/drm/virtio/virtgpu_drv.c| 2 --
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 2 --
include/linux/console.h | 2 ++
11 files changed, 2 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index f1e17d60055a..93462aea9faa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -556,12 +556,10 @@ static struct pci_driver amdgpu_kms_pci_driver = {
static int __init amdgpu_init(void)
{
amdgpu_sync_init();
-#ifdef CONFIG_VGA_CONSOLE
if (vgacon_text_force()) {
DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
return -EINVAL;
}
-#endif
DRM_INFO("amdgpu kernel modesetting enabled.\n");
driver = &kms_driver;
pdriver = &amdgpu_kms_pci_driver;
diff --git a/drivers/gpu/drm/ast/ast_drv.c b/drivers/gpu/drm/ast/ast_drv.c
index 9a32d9dfdd26..fcd9c0714836 100644
--- a/drivers/gpu/drm/ast/ast_drv.c
+++ b/drivers/gpu/drm/ast/ast_drv.c
@@ -218,10 +218,8 @@ static struct drm_driver driver = {
static int __init ast_init(void)
{
-#ifdef CONFIG_VGA_CONSOLE
if (vgacon_text_force() && ast_modeset == -1)
return -EINVAL;
-#endif
if (ast_modeset == 0)
return -EINVAL;
diff --git a/drivers/gpu/drm/cirrus/cirrus_drv.c
b/drivers/gpu/drm/cirrus/cirrus_drv.c
index 7bc394ec9fb3..dc83f69da6f1 100644
--- a/drivers/gpu/drm/cirrus/cirrus_drv.c
+++ b/drivers/gpu/drm/cirrus/cirrus_drv.c
@@ -163,10 +163,8 @@ static struct pci_driver cirrus_pci_driver = {
static int __init cirrus_init(void)
{
-#ifdef CONFIG_VGA_CONSOLE
if (vgacon_text_force() && cirrus_modeset == -1)
return -EINVAL;
-#endif
if (cirrus_modeset == 0)
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f73b4f7b2d39..349e17cc8540 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1754,10 +1754,8 @@ static int __init i915_init(void)
if (i915.modeset == 0)
driver.driver_features &= ~DRIVER_MODESET;
-#ifdef CONFIG_VGA_CONSOLE
if (vgacon_text_force() && i915.modeset == -1)
driver.driver_features &= ~DRIVER_MODESET;
-#endif
if (!(driver.driver_features & DRIVER_MODESET)) {
/* Silently fail loading to not upset userspace. */
diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.c
b/drivers/gpu/drm/mgag200/mgag200_drv.c
index b0af77454d52..ebb470ff7200 100644
--- a/drivers/gpu/drm/mgag200/mgag200_drv.c
+++ b/drivers/gpu/drm/mgag200/mgag200_drv.c
@@ -116,10 +116,8 @@ static struct pci_driver mgag200_pci_driver = {
static int __init mgag200_init(void)
{
-#ifdef CONFIG_VGA_CONSOLE
if (vgacon_text_force() && mgag200_modeset == -1)
return -EINVAL;
-#endif
if (mgag200_modeset == 0)
return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c
b/drivers/gpu/drm/nouveau/nouveau_drm.c
index d06877d9c1ed..db5c7d0cc25c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -1083,10 +1083,8 @@ nouveau_drm_init(void)
nouveau_display_options();
if (nouveau_modeset == -1) {
-#ifdef CONFIG_VGA_CONSOLE
if (vgacon_text_force())
nouveau_modeset = 0;
-#endif
}
if (!nouveau_modeset)
diff --git a/drivers/gpu/drm/qxl/qxl_drv.c b/drivers/gpu/drm/qxl/qxl_drv.c
index 7307b07fe06b..dc9df5fe50ba 100644
--- a/drivers/gpu/drm/qxl/qxl_drv.c
+++ b/drivers/gpu/drm/qxl/qxl_drv.c
@@ -272,10 +272,8 @@ static struct drm_driver qxl_driver = {
static int __init qxl_init(void)
{
-#ifdef CONFIG_VGA_CONSOLE
if (vgacon_text_force() && qxl_modeset == -1)
return -EINVAL;
-#endif
if (qxl_modeset == 0)
return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c
b/drivers/gpu/drm/radeon/radeon_drv.c
index ccd4ad4ee592..5d44ed0d104a 100644
--- a/drivers/gpu/drm/radeon/radeon
[Intel-gfx] [PATCH] drm/i915: Remove PIPE_CONF_CHECK_I_ALT
And move the comment to the right macro. This was mixed up in
commit cfb23ed622d040619abb91e625fcba74d356b8a8
Author: Maarten Lankhorst
Date: Tue Jul 14 12:17:40 2015 +0200
drm/i915: Allow fuzzy matching in pipe_config_compare, v2
v2: Rebase.
Cc: Maarten Lankhorst
Cc: Daniel Stone
Acked-by: Maarten Lankhorst
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c | 22 +-
1 file changed, 5 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 29aa64be1f03..fec6392dfc02 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12569,6 +12569,11 @@ intel_pipe_config_compare(struct drm_device *dev,
ret = false; \
}
+/* This is required for BDW+ where there is only one set of registers for
+ * switching between high and low RR.
+ * This macro can be used whenever a comparison has to be made between one
+ * hw state and multiple sw state variables.
+ */
#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
if (!intel_compare_link_m_n(¤t_config->name, \
&pipe_config->name, adjust) && \
@@ -12596,22 +12601,6 @@ intel_pipe_config_compare(struct drm_device *dev,
ret = false; \
}
-/* This is required for BDW+ where there is only one set of registers for
- * switching between high and low RR.
- * This macro can be used whenever a comparison has to be made between one
- * hw state and multiple sw state variables.
- */
-#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
- if ((current_config->name != pipe_config->name) && \
- (current_config->alt_name != pipe_config->name)) { \
- INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
- "(expected %i or %i, found %i)\n", \
- current_config->name, \
- current_config->alt_name, \
- pipe_config->name); \
- ret = false; \
- }
-
#define PIPE_CONF_CHECK_FLAGS(name, mask) \
if ((current_config->name ^ pipe_config->name) & (mask)) { \
INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
@@ -12736,7 +12725,6 @@ intel_pipe_config_compare(struct drm_device *dev,
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
#undef PIPE_CONF_CHECK_P
-#undef PIPE_CONF_CHECK_I_ALT
#undef PIPE_CONF_CHECK_FLAGS
#undef PIPE_CONF_CHECK_CLOCK_FUZZY
#undef PIPE_CONF_QUIRK
--
2.8.0.rc3
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[Intel-gfx] [PATCH 04/10] drm/sysfs: Nuke TV/DVI property files
This goes all the way back to the original KMS commit aeons ago
commit f453ba0460742ad027ae0c4c7d61e62817b3e7ef
Author: Dave Airlie
Date: Fri Nov 7 14:05:41 2008 -0800
DRM: add mode setting support
But it seems to be completely unused. Only i915 and nouveau even
register these properties, and the corresponding DDX don't even look
at them. Also the sysfs files are read-only, so not useful to
configure anything.
I suspect that this was added with the goal to have read-only access
to all properties in sysfs, but we never followed through on that.
Also, that should be done in a more generic fashion.
Since it would be real work to fix up the locking (with atomic we're
now chasing pointers when reading properties) and it seems unused lets
just nuke this all. It's easier. Of course we'll keep the properties
themselves, those are still exposed through the KMS ioctls.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_sysfs.c | 156
1 file changed, 156 deletions(-)
diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
index 43875cb35691..fa7fadce8063 100644
--- a/drivers/gpu/drm/drm_sysfs.c
+++ b/drivers/gpu/drm/drm_sysfs.c
@@ -292,102 +292,6 @@ static ssize_t modes_show(struct device *device,
return written;
}
-static ssize_t tv_subconnector_show(struct device *device,
- struct device_attribute *attr,
- char *buf)
-{
- struct drm_connector *connector = to_drm_connector(device);
- struct drm_device *dev = connector->dev;
- struct drm_property *prop;
- uint64_t subconnector;
- int ret;
-
- prop = dev->mode_config.tv_subconnector_property;
- if (!prop) {
- DRM_ERROR("Unable to find subconnector property\n");
- return 0;
- }
-
- ret = drm_object_property_get_value(&connector->base, prop,
&subconnector);
- if (ret)
- return 0;
-
- return snprintf(buf, PAGE_SIZE, "%s",
- drm_get_tv_subconnector_name((int)subconnector));
-}
-
-static ssize_t tv_select_subconnector_show(struct device *device,
- struct device_attribute *attr,
- char *buf)
-{
- struct drm_connector *connector = to_drm_connector(device);
- struct drm_device *dev = connector->dev;
- struct drm_property *prop;
- uint64_t subconnector;
- int ret;
-
- prop = dev->mode_config.tv_select_subconnector_property;
- if (!prop) {
- DRM_ERROR("Unable to find select subconnector property\n");
- return 0;
- }
-
- ret = drm_object_property_get_value(&connector->base, prop,
&subconnector);
- if (ret)
- return 0;
-
- return snprintf(buf, PAGE_SIZE, "%s",
- drm_get_tv_select_name((int)subconnector));
-}
-
-static ssize_t dvii_subconnector_show(struct device *device,
- struct device_attribute *attr,
- char *buf)
-{
- struct drm_connector *connector = to_drm_connector(device);
- struct drm_device *dev = connector->dev;
- struct drm_property *prop;
- uint64_t subconnector;
- int ret;
-
- prop = dev->mode_config.dvi_i_subconnector_property;
- if (!prop) {
- DRM_ERROR("Unable to find subconnector property\n");
- return 0;
- }
-
- ret = drm_object_property_get_value(&connector->base, prop,
&subconnector);
- if (ret)
- return 0;
-
- return snprintf(buf, PAGE_SIZE, "%s",
- drm_get_dvi_i_subconnector_name((int)subconnector));
-}
-
-static ssize_t dvii_select_subconnector_show(struct device *device,
-struct device_attribute *attr,
-char *buf)
-{
- struct drm_connector *connector = to_drm_connector(device);
- struct drm_device *dev = connector->dev;
- struct drm_property *prop;
- uint64_t subconnector;
- int ret;
-
- prop = dev->mode_config.dvi_i_select_subconnector_property;
- if (!prop) {
- DRM_ERROR("Unable to find select subconnector property\n");
- return 0;
- }
-
- ret = drm_object_property_get_value(&connector->base, prop,
&subconnector);
- if (ret)
- return 0;
-
- return snprintf(buf, PAGE_SIZE, "%s",
- drm_get_dvi_i_select_name((int)subconnector));
-}
-
static DEVICE_ATTR_RW(status);
static DEVICE_ATTR_RO(enabled);
static DEVICE_ATTR_RO(dpms);
@@ -401,54 +305,6 @@ static struct attribute *connector_dev_attrs[] = {
NULL
};
-static DEVICE_ATTR_RO(tv_subconnector);
-static DEVICE_ATTR_RO(tv_select_subconnector);
-
-static struct attribute *connector_tv_dev_attr
[Intel-gfx] [PATCH 02/10] drm: Use dev->name as fallback for dev->unique
Lots of arm drivers get this wrong and for most arm boards this is the
right thing actually. And anyway with most loaders you want to chase
sysfs links anyway to figure out which dri device you want.
This will fix dmesg noise for rockchip and sti.
Cc: Ilia Mirkin
Reported-by: Ilia Mirkin
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_ioctl.c | 12 +---
drivers/gpu/drm/vgem/vgem_drv.c | 2 --
2 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 8ce2a0c59116..3ecd1368c23a 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -134,16 +134,14 @@ static int drm_set_busid(struct drm_device *dev, struct
drm_file *file_priv)
drm_unset_busid(dev, master);
return ret;
}
- } else {
- if (WARN(dev->unique == NULL,
-"No drm_driver.set_busid() implementation provided by "
-"%ps. Use drm_dev_set_unique() to set the unique "
-"name explicitly.", dev->driver))
- return -EINVAL;
-
+ } else if (dev->unique) {
master->unique = kstrdup(dev->unique, GFP_KERNEL);
if (master->unique)
master->unique_len = strlen(dev->unique);
+ } else {
+ master->unique = kstrdup(dev->driver->name, GFP_KERNEL);
+ if (master->unique)
+ master->unique_len = strlen(dev->driver->name);
}
return 0;
diff --git a/drivers/gpu/drm/vgem/vgem_drv.c b/drivers/gpu/drm/vgem/vgem_drv.c
index ae4de36d1d83..d61a547fa3c9 100644
--- a/drivers/gpu/drm/vgem/vgem_drv.c
+++ b/drivers/gpu/drm/vgem/vgem_drv.c
@@ -260,8 +260,6 @@ static int __init vgem_init(void)
goto out;
}
- drm_dev_set_unique(vgem_device, "vgem");
-
ret = drm_dev_register(vgem_device, 0);
if (ret)
--
2.8.0.rc3
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[Intel-gfx] [PATCH 03/10] drm/sysfs: Annote lockless show functions with READ_ONCE
For documentation and paranoia.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_sysfs.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
index d503f8e8c2d1..43875cb35691 100644
--- a/drivers/gpu/drm/drm_sysfs.c
+++ b/drivers/gpu/drm/drm_sysfs.c
@@ -208,9 +208,12 @@ static ssize_t status_show(struct device *device,
char *buf)
{
struct drm_connector *connector = to_drm_connector(device);
+ enum drm_connector_status status;
+
+ status = READ_ONCE(connector->status);
return snprintf(buf, PAGE_SIZE, "%s\n",
- drm_get_connector_status_name(connector->status));
+ drm_get_connector_status_name(status));
}
static ssize_t dpms_show(struct device *device,
@@ -231,9 +234,11 @@ static ssize_t enabled_show(struct device *device,
char *buf)
{
struct drm_connector *connector = to_drm_connector(device);
+ bool enabled;
+
+ enabled = READ_ONCE(connector->encoder);
- return snprintf(buf, PAGE_SIZE, "%s\n", connector->encoder ? "enabled" :
- "disabled");
+ return snprintf(buf, PAGE_SIZE, enabled ? "enabled\n" : "disabled\n");
}
static ssize_t edid_show(struct file *filp, struct kobject *kobj,
--
2.8.0.rc3
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[Intel-gfx] [PATCH 01/10] drm/ttm: Remove TTM_HAS_AGP
It tries to do fancy things with excluding agp support if ttm is
built-in, but agp isn't. Instead just express this depency like drm
does and use CONFIG_AGP everywhere.
Also use the neat Makefile magic to make the entire ttm_agp_backend
file optional.
v2: Use IS_ENABLED(CONFIG_AGP) as suggested by Ville
Cc: Ville Syrjälä
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/Kconfig | 1 +
drivers/gpu/drm/ttm/Makefile | 3 ++-
drivers/gpu/drm/ttm/ttm_agp_backend.c| 3 ---
drivers/gpu/drm/ttm/ttm_page_alloc.c | 8
drivers/gpu/drm/ttm/ttm_page_alloc_dma.c | 8
include/drm/ttm/ttm_bo_driver.h | 3 +--
6 files changed, 12 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index f2a74d0b68ae..7c9fc451f1aa 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -83,6 +83,7 @@ config DRM_LOAD_EDID_FIRMWARE
config DRM_TTM
tristate
depends on DRM
+ depends on (AGP || AGP=n)
help
GPU memory management subsystem for devices with multiple
GPU memory types. Will be enabled automatically if a device driver
diff --git a/drivers/gpu/drm/ttm/Makefile b/drivers/gpu/drm/ttm/Makefile
index b433b9f040c9..f92325800f8a 100644
--- a/drivers/gpu/drm/ttm/Makefile
+++ b/drivers/gpu/drm/ttm/Makefile
@@ -2,9 +2,10 @@
# Makefile for the drm device driver. This driver provides support for the
ccflags-y := -Iinclude/drm
-ttm-y := ttm_agp_backend.o ttm_memory.o ttm_tt.o ttm_bo.o \
+ttm-y := ttm_memory.o ttm_tt.o ttm_bo.o \
ttm_bo_util.o ttm_bo_vm.o ttm_module.o \
ttm_object.o ttm_lock.o ttm_execbuf_util.o ttm_page_alloc.o \
ttm_bo_manager.o ttm_page_alloc_dma.o
+ttm-$(CONFIG_AGP) += ttm_agp_backend.o
obj-$(CONFIG_DRM_TTM) += ttm.o
diff --git a/drivers/gpu/drm/ttm/ttm_agp_backend.c
b/drivers/gpu/drm/ttm/ttm_agp_backend.c
index 764be36397fd..028ab6007873 100644
--- a/drivers/gpu/drm/ttm/ttm_agp_backend.c
+++ b/drivers/gpu/drm/ttm/ttm_agp_backend.c
@@ -34,7 +34,6 @@
#include
#include
#include
-#ifdef TTM_HAS_AGP
#include
#include
#include
@@ -148,5 +147,3 @@ void ttm_agp_tt_unpopulate(struct ttm_tt *ttm)
ttm_pool_unpopulate(ttm);
}
EXPORT_SYMBOL(ttm_agp_tt_unpopulate);
-
-#endif
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c
b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index 025c429050c0..a37de5db5731 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -48,7 +48,7 @@
#include
#include
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
#include
#endif
@@ -219,7 +219,7 @@ static struct ttm_pool_manager *_manager;
#ifndef CONFIG_X86
static int set_pages_array_wb(struct page **pages, int addrinarray)
{
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
int i;
for (i = 0; i < addrinarray; i++)
@@ -230,7 +230,7 @@ static int set_pages_array_wb(struct page **pages, int
addrinarray)
static int set_pages_array_wc(struct page **pages, int addrinarray)
{
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
int i;
for (i = 0; i < addrinarray; i++)
@@ -241,7 +241,7 @@ static int set_pages_array_wc(struct page **pages, int
addrinarray)
static int set_pages_array_uc(struct page **pages, int addrinarray)
{
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
int i;
for (i = 0; i < addrinarray; i++)
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
index 624d941aaad1..bef9f6feb635 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
@@ -50,7 +50,7 @@
#include
#include
#include
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
#include
#endif
@@ -271,7 +271,7 @@ static struct kobj_type ttm_pool_kobj_type = {
#ifndef CONFIG_X86
static int set_pages_array_wb(struct page **pages, int addrinarray)
{
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
int i;
for (i = 0; i < addrinarray; i++)
@@ -282,7 +282,7 @@ static int set_pages_array_wb(struct page **pages, int
addrinarray)
static int set_pages_array_wc(struct page **pages, int addrinarray)
{
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
int i;
for (i = 0; i < addrinarray; i++)
@@ -293,7 +293,7 @@ static int set_pages_array_wc(struct page **pages, int
addrinarray)
static int set_pages_array_uc(struct page **pages, int addrinarray)
{
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
int i;
for (i = 0; i < addrinarray; i++)
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index 3d4bf08aa21f..ff544e3e37a7 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -1030,8 +1030,7 @@ extern pgprot_t ttm_io_prot(uint32_t caching_flags,
pgprot_t tmp);
extern const struct ttm_mem_type_manager_func ttm_bo_manager_func;
-#if (defined(CONFIG_AGP) || (defined(CONFIG_AGP
[Intel-gfx] [PATCH 00/10] Another shot at cruft removal
Hi all, Found this pile of cruft removal patches hiding. Bunch of them have been posted already a few times, most of them are variations of the "hide dev->struct_mutex" theme. Feedback and review highly welcome, I'd like to get them all in. Thanks, Daniel Daniel Vetter (10): drm/ttm: Remove TTM_HAS_AGP drm: Use dev->name as fallback for dev->unique drm/sysfs: Annote lockless show functions with READ_ONCE drm/sysfs: Nuke TV/DVI property files drm: Give drm_agp_clear drm_legacy_ prefix drm: Put legacy lastclose work into drm_legacy_dev_reinit drm: Move drm_getmap into drm_bufs.c and give it a legacy prefix drm: Forbid legacy MAP functions for DRIVER_MODESET drm: Push struct_mutex into ->master_destroy drm: Hide master MAP cleanup in drm_bufs.c drivers/gpu/drm/Kconfig | 1 + drivers/gpu/drm/drm_agpsupport.c | 4 +- drivers/gpu/drm/drm_bufs.c | 92 - drivers/gpu/drm/drm_drv.c| 10 +- drivers/gpu/drm/drm_fops.c | 42 drivers/gpu/drm/drm_internal.h | 2 +- drivers/gpu/drm/drm_ioctl.c | 66 ++-- drivers/gpu/drm/drm_legacy.h | 2 + drivers/gpu/drm/drm_pci.c| 2 +- drivers/gpu/drm/drm_sysfs.c | 167 ++- drivers/gpu/drm/ttm/Makefile | 3 +- drivers/gpu/drm/ttm/ttm_agp_backend.c| 3 - drivers/gpu/drm/ttm/ttm_page_alloc.c | 8 +- drivers/gpu/drm/ttm/ttm_page_alloc_dma.c | 8 +- drivers/gpu/drm/vgem/vgem_drv.c | 2 - include/drm/drm_agpsupport.h | 4 +- include/drm/drm_legacy.h | 4 +- include/drm/ttm/ttm_bo_driver.h | 3 +- 18 files changed, 145 insertions(+), 278 deletions(-) -- 2.8.0.rc3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/10] drm: Push struct_mutex into ->master_destroy
Only two drivers implement this hook. vmwgfx (which doesn't need it
really) and legacy radeon (which since v1 has been nuked, yay).
v1: Rebase over radeon ums removal.
Cc: Thomas Hellstrom
Cc: Alex Deucher
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 167c8d3d4a31..845aa644c890 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -113,10 +113,10 @@ static void drm_master_destroy(struct kref *kref)
struct drm_device *dev = master->minor->dev;
struct drm_map_list *r_list, *list_temp;
- mutex_lock(&dev->struct_mutex);
if (dev->driver->master_destroy)
dev->driver->master_destroy(dev, master);
+ mutex_lock(&dev->struct_mutex);
list_for_each_entry_safe(r_list, list_temp, &dev->maplist, head) {
if (r_list->master == master) {
drm_legacy_rmmap_locked(dev, r_list->map);
--
2.8.0.rc3
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[Intel-gfx] [PATCH 10/10] drm: Hide master MAP cleanup in drm_bufs.c
And again make sure it's a no-op for modern drivers, again with the
exception of nouveau. Another case of dev->struct_mutex gone for
modern drivers!
v2: Also add a DRIVER_* check like for all other maps functions to
really short-circuit the code. And give drm_legacy_rmmap used by the
dev unregister code the same treatment.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_bufs.c | 28
drivers/gpu/drm/drm_drv.c | 10 +-
include/drm/drm_legacy.h | 4 +++-
3 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
index e8a12a4fd400..5a51633da033 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -542,18 +542,38 @@ int drm_legacy_rmmap_locked(struct drm_device *dev,
struct drm_local_map *map)
}
EXPORT_SYMBOL(drm_legacy_rmmap_locked);
-int drm_legacy_rmmap(struct drm_device *dev, struct drm_local_map *map)
+void drm_legacy_rmmap(struct drm_device *dev, struct drm_local_map *map)
{
- int ret;
+ if (!drm_core_check_feature(dev, DRIVER_KMS_LEGACY_CONTEXT) &&
+ drm_core_check_feature(dev, DRIVER_MODESET))
+ return;
mutex_lock(&dev->struct_mutex);
- ret = drm_legacy_rmmap_locked(dev, map);
+ drm_legacy_rmmap_locked(dev, map);
mutex_unlock(&dev->struct_mutex);
- return ret;
+ return;
}
EXPORT_SYMBOL(drm_legacy_rmmap);
+void drm_legacy_master_rmmaps(struct drm_device *dev, struct drm_master
*master)
+{
+ struct drm_map_list *r_list, *list_temp;
+
+ if (!drm_core_check_feature(dev, DRIVER_KMS_LEGACY_CONTEXT) &&
+ drm_core_check_feature(dev, DRIVER_MODESET))
+ return;
+
+ mutex_lock(&dev->struct_mutex);
+ list_for_each_entry_safe(r_list, list_temp, &dev->maplist, head) {
+ if (r_list->master == master) {
+ drm_legacy_rmmap_locked(dev, r_list->map);
+ r_list = NULL;
+ }
+ }
+ mutex_unlock(&dev->struct_mutex);
+}
+
/* The rmmap ioctl appears to be unnecessary. All mappings are torn down on
* the last close of the device, and this is necessary for cleanup when things
* exit uncleanly. Therefore, having userland manually remove mappings seems
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 845aa644c890..4bd8ec529060 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -111,19 +111,11 @@ static void drm_master_destroy(struct kref *kref)
{
struct drm_master *master = container_of(kref, struct drm_master,
refcount);
struct drm_device *dev = master->minor->dev;
- struct drm_map_list *r_list, *list_temp;
if (dev->driver->master_destroy)
dev->driver->master_destroy(dev, master);
- mutex_lock(&dev->struct_mutex);
- list_for_each_entry_safe(r_list, list_temp, &dev->maplist, head) {
- if (r_list->master == master) {
- drm_legacy_rmmap_locked(dev, r_list->map);
- r_list = NULL;
- }
- }
- mutex_unlock(&dev->struct_mutex);
+ drm_legacy_master_rmmaps(dev, master);
idr_destroy(&master->magic_map);
kfree(master->unique);
diff --git a/include/drm/drm_legacy.h b/include/drm/drm_legacy.h
index 3e698038dc7b..a5ef2c7e40f8 100644
--- a/include/drm/drm_legacy.h
+++ b/include/drm/drm_legacy.h
@@ -154,8 +154,10 @@ struct drm_map_list {
int drm_legacy_addmap(struct drm_device *d, resource_size_t offset,
unsigned int size, enum drm_map_type type,
enum drm_map_flags flags, struct drm_local_map **map_p);
-int drm_legacy_rmmap(struct drm_device *d, struct drm_local_map *map);
+void drm_legacy_rmmap(struct drm_device *d, struct drm_local_map *map);
int drm_legacy_rmmap_locked(struct drm_device *d, struct drm_local_map *map);
+void drm_legacy_master_rmmaps(struct drm_device *dev,
+ struct drm_master *master);
struct drm_local_map *drm_legacy_getsarea(struct drm_device *dev);
int drm_legacy_mmap(struct file *filp, struct vm_area_struct *vma);
--
2.8.0.rc3
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[Intel-gfx] [PATCH 07/10] drm: Move drm_getmap into drm_bufs.c and give it a legacy prefix
It belongs right next to the addmap and rmmap functions really. And
for OCD consistency name it drm_legacy_getmap_ioctl.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_bufs.c | 52 ++
drivers/gpu/drm/drm_ioctl.c | 54 +---
drivers/gpu/drm/drm_legacy.h | 2 ++
3 files changed, 55 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
index f1a204d253cc..d92db7007f62 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -416,6 +416,58 @@ int drm_legacy_addmap_ioctl(struct drm_device *dev, void
*data,
return 0;
}
+/*
+ * Get a mapping information.
+ *
+ * \param inode device inode.
+ * \param file_priv DRM file private.
+ * \param cmd command.
+ * \param arg user argument, pointing to a drm_map structure.
+ *
+ * \return zero on success or a negative number on failure.
+ *
+ * Searches for the mapping with the specified offset and copies its
information
+ * into userspace
+ */
+int drm_legacy_getmap_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ struct drm_map *map = data;
+ struct drm_map_list *r_list = NULL;
+ struct list_head *list;
+ int idx;
+ int i;
+
+ idx = map->offset;
+ if (idx < 0)
+ return -EINVAL;
+
+ i = 0;
+ mutex_lock(&dev->struct_mutex);
+ list_for_each(list, &dev->maplist) {
+ if (i == idx) {
+ r_list = list_entry(list, struct drm_map_list, head);
+ break;
+ }
+ i++;
+ }
+ if (!r_list || !r_list->map) {
+ mutex_unlock(&dev->struct_mutex);
+ return -EINVAL;
+ }
+
+ map->offset = r_list->map->offset;
+ map->size = r_list->map->size;
+ map->type = r_list->map->type;
+ map->flags = r_list->map->flags;
+ map->handle = (void *)(unsigned long) r_list->user_token;
+ map->mtrr = arch_phys_wc_index(r_list->map->mtrr);
+
+ mutex_unlock(&dev->struct_mutex);
+
+ return 0;
+}
+
/**
* Remove a map private from list and deallocate resources if the mapping
* isn't in use.
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 3ecd1368c23a..24b941c3b561 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -148,58 +148,6 @@ static int drm_set_busid(struct drm_device *dev, struct
drm_file *file_priv)
}
/*
- * Get a mapping information.
- *
- * \param inode device inode.
- * \param file_priv DRM file private.
- * \param cmd command.
- * \param arg user argument, pointing to a drm_map structure.
- *
- * \return zero on success or a negative number on failure.
- *
- * Searches for the mapping with the specified offset and copies its
information
- * into userspace
- */
-static int drm_getmap(struct drm_device *dev, void *data,
- struct drm_file *file_priv)
-{
- struct drm_map *map = data;
- struct drm_map_list *r_list = NULL;
- struct list_head *list;
- int idx;
- int i;
-
- idx = map->offset;
- if (idx < 0)
- return -EINVAL;
-
- i = 0;
- mutex_lock(&dev->struct_mutex);
- list_for_each(list, &dev->maplist) {
- if (i == idx) {
- r_list = list_entry(list, struct drm_map_list, head);
- break;
- }
- i++;
- }
- if (!r_list || !r_list->map) {
- mutex_unlock(&dev->struct_mutex);
- return -EINVAL;
- }
-
- map->offset = r_list->map->offset;
- map->size = r_list->map->size;
- map->type = r_list->map->type;
- map->flags = r_list->map->flags;
- map->handle = (void *)(unsigned long) r_list->user_token;
- map->mtrr = arch_phys_wc_index(r_list->map->mtrr);
-
- mutex_unlock(&dev->struct_mutex);
-
- return 0;
-}
-
-/*
* Get client information.
*
* \param inode device inode.
@@ -556,7 +504,7 @@ static const struct drm_ioctl_desc drm_ioctls[] = {
DRM_IOCTL_DEF(DRM_IOCTL_GET_UNIQUE, drm_getunique, 0),
DRM_IOCTL_DEF(DRM_IOCTL_GET_MAGIC, drm_getmagic, 0),
DRM_IOCTL_DEF(DRM_IOCTL_IRQ_BUSID, drm_irq_by_busid,
DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF(DRM_IOCTL_GET_MAP, drm_getmap, DRM_UNLOCKED),
+ DRM_IOCTL_DEF(DRM_IOCTL_GET_MAP, drm_legacy_getmap_ioctl, DRM_UNLOCKED),
DRM_IOCTL_DEF(DRM_IOCTL_GET_CLIENT, drm_getclient, DRM_UNLOCKED),
DRM_IOCTL_DEF(DRM_IOCTL_GET_STATS, drm_getstats, DRM_UNLOCKED),
DRM_IOCTL_DEF(DRM_IOCTL_GET_CAP, drm_getcap,
DRM_UNLOCKED|DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/drm_legacy.h b/drivers/gpu/drm/drm_legacy.h
index 9b731786e4db..d3b6ee357a2b 100644
--- a/drivers/gpu/drm/drm_legacy.h
+++ b/drivers/gpu/drm/drm_legacy.h
@@ -63,6 +63,8 @@ int drm_
[Intel-gfx] [PATCH 06/10] drm: Put legacy lastclose work into drm_legacy_dev_reinit
Except for the ->lasclose driver callback evrything in drm_lastclose()
is all legacy cruft and can be hidden. Which means another
dev->struct_mutex site disappears entirely for modern drivers!
Also while at it change the return value of drm_lastclose to void
since it will always succeed. No one checks the return value of
close() anyway, ever.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_fops.c | 42 +++---
drivers/gpu/drm/drm_internal.h | 2 +-
include/drm/drm_agpsupport.h | 2 +-
3 files changed, 21 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
index 7b5a13cda7a6..c3d0aaac0669 100644
--- a/drivers/gpu/drm/drm_fops.c
+++ b/drivers/gpu/drm/drm_fops.c
@@ -381,14 +381,26 @@ static void drm_events_release(struct drm_file *file_priv)
*/
static void drm_legacy_dev_reinit(struct drm_device *dev)
{
- if (drm_core_check_feature(dev, DRIVER_MODESET))
- return;
+ if (dev->irq_enabled)
+ drm_irq_uninstall(dev);
+
+ mutex_lock(&dev->struct_mutex);
+
+ drm_legacy_agp_clear(dev);
+
+ drm_legacy_sg_cleanup(dev);
+ drm_legacy_vma_flush(dev);
+ drm_legacy_dma_takedown(dev);
+
+ mutex_unlock(&dev->struct_mutex);
dev->sigdata.lock = NULL;
dev->context_flag = 0;
dev->last_context = 0;
dev->if_version = 0;
+
+ DRM_DEBUG("lastclose completed\n");
}
/*
@@ -400,7 +412,7 @@ static void drm_legacy_dev_reinit(struct drm_device *dev)
*
* \sa drm_device
*/
-int drm_lastclose(struct drm_device * dev)
+void drm_lastclose(struct drm_device * dev)
{
DRM_DEBUG("\n");
@@ -408,23 +420,8 @@ int drm_lastclose(struct drm_device * dev)
dev->driver->lastclose(dev);
DRM_DEBUG("driver lastclose completed\n");
- if (dev->irq_enabled && !drm_core_check_feature(dev, DRIVER_MODESET))
- drm_irq_uninstall(dev);
-
- mutex_lock(&dev->struct_mutex);
-
- drm_legacy_agp_clear(dev);
-
- drm_legacy_sg_cleanup(dev);
- drm_legacy_vma_flush(dev);
- drm_legacy_dma_takedown(dev);
-
- mutex_unlock(&dev->struct_mutex);
-
- drm_legacy_dev_reinit(dev);
-
- DRM_DEBUG("lastclose completed\n");
- return 0;
+ if (!drm_core_check_feature(dev, DRIVER_MODESET))
+ drm_legacy_dev_reinit(dev);
}
/**
@@ -445,7 +442,6 @@ int drm_release(struct inode *inode, struct file *filp)
struct drm_file *file_priv = filp->private_data;
struct drm_minor *minor = file_priv->minor;
struct drm_device *dev = minor->dev;
- int retcode = 0;
mutex_lock(&drm_global_mutex);
@@ -538,7 +534,7 @@ int drm_release(struct inode *inode, struct file *filp)
*/
if (!--dev->open_count) {
- retcode = drm_lastclose(dev);
+ drm_lastclose(dev);
if (drm_device_is_unplugged(dev))
drm_put_dev(dev);
}
@@ -546,7 +542,7 @@ int drm_release(struct inode *inode, struct file *filp)
drm_minor_release(minor);
- return retcode;
+ return 0;
}
EXPORT_SYMBOL(drm_release);
diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h
index 43cbda3306ac..c81ff4769e7b 100644
--- a/drivers/gpu/drm/drm_internal.h
+++ b/drivers/gpu/drm/drm_internal.h
@@ -26,7 +26,7 @@ extern unsigned int drm_timestamp_monotonic;
/* drm_fops.c */
extern struct mutex drm_global_mutex;
-int drm_lastclose(struct drm_device *dev);
+void drm_lastclose(struct drm_device *dev);
/* drm_pci.c */
int drm_pci_set_unique(struct drm_device *dev,
diff --git a/include/drm/drm_agpsupport.h b/include/drm/drm_agpsupport.h
index e134e9ca422b..b2d912670a7f 100644
--- a/include/drm/drm_agpsupport.h
+++ b/include/drm/drm_agpsupport.h
@@ -93,7 +93,7 @@ static inline struct drm_agp_head *drm_agp_init(struct
drm_device *dev)
return NULL;
}
-static inline void drm_agp_clear(struct drm_device *dev)
+static inline void drm_legacy_agp_clear(struct drm_device *dev)
{
}
--
2.8.0.rc3
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[Intel-gfx] [PATCH 08/10] drm: Forbid legacy MAP functions for DRIVER_MODESET
Like in
commit 0e975980d435d58df2d430d688b8c18778b42218
Author: Peter Antoine
Date: Tue Jun 23 08:18:49 2015 +0100
drm: Turn off Legacy Context Functions
we need to again make an exception for nouveau, but everyone else
really doesn't need this.
Cc: Peter Antoine
Cc: Ben Skeggs
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_bufs.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
index d92db7007f62..e8a12a4fd400 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -396,6 +396,10 @@ int drm_legacy_addmap_ioctl(struct drm_device *dev, void
*data,
if (!(capable(CAP_SYS_ADMIN) || map->type == _DRM_AGP || map->type ==
_DRM_SHM))
return -EPERM;
+ if (!drm_core_check_feature(dev, DRIVER_KMS_LEGACY_CONTEXT) &&
+ drm_core_check_feature(dev, DRIVER_MODESET))
+ return -EINVAL;
+
err = drm_addmap_core(dev, map->offset, map->size, map->type,
map->flags, &maplist);
@@ -438,6 +442,10 @@ int drm_legacy_getmap_ioctl(struct drm_device *dev, void
*data,
int idx;
int i;
+ if (!drm_core_check_feature(dev, DRIVER_KMS_LEGACY_CONTEXT) &&
+ drm_core_check_feature(dev, DRIVER_MODESET))
+ return -EINVAL;
+
idx = map->offset;
if (idx < 0)
return -EINVAL;
@@ -569,6 +577,10 @@ int drm_legacy_rmmap_ioctl(struct drm_device *dev, void
*data,
struct drm_map_list *r_list;
int ret;
+ if (!drm_core_check_feature(dev, DRIVER_KMS_LEGACY_CONTEXT) &&
+ drm_core_check_feature(dev, DRIVER_MODESET))
+ return -EINVAL;
+
mutex_lock(&dev->struct_mutex);
list_for_each_entry(r_list, &dev->maplist, head) {
if (r_list->map &&
--
2.8.0.rc3
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[Intel-gfx] [PATCH 05/10] drm: Give drm_agp_clear drm_legacy_ prefix
It has a DRIVER_MODESET check to sure make it's not creating havoc
for drm drivers. Make that clear in the name too.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_agpsupport.c | 4 ++--
drivers/gpu/drm/drm_fops.c | 2 +-
drivers/gpu/drm/drm_pci.c| 2 +-
include/drm/drm_agpsupport.h | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/drm_agpsupport.c b/drivers/gpu/drm/drm_agpsupport.c
index a10ea6aec629..605bd243fb36 100644
--- a/drivers/gpu/drm/drm_agpsupport.c
+++ b/drivers/gpu/drm/drm_agpsupport.c
@@ -423,7 +423,7 @@ struct drm_agp_head *drm_agp_init(struct drm_device *dev)
}
/**
- * drm_agp_clear - Clear AGP resource list
+ * drm_legacy_agp_clear - Clear AGP resource list
* @dev: DRM device
*
* Iterate over all AGP resources and remove them. But keep the AGP head
@@ -434,7 +434,7 @@ struct drm_agp_head *drm_agp_init(struct drm_device *dev)
* resources from getting destroyed. Drivers are responsible of cleaning them
up
* during device shutdown.
*/
-void drm_agp_clear(struct drm_device *dev)
+void drm_legacy_agp_clear(struct drm_device *dev)
{
struct drm_agp_mem *entry, *tempe;
diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
index aeef58ed359b..7b5a13cda7a6 100644
--- a/drivers/gpu/drm/drm_fops.c
+++ b/drivers/gpu/drm/drm_fops.c
@@ -413,7 +413,7 @@ int drm_lastclose(struct drm_device * dev)
mutex_lock(&dev->struct_mutex);
- drm_agp_clear(dev);
+ drm_legacy_agp_clear(dev);
drm_legacy_sg_cleanup(dev);
drm_legacy_vma_flush(dev);
diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
index a1fff1179a97..29d5a548d07a 100644
--- a/drivers/gpu/drm/drm_pci.c
+++ b/drivers/gpu/drm/drm_pci.c
@@ -250,7 +250,7 @@ void drm_pci_agp_destroy(struct drm_device *dev)
{
if (dev->agp) {
arch_phys_wc_del(dev->agp->agp_mtrr);
- drm_agp_clear(dev);
+ drm_legacy_agp_clear(dev);
kfree(dev->agp);
dev->agp = NULL;
}
diff --git a/include/drm/drm_agpsupport.h b/include/drm/drm_agpsupport.h
index 193ef19dfc5c..e134e9ca422b 100644
--- a/include/drm/drm_agpsupport.h
+++ b/include/drm/drm_agpsupport.h
@@ -37,7 +37,7 @@ struct agp_memory *drm_agp_bind_pages(struct drm_device *dev,
uint32_t type);
struct drm_agp_head *drm_agp_init(struct drm_device *dev);
-void drm_agp_clear(struct drm_device *dev);
+void drm_legacy_agp_clear(struct drm_device *dev);
int drm_agp_acquire(struct drm_device *dev);
int drm_agp_acquire_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
--
2.8.0.rc3
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[Intel-gfx] [PATCH 02/10] drm/fb-helper: Remove dead code in setcolreg
DRM fbdev emulation only supports pallete_color with depth == 8, and
truecolor with depth > 8. Handling depth == 16 for palettes is hence
dead code, let's remove it.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_fb_helper.c | 33 ++---
1 file changed, 2 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 855108e6e1bd..39f9b8a41843 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -969,7 +969,6 @@ static int setcolreg(struct drm_crtc *crtc, u16 red, u16
green,
{
struct drm_fb_helper *fb_helper = info->par;
struct drm_framebuffer *fb = fb_helper->fb;
- int pindex;
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
u32 *palette;
@@ -1001,38 +1000,10 @@ static int setcolreg(struct drm_crtc *crtc, u16 red,
u16 green,
!fb_helper->funcs->gamma_get))
return -EINVAL;
- pindex = regno;
+ WARN_ON(fb->bits_per_pixel != 8);
- if (fb->bits_per_pixel == 16) {
- pindex = regno << 3;
+ fb_helper->funcs->gamma_set(crtc, red, green, blue, regno);
- if (fb->depth == 16 && regno > 63)
- return -EINVAL;
- if (fb->depth == 15 && regno > 31)
- return -EINVAL;
-
- if (fb->depth == 16) {
- u16 r, g, b;
- int i;
- if (regno < 32) {
- for (i = 0; i < 8; i++)
- fb_helper->funcs->gamma_set(crtc, red,
- green, blue, pindex + i);
- }
-
- fb_helper->funcs->gamma_get(crtc, &r,
- &g, &b,
- pindex >> 1);
-
- for (i = 0; i < 4; i++)
- fb_helper->funcs->gamma_set(crtc, r,
- green, b,
- (pindex >> 1) + i);
- }
- }
-
- if (fb->depth != 16)
- fb_helper->funcs->gamma_set(crtc, red, green, blue, pindex);
return 0;
}
--
2.8.0.rc3
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[Intel-gfx] [PATCH 01/10] drm: Initialize a linear gamma table by default
Code stolen from gma500.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_crtc.c | 13 +
drivers/gpu/drm/gma500/psb_intel_display.c | 7 ---
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 55ffde5a3a4a..a5bba9f023e9 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -5138,6 +5138,9 @@ EXPORT_SYMBOL(drm_mode_connector_attach_encoder);
int drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc,
int gamma_size)
{
+ uint16_t *r_base, *g_base, *b_base;
+ int i;
+
crtc->gamma_size = gamma_size;
crtc->gamma_store = kcalloc(gamma_size, sizeof(uint16_t) * 3,
@@ -5147,6 +5150,16 @@ int drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc,
return -ENOMEM;
}
+ r_base = crtc->gamma_store;
+ g_base = r_base + gamma_size;
+ b_base = g_base + gamma_size;
+ for (i = 0; i < gamma_size; i++) {
+ r_base[i] = i << 8;
+ g_base[i] = i << 8;
+ b_base[i] = i << 8;
+ }
+
+
return 0;
}
EXPORT_SYMBOL(drm_mode_crtc_set_gamma_size);
diff --git a/drivers/gpu/drm/gma500/psb_intel_display.c
b/drivers/gpu/drm/gma500/psb_intel_display.c
index 398015be87e4..7b6c84925098 100644
--- a/drivers/gpu/drm/gma500/psb_intel_display.c
+++ b/drivers/gpu/drm/gma500/psb_intel_display.c
@@ -491,7 +491,6 @@ void psb_intel_crtc_init(struct drm_device *dev, int pipe,
struct drm_psb_private *dev_priv = dev->dev_private;
struct gma_crtc *gma_crtc;
int i;
- uint16_t *r_base, *g_base, *b_base;
/* We allocate a extra array of drm_connector pointers
* for fbdev after the crtc */
@@ -519,16 +518,10 @@ void psb_intel_crtc_init(struct drm_device *dev, int pipe,
gma_crtc->pipe = pipe;
gma_crtc->plane = pipe;
- r_base = gma_crtc->base.gamma_store;
- g_base = r_base + 256;
- b_base = g_base + 256;
for (i = 0; i < 256; i++) {
gma_crtc->lut_r[i] = i;
gma_crtc->lut_g[i] = i;
gma_crtc->lut_b[i] = i;
- r_base[i] = i << 8;
- g_base[i] = i << 8;
- b_base[i] = i << 8;
gma_crtc->lut_adj[i] = 0;
}
--
2.8.0.rc3
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[Intel-gfx] [PATCH 00/10] legacy gamma code cleanup
Hi all, Inspired by the color manager work, some prep work cleanup for the legacy gamma code. Two more things I'd like to pull off: - rework the fbdev emulation to use the main gamma interfaces, instead of hand-rolling it's own. - add some helpers to implement legacy gamma in terms of atomic and the new color manager stuff. Probably not too useful for i915.ko, since legacy gamma (which is needed to support C8) and the new color manager stuff use completely different hw blocks. As usual, review&comments highly welcome. Thanks, Daniel Daniel Vetter (10): drm: Initialize a linear gamma table by default drm/fb-helper: Remove dead code in setcolreg drm/armada: Drop fb gamma_set/get functions drm/bochs: Drop fake gamma support drm/cirrus: Drop redundnant gamma size check drm/msm: Nuke dummy gamma_set/get functions drm/virtio: Drop dummy gamma table support drm/imx: Don't set a gamma table size drm/qxl: Don't set a gamma table size drm/tegra: Don't set a gamma table size drivers/gpu/drm/armada/armada_crtc.c | 10 - drivers/gpu/drm/armada/armada_crtc.h | 2 -- drivers/gpu/drm/armada/armada_fbdev.c | 2 -- drivers/gpu/drm/bochs/bochs_fbdev.c| 15 -- drivers/gpu/drm/bochs/bochs_kms.c | 7 --- drivers/gpu/drm/cirrus/cirrus_mode.c | 3 --- drivers/gpu/drm/drm_crtc.c | 13 drivers/gpu/drm/drm_fb_helper.c| 33 ++ drivers/gpu/drm/gma500/psb_intel_display.c | 7 --- drivers/gpu/drm/imx/imx-drm-core.c | 4 drivers/gpu/drm/msm/msm_fbdev.c| 14 - drivers/gpu/drm/qxl/qxl_display.c | 1 - drivers/gpu/drm/tegra/dc.c | 1 - drivers/gpu/drm/virtio/virtgpu_display.c | 9 14 files changed, 15 insertions(+), 106 deletions(-) -- 2.8.0.rc3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/10] drm/virtio: Drop dummy gamma table support
No need to confuse userspace like this.
Cc: Gerd Hoffmann
Cc: Dave Airlie
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/virtio/virtgpu_display.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/virtio/virtgpu_display.c
b/drivers/gpu/drm/virtio/virtgpu_display.c
index 4854dac87e24..12b72e29678a 100644
--- a/drivers/gpu/drm/virtio/virtgpu_display.c
+++ b/drivers/gpu/drm/virtio/virtgpu_display.c
@@ -38,13 +38,6 @@
#define XRES_MAX 8192
#define YRES_MAX 8192
-static void virtio_gpu_crtc_gamma_set(struct drm_crtc *crtc,
- u16 *red, u16 *green, u16 *blue,
- uint32_t start, uint32_t size)
-{
- /* TODO */
-}
-
static void
virtio_gpu_hide_cursor(struct virtio_gpu_device *vgdev,
struct virtio_gpu_output *output)
@@ -173,7 +166,6 @@ static int virtio_gpu_page_flip(struct drm_crtc *crtc,
static const struct drm_crtc_funcs virtio_gpu_crtc_funcs = {
.cursor_set2= virtio_gpu_crtc_cursor_set,
.cursor_move= virtio_gpu_crtc_cursor_move,
- .gamma_set = virtio_gpu_crtc_gamma_set,
.set_config = drm_atomic_helper_set_config,
.destroy= drm_crtc_cleanup,
@@ -416,7 +408,6 @@ static int vgdev_output_init(struct virtio_gpu_device
*vgdev, int index)
return PTR_ERR(plane);
drm_crtc_init_with_planes(dev, crtc, plane, NULL,
&virtio_gpu_crtc_funcs, NULL);
- drm_mode_crtc_set_gamma_size(crtc, 256);
drm_crtc_helper_add(crtc, &virtio_gpu_crtc_helper_funcs);
plane->crtc = crtc;
--
2.8.0.rc3
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[Intel-gfx] [PATCH 08/10] drm/imx: Don't set a gamma table size
imx doesn't have any functions for setting the gamma table, so this is completely defunct. Not nice to lie to userspace, so let's stop! Cc: Russell King Cc: Philipp Zabel Signed-off-by: Daniel Vetter --- drivers/gpu/drm/imx/imx-drm-core.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/imx/imx-drm-core.c b/drivers/gpu/drm/imx/imx-drm-core.c index 9876e0f0c3e1..21a52937f9cd 100644 --- a/drivers/gpu/drm/imx/imx-drm-core.c +++ b/drivers/gpu/drm/imx/imx-drm-core.c @@ -351,10 +351,6 @@ int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc, *new_crtc = imx_drm_crtc; - ret = drm_mode_crtc_set_gamma_size(imx_drm_crtc->crtc, 256); - if (ret) - goto err_register; - drm_crtc_helper_add(crtc, imx_drm_crtc->imx_drm_helper_funcs.crtc_helper_funcs); -- 2.8.0.rc3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/10] drm/tegra: Don't set a gamma table size
tegra doesn't have any functions to set gamma tables, so this is completely defunct. Not nice to lie to userspace, so let's stop! Cc: Thierry Reding Signed-off-by: Daniel Vetter --- drivers/gpu/drm/tegra/dc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index fb2b4b0271a2..3b85a31b625d 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1722,7 +1722,6 @@ static int tegra_dc_init(struct host1x_client *client) if (err < 0) goto cleanup; - drm_mode_crtc_set_gamma_size(&dc->base, 256); drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); /* -- 2.8.0.rc3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/10] drm/bochs: Drop fake gamma support
Only really needed for fbdev emulation at 8bpp. And bochs doesn't do
that. And either way bochs only does 32bit rgb, so this is all pretty
much wasted dead code.
The only consideration is that we need to not set up any gamma size
either.
Cc: Gerd Hoffmann
Cc: Dave Airlie
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/bochs/bochs_fbdev.c | 15 ---
drivers/gpu/drm/bochs/bochs_kms.c | 7 ---
2 files changed, 22 deletions(-)
diff --git a/drivers/gpu/drm/bochs/bochs_fbdev.c
b/drivers/gpu/drm/bochs/bochs_fbdev.c
index 7520bf81fc25..369f11f10c72 100644
--- a/drivers/gpu/drm/bochs/bochs_fbdev.c
+++ b/drivers/gpu/drm/bochs/bochs_fbdev.c
@@ -162,22 +162,7 @@ static int bochs_fbdev_destroy(struct bochs_device *bochs)
return 0;
}
-void bochs_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
- u16 blue, int regno)
-{
-}
-
-void bochs_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
- u16 *blue, int regno)
-{
- *red = regno;
- *green = regno;
- *blue = regno;
-}
-
static const struct drm_fb_helper_funcs bochs_fb_helper_funcs = {
- .gamma_set = bochs_fb_gamma_set,
- .gamma_get = bochs_fb_gamma_get,
.fb_probe = bochsfb_create,
};
diff --git a/drivers/gpu/drm/bochs/bochs_kms.c
b/drivers/gpu/drm/bochs/bochs_kms.c
index 96926f09e0c9..89adfd916a7c 100644
--- a/drivers/gpu/drm/bochs/bochs_kms.c
+++ b/drivers/gpu/drm/bochs/bochs_kms.c
@@ -93,11 +93,6 @@ static void bochs_crtc_commit(struct drm_crtc *crtc)
{
}
-static void bochs_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
-u16 *blue, uint32_t start, uint32_t size)
-{
-}
-
static int bochs_crtc_page_flip(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
struct drm_pending_vblank_event *event,
@@ -120,7 +115,6 @@ static int bochs_crtc_page_flip(struct drm_crtc *crtc,
/* These provide the minimum set of functions required to handle a CRTC */
static const struct drm_crtc_funcs bochs_crtc_funcs = {
- .gamma_set = bochs_crtc_gamma_set,
.set_config = drm_crtc_helper_set_config,
.destroy = drm_crtc_cleanup,
.page_flip = bochs_crtc_page_flip,
@@ -140,7 +134,6 @@ static void bochs_crtc_init(struct drm_device *dev)
struct drm_crtc *crtc = &bochs->crtc;
drm_crtc_init(dev, crtc, &bochs_crtc_funcs);
- drm_mode_crtc_set_gamma_size(crtc, 256);
drm_crtc_helper_add(crtc, &bochs_helper_funcs);
}
--
2.8.0.rc3
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[Intel-gfx] [PATCH 03/10] drm/armada: Drop fb gamma_set/get functions
The fb helper private gamma_set/get functions are only required when
the driver supports paletted 8bit mode with fbdev. Armada uses 32bpp
unconditionally, so this is just dead code. It also doesn't do
anything really. Let's just remove it.
Cc: Russell King
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/armada/armada_crtc.c | 10 --
drivers/gpu/drm/armada/armada_crtc.h | 2 --
drivers/gpu/drm/armada/armada_fbdev.c | 2 --
3 files changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/armada/armada_crtc.c
b/drivers/gpu/drm/armada/armada_crtc.c
index 0293eb74d777..f2979655e100 100644
--- a/drivers/gpu/drm/armada/armada_crtc.c
+++ b/drivers/gpu/drm/armada/armada_crtc.c
@@ -317,16 +317,6 @@ static void armada_drm_vblank_off(struct armada_crtc
*dcrtc)
armada_drm_plane_work_run(dcrtc, plane);
}
-void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b,
- int idx)
-{
-}
-
-void armada_drm_crtc_gamma_get(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
- int idx)
-{
-}
-
/* The mode_config.mutex will be held for this call */
static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
{
diff --git a/drivers/gpu/drm/armada/armada_crtc.h
b/drivers/gpu/drm/armada/armada_crtc.h
index 04fdd22d483b..6e2770343856 100644
--- a/drivers/gpu/drm/armada/armada_crtc.h
+++ b/drivers/gpu/drm/armada/armada_crtc.h
@@ -92,8 +92,6 @@ struct armada_crtc {
};
#define drm_to_armada_crtc(c) container_of(c, struct armada_crtc, crtc)
-void armada_drm_crtc_gamma_set(struct drm_crtc *, u16, u16, u16, int);
-void armada_drm_crtc_gamma_get(struct drm_crtc *, u16 *, u16 *, u16 *, int);
void armada_drm_crtc_disable_irq(struct armada_crtc *, u32);
void armada_drm_crtc_enable_irq(struct armada_crtc *, u32);
void armada_drm_crtc_update_regs(struct armada_crtc *, struct armada_regs *);
diff --git a/drivers/gpu/drm/armada/armada_fbdev.c
b/drivers/gpu/drm/armada/armada_fbdev.c
index 7d03c51abcb9..7781bac2ada2 100644
--- a/drivers/gpu/drm/armada/armada_fbdev.c
+++ b/drivers/gpu/drm/armada/armada_fbdev.c
@@ -124,8 +124,6 @@ static int armada_fb_probe(struct drm_fb_helper *fbh,
}
static const struct drm_fb_helper_funcs armada_fb_helper_funcs = {
- .gamma_set = armada_drm_crtc_gamma_set,
- .gamma_get = armada_drm_crtc_gamma_get,
.fb_probe = armada_fb_probe,
};
--
2.8.0.rc3
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[Intel-gfx] [PATCH 09/10] drm/qxl: Don't set a gamma table size
qxl doesn't have any functions for setting the gamma table, so this is completely defunct. Not nice to lie to userspace, so let's stop! Cc: Dave Airlie Signed-off-by: Daniel Vetter --- drivers/gpu/drm/qxl/qxl_display.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c index 030409a3ee4e..21c70952402d 100644 --- a/drivers/gpu/drm/qxl/qxl_display.c +++ b/drivers/gpu/drm/qxl/qxl_display.c @@ -729,7 +729,6 @@ static int qdev_crtc_init(struct drm_device *dev, int crtc_id) drm_crtc_init(dev, &qxl_crtc->base, &qxl_crtc_funcs); qxl_crtc->index = crtc_id; - drm_mode_crtc_set_gamma_size(&qxl_crtc->base, 256); drm_crtc_helper_add(&qxl_crtc->base, &qxl_crtc_helper_funcs); return 0; } -- 2.8.0.rc3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/10] drm/msm: Nuke dummy gamma_set/get functions
Again the fbdev emulation gamma_set/get functions are only needed for
drivers that try to also use 8bpp paletted mode. Which msm doesn't, so
this is dead code. Let's rip it out.
Cc: Rob Clark
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/msm/msm_fbdev.c | 14 --
1 file changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_fbdev.c b/drivers/gpu/drm/msm/msm_fbdev.c
index d9759bf3482e..1a061e3e8b9e 100644
--- a/drivers/gpu/drm/msm/msm_fbdev.c
+++ b/drivers/gpu/drm/msm/msm_fbdev.c
@@ -184,21 +184,7 @@ fail:
return ret;
}
-static void msm_crtc_fb_gamma_set(struct drm_crtc *crtc,
- u16 red, u16 green, u16 blue, int regno)
-{
- DBG("fbdev: set gamma");
-}
-
-static void msm_crtc_fb_gamma_get(struct drm_crtc *crtc,
- u16 *red, u16 *green, u16 *blue, int regno)
-{
- DBG("fbdev: get gamma");
-}
-
static const struct drm_fb_helper_funcs msm_fb_helper_funcs = {
- .gamma_set = msm_crtc_fb_gamma_set,
- .gamma_get = msm_crtc_fb_gamma_get,
.fb_probe = msm_fbdev_create,
};
--
2.8.0.rc3
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[Intel-gfx] [PATCH 05/10] drm/cirrus: Drop redundnant gamma size check
The core does this for us already.
Cc: Dave Airlie
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/cirrus/cirrus_mode.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/cirrus/cirrus_mode.c
b/drivers/gpu/drm/cirrus/cirrus_mode.c
index d3d8d7bfcc57..0b1a411cb89e 100644
--- a/drivers/gpu/drm/cirrus/cirrus_mode.c
+++ b/drivers/gpu/drm/cirrus/cirrus_mode.c
@@ -331,9 +331,6 @@ static void cirrus_crtc_gamma_set(struct drm_crtc *crtc,
u16 *red, u16 *green,
struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
int i;
- if (size != CIRRUS_LUT_SIZE)
- return;
-
for (i = 0; i < CIRRUS_LUT_SIZE; i++) {
cirrus_crtc->lut_r[i] = red[i];
cirrus_crtc->lut_g[i] = green[i];
--
2.8.0.rc3
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Re: [Intel-gfx] [PATCH] drm/i915: fix deadlock on lid open
On Wed, Mar 30, 2016 at 11:08:33AM +0200, Bjørn Mork wrote:
> commit e2c8b8701e2d moved modeset locking inside resume/suspend
> functions, but missed a code path only executed on lid close/open
> on older hardware. The result was a deadlock when closing and
> opening the lid without suspending on such hardware:
>
> =
> [ INFO: possible recursive locking detected ]
> 4.6.0-rc1 #385 Not tainted
> -
> kworker/0:3/88 is trying to acquire lock:
> (&dev->mode_config.mutex){+.+.+.}, at: []
> intel_display_resume+0x4a/0x12f [i915]
>
> but task is already holding lock:
> (&dev->mode_config.mutex){+.+.+.}, at: []
> drm_modeset_lock_all+0x3e/0xa6 [drm]
>
> other info that might help us debug this:
> Possible unsafe locking scenario:
>
> CPU0
>
>lock(&dev->mode_config.mutex);
>lock(&dev->mode_config.mutex);
>
> *** DEADLOCK ***
>
> May be due to missing lock nesting notation
>
> 7 locks held by kworker/0:3/88:
> #0: ("kacpi_notify"){.+}, at: []
> process_one_work+0x14a/0x50b
> #1: ((&dpc->work)#2){+.+.+.}, at: []
> process_one_work+0x14a/0x50b
> #2: ((acpi_lid_notifier).rwsem){.+}, at: []
> __blocking_notifier_call_chain+0x34/0x65
> #3: (&dev_priv->modeset_restore_lock){+.+.+.}, at: []
> intel_lid_notify+0x3c/0xd9 [i915]
> #4: (&dev->mode_config.mutex){+.+.+.}, at: []
> drm_modeset_lock_all+0x3e/0xa6 [drm]
> #5: (crtc_ww_class_acquire){+.+.+.}, at: []
> drm_modeset_lock_all+0x48/0xa6 [drm]
> #6: (crtc_ww_class_mutex){+.+.+.}, at: []
> modeset_lock+0x13c/0x1cd [drm]
>
> stack backtrace:
> CPU: 0 PID: 88 Comm: kworker/0:3 Not tainted 4.6.0-rc1 #385
> Hardware name: LENOVO 2776LEG/2776LEG, BIOS 6EET55WW (3.15 ) 12/19/2011
> Workqueue: kacpi_notify acpi_os_execute_deferred
> 88022fd5f990 8124af06 825b39c0
> 825b39c0 88022fd5fa60 8108f547 88022fd5fa70
> 8108e817 880230236cc0 825b39c0
> Call Trace:
> [] dump_stack+0x67/0x90
> [] __lock_acquire+0xdb5/0xf71
> [] ? look_up_lock_class+0xbe/0x10a
> [] lock_acquire+0x137/0x1cb
> [] ? lock_acquire+0x137/0x1cb
> [] ? intel_display_resume+0x4a/0x12f [i915]
> [] mutex_lock_nested+0x7e/0x3a4
> [] ? intel_display_resume+0x4a/0x12f [i915]
> [] ? intel_display_resume+0x4a/0x12f [i915]
> [] ? modeset_lock+0x13c/0x1cd [drm]
> [] intel_display_resume+0x4a/0x12f [i915]
> [] ? intel_display_resume+0x4a/0x12f [i915]
> [] ? modeset_lock+0x13c/0x1cd [drm]
> [] ? modeset_lock+0x13c/0x1cd [drm]
> [] ? drm_modeset_lock+0x17/0x24 [drm]
> [] ? drm_modeset_lock_all_ctx+0x87/0xa1 [drm]
> [] intel_lid_notify+0xb0/0xd9 [i915]
> [] notifier_call_chain+0x4a/0x6c
> [] __blocking_notifier_call_chain+0x4d/0x65
> [] blocking_notifier_call_chain+0x14/0x16
> [] acpi_lid_send_state+0x83/0xad [button]
> [] acpi_button_notify+0x41/0x132 [button]
> [] acpi_device_notify+0x19/0x1b
> [] acpi_ev_notify_dispatch+0x49/0x64
> [] acpi_os_execute_deferred+0x14/0x20
> [] process_one_work+0x265/0x50b
> [] worker_thread+0x1fc/0x2dd
> [] ? rescuer_thread+0x309/0x309
> [] ? rescuer_thread+0x309/0x309
> [] kthread+0xe0/0xe8
> [] ? local_clock+0x19/0x22
> [] ret_from_fork+0x22/0x40
> [] ? kthread_create_on_node+0x1b5/0x1b5
>
> Fixes: e2c8b8701e2d ("drm/i915: Use atomic helpers for suspend, v2.")
> Cc: Maarten Lankhorst
> Signed-off-by: Bjørn Mork
Oops, that one's pretty silly. Unfortunately we don't have any such
machines in CI yet, and it wouldn't be possible to exercise the lid
notifier automatically.
Thanks for your fix, applied.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_lvds.c | 5 +
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c
> b/drivers/gpu/drm/i915/intel_lvds.c
> index 30a8403a8f4f..cd9fe609aefb 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -478,11 +478,8 @@ static int intel_lid_notify(struct notifier_block *nb,
> unsigned long val,
>* and as part of the cleanup in the hw state restore we also redisable
>* the vga plane.
>*/
> - if (!HAS_PCH_SPLIT(dev)) {
> - drm_modeset_lock_all(dev);
> + if (!HAS_PCH_SPLIT(dev))
> intel_display_resume(dev);
> - drm_modeset_unlock_all(dev);
> - }
>
> dev_priv->modeset_restore = MODESET_DONE;
>
> --
> 2.1.4
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH] drm/i915: BUG_ON when ggtt_view is NULL
On to, 2016-03-24 at 15:54 +, Matthew Auld wrote:
> Lets BUG_ON and don't bother with a WARN and returning an error, so we can
> remove the need to pollute the code with error handling, after all it is
> a programmer error to provide NULL view. Also while we're here remove
> redundant NULL ggtt_view check.
>
> Cc: Joonas Lahtinen
> Cc: Tvrtko Ursulin
Thanks for the patch, I'll merge.
Reviewed-by: Joonas Lahtinen
> Signed-off-by: Matthew Auld
> ---
> drivers/gpu/drm/i915/i915_gem.c | 9 ++---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 10 +-
> 2 files changed, 3 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index c7a997a..cbf616a 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4235,9 +4235,6 @@ i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
> vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
> i915_gem_obj_to_vma(obj, vm);
>
> - if (IS_ERR(vma))
> - return PTR_ERR(vma);
> -
> if (vma) {
> if (WARN_ON(vma->pin_count ==
> DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
> return -EBUSY;
> @@ -4300,8 +4297,7 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object
> *obj,
> uint32_t alignment,
> uint64_t flags)
> {
> - if (WARN_ONCE(!view, "no view specified"))
> - return -EINVAL;
> + BUG_ON(!view);
>
> return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view,
> alignment, flags | PIN_GLOBAL);
> @@ -4618,8 +4614,7 @@ struct i915_vma *i915_gem_obj_to_ggtt_view(struct
> drm_i915_gem_object *obj,
> struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
> struct i915_vma *vma;
>
> - if (WARN_ONCE(!view, "no view specified"))
> - return ERR_PTR(-EINVAL);
> + BUG_ON(!view);
>
> list_for_each_entry(vma, &obj->vma_list, obj_link)
> if (vma->vm == ggtt &&
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 7cfafdc..073c6bb 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -3341,15 +3341,7 @@ i915_gem_obj_lookup_or_create_ggtt_vma(struct
> drm_i915_gem_object *obj,
> const struct i915_ggtt_view *view)
> {
> struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
> - struct i915_vma *vma;
> -
> - if (WARN_ON(!view))
> - return ERR_PTR(-EINVAL);
> -
> - vma = i915_gem_obj_to_ggtt_view(obj, view);
> -
> - if (IS_ERR(vma))
> - return vma;
> + struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
>
> if (!vma)
> vma = __i915_gem_vma_create(obj, ggtt, view);
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 05/10] drm: Give drm_agp_clear drm_legacy_ prefix
Hi Daniel, [auto build test ERROR on drm/drm-next] [also build test ERROR on v4.6-rc1 next-20160330] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url: https://github.com/0day-ci/linux/commits/Daniel-Vetter/Another-shot-at-cruft-removal/20160330-174803 base: git://people.freedesktop.org/~airlied/linux.git drm-next config: sparc64-allmodconfig (attached as .config) reproduce: wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree make.cross ARCH=sparc64 Note: the linux-review/Daniel-Vetter/Another-shot-at-cruft-removal/20160330-174803 HEAD 0ef75daff5d81f77ebd5796d853c534749223b2e builds fine. It only hurts bisectibility. All errors (new ones prefixed by >>): drivers/gpu/drm/drm_fops.c: In function 'drm_lastclose': >> drivers/gpu/drm/drm_fops.c:416:2: error: implicit declaration of function >> 'drm_legacy_agp_clear' [-Werror=implicit-function-declaration] drm_legacy_agp_clear(dev); ^ cc1: some warnings being treated as errors -- drivers/gpu/drm/drm_pci.c: In function 'drm_pci_agp_destroy': >> drivers/gpu/drm/drm_pci.c:253:3: error: implicit declaration of function >> 'drm_legacy_agp_clear' [-Werror=implicit-function-declaration] drm_legacy_agp_clear(dev); ^ cc1: some warnings being treated as errors vim +/drm_legacy_agp_clear +416 drivers/gpu/drm/drm_fops.c 410 411 if (dev->irq_enabled && !drm_core_check_feature(dev, DRIVER_MODESET)) 412 drm_irq_uninstall(dev); 413 414 mutex_lock(&dev->struct_mutex); 415 > 416 drm_legacy_agp_clear(dev); 417 418 drm_legacy_sg_cleanup(dev); 419 drm_legacy_vma_flush(dev); --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation .config.gz Description: Binary data ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Unbind objects in shrinker only if device is runtime active
From: Praveen Paneri When the system is running low on memory, gem shrinker is invoked. In this process objects will be unbounded from GTT and unbinding process will require access to GTT(GTTADR) and also to fence register potentially. That requires a resume of gfx device, if suspended, in the shrinker path. Considering the power leakage due to intermediate resume, perform unbinding operation only if device is already runtime active. v2: Using newly implemented intel_runtime_pm_get_if_in_use() Signed-off-by: Akash Goel Signed-off-by: Praveen Paneri Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_shrinker.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c index d3c473ffb90a..3bc292d626ff 100644 --- a/drivers/gpu/drm/i915/i915_gem_shrinker.c +++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c @@ -129,6 +129,15 @@ i915_gem_shrink(struct drm_i915_private *dev_priv, i915_gem_retire_requests(dev_priv->dev); /* +* Unbinding of objects will require HW access; Let us not wake the +* device just to recover a little memory. If absolutely necessary, +* we will force the wake during oom-notifier. +*/ + if ((flags & I915_SHRINK_BOUND) && + !intel_runtime_pm_get_if_in_use(dev_priv)) + flags &= ~I915_SHRINK_BOUND; + + /* * As we may completely rewrite the (un)bound list whilst unbinding * (due to retiring requests) we have to strictly process only * one element of the list at the time, and recheck the list @@ -188,6 +197,9 @@ i915_gem_shrink(struct drm_i915_private *dev_priv, list_splice(&still_in_list, phase->list); } + if (flags & I915_SHRINK_BOUND) + intel_runtime_pm_put(dev_priv); + i915_gem_retire_requests(dev_priv->dev); return count; -- 2.5.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: fix deadlock on lid open
Op 30-03-16 om 11:08 schreef Bjørn Mork: > commit e2c8b8701e2d moved modeset locking inside resume/suspend > functions, but missed a code path only executed on lid close/open > on older hardware. The result was a deadlock when closing and > opening the lid without suspending on such hardware: > Applied, thanks! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] vgacon: dummy implementation for vgacon_text_force
On 30 March 2016 at 10:26, Daniel Vetter wrote: > This allows us to ditch a ton of ugly #ifdefs from a bunch of drm modeset > drivers. > > v2: Make the dummy function actually return a sane value, spotted by > Ville. > > v3: Because the patch is still in limbo there's no more drivers to > convert, noticed by Emil. > > v4: Rebase once more, because hooray. I'll just go ahead an apply this > one later on to drm-misc. > > Cc: Emil Velikov > Cc: Ville Syrjälä > Cc: Andrew Morton > Cc: Greg Kroah-Hartman > Signed-off-by: Daniel Vetter Good bye #ifdef spaghetti :-) Reviewed-by: Emil Velikov -Emil ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Unbind objects in shrinker only if device is runtime active
On Wed, Mar 30, 2016 at 01:11:53PM +0300, Mika Kuoppala wrote: > From: Praveen Paneri > > When the system is running low on memory, gem shrinker is invoked. > In this process objects will be unbounded from GTT and unbinding process > will require access to GTT(GTTADR) and also to fence register potentially. > That requires a resume of gfx device, if suspended, in the shrinker path. > Considering the power leakage due to intermediate resume, perform unbinding > operation only if device is already runtime active. > > v2: Using newly implemented intel_runtime_pm_get_if_in_use() > > Signed-off-by: Akash Goel > Signed-off-by: Praveen Paneri > Reviewed-by: Chris Wilson > --- > drivers/gpu/drm/i915/i915_gem_shrinker.c | 12 > 1 file changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c > b/drivers/gpu/drm/i915/i915_gem_shrinker.c > index d3c473ffb90a..3bc292d626ff 100644 > --- a/drivers/gpu/drm/i915/i915_gem_shrinker.c > +++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c > @@ -129,6 +129,15 @@ i915_gem_shrink(struct drm_i915_private *dev_priv, > i915_gem_retire_requests(dev_priv->dev); > > /* > + * Unbinding of objects will require HW access; Let us not wake the > + * device just to recover a little memory. If absolutely necessary, > + * we will force the wake during oom-notifier. > + */ The implication was that we would send the companion patch as well! -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Rename __force_wake_get to __force_wake_auto
Patchwork writes: > [ text/plain ] > == Series Details == > > Series: drm/i915: Rename __force_wake_get to __force_wake_auto > URL : https://patchwork.freedesktop.org/series/4864/ > State : warning > > == Summary == > > Series 4864v1 drm/i915: Rename __force_wake_get to __force_wake_auto > http://patchwork.freedesktop.org/api/1.0/series/4864/revisions/1/mbox/ > > Test gem_exec_suspend: > Subgroup basic-s3: > pass -> DMESG-WARN (bsw-nuc-2) https://bugs.freedesktop.org/show_bug.cgi?id=94350 > Test kms_pipe_crc_basic: > Subgroup suspend-read-crc-pipe-c: > pass -> SKIP (hsw-gt2) > Test pm_rpm: > Subgroup basic-rte: > pass -> DMESG-WARN (bsw-nuc-2) > dmesg-warn -> PASS (byt-nuc) UNSTABLE https://bugs.freedesktop.org/show_bug.cgi?id=94164 > > bdw-nuci7total:192 pass:179 dwarn:0 dfail:0 fail:1 skip:12 > bdw-ultratotal:192 pass:170 dwarn:0 dfail:0 fail:1 skip:21 > bsw-nuc-2total:192 pass:153 dwarn:2 dfail:0 fail:0 skip:37 > byt-nuc total:192 pass:157 dwarn:0 dfail:0 fail:0 skip:35 > hsw-brixbox total:192 pass:170 dwarn:0 dfail:0 fail:0 skip:22 > hsw-gt2 total:192 pass:174 dwarn:0 dfail:0 fail:0 skip:18 > ivb-t430stotal:192 pass:167 dwarn:0 dfail:0 fail:0 skip:25 > skl-i7k-2total:192 pass:169 dwarn:0 dfail:0 fail:0 skip:23 > skl-nuci5total:192 pass:181 dwarn:0 dfail:0 fail:0 skip:11 > snb-dellxps total:192 pass:158 dwarn:0 dfail:0 fail:0 skip:34 > > Results at /archive/results/CI_IGT_test/Patchwork_1710/ > > f5d413cccefa1f93d64c34f357151d42add63a84 drm-intel-nightly: > 2016y-03m-24d-14h-34m-29s UTC integration manifest > c2a5605a3ca807381aefbcbc7b4097391b55a268 drm/i915: Rename __force_wake_get to > __force_wake_auto > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Add rpm get/put in i915_shrinker_oom
From: Praveen Paneri i915_gem_shrink_all() will scan the bound list only if device is not suspended but in OOM scenarios it becomes absolutely necessary to release as much memory as possible. So, adding rpm get/put in i915_shrinker_oom() to ensure shrinking of bound objects in OOM scenario. Signed-off-by: Praveen Paneri Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_shrinker.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c index 3bc292d626ff..4457f86c81ef 100644 --- a/drivers/gpu/drm/i915/i915_gem_shrinker.c +++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c @@ -325,7 +325,9 @@ i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr) was_interruptible = dev_priv->mm.interruptible; dev_priv->mm.interruptible = false; + intel_runtime_pm_get(dev_priv); freed_pages = i915_gem_shrink_all(dev_priv); + intel_runtime_pm_put(dev_priv); dev_priv->mm.interruptible = was_interruptible; -- 2.5.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Unbind objects in shrinker only if device is runtime active
Chris Wilson writes: > [ text/plain ] > On Wed, Mar 30, 2016 at 01:11:53PM +0300, Mika Kuoppala wrote: >> From: Praveen Paneri >> >> When the system is running low on memory, gem shrinker is invoked. >> In this process objects will be unbounded from GTT and unbinding process >> will require access to GTT(GTTADR) and also to fence register potentially. >> That requires a resume of gfx device, if suspended, in the shrinker path. >> Considering the power leakage due to intermediate resume, perform unbinding >> operation only if device is already runtime active. >> >> v2: Using newly implemented intel_runtime_pm_get_if_in_use() >> >> Signed-off-by: Akash Goel >> Signed-off-by: Praveen Paneri >> Reviewed-by: Chris Wilson >> --- >> drivers/gpu/drm/i915/i915_gem_shrinker.c | 12 >> 1 file changed, 12 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c >> b/drivers/gpu/drm/i915/i915_gem_shrinker.c >> index d3c473ffb90a..3bc292d626ff 100644 >> --- a/drivers/gpu/drm/i915/i915_gem_shrinker.c >> +++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c >> @@ -129,6 +129,15 @@ i915_gem_shrink(struct drm_i915_private *dev_priv, >> i915_gem_retire_requests(dev_priv->dev); >> >> /* >> + * Unbinding of objects will require HW access; Let us not wake the >> + * device just to recover a little memory. If absolutely necessary, >> + * we will force the wake during oom-notifier. >> + */ > > The implication was that we would send the companion patch as well! Missed it, thanks for pointing out. Will send it as a separate one and combine when merging. Thanks, -Mika > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/10] drm: Forbid legacy MAP functions for DRIVER_MODESET
On 30 March 2016 at 10:45, Daniel Vetter wrote: > Like in > > commit 0e975980d435d58df2d430d688b8c18778b42218 > Author: Peter Antoine > Date: Tue Jun 23 08:18:49 2015 +0100 > > drm: Turn off Legacy Context Functions > > we need to again make an exception for nouveau, but everyone else > really doesn't need this. > > Cc: Peter Antoine > Cc: Ben Skeggs > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/drm_bufs.c | 12 > 1 file changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c > index d92db7007f62..e8a12a4fd400 100644 > --- a/drivers/gpu/drm/drm_bufs.c > +++ b/drivers/gpu/drm/drm_bufs.c > @@ -396,6 +396,10 @@ int drm_legacy_addmap_ioctl(struct drm_device *dev, void > *data, > if (!(capable(CAP_SYS_ADMIN) || map->type == _DRM_AGP || map->type == > _DRM_SHM)) > return -EPERM; > > + if (!drm_core_check_feature(dev, DRIVER_KMS_LEGACY_CONTEXT) && > + drm_core_check_feature(dev, DRIVER_MODESET)) > + return -EINVAL; > + Wondering if making this the first check in the function won't be better ? We have a handful of places which preemptively check DRIVER_MODESET prior to calling drm_legacy functions and similarly some (last time I've looked) drm_legacy functions check for DRIVER_MODESET. Perhaps we can move all the checking into the drm_legacy API alone ? -Emil ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/BXT: Get pipe conf from the port registers
On Tue, 29 Mar 2016, Ramalingam C wrote:
> At BXT DSI, PIPE registers are inactive. So we can't get the
> PIPE's mode parameters from them. The possible option is
> retriving them from the PORT registers.
>
> The required changes are added for BXT in intel_dsi_get_config
> (encoder->get_config).
>
> Signed-off-by: Ramalingam C
> Signed-off-by: Uma Shankar
> ---
> Previously reviewed at https://patchwork.freedesktop.org/patch/75301/
>
> drivers/gpu/drm/i915/i915_reg.h |1 +
> drivers/gpu/drm/i915/intel_display.c | 44 ++
> drivers/gpu/drm/i915/intel_dsi.c | 104
> ++
> 3 files changed, 149 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c839ce9..da3cdef 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8210,6 +8210,7 @@ enum skl_disp_power_wells {
> #define BXT_PIPE_SELECT_SHIFT 7
> #define BXT_PIPE_SELECT_MASK(7 << 7)
> #define BXT_PIPE_SELECT(pipe) ((pipe) << 7)
> +#define BXT_PORT_TO_PIPE(ctrl) ((ctrl & BXT_PIPE_SELECT_MASK)
> >> 7)
>
> #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
> #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 29aa64b..c0627d6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9941,11 +9941,40 @@ static void haswell_get_ddi_port_state(struct
> intel_crtc *crtc,
> }
> }
>
> +struct intel_encoder *bxt_get_dsi_encoder_for_crtc(struct intel_crtc *crtc,
> + struct intel_crtc_state *pipe_config)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_encoder *intel_encoder;
> + struct intel_dsi *intel_dsi;
> + enum port port;
> + u32 tmp;
> +
> + for_each_intel_encoder(dev, intel_encoder) {
> + if (intel_encoder->type == INTEL_OUTPUT_DSI) {
> + intel_dsi = enc_to_intel_dsi(&intel_encoder->base);
> + for_each_dsi_port(port, intel_dsi->ports) {
> + if (!(I915_READ(BXT_MIPI_PORT_CTRL(port)) &
> + DPI_ENABLE))
> + break;
> +
> + tmp = I915_READ(MIPI_CTRL(port));
> + if ((tmp & BXT_PIPE_SELECT_MASK) ==
> + BXT_PIPE_SELECT(crtc->pipe))
> + return intel_encoder;
> + }
> + }
> + }
> + return NULL;
> +}
> +
> static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_encoder *intel_encoder, *attached_encoder = NULL;
> enum intel_display_power_domain power_domain;
> unsigned long power_domain_mask;
> bool active;
> @@ -9965,6 +9994,21 @@ static bool haswell_get_pipe_config(struct intel_crtc
> *crtc,
> WARN_ON(active && pipe_config->has_dsi_encoder);
> if (pipe_config->has_dsi_encoder)
> active = true;
> +
> + for_each_encoder_on_crtc(dev, &crtc->base, intel_encoder)
> + attached_encoder = intel_encoder;
> +
> + /*
> + * attached_encoder will be NULL, if there is no modeset from
> + * the kernel bootup.
> + */
> + if (!attached_encoder && pipe_config->has_dsi_encoder)
> + attached_encoder =
> + bxt_get_dsi_encoder_for_crtc(crtc, pipe_config);
> +
> + if (attached_encoder && attached_encoder->get_config)
> + attached_encoder->get_config(attached_encoder,
> + pipe_config);
No, you must not add a new call to the encoder->get_config() hook.
haswell_get_pipe_config() is called through the
dev_priv->display.get_pipe_config() function pointer. This happens in
check_crtc_state() and intel_modeset_readout_hw_state(). In both places,
encoder->get_config() is called afterwards, if encoder->get_hw_state()
returns true for the encoder.
The infrastructure is there, you only need to update DSI ->get_config().
> }
>
> if (!active)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 0de74e1..69a801e 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
Re: [Intel-gfx] [PATCH 02/10] drm: Use dev->name as fallback for dev->unique
On 30 March 2016 at 10:45, Daniel Vetter wrote: > Lots of arm drivers get this wrong and for most arm boards this is the > right thing actually. And anyway with most loaders you want to chase > sysfs links anyway to figure out which dri device you want. > > This will fix dmesg noise for rockchip and sti. > Fwiw I still hope to finish libdrm-2 (hint importing kernel headers), which will remove the biggest user of these legacy ioctls. This way we might even nuke all these lovelies from the kernel. I doubt you'll object against the idea, will you ? -Emil ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/10] drm/ttm: Remove TTM_HAS_AGP
On 30 March 2016 at 10:45, Daniel Vetter wrote: > --- a/drivers/gpu/drm/Kconfig > +++ b/drivers/gpu/drm/Kconfig > @@ -83,6 +83,7 @@ config DRM_LOAD_EDID_FIRMWARE > config DRM_TTM > tristate > depends on DRM > + depends on (AGP || AGP=n) Already part of config DRM, so we don't need it here ? > --- a/include/drm/ttm/ttm_bo_driver.h > +++ b/include/drm/ttm/ttm_bo_driver.h > @@ -1030,8 +1030,7 @@ extern pgprot_t ttm_io_prot(uint32_t caching_flags, > pgprot_t tmp); > > extern const struct ttm_mem_type_manager_func ttm_bo_manager_func; > > -#if (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE))) > -#define TTM_HAS_AGP > +#ifdef CONFIG_AGP #if IS_ENABLED(CONFIG_AGP) ? -Emil ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Rename GGTT init functions
On ke, 2016-03-30 at 10:12 +0100, Chris Wilson wrote: > On Tue, Mar 29, 2016 at 03:25:38PM +0100, Chris Wilson wrote: > > > > On Tue, Mar 29, 2016 at 04:15:54PM +0300, Joonas Lahtinen wrote: > > > > > > On to, 2016-03-24 at 16:47 +0200, Joonas Lahtinen wrote: > > > > > > > > Rename and document the GGTT init functions to give a better > > > > idea of the context where they are called from. > > > > > > > > i915_gem_gtt_init => i915_ggtt_init_hw > > > > i915_gem_init_global_gtt => i915_gem_init_ggtt > > > > i915_global_gtt_cleanup => i915_ggtt_cleanup_hw > > > > > > > > Cc: Tvrtko Ursulin > > > > Cc: Mika Kuoppala > > > > Cc: Ville Syrjälä > > > > Acked-by: Chris Wilson > > > Chris, accidentally did not remove you A-b for v2. You can retake your > > > position here. > > > > > > This is the best balance between general naming logic and consistency > > > with ppgtt I could come up. How about I merge this? > > I don't have any better names to suggest, and the init_hw should help a > > lot. Go for it. > Reviewed-by: Chris Wilson Merged, thanks for review and comments everyone. > -Chris > -- Joonas Lahtinen Open Source Technology Center Intel Corporation ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/10] drm/ttm: Remove TTM_HAS_AGP
Hi Daniel,
[auto build test ERROR on drm/drm-next]
[also build test ERROR on v4.6-rc1 next-20160330]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Daniel-Vetter/Another-shot-at-cruft-removal/20160330-174803
base: git://people.freedesktop.org/~airlied/linux.git drm-next
config: i386-allmodconfig (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All error/warnings (new ones prefixed by >>):
drivers/gpu/drm/nouveau/nouveau_bo.c: In function 'nouveau_ttm_tt_create':
>> drivers/gpu/drm/nouveau/nouveau_bo.c:581:10: error: implicit declaration of
>> function 'ttm_agp_tt_create' [-Werror=implicit-function-declaration]
return ttm_agp_tt_create(bdev, drm->agp.bridge, size,
^
>> drivers/gpu/drm/nouveau/nouveau_bo.c:581:10: warning: return makes pointer
>> from integer without a cast [-Wint-conversion]
drivers/gpu/drm/nouveau/nouveau_bo.c: In function 'nouveau_ttm_tt_populate':
>> drivers/gpu/drm/nouveau/nouveau_bo.c:1501:10: error: implicit declaration of
>> function 'ttm_agp_tt_populate' [-Werror=implicit-function-declaration]
return ttm_agp_tt_populate(ttm);
^
drivers/gpu/drm/nouveau/nouveau_bo.c: In function
'nouveau_ttm_tt_unpopulate':
>> drivers/gpu/drm/nouveau/nouveau_bo.c:1568:3: error: implicit declaration of
>> function 'ttm_agp_tt_unpopulate' [-Werror=implicit-function-declaration]
ttm_agp_tt_unpopulate(ttm);
^
cc1: some warnings being treated as errors
--
drivers/gpu/drm/radeon/radeon_ttm.c: In function 'radeon_ttm_tt_create':
>> drivers/gpu/drm/radeon/radeon_ttm.c:685:10: error: implicit declaration of
>> function 'ttm_agp_tt_create' [-Werror=implicit-function-declaration]
return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge,
^
>> drivers/gpu/drm/radeon/radeon_ttm.c:685:10: warning: return makes pointer
>> from integer without a cast [-Wint-conversion]
drivers/gpu/drm/radeon/radeon_ttm.c: In function 'radeon_ttm_tt_populate':
>> drivers/gpu/drm/radeon/radeon_ttm.c:741:10: error: implicit declaration of
>> function 'ttm_agp_tt_populate' [-Werror=implicit-function-declaration]
return ttm_agp_tt_populate(ttm);
^
drivers/gpu/drm/radeon/radeon_ttm.c: In function 'radeon_ttm_tt_unpopulate':
>> drivers/gpu/drm/radeon/radeon_ttm.c:792:3: error: implicit declaration of
>> function 'ttm_agp_tt_unpopulate' [-Werror=implicit-function-declaration]
ttm_agp_tt_unpopulate(ttm);
^
cc1: some warnings being treated as errors
vim +/ttm_agp_tt_unpopulate +1568 drivers/gpu/drm/nouveau/nouveau_bo.c
26c9e8eff Ben Skeggs2015-08-20 1495if
(!nvxx_device(&drm->device)->func->cpu_coherent &&
c3a0c771e Alexandre Courbot 2014-10-27 1496ttm->caching_state
== tt_uncached)
c3a0c771e Alexandre Courbot 2014-10-27 1497return
ttm_dma_populate(ttm_dma, dev->dev);
c3a0c771e Alexandre Courbot 2014-10-27 1498
a7fb8a23c Daniel Vetter 2015-09-09 1499 #if IS_ENABLED(CONFIG_AGP)
340b0e7c5 Ben Skeggs2015-08-20 1500if (drm->agp.bridge) {
dea7e0ac4 Jerome Glisse 2012-01-03 @1501return
ttm_agp_tt_populate(ttm);
dea7e0ac4 Jerome Glisse 2012-01-03 1502}
dea7e0ac4 Jerome Glisse 2012-01-03 1503 #endif
dea7e0ac4 Jerome Glisse 2012-01-03 1504
9bcd38de5 Alexandre Courbot 2016-03-02 1505 #if
IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
3230cfc34 Konrad Rzeszutek Wilk 2011-10-17 1506if (swiotlb_nr_tbl()) {
8e7e70522 Jerome Glisse 2011-11-09 1507return
ttm_dma_populate((void *)ttm, dev->dev);
3230cfc34 Konrad Rzeszutek Wilk 2011-10-17 1508}
3230cfc34 Konrad Rzeszutek Wilk 2011-10-17 1509 #endif
3230cfc34 Konrad Rzeszutek Wilk 2011-10-17 1510
3230cfc34 Konrad Rzeszutek Wilk 2011-10-17 1511r =
ttm_pool_populate(ttm);
3230cfc34 Konrad Rzeszutek Wilk 2011-10-17 1512if (r) {
3230cfc34 Konrad Rzeszutek Wilk 2011-10-17 1513return r;
3230cfc34 Konrad Rzeszutek Wilk 2011-10-17 1514}
3230cfc34 Konrad Rzeszutek Wilk 2011-10-17 1515
3230cfc34 Konrad Rzeszutek Wilk 2011-10-17 1516for (i = 0; i <
ttm->num_pages; i++) {
fd1496a0f Alexandre Courbot 2014-07-31 1517dma_addr_t addr;
fd1496a0f Alexandre Courbot 2014-07-31 1518
fd1496a0f Alexandre Courbot 2014-07-31 1519addr =
dma_map_page(pdev, ttm->pages[i], 0, PAGE_SIZE,
fd1496a0f Alexandre Co
Re: [Intel-gfx] [PATCH 2/2] drm/i915/BXT: Tolerance at BXT DSI pipe_config comparison
On Tue, 29 Mar 2016, Ramalingam C wrote:
> At BXT DSI, PIPE registers are inactive. So we can't get the
> PIPE's mode parameters from them. The possible option is
> retriving them from the PORT registers. But mode timing
> parameters are progammed to port registers interms of byteclocks.
>
> The formula used to convert the pixels interms of byteclk is
> DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
> 8 * 100), lane_count);
>
> So we retrieve them, interms of pixels as
> DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
> (bpp * burst_mode_ratio));
>
> Due to the multiple DIV_ROUND_UP in both formulas we get the worst
> case delta in the retrieved PIPE's timing parameter as below
> DIV_ROUND_UP((8 * intel_dsi->lane_count * 100),
> (dsi_pixel_format_bpp(intel_dsi->pixel_format) *
> intel_dsi->burst_mode_ratio)))
>
> This converson of byteclk to pixel is required for hsync, hfp and hbp.
> Which intern impacts horrizontal timing parameters. At worst case to
> get htotal all there parameters are added with hactive.
> Hence delta will be 3 times of above formula. Hence this value is
> considered as tolerance for pipe_config comparison, in case of BXT DSI.
>
> Signed-off-by: Ramalingam C
> ---
> Reviewed at
> https://lists.freedesktop.org/archives/intel-gfx/2016-March/089548.html
>
> drivers/gpu/drm/i915/intel_display.c | 62
> +++---
> 1 file changed, 57 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index c0627d6..282f036 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12557,6 +12557,9 @@ intel_pipe_config_compare(struct drm_device *dev,
> bool adjust)
> {
> bool ret = true;
> + struct intel_crtc *crtc = to_intel_crtc(current_config->base.crtc);
> + struct intel_encoder *intel_encoder;
> + struct intel_dsi *intel_dsi = NULL;
>
> #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
> do { \
> @@ -12593,6 +12596,54 @@ intel_pipe_config_compare(struct drm_device *dev,
> ret = false; \
> }
>
> +/*
> + * In case of BXT DSI, HW pipe_config will be retrieved from the port's
> timing
> + * configuration. This retrival includes some errors due to the DIV_ROUND_UP.
> + * So we are considering the max possible error at the comparison.
> + */
> +/*
> + * htotal = hactive + hfp + hsync + hbp. Here last three lements might have
> + * the converson error, hence we consider the 3 times of error as tolerance.
> + */
> +
> +#define MAX_BXT_DSI_TIMING_RETRIVAL_ERR \
> + (intel_dsi == NULL ? 0 : \
> + DIV_ROUND_UP((3 * 8 * intel_dsi->lane_count * 100), \
> + (dsi_pixel_format_bpp(intel_dsi->pixel_format) * \
> + intel_dsi->burst_mode_ratio)))
> +
> +#define BXT_DSI_PIPE_CONF_CHECK_I_RANGE(name) { \
> + for_each_encoder_on_crtc(dev, &crtc->base, \
> + intel_encoder) { \
> + if (intel_encoder->type == INTEL_OUTPUT_DSI) { \
> + intel_dsi = enc_to_intel_dsi(&intel_encoder->base); \
> + } \
> + } \
> + if (!(current_config->name < pipe_config->name && \
> + current_config->name >= (pipe_config->name - \
> + MAX_BXT_DSI_TIMING_RETRIVAL_ERR))) { \
> + INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
> + "(expected %i, found %i(Err tolerance considered))\n", \
> + current_config->name, \
> + pipe_config->name); \
> + ret = false; \
> + } \
> +}
> +
> +#define PIPE_CONF_CHECK_I_RANGE(name) { \
> + if (current_config->name != pipe_config->name) { \
> + if (IS_BROXTON(dev) && crtc->config->has_dsi_encoder) { \
Please drop the platform and encoder type checks here, and move them to
a higher level.
> + BXT_DSI_PIPE_CONF_CHECK_I_RANGE(name) \
> + } else { \
> + INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
> + "(expected %i, found %i)\n", \
> + current_config->name, \
> + pipe_config->name); \
> + ret = false; \
> + } \
> + } \
> +}
I think you should model this after PIPE_CONF_CHECK_CLOCK_FUZZY. Please
add a function to do the check, similar to intel_fuzzy_clock_check(),
and this will be much easier to read and understand.
Maybe call the macro PIPE_CONF_CHECK_DSI_TIMING_FUZZY or something,
since I guess it has to be encoder specific.
> +
> #define PIPE_CONF_CHECK_M_N(name) \
> if (!intel_compare_link_m_n(¤t_config->name, \
> &pipe_config->name,\
> @@ -12697,11 +12748,11 @@ intel_pipe_config_compare(struct drm_de
[Intel-gfx] [PATCH] drm/ttm: Remove TTM_HAS_AGP
It tries to do fancy things with excluding agp support if ttm is
built-in, but agp isn't. Instead just express this depency like drm
does and use CONFIG_AGP everywhere.
Also use the neat Makefile magic to make the entire ttm_agp_backend
file optional.
v2: Use IS_ENABLED(CONFIG_AGP) as suggested by Ville
v3: Review from Emil.
Cc: Emil Velikov
Cc: Ville Syrjälä
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/ttm/Makefile | 3 ++-
drivers/gpu/drm/ttm/ttm_agp_backend.c| 3 ---
drivers/gpu/drm/ttm/ttm_page_alloc.c | 8
drivers/gpu/drm/ttm/ttm_page_alloc_dma.c | 8
include/drm/ttm/ttm_bo_driver.h | 3 +--
5 files changed, 11 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/ttm/Makefile b/drivers/gpu/drm/ttm/Makefile
index b433b9f040c9..f92325800f8a 100644
--- a/drivers/gpu/drm/ttm/Makefile
+++ b/drivers/gpu/drm/ttm/Makefile
@@ -2,9 +2,10 @@
# Makefile for the drm device driver. This driver provides support for the
ccflags-y := -Iinclude/drm
-ttm-y := ttm_agp_backend.o ttm_memory.o ttm_tt.o ttm_bo.o \
+ttm-y := ttm_memory.o ttm_tt.o ttm_bo.o \
ttm_bo_util.o ttm_bo_vm.o ttm_module.o \
ttm_object.o ttm_lock.o ttm_execbuf_util.o ttm_page_alloc.o \
ttm_bo_manager.o ttm_page_alloc_dma.o
+ttm-$(CONFIG_AGP) += ttm_agp_backend.o
obj-$(CONFIG_DRM_TTM) += ttm.o
diff --git a/drivers/gpu/drm/ttm/ttm_agp_backend.c
b/drivers/gpu/drm/ttm/ttm_agp_backend.c
index 764be36397fd..028ab6007873 100644
--- a/drivers/gpu/drm/ttm/ttm_agp_backend.c
+++ b/drivers/gpu/drm/ttm/ttm_agp_backend.c
@@ -34,7 +34,6 @@
#include
#include
#include
-#ifdef TTM_HAS_AGP
#include
#include
#include
@@ -148,5 +147,3 @@ void ttm_agp_tt_unpopulate(struct ttm_tt *ttm)
ttm_pool_unpopulate(ttm);
}
EXPORT_SYMBOL(ttm_agp_tt_unpopulate);
-
-#endif
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c
b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index 025c429050c0..a37de5db5731 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -48,7 +48,7 @@
#include
#include
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
#include
#endif
@@ -219,7 +219,7 @@ static struct ttm_pool_manager *_manager;
#ifndef CONFIG_X86
static int set_pages_array_wb(struct page **pages, int addrinarray)
{
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
int i;
for (i = 0; i < addrinarray; i++)
@@ -230,7 +230,7 @@ static int set_pages_array_wb(struct page **pages, int
addrinarray)
static int set_pages_array_wc(struct page **pages, int addrinarray)
{
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
int i;
for (i = 0; i < addrinarray; i++)
@@ -241,7 +241,7 @@ static int set_pages_array_wc(struct page **pages, int
addrinarray)
static int set_pages_array_uc(struct page **pages, int addrinarray)
{
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
int i;
for (i = 0; i < addrinarray; i++)
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
index 624d941aaad1..bef9f6feb635 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
@@ -50,7 +50,7 @@
#include
#include
#include
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
#include
#endif
@@ -271,7 +271,7 @@ static struct kobj_type ttm_pool_kobj_type = {
#ifndef CONFIG_X86
static int set_pages_array_wb(struct page **pages, int addrinarray)
{
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
int i;
for (i = 0; i < addrinarray; i++)
@@ -282,7 +282,7 @@ static int set_pages_array_wb(struct page **pages, int
addrinarray)
static int set_pages_array_wc(struct page **pages, int addrinarray)
{
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
int i;
for (i = 0; i < addrinarray; i++)
@@ -293,7 +293,7 @@ static int set_pages_array_wc(struct page **pages, int
addrinarray)
static int set_pages_array_uc(struct page **pages, int addrinarray)
{
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
int i;
for (i = 0; i < addrinarray; i++)
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index 3d4bf08aa21f..19b39cc2dcaa 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -1030,8 +1030,7 @@ extern pgprot_t ttm_io_prot(uint32_t caching_flags,
pgprot_t tmp);
extern const struct ttm_mem_type_manager_func ttm_bo_manager_func;
-#if (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE)))
-#define TTM_HAS_AGP
+#ifdef IS_ENABLED(CONFIG_AGP)
#include
/**
--
2.8.0.rc3
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/5] drm/i915: force full detect on sink count change
On Thu, 2016-03-24 at 12:21 +, Shrivastava, Shubhangi wrote:
> Hi Daniel,
>
> Is something else required for this patch series (5 patches) to be merged?
It needs to please CI. The errors reported are probably not caused by this
series, but at this point is probably better to rebase and resend. CI seems to
be a lot happier lately. :)
Ander
>
> Thanks and Regards,
> Shubhangi Shrivastava.
>
> -Original Message-
> From: Ander Conselvan De Oliveira [mailto:conselv...@gmail.com]
> Sent: Wednesday, January 20, 2016 8:07 PM
> To: Shrivastava, Shubhangi ;
> intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 5/5] drm/i915: force full detect on sink count
> change
>
> On Tue, 2016-01-19 at 16:07 +0530, Shubhangi Shrivastava wrote:
> > This patch checks for changes in sink count between short pulse hpds
> > and forces full detect when there is a change.
> >
> > This will allow both detection of hotplug and unplug of panels through
> > dongles that give only short pulse for such events.
> >
> > v2: changed variable type from u8 to bool (Jani)
> > return immediately if perform_full_detect is set(Siva)
> >
> > v3: changed method of determining full detection from using
> > pointer to return code (Siva)
> >
> > v4: changed comments to indicate meaning of return value of
> > intel_dp_short_pulse and explain the use of return value
> > from intel_dp_get_dpcd in intel_dp_short_pulse (Ander)
> >
> > Tested-by: Nathan D Ciobanu
> > Signed-off-by: Sivakumar Thulasimani
> > Signed-off-by: Shubhangi Shrivastava
>
> Reviewed-by: Ander Conselvan de Oliveira
>
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 33
> > +++--
> > 1 file changed, 27 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c index cdf4919..120d263 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4325,12 +4325,19 @@ intel_dp_check_link_status(struct intel_dp
> > *intel_dp)
> > * 2. Configure link according to Receiver Capabilities
> > * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
> > * 4. Check link status on receipt of hot-plug interrupt
> > + *
> > + * intel_dp_short_pulse - handles short pulse interrupts
> > + * when full detection is not required.
> > + * Returns %true if short pulse is handled and full detection
> > + * is NOT required and %false otherwise.
> > */
> > -static void
> > +static bool
> > intel_dp_short_pulse(struct intel_dp *intel_dp) {
> > struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > u8 sink_irq_vector;
> > + u8 old_sink_count = intel_dp->sink_count;
> > + bool ret;
> >
> > /*
> > * Clearing compliance test variables to allow capturing @@ -4340,9
> > +4347,17 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
> > intel_dp->compliance_test_type = 0;
> > intel_dp->compliance_test_data = 0;
> >
> > - /* Now read the DPCD to see if it's actually running */
> > - if (!intel_dp_get_dpcd(intel_dp)) {
> > - return;
> > + /*
> > +* Now read the DPCD to see if it's actually running
> > +* If the current value of sink count doesn't match with
> > +* the value that was stored earlier or dpcd read failed
> > +* we need to do full detection
> > +*/
> > + ret = intel_dp_get_dpcd(intel_dp);
> > +
> > + if ((old_sink_count != intel_dp->sink_count) || !ret) {
> > + /* No need to proceed if we are going to do full detect */
> > + return false;
> > }
> >
> > /* Try to read the source of the interrupt */ @@ -4362,6 +4377,8 @@
> > intel_dp_short_pulse(struct intel_dp *intel_dp)
> > drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
> > intel_dp_check_link_status(intel_dp);
> > drm_modeset_unlock(&dev->mode_config.connection_mutex);
> > +
> > + return true;
> > }
> >
> > /* XXX this is probably wrong for multiple downstream ports */ @@
> > -5086,8 +5103,12 @@ intel_dp_hpd_pulse(struct intel_digital_port
> > *intel_dig_port, bool long_hpd)
> > }
> > }
> >
> > - if (!intel_dp->is_mst)
> > - intel_dp_short_pulse(intel_dp);
> > + if (!intel_dp->is_mst) {
> > + if (!intel_dp_short_pulse(intel_dp)) {
> > + intel_dp_long_pulse(intel_dp
> > ->attached_connector);
> > + goto put_power;
> > + }
> > + }
> > }
> >
> > ret = IRQ_HANDLED;
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Re: [Intel-gfx] [PATCH] drm/i915: Remove PIPE_CONF_CHECK_I_ALT
On Wed, 30 Mar 2016, Daniel Vetter wrote:
> And move the comment to the right macro. This was mixed up in
>
> commit cfb23ed622d040619abb91e625fcba74d356b8a8
> Author: Maarten Lankhorst
> Date: Tue Jul 14 12:17:40 2015 +0200
>
> drm/i915: Allow fuzzy matching in pipe_config_compare, v2
>
> v2: Rebase.
>
> Cc: Maarten Lankhorst
> Cc: Daniel Stone
> Acked-by: Maarten Lankhorst
> Signed-off-by: Daniel Vetter
Didn't read the history, but the change is sane.
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_display.c | 22 +-
> 1 file changed, 5 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 29aa64be1f03..fec6392dfc02 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12569,6 +12569,11 @@ intel_pipe_config_compare(struct drm_device *dev,
> ret = false; \
> }
>
> +/* This is required for BDW+ where there is only one set of registers for
> + * switching between high and low RR.
> + * This macro can be used whenever a comparison has to be made between one
> + * hw state and multiple sw state variables.
> + */
> #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
> if (!intel_compare_link_m_n(¤t_config->name, \
> &pipe_config->name, adjust) && \
> @@ -12596,22 +12601,6 @@ intel_pipe_config_compare(struct drm_device *dev,
> ret = false; \
> }
>
> -/* This is required for BDW+ where there is only one set of registers for
> - * switching between high and low RR.
> - * This macro can be used whenever a comparison has to be made between one
> - * hw state and multiple sw state variables.
> - */
> -#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
> - if ((current_config->name != pipe_config->name) && \
> - (current_config->alt_name != pipe_config->name)) { \
> - INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
> - "(expected %i or %i, found %i)\n", \
> - current_config->name, \
> - current_config->alt_name, \
> - pipe_config->name); \
> - ret = false; \
> - }
> -
> #define PIPE_CONF_CHECK_FLAGS(name, mask)\
> if ((current_config->name ^ pipe_config->name) & (mask)) { \
> INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
> @@ -12736,7 +12725,6 @@ intel_pipe_config_compare(struct drm_device *dev,
> #undef PIPE_CONF_CHECK_X
> #undef PIPE_CONF_CHECK_I
> #undef PIPE_CONF_CHECK_P
> -#undef PIPE_CONF_CHECK_I_ALT
> #undef PIPE_CONF_CHECK_FLAGS
> #undef PIPE_CONF_CHECK_CLOCK_FUZZY
> #undef PIPE_CONF_QUIRK
--
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [v2] drm/i915: Rename GGTT init functions (rev3)
On to, 2016-03-24 at 17:02 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v2] drm/i915: Rename GGTT init functions (rev3)
> URL : https://patchwork.freedesktop.org/series/4790/
> State : warning
>
> == Summary ==
>
> Series 4790v3 Series without cover letter
> http://patchwork.freedesktop.org/api/1.0/series/4790/revisions/3/mbox/
>
> Test gem_exec_basic:
> Subgroup gtt-blt:
> pass -> DMESG-WARN (bsw-nuc-2)
[drm:intel_runtime_suspend [i915]] *ERROR* Unclaimed access detected
prior to suspending
Problem in BSW/BYT runtime PM, reported at:
https://bugs.freedesktop.org/show_bug.cgi?id=94164
> Test pm_rpm:
> Subgroup basic-rte:
> pass -> DMESG-WARN (bsw-nuc-2)
"==
[ INFO: possible circular locking dependency detected ]
4.5.0-gfxbench+ #1 Not tainted
---
gem_exec_basic/5896 is trying to acquire lock:
(&dev->struct_mutex){+.+.+.}, at: []
drm_gem_mmap+0x1a1/0x270
but task is already holding lock:
(&mm->mmap_sem){++}, at: []
vm_mmap_pgoff+0x44/0xa0
which lock already depends on the new lock."
Lockdep issue (completely unrelated to renaming functions :P), this
whole chain causing multiple splats is being worked on. Opened a bug to
track this specific warn:
https://bugs.freedesktop.org/show_bug.cgi?id=94759
Regards, Joonas
>
> bdw-nuci7total:192 pass:179 dwarn:0 dfail:0 fail:1 skip:12
> bdw-ultratotal:192 pass:170 dwarn:0 dfail:0 fail:1 skip:21
> bsw-nuc-2total:192 pass:153 dwarn:2 dfail:0 fail:0 skip:37
> byt-nuc total:192 pass:156 dwarn:1 dfail:0 fail:0 skip:35
> hsw-brixbox total:192 pass:170 dwarn:0 dfail:0 fail:0 skip:22
> hsw-gt2 total:192 pass:175 dwarn:0 dfail:0 fail:0 skip:17
> ivb-t430stotal:192 pass:167 dwarn:0 dfail:0 fail:0 skip:25
> skl-i7k-2total:192 pass:169 dwarn:0 dfail:0 fail:0 skip:23
> skl-nuci5total:192 pass:181 dwarn:0 dfail:0 fail:0 skip:11
> snb-dellxps total:192 pass:158 dwarn:0 dfail:0 fail:0 skip:34
> snb-x220ttotal:192 pass:158 dwarn:0 dfail:0 fail:1 skip:33
>
> Results at /archive/results/CI_IGT_test/Patchwork_1712/
>
> f5d413cccefa1f93d64c34f357151d42add63a84 drm-intel-nightly:
> 2016y-03m-24d-14h-34m-29s UTC integration manifest
> 9a1fb4808f9bc1219d05bf79c4a90079c246e7ed drm/i915: Refer to GGTT VM
> consistently
> 4351646d82c63100310f5d4e437c2f8a4435c9a7 drm/i915: Rename GGTT init functions
>
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH 03/10] drm/armada: Drop fb gamma_set/get functions
On Wed, Mar 30, 2016 at 11:51:18AM +0200, Daniel Vetter wrote: > The fb helper private gamma_set/get functions are only required when > the driver supports paletted 8bit mode with fbdev. Armada uses 32bpp > unconditionally, so this is just dead code. It also doesn't do > anything really. Let's just remove it. This comment is misleading: Armada supports 16bpp formats as well as 32bpp, and the hardware does have 8bpp modes to, but I've chosen not to support the 8bpp modes. -- RMK's Patch system: http://www.arm.linux.org.uk/developer/patches/ FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/10] drm/armada: Drop fb gamma_set/get functions
On Wed, Mar 30, 2016 at 1:09 PM, Russell King - ARM Linux wrote: > On Wed, Mar 30, 2016 at 11:51:18AM +0200, Daniel Vetter wrote: >> The fb helper private gamma_set/get functions are only required when >> the driver supports paletted 8bit mode with fbdev. Armada uses 32bpp >> unconditionally, so this is just dead code. It also doesn't do >> anything really. Let's just remove it. > > This comment is misleading: Armada supports 16bpp formats as well as > 32bpp, and the hardware does have 8bpp modes to, but I've chosen not > to support the 8bpp modes. This is purely about the fbdev emulation (and yeah need to clarify that), not about kms support in general. And these two gamma_set/get hooks are _only_ used by the fbdev emulation, and only needed if you do 8bit paletted mode. Ok if I change the commit message to "Armada used 32bpp unconditionally for fbdev emulation, ..."? -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/ttm: Remove TTM_HAS_AGP
Hi Daniel, [auto build test WARNING on drm/drm-next] [also build test WARNING on v4.6-rc1 next-20160330] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url: https://github.com/0day-ci/linux/commits/Daniel-Vetter/drm-ttm-Remove-TTM_HAS_AGP/20160330-191030 base: git://people.freedesktop.org/~airlied/linux.git drm-next config: sparc64-allyesconfig (attached as .config) reproduce: wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree make.cross ARCH=sparc64 All warnings (new ones prefixed by >>): In file included from include/drm/ttm/ttm_page_alloc.h:29:0, from drivers/gpu/drm/ttm/ttm_memory.c:32: >> include/drm/ttm/ttm_bo_driver.h:1033:18: warning: extra tokens at end of >> #ifdef directive #ifdef IS_ENABLED(CONFIG_AGP) ^ In file included from include/drm/ttm/ttm_page_alloc.h:29:0, from drivers/gpu/drm/ttm/ttm_memory.c:32: >> include/drm/ttm/ttm_bo_driver.h:1033:18: warning: extra tokens at end of >> #ifdef directive #ifdef IS_ENABLED(CONFIG_AGP) ^ vim +1033 include/drm/ttm/ttm_bo_driver.h 1017 struct fence *fence, 1018 bool evict, bool no_wait_gpu, 1019 struct ttm_mem_reg *new_mem); 1020 /** 1021 * ttm_io_prot 1022 * 1023 * @c_state: Caching state. 1024 * @tmp: Page protection flag for a normal, cached mapping. 1025 * 1026 * Utility function that returns the pgprot_t that should be used for 1027 * setting up a PTE with the caching model indicated by @c_state. 1028 */ 1029 extern pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp); 1030 1031 extern const struct ttm_mem_type_manager_func ttm_bo_manager_func; 1032 > 1033 #ifdef IS_ENABLED(CONFIG_AGP) 1034 #include 1035 1036 /** 1037 * ttm_agp_tt_create 1038 * 1039 * @bdev: Pointer to a struct ttm_bo_device. 1040 * @bridge: The agp bridge this device is sitting on. 1041 * @size: Size of the data needed backing. --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation .config.gz Description: Binary data ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/ttm: Remove TTM_HAS_AGP
It tries to do fancy things with excluding agp support if ttm is
built-in, but agp isn't. Instead just express this depency like drm
does and use CONFIG_AGP everywhere.
Also use the neat Makefile magic to make the entire ttm_agp_backend
file optional.
v2: Use IS_ENABLED(CONFIG_AGP) as suggested by Ville
v3: Review from Emil.
v4: Actually get it right as spotted by 0-day.
Cc: Emil Velikov
Cc: Ville Syrjälä
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/ttm/Makefile | 3 ++-
drivers/gpu/drm/ttm/ttm_agp_backend.c| 3 ---
drivers/gpu/drm/ttm/ttm_page_alloc.c | 8
drivers/gpu/drm/ttm/ttm_page_alloc_dma.c | 8
include/drm/ttm/ttm_bo_driver.h | 3 +--
5 files changed, 11 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/ttm/Makefile b/drivers/gpu/drm/ttm/Makefile
index b433b9f040c9..f92325800f8a 100644
--- a/drivers/gpu/drm/ttm/Makefile
+++ b/drivers/gpu/drm/ttm/Makefile
@@ -2,9 +2,10 @@
# Makefile for the drm device driver. This driver provides support for the
ccflags-y := -Iinclude/drm
-ttm-y := ttm_agp_backend.o ttm_memory.o ttm_tt.o ttm_bo.o \
+ttm-y := ttm_memory.o ttm_tt.o ttm_bo.o \
ttm_bo_util.o ttm_bo_vm.o ttm_module.o \
ttm_object.o ttm_lock.o ttm_execbuf_util.o ttm_page_alloc.o \
ttm_bo_manager.o ttm_page_alloc_dma.o
+ttm-$(CONFIG_AGP) += ttm_agp_backend.o
obj-$(CONFIG_DRM_TTM) += ttm.o
diff --git a/drivers/gpu/drm/ttm/ttm_agp_backend.c
b/drivers/gpu/drm/ttm/ttm_agp_backend.c
index 764be36397fd..028ab6007873 100644
--- a/drivers/gpu/drm/ttm/ttm_agp_backend.c
+++ b/drivers/gpu/drm/ttm/ttm_agp_backend.c
@@ -34,7 +34,6 @@
#include
#include
#include
-#ifdef TTM_HAS_AGP
#include
#include
#include
@@ -148,5 +147,3 @@ void ttm_agp_tt_unpopulate(struct ttm_tt *ttm)
ttm_pool_unpopulate(ttm);
}
EXPORT_SYMBOL(ttm_agp_tt_unpopulate);
-
-#endif
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c
b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index 025c429050c0..a37de5db5731 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -48,7 +48,7 @@
#include
#include
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
#include
#endif
@@ -219,7 +219,7 @@ static struct ttm_pool_manager *_manager;
#ifndef CONFIG_X86
static int set_pages_array_wb(struct page **pages, int addrinarray)
{
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
int i;
for (i = 0; i < addrinarray; i++)
@@ -230,7 +230,7 @@ static int set_pages_array_wb(struct page **pages, int
addrinarray)
static int set_pages_array_wc(struct page **pages, int addrinarray)
{
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
int i;
for (i = 0; i < addrinarray; i++)
@@ -241,7 +241,7 @@ static int set_pages_array_wc(struct page **pages, int
addrinarray)
static int set_pages_array_uc(struct page **pages, int addrinarray)
{
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
int i;
for (i = 0; i < addrinarray; i++)
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
index 624d941aaad1..bef9f6feb635 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c
@@ -50,7 +50,7 @@
#include
#include
#include
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
#include
#endif
@@ -271,7 +271,7 @@ static struct kobj_type ttm_pool_kobj_type = {
#ifndef CONFIG_X86
static int set_pages_array_wb(struct page **pages, int addrinarray)
{
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
int i;
for (i = 0; i < addrinarray; i++)
@@ -282,7 +282,7 @@ static int set_pages_array_wb(struct page **pages, int
addrinarray)
static int set_pages_array_wc(struct page **pages, int addrinarray)
{
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
int i;
for (i = 0; i < addrinarray; i++)
@@ -293,7 +293,7 @@ static int set_pages_array_wc(struct page **pages, int
addrinarray)
static int set_pages_array_uc(struct page **pages, int addrinarray)
{
-#ifdef TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
int i;
for (i = 0; i < addrinarray; i++)
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index 3d4bf08aa21f..cb91f80c15b3 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -1030,8 +1030,7 @@ extern pgprot_t ttm_io_prot(uint32_t caching_flags,
pgprot_t tmp);
extern const struct ttm_mem_type_manager_func ttm_bo_manager_func;
-#if (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE)))
-#define TTM_HAS_AGP
+#if IS_ENABLED(CONFIG_AGP)
#include
/**
--
2.8.0.rc3
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Re: [Intel-gfx] [PATCH 3/2] drm/i915: Rename hw state checker to hw state verifier.
On Wed, Mar 30, 2016 at 10:00:05AM +0200, Maarten Lankhorst wrote:
> Check functions are used by atomic to see if the new state will
> be allowed. There's also a hw state checker which checks afterwards
> that the committed state is correct. Rename it to hw state verifier
> to reduce some confusion.
>
> Suggested-by: Matt Roper
> Signed-off-by: Maarten Lankhorst
Great idea!
Acked-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/intel_display.c | 60
> ++--
> 1 file changed, 30 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 9e63720428fc..8b423cdd5295 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6283,7 +6283,7 @@ void intel_encoder_destroy(struct drm_encoder *encoder)
>
> /* Cross check the actual hw state with our own modeset state tracking (and
> it's
> * internal consistency). */
> -static void intel_connector_check_state(struct intel_connector *connector)
> +static void intel_connector_verify_state(struct intel_connector *connector)
> {
> struct drm_crtc *crtc = connector->base.state->crtc;
>
> @@ -12752,8 +12752,8 @@ static void intel_pipe_config_sanity_check(struct
> drm_i915_private *dev_priv,
> }
> }
>
> -static void check_wm_state(struct drm_crtc *crtc,
> -struct drm_crtc_state *new_state)
> +static void verify_wm_state(struct drm_crtc *crtc,
> + struct drm_crtc_state *new_state)
> {
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -12798,7 +12798,7 @@ static void check_wm_state(struct drm_crtc *crtc,
> }
>
> static void
> -check_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
> +verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
> {
> struct drm_connector *connector;
>
> @@ -12809,7 +12809,7 @@ check_connector_state(struct drm_device *dev, struct
> drm_crtc *crtc)
> if (state->crtc != crtc)
> continue;
>
> - intel_connector_check_state(to_intel_connector(connector));
> + intel_connector_verify_state(to_intel_connector(connector));
>
> I915_STATE_WARN(state->best_encoder != encoder,
>"connector's atomic encoder doesn't match legacy
> encoder\n");
> @@ -12817,7 +12817,7 @@ check_connector_state(struct drm_device *dev, struct
> drm_crtc *crtc)
> }
>
> static void
> -check_encoder_state(struct drm_device *dev)
> +verify_encoder_state(struct drm_device *dev)
> {
> struct intel_encoder *encoder;
> struct intel_connector *connector;
> @@ -12857,9 +12857,9 @@ check_encoder_state(struct drm_device *dev)
> }
>
> static void
> -check_crtc_state(struct drm_crtc *crtc,
> - struct drm_crtc_state *old_crtc_state,
> - struct drm_crtc_state *new_crtc_state)
> +verify_crtc_state(struct drm_crtc *crtc,
> + struct drm_crtc_state *old_crtc_state,
> + struct drm_crtc_state *new_crtc_state)
> {
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -12926,10 +12926,10 @@ check_crtc_state(struct drm_crtc *crtc,
> }
>
> static void
> -check_single_dpll_state(struct drm_i915_private *dev_priv,
> - struct intel_shared_dpll *pll,
> - struct drm_crtc *crtc,
> - struct drm_crtc_state *new_state)
> +verify_single_dpll_state(struct drm_i915_private *dev_priv,
> + struct intel_shared_dpll *pll,
> + struct drm_crtc *crtc,
> + struct drm_crtc_state *new_state)
> {
> struct intel_dpll_hw_state dpll_hw_state;
> unsigned crtc_mask;
> @@ -12981,16 +12981,16 @@ check_single_dpll_state(struct drm_i915_private
> *dev_priv,
> }
>
> static void
> -check_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
> - struct drm_crtc_state *old_crtc_state,
> - struct drm_crtc_state *new_crtc_state)
> +verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
> + struct drm_crtc_state *old_crtc_state,
> + struct drm_crtc_state *new_crtc_state)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc_state *old_state =
> to_intel_crtc_state(old_crtc_state);
> struct intel_crtc_state *new_state =
> to_intel_crtc_state(new_crtc_state);
>
> if (new_state->shared_dpll)
> - check_single_dpll_state(dev_priv, new_state->shared_dpll, crtc,
> new_crtc_state);
> + verify_single_dpll_state(dev_priv, new_state->shared_dpll,
> crtc, new_crtc_state);
>
> if (old_state->shared_dpll &&
> old_state->shared_dpll != new_state->shared_dpll)
Re: [Intel-gfx] [PATCH 08/10] x86/cpufeature: Kill cpu_has_pat
On Tue, Mar 29, 2016 at 05:42:01PM +0200, Borislav Petkov wrote:
> From: Borislav Petkov
>
> Signed-off-by: Borislav Petkov
> Cc: intel-gfx@lists.freedesktop.org
Acked-by: Daniel Vetter
> ---
>
> @tip guys, the pat_bsp_init() and pat_ap_init() hunk will conflict with
>
> d63dcf49cf5a ("x86/mm/pat: Replace cpu_has_pat with boot_cpu_has()")
>
> in tip/x86:mm. Let me know how you wanna handle it. Or you can simply
> delete those hunks below when applying after merging the above branch.
> Or I can send this patch later... Yadda yadda.
>
> arch/x86/include/asm/cpufeature.h | 1 -
> arch/x86/mm/pat.c | 4 ++--
> drivers/gpu/drm/i915/i915_gem.c | 2 +-
> 3 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/arch/x86/include/asm/cpufeature.h
> b/arch/x86/include/asm/cpufeature.h
> index 5e02bc2e8444..ad480c5fb27c 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -128,7 +128,6 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
> #define cpu_has_aes boot_cpu_has(X86_FEATURE_AES)
> #define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX)
> #define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2)
> -#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
> #define cpu_has_xsaveboot_cpu_has(X86_FEATURE_XSAVE)
> #define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES)
> /*
> diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c
> index faec01e7a17d..6df20ac83ec3 100644
> --- a/arch/x86/mm/pat.c
> +++ b/arch/x86/mm/pat.c
> @@ -202,7 +202,7 @@ static void pat_bsp_init(u64 pat)
> {
> u64 tmp_pat;
>
> - if (!cpu_has_pat) {
> + if (!boot_cpu_has(X86_FEATURE_PAT)) {
> pat_disable("PAT not supported by CPU.");
> return;
> }
> @@ -227,7 +227,7 @@ static void pat_ap_init(u64 pat)
> if (!pat_enabled())
> return;
>
> - if (!cpu_has_pat) {
> + if (!boot_cpu_has(X86_FEATURE_PAT)) {
> /*
>* If this happens we are on a secondary CPU, but switched to
>* PAT on the boot CPU. We have no way to undo PAT.
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 3d31d3ac589e..aaec8aef9fd4 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1732,7 +1732,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
> if (args->flags & ~(I915_MMAP_WC))
> return -EINVAL;
>
> - if (args->flags & I915_MMAP_WC && !cpu_has_pat)
> + if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
> return -ENODEV;
>
> obj = drm_gem_object_lookup(dev, file, args->handle);
> --
> 2.7.3
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
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http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/BXT: Tolerance at BXT DSI pipe_config comparison
On Tue, Mar 29, 2016 at 11:04:51PM +0530, Ramalingam C wrote:
> At BXT DSI, PIPE registers are inactive. So we can't get the
> PIPE's mode parameters from them. The possible option is
> retriving them from the PORT registers. But mode timing
> parameters are progammed to port registers interms of byteclocks.
>
> The formula used to convert the pixels interms of byteclk is
> DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
> 8 * 100), lane_count);
>
> So we retrieve them, interms of pixels as
> DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
> (bpp * burst_mode_ratio));
>
> Due to the multiple DIV_ROUND_UP in both formulas we get the worst
> case delta in the retrieved PIPE's timing parameter as below
> DIV_ROUND_UP((8 * intel_dsi->lane_count * 100),
> (dsi_pixel_format_bpp(intel_dsi->pixel_format) *
> intel_dsi->burst_mode_ratio)))
>
> This converson of byteclk to pixel is required for hsync, hfp and hbp.
> Which intern impacts horrizontal timing parameters. At worst case to
> get htotal all there parameters are added with hactive.
> Hence delta will be 3 times of above formula. Hence this value is
> considered as tolerance for pipe_config comparison, in case of BXT DSI.
>
> Signed-off-by: Ramalingam C
This is the wrong way round imo, better would be to adjust the adjusted
mode in the bxt dsi compute_config function to match the hw granularity.
Stuff _really_ should match exactly, the fuzzy clock matching is mostly
because our clock cod is a mess, and we can't/don't properly
forward-compuate the actual clock timings we program into the hardware.
-Daniel
> ---
> Reviewed at
> https://lists.freedesktop.org/archives/intel-gfx/2016-March/089548.html
>
> drivers/gpu/drm/i915/intel_display.c | 62
> +++---
> 1 file changed, 57 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index c0627d6..282f036 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12557,6 +12557,9 @@ intel_pipe_config_compare(struct drm_device *dev,
> bool adjust)
> {
> bool ret = true;
> + struct intel_crtc *crtc = to_intel_crtc(current_config->base.crtc);
> + struct intel_encoder *intel_encoder;
> + struct intel_dsi *intel_dsi = NULL;
>
> #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
> do { \
> @@ -12593,6 +12596,54 @@ intel_pipe_config_compare(struct drm_device *dev,
> ret = false; \
> }
>
> +/*
> + * In case of BXT DSI, HW pipe_config will be retrieved from the port's
> timing
> + * configuration. This retrival includes some errors due to the DIV_ROUND_UP.
> + * So we are considering the max possible error at the comparison.
> + */
> +/*
> + * htotal = hactive + hfp + hsync + hbp. Here last three lements might have
> + * the converson error, hence we consider the 3 times of error as tolerance.
> + */
> +
> +#define MAX_BXT_DSI_TIMING_RETRIVAL_ERR \
> + (intel_dsi == NULL ? 0 : \
> + DIV_ROUND_UP((3 * 8 * intel_dsi->lane_count * 100), \
> + (dsi_pixel_format_bpp(intel_dsi->pixel_format) * \
> + intel_dsi->burst_mode_ratio)))
> +
> +#define BXT_DSI_PIPE_CONF_CHECK_I_RANGE(name) { \
> + for_each_encoder_on_crtc(dev, &crtc->base, \
> + intel_encoder) { \
> + if (intel_encoder->type == INTEL_OUTPUT_DSI) { \
> + intel_dsi = enc_to_intel_dsi(&intel_encoder->base); \
> + } \
> + } \
> + if (!(current_config->name < pipe_config->name && \
> + current_config->name >= (pipe_config->name - \
> + MAX_BXT_DSI_TIMING_RETRIVAL_ERR))) { \
> + INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
> + "(expected %i, found %i(Err tolerance considered))\n", \
> + current_config->name, \
> + pipe_config->name); \
> + ret = false; \
> + } \
> +}
> +
> +#define PIPE_CONF_CHECK_I_RANGE(name) { \
> + if (current_config->name != pipe_config->name) { \
> + if (IS_BROXTON(dev) && crtc->config->has_dsi_encoder) { \
> + BXT_DSI_PIPE_CONF_CHECK_I_RANGE(name) \
> + } else { \
> + INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
> + "(expected %i, found %i)\n", \
> + current_config->name, \
> + pipe_config->name); \
> + ret = false; \
> + } \
> + } \
> +}
> +
> #define PIPE_CONF_CHECK_M_N(name) \
> if (!intel_compare_link_m_n(¤t_config->name, \
> &pipe_config->name,\
> @@ -12697,11 +12748,11 @@ intel_pipe_config_compare(struct drm_device *dev,
>
Re: [Intel-gfx] [PATCH] drm/i915: Remove PIPE_CONF_CHECK_I_ALT
On Wed, Mar 30, 2016 at 02:09:11PM +0300, Jani Nikula wrote:
> On Wed, 30 Mar 2016, Daniel Vetter wrote:
> > And move the comment to the right macro. This was mixed up in
> >
> > commit cfb23ed622d040619abb91e625fcba74d356b8a8
> > Author: Maarten Lankhorst
> > Date: Tue Jul 14 12:17:40 2015 +0200
> >
> > drm/i915: Allow fuzzy matching in pipe_config_compare, v2
> >
> > v2: Rebase.
> >
> > Cc: Maarten Lankhorst
> > Cc: Daniel Stone
> > Acked-by: Maarten Lankhorst
> > Signed-off-by: Daniel Vetter
>
> Didn't read the history, but the change is sane.
>
> Reviewed-by: Jani Nikula
Queued for -next, thanks for the patch.
-Daniel
>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 22 +-
> > 1 file changed, 5 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 29aa64be1f03..fec6392dfc02 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -12569,6 +12569,11 @@ intel_pipe_config_compare(struct drm_device *dev,
> > ret = false; \
> > }
> >
> > +/* This is required for BDW+ where there is only one set of registers for
> > + * switching between high and low RR.
> > + * This macro can be used whenever a comparison has to be made between one
> > + * hw state and multiple sw state variables.
> > + */
> > #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
> > if (!intel_compare_link_m_n(¤t_config->name, \
> > &pipe_config->name, adjust) && \
> > @@ -12596,22 +12601,6 @@ intel_pipe_config_compare(struct drm_device *dev,
> > ret = false; \
> > }
> >
> > -/* This is required for BDW+ where there is only one set of registers for
> > - * switching between high and low RR.
> > - * This macro can be used whenever a comparison has to be made between one
> > - * hw state and multiple sw state variables.
> > - */
> > -#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
> > - if ((current_config->name != pipe_config->name) && \
> > - (current_config->alt_name != pipe_config->name)) { \
> > - INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
> > - "(expected %i or %i, found %i)\n", \
> > - current_config->name, \
> > - current_config->alt_name, \
> > - pipe_config->name); \
> > - ret = false; \
> > - }
> > -
> > #define PIPE_CONF_CHECK_FLAGS(name, mask) \
> > if ((current_config->name ^ pipe_config->name) & (mask)) { \
> > INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
> > @@ -12736,7 +12725,6 @@ intel_pipe_config_compare(struct drm_device *dev,
> > #undef PIPE_CONF_CHECK_X
> > #undef PIPE_CONF_CHECK_I
> > #undef PIPE_CONF_CHECK_P
> > -#undef PIPE_CONF_CHECK_I_ALT
> > #undef PIPE_CONF_CHECK_FLAGS
> > #undef PIPE_CONF_CHECK_CLOCK_FUZZY
> > #undef PIPE_CONF_QUIRK
>
> --
> Jani Nikula, Intel Open Source Technology Center
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH v3 (rebased) 4/4] drm/i915: Add locking to pll updates, v3.
On Wed, 2016-03-23 at 14:51 +0100, Maarten Lankhorst wrote:
> With async modesets this is no longer protected with connection_mutex,
> so ensure that each pll has its own lock. The pll configuration state
> is still protected; it's only the pll updates that need locking against
> concurrency.
>
> Changes since v1:
> - Rebased.
> - Fix locking to protect all accesses. (Durgadoss)
> Changes since v2:
> - Make the dpll_lock global to protect concurrent updates to the
> same register, for example DPLL_CTRL1 on skl. (Ander)
>
> Signed-off-by: Maarten Lankhorst
Reviewed-by: Ander Conselvan de Oliveira
> ---
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 06e4773ae7f6..a66732744494 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1854,6 +1854,13 @@ struct drm_i915_private {
> struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
> const struct intel_dpll_mgr *dpll_mgr;
>
> + /*
> + * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
> + * Must be global rather than per dpll, because on some platforms
> + * plls share registers.
> + */
> + struct mutex dpll_lock;
> +
> unsigned int active_crtcs;
> unsigned int min_pixclk[I915_MAX_PIPES];
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 19bfe6743ef2..1175eebfe03b 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -89,14 +89,16 @@ void intel_prepare_shared_dpll(struct intel_crtc *crtc)
> if (WARN_ON(pll == NULL))
> return;
>
> + mutex_lock(&dev_priv->dpll_lock);
> WARN_ON(!pll->config.crtc_mask);
> - if (pll->active_mask == 0) {
> + if (!pll->active_mask) {
> DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
> WARN_ON(pll->on);
> assert_shared_dpll_disabled(dev_priv, pll);
>
> pll->funcs.mode_set(dev_priv, pll);
> }
> + mutex_unlock(&dev_priv->dpll_lock);
> }
>
> /**
> @@ -113,14 +115,17 @@ void intel_enable_shared_dpll(struct intel_crtc *crtc)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_shared_dpll *pll = crtc->config->shared_dpll;
> unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base);
> - unsigned old_mask = pll->active_mask;
> + unsigned old_mask;
>
> if (WARN_ON(pll == NULL))
> return;
>
> + mutex_lock(&dev_priv->dpll_lock);
> + old_mask = pll->active_mask;
> +
> if (WARN_ON(!(pll->config.crtc_mask & crtc_mask)) ||
> WARN_ON(pll->active_mask & crtc_mask))
> - return;
> + goto out;
>
> pll->active_mask |= crtc_mask;
>
> @@ -131,13 +136,16 @@ void intel_enable_shared_dpll(struct intel_crtc *crtc)
> if (old_mask) {
> WARN_ON(!pll->on);
> assert_shared_dpll_enabled(dev_priv, pll);
> - return;
> + goto out;
> }
> WARN_ON(pll->on);
>
> DRM_DEBUG_KMS("enabling %s\n", pll->name);
> pll->funcs.enable(dev_priv, pll);
> pll->on = true;
> +
> +out:
> + mutex_unlock(&dev_priv->dpll_lock);
> }
>
> void intel_disable_shared_dpll(struct intel_crtc *crtc)
> @@ -154,8 +162,9 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc)
> if (pll == NULL)
> return;
>
> + mutex_lock(&dev_priv->dpll_lock);
> if (WARN_ON(!(pll->active_mask & crtc_mask)))
> - return;
> + goto out;
>
> DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n",
> pll->name, pll->active_mask, pll->on,
> @@ -166,11 +175,14 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc)
>
> pll->active_mask &= ~crtc_mask;
> if (pll->active_mask)
> - return;
> + goto out;
>
> DRM_DEBUG_KMS("disabling %s\n", pll->name);
> pll->funcs.disable(dev_priv, pll);
> pll->on = false;
> +
> +out:
> + mutex_unlock(&dev_priv->dpll_lock);
> }
>
> static struct intel_shared_dpll *
> @@ -1750,6 +1762,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
>
> dev_priv->dpll_mgr = dpll_mgr;
> dev_priv->num_shared_dpll = i;
> + mutex_init(&dev_priv->dpll_lock);
>
> BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
>
>
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[Intel-gfx] [PATCH v3] drm/i915: Refer to GGTT VM consistently
Refer to the GGTT VM consistently as "ggtt->base" instead of just "ggtt",
"vm" or indirectly through other variables like "dev_priv->ggtt.base"
to avoid confusion with the i915_ggtt object itself and PPGTT VMs.
As a bonus gets rid of the long-standing i915_obj_to_ggtt vs.
i915_gem_obj_to_ggtt conflict, due to removal of i915_obj_to_ggtt!
v2:
- Added some more after grepping sources with Chris
v3:
- Refer to GGTT VM through ggtt->base consistently instead of ggtt_vm
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Chris Wilson
Signed-off-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c| 15 +++---
drivers/gpu/drm/i915/i915_drv.h| 15 --
drivers/gpu/drm/i915/i915_gem.c| 31
drivers/gpu/drm/i915/i915_gem_gtt.c| 93 +-
drivers/gpu/drm/i915/i915_gem_stolen.c | 10 ++--
drivers/gpu/drm/i915/i915_vgpu.c | 24 -
6 files changed, 102 insertions(+), 86 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index d02f8ce..cd7c4ed 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -203,7 +203,7 @@ static int i915_gem_object_list_info(struct seq_file *m,
void *data)
struct list_head *head;
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct i915_address_space *vm = &dev_priv->ggtt.base;
+ struct i915_ggtt *ggtt = &dev_priv->ggtt;
struct i915_vma *vma;
u64 total_obj_size, total_gtt_size;
int count, ret;
@@ -216,11 +216,11 @@ static int i915_gem_object_list_info(struct seq_file *m,
void *data)
switch (list) {
case ACTIVE_LIST:
seq_puts(m, "Active:\n");
- head = &vm->active_list;
+ head = &ggtt->base.active_list;
break;
case INACTIVE_LIST:
seq_puts(m, "Inactive:\n");
- head = &vm->inactive_list;
+ head = &ggtt->base.inactive_list;
break;
default:
mutex_unlock(&dev->struct_mutex);
@@ -430,10 +430,10 @@ static int i915_gem_object_info(struct seq_file *m, void*
data)
struct drm_info_node *node = m->private;
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct i915_ggtt *ggtt = &dev_priv->ggtt;
u32 count, mappable_count, purgeable_count;
u64 size, mappable_size, purgeable_size;
struct drm_i915_gem_object *obj;
- struct i915_address_space *vm = &dev_priv->ggtt.base;
struct drm_file *file;
struct i915_vma *vma;
int ret;
@@ -452,12 +452,12 @@ static int i915_gem_object_info(struct seq_file *m, void*
data)
count, mappable_count, size, mappable_size);
size = count = mappable_size = mappable_count = 0;
- count_vmas(&vm->active_list, vm_link);
+ count_vmas(&ggtt->base.active_list, vm_link);
seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
count, mappable_count, size, mappable_size);
size = count = mappable_size = mappable_count = 0;
- count_vmas(&vm->inactive_list, vm_link);
+ count_vmas(&ggtt->base.inactive_list, vm_link);
seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
count, mappable_count, size, mappable_size);
@@ -492,8 +492,7 @@ static int i915_gem_object_info(struct seq_file *m, void*
data)
count, size);
seq_printf(m, "%llu [%llu] gtt total\n",
- dev_priv->ggtt.base.total,
- (u64)dev_priv->ggtt.mappable_end -
dev_priv->ggtt.base.start);
+ ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
seq_putc(m, '\n');
print_batch_pool_stats(m, dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f6d7159..ffe0908 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3147,9 +3147,6 @@ i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
/* Some GGTT VM helpers */
-#define i915_obj_to_ggtt(obj) \
- (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->ggtt.base)
-
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
@@ -3166,7 +3163,11 @@ static inline bool i915_gem_obj_ggtt_bound(struct
drm_i915_gem_object *obj)
static inline unsigned long
i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
{
- return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
+ struct drm_device *dev = obj->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct i915_ggtt *ggtt = &dev_priv->ggtt;
+
+ return i915_gem_obj_size(obj, &ggtt->base);
}
static inline int __
[Intel-gfx] [PATCH 5/5] drm/i915: force full detect on sink count change
This patch checks for changes in sink count between short pulse
hpds and forces full detect when there is a change.
This will allow both detection of hotplug and unplug of panels
through dongles that give only short pulse for such events.
v2: changed variable type from u8 to bool (Jani)
return immediately if perform_full_detect is set(Siva)
v3: changed method of determining full detection from using
pointer to return code (Siva)
v4: changed comments to indicate meaning of return value of
intel_dp_short_pulse and explain the use of return value
from intel_dp_get_dpcd in intel_dp_short_pulse (Ander)
Tested-by: Nathan D Ciobanu
Signed-off-by: Sivakumar Thulasimani
Signed-off-by: Shubhangi Shrivastava
Reviewed-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_dp.c | 33 +++--
1 file changed, 27 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9b2b96f..538bc02 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4273,12 +4273,19 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
* 2. Configure link according to Receiver Capabilities
* 3. Use Link Training from 2.5.3.3 and 3.5.1.3
* 4. Check link status on receipt of hot-plug interrupt
+ *
+ * intel_dp_short_pulse - handles short pulse interrupts
+ * when full detection is not required.
+ * Returns %true if short pulse is handled and full detection
+ * is NOT required and %false otherwise.
*/
-static void
+static bool
intel_dp_short_pulse(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
u8 sink_irq_vector;
+ u8 old_sink_count = intel_dp->sink_count;
+ bool ret;
/*
* Clearing compliance test variables to allow capturing
@@ -4288,9 +4295,17 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
intel_dp->compliance_test_type = 0;
intel_dp->compliance_test_data = 0;
- /* Now read the DPCD to see if it's actually running */
- if (!intel_dp_get_dpcd(intel_dp)) {
- return;
+ /*
+* Now read the DPCD to see if it's actually running
+* If the current value of sink count doesn't match with
+* the value that was stored earlier or dpcd read failed
+* we need to do full detection
+*/
+ ret = intel_dp_get_dpcd(intel_dp);
+
+ if ((old_sink_count != intel_dp->sink_count) || !ret) {
+ /* No need to proceed if we are going to do full detect */
+ return false;
}
/* Try to read the source of the interrupt */
@@ -4310,6 +4325,8 @@ intel_dp_short_pulse(struct intel_dp *intel_dp)
drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
intel_dp_check_link_status(intel_dp);
drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+ return true;
}
/* XXX this is probably wrong for multiple downstream ports */
@@ -5043,8 +5060,12 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
}
}
- if (!intel_dp->is_mst)
- intel_dp_short_pulse(intel_dp);
+ if (!intel_dp->is_mst) {
+ if (!intel_dp_short_pulse(intel_dp)) {
+
intel_dp_long_pulse(intel_dp->attached_connector);
+ goto put_power;
+ }
+ }
}
ret = IRQ_HANDLED;
--
2.6.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/5] drm/i915: Reorganizing intel_dp_check_link_status
When created originally intel_dp_check_link_status()
was supposed to handle only link training for short
pulse but has grown into handler for short pulse itself.
This patch cleans up this function by splitting it into
two halves. First intel_dp_short_pulse() is called,
which will be entry point and handle all logic for
short pulse handling while intel_dp_check_link_status()
will retain its original purpose of only doing link
status related work.
intel_dp_short_pulse: All existing code other than
link status read and link training upon error status.
intel_dp_check_link_status:
The link status should be read on short pulse
irrespective of panel being enabled or not so
intel_dp_get_link_status() performs dpcd read first
then based on crtc active / enabled it will
perform the link training.
This is because short pulse is a generic interrupt
which should always be handled, because it may mean:
1. Hotplug/unplug of MST panel
2. Hotplug/unplug of dongle
3. Link status change for other DP panels
v2: Added WARN_ON to intel_dp_check_link_status()
Removed a call to intel_dp_get_link_status() (Ander)
v3: Changed commit message to explain need of link status
being read before performing encoder checks (Daniel)
v4: Changed commit message to explain need of reading
link status on short pulse (Ander)
Tested-by: Nathan D Ciobanu
Signed-off-by: Sivakumar Thulasimani
Signed-off-by: Shubhangi Shrivastava
Reviewed-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_dp.c | 65 +++--
1 file changed, 36 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0e16f74..46030a2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4215,6 +4215,36 @@ go_again:
return -EINVAL;
}
+static void
+intel_dp_check_link_status(struct intel_dp *intel_dp)
+{
+ struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ u8 link_status[DP_LINK_STATUS_SIZE];
+
+ WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
+
+ if (!intel_dp_get_link_status(intel_dp, link_status)) {
+ DRM_ERROR("Failed to get link status\n");
+ return;
+ }
+
+ if (!intel_encoder->base.crtc)
+ return;
+
+ if (!to_intel_crtc(intel_encoder->base.crtc)->active)
+ return;
+
+ /* if link training is requested we should perform it always */
+ if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
+ (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
+ DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
+ intel_encoder->base.name);
+ intel_dp_start_link_train(intel_dp);
+ intel_dp_stop_link_train(intel_dp);
+ }
+}
+
/*
* According to DP spec
* 5.1.2:
@@ -4224,14 +4254,10 @@ go_again:
* 4. Check link status on receipt of hot-plug interrupt
*/
static void
-intel_dp_check_link_status(struct intel_dp *intel_dp)
+intel_dp_short_pulse(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
- struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
u8 sink_irq_vector;
- u8 link_status[DP_LINK_STATUS_SIZE];
-
- WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
/*
* Clearing compliance test variables to allow capturing
@@ -4241,17 +4267,6 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
intel_dp->compliance_test_type = 0;
intel_dp->compliance_test_data = 0;
- if (!intel_encoder->base.crtc)
- return;
-
- if (!to_intel_crtc(intel_encoder->base.crtc)->active)
- return;
-
- /* Try to read receiver status if the link appears to be up */
- if (!intel_dp_get_link_status(intel_dp, link_status)) {
- return;
- }
-
/* Now read the DPCD to see if it's actually running */
if (!intel_dp_get_dpcd(intel_dp)) {
return;
@@ -4271,14 +4286,9 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
}
- /* if link training is requested we should perform it always */
- if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
- (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
- DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
- intel_encoder->base.name);
- intel_dp_start_link_train(intel_dp);
- intel_dp_stop_link_train(intel_dp);
- }
+ drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
+ intel_dp_check_link_status(intel_dp);
+
[Intel-gfx] [PATCH 4/5] drm/i915: Read sink_count dpcd always
Sink count can change between short pulse hpd hence this patch
adds a member variable to intel_dp so we can track any changes
between short pulse interrupts.
This patch reads sink_count dpcd always and removes its
read operation based on values in downstream port dpcd.
SINK_COUNT dpcd is not dependent on DOWNSTREAM_PORT_PRESENT dpcd.
SINK_COUNT denotes if a display is attached, while
DOWNSTREAM_PORT_PRESET indicates how many ports are available
in the dongle where display can be attached. so it is possible
for sink count to change irrespective of value in downstream
port dpcd.
Here is a table of possible values and scenarios
sink_count downstream_port
present
0 0 no display is attached
0 1 dongle is connected without display
1 0 display connected directly
1 1 display connected through dongle
v2: Storing value of intel_dp->sink_count that is ready
for consumption. (Ander)
Squashing two commits into one. (Ander)
v3: Added comment to explain the need of early return when
sink count is 0. (Ander)
Tested-by: Nathan D Ciobanu
Signed-off-by: Sivakumar Thulasimani
Signed-off-by: Shubhangi Shrivastava
Reviewed-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_dp.c | 30 +++---
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 24 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 46030a2..9b2b96f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3788,6 +3788,27 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
if (intel_dp->dpcd[DP_DPCD_REV] == 0)
return false; /* DPCD not present */
+ if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
+ &intel_dp->sink_count, 1) < 0)
+ return false;
+
+ /*
+* Sink count can change between short pulse hpd hence
+* a member variable in intel_dp will track any changes
+* between short pulse interrupts.
+*/
+ intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
+
+ /*
+* SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
+* a dongle is present but no display. Unless we require to know
+* if a dongle is present or not, we don't need to update
+* downstream port information. So, an early return here saves
+* time from performing other operations which are not required.
+*/
+ if (!intel_dp->sink_count)
+ return false;
+
/* Check if the panel supports PSR */
memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
if (is_edp(intel_dp)) {
@@ -4308,14 +4329,9 @@ intel_dp_detect_dpcd(struct intel_dp *intel_dp)
/* If we're HPD-aware, SINK_COUNT changes dynamically */
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
- uint8_t reg;
-
- if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
- ®, 1) < 0)
- return connector_status_unknown;
- return DP_GET_SINK_COUNT(reg) ? connector_status_connected
- : connector_status_disconnected;
+ return intel_dp->sink_count ?
+ connector_status_connected : connector_status_disconnected;
}
/* If no HPD, poke DDC gently */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3ce9391..36c41e8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -796,6 +796,7 @@ struct intel_dp {
uint32_t DP;
int link_rate;
uint8_t lane_count;
+ uint8_t sink_count;
bool has_audio;
bool detect_done;
enum hdmi_force_audio force_audio;
--
2.6.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/5] drm/i915: Cleaning up intel_dp_hpd_pulse
Current DP detection has DPCD operations split across
intel_dp_hpd_pulse and intel_dp_detect which contains
duplicates as well. Also intel_dp_detect is called
during modes enumeration as well which will result
in multiple dpcd operations. So this patch tries
to solve both these by bringing all DPCD operations
in one single function and make intel_dp_detect
use existing values instead of repeating same steps.
v2: Pulled in a hunk from last patch of the series to
this patch. (Ander)
v3: Added MST hotplug handling. (Ander)
v4: Added a flag to check if detect is performed to
prevent multiple detects on hotplug. (Ander)
Tested-by: Nathan D Ciobanu
Signed-off-by: Sivakumar Thulasimani
Signed-off-by: Shubhangi Shrivastava
Reviewed-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_dp.c | 72 +---
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 47 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b4cff63..0e16f74 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4582,6 +4582,16 @@ intel_dp_long_pulse(struct intel_connector
*intel_connector)
*/
status = connector_status_disconnected;
goto out;
+ } else if (connector->status == connector_status_connected) {
+ /*
+* If display was connected already and is still connected
+* check links status, there has been known issues of
+* link loss triggerring long pulse
+*/
+ drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
+ intel_dp_check_link_status(intel_dp);
+ drm_modeset_unlock(&dev->mode_config.connection_mutex);
+ goto out;
}
/*
@@ -4595,6 +4605,7 @@ intel_dp_long_pulse(struct intel_connector
*intel_connector)
intel_dp_set_edid(intel_dp);
status = connector_status_connected;
+ intel_dp->detect_done = true;
/* Try to read the source of the interrupt */
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
@@ -4611,8 +4622,21 @@ intel_dp_long_pulse(struct intel_connector
*intel_connector)
}
out:
- if (status != connector_status_connected)
+ if (status != connector_status_connected) {
intel_dp_unset_edid(intel_dp);
+ /*
+* If we were in MST mode, and device is not there,
+* get out of MST mode
+*/
+ if (intel_dp->is_mst) {
+ DRM_DEBUG_KMS("MST device may have disappeared %d vs
%d\n",
+ intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
+ intel_dp->is_mst = false;
+ drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
+ intel_dp->is_mst);
+ }
+ }
+
intel_display_power_put(to_i915(dev), power_domain);
return;
}
@@ -4636,7 +4660,11 @@ intel_dp_detect(struct drm_connector *connector, bool
force)
return connector_status_disconnected;
}
- intel_dp_long_pulse(intel_dp->attached_connector);
+ /* If full detect is not performed yet, do a full detect */
+ if (!intel_dp->detect_done)
+ intel_dp_long_pulse(intel_dp->attached_connector);
+
+ intel_dp->detect_done = false;
if (intel_connector->detect_edid)
return connector_status_connected;
@@ -4968,25 +4996,25 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
/* indicate that we need to restart link training */
intel_dp->train_set_valid = false;
- if (!intel_digital_port_connected(dev_priv, intel_dig_port))
- goto mst_fail;
-
- if (!intel_dp_get_dpcd(intel_dp)) {
- goto mst_fail;
- }
-
- intel_dp_probe_oui(intel_dp);
+ intel_dp_long_pulse(intel_dp->attached_connector);
+ if (intel_dp->is_mst)
+ ret = IRQ_HANDLED;
+ goto put_power;
- if (!intel_dp_probe_mst(intel_dp)) {
- drm_modeset_lock(&dev->mode_config.connection_mutex,
NULL);
- intel_dp_check_link_status(intel_dp);
- drm_modeset_unlock(&dev->mode_config.connection_mutex);
- goto mst_fail;
- }
} else {
if (intel_dp->is_mst) {
- if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
- goto mst_fail;
+ if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
+ /*
+* If we were in MS
[Intel-gfx] [PATCH 1/5] drm/i915: Splitting intel_dp_detect
intel_dp_detect() is called for not just detection but
during modes enumeration as well. Repeating the whole
sequence during each of these calls is wasteful and
time consuming.
This patch moves probing for panel, DPCD read etc done in
intel_dp_detect() to a new function intel_dp_long_pulse().
Note that the behavior of intel_dp_detect() is changed to
report connected or disconnected depending on whether the
EDID is available or not.
This change will be required by further patches in the series
to avoid performing duplicated DPCD operations on hotplug.
v2: Moved a hunk to next patch of the series.
Moved intel_dp_unset_edid to out. (Ander)
v3: Rephrased commit message and intel_dp_unset_dp() is called
within intel_dp_set_dp() to free the previous EDID. (Ander)
v4: Added overriding of status to disconnected for MST. (Ander)
Tested-by: Nathan D Ciobanu
Signed-off-by: Sivakumar Thulasimani
Signed-off-by: Shubhangi Shrivastava
Reviewed-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_dp.c | 63 -
1 file changed, 43 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3bdd8ba..b4cff63 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -129,6 +129,7 @@ static void edp_panel_vdd_off(struct intel_dp *intel_dp,
bool sync);
static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
static void vlv_steal_power_sequencer(struct drm_device *dev,
enum pipe pipe);
+static void intel_dp_unset_edid(struct intel_dp *intel_dp);
static unsigned int intel_dp_unused_lane_mask(int lane_count)
{
@@ -4513,6 +4514,7 @@ intel_dp_set_edid(struct intel_dp *intel_dp)
struct intel_connector *intel_connector = intel_dp->attached_connector;
struct edid *edid;
+ intel_dp_unset_edid(intel_dp);
edid = intel_dp_get_edid(intel_dp);
intel_connector->detect_edid = edid;
@@ -4533,9 +4535,10 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
intel_dp->has_audio = false;
}
-static enum drm_connector_status
-intel_dp_detect(struct drm_connector *connector, bool force)
+static void
+intel_dp_long_pulse(struct intel_connector *intel_connector)
{
+ struct drm_connector *connector = &intel_connector->base;
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct intel_encoder *intel_encoder = &intel_dig_port->base;
@@ -4545,17 +4548,6 @@ intel_dp_detect(struct drm_connector *connector, bool
force)
bool ret;
u8 sink_irq_vector;
- DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
- connector->base.id, connector->name);
- intel_dp_unset_edid(intel_dp);
-
- if (intel_dp->is_mst) {
- /* MST devices are disconnected from a monitor POV */
- if (intel_encoder->type != INTEL_OUTPUT_EDP)
- intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
- return connector_status_disconnected;
- }
-
power_domain = intel_display_port_aux_power_domain(intel_encoder);
intel_display_power_get(to_i915(dev), power_domain);
@@ -4576,14 +4568,18 @@ intel_dp_detect(struct drm_connector *connector, bool
force)
goto out;
}
+ if (intel_encoder->type != INTEL_OUTPUT_EDP)
+ intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
+
intel_dp_probe_oui(intel_dp);
ret = intel_dp_probe_mst(intel_dp);
if (ret) {
- /* if we are in MST mode then this connector
- won't appear connected or have anything with EDID on it */
- if (intel_encoder->type != INTEL_OUTPUT_EDP)
- intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
+ /*
+* If we are in MST mode then this connector
+* won't appear connected or have anything
+* with EDID on it
+*/
status = connector_status_disconnected;
goto out;
}
@@ -4598,8 +4594,6 @@ intel_dp_detect(struct drm_connector *connector, bool
force)
intel_dp_set_edid(intel_dp);
- if (intel_encoder->type != INTEL_OUTPUT_EDP)
- intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
status = connector_status_connected;
/* Try to read the source of the interrupt */
@@ -4617,8 +4611,37 @@ intel_dp_detect(struct drm_connector *connector, bool
force)
}
out:
+ if (status != connector_status_connected)
+ intel_dp_unset_edid(intel_dp);
intel_display_power_put(to_i915(dev), power_domain);
- return status;
+ return;
+}
+
+static enum drm_connector_status
+intel_dp_detect(struct drm_connector *connector, bool force)
+{
+ struct intel_dp *intel_dp = in
Re: [Intel-gfx] [PATCH 10/10] drm/tegra: Don't set a gamma table size
On Wed, Mar 30, 2016 at 11:51:25AM +0200, Daniel Vetter wrote: > tegra doesn't have any functions to set gamma tables, so this is > completely defunct. > > Not nice to lie to userspace, so let's stop! > > Cc: Thierry Reding > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/tegra/dc.c | 1 - > 1 file changed, 1 deletion(-) Do you want this to go through the Tegra tree or do you have follow-up work that depends on this? Thierry signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/ttm: Remove TTM_HAS_AGP
On 30 March 2016 at 12:24, Daniel Vetter wrote: > It tries to do fancy things with excluding agp support if ttm is > built-in, but agp isn't. Instead just express this depency like drm > does and use CONFIG_AGP everywhere. > > Also use the neat Makefile magic to make the entire ttm_agp_backend > file optional. > > v2: Use IS_ENABLED(CONFIG_AGP) as suggested by Ville > > v3: Review from Emil. > > v4: Actually get it right as spotted by 0-day. > Nice one. I didn't even spot the typo/thinko in v3 ;-) > Cc: Emil Velikov > Cc: Ville Syrjälä > Signed-off-by: Daniel Vetter Reviewed-by: Emil Velikov -Emil ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/10] drm/armada: Drop fb gamma_set/get functions
On Wed, Mar 30, 2016 at 01:19:21PM +0200, Daniel Vetter wrote: > On Wed, Mar 30, 2016 at 1:09 PM, Russell King - ARM Linux > wrote: > > On Wed, Mar 30, 2016 at 11:51:18AM +0200, Daniel Vetter wrote: > >> The fb helper private gamma_set/get functions are only required when > >> the driver supports paletted 8bit mode with fbdev. Armada uses 32bpp > >> unconditionally, so this is just dead code. It also doesn't do > >> anything really. Let's just remove it. > > > > This comment is misleading: Armada supports 16bpp formats as well as > > 32bpp, and the hardware does have 8bpp modes to, but I've chosen not > > to support the 8bpp modes. > > This is purely about the fbdev emulation (and yeah need to clarify > that), not about kms support in general. And these two gamma_set/get > hooks are _only_ used by the fbdev emulation, and only needed if you > do 8bit paletted mode. Ok if I change the commit message to "Armada > used 32bpp unconditionally for fbdev emulation, ..."? I still don't know where you get that from - the armada fbdev code supports more than just 32bpp. Please explain. -- RMK's Patch system: http://www.arm.linux.org.uk/developer/patches/ FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/10] drm: Give drm_agp_clear drm_legacy_ prefix
On Wed, Mar 30, 2016 at 06:09:04PM +0800, kbuild test robot wrote: > Hi Daniel, > > [auto build test ERROR on drm/drm-next] > [also build test ERROR on v4.6-rc1 next-20160330] > [if your patch is applied to the wrong git tree, please drop us a note to > help improving the system] > > url: > https://github.com/0day-ci/linux/commits/Daniel-Vetter/Another-shot-at-cruft-removal/20160330-174803 > base: git://people.freedesktop.org/~airlied/linux.git drm-next > config: sparc64-allmodconfig (attached as .config) > reproduce: > wget > https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross > -O ~/bin/make.cross > chmod +x ~/bin/make.cross > # save the attached .config to linux build tree > make.cross ARCH=sparc64 > > Note: the > linux-review/Daniel-Vetter/Another-shot-at-cruft-removal/20160330-174803 HEAD > 0ef75daff5d81f77ebd5796d853c534749223b2e builds fine. > It only hurts bisectibility. > > All errors (new ones prefixed by >>): > >drivers/gpu/drm/drm_fops.c: In function 'drm_lastclose': > >> drivers/gpu/drm/drm_fops.c:416:2: error: implicit declaration of function > >> 'drm_legacy_agp_clear' [-Werror=implicit-function-declaration] > drm_legacy_agp_clear(dev); > ^ >cc1: some warnings being treated as errors > -- >drivers/gpu/drm/drm_pci.c: In function 'drm_pci_agp_destroy': > >> drivers/gpu/drm/drm_pci.c:253:3: error: implicit declaration of function > >> 'drm_legacy_agp_clear' [-Werror=implicit-function-declaration] > drm_legacy_agp_clear(dev); > ^ >cc1: some warnings being treated as errors > > vim +/drm_legacy_agp_clear +416 drivers/gpu/drm/drm_fops.c > >410 >411if (dev->irq_enabled && !drm_core_check_feature(dev, > DRIVER_MODESET)) >412drm_irq_uninstall(dev); >413 >414mutex_lock(&dev->struct_mutex); >415 > > 416drm_legacy_agp_clear(dev); >417 >418drm_legacy_sg_cleanup(dev); >419drm_legacy_vma_flush(dev); FWIW, this is because the dummy implementation wasn't renamed. Thierry signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t v4 0/5] Scheduler tests
This patch set adds scheduler tests. Patch 1 adds library code used by the tests. There are other tests under development which are planned to reuse some of these libraries. Patch 2 adds some basic tests, read dependency tests and write dependency tests. Patch 3 Is the patch previously submitted by John Harrison to update gem_ctx_param_basic with ioctls to set context priorities. It is included as part of this patch set as Patch 6 & 7 are dependant on it. Patch 4 adds subtests to check sheduler behaviour for batch buffers submitted at differing priorities. Patch 5 adds subtests to check priority starving behaviour. v2: Updates for comments from and Daniel Vetter Added tests requested by Joonas Lahtinen v3: Removed the patch to update gem_has_ring() and updated the test to use BSD if there is 1 ring and BSD1 / BSD2 if there are two. v4: Removed patch to make gem_has_ring() non static as another patch has already done so. Addressed more comments from Daniele Ceraolo Spurio Derek Morton (4): lib/intel_batchbuffer: Add functions to be used in the scheduler test tests/gem_scheduler: Add gem_scheduler test tests/gem_scheduler: Add subtests to test batch priority behaviour gem_scheduler: Added subtests to test priority starving John Harrison (1): igt/gem_ctx_param_basic: Updated to support scheduler priority interface lib/intel_batchbuffer.c | 372 +- lib/intel_batchbuffer.h | 14 + lib/ioctl_wrappers.h| 1 + tests/Makefile.sources | 1 + tests/gem_ctx_param_basic.c | 34 ++- tests/gem_scheduler.c | 622 6 files changed, 1038 insertions(+), 6 deletions(-) create mode 100644 tests/gem_scheduler.c -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t v4 1/5] lib/intel_batchbuffer: Add functions to be used in the scheduler test
Adds functions to create a number of different batch buffers to perform
several functions including:
Batch buffer which will run for a long duration to provide a delay on a
specified ring.
Function to calibrate the delay batch buffer to run for a specified period
of time.
Function to create a batch buffer which writes timestamps to a buffer object.
Function to compare timestamps allowing for wrapping of the values.
v2: Moved code to intel_batchbuffer (Daniel Vetter)
Addressed review comments from Daniele Ceraolo Spurio
v4: Addressed more comments from Daniele Ceraolo Spurio
Signed-off-by: Derek Morton
---
lib/intel_batchbuffer.c | 372 +++-
lib/intel_batchbuffer.h | 14 ++
2 files changed, 381 insertions(+), 5 deletions(-)
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 692521f..aa4eeaf 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1,8 +1,8 @@
/**
- *
+ *
* Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
@@ -10,11 +10,11 @@
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
- *
+ *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
@@ -22,7 +22,7 @@
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
+ *
**/
#include
@@ -30,6 +30,8 @@
#include
#include
#include
+#include
+#include
#include "drm.h"
#include "drmtest.h"
@@ -42,6 +44,7 @@
#include "ioctl_wrappers.h"
#include "media_spin.h"
#include "gpgpu_fill.h"
+#include "igt_gt.h"
#include
@@ -817,3 +820,362 @@ igt_media_spinfunc_t igt_get_media_spinfunc(int devid)
return spin;
}
+
+#define SEC_TO_NSEC (1000 * 1000 * 1000)
+#define DWORDS_TO_BYTES(x) ((x)*4)
+
+#define MI_STORE_REGISTER_MEM(LENGTH) ((0x024 << 23) | ((LENGTH - 2) & 0xff))
+#define MI_MATH(NrInst) ((0x01A << 23) | ((NrInst - 1) & 0x3f))
+#define MI_CONDITIONAL_BATCH_BUFFER_END ((0x036 << 23) | (1 << 21) | 2)
+#define MI_COPY_MEM_MEM ((0x02E << 23) | (3))
+
+#define ALU_LOAD(TO, FROM) ((0x080 << 20) | ((TO) << 10) | (FROM))
+#define ALU_SUB ( 0x101 << 20)
+#define ALU_STORE(TO, FROM) ((0x180 << 20) | ((TO) << 10) | (FROM))
+
+#define TIMESTAMP_offset (0x358) /* Elapsed time from system start */
+#define ALU_GPU_R0_LSB_offset (0x600)
+#define ALU_GPU_R0_MSB_offset (0x604)
+#define ALU_GPU_R1_LSB_offset (0x608)
+#define ALU_GPU_R1_MSB_offset (0x60C)
+#define ALU_GPU_R2_LSB_offset (0x610)
+#define ALU_GPU_R2_MSB_offset (0x614)
+
+#define ALU_R0_ENCODING (0x00)
+#define ALU_R1_ENCODING (0x01)
+#define ALU_SRCA_ENCODING (0x20)
+#define ALU_SRCB_ENCODING (0x21)
+#define ALU_ACCU_ENCODING (0x31)
+
+static int bb_address_size_dw(int gen)
+{
+ if (gen >= 8)
+ return 2;
+ else
+ return 1;
+}
+
+static uint32_t get_mmio_base(int ringid)
+{
+ switch (ringid) {
+ case I915_EXEC_RENDER:
+ return 0x02000;
+ case I915_EXEC_BSD:
+ case I915_EXEC_BSD | 1<<13: /* BSD1 */
+ return 0x12000;
+ case I915_EXEC_BSD | 2<<13: /* BSD2 */
+ return 0x1c000;
+ case I915_EXEC_BLT:
+ return 0x22000;
+ case I915_EXEC_VEBOX:
+ return 0x1A000;
+ default:
+ igt_assert_f(0, "Invalid ringid %d passed to
get_mmio_base()\n", ringid);
+ }
+}
+
+/**
+ * igt_batch_used
+ * @batch batchbuffer to get offset from
+ *
+ * This returns the number of bytes of the batchbuffer that have been used.
+ * e.g. The offset into the batchbuffer that the next OUT_BATCH would write to.
+ *
+ * Returns:
+ * The number of bytes of the batchbuffer that have been used.
+ */
+uint32_t igt_batch_used(struct intel_batchbuffer *batch)
+{
+ return batch->ptr - batch->buffer;
+}
+
+/**
+ * igt_create_delay_bb:
+ * @batch: Batch buffer to write to
+ * @ringid: Execution flag of the ring. e.g. I915_EXEC_RENDER
+ * @loops: Number of times to loop
+ * @dest: Buffer to use for sa
[Intel-gfx] [PATCH i-g-t v4 2/5] tests/gem_scheduler: Add gem_scheduler test
This is intended to test the scheduler behaviour is correct.
The subtests are
-basic
Tests that batch buffers of the same priority submitted to a ring
execute in the order they are submitted.
-read
Submits a batch buffer with a read dependency to a buffer object to
a ring which is held in the scheduler queue by a long running batch
buffer. Submit batch buffers to other rings that have a read dependency
to the same buffer object. Ensure they execute before the batch buffer
being held up behind the long running batch buffer.
-write
Submits a batch buffer with a write dependency to a buffer object to
a ring which is held in the scheduler queue by a long running batch
buffer. Submit batch buffers to other rings that have a write dependency
to the same buffer object. Submit batch buffers with no interdependencies
to all rings. Ensure the batch buffers that have write dependencies are
executed in submission order but the batch buffers without interdependencies
do not get held up.
v2: Addressed review comments from Daniele Ceraolo Spurio
v3: Added logic to use generic BSD ring if there is 1 and BSD1 / BSD2 if there
are 2.
v4: Addressed more review comments from Daniele Ceraolo Spurio
Signed-off-by: Derek Morton
---
tests/Makefile.sources | 1 +
tests/gem_scheduler.c | 451 +
2 files changed, 452 insertions(+)
create mode 100644 tests/gem_scheduler.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 26e487a..cdbb37c 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -68,6 +68,7 @@ TESTS_progs_M = \
gem_request_retire \
gem_reset_stats \
gem_ringfill \
+ gem_scheduler \
gem_set_tiling_vs_blt \
gem_shrink \
gem_softpin \
diff --git a/tests/gem_scheduler.c b/tests/gem_scheduler.c
new file mode 100644
index 000..704dbb1
--- /dev/null
+++ b/tests/gem_scheduler.c
@@ -0,0 +1,451 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *Derek Morton
+ *
+ */
+
+#include "igt.h"
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+IGT_TEST_DESCRIPTION("Check scheduler behaviour. Basic tests ensure
independant "
+ "batch buffers of the same priority are executed in "
+ "submission order. Read-read tests ensure "
+ "batch buffers with a read dependency to the same buffer "
+ "object do not block each other. Write-write dependency "
+ "tests ensure batch buffers with a write dependency to a "
+ "buffer object will be executed in submission order but "
+ "will not block execution of other independant batch "
+ "buffers.");
+
+#define SEC_TO_NSEC (1000 * 1000 * 1000)
+
+/* Create an array of rings to test. Need to test rings concurrently and
+ * explicitly so this array differs from intel_execution_engines as it
+ * excludes the default engine and is updated by check_rings() to handle either
+ * BSD or BSD1 and BSD2.
+ */
+static struct ring {
+ const char *name;
+ int id;
+ bool exists;
+} rings[] = {
+ { "render", I915_EXEC_RENDER, false },
+ { "bsd",I915_EXEC_BSD , false },
+ { "bsd2",I915_EXEC_BSD | 2<<13, false },
+ { "blt",I915_EXEC_BLT, false },
+ { "vebox", I915_EXEC_VEBOX, false },
+};
+
+#define NBR_RINGS (sizeof(rings)/sizeof(struct ring))
+
+static void check_rings(int fd) {
+ int loop;
+ for (loop=0; loop < NBR_RINGS; loop++) {
+ if (gem_has_ring(fd, rings[loop].id)) {
+ if (rings[loop].id == (I915_EXEC_BSD | 2<<13)) {
+ rings[loop].exists = gem_has_bsd2(fd);
+ } else {
[Intel-gfx] [PATCH i-g-t v4 3/5] igt/gem_ctx_param_basic: Updated to support scheduler priority interface
From: John Harrison
The GPU scheduler has added an execution priority level to the context
object. There is an IOCTL interface to allow user apps/libraries to
set this priority. This patch updates the context paramter IOCTL test
to include the new interface.
For: VIZ-1587
Signed-off-by: John Harrison
---
lib/ioctl_wrappers.h| 1 +
tests/gem_ctx_param_basic.c | 34 +-
2 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index d986f61..3b8a015 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -109,6 +109,7 @@ struct local_i915_gem_context_param {
#define LOCAL_CONTEXT_PARAM_BAN_PERIOD 0x1
#define LOCAL_CONTEXT_PARAM_NO_ZEROMAP 0x2
#define LOCAL_CONTEXT_PARAM_GTT_SIZE 0x3
+#define LOCAL_CONTEXT_PARAM_PRIORITY 0x4
uint64_t value;
};
void gem_context_require_ban_period(int fd);
diff --git a/tests/gem_ctx_param_basic.c b/tests/gem_ctx_param_basic.c
index b75800c..585a1a8 100644
--- a/tests/gem_ctx_param_basic.c
+++ b/tests/gem_ctx_param_basic.c
@@ -147,10 +147,42 @@ igt_main
TEST_SUCCESS(LOCAL_IOCTL_I915_GEM_CONTEXT_SETPARAM);
}
+ ctx_param.param = LOCAL_CONTEXT_PARAM_PRIORITY;
+
+ igt_subtest("priority-root-set") {
+ ctx_param.context = ctx;
+ ctx_param.value = 2048;
+ TEST_FAIL(LOCAL_IOCTL_I915_GEM_CONTEXT_SETPARAM, EINVAL);
+ ctx_param.value = -2048;
+ TEST_FAIL(LOCAL_IOCTL_I915_GEM_CONTEXT_SETPARAM, EINVAL);
+ ctx_param.value = 512;
+ TEST_SUCCESS(LOCAL_IOCTL_I915_GEM_CONTEXT_SETPARAM);
+ ctx_param.value = -512;
+ TEST_SUCCESS(LOCAL_IOCTL_I915_GEM_CONTEXT_SETPARAM);
+ ctx_param.value = 0;
+ TEST_SUCCESS(LOCAL_IOCTL_I915_GEM_CONTEXT_SETPARAM);
+ }
+
+ igt_subtest("priority-non-root-set") {
+ igt_fork(child, 1) {
+ igt_drop_root();
+
+ ctx_param.context = ctx;
+ ctx_param.value = 512;
+ TEST_FAIL(LOCAL_IOCTL_I915_GEM_CONTEXT_SETPARAM, EPERM);
+ ctx_param.value = -512;
+ TEST_SUCCESS(LOCAL_IOCTL_I915_GEM_CONTEXT_SETPARAM);
+ ctx_param.value = 0;
+ TEST_SUCCESS(LOCAL_IOCTL_I915_GEM_CONTEXT_SETPARAM);
+ }
+
+ igt_waitchildren();
+ }
+
/* NOTE: This testcase intentionally tests for the next free parameter
* to catch ABI extensions. Don't "fix" this testcase without adding all
* the tests for the new param first. */
- ctx_param.param = LOCAL_CONTEXT_PARAM_GTT_SIZE + 1;
+ ctx_param.param = LOCAL_CONTEXT_PARAM_PRIORITY + 1;
igt_subtest("invalid-param-get") {
ctx_param.context = ctx;
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t v4 4/5] tests/gem_scheduler: Add subtests to test batch priority behaviour
Add subtests to test each ring to check batch buffers of a higher
priority will be executed before batch buffers of a lower priority.
v2: Addressed review comments from Daniele Ceraolo Spurio
v4: Changed priorities to +/-200 - Daniele Ceraolo Spurio
Signed-off-by: Derek Morton
---
tests/gem_scheduler.c | 57 ++-
1 file changed, 47 insertions(+), 10 deletions(-)
diff --git a/tests/gem_scheduler.c b/tests/gem_scheduler.c
index 704dbb1..504607f 100644
--- a/tests/gem_scheduler.c
+++ b/tests/gem_scheduler.c
@@ -39,7 +39,8 @@
IGT_TEST_DESCRIPTION("Check scheduler behaviour. Basic tests ensure
independant "
"batch buffers of the same priority are executed in "
- "submission order. Read-read tests ensure "
+ "submission order. Priority tests ensure higher priority "
+ "batch buffers are executed first. Read-read tests ensure
"
"batch buffers with a read dependency to the same buffer "
"object do not block each other. Write-write dependency "
"tests ensure batch buffers with a write dependency to a "
@@ -61,7 +62,7 @@ static struct ring {
} rings[] = {
{ "render", I915_EXEC_RENDER, false },
{ "bsd",I915_EXEC_BSD , false },
- { "bsd2",I915_EXEC_BSD | 2<<13, false },
+ { "bsd2", I915_EXEC_BSD | 2<<13, false },
{ "blt",I915_EXEC_BLT, false },
{ "vebox", I915_EXEC_VEBOX, false },
};
@@ -70,7 +71,7 @@ static struct ring {
static void check_rings(int fd) {
int loop;
- for (loop=0; loop < NBR_RINGS; loop++) {
+ for (loop = 0; loop < NBR_RINGS; loop++) {
if (gem_has_ring(fd, rings[loop].id)) {
if (rings[loop].id == (I915_EXEC_BSD | 2<<13)) {
rings[loop].exists = gem_has_bsd2(fd);
@@ -145,11 +146,23 @@ static void init_context(int *fd, drm_intel_bufmgr
**bufmgr, int ringid)
intel_batchbuffer_free(noop_bb);
}
-/* Basic test. Check batch buffers of the same priority and with no
dependencies
- * are executed in the order they are submitted.
+static void set_priority(int fd, int value)
+{
+ struct local_i915_gem_context_param param;
+ param.context = 0; /* Default context */
+ param.size = 0;
+ param.param = LOCAL_CONTEXT_PARAM_PRIORITY;
+ param.value = (uint64_t)value;
+ gem_context_set_param(fd, ¶m);
+}
+
+/* If 'priority' is 0, check batch buffers of the same priority and with
+ * no dependencies are executed in the order they are submitted.
+ * If 'priority' is set !0, check batch buffers of higher priority are
+ * executed before batch buffers of lower priority.
*/
#define NBR_BASIC_FDs (3)
-static void run_test_basic(int in_flight, int ringid)
+static void run_test_basic(int in_flight, int ringid, int priority)
{
int fd[NBR_BASIC_FDs];
int loop;
@@ -169,6 +182,13 @@ static void run_test_basic(int in_flight, int ringid)
for (loop = 0; loop < NBR_BASIC_FDs; loop++)
init_context(&(fd[loop]), &(bufmgr[loop]), ringid);
+ /* For high priority set priority of second context to overtake first
+* For low priority set priority of first context to be overtaxen by
second
+*/
+ if(priority > 0)
+ set_priority(fd[2], priority);
+ else if(priority < 0)
+ set_priority(fd[1], priority);
/* Create buffer objects */
delay_bo = create_and_check_bo(bufmgr[0], "delay bo");
@@ -212,9 +232,14 @@ static void run_test_basic(int in_flight, int ringid)
igt_assert_f(igt_compare_timestamps(delay_buf[2], ts1_buf[0]),
"Delay ts (0x%08" PRIx32 ") > TS1 ts (0x%08" PRIx32 ")\n",
delay_buf[2], ts1_buf[0]);
- igt_assert_f(igt_compare_timestamps(ts1_buf[0], ts2_buf[0]),
-"TS1 ts (0x%08" PRIx32 ") > TS2 ts (0x%08" PRIx32 ")\n",
-ts1_buf[0], ts2_buf[0]);
+ if(priority)
+ igt_assert_f(igt_compare_timestamps(ts2_buf[0], ts1_buf[0]),
+"TS2 ts (0x%08" PRIx32 ") > TS1 ts (0x%08" PRIx32
")\n",
+ts2_buf[0], ts1_buf[0]);
+ else
+ igt_assert_f(igt_compare_timestamps(ts1_buf[0], ts2_buf[0]),
+"TS1 ts (0x%08" PRIx32 ") > TS2 ts (0x%08" PRIx32
")\n",
+ts1_buf[0], ts2_buf[0]);
/* Cleanup */
for (loop = 0; loop < in_flight; loop++)
@@ -430,7 +455,19 @@ igt_main
for (loop = 0; loop < NBR_RINGS; loop++)
igt_subtest_f("%s-basic", rings[loop].name) {
gem_require_ring(fd, rings[loop].id);
- run_test_basic(in_flight, rings[loop].id);
+ run_test_basic(in_flight, rings[loop].id, false);
+
[Intel-gfx] [PATCH i-g-t v4 5/5] gem_scheduler: Added subtests to test priority starving
When a batch is selected for execution all other batch buffers in the
scheduler queue get a small priority increase to prevent starving due
to continuous submissions by a high priority user.
Added a subtest to check this behaviour.
Requested by Joonas Lahtinen during scheduler code review
v4: Addressed review comments from Daniele Ceraolo Spurio
Signed-off-by: Derek Morton
---
tests/gem_scheduler.c | 134 ++
1 file changed, 134 insertions(+)
diff --git a/tests/gem_scheduler.c b/tests/gem_scheduler.c
index 504607f..5d8fecf 100644
--- a/tests/gem_scheduler.c
+++ b/tests/gem_scheduler.c
@@ -257,6 +257,134 @@ static void run_test_basic(int in_flight, int ringid, int
priority)
free(in_flight_bbs);
}
+
+/* Test priority starving behaviour.
+ When a batch is selected for execution all other batch buffers in the
+ scheduler queue get a small priority increase to prevent starving due
+ to continuous submissions by a high priority user.
+ * Submit two delay batch buffers then fill the in flight queue. Submit a
+ * slightly reduced priority batch buffer and a normal priority batch buffer.
+ * When the first delay batch buffer completes and the next is put in flight
all
+ * other batch buffers in the scheduler queue should get a small priority
+ * increase.
+ * Submit another normal priority batch buffer. It should not overtake the
+ * reduced priority batch buffer whose priority has been increased.
+ */
+#define NBR_PRIO_STARVE_FDs (4)
+static void run_test_priority_starve(int in_flight, int ringid)
+{
+ int fd[NBR_PRIO_STARVE_FDs];
+ int loop;
+ drm_intel_bufmgr *bufmgr[NBR_PRIO_STARVE_FDs];
+ uint32_t *delay_buf, *delay2_buf, *ts1_buf, *ts2_buf, *ts3_buf;
+ struct intel_batchbuffer *ts1_bb, *ts2_bb, *ts3_bb;
+ struct intel_batchbuffer **in_flight_bbs;
+ uint32_t calibrated_1s;
+ drm_intel_bo *delay_bo, *delay2_bo ,*ts1_bo, *ts2_bo, *ts3_bo;
+
+ in_flight_bbs = malloc(in_flight * sizeof(struct intel_batchbuffer *));
+ igt_assert(in_flight_bbs);
+
+ /* Need multiple i915 fd's. Scheduler will not change execution order of
+* batch buffers from the same context.
+*/
+ for(loop = 0; loop < NBR_PRIO_STARVE_FDs; loop++)
+ init_context(&(fd[loop]), &(bufmgr[loop]), ringid);
+
+ /* Lower priority of first timestamp batch buffer
+* Second timestamp batch buffer should overtake the first
+* Overtaken batch should then get a priority increase so the third does
+* not overtake it.
+*/
+ set_priority(fd[1], -1);
+
+ /* Create buffer objects */
+ delay_bo = create_and_check_bo(bufmgr[0], "delay bo");
+ delay2_bo = create_and_check_bo(bufmgr[0], "delay bo2");
+ ts1_bo = create_and_check_bo(bufmgr[1], "ts1 bo");
+ ts2_bo = create_and_check_bo(bufmgr[2], "ts2 bo");
+ ts3_bo = create_and_check_bo(bufmgr[3], "ts3 bo");
+
+ calibrated_1s = igt_calibrate_delay_bb(fd[0], bufmgr[0], ringid);
+
+ /* Batch buffers to fill the in flight queue */
+ in_flight_bbs[0] = create_delay_bb(fd[0], bufmgr[0], ringid,
calibrated_1s, delay_bo);
+ in_flight_bbs[1] = create_delay_bb(fd[0], bufmgr[0], ringid,
calibrated_1s, delay2_bo);
+ for(loop = 2; loop < in_flight; loop++)
+ in_flight_bbs[loop] = create_noop_bb(fd[0], bufmgr[0], 5);
+
+ /* Extra batch buffers in the scheduler queue */
+ ts1_bb = create_timestamp_bb(fd[1], bufmgr[1], ringid, ts1_bo, NULL,
false);
+ ts2_bb = create_timestamp_bb(fd[2], bufmgr[2], ringid, ts2_bo, NULL,
false);
+ ts3_bb = create_timestamp_bb(fd[3], bufmgr[3], ringid, ts3_bo, NULL,
false);
+
+ /* Flush batchbuffers */
+ for(loop = 0; loop < in_flight; loop++)
+ intel_batchbuffer_flush_on_ring(in_flight_bbs[loop], ringid);
+ intel_batchbuffer_flush_on_ring(ts1_bb, ringid);
+ intel_batchbuffer_flush_on_ring(ts2_bb, ringid);
+
+ /* This will not return until the bo has finished executing */
+ drm_intel_bo_map(delay_bo, 0);
+ /* Once the first delay is complete and any bumping has occured, submit
+* the final batch buffer
+*/
+ intel_batchbuffer_flush_on_ring(ts3_bb, ringid);
+
+ drm_intel_bo_map(delay2_bo, 0);
+ drm_intel_bo_map(ts1_bo, 0);
+ drm_intel_bo_map(ts2_bo, 0);
+ drm_intel_bo_map(ts3_bo, 0);
+
+ delay_buf = delay_bo->virtual;
+ delay2_buf = delay2_bo->virtual;
+ ts1_buf = ts1_bo->virtual;
+ ts2_buf = ts2_bo->virtual;
+ ts3_buf = ts3_bo->virtual;
+
+ igt_debug("Delay Timestamp = 0x%08" PRIx32 "\n", delay_buf[2]);
+ igt_debug("Delay Timestamp = 0x%08" PRIx32 "\n", delay2_buf[2]);
+ igt_debug("TS1 Timestamp = 0x%08" PRIx32 "\n", ts1_buf[0]);
+ igt_debug("TS2 Timestamp = 0x%08" PRIx32 "\n", ts2_buf[0]);
+ igt_debug("TS3 Timestamp = 0x%08" PR
Re: [Intel-gfx] [PATCH 06/10] drm: Put legacy lastclose work into drm_legacy_dev_reinit
On Wed, Mar 30, 2016 at 11:45:16AM +0200, Daniel Vetter wrote: [...] > diff --git a/include/drm/drm_agpsupport.h b/include/drm/drm_agpsupport.h > index e134e9ca422b..b2d912670a7f 100644 > --- a/include/drm/drm_agpsupport.h > +++ b/include/drm/drm_agpsupport.h > @@ -93,7 +93,7 @@ static inline struct drm_agp_head *drm_agp_init(struct > drm_device *dev) > return NULL; > } > > -static inline void drm_agp_clear(struct drm_device *dev) > +static inline void drm_legacy_agp_clear(struct drm_device *dev) Ah... it ended up in the wrong patch. Thierry signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/6] drm/i915: Allow mmio updates on all platforms.
On Tue, Mar 29, 2016 at 10:03:56AM +0200, Maarten Lankhorst wrote:
> Op 24-03-16 om 16:32 schreef Ville Syrjälä:
> > On Thu, Mar 24, 2016 at 04:19:13PM +0100, Maarten Lankhorst wrote:
> >> Op 24-03-16 om 15:48 schreef Ville Syrjälä:
> >>> On Thu, Mar 24, 2016 at 03:42:28PM +0100, Maarten Lankhorst wrote:
> Op 24-03-16 om 15:26 schreef Ville Syrjälä:
> > On Thu, Mar 24, 2016 at 09:35:04AM +0100, Maarten Lankhorst wrote:
> >> Op 23-03-16 om 16:07 schreef Ville Syrjälä:
> >>> On Wed, Mar 23, 2016 at 02:24:30PM +0100, Maarten Lankhorst wrote:
> Rename intel_unpin_work to intel_flip_work and use it for mmio flips
> and unpinning. Use flip_queued_req to hold the wait request in the
> mmio case and allow the vblank interrupt to complete mmio work to
> have mmio flips run correctly on g4 and earlier.
> >>> Before you actually go and trust drm_vblank_count() you should make it
> >>> race free.
> >> How about adding the below to the patch?
> > You can't just mix the hw and sw counter. Using the hw counter would be
> > neat because it doesn't require so much work to be race-free, but that
> > leaves out gen2 which I don't like. My atomic code used the hw counter
> > though, but I had plans to fall back to the sw counter on gen2
> > eventually.
> >
> So I dug in a little bit more..
>
> MMIO updates don't require accurate vblank count for anything, so even
> if it was completely removed it would work.
> >>> Yes they do if you want to use the vblank irq for completing them.
> >>>
> >> Why? We only need a vblank irq, after the mmio updates are done we set an
> >> atomic that indicates mmio is done, which is checked in the vblank irq.
> > You can race with the irq handler, especially on gen2/3 where the vblank
> > irq is actually the frame start irq that is delayed by at least ~1
> > scanline. So you absolutely need to know on which frame actually
> > submitted the flip so as not to complete it prematurely.
> In that case won't you get a DRM_ERROR("Atomic update failure on pipe %c
> (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end
> %d\n"); anyway?
Nope. The update start+end will happen within the same frame (unless we
messed up the vblank evade) so the hw counter will show the same value
on both sides. The irq handler isn't involved with that code at all.
--
Ville Syrjälä
Intel OTC
___
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Re: [Intel-gfx] [PATCH] drm/core: Add drm_accurate_vblank_count_and_time.
On Tue, Mar 29, 2016 at 03:38:55PM +0200, Maarten Lankhorst wrote:
> This function is useful for gen2 intel devices which have no frame
> counter, but need a way to determine the current vblank count without
> racing with the vblank interrupt handler.
>
> intel_pipe_update_start checks if no vblank interrupt will occur
> during vblank evasion, but cannot check whether the vblank handler has
> run to completion. This function uses the timestamps to determine
> when the last vblank has happened, and interpolates from there.
Didn't really read it in detail, but on a glance it seems too
complicated to me. All we should really need is something like this:
drm_vblank_get();
drm_update_vblank_count();
accurate = drm_vblank_count();
>
> Cc: Mario Kleiner
> Cc: Ville Syrjälä
> Signed-off-by: Maarten Lankhorst
> ---
> Unfortunately only compile time tested, I don't have a gen2 to test with.
>
> drivers/gpu/drm/drm_irq.c | 90
> +++
> include/drm/drmP.h| 2 ++
> 2 files changed, 69 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
> index 881c5a6c180c..44d8f9607ccd 100644
> --- a/drivers/gpu/drm/drm_irq.c
> +++ b/drivers/gpu/drm/drm_irq.c
> @@ -155,24 +155,10 @@ static void drm_reset_vblank_timestamp(struct
> drm_device *dev, unsigned int pipe
> spin_unlock(&dev->vblank_time_lock);
> }
>
> -/**
> - * drm_update_vblank_count - update the master vblank counter
> - * @dev: DRM device
> - * @pipe: counter to update
> - *
> - * Call back into the driver to update the appropriate vblank counter
> - * (specified by @pipe). Deal with wraparound, if it occurred, and
> - * update the last read value so we can deal with wraparound on the next
> - * call if necessary.
> - *
> - * Only necessary when going from off->on, to account for frames we
> - * didn't get an interrupt for.
> - *
> - * Note: caller must hold dev->vbl_lock since this reads & writes
> - * device vblank fields.
> - */
> -static void drm_update_vblank_count(struct drm_device *dev, unsigned int
> pipe,
> - unsigned long flags)
> +static u32 __drm_accurate_vblank_count_and_time(struct drm_device *dev,
> unsigned int pipe,
> + const struct timeval *t_old,
> + unsigned long flags, u32 *pdiff,
> + struct timeval *tv_ret)
> {
> struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
> u32 cur_vblank, diff;
> @@ -202,10 +188,8 @@ static void drm_update_vblank_count(struct drm_device
> *dev, unsigned int pipe,
> /* trust the hw counter when it's around */
> diff = (cur_vblank - vblank->last) & dev->max_vblank_count;
> } else if (rc && framedur_ns) {
> - const struct timeval *t_old;
> u64 diff_ns;
>
> - t_old = &vblanktimestamp(dev, pipe, vblank->count);
> diff_ns = timeval_to_ns(&t_vblank) - timeval_to_ns(t_old);
>
> /*
> @@ -286,9 +270,13 @@ static void drm_update_vblank_count(struct drm_device
> *dev, unsigned int pipe,
> " current=%u, diff=%u, hw=%u hw_last=%u\n",
> pipe, vblank->count, diff, cur_vblank, vblank->last);
>
> + *pdiff = diff;
> + *tv_ret = t_vblank;
> +
> if (diff == 0) {
> WARN_ON_ONCE(cur_vblank != vblank->last);
> - return;
> +
> + return cur_vblank;
> }
>
> /*
> @@ -298,9 +286,65 @@ static void drm_update_vblank_count(struct drm_device
> *dev, unsigned int pipe,
>* for now, to mark the vblanktimestamp as invalid.
>*/
> if (!rc && (flags & DRM_CALLED_FROM_VBLIRQ) == 0)
> - t_vblank = (struct timeval) {0, 0};
> + *tv_ret = (struct timeval) {0, 0};
> +
> + return cur_vblank;
> +}
> +
> +/**
> + * drm_accurate_vblank_count_and_time - retrieve the master vblank counter
> + * @crtc: which counter to retrieve
> + * @tv_ret: last time counter was updated
> + *
> + * This function is similar to @drm_update_vblank_count_and_time but
> + * this function interpolates to handle a race with vblank irq's, and
> + * is only useful for crtc's that have no hw vblank counter.
> + */
> +
> +u32 drm_accurate_vblank_count_and_time(struct drm_crtc *crtc,
> +struct timeval *tv_ret)
> +{
> + struct drm_device *dev = crtc->dev;
> + u32 pdiff, old_vblank;
> + struct timeval tv_old = {};
> +
> + WARN(dev->max_vblank_count, "This function is only useful when a hw
> counter is unavailable.");
> +
> + old_vblank = drm_crtc_vblank_count_and_time(crtc, &tv_old);
> +
> + __drm_accurate_vblank_count_and_time(dev, drm_crtc_index(crtc),
> + &tv_old, 0, &pdiff, tv_ret);
> +
> + return old_vblank + pdiff;
> +}
> +EXPORT_SYMBO
Re: [Intel-gfx] [PATCH 02/16] drm/i915: Make {vlv, chv}_{disable, update}_pll() more similar
On Tue, 15 Mar 2016, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The VLV and CHV DPLL disable and update are almost identical in
> how the DPLL/DPLL_MD registers need to be set up. But the code
> looks more different than it really is. Try to bring them into
> line.
>
> v2: s/chv_update_pll/chv_compute_dpll/
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 63
> ++--
> 1 file changed, 25 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 22930f05457c..414ed5007e60 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1759,16 +1759,13 @@ static void vlv_disable_pll(struct drm_i915_private
> *dev_priv, enum pipe pipe)
> /* Make sure the pipe isn't still relying on us */
> assert_pipe_disabled(dev_priv, pipe);
>
> - /*
> - * Leave integrated clock source and reference clock enabled for pipe B.
> - * The latter is needed for VGA hotplug / manual detection.
> - */
So, you change this to keep the reference clock enabled for both
pipes. Deserves a mention in the commit message. AFAICT it's the only
functional change in the patch.
Other than that,
Reviewed-by: Jani Nikula
> - val = DPLL_VGA_MODE_DIS;
> - if (pipe == PIPE_B)
> - val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
> + val = DPLL_INTEGRATED_REF_CLK_VLV |
> + DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> + if (pipe != PIPE_A)
> + val |= DPLL_INTEGRATED_CRI_CLK_VLV;
> +
> I915_WRITE(DPLL(pipe), val);
> POSTING_READ(DPLL(pipe));
> -
> }
>
> static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe
> pipe)
> @@ -1779,11 +1776,11 @@ static void chv_disable_pll(struct drm_i915_private
> *dev_priv, enum pipe pipe)
> /* Make sure the pipe isn't still relying on us */
> assert_pipe_disabled(dev_priv, pipe);
>
> - /* Set PLL en = 0 */
> val = DPLL_SSC_REF_CLK_CHV |
> DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> if (pipe != PIPE_A)
> val |= DPLL_INTEGRATED_CRI_CLK_VLV;
> +
> I915_WRITE(DPLL(pipe), val);
> POSTING_READ(DPLL(pipe));
>
> @@ -7240,24 +7237,27 @@ void intel_dp_set_m_n(struct intel_crtc *crtc, enum
> link_m_n_set m_n)
> static void vlv_compute_dpll(struct intel_crtc *crtc,
>struct intel_crtc_state *pipe_config)
> {
> - u32 dpll, dpll_md;
> + pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
> + DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
> + DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;
> + if (crtc->pipe != PIPE_A)
> + pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
>
> - /*
> - * Enable DPIO clock input. We should never disable the reference
> - * clock for pipe B, since VGA hotplug / manual detection depends
> - * on it.
> - */
> - dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
> - DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
> - /* We should never disable this, set it here for state tracking */
> - if (crtc->pipe == PIPE_B)
> - dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
> - dpll |= DPLL_VCO_ENABLE;
> - pipe_config->dpll_hw_state.dpll = dpll;
> + pipe_config->dpll_hw_state.dpll_md =
> + (pipe_config->pixel_multiplier - 1) <<
> DPLL_MD_UDI_MULTIPLIER_SHIFT;
> +}
> +
> +static void chv_compute_dpll(struct intel_crtc *crtc,
> + struct intel_crtc_state *pipe_config)
> +{
> + pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
> + DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
> + DPLL_VCO_ENABLE;
> + if (crtc->pipe != PIPE_A)
> + pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
>
> - dpll_md = (pipe_config->pixel_multiplier - 1)
> - << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> - pipe_config->dpll_hw_state.dpll_md = dpll_md;
> + pipe_config->dpll_hw_state.dpll_md =
> + (pipe_config->pixel_multiplier - 1) <<
> DPLL_MD_UDI_MULTIPLIER_SHIFT;
> }
>
> static void vlv_prepare_pll(struct intel_crtc *crtc,
> @@ -7351,19 +7351,6 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
> mutex_unlock(&dev_priv->sb_lock);
> }
>
> -static void chv_compute_dpll(struct intel_crtc *crtc,
> - struct intel_crtc_state *pipe_config)
> -{
> - pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
> - DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
> - DPLL_VCO_ENABLE;
> - if (crtc->pipe != PIPE_A)
> - pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
> -
> - pipe_config->dpll_hw_state.dpll_md =
> - (pipe_config->pixel_mul
Re: [Intel-gfx] [PATCH 15/16] drm/i915: Hook up pfit for DSI
On Tue, 15 Mar 2016, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Add the scaling mode property to DSI connectors, handle changes in the
> property value, and compute the panel fitter state during
> .compute_config().
>
> v2: Handle BXT as well
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 74
> +---
> 1 file changed, 69 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 1b4e83df4560..3823425a3e36 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -268,10 +268,12 @@ static inline bool is_cmd_mode(struct intel_dsi
> *intel_dsi)
> static bool intel_dsi_compute_config(struct intel_encoder *encoder,
>struct intel_crtc_state *pipe_config)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
> base);
> struct intel_connector *intel_connector = intel_dsi->attached_connector;
> - struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + const struct drm_display_mode *fixed_mode =
> intel_connector->panel.fixed_mode;
> struct drm_display_mode *adjusted_mode =
> &pipe_config->base.adjusted_mode;
> int ret;
>
> @@ -279,9 +281,17 @@ static bool intel_dsi_compute_config(struct
> intel_encoder *encoder,
>
> pipe_config->has_dsi_encoder = true;
>
> - if (fixed_mode)
> + if (fixed_mode) {
> intel_fixed_panel_mode(fixed_mode, adjusted_mode);
>
> + if (HAS_GMCH_DISPLAY(dev_priv))
> + intel_gmch_panel_fitting(crtc, pipe_config,
> +
> intel_connector->panel.fitting_mode);
> + else
> + intel_pch_panel_fitting(crtc, pipe_config,
> +
> intel_connector->panel.fitting_mode);
> + }
> +
> /* DSI uses short packets for sync events, so clear mode flags for DSI
> */
> adjusted_mode->flags = 0;
>
> @@ -731,7 +741,7 @@ intel_dsi_mode_valid(struct drm_connector *connector,
>struct drm_display_mode *mode)
> {
> struct intel_connector *intel_connector = to_intel_connector(connector);
> - struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
> + const struct drm_display_mode *fixed_mode =
> intel_connector->panel.fixed_mode;
> int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
>
> DRM_DEBUG_KMS("\n");
> @@ -1054,6 +1064,43 @@ static int intel_dsi_get_modes(struct drm_connector
> *connector)
> return 1;
> }
>
> +static int intel_dsi_set_property(struct drm_connector *connector,
> + struct drm_property *property,
> + uint64_t val)
> +{
> + struct drm_device *dev = connector->dev;
> + struct intel_connector *intel_connector = to_intel_connector(connector);
> + struct drm_crtc *crtc;
> + int ret;
> +
> + ret = drm_object_property_set_value(&connector->base, property, val);
> + if (ret)
> + return ret;
> +
> + if (property == dev->mode_config.scaling_mode_property) {
> + if (val == DRM_MODE_SCALE_NONE) {
> + DRM_DEBUG_KMS("no scaling not supported\n");
> + return -EINVAL;
> + }
> +
> + if (intel_connector->panel.fitting_mode == val)
> + return 0;
> +
> + intel_connector->panel.fitting_mode = val;
> + }
> +
> + crtc = intel_attached_encoder(connector)->base.crtc;
> + if (crtc && crtc->state->enable) {
> + /*
> + * If the CRTC is enabled, the display will be changed
> + * according to the new panel fitting mode.
> + */
> + intel_crtc_restore_mode(crtc);
> + }
> +
> + return 0;
> +}
> +
> static void intel_dsi_connector_destroy(struct drm_connector *connector)
> {
> struct intel_connector *intel_connector = to_intel_connector(connector);
> @@ -1096,11 +1143,25 @@ static const struct drm_connector_funcs
> intel_dsi_connector_funcs = {
> .detect = intel_dsi_detect,
> .destroy = intel_dsi_connector_destroy,
> .fill_modes = drm_helper_probe_single_connector_modes,
> + .set_property = intel_dsi_set_property,
> .atomic_get_property = intel_connector_atomic_get_property,
> .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> };
>
> +static void intel_dsi_add_properties(struct intel_connector *connector)
> +
Re: [Intel-gfx] [PATCH 08/10] drm/imx: Don't set a gamma table size
Hi Daniel,
Am Mittwoch, den 30.03.2016, 11:51 +0200 schrieb Daniel Vetter:
> imx doesn't have any functions for setting the gamma table, so this is
> completely defunct.
>
> Not nice to lie to userspace, so let's stop!
Thank you for the patch. Now the ret variable and the err_register label
are both unused, so I have applied it with the following fixup:
diff --git a/drivers/gpu/drm/imx/imx-drm-core.c
b/drivers/gpu/drm/imx/imx-drm-core.c
index 21a5293..e26dcde 100644
--- a/drivers/gpu/drm/imx/imx-drm-core.c
+++ b/drivers/gpu/drm/imx/imx-drm-core.c
@@ -326,7 +326,6 @@ int imx_drm_add_crtc(struct drm_device *drm, struct
drm_crtc *crtc,
{
struct imx_drm_device *imxdrm = drm->dev_private;
struct imx_drm_crtc *imx_drm_crtc;
- int ret;
/*
* The vblank arrays are dimensioned by MAX_CRTC - we can't
@@ -358,11 +357,6 @@ int imx_drm_add_crtc(struct drm_device *drm, struct
drm_crtc *crtc,
imx_drm_crtc->imx_drm_helper_funcs.crtc_funcs, NULL);
return 0;
-
-err_register:
- imxdrm->crtc[--imxdrm->pipes] = NULL;
- kfree(imx_drm_crtc);
- return ret;
}
EXPORT_SYMBOL_GPL(imx_drm_add_crtc);
regards
Philipp
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Re: [Intel-gfx] [PATCH 16/16] drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms
On Tue, 15 Mar 2016, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> We don't have a LVDS_BORDER_ENABLE type of bit for either eDP or DSI,
> and just trying to frob the display timings to include borders results
> in a corrupted picture. So reject the 'Center' scaling mode on GMCH
> platforms for eDP and DSI.
>
> TODO: Should really filter out the unsupported modes from the prop,
> but that would be fairly invasive since the prop is now created and
> stored by drm core. So leave it for a rainy day.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_dp.c | 5 +
> drivers/gpu/drm/i915/intel_dsi.c | 5 +
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 0e326e776e8f..f268bda6d55e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4754,6 +4754,11 @@ intel_dp_set_property(struct drm_connector *connector,
> DRM_DEBUG_KMS("no scaling not supported\n");
> return -EINVAL;
> }
> + if (HAS_GMCH_DISPLAY(dev_priv) &&
> + val == DRM_MODE_SCALE_CENTER) {
> + DRM_DEBUG_KMS("centering not supported\n");
> + return -EINVAL;
> + }
>
> if (intel_connector->panel.fitting_mode == val) {
> /* the eDP scaling property is not changed */
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 3823425a3e36..0ffa125a83e7 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -1082,6 +1082,11 @@ static int intel_dsi_set_property(struct drm_connector
> *connector,
> DRM_DEBUG_KMS("no scaling not supported\n");
> return -EINVAL;
> }
> + if (HAS_GMCH_DISPLAY(dev) &&
> + val == DRM_MODE_SCALE_CENTER) {
> + DRM_DEBUG_KMS("centering not supported\n");
> + return -EINVAL;
> + }
>
> if (intel_connector->panel.fitting_mode == val)
> return 0;
--
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/BXT: Get pipe conf from the port registers
Jani,
Thanks for the review comments. Addressing them in the next patch ver.
On Wednesday 30 March 2016 04:13 PM, Jani Nikula wrote:
On Tue, 29 Mar 2016, Ramalingam C wrote:
At BXT DSI, PIPE registers are inactive. So we can't get the
PIPE's mode parameters from them. The possible option is
retriving them from the PORT registers.
The required changes are added for BXT in intel_dsi_get_config
(encoder->get_config).
Signed-off-by: Ramalingam C
Signed-off-by: Uma Shankar
---
Previously reviewed at https://patchwork.freedesktop.org/patch/75301/
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 44 ++
drivers/gpu/drm/i915/intel_dsi.c | 104 ++
3 files changed, 149 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c839ce9..da3cdef 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8210,6 +8210,7 @@ enum skl_disp_power_wells {
#define BXT_PIPE_SELECT_SHIFT7
#define BXT_PIPE_SELECT_MASK (7 << 7)
#define BXT_PIPE_SELECT(pipe)((pipe) << 7)
+#define BXT_PORT_TO_PIPE(ctrl)((ctrl & BXT_PIPE_SELECT_MASK)
>> 7)
#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 29aa64b..c0627d6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9941,11 +9941,40 @@ static void haswell_get_ddi_port_state(struct
intel_crtc *crtc,
}
}
+struct intel_encoder *bxt_get_dsi_encoder_for_crtc(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_encoder *intel_encoder;
+ struct intel_dsi *intel_dsi;
+ enum port port;
+ u32 tmp;
+
+ for_each_intel_encoder(dev, intel_encoder) {
+ if (intel_encoder->type == INTEL_OUTPUT_DSI) {
+ intel_dsi = enc_to_intel_dsi(&intel_encoder->base);
+ for_each_dsi_port(port, intel_dsi->ports) {
+ if (!(I915_READ(BXT_MIPI_PORT_CTRL(port)) &
+ DPI_ENABLE))
+ break;
+
+ tmp = I915_READ(MIPI_CTRL(port));
+ if ((tmp & BXT_PIPE_SELECT_MASK) ==
+ BXT_PIPE_SELECT(crtc->pipe))
+ return intel_encoder;
+ }
+ }
+ }
+ return NULL;
+}
+
static bool haswell_get_pipe_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_encoder *intel_encoder, *attached_encoder = NULL;
enum intel_display_power_domain power_domain;
unsigned long power_domain_mask;
bool active;
@@ -9965,6 +9994,21 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
WARN_ON(active && pipe_config->has_dsi_encoder);
if (pipe_config->has_dsi_encoder)
active = true;
+
+ for_each_encoder_on_crtc(dev, &crtc->base, intel_encoder)
+ attached_encoder = intel_encoder;
+
+ /*
+* attached_encoder will be NULL, if there is no modeset from
+* the kernel bootup.
+*/
+ if (!attached_encoder && pipe_config->has_dsi_encoder)
+ attached_encoder =
+ bxt_get_dsi_encoder_for_crtc(crtc, pipe_config);
+
+ if (attached_encoder && attached_encoder->get_config)
+ attached_encoder->get_config(attached_encoder,
+ pipe_config);
No, you must not add a new call to the encoder->get_config() hook.
haswell_get_pipe_config() is called through the
dev_priv->display.get_pipe_config() function pointer. This happens in
check_crtc_state() and intel_modeset_readout_hw_state(). In both places,
encoder->get_config() is called afterwards, if encoder->get_hw_state()
returns true for the encoder.
The infrastructure is there, you only need to update DSI ->get_config().
Thanks for catching such a redundant lines. dropping them.
}
if (!active)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 0de74e1..69a80
Re: [Intel-gfx] [PATCH] drm/core: Add drm_accurate_vblank_count_and_time.
Op 30-03-16 om 15:13 schreef Ville Syrjälä: > On Tue, Mar 29, 2016 at 03:38:55PM +0200, Maarten Lankhorst wrote: >> This function is useful for gen2 intel devices which have no frame >> counter, but need a way to determine the current vblank count without >> racing with the vblank interrupt handler. >> >> intel_pipe_update_start checks if no vblank interrupt will occur >> during vblank evasion, but cannot check whether the vblank handler has >> run to completion. This function uses the timestamps to determine >> when the last vblank has happened, and interpolates from there. > Didn't really read it in detail, but on a glance it seems too > complicated to me. All we should really need is something like this: > > drm_vblank_get(); > drm_update_vblank_count(); > accurate = drm_vblank_count(); > Updating from non vblank irq context might cause the vblank clock to drift, or at least contend the vblank lock. This is why I call drm_vblank_count_and_time, and then interpolate as if update_vblank_count was called on the result. ~Maarten ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/core: Add drm_accurate_vblank_count_and_time.
On Wed, Mar 30, 2016 at 03:41:26PM +0200, Maarten Lankhorst wrote: > Op 30-03-16 om 15:13 schreef Ville Syrjälä: > > On Tue, Mar 29, 2016 at 03:38:55PM +0200, Maarten Lankhorst wrote: > >> This function is useful for gen2 intel devices which have no frame > >> counter, but need a way to determine the current vblank count without > >> racing with the vblank interrupt handler. > >> > >> intel_pipe_update_start checks if no vblank interrupt will occur > >> during vblank evasion, but cannot check whether the vblank handler has > >> run to completion. This function uses the timestamps to determine > >> when the last vblank has happened, and interpolates from there. > > Didn't really read it in detail, but on a glance it seems too > > complicated to me. All we should really need is something like this: > > > > drm_vblank_get(); > > drm_update_vblank_count(); > > accurate = drm_vblank_count(); > > > Updating from non vblank irq context might cause the vblank clock to drift, > or at least contend the vblank lock. I don't see a problem. The scanout position is anyway used to fix up the timestamp. > > This is why I call drm_vblank_count_and_time, and then interpolate as if > update_vblank_count was called on the result. > > ~Maarten -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 04/10] drm/sysfs: Nuke TV/DVI property files
On Wed, Mar 30, 2016 at 5:45 AM, Daniel Vetter wrote:
> This goes all the way back to the original KMS commit aeons ago
>
> commit f453ba0460742ad027ae0c4c7d61e62817b3e7ef
> Author: Dave Airlie
> Date: Fri Nov 7 14:05:41 2008 -0800
>
> DRM: add mode setting support
>
> But it seems to be completely unused. Only i915 and nouveau even
> register these properties, and the corresponding DDX don't even look
> at them. Also the sysfs files are read-only, so not useful to
> configure anything.
>
> I suspect that this was added with the goal to have read-only access
> to all properties in sysfs, but we never followed through on that.
> Also, that should be done in a more generic fashion.
>
> Since it would be real work to fix up the locking (with atomic we're
> now chasing pointers when reading properties) and it seems unused lets
> just nuke this all. It's easier. Of course we'll keep the properties
> themselves, those are still exposed through the KMS ioctls.
>
> Signed-off-by: Daniel Vetter
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/drm_sysfs.c | 156
>
> 1 file changed, 156 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
> index 43875cb35691..fa7fadce8063 100644
> --- a/drivers/gpu/drm/drm_sysfs.c
> +++ b/drivers/gpu/drm/drm_sysfs.c
> @@ -292,102 +292,6 @@ static ssize_t modes_show(struct device *device,
> return written;
> }
>
> -static ssize_t tv_subconnector_show(struct device *device,
> - struct device_attribute *attr,
> - char *buf)
> -{
> - struct drm_connector *connector = to_drm_connector(device);
> - struct drm_device *dev = connector->dev;
> - struct drm_property *prop;
> - uint64_t subconnector;
> - int ret;
> -
> - prop = dev->mode_config.tv_subconnector_property;
> - if (!prop) {
> - DRM_ERROR("Unable to find subconnector property\n");
> - return 0;
> - }
> -
> - ret = drm_object_property_get_value(&connector->base, prop,
> &subconnector);
> - if (ret)
> - return 0;
> -
> - return snprintf(buf, PAGE_SIZE, "%s",
> - drm_get_tv_subconnector_name((int)subconnector));
> -}
> -
> -static ssize_t tv_select_subconnector_show(struct device *device,
> - struct device_attribute *attr,
> - char *buf)
> -{
> - struct drm_connector *connector = to_drm_connector(device);
> - struct drm_device *dev = connector->dev;
> - struct drm_property *prop;
> - uint64_t subconnector;
> - int ret;
> -
> - prop = dev->mode_config.tv_select_subconnector_property;
> - if (!prop) {
> - DRM_ERROR("Unable to find select subconnector property\n");
> - return 0;
> - }
> -
> - ret = drm_object_property_get_value(&connector->base, prop,
> &subconnector);
> - if (ret)
> - return 0;
> -
> - return snprintf(buf, PAGE_SIZE, "%s",
> - drm_get_tv_select_name((int)subconnector));
> -}
> -
> -static ssize_t dvii_subconnector_show(struct device *device,
> - struct device_attribute *attr,
> - char *buf)
> -{
> - struct drm_connector *connector = to_drm_connector(device);
> - struct drm_device *dev = connector->dev;
> - struct drm_property *prop;
> - uint64_t subconnector;
> - int ret;
> -
> - prop = dev->mode_config.dvi_i_subconnector_property;
> - if (!prop) {
> - DRM_ERROR("Unable to find subconnector property\n");
> - return 0;
> - }
> -
> - ret = drm_object_property_get_value(&connector->base, prop,
> &subconnector);
> - if (ret)
> - return 0;
> -
> - return snprintf(buf, PAGE_SIZE, "%s",
> - drm_get_dvi_i_subconnector_name((int)subconnector));
> -}
> -
> -static ssize_t dvii_select_subconnector_show(struct device *device,
> -struct device_attribute *attr,
> -char *buf)
> -{
> - struct drm_connector *connector = to_drm_connector(device);
> - struct drm_device *dev = connector->dev;
> - struct drm_property *prop;
> - uint64_t subconnector;
> - int ret;
> -
> - prop = dev->mode_config.dvi_i_select_subconnector_property;
> - if (!prop) {
> - DRM_ERROR("Unable to find select subconnector property\n");
> - return 0;
> - }
> -
> - ret = drm_object_property_get_value(&connector->base, prop,
> &subconnector);
> - if (ret)
> - return 0;
> -
> - return snprintf(buf, PAGE_SIZE, "%s",
> - drm_get_dvi_i_select_name((int)s
Re: [Intel-gfx] [PATCH 3/5] drm/i915: Parse LFP brightness control field in VBT
On Tue, 29 Mar 2016, "Deepak, M" wrote:
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Tuesday, March 29, 2016 8:31 PM
>> To: intel-gfx@lists.freedesktop.org; Deepak, M
>> Cc: Nikula, Jani
>> Subject: [PATCH 3/5] drm/i915: Parse LFP brightness control field in VBT
>>
>> From: Deepak M
>>
>> These fields in VBT indicates the PWM source which is used and also the
>> controller number.
>>
>> v2 by Jani: check for out of bounds access, some renames, change default
>> type, etc.
>>
>> Signed-off-by: Deepak M
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>> drivers/gpu/drm/i915/intel_bios.c | 9 +
>> drivers/gpu/drm/i915/intel_bios.h | 8
>> drivers/gpu/drm/i915/intel_vbt_defs.h | 6 ++
>> 4 files changed, 24 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h index 0906dfd7b1a9..4a76b7b2dbd9
>> 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1472,6 +1472,7 @@ struct intel_vbt_data {
>> bool present;
>> bool active_low_pwm;
>> u8 min_brightness; /* min_brightness/255 of max */
>> +enum intel_backlight_type type;
>> } backlight;
>>
>> /* MIPI DSI */
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c
>> b/drivers/gpu/drm/i915/intel_bios.c
>> index 6985519921b4..2f639820aded 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -304,6 +304,15 @@ parse_lfp_backlight(struct drm_i915_private
>> *dev_priv,
>> return;
>> }
>>
>> +dev_priv->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
>> +if (bdb->version >= 191 &&
>> +get_blocksize(backlight_data) >= sizeof(*backlight_data)) {
>> +const struct bdb_lfp_backlight_control_method *method;
>> +
>> +method = &backlight_data->backlight_control[panel_type];
>> +dev_priv->vbt.backlight.type = method->type;
>> +}
>> +
>> dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
>> dev_priv->vbt.backlight.active_low_pwm = entry-
>> >active_low_pwm;
>> dev_priv->vbt.backlight.min_brightness = entry->min_brightness;
>> diff --git a/drivers/gpu/drm/i915/intel_bios.h
>> b/drivers/gpu/drm/i915/intel_bios.h
>> index 149c3226e895..df6ce3e3d26f 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.h
>> +++ b/drivers/gpu/drm/i915/intel_bios.h
>> @@ -30,6 +30,14 @@
>> #ifndef _INTEL_BIOS_H_
>> #define _INTEL_BIOS_H_
>>
>> +enum intel_backlight_type {
>> +INTEL_BACKLIGHT_PMIC,
>> +INTEL_BACKLIGHT_LPSS,
>> +INTEL_BACKLIGHT_DISPLAY_DDI,
>> +INTEL_BACKLIGHT_CABC,
> [Deepak, M] Better to rename CABC to PANEL_PWM, because CABC is not
> the source of the PWM. There may be some panel which have the panel
> PWM but may not support CABC.
How about INTEL_BACKLIGHT_DSI_DCS?
The panel need not have PWM. Really, the panel need not have backlight
either for panel brightness control (see OLED), but in this case I'd
just conflate that into "backlight" as well.
BR,
Jani.
>> +INTEL_BACKLIGHT_PANEL_DRIVER_INTERFACE,
>> +};
>> +
>> struct edp_power_seq {
>> u16 t1_t3;
>> u16 t8;
>> diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h
>> b/drivers/gpu/drm/i915/intel_vbt_defs.h
>> index 749dceab7c02..2191076c3ff6 100644
>> --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
>> +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
>> @@ -440,10 +440,16 @@ struct bdb_lfp_backlight_data_entry {
>> u8 obsolete3;
>> } __packed;
>>
>> +struct bdb_lfp_backlight_control_method {
>> +u8 type:4;
>> +u8 controller:4;
>> +} __packed;
>> +
>> struct bdb_lfp_backlight_data {
>> u8 entry_size;
>> struct bdb_lfp_backlight_data_entry data[16];
>> u8 level[16];
>> +struct bdb_lfp_backlight_control_method backlight_control[16];
>> } __packed;
>>
>> struct aimdb_header {
>> --
>> 2.1.4
>
--
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH] vgacon: dummy implementation for vgacon_text_force
On Wed, Mar 30, 2016 at 5:26 AM, Daniel Vetter wrote:
> This allows us to ditch a ton of ugly #ifdefs from a bunch of drm modeset
> drivers.
>
> v2: Make the dummy function actually return a sane value, spotted by
> Ville.
>
> v3: Because the patch is still in limbo there's no more drivers to
> convert, noticed by Emil.
>
> v4: Rebase once more, because hooray. I'll just go ahead an apply this
> one later on to drm-misc.
>
> Cc: Emil Velikov
> Cc: Ville Syrjälä
> Cc: Andrew Morton
> Cc: Greg Kroah-Hartman
> Signed-off-by: Daniel Vetter
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 --
> drivers/gpu/drm/ast/ast_drv.c | 2 --
> drivers/gpu/drm/cirrus/cirrus_drv.c | 2 --
> drivers/gpu/drm/i915/i915_drv.c | 2 --
> drivers/gpu/drm/mgag200/mgag200_drv.c | 2 --
> drivers/gpu/drm/nouveau/nouveau_drm.c | 2 --
> drivers/gpu/drm/qxl/qxl_drv.c | 2 --
> drivers/gpu/drm/radeon/radeon_drv.c | 2 --
> drivers/gpu/drm/virtio/virtgpu_drv.c| 2 --
> drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 2 --
> include/linux/console.h | 2 ++
> 11 files changed, 2 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index f1e17d60055a..93462aea9faa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -556,12 +556,10 @@ static struct pci_driver amdgpu_kms_pci_driver = {
> static int __init amdgpu_init(void)
> {
> amdgpu_sync_init();
> -#ifdef CONFIG_VGA_CONSOLE
> if (vgacon_text_force()) {
> DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
> return -EINVAL;
> }
> -#endif
> DRM_INFO("amdgpu kernel modesetting enabled.\n");
> driver = &kms_driver;
> pdriver = &amdgpu_kms_pci_driver;
> diff --git a/drivers/gpu/drm/ast/ast_drv.c b/drivers/gpu/drm/ast/ast_drv.c
> index 9a32d9dfdd26..fcd9c0714836 100644
> --- a/drivers/gpu/drm/ast/ast_drv.c
> +++ b/drivers/gpu/drm/ast/ast_drv.c
> @@ -218,10 +218,8 @@ static struct drm_driver driver = {
>
> static int __init ast_init(void)
> {
> -#ifdef CONFIG_VGA_CONSOLE
> if (vgacon_text_force() && ast_modeset == -1)
> return -EINVAL;
> -#endif
>
> if (ast_modeset == 0)
> return -EINVAL;
> diff --git a/drivers/gpu/drm/cirrus/cirrus_drv.c
> b/drivers/gpu/drm/cirrus/cirrus_drv.c
> index 7bc394ec9fb3..dc83f69da6f1 100644
> --- a/drivers/gpu/drm/cirrus/cirrus_drv.c
> +++ b/drivers/gpu/drm/cirrus/cirrus_drv.c
> @@ -163,10 +163,8 @@ static struct pci_driver cirrus_pci_driver = {
>
> static int __init cirrus_init(void)
> {
> -#ifdef CONFIG_VGA_CONSOLE
> if (vgacon_text_force() && cirrus_modeset == -1)
> return -EINVAL;
> -#endif
>
> if (cirrus_modeset == 0)
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index f73b4f7b2d39..349e17cc8540 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1754,10 +1754,8 @@ static int __init i915_init(void)
> if (i915.modeset == 0)
> driver.driver_features &= ~DRIVER_MODESET;
>
> -#ifdef CONFIG_VGA_CONSOLE
> if (vgacon_text_force() && i915.modeset == -1)
> driver.driver_features &= ~DRIVER_MODESET;
> -#endif
>
> if (!(driver.driver_features & DRIVER_MODESET)) {
> /* Silently fail loading to not upset userspace. */
> diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.c
> b/drivers/gpu/drm/mgag200/mgag200_drv.c
> index b0af77454d52..ebb470ff7200 100644
> --- a/drivers/gpu/drm/mgag200/mgag200_drv.c
> +++ b/drivers/gpu/drm/mgag200/mgag200_drv.c
> @@ -116,10 +116,8 @@ static struct pci_driver mgag200_pci_driver = {
>
> static int __init mgag200_init(void)
> {
> -#ifdef CONFIG_VGA_CONSOLE
> if (vgacon_text_force() && mgag200_modeset == -1)
> return -EINVAL;
> -#endif
>
> if (mgag200_modeset == 0)
> return -EINVAL;
> diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c
> b/drivers/gpu/drm/nouveau/nouveau_drm.c
> index d06877d9c1ed..db5c7d0cc25c 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_drm.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
> @@ -1083,10 +1083,8 @@ nouveau_drm_init(void)
> nouveau_display_options();
>
> if (nouveau_modeset == -1) {
> -#ifdef CONFIG_VGA_CONSOLE
> if (vgacon_text_force())
> nouveau_modeset = 0;
> -#endif
> }
>
> if (!nouveau_modeset)
> diff --git a/drivers/gpu/drm/qxl/qxl_drv.c b/drivers/gpu/drm/qxl/qxl_drv.c
> index 7307b07fe06b..dc9df5fe50ba 100644
> --- a/drivers/gpu/drm/qxl/qxl_drv.c
> +++ b/drivers/gpu/drm/qxl/qxl_drv.c
> @@ -272,10 +272,8 @@ static struct drm_driver qxl_driver = {
>
> static int __init qxl_init(void)
> {
> -#ifdef CONFIG_VGA_
[Intel-gfx] [PATCH v4] drm/i915: Refer to GGTT {,VM} consistently
Refer to the GGTT VM consistently as "ggtt->base" instead of just "ggtt",
"vm" or indirectly through other variables like "dev_priv->ggtt.base"
to avoid confusion with the i915_ggtt object itself and PPGTT VMs.
Refer to the GGTT as "ggtt" instead of indirectly through chaining.
As a bonus gets rid of the long-standing i915_obj_to_ggtt vs.
i915_gem_obj_to_ggtt conflict, due to removal of i915_obj_to_ggtt!
v2:
- Added some more after grepping sources with Chris
v3:
- Refer to GGTT VM through ggtt->base consistently instead of ggtt_vm (Chris)
v4:
- Convert all dev_priv->ggtt->foo accesses to ggtt->foo.
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Chris Wilson
Signed-off-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c| 19 ++--
drivers/gpu/drm/i915/i915_dma.c| 21 ++--
drivers/gpu/drm/i915/i915_drv.h| 13 ++-
drivers/gpu/drm/i915/i915_gem.c| 50 ++---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 12 +-
drivers/gpu/drm/i915/i915_gem_gtt.c| 170 +++--
drivers/gpu/drm/i915/i915_gem_gtt.h| 2 +-
drivers/gpu/drm/i915/i915_gem_stolen.c | 98 +
drivers/gpu/drm/i915/i915_gpu_error.c | 12 +-
drivers/gpu/drm/i915/i915_vgpu.c | 36 +++---
drivers/gpu/drm/i915/intel_display.c | 8 +-
drivers/gpu/drm/i915/intel_fbc.c | 5 +-
drivers/gpu/drm/i915/intel_fbdev.c | 10 +-
drivers/gpu/drm/i915/intel_overlay.c | 10 +-
drivers/gpu/drm/i915/intel_pm.c| 13 ++-
drivers/gpu/drm/i915/intel_ringbuffer.c| 3 +-
16 files changed, 264 insertions(+), 218 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index d02f8ce..74f2274 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -202,8 +202,8 @@ static int i915_gem_object_list_info(struct seq_file *m,
void *data)
uintptr_t list = (uintptr_t) node->info_ent->data;
struct list_head *head;
struct drm_device *dev = node->minor->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct i915_address_space *vm = &dev_priv->ggtt.base;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct i915_ggtt *ggtt = &dev_priv->ggtt;
struct i915_vma *vma;
u64 total_obj_size, total_gtt_size;
int count, ret;
@@ -216,11 +216,11 @@ static int i915_gem_object_list_info(struct seq_file *m,
void *data)
switch (list) {
case ACTIVE_LIST:
seq_puts(m, "Active:\n");
- head = &vm->active_list;
+ head = &ggtt->base.active_list;
break;
case INACTIVE_LIST:
seq_puts(m, "Inactive:\n");
- head = &vm->inactive_list;
+ head = &ggtt->base.inactive_list;
break;
default:
mutex_unlock(&dev->struct_mutex);
@@ -429,11 +429,11 @@ static int i915_gem_object_info(struct seq_file *m, void*
data)
{
struct drm_info_node *node = m->private;
struct drm_device *dev = node->minor->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct i915_ggtt *ggtt = &dev_priv->ggtt;
u32 count, mappable_count, purgeable_count;
u64 size, mappable_size, purgeable_size;
struct drm_i915_gem_object *obj;
- struct i915_address_space *vm = &dev_priv->ggtt.base;
struct drm_file *file;
struct i915_vma *vma;
int ret;
@@ -452,12 +452,12 @@ static int i915_gem_object_info(struct seq_file *m, void*
data)
count, mappable_count, size, mappable_size);
size = count = mappable_size = mappable_count = 0;
- count_vmas(&vm->active_list, vm_link);
+ count_vmas(&ggtt->base.active_list, vm_link);
seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
count, mappable_count, size, mappable_size);
size = count = mappable_size = mappable_count = 0;
- count_vmas(&vm->inactive_list, vm_link);
+ count_vmas(&ggtt->base.inactive_list, vm_link);
seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
count, mappable_count, size, mappable_size);
@@ -492,8 +492,7 @@ static int i915_gem_object_info(struct seq_file *m, void*
data)
count, size);
seq_printf(m, "%llu [%llu] gtt total\n",
- dev_priv->ggtt.base.total,
- (u64)dev_priv->ggtt.mappable_end -
dev_priv->ggtt.base.start);
+ ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
seq_putc(m, '\n');
print_batch_pool_stats(m, dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index d301173..73dcbcf 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i9
[Intel-gfx] [PATCH 1/2] drm/i915: Sharing the pixel_format_from_vbt to whole i915
Shared the function pixel_format_from_vbt for whole display module.
Function declaration is added to intel_dsi.h.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_dsi.h |1 +
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index ec58ead..9612916 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -126,6 +126,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct
drm_encoder *encoder)
return container_of(encoder, struct intel_dsi, base.base);
}
+enum mipi_dsi_pixel_format pixel_format_from_vbt(u32 fmt);
bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
extern void intel_disable_dsi_pll(struct intel_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 8302a97..d78d59c 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -413,7 +413,7 @@ static const struct drm_panel_funcs vbt_panel_funcs = {
};
/* XXX: This should be done when parsing the VBT in intel_bios.c */
-static enum mipi_dsi_pixel_format pixel_format_from_vbt(u32 fmt)
+enum mipi_dsi_pixel_format pixel_format_from_vbt(u32 fmt)
{
/* It just so happens the VBT matches register contents. */
switch (fmt) {
--
1.7.9.5
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[Intel-gfx] [PATCH 2/2] drm/i915/BXT: Get pipe conf from the port registers
At BXT DSI, PIPE registers are inactive. So we can't get the
PIPE's mode parameters from them. The possible option is
retriving them from the PORT registers.
The required changes are added for BXT in intel_dsi_get_config
(encoder->get_config).
v2: Addressed the Jani's comments
-removed the redundant call to encoder->get_config
-read bpp from port register
-removed retrival of src_size from encoder->get_config
Signed-off-by: Ramalingam C
Signed-off-by: Uma Shankar
---
Previously reviewed at https://patchwork.freedesktop.org/patch/75301/
drivers/gpu/drm/i915/intel_dsi.c | 99 ++
1 file changed, 99 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 0de74e1..2117187 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -46,6 +46,11 @@ static const struct {
},
};
+enum mipi_dsi_pixel_format reg_to_pixel_format(u32 fmt)
+{
+ return pixel_format_from_vbt(fmt);
+}
+
static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port
port)
{
struct drm_encoder *encoder = &intel_dsi->base.base;
@@ -740,14 +745,108 @@ out_put_power:
return active;
}
+/* return pixels equvalent to txbyteclkhs */
+static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
+ u16 burst_mode_ratio)
+{
+ return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
+ (bpp * burst_mode_ratio));
+}
+
+static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
+struct intel_crtc_state *pipe_config)
+{
+ struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_display_mode *adjusted_mode =
+ &pipe_config->base.adjusted_mode;
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ unsigned int lane_count = intel_dsi->lane_count;
+ unsigned int bpp, fmt;
+ enum port port;
+ u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
+
+ /*
+* Atleast one port is active as encoder->get_config called only if
+* encoder->get_hw_state() returns true.
+*/
+ for_each_dsi_port(port, intel_dsi->ports) {
+ if (!(I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE))
+ continue;
+ break;
+ }
+
+ fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
+ pipe_config->pipe_bpp = reg_to_pixel_format(fmt);
+
+ bpp = mipi_dsi_pixel_format_to_bpp(pipe_config->pipe_bpp);
+
+ /* In terms of pixels */
+ adjusted_mode->crtc_hdisplay =
+ I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
+ adjusted_mode->crtc_vdisplay =
+ I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
+ adjusted_mode->crtc_vtotal =
+ I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
+
+ hactive = adjusted_mode->crtc_hdisplay;
+ hfp = I915_READ(MIPI_HFP_COUNT(port));
+
+ /*
+* meaningful for video mode non-burst sync pulse mode only,
+* can be zero for non-burst sync events and burst modes
+*/
+ hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
+ hbp = I915_READ(MIPI_HBP_COUNT(port));
+
+ /* horizontal values are in terms of high speed byte clock */
+ hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
+ intel_dsi->burst_mode_ratio);
+ hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
+ intel_dsi->burst_mode_ratio);
+ hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
+ intel_dsi->burst_mode_ratio);
+
+ if (intel_dsi->dual_link) {
+ hfp *= 2;
+ hsync *= 2;
+ hbp *= 2;
+ }
+
+ /* vertical values are in terms of lines */
+ vfp = I915_READ(MIPI_VFP_COUNT(port));
+ vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
+ vbp = I915_READ(MIPI_VBP_COUNT(port));
+
+ adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
+ adjusted_mode->crtc_hsync_start =
+ hfp + adjusted_mode->crtc_hdisplay;
+ adjusted_mode->crtc_hsync_end =
+ hsync + adjusted_mode->crtc_hsync_start;
+ adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
+ adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
+
+ adjusted_mode->crtc_vsync_start =
+ vfp + adjusted_mode->crtc_vdisplay;
+ adjusted_mode->crtc_vsync_end =
+ vsync + adjusted_mode->crtc_vsync_start;
+ adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
+ adjusted_mode->c
[Intel-gfx] [PATCH 1/5] drm: Add new DCS commands in the enum list
From: Deepak M
Adding new DCS commands which are specified in the
DCS 1.3 spec related to CABC.
v2: Sorted the Macro`s by value (Andrzej)
v3 by Jani: sort all of enum, refer to MIPI DCS 1.3
Cc: Andrzej Hajda
Cc: Thierry Reding
Cc: David Airlie
Cc: Ville Syrjälä
Cc: Daniel Vetter
Cc:
Suggested-by: Jani Nikula
Signed-off-by: Deepak M
Signed-off-by: Jani Nikula
---
include/video/mipi_display.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/video/mipi_display.h b/include/video/mipi_display.h
index ddcc8ca7316b..19aa65a35546 100644
--- a/include/video/mipi_display.h
+++ b/include/video/mipi_display.h
@@ -115,6 +115,14 @@ enum {
MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
MIPI_DCS_GET_SCANLINE = 0x45,
+ MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */
+ MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 0x52, /* MIPI DCS 1.3 */
+ MIPI_DCS_WRITE_CONTROL_DISPLAY = 0x53, /* MIPI DCS 1.3 */
+ MIPI_DCS_GET_CONTROL_DISPLAY= 0x54, /* MIPI DCS 1.3 */
+ MIPI_DCS_WRITE_POWER_SAVE = 0x55, /* MIPI DCS 1.3 */
+ MIPI_DCS_GET_POWER_SAVE = 0x56, /* MIPI DCS 1.3 */
+ MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E,/* MIPI DCS 1.3 */
+ MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F,/* MIPI DCS 1.3 */
MIPI_DCS_READ_DDB_START = 0xA1,
MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
};
--
2.1.4
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[Intel-gfx] [PATCH 2/5] drm/i915: Parsing the PWM cntrl and CABC ON/OFF fields in VBT
From: Deepak M
For dual link panel scenarios there are new fields added in the
VBT which indicate on which port the PWM cntrl and CABC ON/OFF
commands needs to be sent.
v2: Moving the comment to intel_dsi.h(Jani)
v3: Renaming the field names (Jani)
v4 by Jani: make this patch only about VBT
Cc: Jani Nikula
Cc: Daniel Vetter
Cc: Yetunde Adebisi
Signed-off-by: Deepak M
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_bios.c | 10 ++
drivers/gpu/drm/i915/intel_bios.h | 8 +++-
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 9c406b0f4173..6985519921b4 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -746,6 +746,16 @@ parse_mipi_config(struct drm_i915_private *dev_priv,
return;
}
+ /*
+* These fields are introduced from the VBT version 197 onwards,
+* so making sure that these bits are set zero in the previous
+* versions.
+*/
+ if (dev_priv->vbt.dsi.config->dual_link && bdb->version < 197) {
+ dev_priv->vbt.dsi.config->dl_dcs_cabc_ports = 0;
+ dev_priv->vbt.dsi.config->dl_dcs_backlight_ports = 0;
+ }
+
/* We have mandatory mipi config blocks. Initialize as generic panel */
dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
}
diff --git a/drivers/gpu/drm/i915/intel_bios.h
b/drivers/gpu/drm/i915/intel_bios.h
index ab0ea315eddb..149c3226e895 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -113,7 +113,13 @@ struct mipi_config {
u16 dual_link:2;
u16 lane_cnt:2;
u16 pixel_overlap:3;
- u16 rsvd3:9;
+ u16 rgb_flip:1;
+#define DL_DCS_PORT_A 0x00
+#define DL_DCS_PORT_C 0x01
+#define DL_DCS_PORT_A_AND_C0x02
+ u16 dl_dcs_cabc_ports:2;
+ u16 dl_dcs_backlight_ports:2;
+ u16 rsvd3:4;
u16 rsvd4;
--
2.1.4
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[Intel-gfx] [PATCH 4/5] drm/i915: Add DCS control for Panel PWM
From: Deepak M
If the source of the backlight PWM is from the
panel then the PWM can be controlled by DCS
command, this patch adds the support to
enable/disbale panel PWM, control backlight level
etc...
v2: Moving the CABC bkl functions to new file.(Jani)
v3: Rebase
v4: Rebase
v5: Use mipi_dsi_dcs_write() instead of mipi_dsi_dcs_write_buffer() (Jani)
Move DCS macro`s to include/video/mipi_display.h (Jani)
v6: Rename the file to intel_dsi_panel_pwm.c
Removing the CABC operations
v7 by Jani: renames, rebases, etc.
v8 by Jani: s/INTEL_BACKLIGHT_CABC/INTEL_BACKLIGHT_DSI_DCS/
Cc: Jani Nikula
Cc: Daniel Vetter
Cc: Yetunde Adebisi
Signed-off-by: Deepak M
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_drv.h | 2 +
drivers/gpu/drm/i915/intel_dsi.c | 19 ++-
drivers/gpu/drm/i915/intel_dsi.h | 3 +
drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c | 157 +
drivers/gpu/drm/i915/intel_panel.c | 4 +
6 files changed, 184 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 7ffb51b0cbc2..3f6a3cfa6524 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -83,6 +83,7 @@ i915-y += dvo_ch7017.o \
intel_dp_mst.o \
intel_dp.o \
intel_dsi.o \
+ intel_dsi_dcs_backlight.o \
intel_dsi_panel_vbt.o \
intel_dsi_pll.o \
intel_dvo.o \
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c87b4503435d..17593d069819 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1325,6 +1325,8 @@ void intel_dp_mst_encoder_cleanup(struct
intel_digital_port *intel_dig_port);
/* intel_dsi.c */
void intel_dsi_init(struct drm_device *dev);
+/* intel_dsi_dcs_backlight.c */
+int intel_dsi_dcs_backlight_init_funcs(struct intel_connector
*intel_connector);
/* intel_dvo.c */
void intel_dvo_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 0de74e1b7ab3..9326e9dcbe50 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1220,10 +1220,25 @@ void intel_dsi_init(struct drm_device *dev)
else
intel_encoder->crtc_mask = BIT(PIPE_B);
- if (dev_priv->vbt.dsi.config->dual_link)
+ if (dev_priv->vbt.dsi.config->dual_link) {
intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
- else
+
+ switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) {
+ case DL_DCS_PORT_A:
+ intel_dsi->dcs_backlight_ports = BIT(PORT_A);
+ break;
+ case DL_DCS_PORT_C:
+ intel_dsi->dcs_backlight_ports = BIT(PORT_C);
+ break;
+ default:
+ case DL_DCS_PORT_A_AND_C:
+ intel_dsi->dcs_backlight_ports = BIT(PORT_A) |
BIT(PORT_C);
+ break;
+ }
+ } else {
intel_dsi->ports = BIT(port);
+ intel_dsi->dcs_backlight_ports = BIT(port);
+ }
/* Create a DSI host (and a device) for each port. */
for_each_dsi_port(port, intel_dsi->ports) {
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index ec58ead9ccd1..efb07f45316f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -78,6 +78,9 @@ struct intel_dsi {
u8 escape_clk_div;
u8 dual_link;
+
+ u16 dcs_backlight_ports;
+
u8 pixel_overlap;
u32 port_bits;
u32 bw_timer;
diff --git a/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c
b/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c
new file mode 100644
index ..bcc10c105c21
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c
@@ -0,0 +1,157 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PUR
[Intel-gfx] [PATCH 3/5] drm/i915: Parse LFP brightness control field in VBT
From: Deepak M
These fields in VBT indicates the PWM source which
is used and also the controller number.
v2 by Jani: check for out of bounds access, some renames, change default
type, etc.
v3 by Jani: s/INTEL_BACKLIGHT_CABC/INTEL_BACKLIGHT_DSI_DCS/
Signed-off-by: Deepak M
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_bios.c | 9 +
drivers/gpu/drm/i915/intel_bios.h | 8
drivers/gpu/drm/i915/intel_vbt_defs.h | 6 ++
4 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f6d71590bd7b..49c033c78f35 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1472,6 +1472,7 @@ struct intel_vbt_data {
bool present;
bool active_low_pwm;
u8 min_brightness; /* min_brightness/255 of max */
+ enum intel_backlight_type type;
} backlight;
/* MIPI DSI */
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 6985519921b4..2f639820aded 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -304,6 +304,15 @@ parse_lfp_backlight(struct drm_i915_private *dev_priv,
return;
}
+ dev_priv->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
+ if (bdb->version >= 191 &&
+ get_blocksize(backlight_data) >= sizeof(*backlight_data)) {
+ const struct bdb_lfp_backlight_control_method *method;
+
+ method = &backlight_data->backlight_control[panel_type];
+ dev_priv->vbt.backlight.type = method->type;
+ }
+
dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm;
dev_priv->vbt.backlight.min_brightness = entry->min_brightness;
diff --git a/drivers/gpu/drm/i915/intel_bios.h
b/drivers/gpu/drm/i915/intel_bios.h
index 149c3226e895..8405b5a367d7 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -30,6 +30,14 @@
#ifndef _INTEL_BIOS_H_
#define _INTEL_BIOS_H_
+enum intel_backlight_type {
+ INTEL_BACKLIGHT_PMIC,
+ INTEL_BACKLIGHT_LPSS,
+ INTEL_BACKLIGHT_DISPLAY_DDI,
+ INTEL_BACKLIGHT_DSI_DCS,
+ INTEL_BACKLIGHT_PANEL_DRIVER_INTERFACE,
+};
+
struct edp_power_seq {
u16 t1_t3;
u16 t8;
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h
b/drivers/gpu/drm/i915/intel_vbt_defs.h
index 749dceab7c02..2191076c3ff6 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -440,10 +440,16 @@ struct bdb_lfp_backlight_data_entry {
u8 obsolete3;
} __packed;
+struct bdb_lfp_backlight_control_method {
+ u8 type:4;
+ u8 controller:4;
+} __packed;
+
struct bdb_lfp_backlight_data {
u8 entry_size;
struct bdb_lfp_backlight_data_entry data[16];
u8 level[16];
+ struct bdb_lfp_backlight_control_method backlight_control[16];
} __packed;
struct aimdb_header {
--
2.1.4
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[Intel-gfx] [PATCH 5/5] CABC support for Panel PWM backlight control
From: Deepak M
In CABC (Content Adaptive Brightness Control) content grey level
scale can be increased while simultaneously decreasing
brightness of the backlight to achieve same perceived brightness.
The CABC is not standardized and panel vendors are free to follow
their implementation. The CABC implementaion here assumes that the
panels use standard SW register for control.
CABC is supported only when the PWM source for backlight is
from the panel.
v2 by Jani: rebase, renames, check cabc support earlier, etc.
Signed-off-by: Deepak M
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 17 +
drivers/gpu/drm/i915/intel_dsi.h | 1 +
drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c | 22 ++
3 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 9326e9dcbe50..6982f0b7dd2d 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1235,11 +1235,28 @@ void intel_dsi_init(struct drm_device *dev)
intel_dsi->dcs_backlight_ports = BIT(PORT_A) |
BIT(PORT_C);
break;
}
+
+ switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) {
+ case DL_DCS_PORT_A:
+ intel_dsi->dcs_cabc_ports = BIT(PORT_A);
+ break;
+ case DL_DCS_PORT_C:
+ intel_dsi->dcs_cabc_ports = BIT(PORT_C);
+ break;
+ default:
+ case DL_DCS_PORT_A_AND_C:
+ intel_dsi->dcs_cabc_ports = BIT(PORT_A) | BIT(PORT_C);
+ break;
+ }
} else {
intel_dsi->ports = BIT(port);
intel_dsi->dcs_backlight_ports = BIT(port);
+ intel_dsi->dcs_cabc_ports = BIT(port);
}
+ if (!dev_priv->vbt.dsi.config->cabc_supported)
+ intel_dsi->dcs_cabc_ports = 0;
+
/* Create a DSI host (and a device) for each port. */
for_each_dsi_port(port, intel_dsi->ports) {
struct intel_dsi_host *host;
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index efb07f45316f..6d84de30f289 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -80,6 +80,7 @@ struct intel_dsi {
u8 dual_link;
u16 dcs_backlight_ports;
+ u16 dcs_cabc_ports;
u8 pixel_overlap;
u32 port_bits;
diff --git a/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c
b/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c
index bcc10c105c21..9ca74e84c857 100644
--- a/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c
+++ b/drivers/gpu/drm/i915/intel_dsi_dcs_backlight.c
@@ -33,6 +33,12 @@
#define CONTROL_DISPLAY_DD (1 << 3)
#define CONTROL_DISPLAY_BL (1 << 2)
+#define POWER_SAVE_OFF (0 << 0)
+#define POWER_SAVE_LOW (1 << 0)
+#define POWER_SAVE_MEDIUM (2 << 0)
+#define POWER_SAVE_HIGH(3 << 0)
+#define POWER_SAVE_OUTDOOR_MODE(4 << 0)
+
#define PANEL_PWM_MAX_VALUE0xFF
static u32 dcs_get_backlight(struct intel_connector *connector)
@@ -79,6 +85,14 @@ static void dcs_disable_backlight(struct intel_connector
*connector)
dcs_set_backlight(connector, 0);
+ for_each_dsi_port(port, intel_dsi->dcs_cabc_ports) {
+ u8 cabc = POWER_SAVE_OFF;
+
+ dsi_device = intel_dsi->dsi_hosts[port]->device;
+ mipi_dsi_dcs_write(dsi_device, MIPI_DCS_WRITE_POWER_SAVE,
+ &cabc, sizeof(cabc));
+ }
+
for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) {
u8 ctrl = 0;
@@ -120,6 +134,14 @@ static void dcs_enable_backlight(struct intel_connector
*connector)
&ctrl, sizeof(ctrl));
}
+ for_each_dsi_port(port, intel_dsi->dcs_cabc_ports) {
+ u8 cabc = POWER_SAVE_MEDIUM;
+
+ dsi_device = intel_dsi->dsi_hosts[port]->device;
+ mipi_dsi_dcs_write(dsi_device, MIPI_DCS_WRITE_POWER_SAVE,
+ &cabc, sizeof(cabc));
+ }
+
dcs_set_backlight(connector, panel->backlight.level);
}
--
2.1.4
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Re: [Intel-gfx] [PATCH v4] drm/i915: Refer to GGTT {, VM} consistently
On Wed, Mar 30, 2016 at 04:57:10PM +0300, Joonas Lahtinen wrote: > Refer to the GGTT VM consistently as "ggtt->base" instead of just "ggtt", > "vm" or indirectly through other variables like "dev_priv->ggtt.base" > to avoid confusion with the i915_ggtt object itself and PPGTT VMs. > > Refer to the GGTT as "ggtt" instead of indirectly through chaining. > > As a bonus gets rid of the long-standing i915_obj_to_ggtt vs. > i915_gem_obj_to_ggtt conflict, due to removal of i915_obj_to_ggtt! > > v2: > - Added some more after grepping sources with Chris > > v3: > - Refer to GGTT VM through ggtt->base consistently instead of ggtt_vm (Chris) > > v4: > - Convert all dev_priv->ggtt->foo accesses to ggtt->foo. > > Cc: Tvrtko Ursulin > Cc: Mika Kuoppala > Cc: Chris Wilson > Signed-off-by: Joonas Lahtinen It pains me to see changes to code I've deleted, but nevertheless the consistency looks good. Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
