[Intel-gfx] [PATCH] drm/i915/bxt: Save/Restore Backlight registers when PG0 is gated
Currently Backlight registers which are associated with Power Well 0
are not being saved before gating the power well for S0ix. Hence,
upon resume from S0ix, these registers are not being restored. Due to
this, the display has resumed and since there is no backlight, nothing is
seen. Patch fixes this issue by saving/restoring BLC registers for S0ix.
Signed-off-by: A.Sunil Kamath
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_drv.h | 4
drivers/gpu/drm/i915/intel_panel.c | 18 ++
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 50f83d2..752fb58 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -193,6 +193,10 @@ struct intel_panel {
uint32_t hz);
void (*power)(struct intel_connector *, bool enable);
} backlight;
+
+ u32 blc_pwm_ctl;
+ u32 blc_pwm_freq;
+ u32 blc_pwm_duty;
};
struct intel_connector {
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index ae808b6..421cd3a 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -816,6 +816,16 @@ static void bxt_disable_backlight(struct intel_connector
*connector)
val &= ~UTIL_PIN_ENABLE;
I915_WRITE(UTIL_PIN_CTL, val);
}
+
+ /* Saving BLC registers for PG0 gating */
+ panel->blc_pwm_ctl =
+ I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+ panel->blc_pwm_freq =
+ I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller));
+ panel->blc_pwm_duty =
+ I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller));
+
+
}
static void pwm_disable_backlight(struct intel_connector *connector)
@@ -1050,6 +1060,14 @@ static void bxt_enable_backlight(struct intel_connector
*connector)
enum pipe pipe = intel_get_pipe_from_connector(connector);
u32 pwm_ctl, val;
+ /* Restore BLC registers if PG0 was gated */
+ I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+ panel->blc_pwm_ctl);
+ I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
+ panel->blc_pwm_freq);
+ I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller),
+ panel->blc_pwm_duty);
+
/* To use 2nd set of backlight registers, utility pin has to be
* enabled with PWM mode.
* The field should only be changed when the utility pin is disabled
--
1.9.1
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[Intel-gfx] ✗ warning: Fi.CI.BAT
== Summary == Built on 79686f613b3955a4ed09cee936e7f70ec4e61b67 drm-intel-nightly: 2015y-12m-30d-11h-59m-54s UTC integration manifest Test kms_flip: Subgroup basic-flip-vs-dpms: dmesg-warn -> PASS (ilk-hp8440p) Subgroup basic-flip-vs-modeset: dmesg-warn -> PASS (skl-i5k-2) dmesg-warn -> PASS (bsw-nuc-2) dmesg-warn -> PASS (ilk-hp8440p) Test kms_pipe_crc_basic: Subgroup read-crc-pipe-a: dmesg-warn -> PASS (snb-x220t) dmesg-warn -> PASS (byt-nuc) Subgroup read-crc-pipe-b: pass -> DMESG-WARN (snb-dellxps) Subgroup suspend-read-crc-pipe-b: pass -> DMESG-WARN (snb-x220t) Test kms_setmode: Subgroup basic-clone-single-crtc: dmesg-warn -> PASS (snb-dellxps) bdw-nuci7total:132 pass:121 dwarn:2 dfail:0 fail:0 skip:9 bdw-ultratotal:132 pass:124 dwarn:2 dfail:0 fail:0 skip:6 bsw-nuc-2total:135 pass:114 dwarn:1 dfail:0 fail:0 skip:20 byt-nuc total:135 pass:120 dwarn:2 dfail:0 fail:0 skip:13 hsw-brixbox total:135 pass:126 dwarn:2 dfail:0 fail:0 skip:7 hsw-gt2 total:135 pass:130 dwarn:1 dfail:0 fail:0 skip:4 hsw-xps12total:132 pass:125 dwarn:3 dfail:0 fail:0 skip:4 ilk-hp8440p total:135 pass:100 dwarn:0 dfail:0 fail:0 skip:35 ivb-t430stotal:135 pass:127 dwarn:2 dfail:0 fail:0 skip:6 skl-i5k-2total:135 pass:124 dwarn:3 dfail:0 fail:0 skip:8 skl-i7k-2total:135 pass:124 dwarn:3 dfail:0 fail:0 skip:8 snb-dellxps total:135 pass:121 dwarn:2 dfail:0 fail:0 skip:12 snb-x220ttotal:135 pass:121 dwarn:2 dfail:0 fail:1 skip:11 Results at /archive/results/CI_IGT_test/Patchwork_975/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Hold a RPM reference during i915_driver_unload
On 30.12.2015 15:03, Joonas Lahtinen wrote:
Hi,
On ti, 2015-12-29 at 12:55 +0200, Gabriel Feceoru wrote:
This fixes an issue added with: "1f814da drm/i915: add support for
checking
if we hold an RPM reference", noticed while running
drv_module_reload_basic.
WARNING: CPU: 1 PID: 2032 at drivers/gpu/drm/i915/intel_drv.h:1446
gen6_read32+0x1ca/0x1e0 [i915]()
[ 138.682686] RPM wakelock ref not held during HW access
[ 138.682687] Modules linked in:
[ 138.682688] i915(-) drm_kms_helper drm snd_hda_codec_hdmi
snd_hda_codec_realtek snd_hda_codec_generic snd_hda_codec snd_hwdep
x86_pkg_temp_thermal snd_hda_core i2c_algo_bit syscopyarea
sysfillrect sysimgblt fb_sys_fops xhci_pci ehci_pci r8169 xhci_hcd
mii ehci_hcd video [last unloaded: snd_hda_intel]
[ 138.682699] CPU: 1 PID: 2032 Comm: rmmod Tainted: GW
4.4.0-rc4+ #44
[ 138.682701] Hardware name: Dell Inc. Inspiron 3847/088DT1 ,
BIOS A06 01/15/2015
[ 138.682702] c03b6358 880210d8ba58 813e0c0f
880210d8baa0
[ 138.682703] 880210d8ba90 8105f6a2 8800daa4
00064400
[ 138.682705] 0004 880210d8bb9c 8800daa4
880210d8baf0
[ 138.682706] Call Trace:
[ 138.682710] [] dump_stack+0x44/0x55
[ 138.682713] [] warn_slowpath_common+0x82/0xc0
[ 138.682715] [] warn_slowpath_fmt+0x4c/0x50
[ 138.682725] [] ?
i915_gem_object_unpin_from_display_plane+0x1c/0x50 [i915]
[ 138.682734] [] gen6_read32+0x1ca/0x1e0 [i915]
[ 138.682737] [] ? mutex_lock+0x12/0x30
[ 138.682747] []
intel_ddi_get_hw_state+0x7a/0x180 [i915]
[ 138.682758] []
intel_connector_get_hw_state+0x28/0x30 [i915]
[ 138.682767] [] intel_atomic_commit+0xa9c/0x17e0
[i915]
[ 138.682779] [] ?
drm_atomic_check_only+0x18e/0x590 [drm]
[ 138.682786] [] ?
drm_atomic_add_affected_connectors+0x8c/0xf0 [drm]
[ 138.682792] [] drm_atomic_commit+0x37/0x60
[drm]
[ 138.682797] []
drm_atomic_helper_set_config+0x76/0xb0 [drm_kms_helper]
[ 138.682804] [] ?
drm_modeset_lock_all_ctx+0x9a/0xb0 [drm]
[ 138.682809] []
drm_mode_set_config_internal+0x62/0x100 [drm]
[ 138.682814] []
drm_framebuffer_remove+0xe8/0x120 [drm]
[ 138.682826] [] intel_fbdev_fini+0x6d/0x90
[i915]
[ 138.682838] [] i915_driver_unload+0x1a/0x290
[i915]
[ 138.682844] [] drm_dev_unregister+0x29/0xb0
[drm]
[ 138.682848] [] drm_put_dev+0x23/0x60 [drm]
[ 138.682854] [] i915_pci_remove+0x15/0x20 [i915]
[ 138.682856] [] pci_device_remove+0x39/0xc0
[ 138.682859] []
__device_release_driver+0xa1/0x150
[ 138.682860] [] driver_detach+0xa3/0xb0
[ 138.682862] [] bus_remove_driver+0x55/0xd0
[ 138.682864] [] driver_unregister+0x2c/0x50
[ 138.682866] [] pci_unregister_driver+0x21/0x90
[ 138.682871] [] drm_pci_exit+0x94/0xb0 [drm]
[ 138.682883] [] i915_exit+0x20/0xc1c [i915]
Reported-by: Marius Vlad
Signed-off-by: Gabriel Feceoru
---
drivers/gpu/drm/i915/i915_dma.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c
b/drivers/gpu/drm/i915/i915_dma.c
index 988a380..08ad01f0 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1136,6 +1136,8 @@ int i915_driver_unload(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
int ret;
+ intel_runtime_pm_get(dev_priv);
+
intel_fbdev_fini(dev);
i915_audio_component_cleanup(dev_priv);
@@ -1143,6 +1145,7 @@ int i915_driver_unload(struct drm_device *dev)
ret = i915_gem_suspend(dev);
if (ret) {
DRM_ERROR("failed to idle hardware: %d\n", ret);
+ intel_runtime_pm_put(dev_priv);
This should be made into goto construct.
I cannot have one instance only of intel_runtime_put() at the end of the
function, since one exit branch uses kfree(dev_priv) and the other
doesn't. Similar to i915_driver_load()
If this comment refers just to the 'return ret' - this is a legacy issue
not related to this fix. Could be seen in many places (i915_driver_load
again), just check i915_driver_open() where the last 3 lines of code
could be replaced with 'return ret'
return ret;
}
@@ -1221,6 +1224,9 @@ int i915_driver_unload(struct drm_device *dev)
kmem_cache_destroy(dev_priv->vmas);
kmem_cache_destroy(dev_priv->objects);
pci_dev_put(dev_priv->bridge_dev);
+
+ intel_runtime_pm_put(dev_priv);
+
Not sure if we should/can keep the runtime reference until this point.
At worst this could lead into the runtime_pm_put function poking at the
hardware registers after the pci_dev has been released.
Also if we change the hangcheck task to execute depending on the
runtime_pm count, this will surely cause trouble. Added Imre as CC to
comment on this.
I'm not sure either, but again, the same is done in i915_driver_load().
Waiting for Imre's feedback on this.
kfree(dev_priv);
return 0;
Insert goto label around here and make it "return ret;".
Regards, Joonas
___
Re: [Intel-gfx] [PATCH] drm/i915: Hold a RPM reference during i915_driver_unload
On to, 2015-12-31 at 12:44 +0200, Gabriel Feceoru wrote:
>
> On 30.12.2015 15:03, Joonas Lahtinen wrote:
> > Hi
> > > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > > @@ -1136,6 +1136,8 @@ int i915_driver_unload(struct drm_device
> > > *dev)
> > > struct drm_i915_private *dev_priv = dev->dev_private;
> > > int ret;
> > >
> > > + intel_runtime_pm_get(dev_priv);
> > > +
> > > intel_fbdev_fini(dev);
> > >
> > > i915_audio_component_cleanup(dev_priv);
> > > @@ -1143,6 +1145,7 @@ int i915_driver_unload(struct drm_device
> > > *dev)
> > > ret = i915_gem_suspend(dev);
> > > if (ret) {
> > > DRM_ERROR("failed to idle hardware: %d\n",
> > > ret);
> > > + intel_runtime_pm_put(dev_priv);
> >
> > This should be made into goto construct.
> I cannot have one instance only of intel_runtime_put() at the end of
> the
> function, since one exit branch uses kfree(dev_priv) and the other
> doesn't. Similar to i915_driver_load()
> If this comment refers just to the 'return ret' - this is a legacy
> issue
> not related to this fix. Could be seen in many places
> (i915_driver_load
> again), just check i915_driver_open() where the last 3 lines of code
> could be replaced with 'return ret'
In that case a second path is made for erroring out of the function
(see i915_driver_load):
...
return 0;
label1:
...
labelN:
intel_runtime_pm_put(dev_priv)
return ret;
> >
> > > return ret;
> > > }
> > >
> > > @@ -1221,6 +1224,9 @@ int i915_driver_unload(struct drm_device
> > > *dev)
> > > kmem_cache_destroy(dev_priv->vmas);
> > > kmem_cache_destroy(dev_priv->objects);
> > > pci_dev_put(dev_priv->bridge_dev);
> > > +
> > > + intel_runtime_pm_put(dev_priv);
> > > +
> >
> > Not sure if we should/can keep the runtime reference until this
> > point.
> > At worst this could lead into the runtime_pm_put function poking at
> > the
> > hardware registers after the pci_dev has been released.
> >
> > Also if we change the hangcheck task to execute depending on the
> > runtime_pm count, this will surely cause trouble. Added Imre as CC
> > to
> > comment on this.
> I'm not sure either, but again, the same is done in
> i915_driver_load().
Except that i915_driver_load is the function during which autosuspend
is enabled by calling intel_runtime_pm_enable so it's quite a different
animal. But I think that function has it incorrectly too, the return
path for no errors, _put is correct, but the return path for errors,
the _put should really be _put_noidle because the whole RPM thing was
torn down already see below for explanation.
The load/unload sequences are really not in sync (compare the _unload
function to the _load function teardown path for example), and in
addition to that it is not exactly clear (without going through all the
functions one by one) which functions might end up altering the
hardware state and do require the wakeref and which are tearing down
pure software constructs, so I might be off here, but this is what it
looks like to me.
I feel uneasy for the fact we're calling runtime_pm_put after releasing
the PCI device which basically should be the last put and which should
end up suspending the device when there is no device being held
anymore.
Also, in i915_driver_unload function the PM system teardown has already
been performed by intel_power_domains_fini way earlier in the function,
after which I think we can call at most runtime_pm_put_noidle because
essentially the device has been shut down already.
I do not think those error paths have been stressed much.
Regards, Joonas
> Waiting for Imre's feedback on this.
> >
> > > kfree(dev_priv);
> > >
> > > return 0;
> >
> > Insert goto label around here and make it "return ret;".
> >
> > Regards, Joonas
> >
> > >
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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[Intel-gfx] [PATCH] drm/i915: Add RPM references in the *_get_hw_state functions
This gets rid of errors like:
[ 906.286213] [ cut here ]
[ 906.286233] WARNING: CPU: 0 PID: 12252 at
drivers/gpu/drm/i915/intel_drv.h:1457 gen6_read32+0x1ca/0x1e0 [i915]()
[ 906.286234] RPM wakelock ref not held during HW access
[ 906.286235] Modules linked in:
[ 906.286236] snd_hda_intel i915 drm_kms_helper drm msr snd_hda_codec_hdmi
snd_hda_codec_realtek snd_hda_codec_generic snd_hda_codec snd_hwdep
x86_pkg_temp_thermal snd_hda_core i2c_algo_bit ehci_pci syscopyarea sysfillrect
sysimgblt fb_sys_fops ehci_hcd r8169 xhci_pci mii xhci_hcd video [last
unloaded: drm]
[ 906.286246] CPU: 0 PID: 12252 Comm: kms_pipe_crc_ba Tainted: G U W
4.4.0-rc6+ #45
[ 906.286247] Hardware name: Dell Inc. Inspiron 3847/088DT1 , BIOS A06
01/15/2015
[ 906.286248] c022c098 880210dbbae0 813e0e4f
880210dbbb28
[ 906.286250] 880210dbbb18 8105f5f2 8801fff4
00046040
[ 906.286251] 8801fff49170 8801fff49170 8801fff4
880210dbbb78
[ 906.286253] Call Trace:
[ 906.286256] [] dump_stack+0x44/0x55
[ 906.286259] [] warn_slowpath_common+0x82/0xc0
[ 906.286261] [] warn_slowpath_fmt+0x4c/0x50
[ 906.286270] [] ? drm_property_free_blob+0x8c/0xb0 [drm]
[ 906.286280] [] gen6_read32+0x1ca/0x1e0 [i915]
[ 906.286283] [] ? mutex_lock+0x12/0x30
[ 906.286294] [] hsw_ddi_wrpll_get_hw_state+0x40/0x50 [i915]
[ 906.286304] [] intel_atomic_commit+0xd41/0x1740 [i915]
[ 906.286312] [] drm_atomic_commit+0x37/0x60 [drm]
[ 906.286316] [] drm_atomic_helper_set_config+0x76/0xb0
[drm_kms_helper]
[ 906.286323] [] ? drm_modeset_lock_all_ctx+0x9a/0xb0 [drm]
[ 906.286329] [] drm_mode_set_config_internal+0x62/0x100
[drm]
[ 906.286335] [] drm_mode_setcrtc+0x3cd/0x4e0 [drm]
[ 906.286339] [] drm_ioctl+0x152/0x540 [drm]
[ 906.286341] [] ? __wake_up+0x44/0x50
[ 906.286346] [] ? drm_mode_setplane+0x1b0/0x1b0 [drm]
[ 906.286348] [] ? mntput+0x24/0x40
[ 906.286350] [] ? __fput+0x172/0x1e0
[ 906.286352] [] do_vfs_ioctl+0x288/0x460
[ 906.286353] [] ? fput+0xe/0x10
Signed-off-by: Gabriel Feceoru
---
drivers/gpu/drm/i915/intel_ddi.c | 48 ++--
1 file changed, 36 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index e6408e5..4ba9f2c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2014,15 +2014,18 @@ bool intel_ddi_get_hw_state(struct intel_encoder
*encoder,
enum intel_display_power_domain power_domain;
u32 tmp;
int i;
+ bool ret = false;
power_domain = intel_display_port_power_domain(encoder);
if (!intel_display_power_is_enabled(dev_priv, power_domain))
- return false;
+ return ret;
+
+ intel_runtime_pm_get(dev_priv);
tmp = I915_READ(DDI_BUF_CTL(port));
if (!(tmp & DDI_BUF_CTL_ENABLE))
- return false;
+ goto out;
if (port == PORT_A) {
tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
@@ -2040,7 +2043,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
break;
}
- return true;
+ ret = true;
+ goto out;
} else {
for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
@@ -2048,17 +2052,19 @@ bool intel_ddi_get_hw_state(struct intel_encoder
*encoder,
if ((tmp & TRANS_DDI_PORT_MASK)
== TRANS_DDI_SELECT_PORT(port)) {
if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
TRANS_DDI_MODE_SELECT_DP_MST)
- return false;
+ goto out;
*pipe = i;
- return true;
+ ret = true;
+ goto out;
}
}
}
DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
-
- return false;
+out:
+ intel_runtime_pm_put(dev_priv);
+ return ret;
}
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
@@ -2510,7 +2516,10 @@ static bool hsw_ddi_wrpll_get_hw_state(struct
drm_i915_private *dev_priv,
if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
return false;
+ intel_runtime_pm_get(dev_priv);
val = I915_READ(WRPLL_CTL(pll->id));
+ intel_runtime_pm_put(dev_priv);
+
hw_state->wrpll = val;
return val & WRPLL_PLL_ENABLE;
@@ -2525,7 +2534,10 @@ static bool hsw_ddi_spll_get_hw_state(struct
drm_i915_private *dev_priv,
if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
return false;
+ intel_
[Intel-gfx] ✗ failure: Fi.CI.BAT
== Summary == Built on 79686f613b3955a4ed09cee936e7f70ec4e61b67 drm-intel-nightly: 2015y-12m-30d-11h-59m-54s UTC integration manifest Test gem_basic: Subgroup create-close: pass -> DMESG-WARN (skl-i7k-2) Test gem_cpu_reloc: Subgroup basic: pass -> DMESG-FAIL (skl-i7k-2) Test gem_ctx_param_basic: Subgroup basic: pass -> DMESG-WARN (skl-i7k-2) Subgroup invalid-param-set: pass -> DMESG-WARN (skl-i7k-2) Subgroup non-root-set-no-zeromap: pass -> DMESG-WARN (skl-i7k-2) Subgroup root-set-no-zeromap-disabled: pass -> DMESG-WARN (skl-i7k-2) Test gem_mmap: Subgroup basic: pass -> DMESG-WARN (skl-i7k-2) Test gem_mmap_gtt: Subgroup basic-read: pass -> DMESG-WARN (skl-i7k-2) Subgroup basic-write: pass -> DMESG-WARN (skl-i7k-2) Test gem_storedw_loop: Subgroup basic-render: dmesg-warn -> PASS (skl-i5k-2) dmesg-warn -> PASS (skl-i7k-2) Test kms_addfb_basic: Subgroup addfb25-modifier-no-flag: pass -> DMESG-WARN (skl-i7k-2) Subgroup addfb25-x-tiled-mismatch: pass -> DMESG-WARN (skl-i7k-2) Subgroup bad-pitch-1024: pass -> DMESG-WARN (skl-i7k-2) Subgroup bad-pitch-63: pass -> DMESG-WARN (skl-i7k-2) Subgroup bad-pitch-999: pass -> DMESG-WARN (skl-i7k-2) Subgroup clobberred-modifier: pass -> DMESG-WARN (skl-i7k-2) Subgroup too-high: pass -> DMESG-WARN (skl-i7k-2) Subgroup too-wide: pass -> DMESG-WARN (skl-i7k-2) Subgroup unused-offsets: pass -> DMESG-WARN (skl-i7k-2) Test kms_flip: Subgroup basic-flip-vs-dpms: pass -> DMESG-WARN (skl-i5k-2) pass -> DMESG-WARN (skl-i7k-2) dmesg-warn -> PASS (ilk-hp8440p) Subgroup basic-flip-vs-modeset: dmesg-warn -> PASS (bsw-nuc-2) dmesg-warn -> PASS (hsw-brixbox) dmesg-warn -> PASS (bdw-nuci7) dmesg-warn -> PASS (ilk-hp8440p) Subgroup basic-plain-flip: pass -> DMESG-WARN (skl-i5k-2) pass -> DMESG-WARN (snb-x220t) pass -> DMESG-WARN (bdw-ultra) pass -> DMESG-FAIL (skl-i7k-2) Test kms_force_connector_basic: Subgroup force-connector-state: pass -> SKIP (snb-x220t) Test kms_pipe_crc_basic: Subgroup hang-read-crc-pipe-a: pass -> DMESG-WARN (skl-i5k-2) pass -> DMESG-WARN (skl-i7k-2) Subgroup hang-read-crc-pipe-b: pass -> DMESG-WARN (skl-i5k-2) pass -> DMESG-WARN (skl-i7k-2) Subgroup hang-read-crc-pipe-c: pass -> DMESG-WARN (skl-i5k-2) pass -> DMESG-WARN (skl-i7k-2) Subgroup read-crc-pipe-a: pass -> DMESG-WARN (skl-i5k-2) dmesg-warn -> PASS (snb-x220t) pass -> DMESG-WARN (skl-i7k-2) dmesg-warn -> PASS (byt-nuc) Subgroup read-crc-pipe-a-frame-sequence: pass -> DMESG-WARN (skl-i5k-2) pass -> DMESG-WARN (skl-i7k-2) Subgroup read-crc-pipe-b: pass -> DMESG-WARN (skl-i5k-2) pass -> DMESG-WARN (snb-dellxps) pass -> DMESG-WARN (skl-i7k-2) Subgroup read-crc-pipe-b-frame-sequence: pass -> DMESG-WARN (skl-i5k-2) pass -> DMESG-FAIL (skl-i7k-2) Subgroup read-crc-pipe-c: pass -> DMESG-WARN (skl-i5k-2) pass -> DMESG-WARN (skl-i7k-2) Subgroup read-crc-pipe-c-frame-sequence: pass -> DMESG-WARN (skl-i5k-2) pass -> DMESG-WARN (skl-i7k-2) Subgroup suspend-read-crc-pipe-a: pass -> DMESG-WARN (skl-i5k-2) pass -> DMESG-WARN (skl-i7k-2) Subgroup suspend-read-crc-pipe-c: pass -> DMESG-WARN (skl-i5k-2) pass -> DMESG-WARN (skl-i7k-2) Test kms_psr_sink_crc: Subgroup psr_basic: dmesg-warn -> PASS (bdw-ultra) Test kms_setmode: Subgroup basic-clone-single-crtc: dmesg-warn -> PASS (snb-dellxps) Test pm_rpm: Subgroup basic-pci-d3-state: pass -> DMESG-WARN (skl-i5k-2) pass -> DMESG-WARN (skl-i7k-2) Subgroup bas
[Intel-gfx] [PATCH v2] drm/i915: Add RPM references in the *_get_hw_state functions
This gets rid of errors like:
[ 906.286213] [ cut here ]
[ 906.286233] WARNING: CPU: 0 PID: 12252 at
drivers/gpu/drm/i915/intel_drv.h:1457 gen6_read32+0x1ca/0x1e0 [i915]()
[ 906.286234] RPM wakelock ref not held during HW access
[ 906.286235] Modules linked in:
[ 906.286236] snd_hda_intel i915 drm_kms_helper drm msr snd_hda_codec_hdmi
snd_hda_codec_realtek snd_hda_codec_generic snd_hda_codec snd_hwdep
x86_pkg_temp_thermal snd_hda_core i2c_algo_bit ehci_pci syscopyarea sysfillrect
sysimgblt fb_sys_fops ehci_hcd r8169 xhci_pci mii xhci_hcd video [last
unloaded: drm]
[ 906.286246] CPU: 0 PID: 12252 Comm: kms_pipe_crc_ba Tainted: G U W
4.4.0-rc6+ #45
[ 906.286247] Hardware name: Dell Inc. Inspiron 3847/088DT1 , BIOS A06
01/15/2015
[ 906.286248] c022c098 880210dbbae0 813e0e4f
880210dbbb28
[ 906.286250] 880210dbbb18 8105f5f2 8801fff4
00046040
[ 906.286251] 8801fff49170 8801fff49170 8801fff4
880210dbbb78
[ 906.286253] Call Trace:
[ 906.286256] [] dump_stack+0x44/0x55
[ 906.286259] [] warn_slowpath_common+0x82/0xc0
[ 906.286261] [] warn_slowpath_fmt+0x4c/0x50
[ 906.286270] [] ? drm_property_free_blob+0x8c/0xb0 [drm]
[ 906.286280] [] gen6_read32+0x1ca/0x1e0 [i915]
[ 906.286283] [] ? mutex_lock+0x12/0x30
[ 906.286294] [] hsw_ddi_wrpll_get_hw_state+0x40/0x50 [i915]
[ 906.286304] [] intel_atomic_commit+0xd41/0x1740 [i915]
[ 906.286312] [] drm_atomic_commit+0x37/0x60 [drm]
[ 906.286316] [] drm_atomic_helper_set_config+0x76/0xb0
[drm_kms_helper]
[ 906.286323] [] ? drm_modeset_lock_all_ctx+0x9a/0xb0 [drm]
[ 906.286329] [] drm_mode_set_config_internal+0x62/0x100
[drm]
[ 906.286335] [] drm_mode_setcrtc+0x3cd/0x4e0 [drm]
[ 906.286339] [] drm_ioctl+0x152/0x540 [drm]
[ 906.286341] [] ? __wake_up+0x44/0x50
[ 906.286346] [] ? drm_mode_setplane+0x1b0/0x1b0 [drm]
[ 906.286348] [] ? mntput+0x24/0x40
[ 906.286350] [] ? __fput+0x172/0x1e0
[ 906.286352] [] do_vfs_ioctl+0x288/0x460
[ 906.286353] [] ? fput+0xe/0x10
v2:
Fixed return value in skl_ddi_pll_get_hw_state
Signed-off-by: Gabriel Feceoru
---
drivers/gpu/drm/i915/intel_ddi.c | 50 +---
1 file changed, 37 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index e6408e5..e92ed7a 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2014,15 +2014,18 @@ bool intel_ddi_get_hw_state(struct intel_encoder
*encoder,
enum intel_display_power_domain power_domain;
u32 tmp;
int i;
+ bool ret = false;
power_domain = intel_display_port_power_domain(encoder);
if (!intel_display_power_is_enabled(dev_priv, power_domain))
- return false;
+ return ret;
+
+ intel_runtime_pm_get(dev_priv);
tmp = I915_READ(DDI_BUF_CTL(port));
if (!(tmp & DDI_BUF_CTL_ENABLE))
- return false;
+ goto out;
if (port == PORT_A) {
tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
@@ -2040,7 +2043,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
break;
}
- return true;
+ ret = true;
+ goto out;
} else {
for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
@@ -2048,17 +2052,19 @@ bool intel_ddi_get_hw_state(struct intel_encoder
*encoder,
if ((tmp & TRANS_DDI_PORT_MASK)
== TRANS_DDI_SELECT_PORT(port)) {
if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
TRANS_DDI_MODE_SELECT_DP_MST)
- return false;
+ goto out;
*pipe = i;
- return true;
+ ret = true;
+ goto out;
}
}
}
DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
-
- return false;
+out:
+ intel_runtime_pm_put(dev_priv);
+ return ret;
}
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
@@ -2510,7 +2516,10 @@ static bool hsw_ddi_wrpll_get_hw_state(struct
drm_i915_private *dev_priv,
if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
return false;
+ intel_runtime_pm_get(dev_priv);
val = I915_READ(WRPLL_CTL(pll->id));
+ intel_runtime_pm_put(dev_priv);
+
hw_state->wrpll = val;
return val & WRPLL_PLL_ENABLE;
@@ -2525,7 +2534,10 @@ static bool hsw_ddi_spll_get_hw_state(struct
drm_i915_private *dev_priv,
if (!intel_display_power_is_enabled(dev_priv, POWER_DOMA
[Intel-gfx] ✗ warning: Fi.CI.BAT
== Summary == Built on 79686f613b3955a4ed09cee936e7f70ec4e61b67 drm-intel-nightly: 2015y-12m-30d-11h-59m-54s UTC integration manifest Test kms_flip: Subgroup basic-flip-vs-dpms: dmesg-warn -> PASS (ilk-hp8440p) Subgroup basic-flip-vs-modeset: dmesg-warn -> PASS (bsw-nuc-2) dmesg-warn -> PASS (bdw-nuci7) dmesg-warn -> PASS (ilk-hp8440p) Test kms_pipe_crc_basic: Subgroup read-crc-pipe-a: dmesg-warn -> PASS (snb-x220t) dmesg-warn -> PASS (byt-nuc) Subgroup read-crc-pipe-b: pass -> DMESG-WARN (skl-i5k-2) pass -> DMESG-WARN (snb-dellxps) Subgroup suspend-read-crc-pipe-a: pass -> DMESG-WARN (snb-x220t) Test kms_setmode: Subgroup basic-clone-single-crtc: dmesg-warn -> PASS (snb-dellxps) bdw-nuci7total:132 pass:122 dwarn:1 dfail:0 fail:0 skip:9 bdw-ultratotal:132 pass:124 dwarn:2 dfail:0 fail:0 skip:6 bsw-nuc-2total:135 pass:114 dwarn:1 dfail:0 fail:0 skip:20 byt-nuc total:135 pass:120 dwarn:2 dfail:0 fail:0 skip:13 hsw-brixbox total:135 pass:126 dwarn:2 dfail:0 fail:0 skip:7 hsw-gt2 total:135 pass:130 dwarn:1 dfail:0 fail:0 skip:4 ilk-hp8440p total:135 pass:100 dwarn:0 dfail:0 fail:0 skip:35 ivb-t430stotal:135 pass:127 dwarn:2 dfail:0 fail:0 skip:6 skl-i5k-2total:135 pass:122 dwarn:5 dfail:0 fail:0 skip:8 skl-i7k-2total:135 pass:124 dwarn:3 dfail:0 fail:0 skip:8 snb-dellxps total:135 pass:121 dwarn:2 dfail:0 fail:0 skip:12 snb-x220ttotal:135 pass:121 dwarn:2 dfail:0 fail:1 skip:11 Results at /archive/results/CI_IGT_test/Patchwork_987/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/bxt: Fix eDP panel power save/restore
On Thu, Dec 31, 2015 at 08:31:45AM +0530, Kannan, Vandana wrote:
> When I submitted the PPS patch in April, I got an input from Jani to
> not make changes in i915_suspend.c as it was to become obsolete.
> Below mail for your reference.
>
> Jani,
> Does your initial comment still hold good?
I don't think not touching i915_suspend.c at all is an option since that
means that the current code will try to read/write registers that simply
don't exist on the platform. Based on Jani's comment, maybe we should
just be adding BXT to the list of platforms we don't do any PP
save/restore on?
diff --git a/drivers/gpu/drm/i915/i915_suspend.c
b/drivers/gpu/drm/i915/i915_suspend.c
index 61bec8e..69d5965 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -60,7 +60,7 @@ static void i915_save_display(struct drm_device *dev)
dev_priv->regfile.savePP_ON_DELAYS =
I915_READ(PCH_PP_ON_DELAYS);
dev_priv->regfile.savePP_OFF_DELAYS =
I915_READ(PCH_PP_OFF_DELAYS);
dev_priv->regfile.savePP_DIVISOR =
I915_READ(PCH_PP_DIVISOR);
- } else if (!IS_VALLEYVIEW(dev)) {
+ } else if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
dev_priv->regfile.savePP_CONTROL =
I915_READ(PP_CONTROL);
dev_priv->regfile.savePP_ON_DELAYS =
I915_READ(PP_ON_DELAYS);
dev_priv->regfile.savePP_OFF_DELAYS =
I915_READ(PP_OFF_DELAYS);
I'm not really familiar with the panel power sequencing stuff, so I'll let you
and Jani make the call there. I'm just looking at S3 on Broxton (which has all
kinds of problems right now), and figured I'd try to clear up a couple of the
unclaimed register warnings to make it more clear where the real S3 problems
lie.
Thanks.
Matt
>
> On Thu, 30 Apr 2015, Vandana Kannan wrote:
> > Changes based on future platform readiness patches related to
> > HAS_PCH_SPLIT(). Use HAS_GMCH_DISPLAY() instead of HAS_PCH_SPLIT
> >
> > Signed-off-by: Vandana Kannan
> > Signed-off-by: A.Sunil Kamath
> > ---
> > drivers/gpu/drm/i915/i915_suspend.c | 4 ++--
> > drivers/gpu/drm/i915/intel_dp.c | 8
> > 2 files changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_suspend.c
> > b/drivers/gpu/drm/i915/i915_suspend.c
> > index cf67f82..e91d637 100644
> > --- a/drivers/gpu/drm/i915/i915_suspend.c
> > +++ b/drivers/gpu/drm/i915/i915_suspend.c
> > @@ -44,7 +44,7 @@ static void i915_save_display(struct drm_device *dev)
> > dev_priv->regfile.saveLVDS = I915_READ(LVDS);
> >
> > /* Panel power sequencer */
> > - if (HAS_PCH_SPLIT(dev)) {
> > + if (!HAS_GMCH_DISPLAY(dev)) {
> > dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
> > dev_priv->regfile.savePP_ON_DELAYS =
> > I915_READ(PCH_PP_ON_DELAYS);
> > dev_priv->regfile.savePP_OFF_DELAYS =
> > I915_READ(PCH_PP_OFF_DELAYS);
> > @@ -79,7 +79,7 @@ static void i915_restore_display(struct
> drm_device *dev)
> > I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
> >
> > /* Panel power sequencer */
> > - if (HAS_PCH_SPLIT(dev)) {
> > + if (!HAS_GMCH_DISPLAY(dev)) {
> > I915_WRITE(PCH_PP_ON_DELAYS,
> > dev_priv->regfile.savePP_ON_DELAYS);
> > I915_WRITE(PCH_PP_OFF_DELAYS,
> > dev_priv->regfile.savePP_OFF_DELAYS);
> > I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
>
> I don't think you should touch i915_suspend.c at all. We're trying
> to get rid of this blind register save/restore, and make everything
> work in the encoder/connector code. Do note that we already skip
> this for vlv/chv power sequencer registers.
>
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c index 937ba31..68e10c1 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -559,7 +559,7 @@ static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
> > {
> > struct drm_device *dev = intel_dp_to_dev(intel_dp);
> >
> > - if (HAS_PCH_SPLIT(dev))
> > + if (!HAS_GMCH_DISPLAY(dev))
> > return PCH_PP_CONTROL;
> > else
> > return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
> > @@ -569,7 +569,7 @@ static u32 _pp_stat_reg(struct intel_dp *intel_dp)
> > {
> > struct drm_device *dev = intel_dp_to_dev(intel_dp);
> >
> > - if (HAS_PCH_SPLIT(dev))
> > + if (!HAS_GMCH_DISPLAY(dev))
> > return PCH_PP_STATUS;
> > else
> > return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
> > @@ -4963,7 +4963,7 @@ intel_dp_init_panel_power_sequencer(struct
> drm_device *dev,
> > if (final->t11_t12 != 0)
> > return;
> >
> > - if (HAS_PCH_SPLIT(dev)) {
> > + if (!HAS_GMCH_DISPLAY(dev)) {
> > pp_ctrl_reg = PCH_PP_CONTROL;
> > pp_on_re
Re: [Intel-gfx] Why idle_freq is set to RPn and not RPe
On 12/30/2015 4:20 PM, Chris Wilson wrote: On Wed, Dec 30, 2015 at 04:09:46PM +0530, Kamble, Sagar A wrote: Turbo frequency range is Rpe to Rp0 when GPU is active as, on workload submission frequency is taken to Rpe. Does the HW require us to drop to RPn before entering RC6? If we can enter RC6 even with other frequencies I think we can keep running at Rpe on Idle. Remember that we quite frequently prevent the hardware going into RC6, I assume this is threshold times in TO/EI mode for which GT is idle but not power gated. and that it has been known for the hardware to fail to enter RC6 itself (through driver error or whatnot). And assume this is because of forcewake/rc6 setup errors in driver paths which should not happen in best case :) Agree that running at Rpn makes sense. Going to the extreme, why wouldn't you set Rp0 on idle, since that will give the best restart latency? True. We can have different logic that starts from Rp0 and comes down if perf is met. -Chris Thanks for the inputs Chris. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
