Re: [Intel-gfx] [Contact] git website is irresponsive
I was following your doumention on this URL "https://01.org/linuxgraphics/documentation/build-guide-0";. THE GIT WEBSITE is not responding # git clone git://anongit.freedesktop.org/mesa/drm Cloning into 'drm'... fatal: unable to connect to anongit.freedesktop.org: anongit.freedesktop.org[0: 131.252.210.161]: errno=Connection timed o From: "Chacn Limn, DanielX" To: "olawal...@yahoo.ca" Cc: "Becerra Ruiz, Lilia" ; "Flores Perez, Jimena" ; "Diaz, Victor H" Sent: Friday, August 14, 2015 5:00 PM Subject: RE: [Contact] git website is irresponsive Hello Olawale, Thank you for contacting us. You can contact the Linux Graphics team using their mailing list: intel-gfx@lists.freedesktop.org They might help you with your issue. Please let us know if you have additional questions. Regards, Daniel. -Original Message- From: webmas...@01.org [mailto:webmas...@01.org] On Behalf Of olawal...@yahoo.ca Sent: Thursday, August 13, 2015 10:57 AM To: Becerra Ruiz, Lilia; Flores Perez, Jimena; Chacn Limn, DanielX; Diaz, Victor H Subject: [Contact] git website is irresponsive olawale sanyaolu (olawal...@yahoo.ca) sent a message using the contact form at https://01.org/about/contact-us. I was following your doumention on this URL "https://01.org/linuxgraphics/documentation/build-guide-0";. THE GIT WEBSITE is not responding # git clone git://anongit.freedesktop.org/mesa/drm Cloning into 'drm'... fatal: unable to connect to anongit.freedesktop.org: anongit.freedesktop.org[0: 131.252.210.161]: errno=Connection timed out Report as inappropriate: https://01.org/mollom/report/mollom_captcha/15081370e138f20b56 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Flag the execlists context object as dirty after every use
On Fri, 14 Aug 2015, Daniel Vetter wrote: > On Fri, Aug 14, 2015 at 12:59:19PM +0100, Chris Wilson wrote: >> Everytime we use the logical context with execlists it becomes dirty (as >> the hardware will write the new register values afterwards, as well as >> the GPU state that will be used). We need to then flag the context as >> dirty everytime since after a swap-out/swap-in cycle the dirty flag will >> be cleared, and a further swap-out cycle will then loose the most recent >> GPU state. >> >> Signed-off-by: Chris Wilson >> Cc: sta...@vger.kernel.org > > Yay for reinventing active tracking I guess, legacy hw ctx has this > already. Reviewed-by: Daniel Vetter Pushed to drm-intel-fixes, thanks for the patch and review. BR, Jani. > -Daniel >> --- >> drivers/gpu/drm/i915/intel_lrc.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/intel_lrc.c >> b/drivers/gpu/drm/i915/intel_lrc.c >> index 138964afd187..41cfa6fa909d 100644 >> --- a/drivers/gpu/drm/i915/intel_lrc.c >> +++ b/drivers/gpu/drm/i915/intel_lrc.c >> @@ -1013,6 +1013,8 @@ static int intel_lr_context_pin(struct >> drm_i915_gem_request *rq) >> ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf); >> if (ret) >> goto unpin_ctx_obj; >> + >> +ctx_obj->dirty = true; >> } >> >> return ret; >> -- >> 2.5.0 >> >> ___ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 18/18] gitignore: ignore more files
On Fri, 14 Aug 2015, Jesse Barnes wrote: > On 08/14/2015 09:07 AM, Daniel Vetter wrote: >> On Fri, Aug 14, 2015 at 08:20:22AM -0700, Jesse Barnes wrote: >>> git clean updates the .gitignore file? Not having to run git clean is the >>> whole point of this patch... >> >> I looked at this patch first, but later noticed that you have a few >> renames where you don't update the .gitignore. >>> >>> On 08/14/2015 01:09 AM, Daniel Vetter wrote: On Thu, Aug 13, 2015 at 01:31:41PM -0700, Jesse Barnes wrote: git clean fixes this all, at least over here git status is clean. -Daniel > --- > .gitignore | 3 +++ > tests/.gitignore | 13 + > tools/.gitignore | 8 > 3 files changed, 24 insertions(+) > > diff --git a/.gitignore b/.gitignore > index a438c1c..533f6f1 100644 > --- a/.gitignore > +++ b/.gitignore > @@ -90,3 +90,6 @@ gtk-doc.m4 > > piglit > results > + > +*.orig > +version.h > diff --git a/tests/.gitignore b/tests/.gitignore > index 31d35a5..e45cbb7 100644 > --- a/tests/.gitignore > +++ b/tests/.gitignore > @@ -99,6 +99,7 @@ gem_set_tiling_vs_blt > gem_set_tiling_vs_gtt > gem_set_tiling_vs_pwrite > gem_storedw_batches_loop > +gem_storedw_loop > gem_storedw_loop_blt > gem_storedw_loop_bsd > gem_storedw_loop_render > @@ -169,3 +170,15 @@ prime_udl > template > test-list.txt > testdisplay > +ddi_compute_wrpll > +gem_vmap_blits > +gem_wait_render_timeout > +igt_fork_helper > +igt_list_only > +igt_no_exit > +igt_no_exit_list_only > +igt_no_subtest > +igt_simulation >> >> But all the igt_* have moved to lib/tests/ so you definitely have a pile >> of old build system gunk that needs to be cleaned out first with git >> clean. >> > +pm_pc8 > +pm_psr > + > diff --git a/tools/.gitignore b/tools/.gitignore > index 49bd24f..7bf91e3 100644 > --- a/tools/.gitignore > +++ b/tools/.gitignore > @@ -37,3 +37,11 @@ intel_vga_write > intel_watermark > skl_compute_wrpll > skl_ddb_allocation > +forcewaked > +intel_dpio_read > +intel_dpio_write > +intel_gpu_dump > +intel_nc_read > +intel_nc_write > +intel_punit_read > +intel_punit_write >> >> Same with those, Jani killed them all iirc. > > ah ok, I can drop those. I'll clean and such and just add the minimal > set here. Ooops, I had sent the patch to the list, but never pushed. Done now. BR, Jani. > > Jesse > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/6 v3] drm/i915/skl: enable DDI-E hotplug
v2: fix one error found by checkpath.pl
v3: Add one ignored break for switch-case. DDI-E hotplug
function doesn't work after updating drm-intel tree,
I checked the code and found this missing which isn't
the root cause for broke DDI-E hp. The broken
DDI-E hp function is fixed by "Adding DDI_E power
well domain".
Signed-off-by: Xiong Zhang
Reviewed-by: Rodrigo Vivi
Tested-by: Timo Aaltonen
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 48 +---
drivers/gpu/drm/i915/i915_reg.h | 12 +
drivers/gpu/drm/i915/intel_display.c | 3 +++
drivers/gpu/drm/i915/intel_dp.c | 3 +++
drivers/gpu/drm/i915/intel_hotplug.c | 3 +++
6 files changed, 66 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e0f3f05..5f6fd0b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -215,6 +215,7 @@ enum hpd_pin {
HPD_PORT_B,
HPD_PORT_C,
HPD_PORT_D,
+ HPD_PORT_E,
HPD_NUM_PINS
};
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a051045..8485bea 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -61,6 +61,13 @@ static const u32 hpd_cpt[HPD_NUM_PINS] = {
[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
};
+static const u32 hpd_spt[HPD_NUM_PINS] = {
+ [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
+ [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
+ [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
+ [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
+};
+
static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
[HPD_CRT] = CRT_HOTPLUG_INT_EN,
[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
@@ -1253,6 +1260,8 @@ static bool pch_port_hotplug_long_detect(enum port port,
u32 val)
return val & PORTC_HOTPLUG_LONG_DETECT;
case PORT_D:
return val & PORTD_HOTPLUG_LONG_DETECT;
+ case PORT_E:
+ return val & PORTE_HOTPLUG_LONG_DETECT;
default:
return false;
}
@@ -1753,7 +1762,12 @@ static void cpt_irq_handler(struct drm_device *dev, u32
pch_iir)
{
struct drm_i915_private *dev_priv = dev->dev_private;
int pipe;
- u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
+ u32 hotplug_trigger;
+
+ if (HAS_PCH_SPT(dev))
+ hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT;
+ else
+ hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
if (hotplug_trigger) {
u32 dig_hotplug_reg, pin_mask, long_mask;
@@ -1761,9 +1775,23 @@ static void cpt_irq_handler(struct drm_device *dev, u32
pch_iir)
dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
- intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
- dig_hotplug_reg, hpd_cpt,
- pch_port_hotplug_long_detect);
+ if (HAS_PCH_SPT(dev)) {
+ intel_get_hpd_pins(&pin_mask, &long_mask,
+ hotplug_trigger,
+ dig_hotplug_reg, hpd_spt,
+ pch_port_hotplug_long_detect);
+
+ /* detect PORTE HP event */
+ dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
+ if (pch_port_hotplug_long_detect(PORT_E,
+dig_hotplug_reg))
+ long_mask |= 1 << HPD_PORT_E;
+ } else
+ intel_get_hpd_pins(&pin_mask, &long_mask,
+ hotplug_trigger,
+ dig_hotplug_reg, hpd_cpt,
+ pch_port_hotplug_long_detect);
+
intel_hpd_irq_handler(dev, pin_mask, long_mask);
}
@@ -2985,6 +3013,11 @@ static void ibx_hpd_irq_setup(struct drm_device *dev)
for_each_intel_encoder(dev, intel_encoder)
if
(dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED)
enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
+ } else if (HAS_PCH_SPT(dev)) {
+ hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
+ for_each_intel_encoder(dev, intel_encoder)
+ if
(dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED)
+ enabled_irqs |= hpd_spt[intel_encoder->hpd_pin];
} else {
hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
for_each_intel_encoder(dev, intel_encoder)
@@ -3006,6 +3039,13 @@ static void ibx_hpd_irq_setup(struct drm_device *dev)
hotplug |= PORTC_HOTPLUG_ENABLE | PORTC
[Intel-gfx] [PATCH 6/6 v3] drm/i915: Enable HDMI on DDI-E
DDI-E doesn't have the correspondent GMBUS pin.
We rely on VBT to tell us which one it being used instead.
The DVI/HDMI on shared port couldn't exist.
This patch isn't tested without hardware wchich has HDMI
on DDI-E.
v2: fix trailing whitespace
v3: MISSING_CASE take place of BUG()
Signed-off-by: Xiong Zhang
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/intel_bios.c | 25 +
drivers/gpu/drm/i915/intel_hdmi.c | 21 +
3 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 35192d2..22e8bf0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1418,6 +1418,10 @@ enum modeset_restore {
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30
+#define DDC_PIN_B 0x05
+#define DDC_PIN_C 0x04
+#define DDC_PIN_D 0x06
+
struct ddi_vbt_port_info {
/*
* This is an index in the HDMI/DVI DDI buffer translation table.
@@ -1432,6 +1436,7 @@ struct ddi_vbt_port_info {
uint8_t supports_dp:1;
uint8_t alternate_aux_channel;
+ uint8_t alternate_ddc_pin;
uint8_t dp_boost_level;
uint8_t hdmi_boost_level;
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 8e46149..a2ee347 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -905,7 +905,7 @@ static void parse_ddi_port(struct drm_i915_private
*dev_priv, enum port port,
uint8_t hdmi_level_shift;
int i, j;
bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
- uint8_t aux_channel;
+ uint8_t aux_channel, ddc_pin;
/* Each DDI port can have more than one value on the "DVO Port" field,
* so look for all the possible values for each port and abort if more
* than one is found. */
@@ -939,6 +939,7 @@ static void parse_ddi_port(struct drm_i915_private
*dev_priv, enum port port,
return;
aux_channel = child->raw[25];
+ ddc_pin = child->common.ddc_pin;
is_dvi = child->common.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING;
is_dp = child->common.device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT;
@@ -970,11 +971,27 @@ static void parse_ddi_port(struct drm_i915_private
*dev_priv, enum port port,
DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port));
if (is_dvi) {
- if (child->common.ddc_pin == 0x05 && port != PORT_B)
+ if (port == PORT_E) {
+ info->alternate_ddc_pin = ddc_pin;
+ /* if DDIE share ddc pin with other port, then
+* dvi/hdmi couldn't exist on the shared port.
+* Otherwise they share the same ddc bin and system
+* couldn't communicate with them seperately. */
+ if (ddc_pin == DDC_PIN_B) {
+
dev_priv->vbt.ddi_port_info[PORT_B].supports_dvi = 0;
+
dev_priv->vbt.ddi_port_info[PORT_B].supports_hdmi = 0;
+ } else if (ddc_pin == DDC_PIN_C) {
+
dev_priv->vbt.ddi_port_info[PORT_C].supports_dvi = 0;
+
dev_priv->vbt.ddi_port_info[PORT_C].supports_hdmi = 0;
+ } else if (ddc_pin == DDC_PIN_D) {
+
dev_priv->vbt.ddi_port_info[PORT_D].supports_dvi = 0;
+
dev_priv->vbt.ddi_port_info[PORT_D].supports_hdmi = 0;
+ }
+ } else if (ddc_pin == DDC_PIN_B && port != PORT_B)
DRM_DEBUG_KMS("Unexpected DDC pin for port B\n");
- if (child->common.ddc_pin == 0x04 && port != PORT_C)
+ else if (ddc_pin == DDC_PIN_C && port != PORT_C)
DRM_DEBUG_KMS("Unexpected DDC pin for port C\n");
- if (child->common.ddc_pin == 0x06 && port != PORT_D)
+ else if (ddc_pin == DDC_PIN_D && port != PORT_D)
DRM_DEBUG_KMS("Unexpected DDC pin for port D\n");
}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 7185062..d1a7f7b 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1956,6 +1956,7 @@ void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port,
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
enum port port = intel_dig_port->port;
+ uint8_t alternate_ddc_pin;
drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
DRM_MODE_CONNECTOR_HDMIA);
@@ -1996,6 +1997,26 @@ void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port,
intel_hdmi->ddc_bus = GMBUS
Re: [Intel-gfx] [PATCH 0/7] drm/i915: Move DP link parameters out from intel_dp
Hey,
Op 06-07-15 om 14:09 schreef ville.syrj...@linux.intel.com:
> From: Ville Syrjälä
>
> While working on CHV DPIO powergating I relized DP .compute_config() was
> clobbering lane_count etc. stored in intel_dp. This could cause problems
> if we do the .compute_config() but later fail the modeset for some reason.
> Any subsequent link re-training might then fail if intel_dp->lane_count
> etc. got changed.
>
> The reason I ran into this during the DPIO powergating work was that I may
> need to know which lanes he active when shutting down the link. However
> .compute_config() already clobbered that information by the time I need it.
> By moving it to the pipe config we avoid that problem as well.
>
> I also cleaned up the limited color range handling a bit while I was
> in the neighborhood.
>
> Ville Syrjälä (7):
> drm/i915: Clean up DP/HDMI limited color range handling
> drm/i915: Don't use link_bw for PLL setup
^
> drm/i915: Don't pass clock to DDI PLL select functions
> drm/i915: Avoid confusion between DP and TRANS_DP_CTL in DP
> .get_config()
> drm/i915: Move intel_dp->lane_count into pipe_config
^Your patch series breaks MST entirely.
drm_encoder->crtc will be NULL and dereferencing crtc->config will fail on the
primary encoder:
intel_mst_pre_enable_dp(mst_enc) ->
intel_ddi_init_dp_buf_reg(mst_enc->primary). -> primary->crtc = NULL, OOPS.
Voltage training was failing too and I was getting a MCE until I reverted the
crtc->config changes from this series..
> drm/i915: Don't use link_bw to select between TP1 and TP3
> drm/i915: Kill intel_dp->{link_bw,rate_select}
>
> drivers/gpu/drm/i915/i915_reg.h | 3 +
> drivers/gpu/drm/i915/intel_ddi.c | 41
> drivers/gpu/drm/i915/intel_display.c | 7 +-
> drivers/gpu/drm/i915/intel_dp.c | 177
> ---
> drivers/gpu/drm/i915/intel_dp_mst.c | 19 ++--
> drivers/gpu/drm/i915/intel_drv.h | 9 +-
> drivers/gpu/drm/i915/intel_hdmi.c| 26 +++--
> 7 files changed, 155 insertions(+), 127 deletions(-)
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] drm/i915: Fix module initialisation.
Set DRIVER_MODESET and DRIVER_ATOMIC by default. The driver is fully atomic.
Remove the legacy suspend/resume, to fix a warning introduced by:
"drm: WARN_ON if a modeset driver uses legacy suspend/resume helpers"
and removing the .get_vblank_timestamp reset to NULL. It's a noop without UMS.
Signed-off-by: Maarten Lankhorst
---
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1d887459e37f..411ba8ccecca 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1646,7 +1646,7 @@ static struct drm_driver driver = {
*/
.driver_features =
DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
- DRIVER_RENDER,
+ DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC,
.load = i915_driver_load,
.unload = i915_driver_unload,
.open = i915_driver_open,
@@ -1655,10 +1655,6 @@ static struct drm_driver driver = {
.postclose = i915_driver_postclose,
.set_busid = drm_pci_set_busid,
- /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
- .suspend = i915_suspend_legacy,
- .resume = i915_resume_legacy,
-
#if defined(CONFIG_DEBUG_FS)
.debugfs_init = i915_debugfs_init,
.debugfs_cleanup = i915_debugfs_cleanup,
@@ -1701,7 +1697,6 @@ static int __init i915_init(void)
* either the i915.modeset prarameter or by the
* vga_text_mode_force boot option.
*/
- driver.driver_features |= DRIVER_MODESET;
if (i915.modeset == 0)
driver.driver_features &= ~DRIVER_MODESET;
@@ -1712,20 +1707,11 @@ static int __init i915_init(void)
#endif
if (!(driver.driver_features & DRIVER_MODESET)) {
- driver.get_vblank_timestamp = NULL;
/* Silently fail loading to not upset userspace. */
DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
return 0;
}
- /*
-* FIXME: Note that we're lying to the DRM core here so that we can get
access
-* to the atomic ioctl and the atomic properties. Only plane
operations on
-* a single CRTC will actually work.
-*/
- if (driver.driver_features & DRIVER_MODESET)
- driver.driver_features |= DRIVER_ATOMIC;
-
return drm_pci_init(&driver, &i915_pci_driver);
}
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 00/11] Check pixel clock when setting mode
On Fri, 2015-08-14 at 15:13 +0200, Daniel Vetter wrote: > On Fri, Aug 14, 2015 at 01:03:20PM +0300, Mika Kahola wrote: > > From EDID we can read and request higher pixel clock than > > our HW can support. This set of patches add checks if > > requested pixel clock is lower than the one supported by the HW. > > The requested mode is discarded if we cannot support the requested > > pixel clock. For example for Cherryview > > > > 'cvt 2560 1600 60' gives > > > > # 2560x1600 59.99 Hz (CVT 4.10MA) hsync: 99.46 kHz; pclk: 348.50 MHz > > Modeline "2560x1600_60.00" 348.50 2560 2760 3032 3504 1600 1603 1609 > > 1658 -hsync +vsync > > > > where pixel clock 348.50 MHz is higher than the supported 304 MHz. > > > > The checks are implemented for DisplayPort, HDMI, LVDS, DVO, SDVO, DSI, > > CRT, TV, and DP-MST. > > > > V2: > > - The maximum DOT clock frequency is added to debugfs i915_frequency_info. > > - max dotclock cached in dev_priv structure > > - moved computation of max dotclock to 'intel_display.c' > > > > V3: > > - intel_update_max_dotclk() renamed as intel_compute_max_dotclk() > > - for GEN9 and above the max dotclock frequency is equal to CD clock > > frequency > > - for older generations the dot clock frequency is limited to 90% of the > > CD clock frequency > > - For Cherryview the dot clock is limited to 95% of CD clock frequency > > - for GEN2/3 the maximum dot clock frequency is limited to 90% of the > > 2X CD clock frequency as we have on option to use double wide mode > > - cleanup > > > > V4: > > - renaming of max_dotclk as max_dotclk_freq in dev_priv (i915_drv.h) > > caused changes to all patches in my series even though some of them has > > been r-b'd by Ville > > - for consistency the max_pixclk variable is renamed as max_dotclk > > throughout > > the whole series > > One thing that was completely missed here is testcases? Do they exist? > -Daniel Yes, the testcases are still missing. -Mika- > > > > Mika Kahola (11): > > drm/i915: Store max dotclock > > drm/i915: DisplayPort pixel clock check > > drm/i915: HDMI pixel clock check > > drm/i915: LVDS pixel clock check > > drm/i915: SDVO pixel clock check > > drm/i915: DSI pixel clock check > > drm/i915: CRT pixel clock check > > drm/i915: TV pixel clock check > > drm/i915: DisplayPort-MST pixel clock check > > drm/i915: DVO pixel clock check > > drm/i915: Max DOT clock frequency to debugfs > > > > drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ > > drivers/gpu/drm/i915/i915_drv.h | 1 + > > drivers/gpu/drm/i915/intel_crt.c | 4 > > drivers/gpu/drm/i915/intel_display.c | 19 +++ > > drivers/gpu/drm/i915/intel_dp.c | 3 ++- > > drivers/gpu/drm/i915/intel_dp_mst.c | 5 + > > drivers/gpu/drm/i915/intel_dsi.c | 3 +++ > > drivers/gpu/drm/i915/intel_dvo.c | 3 +++ > > drivers/gpu/drm/i915/intel_hdmi.c| 8 > > drivers/gpu/drm/i915/intel_lvds.c| 15 +++ > > drivers/gpu/drm/i915/intel_sdvo.c| 4 > > drivers/gpu/drm/i915/intel_tv.c | 4 > > 12 files changed, 66 insertions(+), 5 deletions(-) > > > > -- > > 1.9.1 > > > > ___ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] drm/i915: Fix module initialisation.
On Mon, Aug 17, 2015 at 12:00:38PM +0200, Maarten Lankhorst wrote: > Set DRIVER_MODESET and DRIVER_ATOMIC by default. The driver is fully atomic. > Remove the legacy suspend/resume, to fix a warning introduced by: > > "drm: WARN_ON if a modeset driver uses legacy suspend/resume helpers" > > and removing the .get_vblank_timestamp reset to NULL. It's a noop without UMS. > > Signed-off-by: Maarten Lankhorst Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [BXT MIPI PATCH v2 02/13] drm/i915/bxt: Enable BXT DSI PLL
On Sun, 26 Jul 2015, Uma Shankar wrote:
> From: Shashank Sharma
>
> This patch adds new functions for BXT clock and PLL programming.
> They are:
> 1. configure_dsi_pll for BXT.
>This function does the basic math and generates the divider ratio
>based on requested pixclock, and program clock registers.
> 2. enable_dsi_pll function.
>This function programs the calculated clock values on the PLL.
> 3. intel_enable_dsi_pll
>Wrapper function to use same code for multiple platforms. It checks the
>platform and calls appropriate core pll enable function.
>
> v2: Fixed Jani's review comments. Macros are adjusted as per convention.
>
> Signed-off-by: Shashank Sharma
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/i915_reg.h | 25 -
> drivers/gpu/drm/i915/intel_dsi.c |2 +-
> drivers/gpu/drm/i915/intel_dsi.h |2 +-
> drivers/gpu/drm/i915/intel_dsi_pll.c | 95
> +-
> 4 files changed, 119 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index de1eea4..0862018 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7443,10 +7443,31 @@ enum skl_disp_power_wells {
> #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME,
> _PIPE_B_CSC_POSTOFF_ME)
> #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO,
> _PIPE_B_CSC_POSTOFF_LO)
>
> -/* MIPI DSI registers */
> -
> #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and
> C only */
>
> +/* MIPI DSI registers */
Why are you moving this comment?
BR,
Jani.
> +#define BXT_DSI_PLL_CTL 0x161000
> +#define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
> +#define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
> +#define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
> +#define BXT_DSIC_16X_BY2(1 << 10)
> +#define BXT_DSIC_16X_BY3(2 << 10)
> +#define BXT_DSIC_16X_BY4(3 << 10)
> +#define BXT_DSIA_16X_BY2(1 << 8)
> +#define BXT_DSIA_16X_BY3(2 << 8)
> +#define BXT_DSIA_16X_BY4(3 << 8)
> +#define BXT_DSI_FREQ_SEL_SHIFT 8
> +#define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT)
> +
> +#define BXT_DSI_PLL_RATIO_MAX0x7D
> +#define BXT_DSI_PLL_RATIO_MIN0x22
> +#define BXT_DSI_PLL_RATIO_MASK 0xFF
> +#define BXT_REF_CLOCK_KHZ19500
> +
> +#define BXT_DSI_PLL_ENABLE 0x46080
> +#define BXT_DSI_PLL_DO_ENABLE (1 << 31)
> +#define BXT_DSI_PLL_LOCKED (1 << 30)
> +
> #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
> #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
> #define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL,
> _MIPIC_PORT_CTRL)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index d709da3..e201c0f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -898,8 +898,8 @@ static void intel_dsi_pre_pll_enable(struct intel_encoder
> *encoder)
> DRM_DEBUG_KMS("\n");
>
> intel_dsi_prepare(encoder);
> + intel_enable_dsi_pll(encoder);
>
> - vlv_enable_dsi_pll(encoder);
> }
>
> static enum drm_connector_status
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h
> b/drivers/gpu/drm/i915/intel_dsi.h
> index 2784ac4..20cfcf07 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -121,7 +121,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct
> drm_encoder *encoder)
> return container_of(encoder, struct intel_dsi, base.base);
> }
>
> -extern void vlv_enable_dsi_pll(struct intel_encoder *encoder);
> +extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
> extern void vlv_disable_dsi_pll(struct intel_encoder *encoder);
> extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
> b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index c6a8975..b07483b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -246,7 +246,7 @@ static void vlv_configure_dsi_pll(struct intel_encoder
> *encoder)
> vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);
> }
>
> -void vlv_enable_dsi_pll(struct intel_encoder *encoder)
> +static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> u32 tmp;
> @@ -363,3 +363,96 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int
> pipe_bpp)
>
> return pclk;
> }
> +
> +static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_
Re: [Intel-gfx] [BXT MIPI PATCH v2 04/13] drm/i915/bxt: DSI prepare changes for BXT
On Sun, 26 Jul 2015, Uma Shankar wrote:
> From: Shashank Sharma
>
> This patch modifies dsi_prepare() function to support the same
> modeset prepare sequence for BXT also. Main changes are:
> 1. BXT port control register is different than VLV.
> 2. BXT modeset sequence needs vdisplay and hdisplay programmed
>for transcoder.
> 3. BXT can select PIPE for MIPI transcoders.
> 4. BXT needs to program register MIPI_INIT_COUNT for both the ports,
>even if only one is being used.
>
> v2: Fixed Jani's review comments. Rectified the DSI Macros to get
> proper register offsets using _MIPI_PORT instead of _TRANSCODER
>
> Signed-off-by: Shashank Sharma
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/i915_reg.h | 21
> drivers/gpu/drm/i915/intel_dsi.c | 67
> --
> 2 files changed, 78 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0862018..8796b25 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7445,6 +7445,22 @@ enum skl_disp_power_wells {
>
> #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and
> C only */
>
> +/* BXT MIPI mode configure */
> +#define _BXT_MIPIA_TRANS_HACTIVE0x6B0F8
> +#define _BXT_MIPIC_TRANS_HACTIVE0x6B8F8
> +#define BXT_MIPI_TRANS_HACTIVE(tc) _MIPI_PORT(tc, \
> + _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
> +
> +#define _BXT_MIPIA_TRANS_VACTIVE0x6B0FC
> +#define _BXT_MIPIC_TRANS_VACTIVE0x6B8FC
> +#define BXT_MIPI_TRANS_VACTIVE(tc) _MIPI_PORT(tc, \
> + _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
> +
> +#define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
> +#define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
> +#define BXT_MIPI_TRANS_VTOTAL(tc) _MIPI_PORT(tc, \
> + _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
> +
> /* MIPI DSI registers */
This should be the topmost comment for DSI.
> #define BXT_DSI_PLL_CTL 0x161000
> #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
> @@ -7881,6 +7897,11 @@ enum skl_disp_power_wells {
> #define READ_REQUEST_PRIORITY_HIGH (3 << 3)
> #define RGB_FLIP_TO_BGR (1 << 2)
>
> +#define BXT_PIPE_SELECT_MASK(7 << 7)
> +#define BXT_PIPE_SELECT_C (2 << 7)
> +#define BXT_PIPE_SELECT_B (1 << 7)
> +#define BXT_PIPE_SELECT_A (0 << 7)
> +
> #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
> #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
> #define MIPI_DATA_ADDRESS(port) _MIPI_PORT(port,
> _MIPIA_DATA_ADDRESS, \
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 544166f..0b20534 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -721,6 +721,21 @@ static void set_dsi_timings(struct drm_encoder *encoder,
> hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
>
> for_each_dsi_port(port, intel_dsi->ports) {
> + if (IS_BROXTON(dev)) {
> + /*
> + * Program hdisplay and vdisplay on MIPI transcoder.
> + * This is different from calculated hactive and
> + * vactive, as they are calculated per channel basis,
> + * whereas these values should be based on resolution.
> + */
> + I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
> + mode->hdisplay);
> + I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
> + mode->vdisplay);
> + I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
> + mode->vtotal);
> + }
> +
> I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
> I915_WRITE(MIPI_HFP_COUNT(port), hfp);
>
> @@ -761,16 +776,35 @@ static void intel_dsi_prepare(struct intel_encoder
> *intel_encoder)
> }
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - /* escape clock divider, 20MHz, shared for A and C.
> - * device ready must be off when doing this! txclkesc? */
> - tmp = I915_READ(MIPI_CTRL(PORT_A));
> - tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
> - I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
> -
> - /* read request priority is per pipe */
> - tmp = I915_READ(MIPI_CTRL(port));
> - tmp &= ~READ_REQUEST_PRIORITY_MASK;
> - I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
> + if (IS_VALLEY
[Intel-gfx] [PATCH v3 4/4] drm/i915: set proper N/CTS in modeset
From: Libin Yang
When modeset occurs and the TMDS frequency is set to some
speical values, the N/CTS need to be set manually if audio
is playing.
Signed-off-by: Libin Yang
---
drivers/gpu/drm/i915/i915_reg.h| 8
drivers/gpu/drm/i915/intel_audio.c | 40 +-
2 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6786e94..122b5bd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7035,6 +7035,8 @@ enum skl_disp_power_wells {
_HSW_AUD_MISC_CTRL_A, \
_HSW_AUD_MISC_CTRL_B)
+#define HSW_AUD_PIPE_CONN_SEL_CTRL 0x650ac
+
#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
#define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
@@ -7049,6 +7051,12 @@ enum skl_disp_power_wells {
_HSW_AUD_DIG_CNVT_2)
#define DIP_PORT_SEL_MASK 0x3
+#define _HSW_AUD_STR_DESC_10x65084
+#define _HSW_AUD_STR_DESC_20x65184
+#define AUD_STR_DESC(pipe) _PIPE(pipe, \
+_HSW_AUD_STR_DESC_1, \
+_HSW_AUD_STR_DESC_2)
+
#define _HSW_AUD_EDID_DATA_A 0x65050
#define _HSW_AUD_EDID_DATA_B 0x65150
#define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index 27add6a..0a54ac0 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -140,6 +140,27 @@ static bool audio_rate_need_prog(struct intel_crtc *crtc,
return false;
}
+static int audio_config_get_rate(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
+{
+ uint32_t tmp;
+ int cvt_idx;
+ int base_rate, mul, div, rate;
+
+ tmp = I915_READ(HSW_AUD_PIPE_CONN_SEL_CTRL);
+ cvt_idx = (tmp >> (pipe * 8)) & 0xff;
+ tmp = I915_READ(AUD_STR_DESC(cvt_idx));
+ base_rate = tmp & (1 << 14);
+ if (base_rate == 0)
+ rate = 48000;
+ else
+ rate = 44100;
+ mul = (tmp & (0x7 << 11)) + 1;
+ div = (tmp & (0x7 << 8)) + 1;
+ rate = rate * mul / div;
+ return rate;
+}
+
static bool intel_eld_uptodate(struct drm_connector *connector,
int reg_eldv, uint32_t bits_eldv,
int reg_elda, uint32_t bits_elda,
@@ -261,6 +282,8 @@ static void hsw_audio_codec_enable(struct drm_connector
*connector,
const uint8_t *eld = connector->eld;
uint32_t tmp;
int len, i;
+ int n_low, n_up, n;
+ int rate;
DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
pipe_name(pipe), drm_eld_size(eld));
@@ -296,12 +319,27 @@ static void hsw_audio_codec_enable(struct drm_connector
*connector,
/* Enable timestamps */
tmp = I915_READ(HSW_AUD_CFG(pipe));
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
- tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
tmp |= AUD_CONFIG_N_VALUE_INDEX;
else
tmp |= audio_config_hdmi_pixel_clock(mode);
+
+ tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
+ if (audio_rate_need_prog(intel_crtc, mode)) {
+ rate = audio_config_get_rate(dev_priv, pipe);
+ n = audio_config_get_n(mode, rate);
+ if (n != 0) {
+ n_low = n & 0xfff;
+ n_up = (n >> 12) & 0xff;
+ tmp &= ~(AUD_CONFIG_UPPER_N_MASK |
+AUD_CONFIG_LOWER_N_MASK);
+ tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) |
+ (n_low << AUD_CONFIG_LOWER_N_SHIFT) |
+ AUD_CONFIG_N_PROG_ENABLE);
+ }
+ }
+
I915_WRITE(HSW_AUD_CFG(pipe), tmp);
}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 3/4] ALSA: hda - display audio call sync_audio_rate callback
From: Libin Yang
For display audio, call the sync_audio_rate callback function
to do the synchronization between gfx driver and audio driver.
Signed-off-by: Libin Yang
---
sound/pci/hda/patch_hdmi.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
index a97db5f..1668868 100644
--- a/sound/pci/hda/patch_hdmi.c
+++ b/sound/pci/hda/patch_hdmi.c
@@ -1770,6 +1770,16 @@ static bool check_non_pcm_per_cvt(struct hda_codec
*codec, hda_nid_t cvt_nid)
return non_pcm;
}
+/* There is a fixed mapping between audio pin node and display port
+ * on current Intel platforms:
+ * Pin Widget 5 - PORT B (port = 1 in i915 driver)
+ * Pin Widget 6 - PORT C (port = 2 in i915 driver)
+ * Pin Widget 7 - PORT D (port = 3 in i915 driver)
+ */
+static int intel_pin2port(hda_nid_t pin_nid)
+{
+ return pin_nid - 4;
+}
/*
* HDMI callbacks
@@ -1786,6 +1796,8 @@ static int generic_hdmi_playback_pcm_prepare(struct
hda_pcm_stream *hinfo,
int pin_idx = hinfo_to_pin_index(codec, hinfo);
struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
hda_nid_t pin_nid = per_pin->pin_nid;
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct i915_audio_component *acomp = codec->bus->core.audio_component;
bool non_pcm;
int pinctl;
@@ -1802,6 +1814,13 @@ static int generic_hdmi_playback_pcm_prepare(struct
hda_pcm_stream *hinfo,
intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
}
+ /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
+ /* Todo: add DP1.2 MST audio support later */
+ if (acomp && acomp->ops && acomp->ops->sync_audio_rate)
+ acomp->ops->sync_audio_rate(acomp->dev,
+ intel_pin2port(pin_nid),
+ runtime->rate);
+
non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
mutex_lock(&per_pin->lock);
per_pin->channels = substream->runtime->channels;
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 1/4] drm/i915: Add audio sync_audio_rate callback
From: Libin Yang
Add the sync_audio_rate callback.
With the callback, audio driver can trigger
i915 driver to set the proper N/CTS or N/M
based on different sample rates.
Signed-off-by: Libin Yang
---
include/drm/i915_component.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index c9a8b64..aabebcb 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -33,6 +33,7 @@ struct i915_audio_component {
void (*put_power)(struct device *);
void (*codec_wake_override)(struct device *, bool enable);
int (*get_cdclk_freq)(struct device *);
+ int (*sync_audio_rate)(struct device *, int port, int rate);
} *ops;
};
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 2/4] drm/i915: implement sync_audio_rate callback
From: Libin Yang
HDMI audio may not work at some frequencies
with the HW provided N/CTS.
This patch sets the proper N value for the
given audio sample rate at the impacted frequencies.
At other frequencies, it will use the N/CTS value
which HW provides.
Signed-off-by: Libin Yang
---
drivers/gpu/drm/i915/intel_audio.c | 117 +
1 file changed, 117 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index dc32cf4..27add6a 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -68,6 +68,31 @@ static const struct {
{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
};
+/* HDMI N/CTS table */
+#define TMDS_297M 297000
+#define TMDS_296M DIV_ROUND_UP(297000 * 1000, 1001)
+static const struct {
+ int sample_rate;
+ int clock;
+ int n;
+ int cts;
+} aud_ncts[] = {
+ { 44100, TMDS_296M, 4459, 234375 },
+ { 44100, TMDS_297M, 4704, 247500 },
+ { 48000, TMDS_296M, 5824, 281250 },
+ { 48000, TMDS_297M, 5120, 247500 },
+ { 32000, TMDS_296M, 5824, 421875 },
+ { 32000, TMDS_297M, 3072, 222750 },
+ { 88200, TMDS_296M, 8918, 234375 },
+ { 88200, TMDS_297M, 9408, 247500 },
+ { 96000, TMDS_296M, 11648, 281250 },
+ { 96000, TMDS_297M, 10240, 247500 },
+ { 176400, TMDS_296M, 17836, 234375 },
+ { 176400, TMDS_297M, 18816, 247500 },
+ { 44100, TMDS_296M, 23296, 281250 },
+ { 44100, TMDS_297M, 20480, 247500 },
+};
+
/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
{
@@ -90,6 +115,31 @@ static u32 audio_config_hdmi_pixel_clock(struct
drm_display_mode *mode)
return hdmi_audio_clock[i].config;
}
+static int audio_config_get_n(struct drm_display_mode *mode, int rate)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
+ if ((rate == aud_ncts[i].sample_rate) &&
+ (mode->clock == aud_ncts[i].clock)) {
+ return aud_ncts[i].n;
+ }
+ }
+ return 0;
+}
+
+/* check whether N/CTS/M need be set manually */
+static bool audio_rate_need_prog(struct intel_crtc *crtc,
+ struct drm_display_mode *mode)
+{
+ if (((mode->clock == TMDS_297M) ||
+(mode->clock == TMDS_296M)) &&
+ intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
+ return true;
+ else
+ return false;
+}
+
static bool intel_eld_uptodate(struct drm_connector *connector,
int reg_eldv, uint32_t bits_eldv,
int reg_elda, uint32_t bits_elda,
@@ -514,12 +564,79 @@ static int i915_audio_component_get_cdclk_freq(struct
device *dev)
return ret;
}
+static int i915_audio_component_sync_audio_rate(struct device *dev,
+ int port, int rate)
+{
+ struct drm_i915_private *dev_priv = dev_to_i915(dev);
+ struct drm_device *drm_dev = dev_priv->dev;
+ struct intel_encoder *intel_encoder;
+ struct intel_digital_port *intel_dig_port;
+ struct intel_crtc *crtc;
+ struct drm_display_mode *mode;
+ enum pipe pipe = -1;
+ u32 tmp;
+ int n_low, n_up, n;
+
+ /* 1. get the pipe */
+ for_each_intel_encoder(drm_dev, intel_encoder) {
+ intel_dig_port = enc_to_dig_port(&intel_encoder->base);
+ if (port == intel_dig_port->port) {
+ crtc = to_intel_crtc(intel_encoder->base.crtc);
+ if (!crtc) {
+ DRM_DEBUG_KMS("%s: crtc is NULL\n", __func__);
+ continue;
+ }
+ pipe = crtc->pipe;
+ break;
+ }
+ }
+
+ if (pipe == INVALID_PIPE) {
+ DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port));
+ return -ENODEV;
+ }
+ DRM_DEBUG_KMS("pipe %c connects port %c\n",
+ pipe_name(pipe), port_name(port));
+ mode = &crtc->config->base.adjusted_mode;
+
+ /* 2. check whether to set the N/CTS/M manually or not */
+ if (!audio_rate_need_prog(crtc, mode)) {
+ tmp = I915_READ(HSW_AUD_CFG(pipe));
+ tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
+ I915_WRITE(HSW_AUD_CFG(pipe), tmp);
+ return 0;
+ }
+
+ n = audio_config_get_n(mode, rate);
+ if (n == 0) {
+ DRM_DEBUG_KMS("Using automatic mode for N value on port %c\n",
+ port_name(port));
+ tmp = I915_READ(HSW_AUD_CFG(pipe));
+ tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
+ I915_WRITE(HSW_AUD_CFG(pipe), tmp);
+ return
Re: [Intel-gfx] [BXT MIPI PATCH v2 05/13] drm/i915/bxt: DSI encoder support in CRTC modeset
On Sun, 26 Jul 2015, Uma Shankar wrote:
> From: Shashank Sharma
>
> SKL and BXT qualifies the HAS_DDI() check, and hence haswell
> modeset functions are re-used for modeset sequence. But DDI
> interface doesn't include support for DSI.
> This patch adds:
> 1. cases for DSI encoder, in those modeset functions and allows
>a CRTC modeset
> 2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
>needs to be done as such in CRTC for DSI encoder, as PLL, clock
>and and transcoder programming will be taken care in encoder's
>pre_enable and pre_pll_enable function.
>
> v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
> encoder like DSI for platforms having HAS_DDI as true.
>
> Signed-off-by: Shashank Sharma
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/i915_drv.h |1 +
> drivers/gpu/drm/i915/intel_ddi.c | 10 +-
> drivers/gpu/drm/i915/intel_display.c | 19 ++-
> drivers/gpu/drm/i915/intel_opregion.c |3 ++-
> 4 files changed, 26 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 23ce125e..04f746d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -142,6 +142,7 @@ enum plane {
> #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) +
> 'A')
>
> enum port {
> + PORT_INVALID = -1,
> PORT_A = 0,
> PORT_B,
> PORT_C,
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 9a40bfb..2bad86e 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -310,6 +310,10 @@ static void ddi_get_encoder_port(struct intel_encoder
> *intel_encoder,
> } else if (type == INTEL_OUTPUT_ANALOG) {
> *dig_port = NULL;
> *port = PORT_E;
> + } else if (type == INTEL_OUTPUT_DSI) {
> + *dig_port = NULL;
> + *port = PORT_INVALID;
> + DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
> } else {
> DRM_ERROR("Invalid DDI encoder type %d\n", type);
> BUG();
> @@ -565,6 +569,9 @@ void intel_prepare_ddi(struct drm_device *dev)
>
> ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
>
> + if (port == PORT_INVALID)
> + continue;
> +
I think you should add WARN_ON(port == PORT_INVALID) wherever you call
(intel_)ddi_get_encoder_port and you feel you don't need to check the
port.
> if (visited[port])
> continue;
>
> @@ -2052,7 +2059,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder
> *encoder,
> void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
> {
> struct drm_crtc *crtc = &intel_crtc->base;
> - struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
> enum port port = intel_ddi_get_encoder_port(intel_encoder);
> enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 52e21d4..db27995 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4904,6 +4904,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *encoder;
> int pipe = intel_crtc->pipe, hsw_workaround_pipe;
> + bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
> struct intel_crtc_state *pipe_config =
> to_intel_crtc_state(crtc->state);
>
> @@ -4945,7 +4946,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> dev_priv->display.fdi_link_train(crtc);
> }
>
> - intel_ddi_enable_pipe_clock(intel_crtc);
> + if (!is_dsi)
> + intel_ddi_enable_pipe_clock(intel_crtc);
>
> if (INTEL_INFO(dev)->gen == 9)
> skylake_pfit_enable(intel_crtc);
> @@ -4961,7 +4963,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> intel_crtc_load_lut(crtc);
>
> intel_ddi_set_pipe_settings(crtc);
> - intel_ddi_enable_transcoder_func(crtc);
> + if (!is_dsi)
> + intel_ddi_enable_transcoder_func(crtc);
>
> intel_update_watermarks(crtc);
> intel_enable_pipe(intel_crtc);
> @@ -4969,13 +4972,16 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> if (intel_crtc->config->has_pch_encoder)
> lpt_pch_enable(crtc);
>
> - if (intel_crtc->config->dp_encoder_is_mst)
> + if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
> intel_ddi_set_vc_payload_alloc(crtc, true);
>
> assert_vblank_d
Re: [Intel-gfx] [BXT MIPI PATCH v2 06/13] drm/i915/bxt: DSI enable for BXT
On Sun, 26 Jul 2015, Uma Shankar wrote:
> From: Shashank Sharma
>
> This patch contains following changes:
> 1. MIPI device ready changes to support dsi_pre_enable. Changes
>are specific to BXT device ready sequence. Added check for
>ULPS mode(No effects on VLV).
> 2. Changes in dsi_enable to pick BXT port control register.
> 3. Changes in dsi_pre_enable to restrict DPIO programming for VLV
>
> v2: Fixed Jani's review comments. Removed the changes in VLV/CHV
> code. Fixed the macros to get proper port offsets.
>
> Signed-off-by: Shashank Sharma
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/i915_reg.h |9 +++
> drivers/gpu/drm/i915/intel_dsi.c | 156
> ++
> 2 files changed, 115 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8796b25..7559062 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7487,6 +7487,15 @@ enum skl_disp_power_wells {
> #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
> #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
> #define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL,
> _MIPIC_PORT_CTRL)
> +
> + /* BXT port control */
> +#define _BXT_MIPIA_PORT_CTRL 0x6B0C0
> +#define _BXT_MIPIC_PORT_CTRL 0x6B8C0
> +#define BXT_MIPI_PORT_CTRL(tc) _MIPI_PORT(tc, _BXT_MIPIA_PORT_CTRL, \
> + _BXT_MIPIC_PORT_CTRL)
> +#define GET_DSI_PORT_CTRL(dev) (IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
> \
> + MIPI_PORT_CTRL(port))
I think you should just leave that IS_BROXTON check in the code, and
drop the GET_DSI_PORT_CTRL macro. We haven't really done this sort of
thing, and part of the reason (AFAICS) is that it's more obvious to read
the code when you know which register will be used.
> +
> #define DPI_ENABLE (1 << 31) /* A + C */
> #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
> #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK(0xf << 27)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 0b20534..c5889c4 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -281,6 +281,85 @@ static bool intel_dsi_compute_config(struct
> intel_encoder *encoder,
> return true;
> }
>
> +static void bxt_dsi_device_ready(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + enum port port;
> + u32 val;
> +
> + DRM_DEBUG_KMS("\n");
> +
> + /* Exit Low power state in 4 steps*/
> + for_each_dsi_port(port, intel_dsi->ports) {
> +
> + /* 1. Enable MIPI PHY transparent latch */
> + val = I915_READ(BXT_MIPI_PORT_CTRL(port));
> + I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
> + usleep_range(2000, 2500);
> +
> + /* 2. Enter ULPS */
> + val = I915_READ(MIPI_DEVICE_READY(port));
> + val &= ~ULPS_STATE_MASK;
> + val |= (ULPS_STATE_ENTER | DEVICE_READY);
> + I915_WRITE(MIPI_DEVICE_READY(port), val);
> + usleep_range(2, 3);
> +
> + /* 3. Exit ULPS */
> + val = I915_READ(MIPI_DEVICE_READY(port));
> + val &= ~ULPS_STATE_MASK;
> + val |= (ULPS_STATE_EXIT | DEVICE_READY);
> + I915_WRITE(MIPI_DEVICE_READY(port), val);
> + usleep_range(1000, 1500);
> +
> + /* Clear ULPS and set device ready */
> + val = I915_READ(MIPI_DEVICE_READY(port));
> + val &= ~ULPS_STATE_MASK;
> + val |= DEVICE_READY;
> + I915_WRITE(MIPI_DEVICE_READY(port), val);
> + }
> +}
> +
> +static void vlv_dsi_device_ready(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + enum port port;
> + u32 val;
> +
> + DRM_DEBUG_KMS("\n");
> +
> + mutex_lock(&dev_priv->sb_lock);
> + /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
> + * needed everytime after power gate */
> + vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
> + mutex_unlock(&dev_priv->sb_lock);
> +
> + /* bandgap reset is needed after everytime we do power gate */
> + band_gap_reset(dev_priv);
> +
> + for_each_dsi_port(port, intel_dsi->ports) {
> +
> + I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
> + usleep_range(2500, 3000);
> +
> + /* Enable MIPI PHY transparent latch
> + * Common bit for both MIPI Port A & MIPI Port C
> +
[Intel-gfx] [PATCH 0/2] Detect DP displays based on sink count change
From: "Thulasimani,Sivakumar" These two patches together help detect DP displays on short pulse HPD and pass the respective compliance test case (4.2.2.8) Thulasimani,Sivakumar (2): drm/i915: Read sink_count dpcd always for short hpd drm/i915: Perform full detect on sink_count change drivers/gpu/drm/i915/intel_dp.c | 131 +- drivers/gpu/drm/i915/intel_drv.h |1 + 2 files changed, 73 insertions(+), 59 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Perform full detect on sink_count change
From: "Thulasimani,Sivakumar"
This patch checks for changes in sink_count during short pulse hpd
in check_link_status and forces full detect when sink_count
changes. Compliance test 4.2.2.8 expects this behavior in
compliant driver.
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 24 ++--
drivers/gpu/drm/i915/intel_drv.h |1 +
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e4de8e5..04a9ade 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4359,14 +4359,13 @@ intel_dp_detect_dpcd(struct intel_dp *intel_dp)
/* If we're HPD-aware, SINK_COUNT changes dynamically */
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
- uint8_t reg;
if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
- ®, 1) < 0)
+ &intel_dp->sink_count, 1) < 0)
return connector_status_unknown;
- return DP_GET_SINK_COUNT(reg) ? connector_status_connected
- : connector_status_disconnected;
+ return DP_GET_SINK_COUNT(intel_dp->sink_count) ?
+ connector_status_connected : connector_status_disconnected;
}
/* If no HPD, poke DDC gently */
@@ -4401,17 +4400,20 @@ intel_dp_detect_dpcd(struct intel_dp *intel_dp)
* 4. Check link status on receipt of hot-plug interrupt
*/
static void
-intel_dp_check_link_status(struct intel_dp *intel_dp)
+intel_dp_check_link_status(struct intel_dp *intel_dp, bool *need_full_detect)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
struct intel_crtc *crtc =
to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
u8 sink_irq_vector;
+ u8 old_sink_count = intel_dp->sink_count;
u8 link_status[DP_LINK_STATUS_SIZE];
WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
+ *need_full_detect = false;
+
/* 4.2.2.8 requires source to read link_status, 0 - 12 DPCD &
* sink_count even for short pulse irrespective of the sink is
* in use or not
@@ -4423,6 +4425,12 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
if (intel_dp_detect_dpcd(intel_dp) != connector_status_connected)
return;
+ if (old_sink_count != intel_dp->sink_count) {
+ DRM_ERROR("forcing full detect\n");
+ *need_full_detect = true;
+ return;
+ }
+
if (!intel_encoder->base.crtc)
return;
@@ -5026,13 +5034,17 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
}
if (!intel_dp->is_mst) {
+ bool full_detect = false;
/*
* we'll check the link status via the normal hot plug
path later -
* but for short hpds we should check it now
*/
drm_modeset_lock(&dev->mode_config.connection_mutex,
NULL);
- intel_dp_check_link_status(intel_dp);
+ intel_dp_check_link_status(intel_dp, &full_detect);
drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+ if (full_detect)
+ goto put_power;
}
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 81b7d77..8aca5bb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -712,6 +712,7 @@ struct intel_dp {
enum hdmi_force_audio force_audio;
bool limited_color_range;
bool color_range_auto;
+ uint8_t sink_count;
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Read sink_count dpcd always for short hpd
From: "Thulasimani,Sivakumar"
Compliance test 4.2.2.8 requires driver to read the sink_count for
short pulse interrupt even when the panel is not enabled.
This patch performs the following
a) reading sink_count by reusing intel_dp_detect_dpcd
instead of using intel_dp_get_dpcd
b) moving crtc enabled checks post sink_count read call
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 117 ---
1 file changed, 59 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b905c19..e4de8e5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4342,6 +4342,56 @@ go_again:
return -EINVAL;
}
+/* XXX this is probably wrong for multiple downstream ports */
+static enum drm_connector_status
+intel_dp_detect_dpcd(struct intel_dp *intel_dp)
+{
+ uint8_t *dpcd = intel_dp->dpcd;
+ uint8_t type;
+
+ if (!intel_dp_get_dpcd(intel_dp))
+ return connector_status_disconnected;
+
+ /* if there's no downstream port, we're done */
+ if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
+ return connector_status_connected;
+
+ /* If we're HPD-aware, SINK_COUNT changes dynamically */
+ if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
+ intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
+ uint8_t reg;
+
+ if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
+ ®, 1) < 0)
+ return connector_status_unknown;
+
+ return DP_GET_SINK_COUNT(reg) ? connector_status_connected
+ : connector_status_disconnected;
+ }
+
+ /* If no HPD, poke DDC gently */
+ if (drm_probe_ddc(&intel_dp->aux.ddc))
+ return connector_status_connected;
+
+ /* Well we tried, say unknown for unreliable port types */
+ if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
+ type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
+ if (type == DP_DS_PORT_TYPE_VGA ||
+ type == DP_DS_PORT_TYPE_NON_EDID)
+ return connector_status_unknown;
+ } else {
+ type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
+ DP_DWN_STRM_PORT_TYPE_MASK;
+ if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
+ type == DP_DWN_STRM_PORT_TYPE_OTHER)
+ return connector_status_unknown;
+ }
+
+ /* Anything else is out of spec, warn and ignore */
+ DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
+ return connector_status_disconnected;
+}
+
/*
* According to DP spec
* 5.1.2:
@@ -4362,21 +4412,22 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
- if (!intel_encoder->base.crtc)
+ /* 4.2.2.8 requires source to read link_status, 0 - 12 DPCD &
+* sink_count even for short pulse irrespective of the sink is
+* in use or not
+*/
+ if (!intel_dp_get_link_status(intel_dp, link_status))
return;
- if (!to_intel_crtc(intel_encoder->base.crtc)->active)
+ /* reuse to read both 0 - 12 DPCD & sink_count */
+ if (intel_dp_detect_dpcd(intel_dp) != connector_status_connected)
return;
- /* Try to read receiver status if the link appears to be up */
- if (!intel_dp_get_link_status(intel_dp, link_status)) {
+ if (!intel_encoder->base.crtc)
return;
- }
- /* Now read the DPCD to see if it's actually running */
- if (!intel_dp_get_dpcd(intel_dp)) {
+ if (!to_intel_crtc(intel_encoder->base.crtc)->active)
return;
- }
/* Try to read the source of the interrupt */
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
@@ -4401,56 +4452,6 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
}
}
-/* XXX this is probably wrong for multiple downstream ports */
-static enum drm_connector_status
-intel_dp_detect_dpcd(struct intel_dp *intel_dp)
-{
- uint8_t *dpcd = intel_dp->dpcd;
- uint8_t type;
-
- if (!intel_dp_get_dpcd(intel_dp))
- return connector_status_disconnected;
-
- /* if there's no downstream port, we're done */
- if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
- return connector_status_connected;
-
- /* If we're HPD-aware, SINK_COUNT changes dynamically */
- if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
- intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
- uint8_t reg;
-
- if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
- ®, 1) < 0)
-
Re: [Intel-gfx] [PATCH 01/15] drm/i915: Always program m2 fractional value on CHV
On Mon, Aug 17, 2015 at 07:49:41AM +0530, Deepak wrote: > > > On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > When fractional m2 divider isn't used on CHV the fractional part > > is ignore by the hardware. Despite that, program the fractional > > value (0 in this case) to the hardware register just to keep > > things a bit more consistent. Might at least make register dumps > > a bit less confusing when there isn't some stale fractional part > > hanging around. > > > > Signed-off-by: Ville Syrjälä > > --- > > drivers/gpu/drm/i915/intel_display.c | 3 +-- > > 1 file changed, 1 insertion(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index 0b2ad76..3df9cb2 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -7393,8 +7393,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc, > > 1 << DPIO_CHV_N_DIV_SHIFT); > > > > /* M2 fraction division */ > > - if (bestm2_frac) > > - vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); > > + vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); > > > > /* M2 fraction division enable */ > > dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); > Since we do not use fractional m2 driver in chv, can we remove other > bestm2_frac used in chv pll function? > like > if (bestm2_frac) > dpio_val |= DPIO_CHV_FRAC_DIV_EN; > > & > if (!bestm2_frac) > dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; > > Do we need this? We do use the fractional divider, when it's not 0. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [BXT MIPI PATCH v2 07/13] drm/i915/bxt: Program Tx Rx and Dphy clocks
On Sun, 26 Jul 2015, Uma Shankar wrote:
> From: Shashank Sharma
>
> BXT DSI clocks are different than previous platforms. So adding a
> new function to program following clocks and dividers:
> 1. Program variable divider to generate input to Tx clock divider
>(Output value must be < 39.5Mhz)
> 2. Select divide by 2 option to get < 20Mhz for Tx clock
> 3. Program 8by3 divider to generate Rx clock
>
> v2: Fixed Jani's review comments. Adjusted the Macro defintion as
> per convention. Simplified the logic for bit definitions for
> MIPI PORT A and PORT C in same registers.
>
> Signed-off-by: Shashank Sharma
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/i915_reg.h | 40 +
> drivers/gpu/drm/i915/intel_dsi_pll.c | 41
> ++
> 2 files changed, 81 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7559062..310afd4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7445,6 +7445,46 @@ enum skl_disp_power_wells {
>
> #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and
> C only */
>
> +/* BXT MIPI clock controls */
> +#define BXT_MAX_VAR_OUTPUT_KHZ 39500
> +
> +#define BXT_MIPI_CLOCK_CTL 0x46090
> +#define BXT_MIPI_DIV_SHIFT 16
> +/* Var clock divider to generate TX source. Result must be < 39.5 M */
> +#define BXT_MIPI1_ESCLK_VAR_DIV_MASK(0x3F << 26)
> +#define BXT_MIPI2_ESCLK_VAR_DIV_MASK(0x3F << 10)
> +#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
> + (0x3F << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 10))
> +#define BXT_MIPI_ESCLK_VAR_DIV(port, val)\
> + (val << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 10))
> +/* TX control divider to select actual TX clock output from (8x/var) */
> +#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
> +#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
> +#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
> + (3 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 5))
> +#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
> + (0x0 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 5))
> +#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
> + (0x1 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 5))
> +#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
> + (0x2 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 5))
> +/* RX control divider to select actual RX clock output from 8x*/
> +#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
> +#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
> +#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
> + (3 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 3))
> +#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
> + (1 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 3))
> +#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
> + (2 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 3))
> +#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
> + (3 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 3))
> +/* BXT: Always prog DPHY dividers to 00 */
> +#define BXT_MIPI_1_DPHY_DIVIDER_MASK(3 << 16)
> +#define BXT_MIPI_2_DPHY_DIVIDER_MASK(3 << 0)
> +#define BXT_MIPI_DPHY_DIVIDER_MASK(port)\
> + (3 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT))
Meh. Please define the shifts and masks for all fields, and if you want
to have macros with port argument, please use _MIPI_PORT for defining
them.
For example,
#define _BXT_MIPI1_TX_ESCLK_FIXDIV_MASK(3 << 21)
#define _BXT_MIPI2_TX_ESCLK_FIXDIV_MASK(3 << 5)
#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
_MIPI_PORT(port, _BXT_MIPI1_TX_ESCLK_FIXDIV_MASK,
_BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
> +
> /* BXT MIPI mode configure */
> #define _BXT_MIPIA_TRANS_HACTIVE0x6B0F8
> #define _BXT_MIPIC_TRANS_HACTIVE0x6B8F8
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
> b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index f335e6c..0b74399 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -384,6 +384,41 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int
> pipe_bpp)
> return pclk;
> }
>
> +/* Program BXT Mipi clocks and dividers */
> +static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
> +{
> + u32 tmp;
> + u32 divider;
> + u32 dsi_rate;
> + u32 pll_ratio;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + /* Clear old configurations */
> + tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
> + tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
> + tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
> + tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
> + tmp &= ~(
Re: [Intel-gfx] [PATCH 03/15] drm/i915: Add encoder->post_pll_disable() hooks and move CHV clock buffer disables there
On Mon, Aug 17, 2015 at 09:46:01AM +0530, Deepak wrote:
>
>
> On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Move the CHV clock buffer disable from chv_disable_pll() to the new
> > encoder .post_pll_disable() hook. This is more symmetric since the
> > clock buffer enable happens from the .pre_pll_enable() hook.
> >
> > We'll have more use for the new hook soon.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 15 ---
> > drivers/gpu/drm/i915/intel_dp.c | 23 +++
> > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_hdmi.c| 23 +++
> > 4 files changed, 51 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 3df9cb2..db518a7 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1851,17 +1851,6 @@ static void chv_disable_pll(struct drm_i915_private
> > *dev_priv, enum pipe pipe)
> > val &= ~DPIO_DCLKP_EN;
> > vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
> >
> > - /* disable left/right clock distribution */
> > - if (pipe != PIPE_B) {
> > - val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
> > - val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> > - vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
> > - } else {
> > - val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
> > - val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> > - vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> > - }
> > -
> > mutex_unlock(&dev_priv->sb_lock);
> > }
> >
> > @@ -6171,6 +6160,10 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
> > i9xx_disable_pll(intel_crtc);
> > }
> >
> > + for_each_encoder_on_crtc(dev, crtc, encoder)
> > + if (encoder->post_pll_disable)
> > + encoder->post_pll_disable(encoder);
> > +
> We call "vlv_force_pll_off" in vlv_power_sequencer_kick which call
> chv_disablepll.
> Should we add the "post_pll_disable"in force pll off?
Nope. .post_pll_disable() is the counterpart to .pre_pll_enable() which
we don't use either in the pps kick procedure.
Apparently we don't need to concern ourselves with the clock
channel/districtution setp to make the pps kick work. Well, it's either
that, or we've just been lucky and those end up being set up in a good
way by accident. But now that you mention it, I do start wonder a bit
how it really works. So this is probably something I should test more
thoroughly at some point.
> > if (!IS_GEN2(dev))
> > intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> > }
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 32d7e43..40b8430 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2906,6 +2906,28 @@ static void chv_dp_pre_pll_enable(struct
> > intel_encoder *encoder)
> > mutex_unlock(&dev_priv->sb_lock);
> > }
> >
> > +static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > + enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
> > + u32 val;
> > +
> > + mutex_lock(&dev_priv->sb_lock);
> > +
> > + /* disable left/right clock distribution */
> > + if (pipe != PIPE_B) {
> > + val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
> > + val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> > + vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
> > + } else {
> > + val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
> > + val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> > + vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> > + }
> > +
> > + mutex_unlock(&dev_priv->sb_lock);
> > +}
> > +
> > /*
> >* Native read with retry for link status and receiver capability reads
> > for
> >* cases where the sink may still be asleep.
> > @@ -5931,6 +5953,7 @@ intel_dp_init(struct drm_device *dev, int output_reg,
> > enum port port)
> > intel_encoder->pre_enable = chv_pre_enable_dp;
> > intel_encoder->enable = vlv_enable_dp;
> > intel_encoder->post_disable = chv_post_disable_dp;
> > + intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
> > } else if (IS_VALLEYVIEW(dev)) {
> > intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
> > intel_encoder->pre_enable = vlv_pre_enable_dp;
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 4f3b708..42fa135 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu
Re: [Intel-gfx] [BXT MIPI PATCH v2 11/13] drm/i915/bxt: Modify BXT BLC according to VBT changes
On Sun, 26 Jul 2015, Uma Shankar wrote:
> From: Sunil Kamath
>
> Latest VBT mentions which set of registers will be used for BLC,
> as controller number field. Making use of this field in BXT
> BLC implementation. Also, the registers are used in case control
> pin indicates display DDI. Adding a check for this.
> According to Bspec, BLC_PWM_*_2 uses the display utility pin for output.
> To use backlight 2, enable the utility pin with mode = PWM
>v2: Jani's review comments
>addressed
>- Add a prefix _ to BXT BLC registers definitions.
>- Add "bxt only" comment for u8 controller
>- Remove control_pin check for DDI controller
>- Check for valid controller values
>- Set pipe bits in UTIL_PIN_CTL
>- Enable/Disable UTIL_PIN_CTL in enable/disable_backlight()
>- If BLC 2 is used, read active_low_pwm from UTIL_PIN polarity
>Satheesh's review comment addressed
>- If UTIL PIN is already enabled, BIOS would have programmed it. No
>need to disable and enable again.
>v3: Jani's review comments
>- add UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK
>- Disable UTIL_PIN if controller 1 is used
>- Mask out UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK before enabling
>UTIL_PIN
>- check valid controller value in intel_bios.c
>- add backlight.util_pin_active_low
>- disable util pin before enabling
>v4: Change for BXT-PO branch:
>Stubbed unwanted definition which was existing before
>because of DC6 patch.
>UTIL_PIN_MODE_PWM (0x1b << 24)
>
> v2: Fixed Jani's review comment.
>
> Signed-off-by: Vandana Kannan
> Signed-off-by: Sunil Kamath
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/i915_reg.h| 27 ---
> drivers/gpu/drm/i915/intel_drv.h |2 +
> drivers/gpu/drm/i915/intel_panel.c | 94
> +---
> 3 files changed, 100 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 310afd4..0b1d7ff 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3553,17 +3553,29 @@ enum skl_disp_power_wells {
> #define UTIL_PIN_CTL 0x48400
> #define UTIL_PIN_ENABLE(1 << 31)
>
> +#define UTIL_PIN_PIPE(x) ((x) << 29)
> +#define UTIL_PIN_PIPE_MASK (3 << 29)
> +#define UTIL_PIN_MODE_PWM(1 << 24)
> +#define UTIL_PIN_MODE_MASK (0xf << 24)
> +#define UTIL_PIN_POLARITY(1 << 22)
> +
> /* BXT backlight register definition. */
> -#define BXT_BLC_PWM_CTL1 0xC8250
> +#define _BXT_BLC_PWM_CTL10xC8250
> #define BXT_BLC_PWM_ENABLE (1 << 31)
> #define BXT_BLC_PWM_POLARITY (1 << 29)
> -#define BXT_BLC_PWM_FREQ10xC8254
> -#define BXT_BLC_PWM_DUTY10xC8258
> +#define _BXT_BLC_PWM_FREQ1 0xC8254
> +#define _BXT_BLC_PWM_DUTY1 0xC8258
>
> -#define BXT_BLC_PWM_CTL2 0xC8350
> -#define BXT_BLC_PWM_FREQ20xC8354
> -#define BXT_BLC_PWM_DUTY20xC8358
> +#define _BXT_BLC_PWM_CTL20xC8350
> +#define _BXT_BLC_PWM_FREQ2 0xC8354
> +#define _BXT_BLC_PWM_DUTY2 0xC8358
>
> +#define BXT_BLC_PWM_CTL(controller)_PIPE(controller, \
> + _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
> +#define BXT_BLC_PWM_FREQ(controller) _PIPE(controller, \
> + _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
> +#define BXT_BLC_PWM_DUTY(controller) _PIPE(controller, \
> + _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
>
> #define PCH_GTC_CTL 0xe7000
> #define PCH_GTC_ENABLE (1 << 31)
> @@ -7280,6 +7292,9 @@ enum skl_disp_power_wells {
> #define BXT_CDCLK_CD2X_DIV_SEL_4(3<<22)
> #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
>
> +/* Max CDCLK freq for BXT in HZ */
> +#define BXT_CDCLK_MAX62400
> +
> /* LCPLL_CTL */
> #define LCPLL1_CTL 0x46010
> #define LCPLL2_CTL 0x46014
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 3b00d00..8111a21 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -177,7 +177,9 @@ struct intel_panel {
> bool enabled;
> bool combination_mode; /* gen 2/4 only */
> bool active_low_pwm;
> + bool util_pin_active_low; /* bxt+ */
> struct backlight_device *device;
> + u8 controller; /* bxt+ only */
> } backlight;
>
> void (*backlight_power)(struct intel_connector *, bool enable);
> diff --git a/drivers/gpu/drm/i915/intel_panel.c
> b/drivers/gpu/drm/i915/intel_panel.c
> index 55aad23..2a9
Re: [Intel-gfx] [BXT MIPI PATCH v2 12/13] drm/i915/bxt: Remove DSP CLK_GATE programming for BXT
On Sun, 26 Jul 2015, Uma Shankar wrote:
> DSP CLK_GATE registers are specific to BYT and CHT.
> Avoid programming the same for BXT platform.
>
> v2: Rebased on latest drm nightly branch.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/intel_dsi.c |9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 350e10a..d0b26c8 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -612,6 +612,7 @@ static void intel_dsi_clear_device_ready(struct
> intel_encoder *encoder)
>
> static void intel_dsi_post_disable(struct intel_encoder *encoder)
> {
> + struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> u32 val;
> @@ -622,9 +623,11 @@ static void intel_dsi_post_disable(struct intel_encoder
> *encoder)
>
> intel_dsi_clear_device_ready(encoder);
>
> - val = I915_READ(DSPCLK_GATE_D);
> - val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
> - I915_WRITE(DSPCLK_GATE_D, val);
> + if (!IS_BROXTON(dev)) {
You can use dev_priv for IS_BROXTON.
> + val = I915_READ(DSPCLK_GATE_D);
> + val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
> + I915_WRITE(DSPCLK_GATE_D, val);
> + }
>
> drm_panel_unprepare(intel_dsi->panel);
>
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/7] drm/i915: Move DP link parameters out from intel_dp
On Mon, Aug 17, 2015 at 10:42:23AM +0200, Maarten Lankhorst wrote:
> Hey,
>
> Op 06-07-15 om 14:09 schreef ville.syrj...@linux.intel.com:
> > From: Ville Syrjälä
> >
> > While working on CHV DPIO powergating I relized DP .compute_config() was
> > clobbering lane_count etc. stored in intel_dp. This could cause problems
> > if we do the .compute_config() but later fail the modeset for some reason.
> > Any subsequent link re-training might then fail if intel_dp->lane_count
> > etc. got changed.
> >
> > The reason I ran into this during the DPIO powergating work was that I may
> > need to know which lanes he active when shutting down the link. However
> > .compute_config() already clobbered that information by the time I need it.
> > By moving it to the pipe config we avoid that problem as well.
> >
> > I also cleaned up the limited color range handling a bit while I was
> > in the neighborhood.
> >
> > Ville Syrjälä (7):
> > drm/i915: Clean up DP/HDMI limited color range handling
> > drm/i915: Don't use link_bw for PLL setup
> ^
> > drm/i915: Don't pass clock to DDI PLL select functions
> > drm/i915: Avoid confusion between DP and TRANS_DP_CTL in DP
> > .get_config()
> > drm/i915: Move intel_dp->lane_count into pipe_config
> ^Your patch series breaks MST entirely.
>
> drm_encoder->crtc will be NULL and dereferencing crtc->config will fail on
> the primary encoder:
>
> intel_mst_pre_enable_dp(mst_enc) ->
> intel_ddi_init_dp_buf_reg(mst_enc->primary). -> primary->crtc = NULL, OOPS.
>
> Voltage training was failing too and I was getting a MCE until I reverted the
> crtc->config changes from this series..
Hmm. Our modeset code vs. mst seems to a huge mess. To fix it properly
we should split the link compute/setup from the pipe config entirely.
As a short term solution I suppose I could pass the pipe config into
various dp link setup functions rather than assume that we can dig it
out from the encoder->crtc.
>
>
> > drm/i915: Don't use link_bw to select between TP1 and TP3
> > drm/i915: Kill intel_dp->{link_bw,rate_select}
> >
> > drivers/gpu/drm/i915/i915_reg.h | 3 +
> > drivers/gpu/drm/i915/intel_ddi.c | 41
> > drivers/gpu/drm/i915/intel_display.c | 7 +-
> > drivers/gpu/drm/i915/intel_dp.c | 177
> > ---
> > drivers/gpu/drm/i915/intel_dp_mst.c | 19 ++--
> > drivers/gpu/drm/i915/intel_drv.h | 9 +-
> > drivers/gpu/drm/i915/intel_hdmi.c| 26 +++--
> > 7 files changed, 155 insertions(+), 127 deletions(-)
> >
--
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [BXT MIPI PATCH v2 13/13] drm/i915: Added BXT DSI backlight support
On Sun, 26 Jul 2015, Uma Shankar wrote:
> DSI backlight support for bxt is added.
>
> TODO: There is no support for backlight control in drm panel
> framework. This will be added as part of VBT version patches
> fixing the backlight sequence.
>
> v2: Fixed Jani's review comments from previous patch. Added the
> BXT DSI backlight code in this patch. Backlight setup and
> enable/disable code for backlight is added in intel_dsi.c.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 25 -
> 1 file changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index d0b26c8..36fcb86 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -431,6 +431,7 @@ static void intel_dsi_enable(struct intel_encoder
> *encoder)
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + struct intel_connector *intel_connector = intel_dsi->attached_connector;
> enum port port;
>
> DRM_DEBUG_KMS("\n");
> @@ -451,6 +452,16 @@ static void intel_dsi_enable(struct intel_encoder
> *encoder)
>
> intel_dsi_port_enable(encoder);
> }
> +
> + if (IS_BROXTON(dev)) {
> + if (intel_dsi->backlight_on_delay >= 20)
> + msleep(intel_dsi->backlight_on_delay);
> + else
> + usleep_range(intel_dsi->backlight_on_delay * 1000,
> + (intel_dsi->backlight_on_delay * 1000)
> + 500);
Please just use msleep, let's optimize (possibly with sensible wrappers)
later.
> +
> + intel_panel_enable_backlight(intel_connector);
> + }
> }
>
> static void intel_dsi_pre_enable(struct intel_encoder *encoder)
> @@ -615,10 +626,20 @@ static void intel_dsi_post_disable(struct intel_encoder
> *encoder)
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + struct intel_connector *intel_connector = intel_dsi->attached_connector;
> u32 val;
>
> DRM_DEBUG_KMS("\n");
>
> + if (IS_BROXTON(dev)) {
> + intel_panel_disable_backlight(intel_connector);
> + if (intel_dsi->backlight_off_delay >= 20)
> + msleep(intel_dsi->backlight_off_delay);
> + else
> + usleep_range(intel_dsi->backlight_off_delay * 1000,
> + (intel_dsi->backlight_off_delay * 1000) + 500);
> + }
> +
> intel_dsi_disable(encoder);
>
> intel_dsi_clear_device_ready(encoder);
> @@ -1213,9 +1234,11 @@ void intel_dsi_init(struct drm_device *dev)
> }
>
> intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
> + if (IS_BROXTON(dev))
> + intel_panel_setup_backlight(connector,
> + intel_encoder->crtc_mask == (1 << PIPE_A) ? PIPE_A :
> PIPE_B);
The pipe parameter is not used for broxton, you can just pass
INVALID_PIPE.
>
> return;
> -
> err:
> drm_encoder_cleanup(&intel_encoder->base);
> kfree(intel_dsi);
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Read sink_count dpcd always for short hpd
On Mon, 17 Aug 2015, Sivakumar Thulasimani
wrote:
> From: "Thulasimani,Sivakumar"
>
> Compliance test 4.2.2.8 requires driver to read the sink_count for
> short pulse interrupt even when the panel is not enabled.
> This patch performs the following
> a) reading sink_count by reusing intel_dp_detect_dpcd
> instead of using intel_dp_get_dpcd
> b) moving crtc enabled checks post sink_count read call
>
> Signed-off-by: Sivakumar Thulasimani
> ---
> drivers/gpu/drm/i915/intel_dp.c | 117
> ---
> 1 file changed, 59 insertions(+), 58 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b905c19..e4de8e5 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4342,6 +4342,56 @@ go_again:
> return -EINVAL;
> }
>
> +/* XXX this is probably wrong for multiple downstream ports */
> +static enum drm_connector_status
> +intel_dp_detect_dpcd(struct intel_dp *intel_dp)
> +{
> + uint8_t *dpcd = intel_dp->dpcd;
> + uint8_t type;
> +
> + if (!intel_dp_get_dpcd(intel_dp))
> + return connector_status_disconnected;
> +
> + /* if there's no downstream port, we're done */
> + if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
> + return connector_status_connected;
> +
> + /* If we're HPD-aware, SINK_COUNT changes dynamically */
> + if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
> + intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
> + uint8_t reg;
> +
> + if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
> + ®, 1) < 0)
> + return connector_status_unknown;
> +
> + return DP_GET_SINK_COUNT(reg) ? connector_status_connected
> + : connector_status_disconnected;
> + }
> +
> + /* If no HPD, poke DDC gently */
> + if (drm_probe_ddc(&intel_dp->aux.ddc))
> + return connector_status_connected;
> +
> + /* Well we tried, say unknown for unreliable port types */
> + if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
> + type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
> + if (type == DP_DS_PORT_TYPE_VGA ||
> + type == DP_DS_PORT_TYPE_NON_EDID)
> + return connector_status_unknown;
> + } else {
> + type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
> + DP_DWN_STRM_PORT_TYPE_MASK;
> + if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
> + type == DP_DWN_STRM_PORT_TYPE_OTHER)
> + return connector_status_unknown;
> + }
> +
> + /* Anything else is out of spec, warn and ignore */
> + DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
> + return connector_status_disconnected;
> +}
Please either a) just add a forward declaration for
intel_dp_detect_dpcd, or b) add a separate non-functional prep patch
that moves the function around. Please don't combine code movement with
functional changes.
BR,
Jani.
> +
> /*
> * According to DP spec
> * 5.1.2:
> @@ -4362,21 +4412,22 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
>
> WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
>
> - if (!intel_encoder->base.crtc)
> + /* 4.2.2.8 requires source to read link_status, 0 - 12 DPCD &
> + * sink_count even for short pulse irrespective of the sink is
> + * in use or not
> + */
> + if (!intel_dp_get_link_status(intel_dp, link_status))
> return;
>
> - if (!to_intel_crtc(intel_encoder->base.crtc)->active)
> + /* reuse to read both 0 - 12 DPCD & sink_count */
> + if (intel_dp_detect_dpcd(intel_dp) != connector_status_connected)
> return;
>
> - /* Try to read receiver status if the link appears to be up */
> - if (!intel_dp_get_link_status(intel_dp, link_status)) {
> + if (!intel_encoder->base.crtc)
> return;
> - }
>
> - /* Now read the DPCD to see if it's actually running */
> - if (!intel_dp_get_dpcd(intel_dp)) {
> + if (!to_intel_crtc(intel_encoder->base.crtc)->active)
> return;
> - }
>
> /* Try to read the source of the interrupt */
> if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
> @@ -4401,56 +4452,6 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
> }
> }
>
> -/* XXX this is probably wrong for multiple downstream ports */
> -static enum drm_connector_status
> -intel_dp_detect_dpcd(struct intel_dp *intel_dp)
> -{
> - uint8_t *dpcd = intel_dp->dpcd;
> - uint8_t type;
> -
> - if (!intel_dp_get_dpcd(intel_dp))
> - return connector_status_disconnected;
> -
> - /* if there's no downstream port, we're done */
> - if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
> - retur
[Intel-gfx] [PATCH 2/4] drm/i915: remove HBR2 from chv supported list
From: "Thulasimani,Sivakumar" This patch removes 5.4Gbps from supported link rate for CHV since it is not supported in it. v2: change the ordering for better readability (Ville) Signed-off-by: Sivakumar Thulasimani --- drivers/gpu/drm/i915/intel_dp.c |7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index bfe0567..475d8cb 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1220,11 +1220,12 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates) *source_rates = default_rates; + /* WaDisableHBR2:skl */ if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) - /* WaDisableHBR2:skl */ return (DP_LINK_BW_2_7 >> 3) + 1; - else if (INTEL_INFO(dev)->gen >= 8 || - (IS_HASWELL(dev) && !IS_HSW_ULX(dev))) + + if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || + (INTEL_INFO(dev)->gen >= 9)) return (DP_LINK_BW_5_4 >> 3) + 1; else return (DP_LINK_BW_2_7 >> 3) + 1; -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/4] Revert "drm/i915: Add eDP intermediate frequencies for CHV"
From: "Thulasimani,Sivakumar"
This reverts
commit fe51bfb95c996733150c44d21e1c9f4b6322a326.
Author: Ville Syrjälä
Date: Thu Mar 12 17:10:38 2015 +0200
CHV does not support intermediate frequencies so reverting the
patch that added it in the first place
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c |6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b905c19..bfe0567 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -95,9 +95,6 @@ static const int bxt_rates[] = { 162000, 216000, 243000,
27,
324000, 432000, 54 };
static const int skl_rates[] = { 162000, 216000, 27,
324000, 432000, 54 };
-static const int chv_rates[] = { 162000, 202500, 21, 216000,
-243000, 27, 324000, 405000,
-42, 432000, 54 };
static const int default_rates[] = { 162000, 27, 54 };
/**
@@ -1219,9 +1216,6 @@ intel_dp_source_rates(struct drm_device *dev, const int
**source_rates)
} else if (IS_SKYLAKE(dev)) {
*source_rates = skl_rates;
return ARRAY_SIZE(skl_rates);
- } else if (IS_CHERRYVIEW(dev)) {
- *source_rates = chv_rates;
- return ARRAY_SIZE(chv_rates);
}
*source_rates = default_rates;
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/4] HBR2 cleanup for CHV/SKL
From: "Thulasimani,Sivakumar" This patch series cleans up the code to remove HBR2 support for CHV since it is not supported on CHV. Also fixes a bug for SKL platforms where HBR2 is not supported. Thulasimani,Sivakumar (4): Revert "drm/i915: Add eDP intermediate frequencies for CHV" drm/i915: remove HBR2 from chv supported list drm/i915: Avoid TP3 on CHV drm/i915: fix link rates reported for SKL drivers/gpu/drm/i915/intel_dp.c | 43 +++ 1 file changed, 25 insertions(+), 18 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/4] drm/i915: fix link rates reported for SKL
From: "Thulasimani,Sivakumar"
This patch fixes the bug that SKL SKUs before B0 might return
HBR2 as supported even though it is not supposed to be enabled
on such platforms.
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 03523b3..963fdae 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1224,21 +1224,23 @@ static bool intel_dp_is_hbr2_supported(struct
drm_device *dev)
static int
intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
{
+ int size = 0;
if (IS_BROXTON(dev)) {
*source_rates = bxt_rates;
- return ARRAY_SIZE(bxt_rates);
+ size = ARRAY_SIZE(bxt_rates);
} else if (IS_SKYLAKE(dev)) {
*source_rates = skl_rates;
- return ARRAY_SIZE(skl_rates);
+ size = ARRAY_SIZE(skl_rates);
+ } else {
+ *source_rates = default_rates;
+ size = ARRAY_SIZE(default_rates);
}
- *source_rates = default_rates;
-
/* This depends on the fact that 5.4 is last value in the array */
if (intel_dp_is_hbr2_supported(dev))
- return (DP_LINK_BW_5_4 >> 3) + 1;
+ return size;
else
- return (DP_LINK_BW_2_7 >> 3) + 1;
+ return size - 1;
}
static void
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/4] drm/i915: Avoid TP3 on CHV
From: "Thulasimani,Sivakumar"
This patch removes TP3 support on CHV since there is no support
for HBR2 on this platform.
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 475d8cb..03523b3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1207,6 +1207,20 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int
**sink_rates)
return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
}
+static bool intel_dp_is_hbr2_supported(struct drm_device *dev)
+{
+ /* WaDisableHBR2:skl */
+ if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
+ return false;
+
+ if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
+ (INTEL_INFO(dev)->gen >= 9))
+ return true;
+ else
+ return false;
+}
+
+
static int
intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
{
@@ -1220,12 +1234,8 @@ intel_dp_source_rates(struct drm_device *dev, const int
**source_rates)
*source_rates = default_rates;
- /* WaDisableHBR2:skl */
- if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
- return (DP_LINK_BW_2_7 >> 3) + 1;
-
- if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
- (INTEL_INFO(dev)->gen >= 9))
+ /* This depends on the fact that 5.4 is last value in the array */
+ if (intel_dp_is_hbr2_supported(dev))
return (DP_LINK_BW_5_4 >> 3) + 1;
else
return (DP_LINK_BW_2_7 >> 3) + 1;
@@ -3926,7 +3936,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
/* Training Pattern 3 support, both source and sink */
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
- (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
+ intel_dp_is_hbr2_supported(dev)) {
intel_dp->use_tps3 = true;
DRM_DEBUG_KMS("Displayport TPS3 supported\n");
} else
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 2/4] drm/i915: implement sync_audio_rate callback
On Mon, 17 Aug 2015, libin.y...@intel.com wrote:
> From: Libin Yang
>
> HDMI audio may not work at some frequencies
> with the HW provided N/CTS.
>
> This patch sets the proper N value for the
> given audio sample rate at the impacted frequencies.
> At other frequencies, it will use the N/CTS value
> which HW provides.
>
> Signed-off-by: Libin Yang
> ---
> drivers/gpu/drm/i915/intel_audio.c | 117
> +
> 1 file changed, 117 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_audio.c
> b/drivers/gpu/drm/i915/intel_audio.c
> index dc32cf4..27add6a 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -68,6 +68,31 @@ static const struct {
> { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
> };
>
> +/* HDMI N/CTS table */
> +#define TMDS_297M 297000
> +#define TMDS_296M DIV_ROUND_UP(297000 * 1000, 1001)
> +static const struct {
> + int sample_rate;
> + int clock;
> + int n;
> + int cts;
> +} aud_ncts[] = {
> + { 44100, TMDS_296M, 4459, 234375 },
> + { 44100, TMDS_297M, 4704, 247500 },
> + { 48000, TMDS_296M, 5824, 281250 },
> + { 48000, TMDS_297M, 5120, 247500 },
> + { 32000, TMDS_296M, 5824, 421875 },
> + { 32000, TMDS_297M, 3072, 222750 },
> + { 88200, TMDS_296M, 8918, 234375 },
> + { 88200, TMDS_297M, 9408, 247500 },
> + { 96000, TMDS_296M, 11648, 281250 },
> + { 96000, TMDS_297M, 10240, 247500 },
> + { 176400, TMDS_296M, 17836, 234375 },
> + { 176400, TMDS_297M, 18816, 247500 },
> + { 44100, TMDS_296M, 23296, 281250 },
> + { 44100, TMDS_297M, 20480, 247500 },
> +};
> +
> /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
> static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
> {
> @@ -90,6 +115,31 @@ static u32 audio_config_hdmi_pixel_clock(struct
> drm_display_mode *mode)
> return hdmi_audio_clock[i].config;
> }
>
> +static int audio_config_get_n(struct drm_display_mode *mode, int rate)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
> + if ((rate == aud_ncts[i].sample_rate) &&
> + (mode->clock == aud_ncts[i].clock)) {
> + return aud_ncts[i].n;
> + }
> + }
> + return 0;
> +}
> +
> +/* check whether N/CTS/M need be set manually */
> +static bool audio_rate_need_prog(struct intel_crtc *crtc,
> + struct drm_display_mode *mode)
> +{
> + if (((mode->clock == TMDS_297M) ||
> + (mode->clock == TMDS_296M)) &&
> + intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
> + return true;
> + else
> + return false;
> +}
> +
> static bool intel_eld_uptodate(struct drm_connector *connector,
> int reg_eldv, uint32_t bits_eldv,
> int reg_elda, uint32_t bits_elda,
> @@ -514,12 +564,79 @@ static int i915_audio_component_get_cdclk_freq(struct
> device *dev)
> return ret;
> }
>
> +static int i915_audio_component_sync_audio_rate(struct device *dev,
> + int port, int rate)
> +{
> + struct drm_i915_private *dev_priv = dev_to_i915(dev);
> + struct drm_device *drm_dev = dev_priv->dev;
> + struct intel_encoder *intel_encoder;
> + struct intel_digital_port *intel_dig_port;
> + struct intel_crtc *crtc;
> + struct drm_display_mode *mode;
> + enum pipe pipe = -1;
> + u32 tmp;
> + int n_low, n_up, n;
> +
> + /* 1. get the pipe */
> + for_each_intel_encoder(drm_dev, intel_encoder) {
> + intel_dig_port = enc_to_dig_port(&intel_encoder->base);
Mmmh, not all encoders are digital ports. enc_to_dig_port does a
container_of, so you can't just check for NULL either. IOW, you need to
check the encoder->type (and you only care about HDMI here).
> + if (port == intel_dig_port->port) {
> + crtc = to_intel_crtc(intel_encoder->base.crtc);
> + if (!crtc) {
> + DRM_DEBUG_KMS("%s: crtc is NULL\n", __func__);
> + continue;
> + }
> + pipe = crtc->pipe;
> + break;
> + }
> + }
> +
> + if (pipe == INVALID_PIPE) {
> + DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port));
> + return -ENODEV;
> + }
> + DRM_DEBUG_KMS("pipe %c connects port %c\n",
> + pipe_name(pipe), port_name(port));
> + mode = &crtc->config->base.adjusted_mode;
> +
> + /* 2. check whether to set the N/CTS/M manually or not */
> + if (!audio_rate_need_prog(crtc, mode)) {
> + tmp = I915_READ(HSW_AUD_CFG(pipe));
> + tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
> + I915_WRITE(HSW_AUD_CFG(pipe), tmp);
> + return 0;
> + }
> +
> + n = audio_
[Intel-gfx] [PATCH] drm/i915: Pass pipe_config to DP link training functions
From: Ville Syrjälä
With MST the primary encoder doesn't have a crtc, so trying to dig out
the pipe config via that is going to explode. Insted pass the pipe
config in so that the MST code can pass in what it wants.
It's still a huge mess since the MST code recomputes the main link
parameters for every stream. We should really aim to split the main link
setup so that we'd compute it only once.
Fixes a regression with MST caused by:
commit 90a6b7b052b1aa17fbb98b049e9c8b7f729c35a7
Author: Ville Syrjälä
Date: Mon Jul 6 16:39:15 2015 +0300
drm/i915: Move intel_dp->lane_count into pipe_config
Cc: Maarten Lankhorst
Reported-by: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c| 12 +--
drivers/gpu/drm/i915/intel_dp.c | 42 ++---
drivers/gpu/drm/i915/intel_dp_mst.c | 7 ---
drivers/gpu/drm/i915/intel_drv.h| 9 +---
4 files changed, 36 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 56d778f..9b1a538 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -723,16 +723,16 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
DRM_ERROR("FDI link training failed!\n");
}
-void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
+void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config)
{
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
struct intel_digital_port *intel_dig_port =
enc_to_dig_port(&encoder->base);
- struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
intel_dp->DP = intel_dig_port->saved_port_bits |
DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
- intel_dp->DP |= DDI_PORT_WIDTH(crtc->config->lane_count);
+ intel_dp->DP |= DDI_PORT_WIDTH(pipe_config->lane_count);
}
static struct intel_encoder *
@@ -2314,11 +2314,11 @@ static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder)
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- intel_ddi_init_dp_buf_reg(intel_encoder);
+ intel_ddi_init_dp_buf_reg(intel_encoder, crtc->config);
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
- intel_dp_start_link_train(intel_dp);
- intel_dp_complete_link_train(intel_dp);
+ intel_dp_start_link_train(intel_dp, crtc->config);
+ intel_dp_complete_link_train(intel_dp, crtc->config);
if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
intel_dp_stop_link_train(intel_dp);
} else if (type == INTEL_OUTPUT_HDMI) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b905c19..c5d85d8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2576,8 +2576,8 @@ static void intel_enable_dp(struct intel_encoder *encoder)
lane_mask);
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
- intel_dp_start_link_train(intel_dp);
- intel_dp_complete_link_train(intel_dp);
+ intel_dp_start_link_train(intel_dp, crtc->config);
+ intel_dp_complete_link_train(intel_dp, crtc->config);
intel_dp_stop_link_train(intel_dp);
if (crtc->config->has_audio) {
@@ -3620,11 +3620,10 @@ static void intel_dp_set_idle_link_train(struct
intel_dp *intel_dp)
/* Enable corresponding port and start training pattern 1 */
void
-intel_dp_start_link_train(struct intel_dp *intel_dp)
+intel_dp_start_link_train(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *pipe_config)
{
struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
- struct intel_crtc *crtc =
- to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
struct drm_device *dev = encoder->dev;
int i;
uint8_t voltage;
@@ -3636,12 +3635,12 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
if (HAS_DDI(dev))
intel_ddi_prepare_link_retrain(encoder);
- intel_dp_compute_rate(intel_dp, crtc->config->port_clock,
+ intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
&link_bw, &rate_select);
/* Write the link configuration data */
link_config[0] = link_bw;
- link_config[1] = crtc->config->lane_count;
+ link_config[1] = pipe_config->lane_count;
if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
@@ -3675,7 +3674,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
Re: [Intel-gfx] [PATCH 3/4] drm/i915: Avoid TP3 on CHV
On Mon, 17 Aug 2015, Sivakumar Thulasimani
wrote:
> From: "Thulasimani,Sivakumar"
>
> This patch removes TP3 support on CHV since there is no support
> for HBR2 on this platform.
>
> Signed-off-by: Sivakumar Thulasimani
> ---
> drivers/gpu/drm/i915/intel_dp.c | 24 +---
> 1 file changed, 17 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 475d8cb..03523b3 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1207,6 +1207,20 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const
> int **sink_rates)
> return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
> }
>
> +static bool intel_dp_is_hbr2_supported(struct drm_device *dev)
Sorry to be a nitpicker, but I really like how we've started
distinguishing source and sink in such helpers in intel_dp.c, for
example intel_dp_source_rates vs. intel_dp_sink_rates. Similarly I think
you should name this intel_dp_source_supports_hbr2.
BR,
Jani.
> +{
> + /* WaDisableHBR2:skl */
> + if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
> + return false;
> +
> + if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
> + (INTEL_INFO(dev)->gen >= 9))
> + return true;
> + else
> + return false;
> +}
> +
> +
> static int
> intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
> {
> @@ -1220,12 +1234,8 @@ intel_dp_source_rates(struct drm_device *dev, const
> int **source_rates)
>
> *source_rates = default_rates;
>
> - /* WaDisableHBR2:skl */
> - if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
> - return (DP_LINK_BW_2_7 >> 3) + 1;
> -
> - if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
> - (INTEL_INFO(dev)->gen >= 9))
> + /* This depends on the fact that 5.4 is last value in the array */
> + if (intel_dp_is_hbr2_supported(dev))
> return (DP_LINK_BW_5_4 >> 3) + 1;
> else
> return (DP_LINK_BW_2_7 >> 3) + 1;
> @@ -3926,7 +3936,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
> /* Training Pattern 3 support, both source and sink */
> if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
> intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
> - (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
> + intel_dp_is_hbr2_supported(dev)) {
> intel_dp->use_tps3 = true;
> DRM_DEBUG_KMS("Displayport TPS3 supported\n");
> } else
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/4] drm/i915: fix link rates reported for SKL
On Mon, 17 Aug 2015, Sivakumar Thulasimani
wrote:
> From: "Thulasimani,Sivakumar"
>
> This patch fixes the bug that SKL SKUs before B0 might return
> HBR2 as supported even though it is not supposed to be enabled
> on such platforms.
>
> Signed-off-by: Sivakumar Thulasimani
> ---
> drivers/gpu/drm/i915/intel_dp.c | 14 --
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 03523b3..963fdae 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1224,21 +1224,23 @@ static bool intel_dp_is_hbr2_supported(struct
> drm_device *dev)
> static int
> intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
> {
> + int size = 0;
No need to initialize.
> if (IS_BROXTON(dev)) {
> *source_rates = bxt_rates;
> - return ARRAY_SIZE(bxt_rates);
> + size = ARRAY_SIZE(bxt_rates);
> } else if (IS_SKYLAKE(dev)) {
> *source_rates = skl_rates;
> - return ARRAY_SIZE(skl_rates);
> + size = ARRAY_SIZE(skl_rates);
> + } else {
> + *source_rates = default_rates;
> + size = ARRAY_SIZE(default_rates);
> }
>
> - *source_rates = default_rates;
> -
> /* This depends on the fact that 5.4 is last value in the array */
> if (intel_dp_is_hbr2_supported(dev))
> - return (DP_LINK_BW_5_4 >> 3) + 1;
> + return size;
> else
> - return (DP_LINK_BW_2_7 >> 3) + 1;
> + return size - 1;
/* This depends on the fact that 5.4 is last value in the array */
if (!intel_dp_source_supports_hbr2(dev))
size--;
return size;
> }
>
> static void
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 3/4] ALSA: hda - display audio call sync_audio_rate callback
On Mon, 17 Aug 2015 12:40:00 +0200,
libin.y...@intel.com wrote:
>
> From: Libin Yang
>
> For display audio, call the sync_audio_rate callback function
> to do the synchronization between gfx driver and audio driver.
>
> Signed-off-by: Libin Yang
I guess it would be easier to take this series from drm tree.
Feel free to my ack
Reviewed-by: Takashi Iwai
thanks,
Takashi
> ---
> sound/pci/hda/patch_hdmi.c | 19 +++
> 1 file changed, 19 insertions(+)
>
> diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
> index a97db5f..1668868 100644
> --- a/sound/pci/hda/patch_hdmi.c
> +++ b/sound/pci/hda/patch_hdmi.c
> @@ -1770,6 +1770,16 @@ static bool check_non_pcm_per_cvt(struct hda_codec
> *codec, hda_nid_t cvt_nid)
> return non_pcm;
> }
>
> +/* There is a fixed mapping between audio pin node and display port
> + * on current Intel platforms:
> + * Pin Widget 5 - PORT B (port = 1 in i915 driver)
> + * Pin Widget 6 - PORT C (port = 2 in i915 driver)
> + * Pin Widget 7 - PORT D (port = 3 in i915 driver)
> + */
> +static int intel_pin2port(hda_nid_t pin_nid)
> +{
> + return pin_nid - 4;
> +}
>
> /*
> * HDMI callbacks
> @@ -1786,6 +1796,8 @@ static int generic_hdmi_playback_pcm_prepare(struct
> hda_pcm_stream *hinfo,
> int pin_idx = hinfo_to_pin_index(codec, hinfo);
> struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
> hda_nid_t pin_nid = per_pin->pin_nid;
> + struct snd_pcm_runtime *runtime = substream->runtime;
> + struct i915_audio_component *acomp = codec->bus->core.audio_component;
> bool non_pcm;
> int pinctl;
>
> @@ -1802,6 +1814,13 @@ static int generic_hdmi_playback_pcm_prepare(struct
> hda_pcm_stream *hinfo,
> intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
> }
>
> + /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
> + /* Todo: add DP1.2 MST audio support later */
> + if (acomp && acomp->ops && acomp->ops->sync_audio_rate)
> + acomp->ops->sync_audio_rate(acomp->dev,
> + intel_pin2port(pin_nid),
> + runtime->rate);
> +
> non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
> mutex_lock(&per_pin->lock);
> per_pin->channels = substream->runtime->channels;
> --
> 1.9.1
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/4] drm/i915: fix link rates reported for SKL
On Mon, Aug 17, 2015 at 05:45:11PM +0530, Sivakumar Thulasimani wrote:
> From: "Thulasimani,Sivakumar"
>
> This patch fixes the bug that SKL SKUs before B0 might return
> HBR2 as supported even though it is not supposed to be enabled
> on such platforms.
>
> Signed-off-by: Sivakumar Thulasimani
> ---
> drivers/gpu/drm/i915/intel_dp.c | 14 --
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 03523b3..963fdae 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1224,21 +1224,23 @@ static bool intel_dp_is_hbr2_supported(struct
> drm_device *dev)
> static int
> intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
> {
> + int size = 0;
> if (IS_BROXTON(dev)) {
> *source_rates = bxt_rates;
> - return ARRAY_SIZE(bxt_rates);
> + size = ARRAY_SIZE(bxt_rates);
> } else if (IS_SKYLAKE(dev)) {
> *source_rates = skl_rates;
> - return ARRAY_SIZE(skl_rates);
> + size = ARRAY_SIZE(skl_rates);
> + } else {
> + *source_rates = default_rates;
> + size = ARRAY_SIZE(default_rates);
> }
>
> - *source_rates = default_rates;
> -
> /* This depends on the fact that 5.4 is last value in the array */
> if (intel_dp_is_hbr2_supported(dev))
> - return (DP_LINK_BW_5_4 >> 3) + 1;
> + return size;
> else
> - return (DP_LINK_BW_2_7 >> 3) + 1;
> + return size - 1;
Maybe we should use rate_to_index() here? Should be a bit more
future proof for when we get HBR3. So, perhaps something like this?
{
...
*source_rates = bxt_rates;
size_rates = ARRAY_SIZE(bxt_rates);
...
if (intel_dp_is_hbr2_supported)
max_rate = 54;
else
max_rate = 27;
size = rate_to_index(max_rate, *source_rates) + 1;
if (WARN_ON(size > size_rates))
size = size_rates;
return size;
}
But that could be a followup patch.
Otherwise the series looks good so:
Reviewed-by: Ville Syrjälä
> }
>
> static void
> --
> 1.7.9.5
--
Ville Syrjälä
Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Read sink_count dpcd always for short hpd
From: "Thulasimani,Sivakumar"
Compliance test 4.2.2.8 requires driver to read the sink_count for
short pulse interrupt even when the panel is not enabled.
This patch performs the following
a) reading sink_count by reusing intel_dp_detect_dpcd
instead of using intel_dp_get_dpcd
b) moving crtc enabled checks post sink_count read call
v2: avoid code movement with functionality changes (Ville)
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b905c19..0b73e98 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -132,6 +132,8 @@ static void edp_panel_vdd_off(struct intel_dp *intel_dp,
bool sync);
static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
static void vlv_steal_power_sequencer(struct drm_device *dev,
enum pipe pipe);
+static enum drm_connector_status
+intel_dp_detect_dpcd(struct intel_dp *intel_dp);
static int
intel_dp_max_link_bw(struct intel_dp *intel_dp)
@@ -4362,21 +4364,23 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
- if (!intel_encoder->base.crtc)
+ /* 4.2.2.8 requires source to read link_status, 0 - 12 DPCD &
+* sink_count even for short pulse irrespective of the sink is
+* in use or not
+*/
+ if (!intel_dp_get_link_status(intel_dp, link_status)) {
return;
+ }
- if (!to_intel_crtc(intel_encoder->base.crtc)->active)
+ /* reuse to read both 0 - 12 DPCD & sink_count */
+ if (intel_dp_detect_dpcd(intel_dp) != connector_status_connected)
return;
- /* Try to read receiver status if the link appears to be up */
- if (!intel_dp_get_link_status(intel_dp, link_status)) {
+ if (!intel_encoder->base.crtc)
return;
- }
- /* Now read the DPCD to see if it's actually running */
- if (!intel_dp_get_dpcd(intel_dp)) {
+ if (!to_intel_crtc(intel_encoder->base.crtc)->active)
return;
- }
/* Try to read the source of the interrupt */
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Perform full detect on sink_count change
From: "Thulasimani,Sivakumar"
This patch checks for changes in sink_count during short pulse hpd
in check_link_status and forces full detect when sink_count
changes. Compliance test 4.2.2.8 expects this behavior in
compliant driver.
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 25 +++--
drivers/gpu/drm/i915/intel_drv.h |1 +
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0b73e98..067f9ee 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4353,17 +4353,20 @@ go_again:
* 4. Check link status on receipt of hot-plug interrupt
*/
static void
-intel_dp_check_link_status(struct intel_dp *intel_dp)
+intel_dp_check_link_status(struct intel_dp *intel_dp, bool *need_full_detect)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
struct intel_crtc *crtc =
to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
u8 sink_irq_vector;
+ u8 old_sink_count = intel_dp->sink_count;
u8 link_status[DP_LINK_STATUS_SIZE];
WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
+ *need_full_detect = false;
+
/* 4.2.2.8 requires source to read link_status, 0 - 12 DPCD &
* sink_count even for short pulse irrespective of the sink is
* in use or not
@@ -4376,6 +4379,12 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
if (intel_dp_detect_dpcd(intel_dp) != connector_status_connected)
return;
+ if (old_sink_count != intel_dp->sink_count) {
+ DRM_ERROR("forcing full detect\n");
+ *need_full_detect = true;
+ return;
+ }
+
if (!intel_encoder->base.crtc)
return;
@@ -4422,14 +4431,13 @@ intel_dp_detect_dpcd(struct intel_dp *intel_dp)
/* If we're HPD-aware, SINK_COUNT changes dynamically */
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
- uint8_t reg;
if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
- ®, 1) < 0)
+ &intel_dp->sink_count, 1) < 0)
return connector_status_unknown;
- return DP_GET_SINK_COUNT(reg) ? connector_status_connected
- : connector_status_disconnected;
+ return DP_GET_SINK_COUNT(intel_dp->sink_count) ?
+ connector_status_connected : connector_status_disconnected;
}
/* If no HPD, poke DDC gently */
@@ -5029,13 +5037,18 @@ intel_dp_hpd_pulse(struct intel_digital_port
*intel_dig_port, bool long_hpd)
}
if (!intel_dp->is_mst) {
+ bool full_detect = false;
+
/*
* we'll check the link status via the normal hot plug
path later -
* but for short hpds we should check it now
*/
drm_modeset_lock(&dev->mode_config.connection_mutex,
NULL);
- intel_dp_check_link_status(intel_dp);
+ intel_dp_check_link_status(intel_dp, &full_detect);
drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+ if (full_detect)
+ goto put_power;
}
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 81b7d77..8aca5bb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -712,6 +712,7 @@ struct intel_dp {
enum hdmi_force_audio force_audio;
bool limited_color_range;
bool color_range_auto;
+ uint8_t sink_count;
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/2] Detect DP displays based on sink count change
From: "Thulasimani,Sivakumar" These two patches together help detect DP displays on short pulse HPD and pass the respective compliance test case (4.2.2.8) Thulasimani,Sivakumar (2): drm/i915: Read sink_count dpcd always for short hpd drm/i915: Perform full detect on sink_count change drivers/gpu/drm/i915/intel_dp.c | 43 ++ drivers/gpu/drm/i915/intel_drv.h |1 + 2 files changed, 31 insertions(+), 13 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/4] scripts/kernel-doc: Adding cross-reference links to html documentation.
On 08/17/2015 01:10 AM, Jonathan Corbet wrote: > On Tue, 28 Jul 2015 16:45:15 -0300 > Danilo Cesar Lemes de Paula wrote: > >> Functions, Structs and Parameters definitions on kernel documentation >> are pure cosmetic, it only highlights the element. >> >> To ease the navigation in the documentation we should use inside >> those tags so readers can easily jump between methods directly. >> >> This was discussed in 2014[1] and is implemented by getting a list >> of from the DocBook XML to generate a database. Then it looks >> for , and tags that matches the ones in >> the database. As it only links existent references, no broken links are >> added. > > So I had some airplane time today and was able to mess with this some. I > can't make it break anymore, and it clearly improves the resulting > documentation, so I've applied it to the docs tree for 4.3. > > I want to look at the rest of the stuff a bit more and play with it, but > it's hard to imagine why we wouldn't want that as well. I'm a bit more > leery just because it adds another dependency to the build, even if it's > an optional dependency. My thinking at the moment is to apply it shortly I totally agree about the dependency stuff. I even discussed it with Daniel Vetter a bit. I started by writing my-very-own-markup-parser to put alongside kernel-doc to avoid external dependencies, but it gets too complex too quickly (specially when dealing with tables and multi-line stuff). It would be a pain to maintain a something like that, and the world probably doesn't need yet-another-markup-parser, so I decided to use another tool. > after the merge window so it can have a long soak in linux-next before a > 4.4 merge; hope that sounds good. It does sound good. Thanks! > > Thanks for doing this work, Glad I could help. Danilo ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 2/4] drm/i915: implement sync_audio_rate callback
Hi Jani
> -Original Message-
> From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
> Sent: Monday, August 17, 2015 8:21 PM
> To: Yang, Libin; alsa-de...@alsa-project.org; ti...@suse.de; intel-
> g...@lists.freedesktop.org; daniel.vet...@ffwll.ch
> Cc: Yang, Libin
> Subject: Re: [PATCH v3 2/4] drm/i915: implement sync_audio_rate
> callback
>
> On Mon, 17 Aug 2015, libin.y...@intel.com wrote:
> > From: Libin Yang
> >
> > HDMI audio may not work at some frequencies
> > with the HW provided N/CTS.
> >
> > This patch sets the proper N value for the
> > given audio sample rate at the impacted frequencies.
> > At other frequencies, it will use the N/CTS value
> > which HW provides.
> >
> > Signed-off-by: Libin Yang
> > ---
> > drivers/gpu/drm/i915/intel_audio.c | 117
> +
> > 1 file changed, 117 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_audio.c
> b/drivers/gpu/drm/i915/intel_audio.c
> > index dc32cf4..27add6a 100644
> > --- a/drivers/gpu/drm/i915/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/intel_audio.c
> > @@ -68,6 +68,31 @@ static const struct {
> > { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
> > };
> >
> > +/* HDMI N/CTS table */
> > +#define TMDS_297M 297000
> > +#define TMDS_296M DIV_ROUND_UP(297000 * 1000, 1001)
> > +static const struct {
> > + int sample_rate;
> > + int clock;
> > + int n;
> > + int cts;
> > +} aud_ncts[] = {
> > + { 44100, TMDS_296M, 4459, 234375 },
> > + { 44100, TMDS_297M, 4704, 247500 },
> > + { 48000, TMDS_296M, 5824, 281250 },
> > + { 48000, TMDS_297M, 5120, 247500 },
> > + { 32000, TMDS_296M, 5824, 421875 },
> > + { 32000, TMDS_297M, 3072, 222750 },
> > + { 88200, TMDS_296M, 8918, 234375 },
> > + { 88200, TMDS_297M, 9408, 247500 },
> > + { 96000, TMDS_296M, 11648, 281250 },
> > + { 96000, TMDS_297M, 10240, 247500 },
> > + { 176400, TMDS_296M, 17836, 234375 },
> > + { 176400, TMDS_297M, 18816, 247500 },
> > + { 44100, TMDS_296M, 23296, 281250 },
> > + { 44100, TMDS_297M, 20480, 247500 },
> > +};
> > +
> > /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
> > static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode
> *mode)
> > {
> > @@ -90,6 +115,31 @@ static u32
> audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
> > return hdmi_audio_clock[i].config;
> > }
> >
> > +static int audio_config_get_n(struct drm_display_mode *mode, int
> rate)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
> > + if ((rate == aud_ncts[i].sample_rate) &&
> > + (mode->clock == aud_ncts[i].clock)) {
> > + return aud_ncts[i].n;
> > + }
> > + }
> > + return 0;
> > +}
> > +
> > +/* check whether N/CTS/M need be set manually */
> > +static bool audio_rate_need_prog(struct intel_crtc *crtc,
> > + struct drm_display_mode
> *mode)
> > +{
> > + if (((mode->clock == TMDS_297M) ||
> > +(mode->clock == TMDS_296M)) &&
> > + intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
> > + return true;
> > + else
> > + return false;
> > +}
> > +
> > static bool intel_eld_uptodate(struct drm_connector *connector,
> >int reg_eldv, uint32_t bits_eldv,
> >int reg_elda, uint32_t bits_elda,
> > @@ -514,12 +564,79 @@ static int
> i915_audio_component_get_cdclk_freq(struct device *dev)
> > return ret;
> > }
> >
> > +static int i915_audio_component_sync_audio_rate(struct device
> *dev,
> > + int port, int rate)
> > +{
> > + struct drm_i915_private *dev_priv = dev_to_i915(dev);
> > + struct drm_device *drm_dev = dev_priv->dev;
> > + struct intel_encoder *intel_encoder;
> > + struct intel_digital_port *intel_dig_port;
> > + struct intel_crtc *crtc;
> > + struct drm_display_mode *mode;
> > + enum pipe pipe = -1;
> > + u32 tmp;
> > + int n_low, n_up, n;
> > +
> > + /* 1. get the pipe */
> > + for_each_intel_encoder(drm_dev, intel_encoder) {
> > + intel_dig_port = enc_to_dig_port(&intel_encoder-
> >base);
>
> Mmmh, not all encoders are digital ports. enc_to_dig_port does a
> container_of, so you can't just check for NULL either. IOW, you need
> to
> check the encoder->type (and you only care about HDMI here).
Do you mean it should be:
if (!crtc || !intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
regards,
Libin
>
> > + if (port == intel_dig_port->port) {
> > + crtc = to_intel_crtc(intel_encoder->base.crtc);
> > + if (!crtc) {
> > + DRM_DEBUG_KMS("%s: crtc is
> NULL\n", __func__);
> > + continue;
> > + }
> > + pipe = crtc->pipe;
> > + break;
> > + }
> > + }
> > +
> > + if (pipe == INVALID_PIPE) {
> > + DRM_DEBUG_KMS("no pipe
Re: [Intel-gfx] [PATCH v3 3/4] ALSA: hda - display audio call sync_audio_rate callback
Hi Takashi,
> -Original Message-
> From: Takashi Iwai [mailto:ti...@suse.de]
> Sent: Monday, August 17, 2015 8:26 PM
> To: Yang, Libin
> Cc: alsa-de...@alsa-project.org; intel-gfx@lists.freedesktop.org;
> daniel.vet...@ffwll.ch; jani.nik...@linux.intel.com
> Subject: Re: [PATCH v3 3/4] ALSA: hda - display audio call
> sync_audio_rate callback
>
> On Mon, 17 Aug 2015 12:40:00 +0200,
> libin.y...@intel.com wrote:
> >
> > From: Libin Yang
> >
> > For display audio, call the sync_audio_rate callback function
> > to do the synchronization between gfx driver and audio driver.
> >
> > Signed-off-by: Libin Yang
>
> I guess it would be easier to take this series from drm tree.
> Feel free to my ack
> Reviewed-by: Takashi Iwai
Get it. Thanks.
Regards,
Libin
>
>
> thanks,
>
> Takashi
>
>
> > ---
> > sound/pci/hda/patch_hdmi.c | 19 +++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/sound/pci/hda/patch_hdmi.c
> b/sound/pci/hda/patch_hdmi.c
> > index a97db5f..1668868 100644
> > --- a/sound/pci/hda/patch_hdmi.c
> > +++ b/sound/pci/hda/patch_hdmi.c
> > @@ -1770,6 +1770,16 @@ static bool
> check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
> > return non_pcm;
> > }
> >
> > +/* There is a fixed mapping between audio pin node and display
> port
> > + * on current Intel platforms:
> > + * Pin Widget 5 - PORT B (port = 1 in i915 driver)
> > + * Pin Widget 6 - PORT C (port = 2 in i915 driver)
> > + * Pin Widget 7 - PORT D (port = 3 in i915 driver)
> > + */
> > +static int intel_pin2port(hda_nid_t pin_nid)
> > +{
> > + return pin_nid - 4;
> > +}
> >
> > /*
> > * HDMI callbacks
> > @@ -1786,6 +1796,8 @@ static int
> generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
> > int pin_idx = hinfo_to_pin_index(codec, hinfo);
> > struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
> > hda_nid_t pin_nid = per_pin->pin_nid;
> > + struct snd_pcm_runtime *runtime = substream->runtime;
> > + struct i915_audio_component *acomp = codec->bus-
> >core.audio_component;
> > bool non_pcm;
> > int pinctl;
> >
> > @@ -1802,6 +1814,13 @@ static int
> generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
> > intel_not_share_assigned_cvt(codec, pin_nid, per_pin-
> >mux_idx);
> > }
> >
> > + /* Call sync_audio_rate to set the N/CTS/M manually if
> necessary */
> > + /* Todo: add DP1.2 MST audio support later */
> > + if (acomp && acomp->ops && acomp->ops->sync_audio_rate)
> > + acomp->ops->sync_audio_rate(acomp->dev,
> > + intel_pin2port(pin_nid),
> > + runtime->rate);
> > +
> > non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
> > mutex_lock(&per_pin->lock);
> > per_pin->channels = substream->runtime->channels;
> > --
> > 1.9.1
> >
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: Put back lane_count into intel_dp and add link_rate too
From: Ville Syrjälä
With MST there won't be a crtc assigned to the main link encoder, so
trying to dig up the pipe_config from there is a recipe for an oops.
Instead store the parameters (lane_count and link_rate) in the encoder,
and use those values during link training etc. Since those parameters
are now assigned only when the link is actually enabled,
.compute_config() won't clobber them as it did before.
Hardware state readout is still bonkers though as we don't transfer the
link parameters from pipe_config intel_dp. We should do that during
encoder sanitation. But since we don't even do a proper job of reading
out the main link encoder state for MST there's littel point in
worrying about this now.
Fixes a regression with MST caused by:
commit 90a6b7b052b1aa17fbb98b049e9c8b7f729c35a7
Author: Ville Syrjälä
Date: Mon Jul 6 16:39:15 2015 +0300
drm/i915: Move intel_dp->lane_count into pipe_config
v2: Different apporoach that should keep intel_dp_check_mst_status()
somewhat less oopsy
Cc: Maarten Lankhorst
Reported-by: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c| 5 ++--
drivers/gpu/drm/i915/intel_dp.c | 53 +
drivers/gpu/drm/i915/intel_dp_mst.c | 2 ++
drivers/gpu/drm/i915/intel_drv.h| 4 +++
4 files changed, 33 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 56d778f..5dff8b7 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -728,11 +728,10 @@ void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder)
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
struct intel_digital_port *intel_dig_port =
enc_to_dig_port(&encoder->base);
- struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
intel_dp->DP = intel_dig_port->saved_port_bits |
DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
- intel_dp->DP |= DDI_PORT_WIDTH(crtc->config->lane_count);
+ intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
}
static struct intel_encoder *
@@ -2314,6 +2313,8 @@ static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder)
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ intel_dp_set_link_params(intel_dp, crtc->config);
+
intel_ddi_init_dp_buf_reg(intel_encoder);
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b905c19..dcda86a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1584,6 +1584,13 @@ static void ironlake_set_pll_cpu_edp(struct intel_dp
*intel_dp)
udelay(500);
}
+void intel_dp_set_link_params(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *pipe_config)
+{
+ intel_dp->link_rate = pipe_config->port_clock;
+ intel_dp->lane_count = pipe_config->lane_count;
+}
+
static void intel_dp_prepare(struct intel_encoder *encoder)
{
struct drm_device *dev = encoder->base.dev;
@@ -1593,6 +1600,8 @@ static void intel_dp_prepare(struct intel_encoder
*encoder)
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
struct drm_display_mode *adjusted_mode =
&crtc->config->base.adjusted_mode;
+ intel_dp_set_link_params(intel_dp, crtc->config);
+
/*
* There are four kinds of DP registers:
*
@@ -3348,15 +3357,13 @@ static void
intel_get_adjust_train(struct intel_dp *intel_dp,
const uint8_t link_status[DP_LINK_STATUS_SIZE])
{
- struct intel_crtc *crtc =
- to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
uint8_t v = 0;
uint8_t p = 0;
int lane;
uint8_t voltage_max;
uint8_t preemph_max;
- for (lane = 0; lane < crtc->config->lane_count; lane++) {
+ for (lane = 0; lane < intel_dp->lane_count; lane++) {
uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status,
lane);
uint8_t this_p =
drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
@@ -3527,8 +3534,6 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv =
to_i915(intel_dig_port->base.base.dev);
- struct intel_crtc *crtc =
- to_intel_crtc(intel_dig_port->base.base.crtc);
uint8_t buf[sizeof(intel_dp->train_set) + 1];
int ret, len;
@@ -3544,8 +3549,8 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
len = 1;
} else {
/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
- memcpy(buf + 1,
[Intel-gfx] [PATCH] drm/i915: Try to fix MST for SKL
From: Ville Syrjälä
Set up the DDI->PLL mapping on SKL also for MST links. Might help make
MST operational on SKL.
Cc: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c| 49 ++---
drivers/gpu/drm/i915/intel_dp_mst.c | 8 +-
drivers/gpu/drm/i915/intel_drv.h| 2 ++
3 files changed, 32 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 5dff8b7..10a5a98 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2258,30 +2258,21 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
return DDI_BUF_TRANS_SELECT(level);
}
-static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
+void intel_ddi_clk_select(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config)
{
- struct drm_encoder *encoder = &intel_encoder->base;
- struct drm_device *dev = encoder->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
- enum port port = intel_ddi_get_encoder_port(intel_encoder);
- int type = intel_encoder->type;
- int hdmi_level;
-
- if (type == INTEL_OUTPUT_EDP) {
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- intel_edp_panel_on(intel_dp);
- }
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = intel_ddi_get_encoder_port(encoder);
- if (IS_SKYLAKE(dev)) {
- uint32_t dpll = crtc->config->ddi_pll_sel;
+ if (IS_SKYLAKE(dev_priv)) {
+ uint32_t dpll = pipe_config->ddi_pll_sel;
uint32_t val;
/*
* DPLL0 is used for eDP and is the only "private" DPLL (as
* opposed to shared) on SKL
*/
- if (type == INTEL_OUTPUT_EDP) {
+ if (encoder->type == INTEL_OUTPUT_EDP) {
WARN_ON(dpll != SKL_DPLL0);
val = I915_READ(DPLL_CTRL1);
@@ -2289,7 +2280,7 @@ static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder)
val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
DPLL_CTRL1_SSC(dpll) |
DPLL_CTRL1_LINK_RATE_MASK(dpll));
- val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
+ val |= pipe_config->dpll_hw_state.ctrl1 << (dpll * 6);
I915_WRITE(DPLL_CTRL1, val);
POSTING_READ(DPLL_CTRL1);
@@ -2305,11 +2296,29 @@ static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder)
I915_WRITE(DPLL_CTRL2, val);
- } else if (INTEL_INFO(dev)->gen < 9) {
- WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
- I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
+ } else if (INTEL_INFO(dev_priv)->gen < 9) {
+ WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
+ I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
+ }
+}
+
+static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
+{
+ struct drm_encoder *encoder = &intel_encoder->base;
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
+ enum port port = intel_ddi_get_encoder_port(intel_encoder);
+ int type = intel_encoder->type;
+ int hdmi_level;
+
+ if (type == INTEL_OUTPUT_EDP) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ intel_edp_panel_on(intel_dp);
}
+ intel_ddi_clk_select(intel_encoder, crtc->config);
+
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
b/drivers/gpu/drm/i915/intel_dp_mst.c
index ebf2054..fd25aeb7 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -163,20 +163,14 @@ static void intel_mst_pre_enable_dp(struct intel_encoder
*encoder)
intel_mst->port = found->port;
if (intel_dp->active_mst_links == 0) {
- enum port port = intel_ddi_get_encoder_port(encoder);
+ intel_ddi_clk_select(encoder, intel_crtc->config);
intel_dp_set_link_params(intel_dp, intel_crtc->config);
- /* FIXME: add support for SKL */
- if (INTEL_INFO(dev)->gen < 9)
- I915_WRITE(PORT_CLK_SEL(port),
- intel_crtc->config->ddi_pll_sel);
-
intel_ddi_init_dp_buf_reg(&intel_dig_port->base);
intel_dp_si
[Intel-gfx] [PATCH i-g-t] assembler: remove built sources with make clean
Built sources are generated by "make all", so should be removed by "make clean". This also ensures "distcleancheck" passes. Signed-off-by: Thomas Wood --- assembler/Makefile.am | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/assembler/Makefile.am b/assembler/Makefile.am index c285438..fb309ac 100644 --- a/assembler/Makefile.am +++ b/assembler/Makefile.am @@ -47,7 +47,7 @@ intel_gen4disasm_LDADD = libbrw.la pkgconfigdir = $(libdir)/pkgconfig pkgconfig_DATA = intel-gen4asm.pc -MAINTAINERCLEANFILES = $(BUILT_SOURCES) +CLEANFILES = $(BUILT_SOURCES) EXTRA_DIST = \ README \ TODO \ -- 2.4.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: fix driver's versions of WARN_ON & WARN_ON_ONCE
The current versions of these two macros don't work correctly if the
argument expression happens to contain a modulo operator (%) -- when
stringified, it gets interpreted as a printf formatting character!
With a specifically crafted parameter, this could probably cause a
kernel OOPS; consider WARN_ON(p%s) or WARN_ON(f %*pEp).
Instead, we should use an explicit "%s" format, with the stringified
expression as the coresponding literal-string argument.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b157865..674b223 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -67,11 +67,11 @@
BUILD_BUG_ON(__i915_warn_cond); \
WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
#else
-#define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
+#define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
#endif
#undef WARN_ON_ONCE
-#define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")")
+#define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
(long) (x), __func__);
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Video freezes continue
On Sat, 2015-08-15 at 17:17 -0500, Chris wrote: > I'm still continuing to experience video lockups though not quite as > frequent as before. The most recent was 12 August. I'm running the > kernel as shown in my sig. I've attached my Xorg.0.log. I'm able to SSH > into my desktop from my tablet and running > cat /sys/class/drm/card0/error shows 'no error state collected'. Running > cat /sys/kernel/debug/dri/0/i915_swizzle_info outputs > > bit6 swizzle for X-tiling = none > bit6 swizzle for Y-tiling = none > DDC = 0x00200010 > DDC2 = 0x00300030 > C0DRB3 = 0x0030 > C1DRB3 = 0x0010 > > This has been going on for a few months less than a year now. When this > happens the video is frozen however the mouse cursor will continue to > move and all background processes such as fetchmail, procmail, postfix > and all cronjobs continue running. > > This is a Dell Optiplex 780 with BIOS A15 4gb of ram. Periodically this > would show in the syslog about the same time as the freeze > > Jul 28 16:02:28 localhost kernel: [793861.820048] > [drm:i915_hangcheck_elapsed [i915]] *ERROR* Hangcheck timer elapsed... > render ring idle > > The above was the last time the 'Hangcheck' error was noted. I'm running > Gnome 3.12.2 and Ubuntu 14.04.3 LTS > > Any advice will be appreciated. > > Chris > I guess this is an issue I just have to live with or should I update to a newer kernel and see what happens? I'm a little lost here, is there anything I can do to troubleshoot this any further? Chris -- Chris KeyID 0xE372A7DA98E6705C 31.11°N 97.89°W (Elev. 1092 ft) 11:35:47 up 5 days, 4:52, 1 user, load average: 0.55, 0.42, 0.47 Ubuntu 14.04.3 LTS, kernel 4.0.0-997-generic #201503310205 SMP Tue Mar 31 02:07:04 UTC 2015 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH igt] lib/igt_core: use print("%s", #expr) instead of print(#expr)
On 13/08/15 18:17, Paulo Zanoni wrote: If I have a program with the following: igt_skip_on(i % 2 == 0); igt_skip_on_f(i % 2 == 0, "i:%d\n", i); igt_require(i % 2 == 0); igt_require_f(i % 2 == 0, "i:%d\n", i); then I'll get compiler error messages complaining about format conversions related to the '%' character used in the mod operation. So put the whole string as a %s argument to avoid interpreting '%' and any other possible chars. Signed-off-by: Paulo Zanoni Reviewed-by: Dave Gordon ... and I found a similar issue in the i915 driver's macros; see the patch I just posted: [PATCH] drm/i915: fix driver's versions of WARN_ON & WARN_ON_ONCE .Dave. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: fix driver's versions of WARN_ON & WARN_ON_ONCE
2015-08-17 13:30 GMT-03:00 Dave Gordon :
> The current versions of these two macros don't work correctly if the
> argument expression happens to contain a modulo operator (%) -- when
> stringified, it gets interpreted as a printf formatting character!
> With a specifically crafted parameter, this could probably cause a
> kernel OOPS; consider WARN_ON(p%s) or WARN_ON(f %*pEp).
>
> Instead, we should use an explicit "%s" format, with the stringified
> expression as the coresponding literal-string argument.
I suppose that was inspired by the recent IGT commit :)
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Dave Gordon
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b157865..674b223 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -67,11 +67,11 @@
> BUILD_BUG_ON(__i915_warn_cond); \
> WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
> #else
> -#define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
> +#define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
> #endif
>
> #undef WARN_ON_ONCE
> -#define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")")
> +#define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
>
> #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
> (long) (x), __func__);
> --
> 1.9.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] tools/null_state/gen9: Send all components in VF state
On Thu, Aug 13, 2015 at 04:11:00PM +0300, Mika Kuoppala wrote: > Fix > > commit 59cdc16b1a6f069f944ff17851a59edf8f72d45d > Author: Arun Siluvery > Date: Fri Jul 31 16:27:07 2015 +0100 > > tools/null_state/gen9: Send atleast one valid component in VF state > > to honor the Reviewed-by, send all four components as noted by > Ben in his review. > > Cc: Ben Widawsky > Cc: Arun Siluvery > Signed-off-by: Mika Kuoppala Thanks. (STILL in favor of just dropping it :P ) Reviewed-by: Ben Widawsky -- Ben Widawsky, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fix build warning on 32-bit
Em Sex, 2015-08-14 às 12:35 +0200, Thierry Reding escreveu:
> From: Thierry Reding
>
> The gtt.stolen_size field is of type size_t, and so should be printed
> using %zu to avoid build warnings on either 32-bit and 64-bit builds.
While the suggestion from Chris sounds good, this patch alone is
already a fix, so:
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Thierry Reding
> ---
> drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c
> b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index a36cb95ec798..f361c4a56995 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -348,7 +348,7 @@ int i915_gem_init_stolen(struct drm_device *dev)
>* memory, so just consider the start. */
> reserved_total = stolen_top - reserved_base;
>
> - DRM_DEBUG_KMS("Memory reserved for graphics device: %luK,
> usable: %luK\n",
> + DRM_DEBUG_KMS("Memory reserved for graphics device: %zuK,
> usable: %luK\n",
> dev_priv->gtt.stolen_size >> 10,
> (dev_priv->gtt.stolen_size - reserved_total)
> >> 10);
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] lib: add a single include header
Add a header that includes all the headers for the library. This allows reorganisation of the library without affecting programs using it and also simplifies the headers that need to be included to use the library. Signed-off-by: Thomas Wood --- lib/igt.h | 49 ++ tests/core_get_client_auth.c | 3 +-- tests/core_getclient.c | 2 +- tests/core_getstats.c | 3 +-- tests/core_getversion.c| 2 +- tests/drm_auth.c | 4 +-- tests/drm_import_export.c | 3 +-- tests/drm_read.c | 4 +-- tests/drm_vma_limiter.c| 6 + tests/drm_vma_limiter_cached.c | 6 + tests/drm_vma_limiter_cpu.c| 6 + tests/drm_vma_limiter_gtt.c| 6 + tests/drv_getparams_basic.c| 3 +-- tests/drv_hangman.c| 6 + tests/drv_suspend.c| 5 +--- tests/eviction_common.c| 3 +-- tests/gem_alive.c | 2 +- tests/gem_bad_address.c| 6 + tests/gem_bad_batch.c | 6 + tests/gem_bad_blit.c | 6 + tests/gem_bad_length.c | 3 +-- tests/gem_bad_reloc.c | 5 +--- tests/gem_basic.c | 3 +-- tests/gem_caching.c| 7 + tests/gem_close_race.c | 4 +-- tests/gem_concurrent_all.c | 9 +-- tests/gem_cpu_reloc.c | 7 + tests/gem_cs_prefetch.c| 7 + tests/gem_cs_tlb.c | 5 +--- tests/gem_ctx_bad_destroy.c| 3 +-- tests/gem_ctx_bad_exec.c | 3 +-- tests/gem_ctx_basic.c | 6 + tests/gem_ctx_create.c | 3 +-- tests/gem_ctx_exec.c | 5 +--- tests/gem_ctx_param_basic.c| 4 +-- tests/gem_ctx_thrash.c | 5 +--- tests/gem_double_irq_loop.c| 6 + tests/gem_dummy_reloc_loop.c | 6 + tests/gem_eio.c| 6 + tests/gem_evict_alignment.c| 6 + tests/gem_evict_everything.c | 5 +--- tests/gem_exec_alignment.c | 4 +-- tests/gem_exec_bad_domains.c | 6 + tests/gem_exec_big.c | 5 +--- tests/gem_exec_blt.c | 5 +--- tests/gem_exec_faulting_reloc.c| 6 + tests/gem_exec_lut_handle.c| 4 +-- tests/gem_exec_nop.c | 5 +--- tests/gem_exec_params.c| 6 + tests/gem_exec_parse.c | 4 +-- tests/gem_fd_exhaustion.c | 4 +-- tests/gem_fence_thrash.c | 3 +-- tests/gem_fence_upload.c | 3 +-- tests/gem_fenced_exec_thrash.c | 6 + tests/gem_flink_basic.c| 3 +-- tests/gem_flink_race.c | 4 +-- tests/gem_gpgpu_fill.c | 6 + tests/gem_gtt_cpu_tlb.c| 4 +-- tests/gem_gtt_hog.c| 4 +-- tests/gem_gtt_speed.c | 3 +-- tests/gem_hang.c | 6 + tests/gem_hangcheck_forcewake.c| 6 + tests/gem_largeobject.c| 3 +-- tests/gem_linear_blits.c | 6 + tests/gem_lut_handle.c | 3 +-- tests/gem_madvise.c| 3 +-- tests/gem_media_fill.c | 6 + tests/gem_mmap.c | 4 +-- tests/gem_mmap_gtt.c | 5 +--- tests/gem_mmap_offset_exhaustion.c | 3 +-- tests/gem_mmap_wc.c| 4 +-- tests/gem_multi_bsd_sync_loop.c| 6 + tests/gem_non_secure_batch.c | 6 + tests/gem_partial_pwrite_pread.c | 6 + tests/gem_persistent_relocs.c | 7 + tests/gem_pin.c| 6 + tests/gem_pipe_control_store_loop.c| 6 + tests/gem_ppgtt.c | 7 + tests/gem_pread.c | 3 +-- tests/gem_pread_after_blit.c | 7 + tests/gem_pwrite.c | 4 +-- tests/gem_pwrite_pread.c | 6 + tests/gem_pwrite_snooped.c | 5 +--- tests/gem_read_read_speed.c| 9 +-- tests/gem_readwrite.c | 3 +-- tests/gem_reg_read.c | 3 +-- tests/gem_reloc_overflow.c | 5 +--- tests/gem_reloc_vs_gpu.c | 8 +- tests/gem_render_copy.c| 7 + tests/gem_render_copy_redux.c | 7 + tests/gem_render_linear_blits.c| 7 + tests/gem_render_tiled_blits.c | 7 + tests/gem_reset_stats.c| 7 + tests/gem_ring_sync_copy.c | 5 +--- tests/gem_ring
Re: [Intel-gfx] [PATCH 01/11] drm/i915: Clean up various HPD defines
2015-08-12 12:44 GMT-03:00 :
> From: Ville Syrjälä
>
> Indent the PORTx_HOTPLUG_... defines appropriately, and fix some space
> vs. tab issues.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h | 72
> +
> 1 file changed, 37 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6786e94..ed2d150 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5364,15 +5364,17 @@ enum skl_disp_power_wells {
>
> #define CPU_VGACNTRL 0x41000
>
> -#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
Maybe add a comment for the fields that are only valid up to IVB?
> -#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
> -#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
> -#define DIGITAL_PORTA_SHORT_PULSE_4_5MS(1 << 2)
> -#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
> -#define DIGITAL_PORTA_SHORT_PULSE_100MS(3 << 2)
> -#define DIGITAL_PORTA_NO_DETECT(0 << 0)
> -#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
> -#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
> +#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
> +#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
> +#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2)
I think I prefer the old SHORT_PULSE_duration names.
> +#define DIGITAL_PORTA_PULSE_DURATION_4_5ms(1 << 2)
> +#define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2)
> +#define DIGITAL_PORTA_PULSE_DURATION_100ms(3 << 2)
> +#define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2)
> +#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
> +#define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
> +#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT(1 << 0)
> +#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
>
> /* refresh rate hardware control */
> #define RR_HW_CTL 0x45300
> @@ -6000,45 +6002,45 @@ enum skl_disp_power_wells {
>
> /* digital port hotplug */
> #define PCH_PORT_HOTPLUG0xc4030/* SHOTPLUG_CTL */
> -#define BXT_PORTA_HOTPLUG_ENABLE (1 << 28)
> -#define BXT_PORTA_HOTPLUG_STATUS_MASK (0x3 << 24)
> +#define BXT_PORTA_HOTPLUG_ENABLE (1 << 28)
> +#define BXT_PORTA_HOTPLUG_STATUS_MASK (3 << 24)
> #define BXT_PORTA_HOTPLUG_NO_DETECT (0 << 24)
> #define BXT_PORTA_HOTPLUG_SHORT_DETECT(1 << 24)
> #define BXT_PORTA_HOTPLUG_LONG_DETECT (2 << 24)
> -#define PORTD_HOTPLUG_ENABLE(1 << 20)
> -#define PORTD_PULSE_DURATION_2ms(0)
> -#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
> -#define PORTD_PULSE_DURATION_6ms(2 << 18)
> -#define PORTD_PULSE_DURATION_100ms (3 << 18)
> -#define PORTD_PULSE_DURATION_MASK (3 << 18)
> -#define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16)
> +#define PORTD_HOTPLUG_ENABLE (1 << 20)
> +#define PORTD_PULSE_DURATION_2ms (0 << 18)
> +#define PORTD_PULSE_DURATION_4_5ms(1 << 18)
> +#define PORTD_PULSE_DURATION_6ms (2 << 18)
> +#define PORTD_PULSE_DURATION_100ms(3 << 18)
> +#define PORTD_PULSE_DURATION_MASK (3 << 18)
> +#define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
> #define PORTD_HOTPLUG_NO_DETECT (0 << 16)
> #define PORTD_HOTPLUG_SHORT_DETECT(1 << 16)
> #define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
> -#define PORTC_HOTPLUG_ENABLE(1 << 12)
> -#define PORTC_PULSE_DURATION_2ms(0)
> -#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
> -#define PORTC_PULSE_DURATION_6ms(2 << 10)
> -#define PORTC_PULSE_DURATION_100ms (3 << 10)
> -#define PORTC_PULSE_DURATION_MASK (3 << 10)
> -#define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8)
> +#define PORTC_HOTPLUG_ENABLE (1 << 12)
> +#define PORTC_PULSE_DURATION_2ms (0 << 10)
> +#define PORTC_PULSE_DURATION_4_5ms(1 << 10)
> +#define PORTC_PULSE_DURATION_6ms (2 << 10)
> +#define PORTC_PULSE_DURATION_100ms(3 << 10)
> +#define PORTC_PULSE_DURATION_MASK (3 << 10)
> +#define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
> #define PORTC_HOTPLUG_NO_DETECT (0 << 8)
> #define PORTC_HOTPLUG_SHORT_DETECT(1 << 8)
> #define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
> -#define PORTB_HOTPLUG_ENABLE(1 << 4)
> -#define PORTB_PULSE_DURATION_2ms(0)
> -#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
> -#define PORTB_PULSE_DURATION_6ms(2 << 2)
> -#define PORTB_PULSE_DURATION_100ms (3 << 2)
> -#define PORTB_PULSE_DURATION_MASK (3 << 2)
> -#define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0)
> +#define PORTB_HOTPLUG_ENABLE (1 << 4)
> +#define PORTB_PULSE_DURATION_2ms (0 << 2)
> +#define PORTB_PULSE_DURATION_4_5ms(1 << 2)
> +#define PORTB_PULSE_DURATION_6ms (2 << 2)
> +#define PORTB_PULSE_DURATION_100ms(3 << 2)
> +#define PORTB_PULSE_DURATION_MASK (3 << 2)
> +#define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
Re: [Intel-gfx] [PATCH 02/11] drm/i915; Extract intel_hpd_enabled_irqs()
2015-08-12 12:44 GMT-03:00 :
> From: Ville Syrjälä
>
> Eliminate a bunch of duplicated code that calculates the currently
> enabled HPD interrupt bits.
Nice one! I see this one also depends on a patch that's not merged
yet, so I'm not sure if I should wait for it to be merged before
continuing the review, or if you plan to send a version rebased just
on -nightly.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_irq.c | 43
> -
> 1 file changed, 21 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 8485bea..de0edbd 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3002,27 +3002,34 @@ static void cherryview_irq_preinstall(struct
> drm_device *dev)
> vlv_display_irq_reset(dev_priv);
> }
>
> +static u32 intel_hpd_enabled_irqs(struct drm_device *dev,
> + const u32 hpd[HPD_NUM_PINS])
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_encoder *encoder;
> + u32 enabled_irqs = 0;
> +
> + for_each_intel_encoder(dev, encoder)
> + if (dev_priv->hotplug.stats[encoder->hpd_pin].state ==
> HPD_ENABLED)
> + enabled_irqs |= hpd[encoder->hpd_pin];
> +
> + return enabled_irqs;
> +}
> +
> static void ibx_hpd_irq_setup(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_encoder *intel_encoder;
> - u32 hotplug_irqs, hotplug, enabled_irqs = 0;
> + u32 hotplug_irqs, hotplug, enabled_irqs;
>
> if (HAS_PCH_IBX(dev)) {
> hotplug_irqs = SDE_HOTPLUG_MASK;
> - for_each_intel_encoder(dev, intel_encoder)
> - if
> (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED)
> - enabled_irqs |=
> hpd_ibx[intel_encoder->hpd_pin];
> + enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ibx);
> } else if (HAS_PCH_SPT(dev)) {
> hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
> - for_each_intel_encoder(dev, intel_encoder)
> - if
> (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED)
> - enabled_irqs |=
> hpd_spt[intel_encoder->hpd_pin];
> + enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_spt);
> } else {
> hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
> - for_each_intel_encoder(dev, intel_encoder)
> - if
> (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED)
> - enabled_irqs |=
> hpd_cpt[intel_encoder->hpd_pin];
> + enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_cpt);
> }
>
> ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
> @@ -3051,15 +3058,10 @@ static void ibx_hpd_irq_setup(struct drm_device *dev)
> static void bxt_hpd_irq_setup(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_encoder *intel_encoder;
> - u32 hotplug_port = 0;
> + u32 hotplug_port;
> u32 hotplug_ctrl;
>
> - for_each_intel_encoder(dev, intel_encoder) {
> - if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state
> - == HPD_ENABLED)
> - hotplug_port |= hpd_bxt[intel_encoder->hpd_pin];
> - }
> + hotplug_port = intel_hpd_enabled_irqs(dev, hpd_bxt);
>
> hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK;
>
> @@ -3935,7 +3937,6 @@ static int i965_irq_postinstall(struct drm_device *dev)
> static void i915_hpd_irq_setup(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_encoder *intel_encoder;
> u32 hotplug_en;
>
> assert_spin_locked(&dev_priv->irq_lock);
> @@ -3944,9 +3945,7 @@ static void i915_hpd_irq_setup(struct drm_device *dev)
> hotplug_en &= ~HOTPLUG_INT_EN_MASK;
> /* Note HDMI and DP share hotplug bits */
> /* enable bits are the same for all generations */
> - for_each_intel_encoder(dev, intel_encoder)
> - if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state ==
> HPD_ENABLED)
> - hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
> + hotplug_en |= intel_hpd_enabled_irqs(dev, hpd_mask_i915);
> /* Programming the CRT detection parameters tends
>to generate a spurious hotplug event about three
>seconds later. So just do it once.
> --
> 2.4.6
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
_
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Support DDI lane reversal for DP
On Aug 14 2015 or thereabouts, Stéphane Marchesin wrote: > On Wed, Aug 5, 2015 at 12:34 PM, Benjamin Tissoires > wrote: > > On Jul 30 2015 or thereabouts, Sivakumar Thulasimani wrote: > >> > >> > >> On 7/29/2015 8:52 PM, Benjamin Tissoires wrote: > >> >On Jul 29 2015 or thereabouts, Sivakumar Thulasimani wrote: > >> >>why not detect reverse in intel_dp_detect/intel_hpd_pulse ? that way you > >> >>can > >> >>identify both lane count and reversal state without touching anything in > >> >>the > >> >>link training code. i am yet to upstream my changes for CHT that i can > >> >>share > >> >>if required that does the same in intel_dp_detect without touching any > >> >>line > >> >>in link training path. > >> >With my current limited knowledge of the dp hotplug (and i915 driver) I > >> >am not sure we could detect the reversed state without trying to train 1 > >> >lane only. I'd be glad to look at your changes and test them on my > >> >system if you think that could help having a cleaner solution. > >> > > >> >Cheers, > >> >Benjamin > >> No, what i recommended was to do link training but in intel_dp_detect. > >> Since > >> USB Type C cable > >> also has its own lane count restriction (it can have different lane count > >> than the one supported > >> by panel) you might have to figure that out as well. so both reversal and > >> lane count detection > >> can be done outside the modeset path and keep the code free of type C > >> changes outside > >> detection path. > >> > >> Please find below the code to do the same. Do not waste time trying to > >> apply > >> this directly on > >> nightly since this is based on a local tree and because this is pre- atomic > >> changes code, so you > >> might have to modify chv_upfront_link_train to work on top of the latest > >> nightly code. we > >> are supposed to upstream this and is in my todo list. > >> > > > > [original patch snipped...] > > > > Hi Sivakumar, > > > > So I managed to manually re-apply your patch on top of > > drm-intel-nightly, and tried to port it to make Broadwell working too. > > It works OK if the system is already boot without any external DP used. > > In this case, the detection works and I can see my external monitor > > working properly. > > > > However, if the monitor is cold plugged, the cpu/GPU hangs and I can not > > understand why. I think I enabled all that is mentioned in the PRM to be > > able to train the DP link, but I am obviously missing something else. > > Can you have a look? > > > > Hi Benjamin, > > I would recommend against this approach. Some adapters will claim that > they recovered a clock even when it isn't on the lanes you enabled, > which means that the reversal detection doesn't always work. The only > reliable way to do this is to go talk to the Chrome OS EC (you can > find these patches later in the Chrome OS tree). It's not as generic, > but we might be able to abstract that logic, maybe. > Hi Stéphane, This is a very good news. I was afraid we would not have access to the hardware controller because the Intel controller hub spec was not public. I will try to have a look at it, but the latest chromeos branch (3.18) seems to differ quite a lot from the upstream one. Anyway, fingers crossed. Cheers, Benjamin ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Read sink_count dpcd always for short hpd
On 8/17/2015 5:39 PM, Jani Nikula wrote:
On Mon, 17 Aug 2015, Sivakumar Thulasimani
wrote:
From: "Thulasimani,Sivakumar"
Compliance test 4.2.2.8 requires driver to read the sink_count for
short pulse interrupt even when the panel is not enabled.
This patch performs the following
a) reading sink_count by reusing intel_dp_detect_dpcd
instead of using intel_dp_get_dpcd
b) moving crtc enabled checks post sink_count read call
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 117 ---
1 file changed, 59 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b905c19..e4de8e5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4342,6 +4342,56 @@ go_again:
return -EINVAL;
}
+/* XXX this is probably wrong for multiple downstream ports */
+static enum drm_connector_status
+intel_dp_detect_dpcd(struct intel_dp *intel_dp)
+{
+ uint8_t *dpcd = intel_dp->dpcd;
+ uint8_t type;
+
+ if (!intel_dp_get_dpcd(intel_dp))
+ return connector_status_disconnected;
+
+ /* if there's no downstream port, we're done */
+ if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
+ return connector_status_connected;
+
+ /* If we're HPD-aware, SINK_COUNT changes dynamically */
+ if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
+ intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
+ uint8_t reg;
+
+ if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
+ ®, 1) < 0)
+ return connector_status_unknown;
+
+ return DP_GET_SINK_COUNT(reg) ? connector_status_connected
+ : connector_status_disconnected;
+ }
+
+ /* If no HPD, poke DDC gently */
+ if (drm_probe_ddc(&intel_dp->aux.ddc))
+ return connector_status_connected;
+
+ /* Well we tried, say unknown for unreliable port types */
+ if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
+ type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
+ if (type == DP_DS_PORT_TYPE_VGA ||
+ type == DP_DS_PORT_TYPE_NON_EDID)
+ return connector_status_unknown;
+ } else {
+ type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
+ DP_DWN_STRM_PORT_TYPE_MASK;
+ if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
+ type == DP_DWN_STRM_PORT_TYPE_OTHER)
+ return connector_status_unknown;
+ }
+
+ /* Anything else is out of spec, warn and ignore */
+ DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
+ return connector_status_disconnected;
+}
Please either a) just add a forward declaration for
intel_dp_detect_dpcd, or b) add a separate non-functional prep patch
that moves the function around. Please don't combine code movement with
functional changes.
BR,
Jani.
uploaded V2 of the patch with forward declaration.
+
/*
* According to DP spec
* 5.1.2:
@@ -4362,21 +4412,22 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
- if (!intel_encoder->base.crtc)
+ /* 4.2.2.8 requires source to read link_status, 0 - 12 DPCD &
+* sink_count even for short pulse irrespective of the sink is
+* in use or not
+*/
+ if (!intel_dp_get_link_status(intel_dp, link_status))
return;
- if (!to_intel_crtc(intel_encoder->base.crtc)->active)
+ /* reuse to read both 0 - 12 DPCD & sink_count */
+ if (intel_dp_detect_dpcd(intel_dp) != connector_status_connected)
return;
- /* Try to read receiver status if the link appears to be up */
- if (!intel_dp_get_link_status(intel_dp, link_status)) {
+ if (!intel_encoder->base.crtc)
return;
- }
- /* Now read the DPCD to see if it's actually running */
- if (!intel_dp_get_dpcd(intel_dp)) {
+ if (!to_intel_crtc(intel_encoder->base.crtc)->active)
return;
- }
/* Try to read the source of the interrupt */
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
@@ -4401,56 +4452,6 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
}
}
-/* XXX this is probably wrong for multiple downstream ports */
-static enum drm_connector_status
-intel_dp_detect_dpcd(struct intel_dp *intel_dp)
-{
- uint8_t *dpcd = intel_dp->dpcd;
- uint8_t type;
-
- if (!intel_dp_get_dpcd(intel_dp))
- return connector_status_disconnected;
-
- /* if there's no downstream port, we're done */
- if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
- return connector_status_co
Re: [Intel-gfx] [PATCH 4/4] drm/i915: fix link rates reported for SKL
On 8/17/2015 6:11 PM, Ville Syrjälä wrote:
On Mon, Aug 17, 2015 at 05:45:11PM +0530, Sivakumar Thulasimani wrote:
From: "Thulasimani,Sivakumar"
This patch fixes the bug that SKL SKUs before B0 might return
HBR2 as supported even though it is not supposed to be enabled
on such platforms.
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 03523b3..963fdae 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1224,21 +1224,23 @@ static bool intel_dp_is_hbr2_supported(struct
drm_device *dev)
static int
intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
{
+ int size = 0;
if (IS_BROXTON(dev)) {
*source_rates = bxt_rates;
- return ARRAY_SIZE(bxt_rates);
+ size = ARRAY_SIZE(bxt_rates);
} else if (IS_SKYLAKE(dev)) {
*source_rates = skl_rates;
- return ARRAY_SIZE(skl_rates);
+ size = ARRAY_SIZE(skl_rates);
+ } else {
+ *source_rates = default_rates;
+ size = ARRAY_SIZE(default_rates);
}
- *source_rates = default_rates;
-
/* This depends on the fact that 5.4 is last value in the array */
if (intel_dp_is_hbr2_supported(dev))
- return (DP_LINK_BW_5_4 >> 3) + 1;
+ return size;
else
- return (DP_LINK_BW_2_7 >> 3) + 1;
+ return size - 1;
Maybe we should use rate_to_index() here? Should be a bit more
future proof for when we get HBR3. So, perhaps something like this?
{
...
*source_rates = bxt_rates;
size_rates = ARRAY_SIZE(bxt_rates);
...
if (intel_dp_is_hbr2_supported)
max_rate = 54;
else
max_rate = 27;
size = rate_to_index(max_rate, *source_rates) + 1;
if (WARN_ON(size > size_rates))
size = size_rates;
return size;
}
But that could be a followup patch.
Otherwise the series looks good so:
Reviewed-by: Ville Syrjälä
thanks for the review :)
}
static void
--
1.7.9.5
--
regards,
Sivakumar
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/4] Revert "drm/i915: Add eDP intermediate frequencies for CHV"
From: "Thulasimani,Sivakumar"
This reverts
commit fe51bfb95c996733150c44d21e1c9f4b6322a326.
Author: Ville Syrjälä
Date: Thu Mar 12 17:10:38 2015 +0200
CHV does not support intermediate frequencies so reverting the
patch that added it in the first place
Reviewed-by: Ville Syrjälä
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c |6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b905c19..bfe0567 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -95,9 +95,6 @@ static const int bxt_rates[] = { 162000, 216000, 243000,
27,
324000, 432000, 54 };
static const int skl_rates[] = { 162000, 216000, 27,
324000, 432000, 54 };
-static const int chv_rates[] = { 162000, 202500, 21, 216000,
-243000, 27, 324000, 405000,
-42, 432000, 54 };
static const int default_rates[] = { 162000, 27, 54 };
/**
@@ -1219,9 +1216,6 @@ intel_dp_source_rates(struct drm_device *dev, const int
**source_rates)
} else if (IS_SKYLAKE(dev)) {
*source_rates = skl_rates;
return ARRAY_SIZE(skl_rates);
- } else if (IS_CHERRYVIEW(dev)) {
- *source_rates = chv_rates;
- return ARRAY_SIZE(chv_rates);
}
*source_rates = default_rates;
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/4] drm/i915: fix link rates reported for SKL
From: "Thulasimani,Sivakumar"
This patch fixes the bug that SKL SKUs before B0 might return
HBR2 as supported even though it is not supposed to be enabled
on such platforms.
v2: optimize if else condition (Jani)
Reviewed-by: Ville Syrjälä
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8bc6361..32bf961 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1224,21 +1224,24 @@ static bool intel_dp_source_supports_hbr2(struct
drm_device *dev)
static int
intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
{
+ int size;
+
if (IS_BROXTON(dev)) {
*source_rates = bxt_rates;
- return ARRAY_SIZE(bxt_rates);
+ size = ARRAY_SIZE(bxt_rates);
} else if (IS_SKYLAKE(dev)) {
*source_rates = skl_rates;
- return ARRAY_SIZE(skl_rates);
+ size = ARRAY_SIZE(skl_rates);
+ } else {
+ *source_rates = default_rates;
+ size = ARRAY_SIZE(default_rates);
}
- *source_rates = default_rates;
-
/* This depends on the fact that 5.4 is last value in the array */
- if (intel_dp_source_supports_hbr2(dev))
- return (DP_LINK_BW_5_4 >> 3) + 1;
- else
- return (DP_LINK_BW_2_7 >> 3) + 1;
+ if (!intel_dp_source_supports_hbr2(dev))
+ size--;
+
+ return size;
}
static void
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/4] drm/i915: remove HBR2 from chv supported list
From: "Thulasimani,Sivakumar" This patch removes 5.4Gbps from supported link rate for CHV since it is not supported in it. v2: change the ordering for better readability (Ville) Reviewed-by: Ville Syrjälä Signed-off-by: Sivakumar Thulasimani --- drivers/gpu/drm/i915/intel_dp.c |7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index bfe0567..475d8cb 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1220,11 +1220,12 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates) *source_rates = default_rates; + /* WaDisableHBR2:skl */ if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) - /* WaDisableHBR2:skl */ return (DP_LINK_BW_2_7 >> 3) + 1; - else if (INTEL_INFO(dev)->gen >= 8 || - (IS_HASWELL(dev) && !IS_HSW_ULX(dev))) + + if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || + (INTEL_INFO(dev)->gen >= 9)) return (DP_LINK_BW_5_4 >> 3) + 1; else return (DP_LINK_BW_2_7 >> 3) + 1; -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/4] drm/i915: Avoid TP3 on CHV
From: "Thulasimani,Sivakumar"
This patch removes TP3 support on CHV since there is no support
for HBR2 on this platform.
v2: rename the function to indicate it checks source rates (Jani)
Reviewed-by: Ville Syrjälä
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 475d8cb..8bc6361 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1207,6 +1207,20 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int
**sink_rates)
return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
}
+static bool intel_dp_source_supports_hbr2(struct drm_device *dev)
+{
+ /* WaDisableHBR2:skl */
+ if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
+ return false;
+
+ if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
+ (INTEL_INFO(dev)->gen >= 9))
+ return true;
+ else
+ return false;
+}
+
+
static int
intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
{
@@ -1220,12 +1234,8 @@ intel_dp_source_rates(struct drm_device *dev, const int
**source_rates)
*source_rates = default_rates;
- /* WaDisableHBR2:skl */
- if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
- return (DP_LINK_BW_2_7 >> 3) + 1;
-
- if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
- (INTEL_INFO(dev)->gen >= 9))
+ /* This depends on the fact that 5.4 is last value in the array */
+ if (intel_dp_source_supports_hbr2(dev))
return (DP_LINK_BW_5_4 >> 3) + 1;
else
return (DP_LINK_BW_2_7 >> 3) + 1;
@@ -3926,7 +3936,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
/* Training Pattern 3 support, both source and sink */
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
- (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
+ intel_dp_source_supports_hbr2(dev)) {
intel_dp->use_tps3 = true;
DRM_DEBUG_KMS("Displayport TPS3 supported\n");
} else
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/4] HBR2 cleanup for CHV/SKL V2
From: "Thulasimani,Sivakumar" This patch series cleans up the code to remove HBR2 support for CHV since it is not supported on CHV. Also fixes a bug for SKL platforms where HBR2 is not supported. V2: Added RB from Ville Syrjälä patches 3 & 4 updated with comments from Jani. Thulasimani,Sivakumar (4): Revert "drm/i915: Add eDP intermediate frequencies for CHV" drm/i915: remove HBR2 from chv supported list drm/i915: Avoid TP3 on CHV drm/i915: fix link rates reported for SKL drivers/gpu/drm/i915/intel_dp.c | 43 +++ 1 file changed, 25 insertions(+), 18 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/4] drm/i915: fix link rates reported for SKL
On 8/17/2015 5:59 PM, Jani Nikula wrote:
On Mon, 17 Aug 2015, Sivakumar Thulasimani
wrote:
From: "Thulasimani,Sivakumar"
This patch fixes the bug that SKL SKUs before B0 might return
HBR2 as supported even though it is not supposed to be enabled
on such platforms.
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 03523b3..963fdae 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1224,21 +1224,23 @@ static bool intel_dp_is_hbr2_supported(struct
drm_device *dev)
static int
intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
{
+ int size = 0;
No need to initialize.
if (IS_BROXTON(dev)) {
*source_rates = bxt_rates;
- return ARRAY_SIZE(bxt_rates);
+ size = ARRAY_SIZE(bxt_rates);
} else if (IS_SKYLAKE(dev)) {
*source_rates = skl_rates;
- return ARRAY_SIZE(skl_rates);
+ size = ARRAY_SIZE(skl_rates);
+ } else {
+ *source_rates = default_rates;
+ size = ARRAY_SIZE(default_rates);
}
- *source_rates = default_rates;
-
/* This depends on the fact that 5.4 is last value in the array */
if (intel_dp_is_hbr2_supported(dev))
- return (DP_LINK_BW_5_4 >> 3) + 1;
+ return size;
else
- return (DP_LINK_BW_2_7 >> 3) + 1;
+ return size - 1;
/* This depends on the fact that 5.4 is last value in the array */
if (!intel_dp_source_supports_hbr2(dev))
size--;
return size;
uploaded v2 of patches 3 & 4.
thanks for the review :)
}
static void
--
1.7.9.5
--
regards,
Sivakumar
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] drm/i915: Avoid TP3 on CHV
On Tue, 18 Aug 2015, Sivakumar Thulasimani
wrote:
> From: "Thulasimani,Sivakumar"
>
> This patch removes TP3 support on CHV since there is no support
> for HBR2 on this platform.
>
> v2: rename the function to indicate it checks source rates (Jani)
>
> Reviewed-by: Ville Syrjälä
> Signed-off-by: Sivakumar Thulasimani
> ---
> drivers/gpu/drm/i915/intel_dp.c | 24 +---
> 1 file changed, 17 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 475d8cb..8bc6361 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1207,6 +1207,20 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const
> int **sink_rates)
> return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
> }
>
> +static bool intel_dp_source_supports_hbr2(struct drm_device *dev)
> +{
> + /* WaDisableHBR2:skl */
> + if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
> + return false;
> +
> + if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
> + (INTEL_INFO(dev)->gen >= 9))
> + return true;
> + else
> + return false;
> +}
> +
> +
> static int
> intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
> {
> @@ -1220,12 +1234,8 @@ intel_dp_source_rates(struct drm_device *dev, const
> int **source_rates)
>
> *source_rates = default_rates;
>
> - /* WaDisableHBR2:skl */
> - if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
> - return (DP_LINK_BW_2_7 >> 3) + 1;
> -
> - if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
> - (INTEL_INFO(dev)->gen >= 9))
> + /* This depends on the fact that 5.4 is last value in the array */
> + if (intel_dp_source_supports_hbr2(dev))
> return (DP_LINK_BW_5_4 >> 3) + 1;
> else
> return (DP_LINK_BW_2_7 >> 3) + 1;
> @@ -3926,7 +3936,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
> /* Training Pattern 3 support, both source and sink */
> if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
> intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
> - (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
> + intel_dp_source_supports_hbr2(dev)) {
hbr2 is not the same as tps3, is it? It's possible to use tps3 without
using hbr2, right?
BR,
Jani.
> intel_dp->use_tps3 = true;
> DRM_DEBUG_KMS("Displayport TPS3 supported\n");
> } else
> --
> 1.7.9.5
>
--
Jani Nikula, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 3/4] ALSA: hda - display audio call sync_audio_rate callback
From: Libin Yang
For display audio, call the sync_audio_rate callback function
to do the synchronization between gfx driver and audio driver.
Signed-off-by: Libin Yang
Reviewed-by: Takashi Iwai
---
sound/pci/hda/patch_hdmi.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
index a97db5f..1668868 100644
--- a/sound/pci/hda/patch_hdmi.c
+++ b/sound/pci/hda/patch_hdmi.c
@@ -1770,6 +1770,16 @@ static bool check_non_pcm_per_cvt(struct hda_codec
*codec, hda_nid_t cvt_nid)
return non_pcm;
}
+/* There is a fixed mapping between audio pin node and display port
+ * on current Intel platforms:
+ * Pin Widget 5 - PORT B (port = 1 in i915 driver)
+ * Pin Widget 6 - PORT C (port = 2 in i915 driver)
+ * Pin Widget 7 - PORT D (port = 3 in i915 driver)
+ */
+static int intel_pin2port(hda_nid_t pin_nid)
+{
+ return pin_nid - 4;
+}
/*
* HDMI callbacks
@@ -1786,6 +1796,8 @@ static int generic_hdmi_playback_pcm_prepare(struct
hda_pcm_stream *hinfo,
int pin_idx = hinfo_to_pin_index(codec, hinfo);
struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
hda_nid_t pin_nid = per_pin->pin_nid;
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct i915_audio_component *acomp = codec->bus->core.audio_component;
bool non_pcm;
int pinctl;
@@ -1802,6 +1814,13 @@ static int generic_hdmi_playback_pcm_prepare(struct
hda_pcm_stream *hinfo,
intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
}
+ /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
+ /* Todo: add DP1.2 MST audio support later */
+ if (acomp && acomp->ops && acomp->ops->sync_audio_rate)
+ acomp->ops->sync_audio_rate(acomp->dev,
+ intel_pin2port(pin_nid),
+ runtime->rate);
+
non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
mutex_lock(&per_pin->lock);
per_pin->channels = substream->runtime->channels;
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 2/4] drm/i915: implement sync_audio_rate callback
From: Libin Yang
HDMI audio may not work at some frequencies
with the HW provided N/CTS.
This patch sets the proper N value for the
given audio sample rate at the impacted frequencies.
At other frequencies, it will use the N/CTS value
which HW provides.
Signed-off-by: Libin Yang
---
drivers/gpu/drm/i915/intel_audio.c | 116 +
1 file changed, 116 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index dc32cf4..9d6ba84 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -68,6 +68,31 @@ static const struct {
{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
};
+/* HDMI N/CTS table */
+#define TMDS_297M 297000
+#define TMDS_296M DIV_ROUND_UP(297000 * 1000, 1001)
+static const struct {
+ int sample_rate;
+ int clock;
+ int n;
+ int cts;
+} aud_ncts[] = {
+ { 44100, TMDS_296M, 4459, 234375 },
+ { 44100, TMDS_297M, 4704, 247500 },
+ { 48000, TMDS_296M, 5824, 281250 },
+ { 48000, TMDS_297M, 5120, 247500 },
+ { 32000, TMDS_296M, 5824, 421875 },
+ { 32000, TMDS_297M, 3072, 222750 },
+ { 88200, TMDS_296M, 8918, 234375 },
+ { 88200, TMDS_297M, 9408, 247500 },
+ { 96000, TMDS_296M, 11648, 281250 },
+ { 96000, TMDS_297M, 10240, 247500 },
+ { 176400, TMDS_296M, 17836, 234375 },
+ { 176400, TMDS_297M, 18816, 247500 },
+ { 44100, TMDS_296M, 23296, 281250 },
+ { 44100, TMDS_297M, 20480, 247500 },
+};
+
/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
{
@@ -90,6 +115,31 @@ static u32 audio_config_hdmi_pixel_clock(struct
drm_display_mode *mode)
return hdmi_audio_clock[i].config;
}
+static int audio_config_get_n(struct drm_display_mode *mode, int rate)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
+ if ((rate == aud_ncts[i].sample_rate) &&
+ (mode->clock == aud_ncts[i].clock)) {
+ return aud_ncts[i].n;
+ }
+ }
+ return 0;
+}
+
+/* check whether N/CTS/M need be set manually */
+static bool audio_rate_need_prog(struct intel_crtc *crtc,
+ struct drm_display_mode *mode)
+{
+ if (((mode->clock == TMDS_297M) ||
+(mode->clock == TMDS_296M)) &&
+ intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
+ return true;
+ else
+ return false;
+}
+
static bool intel_eld_uptodate(struct drm_connector *connector,
int reg_eldv, uint32_t bits_eldv,
int reg_elda, uint32_t bits_elda,
@@ -514,12 +564,78 @@ static int i915_audio_component_get_cdclk_freq(struct
device *dev)
return ret;
}
+static int i915_audio_component_sync_audio_rate(struct device *dev,
+ int port, int rate)
+{
+ struct drm_i915_private *dev_priv = dev_to_i915(dev);
+ struct drm_device *drm_dev = dev_priv->dev;
+ struct intel_encoder *intel_encoder;
+ struct intel_digital_port *intel_dig_port;
+ struct intel_crtc *crtc;
+ struct drm_display_mode *mode;
+ enum pipe pipe = -1;
+ u32 tmp;
+ int n_low, n_up, n;
+
+ /* 1. get the pipe */
+ for_each_intel_encoder(drm_dev, intel_encoder) {
+ intel_dig_port = enc_to_dig_port(&intel_encoder->base);
+ if (port == intel_dig_port->port) {
+ crtc = to_intel_crtc(intel_encoder->base.crtc);
+ if (!crtc ||
+ !intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
+ continue;
+ pipe = crtc->pipe;
+ break;
+ }
+ }
+
+ if (pipe == INVALID_PIPE) {
+ DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port));
+ return -ENODEV;
+ }
+ DRM_DEBUG_KMS("pipe %c connects port %c\n",
+ pipe_name(pipe), port_name(port));
+ mode = &crtc->config->base.adjusted_mode;
+
+ /* 2. check whether to set the N/CTS/M manually or not */
+ if (!audio_rate_need_prog(crtc, mode)) {
+ tmp = I915_READ(HSW_AUD_CFG(pipe));
+ tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
+ I915_WRITE(HSW_AUD_CFG(pipe), tmp);
+ return 0;
+ }
+
+ n = audio_config_get_n(mode, rate);
+ if (n == 0) {
+ DRM_DEBUG_KMS("Using automatic mode for N value on port %c\n",
+ port_name(port));
+ tmp = I915_READ(HSW_AUD_CFG(pipe));
+ tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
+ I915_WRITE(HSW_AUD_CFG(pipe), tmp);
+ return 0;
+ }
+ n_low
[Intel-gfx] [PATCH v4 1/4] drm/i915: Add audio sync_audio_rate callback
From: Libin Yang
Add the sync_audio_rate callback.
With the callback, audio driver can trigger
i915 driver to set the proper N/CTS or N/M
based on different sample rates.
Signed-off-by: Libin Yang
---
include/drm/i915_component.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index c9a8b64..aabebcb 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -33,6 +33,7 @@ struct i915_audio_component {
void (*put_power)(struct device *);
void (*codec_wake_override)(struct device *, bool enable);
int (*get_cdclk_freq)(struct device *);
+ int (*sync_audio_rate)(struct device *, int port, int rate);
} *ops;
};
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 4/4] drm/i915: set proper N/CTS in modeset
From: Libin Yang
When modeset occurs and the TMDS frequency is set to some
speical values, the N/CTS need to be set manually if audio
is playing.
Signed-off-by: Libin Yang
---
drivers/gpu/drm/i915/i915_reg.h| 8
drivers/gpu/drm/i915/intel_audio.c | 40 +-
2 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6786e94..122b5bd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7035,6 +7035,8 @@ enum skl_disp_power_wells {
_HSW_AUD_MISC_CTRL_A, \
_HSW_AUD_MISC_CTRL_B)
+#define HSW_AUD_PIPE_CONN_SEL_CTRL 0x650ac
+
#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
#define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
@@ -7049,6 +7051,12 @@ enum skl_disp_power_wells {
_HSW_AUD_DIG_CNVT_2)
#define DIP_PORT_SEL_MASK 0x3
+#define _HSW_AUD_STR_DESC_10x65084
+#define _HSW_AUD_STR_DESC_20x65184
+#define AUD_STR_DESC(pipe) _PIPE(pipe, \
+_HSW_AUD_STR_DESC_1, \
+_HSW_AUD_STR_DESC_2)
+
#define _HSW_AUD_EDID_DATA_A 0x65050
#define _HSW_AUD_EDID_DATA_B 0x65150
#define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index 9d6ba84..b756309 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -140,6 +140,27 @@ static bool audio_rate_need_prog(struct intel_crtc *crtc,
return false;
}
+static int audio_config_get_rate(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
+{
+ uint32_t tmp;
+ int cvt_idx;
+ int base_rate, mul, div, rate;
+
+ tmp = I915_READ(HSW_AUD_PIPE_CONN_SEL_CTRL);
+ cvt_idx = (tmp >> (pipe * 8)) & 0xff;
+ tmp = I915_READ(AUD_STR_DESC(cvt_idx));
+ base_rate = tmp & (1 << 14);
+ if (base_rate == 0)
+ rate = 48000;
+ else
+ rate = 44100;
+ mul = (tmp & (0x7 << 11)) + 1;
+ div = (tmp & (0x7 << 8)) + 1;
+ rate = rate * mul / div;
+ return rate;
+}
+
static bool intel_eld_uptodate(struct drm_connector *connector,
int reg_eldv, uint32_t bits_eldv,
int reg_elda, uint32_t bits_elda,
@@ -261,6 +282,8 @@ static void hsw_audio_codec_enable(struct drm_connector
*connector,
const uint8_t *eld = connector->eld;
uint32_t tmp;
int len, i;
+ int n_low, n_up, n;
+ int rate;
DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
pipe_name(pipe), drm_eld_size(eld));
@@ -296,12 +319,27 @@ static void hsw_audio_codec_enable(struct drm_connector
*connector,
/* Enable timestamps */
tmp = I915_READ(HSW_AUD_CFG(pipe));
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
- tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
tmp |= AUD_CONFIG_N_VALUE_INDEX;
else
tmp |= audio_config_hdmi_pixel_clock(mode);
+
+ tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
+ if (audio_rate_need_prog(intel_crtc, mode)) {
+ rate = audio_config_get_rate(dev_priv, pipe);
+ n = audio_config_get_n(mode, rate);
+ if (n != 0) {
+ n_low = n & 0xfff;
+ n_up = (n >> 12) & 0xff;
+ tmp &= ~(AUD_CONFIG_UPPER_N_MASK |
+AUD_CONFIG_LOWER_N_MASK);
+ tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) |
+ (n_low << AUD_CONFIG_LOWER_N_SHIFT) |
+ AUD_CONFIG_N_PROG_ENABLE);
+ }
+ }
+
I915_WRITE(HSW_AUD_CFG(pipe), tmp);
}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 2/4] drm/i915: implement sync_audio_rate callback
On Mon, 17 Aug 2015, "Yang, Libin" wrote:
> Hi Jani
>
>> -Original Message-
>> From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>> Sent: Monday, August 17, 2015 8:21 PM
>> To: Yang, Libin; alsa-de...@alsa-project.org; ti...@suse.de; intel-
>> g...@lists.freedesktop.org; daniel.vet...@ffwll.ch
>> Cc: Yang, Libin
>> Subject: Re: [PATCH v3 2/4] drm/i915: implement sync_audio_rate
>> callback
>>
>> On Mon, 17 Aug 2015, libin.y...@intel.com wrote:
>> > From: Libin Yang
>> >
>> > HDMI audio may not work at some frequencies
>> > with the HW provided N/CTS.
>> >
>> > This patch sets the proper N value for the
>> > given audio sample rate at the impacted frequencies.
>> > At other frequencies, it will use the N/CTS value
>> > which HW provides.
>> >
>> > Signed-off-by: Libin Yang
>> > ---
>> > drivers/gpu/drm/i915/intel_audio.c | 117
>> +
>> > 1 file changed, 117 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_audio.c
>> b/drivers/gpu/drm/i915/intel_audio.c
>> > index dc32cf4..27add6a 100644
>> > --- a/drivers/gpu/drm/i915/intel_audio.c
>> > +++ b/drivers/gpu/drm/i915/intel_audio.c
>> > @@ -68,6 +68,31 @@ static const struct {
>> >{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
>> > };
>> >
>> > +/* HDMI N/CTS table */
>> > +#define TMDS_297M 297000
>> > +#define TMDS_296M DIV_ROUND_UP(297000 * 1000, 1001)
>> > +static const struct {
>> > + int sample_rate;
>> > + int clock;
>> > + int n;
>> > + int cts;
>> > +} aud_ncts[] = {
>> > + { 44100, TMDS_296M, 4459, 234375 },
>> > + { 44100, TMDS_297M, 4704, 247500 },
>> > + { 48000, TMDS_296M, 5824, 281250 },
>> > + { 48000, TMDS_297M, 5120, 247500 },
>> > + { 32000, TMDS_296M, 5824, 421875 },
>> > + { 32000, TMDS_297M, 3072, 222750 },
>> > + { 88200, TMDS_296M, 8918, 234375 },
>> > + { 88200, TMDS_297M, 9408, 247500 },
>> > + { 96000, TMDS_296M, 11648, 281250 },
>> > + { 96000, TMDS_297M, 10240, 247500 },
>> > + { 176400, TMDS_296M, 17836, 234375 },
>> > + { 176400, TMDS_297M, 18816, 247500 },
>> > + { 44100, TMDS_296M, 23296, 281250 },
>> > + { 44100, TMDS_297M, 20480, 247500 },
>> > +};
>> > +
>> > /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
>> > static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode
>> *mode)
>> > {
>> > @@ -90,6 +115,31 @@ static u32
>> audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
>> >return hdmi_audio_clock[i].config;
>> > }
>> >
>> > +static int audio_config_get_n(struct drm_display_mode *mode, int
>> rate)
>> > +{
>> > + int i;
>> > +
>> > + for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
>> > + if ((rate == aud_ncts[i].sample_rate) &&
>> > + (mode->clock == aud_ncts[i].clock)) {
>> > + return aud_ncts[i].n;
>> > + }
>> > + }
>> > + return 0;
>> > +}
>> > +
>> > +/* check whether N/CTS/M need be set manually */
>> > +static bool audio_rate_need_prog(struct intel_crtc *crtc,
>> > + struct drm_display_mode
>> *mode)
>> > +{
>> > + if (((mode->clock == TMDS_297M) ||
>> > + (mode->clock == TMDS_296M)) &&
>> > + intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
>> > + return true;
>> > + else
>> > + return false;
>> > +}
>> > +
>> > static bool intel_eld_uptodate(struct drm_connector *connector,
>> > int reg_eldv, uint32_t bits_eldv,
>> > int reg_elda, uint32_t bits_elda,
>> > @@ -514,12 +564,79 @@ static int
>> i915_audio_component_get_cdclk_freq(struct device *dev)
>> >return ret;
>> > }
>> >
>> > +static int i915_audio_component_sync_audio_rate(struct device
>> *dev,
>> > + int port, int rate)
>> > +{
>> > + struct drm_i915_private *dev_priv = dev_to_i915(dev);
>> > + struct drm_device *drm_dev = dev_priv->dev;
>> > + struct intel_encoder *intel_encoder;
>> > + struct intel_digital_port *intel_dig_port;
>> > + struct intel_crtc *crtc;
>> > + struct drm_display_mode *mode;
>> > + enum pipe pipe = -1;
>> > + u32 tmp;
>> > + int n_low, n_up, n;
>> > +
>> > + /* 1. get the pipe */
>> > + for_each_intel_encoder(drm_dev, intel_encoder) {
>> > + intel_dig_port = enc_to_dig_port(&intel_encoder-
>> >base);
>>
>> Mmmh, not all encoders are digital ports. enc_to_dig_port does a
>> container_of, so you can't just check for NULL either. IOW, you need
>> to
>> check the encoder->type (and you only care about HDMI here).
>
> Do you mean it should be:
> if (!crtc || !intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
No, just check for intel_encoder->type as the first thing in the loop,
and continue if it isn't HDMI.
if (intel_encoder->type != INTEL_OUTPUT_HDMI)
continue;
>
> regards,
> Libin
>
>>
>> > + if (port == intel_dig_port->port) {
>> > + crtc = to_intel_crtc(intel_encoder->base.crtc);
>> > + if (!crtc) {
>> > +
Re: [Intel-gfx] [PATCH 3/4] drm/i915: Avoid TP3 on CHV
On 8/18/2015 12:14 PM, Jani Nikula wrote:
On Tue, 18 Aug 2015, Sivakumar Thulasimani
wrote:
From: "Thulasimani,Sivakumar"
This patch removes TP3 support on CHV since there is no support
for HBR2 on this platform.
v2: rename the function to indicate it checks source rates (Jani)
Reviewed-by: Ville Syrjälä
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 475d8cb..8bc6361 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1207,6 +1207,20 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int
**sink_rates)
return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
}
+static bool intel_dp_source_supports_hbr2(struct drm_device *dev)
+{
+ /* WaDisableHBR2:skl */
+ if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
+ return false;
+
+ if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
+ (INTEL_INFO(dev)->gen >= 9))
+ return true;
+ else
+ return false;
+}
+
+
static int
intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
{
@@ -1220,12 +1234,8 @@ intel_dp_source_rates(struct drm_device *dev, const int
**source_rates)
*source_rates = default_rates;
- /* WaDisableHBR2:skl */
- if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
- return (DP_LINK_BW_2_7 >> 3) + 1;
-
- if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
- (INTEL_INFO(dev)->gen >= 9))
+ /* This depends on the fact that 5.4 is last value in the array */
+ if (intel_dp_source_supports_hbr2(dev))
return (DP_LINK_BW_5_4 >> 3) + 1;
else
return (DP_LINK_BW_2_7 >> 3) + 1;
@@ -3926,7 +3936,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
/* Training Pattern 3 support, both source and sink */
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
- (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
+ intel_dp_source_supports_hbr2(dev)) {
hbr2 is not the same as tps3, is it? It's possible to use tps3 without
using hbr2, right?
BR,
Jani.
Yes, TP3 can be supported on panels that does not support HBR2 as well, but
the check here is for hardware capability. Intel platforms that does not
support
HBR2 cannot support TP3 as well, so we should treat them both the same.
(the only exception here seems to be SKL
intel_dp->use_tps3 = true;
DRM_DEBUG_KMS("Displayport TPS3 supported\n");
} else
--
1.7.9.5
--
regards,
Sivakumar
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
