Re: [Intel-gfx] [PATCH] drm/i915: Fix big cursors on snb
Hi Art,
Indeed my patch looks fishy and it's because this isn't the code I've
tested the entire night :(
The one that works simply disables lp1+ wm levels. Which is a bit an
oversized hammer really. Do you have any ideas for w/a or smaller
tricks I could try? I did try just blantantly multiplying wm levels a
bit but that didn't help. At least not the few things I've tried.
Still only seen this on snb thus far.
Thanks, Daniel
On Mon, Mar 2, 2015 at 8:39 PM, Runyan, Arthur J
wrote:
> I think your ilk_wm_method2 is busted. Method 2 should always give more than
> one full line, making this 1 line redundant.
>
>
> -Original Message-
> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch]
> Sent: Monday, March 02, 2015 9:09 AM
> To: Intel Graphics Development; Runyan, Arthur J
> Cc: Daniel Vetter; Ville Syrjälä; Roper, Matthew D; Paulo Zanoni; Vetter,
> Daniel
> Subject: Re: [PATCH] drm/i915: Fix big cursors on snb
>
> Forgotten to cc Art as fyi.
> -Daniel
>
> On Mon, Mar 2, 2015 at 5:35 PM, Daniel Vetter wrote:
>> My snb seemed somewhat unhappy with 256x256 cursors and failed all the
>> relevant kms_cursor_crc subtests sporadically, including logging cpu
>> fifo underruns. Smaller cursor work perfectly with a failure rate at
>> least 1000x less (got bored after running tests for days).
>>
>> After some playing around with impressive hammers Ville suggested to
>> increase the watermarks to at least cover a full cursor line. It seems
>> to work thus far. This means that for lp wms we now required 1/4th of
>> the fifo for 256 wide cursors, and much less on gen7+. Hence fetches
>> should still be nice&big. Therefore I expect very little power impact
>> and decided to just do this everywhere, even though I've only seen
>> this on my snb laptop. Especially since Ville is thinking about
>> similar changes for the gmch wm code. skl separate wm code and also
>> completely new plane hw, so hopefully isn't affected.
>>
>> Cc: Ville Syrjälä
>> Cc: Matt Roper
>> Cc: Paulo Zanoni
>> Testcase: igt/kms_cursor_crc/*-256x256-*
>> Signed-off-by: Daniel Vetter
>> ---
>> drivers/gpu/drm/i915/intel_pm.c | 17 -
>> 1 file changed, 12 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c
>> b/drivers/gpu/drm/i915/intel_pm.c
>> index 7dcb5b60600b..7e97a30bd6c0 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm[Art] /i915/intel_pm.c
>> @@ -1449,14 +1449,21 @@ static uint32_t ilk_compute_spr_wm(const struct
>> ilk_pipe_wm_parameters *params,
>> static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters
>> *params,
>>uint32_t mem_value)
>> {
>> + uint32_t line_wm, method2;
>> +
>> if (!params->active || !params->cur.enabled)
>> return 0;
>>
>> - return ilk_wm_method2(params->pixel_rate,
>> - params->pipe_htotal,
>> - params->cur.horiz_pixels,
>> - params->cur.bytes_per_pixel,
>> - mem_value);
>> + /* HACK: Big cursors tend to underrun, load at least one line. */
>> + line_wm = params->cur.horiz_pixels * params->cur.bytes_per_pixel /
>> 64;
>> +
>> + method2 = ilk_wm_method2(params->pixel_rate,
>> +params->pipe_htotal,
>> +params->cur.horiz_pixels,
>> +params->cur.bytes_per_pixel,
>> +mem_value);
>> +
>> + return max(line_wm, method2);
>> }
>>
>> /* Only for WM_LP. */
>> --
>> 1.9.3
>>
>
>
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 2/3] drm/i915/skl: Restore pipe interrupt registers after power well enabling
On Mon, Mar 02, 2015 at 03:37:47PM -0300, Paulo Zanoni wrote:
> 2015-02-13 17:37 GMT-02:00 Damien Lespiau :
> > The pipe interrupt registers are in the actual pipe power well, so we
> > need to restore them when re-enable the corresponding power well.
> >
> > I've also copied what we do on HSW/BDW for VGA, even if the we haven't
> > enabled unclaimed registers just yet.
> >
> > Signed-off-by: Damien Lespiau
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 4
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 31
> > +++
> > 2 files changed, 35 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 65fe9e7..292ba89 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3235,6 +3235,10 @@ void gen8_irq_power_well_post_enable(struct
> > drm_i915_private *dev_priv,
> > uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
> >
> > spin_lock_irq(&dev_priv->irq_lock);
> > + if (pipe_mask & 1 << PIPE_A)
> > + GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
> > + dev_priv->de_irq_mask[PIPE_A],
> > + ~dev_priv->de_irq_mask[PIPE_A] |
> > extra_ier);
> > if (pipe_mask & 1 << PIPE_B)
> > GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
> > dev_priv->de_irq_mask[PIPE_B],
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 35e0cb6..8989747 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -199,6 +199,34 @@ static void hsw_power_well_post_enable(struct
> > drm_i915_private *dev_priv)
> > 1 << PIPE_C | 1 << PIPE_B);
> > }
> >
> > +static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
> > + struct i915_power_well *power_well)
> > +{
> > + struct drm_device *dev = dev_priv->dev;
> > +
> > + /*
> > +* After we re-enable the power well, if we touch VGA register 0x3d5
> > +* we'll get unclaimed register interrupts. This stops after we
> > write
> > +* anything to the VGA MSR register. The vgacon module uses this
> > +* register all the time, so if we unbind our driver and, as a
> > +* consequence, bind vgacon, we'll get stuck in an infinite loop at
> > +* console_unlock(). So make here we touch the VGA MSR register,
> > making
> > +* sure vgacon can keep working normally without triggering
> > interrupts
> > +* and error messages.
> > +*/
> > + if (power_well->data == SKL_DISP_PW_2) {
> > + vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
> > + outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
> > + vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
> > +
> > + gen8_irq_power_well_post_enable(dev_priv,
> > + 1 << PIPE_C | 1 << PIPE_B);
> > + }
> > +
> > + if (power_well->data == SKL_DISP_PW_1)
> > + gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
> > +}
> > +
> > static void hsw_set_power_well(struct drm_i915_private *dev_priv,
> >struct i915_power_well *power_well, bool
> > enable)
> > {
> > @@ -359,6 +387,9 @@ static void skl_set_power_well(struct drm_i915_private
> > *dev_priv,
> > DRM_ERROR("PG2 distributing status
> > timeout\n");
> > }
> > }
> > +
> > + if (enable)
> > + skl_power_well_post_enable(dev_priv, power_well);
>
> Please take a look at "drm/i915: only run hsw_power_well_post_enable
> when really needed": http://patchwork.freedesktop.org/patch/34764/ and
> please do the equivalent change here. I also won't complain if you
> create "is_enabled" and "enable_requested" variables on
> skl_set_power_well, just like we have for hsw_set_power_well.
tbh I wonder whether we should move the irq enable/disable into the crtc
enable/disable functions on gen8+. That would have avoided the "have we
enabled this already" logic, which tends to be fragile in general. Otoh
this works too.
-Daniel
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Re: [Intel-gfx] [PATCH 5/7] drm/i915: Make sure we invalidate frontbuffer on fbcon.
On Mon, Mar 02, 2015 at 06:35:26PM +, Vivi, Rodrigo wrote:
> On Mon, 2015-03-02 at 18:59 +0100, Daniel Vetter wrote:
> > On Fri, Feb 27, 2015 at 08:26:05PM -0500, Rodrigo Vivi wrote:
> > > There are some cases like suspend/resume or dpms off/on sequences
> > > that can flush frontbuffer bits. In these cases features that relies
> > > on frontbuffer tracking can start working and user can stop getting
> > > screen updates on fbcon having impression the system is frozen.
> > >
> > > So, let's make sure on fbcon write operation we also invalidate
> > > frontbuffer bits so we will be on the safest side with fbcon.
> >
> > This is just a bandaid since you can always just directly access the
> > fbdev framebuffer. We really need to figure out why we have frontbuffer
> > bit flushes after we've invalidated them for fbcon and catch them all.
>
> yeah, an ugly bandaid... Just to make PSR a bit more reliable without
> breaking fbcon environment when it gets enabled by default.
>
> The issue is that on the logs I see:
>
> 1.fbdev_blank dpms off
> 2. disable planes
> 3. flush frontbuffer bits
> --- blank stage ---
> 4. fbdev_blank dpms on
so fbdev_blank returns _before_ the below enable_planes/frontbuf_flush?
Can you please attach full backtraces for steps 5&6?
> 5. enable planes
> 6. flush frontbuffer bits
>
> So even if we put the invalidate there it will still get flushed.
>
> Along with this sequence I see bunch of fillrect, cursor, imageblt,
> copyarea so what ever happens first right after the "6." will invalidate
> the frontbuffer_bits again so any direct write thought fbdev framebuffer
> will be safe enough.
Yeah generally fbcon starts out with drawing a bit black rectangle for the
entire screen, so this should generally work. But first I really want to
understand where that enable plane is coming from, before I give up and
apply this.
Thanks, Daniel
>
> So yeah, with this bandaid for now I believe we are safe to enable psr
> by default while we continue the investigation to come up with a proper
> fix.
>
> > -Daniel
> >
> > >
> > > Signed-off-by: Rodrigo Vivi
> > > ---
> > > drivers/gpu/drm/i915/intel_fbdev.c | 120
> > > -
> > > 1 file changed, 117 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
> > > b/drivers/gpu/drm/i915/intel_fbdev.c
> > > index 234a699..1b512f2 100644
> > > --- a/drivers/gpu/drm/i915/intel_fbdev.c
> > > +++ b/drivers/gpu/drm/i915/intel_fbdev.c
> > > @@ -71,13 +71,127 @@ static int intel_fbdev_set_par(struct fb_info *info)
> > > return ret;
> > > }
> > >
> > > +void intel_fbdev_fillrect(struct fb_info *info, const struct fb_fillrect
> > > *rect)
> > > +{
> > > + struct drm_fb_helper *fb_helper = info->par;
> > > + struct intel_fbdev *ifbdev =
> > > + container_of(fb_helper, struct intel_fbdev, helper);
> > > +
> > > + cfb_fillrect(info, rect);
> > > +
> > > + /*
> > > + * FIXME: fbdev presumes that all callbacks also work from
> > > + * atomic contexts and relies on that for emergency oops
> > > + * printing. KMS totally doesn't do that and the locking here is
> > > + * by far not the only place this goes wrong. Ignore this for
> > > + * now until we solve this for real.
> > > + */
> > > + mutex_lock(&fb_helper->dev->struct_mutex);
> > > +
> > > + /*
> > > + * There are some cases that can flush frontbuffer bits
> > > + * while we are still on console. So, let's make sure the fb obj
> > > + * gets invalidated on this write op so we don't have any risk
> > > + * of missing screen updates when PSR, FBC or any other power saving
> > > + * feature is enabled.
> > > + */
> > > + intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
> > > + mutex_unlock(&fb_helper->dev->struct_mutex);
> > > +}
> > > +
> > > +void intel_fbdev_copyarea(struct fb_info *info,
> > > + const struct fb_copyarea *region)\
> > > +{
> > > + struct drm_fb_helper *fb_helper = info->par;
> > > + struct intel_fbdev *ifbdev =
> > > + container_of(fb_helper, struct intel_fbdev, helper);
> > > +
> > > + cfb_copyarea(info, region);
> > > +
> > > + /*
> > > + * FIXME: fbdev presumes that all callbacks also work from
> > > + * atomic contexts and relies on that for emergency oops
> > > + * printing. KMS totally doesn't do that and the locking here is
> > > + * by far not the only place this goes wrong. Ignore this for
> > > + * now until we solve this for real.
> > > + */
> > > + mutex_lock(&fb_helper->dev->struct_mutex);
> > > +
> > > + /*
> > > + * There are some cases that can flush frontbuffer bits
> > > + * while we are still on console. So, let's make sure the fb obj
> > > + * gets invalidated on this write op so we don't have any risk
> > > + * of missing screen updates when PSR, FBC or any other power saving
> > > + * feature is enabled.
> > > + */
> > > + intel_fb_obj_invalidate(ifbdev->fb->obj, NULL);
> > > + mutex_unlock(&fb_helper->dev->struct_mutex);
> > >
Re: [Intel-gfx] [PATCH] drm/i915: Export total subslice and EU counts
On Mon, Mar 02, 2015 at 03:37:32PM -0800, jeff.mc...@intel.com wrote:
> From: Jeff McGee
>
> Setup new I915_GETPARAM ioctl entries for subslice total and
> EU total. Userspace drivers need these values when constructing
> GPGPU commands. This kernel query method is intended to replace
> the PCI ID-based tables that userspace drivers currently maintain.
> The kernel driver can employ fuse register reads as needed to
> ensure the most accurate determination of GT config attributes.
> This first became important with Cherryview in which the config
> could differ between devices with the same PCI ID.
>
> The kernel detection of these values is device-specific and not
> included in this patch. Because zero is not a valid value for any of
> these parameters, a value of zero is interpreted as unknown for the
> device. Userspace drivers should continue to maintain ID-based tables
> for older devices not supported by the new query method.
>
> For: VIZ-4636
> Signed-off-by: Jeff McGee
> ---
> drivers/gpu/drm/i915/i915_dma.c | 10 ++
> include/uapi/drm/i915_drm.h | 2 ++
> 2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 053e178..9350ea2 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -150,6 +150,16 @@ static int i915_getparam(struct drm_device *dev, void
> *data,
> case I915_PARAM_MMAP_VERSION:
> value = 1;
> break;
> + case I915_PARAM_SUBSLICE_TOTAL:
> + value = INTEL_INFO(dev)->subslice_total;
> + if (!value)
> + return -ENODEV;
> + break;
> + case I915_PARAM_EU_TOTAL:
> + value = INTEL_INFO(dev)->eu_total;
> + if (!value)
> + return -ENODEV;
I need the corresponding userspace support before I can merged this.
Thanks, Daniel
> + break;
> default:
> DRM_DEBUG("Unknown parameter %d\n", param->param);
> return -EINVAL;
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 6eed16b..8672efc 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -347,6 +347,8 @@ typedef struct drm_i915_irq_wait {
> #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
> #define I915_PARAM_MMAP_VERSION 30
> #define I915_PARAM_HAS_BSD2 31
> +#define I915_PARAM_SUBSLICE_TOTAL 32
> +#define I915_PARAM_EU_TOTAL 33
>
> typedef struct drm_i915_getparam {
> int param;
> --
> 2.3.0
>
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Re: [Intel-gfx] [PATCH] drm/i915: Export total subslice and EU counts
On Tue, Mar 03, 2015 at 09:54:39AM +0100, Daniel Vetter wrote: > On Mon, Mar 02, 2015 at 03:37:32PM -0800, jeff.mc...@intel.com wrote: > > From: Jeff McGee > > > > Setup new I915_GETPARAM ioctl entries for subslice total and > > EU total. Userspace drivers need these values when constructing > > GPGPU commands. This kernel query method is intended to replace > > the PCI ID-based tables that userspace drivers currently maintain. > > The kernel driver can employ fuse register reads as needed to > > ensure the most accurate determination of GT config attributes. > > This first became important with Cherryview in which the config > > could differ between devices with the same PCI ID. > > > > The kernel detection of these values is device-specific and not > > included in this patch. Because zero is not a valid value for any of > > these parameters, a value of zero is interpreted as unknown for the > > device. Userspace drivers should continue to maintain ID-based tables > > for older devices not supported by the new query method. > > > > For: VIZ-4636 > > Signed-off-by: Jeff McGee > > --- > > drivers/gpu/drm/i915/i915_dma.c | 10 ++ > > include/uapi/drm/i915_drm.h | 2 ++ > > 2 files changed, 12 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_dma.c > > b/drivers/gpu/drm/i915/i915_dma.c > > index 053e178..9350ea2 100644 > > --- a/drivers/gpu/drm/i915/i915_dma.c > > +++ b/drivers/gpu/drm/i915/i915_dma.c > > @@ -150,6 +150,16 @@ static int i915_getparam(struct drm_device *dev, void > > *data, > > case I915_PARAM_MMAP_VERSION: > > value = 1; > > break; > > + case I915_PARAM_SUBSLICE_TOTAL: > > + value = INTEL_INFO(dev)->subslice_total; > > + if (!value) > > + return -ENODEV; > > + break; > > + case I915_PARAM_EU_TOTAL: > > + value = INTEL_INFO(dev)->eu_total; > > + if (!value) > > + return -ENODEV; > > I need the corresponding userspace support before I can merged this. Strike that, I've missed the beignet support. As soon as beignet maintainers have that reviewed I can pull this in. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] demos/intel_sprite_on : Sprite Stress Testing
From: meghanelogal
Adding the Sprite Stress Test Feature
Signed-off-by: meghanelogal
---
demos/intel_sprite_on.c | 653 +--
1 file changed, 347 insertions(+), 306 deletions(-)
diff --git a/demos/intel_sprite_on.c b/demos/intel_sprite_on.c
index 23fc56c..ad6b163 100644
--- a/demos/intel_sprite_on.c
+++ b/demos/intel_sprite_on.c
@@ -49,6 +49,8 @@
#include "ioctl_wrappers.h"
+
+static int sprite_iteration_count = 1;
/*
* Mode setting with the kernel interfaces is a bit of a chore.
* First you have to find the connector in question and make sure the
@@ -476,7 +478,7 @@ static int prepare_sprite_surfaces(int fd, int
sprite_width, int sprite_height,
}
static void ricochet(int tiled, int sprite_w, int sprite_h,
-int out_w, int out_h, int dump_info)
+int out_w, int out_h, int dump_info, int delay_time)
{
int ret;
int gfx_fd;
@@ -499,7 +501,7 @@ static void ricochet(int tiled, int sprite_w, int sprite_h,
prim_fb_id;
struct drm_intel_sprite_colorkeyset;
struct connectorcurr_connector;
- drmModeRes *gfx_resources;
+ drmModeRes *gfx_resources = NULL;
struct termios orig_term,
curr_term;
int c_index;
@@ -518,259 +520,264 @@ static void ricochet(int tiled, int sprite_w, int
sprite_h,
charkey;
int sprite_plane_count = 0;
int i;
+ int sprite_loop = 0;
+ int disable_timer = 0;
+ drmModePlaneRes *plane_resources;
+ drmModePlane *ovr;
// Open up I915 graphics device
gfx_fd = drmOpen("i915", NULL);
if (gfx_fd < 0) {
printf("Failed to load i915 driver: %s\n", strerror(errno));
return;
}
-
- // Obtain pointer to struct containing graphics resources
- gfx_resources = drmModeGetResources(gfx_fd);
- if (!gfx_resources) {
- printf("drmModeGetResources failed: %s\n", strerror(errno));
- return;
- }
-
- if (dump_info != 0) {
- dump_connectors(gfx_fd, gfx_resources);
- dump_crtcs(gfx_fd, gfx_resources);
- dump_planes(gfx_fd, gfx_resources);
- }
-
- // Save previous terminal settings
- if (tcgetattr( 0, &orig_term) != 0) {
- printf("tcgetattr failure: %s\n",
- strerror(errno));
- return;
- }
-
- // Set up input to return characters immediately
- curr_term = orig_term;
- curr_term.c_lflag &= ~(ICANON | ECHO | ECHONL);
- curr_term.c_cc[VMIN] = 0; // No minimum number of characters
- curr_term.c_cc[VTIME] = 0 ; // Return immediately, even if
- // nothing has been entered.
- if (tcsetattr( 0, TCSANOW, &curr_term) != 0) {
- printf("tcgetattr failure: %s\n", strerror(errno));
- return;
- }
-
- // Cycle through all connectors and display the flying sprite
- // where there are displays attached and the hardware will support it.
- for (c_index = 0; c_index < gfx_resources->count_connectors; c_index++)
{
- curr_connector.id = gfx_resources->connectors[c_index];
-
- // Find the native (preferred) display mode
- connector_find_preferred_mode(gfx_fd, gfx_resources,
&curr_connector);
- if (curr_connector.mode_valid == 0) {
- printf("No valid preferred mode detected\n");
- goto out;
- }
-
- // Determine if sprite hardware is available on pipe
- // associated with this connector.
- sprite_plane_count = connector_find_plane(gfx_fd,
&curr_connector,
- &sprite_plane_id);
- if (!sprite_plane_count) {
- printf("Failed to find sprite plane on crtc\n");
- goto out;
+ /* Stress Cycle iteration */
+ for (sprite_loop = 0; sprite_loop < sprite_iteration_count;
sprite_loop++) {
+ // Obtain pointer to struct containing graphics resources
+ disable_timer = 0;
+ gfx_resources = drmModeGetResources(gfx_fd);
+ if (!gfx_resources) {
+ printf("drmModeGetResources failed: %s\n",
strerror(errno));
+ return;
}
- // Width and height of preferred mode
- prim_width = curr_connector.mode.hdisplay;
- prim_height = c
Re: [Intel-gfx] [PATCH 3/5] drm/i915/skl: Support secondary (rotated) frame buffer mapping
On 03/02/2015 06:21 PM, Daniel Vetter wrote:
On Mon, Mar 02, 2015 at 02:43:50PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
90/270 rotated scanout needs a rotated GTT view of the framebuffer.
This is put in a separate VMA with a dedicated ggtt_view and wired suchs that
it is created when a framebuffer is pinned to a 90/270 rotated plane.
Rotation is only possible with Yb/Yf buffers and error is propagated to
user space in case of a mismatch.
Special rotated page view is constructed at the VMA creation time by
borrowing the DMA addresses from obj->pages.
v2:
* Do not bother with pages for rotated sg list, just populate the DMA
addresses. (Daniel Vetter)
* Checkpatch cleanup.
v3:
* Rebased on top of new plane handling (create rotated mapping when
setting the rotation property).
* Unpin rotated VMA on unpinning from display plane.
* Simplify rotation check using bitwise AND. (Chris Wilson)
v4:
* Fix unpinning of optional rotated mapping so it is really considered
to be optional.
v5:
* Rebased for fb modifier changes.
* Rebased for atomic commit.
* Only pin needed view for display. (Ville Syrjälä, Daniel Vetter)
For: VIZ-4726
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Michel Thierry (v4)
Bunch of nitpicks below. Also I think it'd be good to split this patch
into the rote refactoring work to add view parameters all over the place
and the actual implementation.
Ok will split it. Rest below...
---
drivers/gpu/drm/i915/i915_drv.h | 33 +-
drivers/gpu/drm/i915/i915_gem.c | 27 +++--
drivers/gpu/drm/i915/i915_gem_gtt.c | 14 ++-
drivers/gpu/drm/i915/i915_gem_gtt.h | 12 +++
drivers/gpu/drm/i915/intel_display.c | 204 +++
drivers/gpu/drm/i915/intel_drv.h | 4 +
drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
drivers/gpu/drm/i915/intel_overlay.c | 3 +-
8 files changed, 263 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e07a1cb..79d3f2c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2743,8 +2743,10 @@ i915_gem_object_set_to_cpu_domain(struct
drm_i915_gem_object *obj, bool write);
int __must_check
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
u32 alignment,
-struct intel_engine_cs *pipelined);
-void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
+struct intel_engine_cs *pipelined,
+const struct i915_ggtt_view *view);
+void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
+ const struct i915_ggtt_view
*view);
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
int align);
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
@@ -2813,7 +2815,13 @@ i915_gem_obj_lookup_or_create_vma(struct
drm_i915_gem_object *obj,
&i915_ggtt_view_normal);
}
-struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
+struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
+ enum i915_ggtt_view_type view);
+static inline
+struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
+{
+ return i915_gem_obj_to_ggtt_view(obj, I915_GGTT_VIEW_NORMAL);
+}
static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
struct i915_vma *vma;
list_for_each_entry(vma, &obj->vma_list, vma_link)
@@ -2867,13 +2875,30 @@ i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
alignment, flags | PIN_GLOBAL);
}
+static inline int __must_check
+i915_gem_obj_ggtt_pin_view(struct drm_i915_gem_object *obj,
+ uint32_t alignment,
+ unsigned flags,
+ const struct i915_ggtt_view *ggtt_view)
+{
+ return i915_gem_object_pin_view(obj, i915_obj_to_ggtt(obj),
+ alignment, flags | PIN_GLOBAL,
+ ggtt_view);
+}
+
static inline int
i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
{
return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
}
-void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
+void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
+enum i915_ggtt_view_type view);
+static inline void
+i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
+{
+ i915_gem_object_ggtt_unpin_view(obj, I915_GGTT_VIEW_NORMAL);
+}
/* i915_gem_context.c */
int __must_check i915_gem_context_init(struct drm_device *dev);
diff --g
Re: [Intel-gfx] [PATCH 7/7] drm/i915: Enable PSR by default.
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5865 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -5 278/278 273/278 ILK -8 308/308 300/308 SNB -1 284/284 283/284 IVB 380/380 380/380 BYT 294/294 294/294 HSW -1 387/387 386/387 BDW -2 316/316 314/316 -Detailed- Platform Testdrm-intel-nightly Series Applied PNV igt_gem_userptr_blits_coherency-sync CRASH(3)PASS(6) CRASH(2) PNV igt_gem_userptr_blits_coherency-unsync CRASH(2)PASS(5) CRASH(2) *PNV igt_gem_userptr_blits_minor-unsync-interruptible PASS(4) DMESG_WARN(1)PASS(1) PNV igt_gen3_render_linear_blits FAIL(3)PASS(5) FAIL(2) PNV igt_gen3_render_mixed_blits FAIL(2)PASS(8) FAIL(2) *ILK igt_gem_bad_length PASS(2) DMESG_WARN(1)PASS(1) *ILK igt_gem_exec_params_no-blt PASS(2) DMESG_WARN(1)PASS(1) *ILK igt_gem_exec_params_sol-reset-not-gen7 PASS(2) DMESG_WARN(1)PASS(1) *ILK igt_gem_reloc_overflow_source-offset-negative-reloc-cpu PASS(2) DMESG_WARN(2) *ILK igt_gem_reloc_overflow_source-offset-negative-reloc-gtt PASS(2) DMESG_WARN(1)PASS(1) *ILK igt_gem_seqno_wrap PASS(2) DMESG_WARN(1)PASS(1) ILK igt_gem_unfence_active_buffers DMESG_WARN(1)PASS(2) DMESG_WARN(1)PASS(1) *ILK igt_kms_addfb_small-bo PASS(2) DMESG_WARN(1)PASS(1) *SNB igt_gem_flink_bad-open PASS(4) DMESG_WARN(1)PASS(1) *HSW igt_gem_storedw_loop_blt PASS(3) DMESG_WARN(1)PASS(1) *BDW igt_gem_gtt_hog PASS(12) TIMEOUT(1)PASS(1) *BDW igt_gem_ringfill_blitter-interruptible PASS(2) NO_RESULT(1)PASS(1) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t v4] tests/gem_render_linear_blits: split into two subtests
From: Tim Gore
The gem_render_linear_blits test tends to get oom killed
on low memory (< 4GB) Android systems. This is because the
test tries to allocate (sysinfo.totalram * 9 / 10) in
buffer objects and the remaining 10% of memory is not
always enough for the Android system.
After a discussion with Chris Wilson I have split this
test into a "basic" and an "apperture-thrash" subtest,
in the same way as gem_linear_blits. The basic test
uses just two buffer objects and the apperture-thrash
test is skipped if there is insuffiecient memory.
v2: Following comment from Chris Wilson:
a) Remove the command line option for count.
b) Add a third subtest to ensure swap is tested
v3: Replace some leading spaces with tabs
v4: Follwing comment from Daniel Vetter:
a) Use igt_main macro instead of "open coding", and
b) cull some more leading spaces
Signed-off-by: Tim Gore
---
tests/gem_render_linear_blits.c | 74 +
1 file changed, 45 insertions(+), 29 deletions(-)
diff --git a/tests/gem_render_linear_blits.c b/tests/gem_render_linear_blits.c
index 60ba831..f83c6d4 100644
--- a/tests/gem_render_linear_blits.c
+++ b/tests/gem_render_linear_blits.c
@@ -73,25 +73,21 @@ check_bo(int fd, uint32_t handle, uint32_t val)
gem_read(fd, handle, 0, linear, sizeof(linear));
for (i = 0; i < WIDTH*HEIGHT; i++) {
igt_assert_f(linear[i] == val,
-"Expected 0x%08x, found 0x%08x "
-"at offset 0x%08x\n",
-val, linear[i], i * 4);
+ "Expected 0x%08x, found 0x%08x "
+ "at offset 0x%08x\n",
+ val, linear[i], i * 4);
val++;
}
}
-int main(int argc, char **argv)
+static void run_test (int fd, int count)
{
drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
uint32_t *start_val;
drm_intel_bo **bo;
uint32_t start = 0;
- int i, j, fd, count;
-
- igt_simple_init(argc, argv);
-
- fd = drm_open_any();
+ int i, j;
render_copy = igt_get_render_copyfunc(intel_get_drm_devid(fd));
igt_require(render_copy);
@@ -99,24 +95,6 @@ int main(int argc, char **argv)
bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
- count = 0;
- if (igt_run_in_simulation())
- count = 2;
- if (argc > 1)
- count = atoi(argv[1]);
-
- if (count == 0)
- count = 3 * gem_aperture_size(fd) / SIZE / 2;
- else if (count < 2) {
- igt_warn("count must be >= 2\n");
- return 1;
- }
-
- if (count > intel_get_total_ram_mb() * 9 / 10) {
- count = intel_get_total_ram_mb() * 9 / 10;
- igt_info("not enough RAM to run test, reducing buffer count\n");
- }
-
bo = malloc(sizeof(*bo)*count);
start_val = malloc(sizeof(*start_val)*count);
@@ -128,7 +106,7 @@ int main(int argc, char **argv)
gem_write(fd, bo[i]->handle, 0, linear, sizeof(linear));
}
- igt_info("Verifying initialisation...\n");
+ igt_info("Verifying initialisation - %d buffers of %d bytes\n", count,
SIZE);
for (i = 0; i < count; i++)
check_bo(fd, bo[i]->handle, start_val[i]);
@@ -153,7 +131,7 @@ int main(int argc, char **argv)
check_bo(fd, bo[i]->handle, start_val[i]);
if (igt_run_in_simulation())
- return 0;
+ return;
igt_info("Cyclic blits, backward...\n");
for (i = 0; i < count * 4; i++) {
@@ -200,5 +178,43 @@ int main(int argc, char **argv)
for (i = 0; i < count; i++)
check_bo(fd, bo[i]->handle, start_val[i]);
+ /* release resources */
+ for (i = 0; i < count; i++) {
+ drm_intel_bo_unreference(bo[i]);
+ }
+ intel_batchbuffer_free(batch);
+ drm_intel_bufmgr_destroy(bufmgr);
+}
+
+igt_main
+{
+ static int fd = 0;
+ int count=0;
+
+ igt_fixture {
+ fd = drm_open_any();
+ }
+
+ igt_subtest("basic") {
+ run_test(fd, 2);
+ }
+
+ /* the rest of the tests are too long for simulation */
+ igt_skip_on_simulation();
+
+ igt_subtest("apperture-thrash") {
+ count = 3 * gem_aperture_size(fd) / SIZE / 2;
+ intel_require_memory(count, SIZE, CHECK_RAM);
+ run_test(fd, count);
+ }
+
+ igt_subtest("swap-thrash") {
+ uint64_t swap_mb = intel_get_total_swap_mb();
+ igt_require(swap_mb > 0);
+ count = ((intel_get_avail_ram_mb() + (swap_mb / 2)) *
1024*1024) / SIZE;
+ intel_require_memory(count, SIZE, CHECK_RAM | CHECK_SWAP);
+ run_test(fd, count);
+ }
+
[Intel-gfx] [PATCH i-g-t v2] tests/gem_render_tiled_blits: split into subtests
From: Tim Gore
The gem_render_tiled_blits test tends to get oom killed
on low memory (< 4GB) Android systems. This is because the
test tries to allocate (sysinfo.totalram * 9 / 10) in
buffer objects and the remaining 10% of memory is not
always enough for the Android system.
A similar issue with gem_render_linear_blits was resolved
by creating several subtests. A "basic" subtest that uses
minimal memory buffers to test the basic operation, and
two stress tests which are skipped if there is insufficient
memory. The first stress test uses more memory than the
graphics apperture and the second uses enough to ensure
that swap space is used (if present).
This patch makes the same changes to gem_render_tiled_blits.
v2: Following comments from Daniel Vetter:
a) Use igt_main macro instead of "open coding", and
b) cull some leading spaces
Signed-off-by: Tim Gore
---
tests/gem_render_tiled_blits.c | 72 ++
1 file changed, 45 insertions(+), 27 deletions(-)
diff --git a/tests/gem_render_tiled_blits.c b/tests/gem_render_tiled_blits.c
index dc22529..f669270 100644
--- a/tests/gem_render_tiled_blits.c
+++ b/tests/gem_render_tiled_blits.c
@@ -85,30 +85,25 @@ check_bo(struct intel_batchbuffer *batch, struct igt_buf
*buf, uint32_t val)
}
for (i = 0; i < WIDTH*HEIGHT; i++) {
igt_assert_f(ptr[i] == val,
-"Expected 0x%08x, found 0x%08x "
-"at offset 0x%08x\n",
-val, ptr[i], i * 4);
+ "Expected 0x%08x, found 0x%08x "
+ "at offset 0x%08x\n",
+ val, ptr[i], i * 4);
val++;
}
if (ptr != data)
dri_bo_unmap(linear);
}
-int main(int argc, char **argv)
+static void run_test (int fd, int count)
{
drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
uint32_t *start_val;
struct igt_buf *buf;
uint32_t start = 0;
- int i, j, fd, count;
+ int i, j;
uint32_t devid;
- igt_simple_init(argc, argv);
-
- igt_skip_on_simulation();
-
- fd = drm_open_any();
devid = intel_get_drm_devid(fd);
render_copy = igt_get_render_copyfunc(devid);
@@ -124,23 +119,6 @@ int main(int argc, char **argv)
drm_intel_bufmgr_gem_set_vma_cache_size(bufmgr, 32);
batch = intel_batchbuffer_alloc(bufmgr, devid);
- count = 0;
- if (argc > 1)
- count = atoi(argv[1]);
- if (count == 0)
- count = 3 * gem_aperture_size(fd) / SIZE / 2;
- else if (count < 2) {
- igt_warn("count must be >= 2\n");
- return 1;
- }
-
- if (count > intel_get_total_ram_mb() * 9 / 10) {
- count = intel_get_total_ram_mb() * 9 / 10;
- igt_info("not enough RAM to run test, reducing buffer count\n");
- }
-
- igt_info("Using %d 1MiB buffers\n", count);
-
linear = drm_intel_bo_alloc(bufmgr, "linear", WIDTH*HEIGHT*4, 0);
if (snoop) {
gem_set_caching(fd, linear->handle, 1);
@@ -211,5 +189,45 @@ int main(int argc, char **argv)
for (i = 0; i < count; i++)
check_bo(batch, &buf[i], start_val[i]);
+ /* release resources */
+ drm_intel_bo_unreference(linear);
+ for (i = 0; i < count; i++) {
+ drm_intel_bo_unreference(buf[i].bo);
+ }
+ intel_batchbuffer_free(batch);
+ drm_intel_bufmgr_destroy(bufmgr);
+}
+
+
+igt_main
+{
+ int fd = 0;
+ int count = 0;
+
+ igt_fixture {
+ fd = drm_open_any();
+ }
+
+ igt_subtest("basic") {
+ run_test(fd, 2);
+ }
+
+ /* the rest of the tests are too long for simulation */
+ igt_skip_on_simulation();
+
+ igt_subtest("apperture-thrash") {
+ count = 3 * gem_aperture_size(fd) / SIZE / 2;
+ intel_require_memory(count, SIZE, CHECK_RAM);
+ run_test(fd, count);
+ }
+
+ igt_subtest("swap-thrash") {
+ uint64_t swap_mb = intel_get_total_swap_mb();
+ igt_require(swap_mb > 0);
+ count = ((intel_get_avail_ram_mb() + (swap_mb / 2)) *
1024*1024) / SIZE;
+ intel_require_memory(count, SIZE, CHECK_RAM | CHECK_SWAP);
+ run_test(fd, count);
+ }
+
igt_exit();
}
--
2.3.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use plane->state->fb in watermark code (v2)
Hi
2015-02-27 15:12 GMT-03:00 Matt Roper :
> plane->fb is a legacy pointer that not always be up-to-date (or updated
> early enough). Make sure the watermark code uses plane->state->fb so
> that we're always doing our calculations based on the correct
> framebuffers.
QA reported a regression caused by this patch: Kernel NULL pointer dereference.
https://bugs.freedesktop.org/show_bug.cgi?id=89388
>
> This patch was generated by Coccinelle with the following semantic
> patch:
>
> @@
> struct drm_plane *P;
> @@
> - P->fb
> + P->state->fb
>
> v2: Rebase
>
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_wm.c | 22 +++---
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_wm.c b/drivers/gpu/drm/i915/intel_wm.c
> index 47a5175..e877e02 100644
> --- a/drivers/gpu/drm/i915/intel_wm.c
> +++ b/drivers/gpu/drm/i915/intel_wm.c
> @@ -496,7 +496,7 @@ static void pineview_update_wm(struct drm_crtc
> *unused_crtc)
> crtc = single_enabled_crtc(dev);
> if (crtc) {
> const struct drm_display_mode *adjusted_mode;
> - int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
> + int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
> int clock;
>
> adjusted_mode =
> &to_intel_crtc(crtc)->config->base.adjusted_mode;
> @@ -572,7 +572,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
> clock = adjusted_mode->crtc_clock;
> htotal = adjusted_mode->crtc_htotal;
> hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
> - pixel_size = crtc->primary->fb->bits_per_pixel / 8;
> + pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
>
> /* Use the small buffer method to calculate plane watermark */
> entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
> @@ -659,7 +659,7 @@ static bool g4x_compute_srwm(struct drm_device *dev,
> clock = adjusted_mode->crtc_clock;
> htotal = adjusted_mode->crtc_htotal;
> hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
> - pixel_size = crtc->primary->fb->bits_per_pixel / 8;
> + pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
>
> line_time_us = max(htotal * 1000 / clock, 1);
> line_count = (latency_ns / line_time_us + 1000) / 1000;
> @@ -742,7 +742,7 @@ static void vlv_update_drain_latency(struct drm_crtc
> *crtc)
> }
>
> /* Primary plane Drain Latency */
> - pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
> + pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; /*
> BPP */
> if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
> &drain_latency)) {
> plane_prec = (prec_mult == high_precision) ?
>DDL_PLANE_PRECISION_HIGH :
> @@ -1023,7 +1023,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
> int clock = adjusted_mode->crtc_clock;
> int htotal = adjusted_mode->crtc_htotal;
> int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
> - int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
> + int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
> unsigned long line_time_us;
> int entries;
>
> @@ -1100,7 +1100,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> crtc = intel_get_crtc_for_plane(dev, 0);
> if (intel_crtc_active(crtc)) {
> const struct drm_display_mode *adjusted_mode;
> - int cpp = crtc->primary->fb->bits_per_pixel / 8;
> + int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
> if (IS_GEN2(dev))
> cpp = 4;
>
> @@ -1122,7 +1122,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> crtc = intel_get_crtc_for_plane(dev, 1);
> if (intel_crtc_active(crtc)) {
> const struct drm_display_mode *adjusted_mode;
> - int cpp = crtc->primary->fb->bits_per_pixel / 8;
> + int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
> if (IS_GEN2(dev))
> cpp = 4;
>
> @@ -1145,7 +1145,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> if (IS_I915GM(dev) && enabled) {
> struct drm_i915_gem_object *obj;
>
> - obj = intel_fb_obj(enabled->primary->fb);
> + obj = intel_fb_obj(enabled->primary->state->fb);
>
> /* self-refresh seems busted with untiled */
> if (obj->tiling_mode == I915_TILING_NONE)
> @@ -1169,7 +1169,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> int clock = adjusted_mode->crtc_clock;
> int htotal = adjusted_mode->crtc_htotal
Re: [Intel-gfx] [PATCH 01/12] drm/i915/bdw: Make pdp allocation more dynamic
On Fri, Feb 20, 2015 at 11:15 PM, Michel Thierry
wrote:
> From: Ben Widawsky
>
> This transitional patch doesn't do much for the existing code. However,
> it should make upcoming patches to use the full 48b address space a bit
> easier to swallow. The patch also introduces the PML4, ie. the new top
> level structure of the page tables.
>
> v2: Renamed pdp_free to be similar to pd/pt (unmap_and_free_pdp),
> To facilitate testing, 48b mode will be available on Broadwell, when
> i915.enable_ppgtt = 3.
>
> Signed-off-by: Ben Widawsky
> Signed-off-by: Michel Thierry (v2)
> ---
> drivers/gpu/drm/i915/i915_drv.h | 7 ++-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 108
> +---
> drivers/gpu/drm/i915/i915_gem_gtt.h | 41 +++---
> 3 files changed, 126 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2dedd43..af0d149 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2432,7 +2432,12 @@ struct drm_i915_cmd_table {
> #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
> #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
> #define USES_PPGTT(dev)(i915.enable_ppgtt)
> -#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
> +#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
> +#ifdef CONFIG_64BIT
> +# define USES_FULL_48BIT_PPGTT(dev)(i915.enable_ppgtt == 3)
> +#else
> +# define USES_FULL_48BIT_PPGTT(dev)false
> +#endif
>
> #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
> #define OVERLAY_NEEDS_PHYSICAL(dev)
> (INTEL_INFO(dev)->overlay_needs_physical)
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index ff86501..489f8db 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -100,10 +100,17 @@ static int sanitize_enable_ppgtt(struct drm_device
> *dev, int enable_ppgtt)
> {
> bool has_aliasing_ppgtt;
> bool has_full_ppgtt;
> + bool has_full_64bit_ppgtt;
>
> has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
> has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
>
> +#ifdef CONFIG_64BIT
> + has_full_64bit_ppgtt = IS_BROADWELL(dev) && false; /* FIXME: 64b */
> +#else
> + has_full_64bit_ppgtt = false;
> +#endif
> +
> if (intel_vgpu_active(dev))
> has_full_ppgtt = false; /* emulation is too hard */
>
> @@ -121,6 +128,9 @@ static int sanitize_enable_ppgtt(struct drm_device *dev,
> int enable_ppgtt)
> if (enable_ppgtt == 2 && has_full_ppgtt)
> return 2;
>
> + if (enable_ppgtt == 3 && has_full_64bit_ppgtt)
> + return 3;
> +
> #ifdef CONFIG_INTEL_IOMMU
> /* Disable ppgtt on SNB if VT-d is on. */
> if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
> @@ -462,6 +472,45 @@ free_pd:
> return ERR_PTR(ret);
> }
>
> +static void __pdp_fini(struct i915_page_directory_pointer_entry *pdp)
> +{
> + kfree(pdp->used_pdpes);
> + kfree(pdp->page_directory);
> + /* HACK */
> + pdp->page_directory = NULL;
> +}
> +
> +static void unmap_and_free_pdp(struct i915_page_directory_pointer_entry *pdp,
> + struct drm_device *dev)
> +{
> + __pdp_fini(pdp);
> + if (USES_FULL_48BIT_PPGTT(dev))
> + kfree(pdp);
> +}
> +
> +static int __pdp_init(struct i915_page_directory_pointer_entry *pdp,
> + struct drm_device *dev)
> +{
> + size_t pdpes = I915_PDPES_PER_PDP(dev);
> +
> + pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
> + sizeof(unsigned long),
> + GFP_KERNEL);
> + if (!pdp->used_pdpes)
> + return -ENOMEM;
> +
> + pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
> GFP_KERNEL);
> + if (!pdp->page_directory) {
> + kfree(pdp->used_pdpes);
> + /* the PDP might be the statically allocated top level. Keep
> it
> +* as clean as possible */
> + pdp->used_pdpes = NULL;
> + return -ENOMEM;
> + }
> +
> + return 0;
> +}
> +
> /* Broadwell Page Directory Pointer Descriptors */
> static int gen8_write_pdp(struct intel_engine_cs *ring,
> unsigned entry,
> @@ -491,7 +540,7 @@ static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
> {
> int i, ret;
>
> - for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
> + for (i = 3; i >= 0; i--) {
> struct i915_page_directory_entry *pd =
> ppgtt->pdp.page_directory[i];
> dma_addr_t pd_daddr = pd ? pd->daddr :
> ppgtt->scratch_pd->daddr;
> /* The page directory might be NULL, but we need to clear out
> @@ -580,9 +629,6 @@ static void gen8_ppgtt_insert_entries(struct
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Make for_each_sprite() take dev_priv as argument
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5866 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -9 278/278 269/278 ILK 308/308 308/308 SNB 284/284 284/284 IVB 380/380 380/380 BYT 294/294 294/294 HSW 387/387 387/387 BDW -1 316/316 315/316 -Detailed- Platform Testdrm-intel-nightly Series Applied *PNV igt_gem_fence_thrash_bo-write-verify-none PASS(4) FAIL(1)PASS(1) *PNV igt_gem_fence_thrash_bo-write-verify-x PASS(4) FAIL(1)PASS(1) *PNV igt_gem_fence_thrash_bo-write-verify-y PASS(4) FAIL(1)PASS(1) PNV igt_gem_userptr_blits_coherency-sync CRASH(3)PASS(6) CRASH(2) PNV igt_gem_userptr_blits_coherency-unsync CRASH(2)PASS(5) CRASH(2) PNV igt_gen3_render_linear_blits FAIL(3)PASS(5) FAIL(2) PNV igt_gen3_render_mixed_blits FAIL(2)PASS(8) FAIL(2) PNV igt_gem_fence_thrash_bo-write-verify-threaded-none FAIL(2)CRASH(1)PASS(3) CRASH(1)PASS(1) *PNV igt_gem_partial_pwrite_pread_reads PASS(4) CRASH(1)PASS(1) *BDW igt_gem_gtt_hog PASS(12) DMESG_WARN(1)PASS(1) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/12] drm/i915/bdw: Abstract PDP usage
On Fri, Feb 20, 2015 at 11:15 PM, Michel Thierry
wrote:
> From: Ben Widawsky
>
> Up until now, ppgtt->pdp has always been the root of our page tables.
> Legacy 32b addresses acted like it had 1 PDP with 4 PDPEs.
>
> In preparation for 4 level page tables, we need to stop use ppgtt->pdp
> directly unless we know it's what we want. The future structure will use
> ppgtt->pml4 for the top level, and the pdp is just one of the entries
> being pointed to by a pml4e.
>
> v2: Updated after dynamic page allocation changes.
>
> Signed-off-by: Ben Widawsky
> Signed-off-by: Michel Thierry (v2)
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 123
>
> 1 file changed, 70 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 489f8db..d3ad517 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -560,6 +560,7 @@ static void gen8_ppgtt_clear_range(struct
> i915_address_space *vm,
> {
> struct i915_hw_ppgtt *ppgtt =
> container_of(vm, struct i915_hw_ppgtt, base);
> + struct i915_page_directory_pointer_entry *pdp = &ppgtt->pdp; /*
> FIXME: 48b */
> gen8_gtt_pte_t *pt_vaddr, scratch_pte;
> unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
> unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
> @@ -575,10 +576,10 @@ static void gen8_ppgtt_clear_range(struct
> i915_address_space *vm,
> struct i915_page_table_entry *pt;
> struct page *page_table;
>
> - if (WARN_ON(!ppgtt->pdp.page_directory[pdpe]))
> + if (WARN_ON(!pdp->page_directory[pdpe]))
> continue;
>
> - pd = ppgtt->pdp.page_directory[pdpe];
> + pd = pdp->page_directory[pdpe];
>
> if (WARN_ON(!pd->page_tables[pde]))
> continue;
> @@ -620,6 +621,7 @@ static void gen8_ppgtt_insert_entries(struct
> i915_address_space *vm,
> {
> struct i915_hw_ppgtt *ppgtt =
> container_of(vm, struct i915_hw_ppgtt, base);
> + struct i915_page_directory_pointer_entry *pdp = &ppgtt->pdp; /*
> FIXME: 48b */
> gen8_gtt_pte_t *pt_vaddr;
> unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
> unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
> @@ -630,7 +632,7 @@ static void gen8_ppgtt_insert_entries(struct
> i915_address_space *vm,
>
> for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
> if (pt_vaddr == NULL) {
> - struct i915_page_directory_entry *pd =
> ppgtt->pdp.page_directory[pdpe];
> + struct i915_page_directory_entry *pd =
> pdp->page_directory[pdpe];
> struct i915_page_table_entry *pt =
> pd->page_tables[pde];
> struct page *page_table = pt->page;
>
> @@ -708,16 +710,17 @@ static void gen8_free_page_tables(struct
> i915_page_directory_entry *pd, struct d
> static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
> {
> struct pci_dev *hwdev = ppgtt->base.dev->pdev;
> + struct i915_page_directory_pointer_entry *pdp = &ppgtt->pdp; /*
> FIXME: 48b */
> int i, j;
>
> - for_each_set_bit(i, ppgtt->pdp.used_pdpes,
> + for_each_set_bit(i, pdp->used_pdpes,
> I915_PDPES_PER_PDP(ppgtt->base.dev)) {
> struct i915_page_directory_entry *pd;
>
> - if (WARN_ON(!ppgtt->pdp.page_directory[i]))
> + if (WARN_ON(!pdp->page_directory[i]))
> continue;
>
> - pd = ppgtt->pdp.page_directory[i];
> + pd = pdp->page_directory[i];
> if (!pd->daddr)
> pci_unmap_page(hwdev, pd->daddr, PAGE_SIZE,
> PCI_DMA_BIDIRECTIONAL);
> @@ -743,15 +746,21 @@ static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
> {
> int i;
>
> - for_each_set_bit(i, ppgtt->pdp.used_pdpes,
> - I915_PDPES_PER_PDP(ppgtt->base.dev)) {
> - if (WARN_ON(!ppgtt->pdp.page_directory[i]))
> - continue;
> + if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
> + for_each_set_bit(i, ppgtt->pdp.used_pdpes,
> +I915_PDPES_PER_PDP(ppgtt->base.dev)) {
> + if (WARN_ON(!ppgtt->pdp.page_directory[i]))
> + continue;
>
> - gen8_free_page_tables(ppgtt->pdp.page_directory[i],
> ppgtt->base.dev);
> - unmap_and_free_pd(ppgtt->pdp.page_directory[i],
> ppgtt->base.dev);
> + gen8_free_page_tables(ppgtt->pdp.page_directory[i],
> + ppgtt->base.dev);
> + unmap_and_free_pd(ppgt
Re: [Intel-gfx] [PATCH 04/12] drm/i915/bdw: Add ppgtt info for dynamic pages
On Fri, Feb 20, 2015 at 11:15 PM, Michel Thierry
wrote:
> From: Ben Widawsky
>
> Note that there is no gen8 ppgtt debug_dump function yet.
>
> Signed-off-by: Ben Widawsky
> Signed-off-by: Michel Thierry
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 19 ++-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 32
> drivers/gpu/drm/i915/i915_gem_gtt.h | 9 +
> 3 files changed, 51 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 40630bd..93c34ab 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2165,7 +2165,6 @@ static void gen6_ppgtt_info(struct seq_file *m, struct
> drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_engine_cs *ring;
> - struct drm_file *file;
> int i;
>
> if (INTEL_INFO(dev)->gen == 6)
> @@ -2189,14 +2188,6 @@ static void gen6_ppgtt_info(struct seq_file *m, struct
> drm_device *dev)
>
> ppgtt->debug_dump(ppgtt, m);
> }
> -
> - list_for_each_entry_reverse(file, &dev->filelist, lhead) {
> - struct drm_i915_file_private *file_priv = file->driver_priv;
> -
> - seq_printf(m, "proc: %s\n",
> - get_pid_task(file->pid, PIDTYPE_PID)->comm);
> - idr_for_each(&file_priv->context_idr, per_file_ctx, m);
> - }
> }
>
> static int i915_ppgtt_info(struct seq_file *m, void *data)
> @@ -2204,6 +2195,7 @@ static int i915_ppgtt_info(struct seq_file *m, void
> *data)
> struct drm_info_node *node = m->private;
> struct drm_device *dev = node->minor->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_file *file;
>
> int ret = mutex_lock_interruptible(&dev->struct_mutex);
> if (ret)
> @@ -2215,6 +2207,15 @@ static int i915_ppgtt_info(struct seq_file *m, void
> *data)
> else if (INTEL_INFO(dev)->gen >= 6)
> gen6_ppgtt_info(m, dev);
>
> + list_for_each_entry_reverse(file, &dev->filelist, lhead) {
> + struct drm_i915_file_private *file_priv = file->driver_priv;
> +
> + seq_printf(m, "\nproc: %s\n",
> + get_pid_task(file->pid, PIDTYPE_PID)->comm);
> + idr_for_each(&file_priv->context_idr, per_file_ctx,
> +(void *)(unsigned long)m);
> + }
> +
> intel_runtime_pm_put(dev_priv);
> mutex_unlock(&dev->struct_mutex);
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index ecfb62a..1edcc17 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2125,6 +2125,38 @@ static void gen8_ggtt_clear_range(struct
> i915_address_space *vm,
> readl(gtt_base);
> }
>
> +void gen8_for_every_pdpe_pde(struct i915_hw_ppgtt *ppgtt,
> +void (*callback)(struct
> i915_page_directory_pointer_entry *pdp,
> + struct
> i915_page_directory_entry *pd,
> + struct i915_page_table_entry
> *pt,
> + unsigned pdpe,
> + unsigned pde,
> + void *data),
> +void *data)
> +{
> + uint64_t start = ppgtt->base.start;
> + uint64_t length = ppgtt->base.total;
> + uint64_t pdpe, pde, temp;
> +
> + struct i915_page_directory_entry *pd;
> + struct i915_page_table_entry *pt;
> +
> + gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
> + uint64_t pd_start = start, pd_length = length;
> + int i;
> +
> + if (pd == NULL) {
> + for (i = 0; i < GEN8_PDES_PER_PAGE; i++)
> + callback(&ppgtt->pdp, NULL, NULL, pdpe, i,
> data);
> + continue;
> + }
> +
> + gen8_for_each_pde(pt, pd, pd_start, pd_length, temp, pde) {
> + callback(&ppgtt->pdp, pd, pt, pdpe, pde, data);
> + }
> + }
> +}
> +
> static void gen6_ggtt_clear_range(struct i915_address_space *vm,
> uint64_t start,
> uint64_t length,
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
> b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index a33c6e9..144858e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -483,6 +483,15 @@ static inline size_t gen8_pde_count(uint64_t addr,
> uint64_t length)
> return i915_pde_index(end, GEN8_PDE_SHIFT) - i915_pde_index(addr,
> GEN8_PDE_SHIFT);
> }
>
> +void gen8_for_every_pdpe_pde(struct i915_
Re: [Intel-gfx] [PATCH] drm/i915: Add debugfs entry for DRRS
On Monday 23 February 2015 11:49 PM, Rodrigo Vivi wrote:
On Mon, Feb 23, 2015 at 4:05 AM, Ramalingam C wrote:
From: Vandana Kannan
Adding a debugfs entry to determine if DRRS is supported or not
V2: [By Ram]: Following details about the active crtc will be filled
in seq-file of the debugfs
1. Encoder output type
2. DRRS Support on this CRTC
3. DRRS current state
4. Current Vrefresh
Format is as follows:
CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_HIGH_RR,
Vrefresh: 60
CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_LOW_RR,
Vrefresh: 40
CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
V3: [By Ram]: Readability is improved.
Another error case is covered [Daniel]
V4: [By Ram]: Current status of the Idleness DRRS along with
the Front buffer bits are added to the debugfs. [Rodrigo]
V5: [By Ram]: Rephrased to make it easy to understand.
And format is modified. [Rodrigo]
Signed-off-by: Vandana Kannan
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_debugfs.c | 113 +++
1 file changed, 113 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 164fa82..e51001c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2869,6 +2869,118 @@ static int i915_ddb_info(struct seq_file *m, void
*unused)
return 0;
}
+static void drrs_status_per_crtc(struct seq_file *m,
+ struct drm_device *dev, struct intel_crtc *intel_crtc)
+{
+ struct intel_encoder *intel_encoder;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct i915_drrs *drrs = &dev_priv->drrs;
+ int vrefresh = 0;
+ u32 work_status;
+
+ for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
+ /* Encoder connected on this CRTC */
+ switch (intel_encoder->type) {
+ case INTEL_OUTPUT_EDP:
+ seq_puts(m, "eDP:\n");
+ break;
+ case INTEL_OUTPUT_DSI:
+ seq_puts(m, "DSI:\n");
+ break;
+ case INTEL_OUTPUT_HDMI:
+ seq_puts(m, "HDMI:\n");
+ break;
+ case INTEL_OUTPUT_DISPLAYPORT:
+ seq_puts(m, "DP:\n");
+ break;
+ default:
+ seq_printf(m, "Other encoder (id=%d).\n",
+ intel_encoder->type);
+ return;
+ }
+ }
+
+ if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
+ seq_puts(m, "\tVBT: DRRS_type: Static");
+ else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
+ seq_puts(m, "\tVBT: DRRS_type: Seamless");
+ else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
+ seq_puts(m, "\tVBT: DRRS_type: None");
+ else
+ seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
+
+ seq_puts(m, "\n\n");
+
+ if (intel_crtc->config->has_drrs) {
+ struct intel_panel *panel;
+
+ panel = &drrs->dp->attached_connector->panel;
+ /* DRRS Supported */
+ seq_puts(m, "\tDRRS Supported: Yes\n");
+ seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
+ drrs->busy_frontbuffer_bits);
+
+ seq_puts(m, "\n\t\t");
+ work_status = work_busy(&drrs->work.work);
+ if (drrs->busy_frontbuffer_bits) {
+ seq_puts(m, "Front buffer: Busy.\n");
+ seq_puts(m, "\t\tIdleness DRRS: Disabled");
+ } else {
+ seq_puts(m, "Front buffer: Idle");
+ seq_puts(m, "\n\t\t");
+ if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
+ if (work_status)
Why do you need to check work_busy here?
This is to capture the DRRS disabled state due to function
intel_edp_drrs_disable.
+ seq_puts(m, "Idleness DRRS: Enabled");
+ else
+ seq_puts(m, "Idleness DRRS: Disabled");
+ } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
+ seq_puts(m, "Idleness DRRS: Enabled");
+ }
+ }
+
+ seq_puts(m, "\n\t\t");
+ if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
+ seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
+ vrefresh = panel->fixed_mode->vrefresh;
+ } else if (drrs->refresh_rate_ty
[Intel-gfx] [PATCH] drm/i915: Fix trivial typos in comments and warning message
Change 'mutliple' to 'multiple'
Change 'mutlipler' to 'multiplier'
Change 'Haswel' to 'Haswell'
Signed-off-by: Yannick Guerrini
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h| 2 +-
drivers/gpu/drm/i915/intel_sdvo.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 85a6ada..213a261 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1518,7 +1518,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
* - The batch is already pinned into the relevant ppgtt, so we
* already have the backing storage fully allocated.
* - No other BO uses the global gtt (well contexts, but meh),
-* so we don't really have issues with mutliple objects not
+* so we don't really have issues with multiple objects not
* fitting due to fragmentation.
* So this is actually safe.
*/
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 55143cb..56b97c4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3019,7 +3019,7 @@ enum skl_disp_power_wells {
/* Video Data Island Packet control */
#define VIDEO_DIP_DATA 0x61178
-/* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
+/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
* (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each
byte
* of the infoframe structure specified by CEA-861. */
#define VIDEO_DIP_DATA_SIZE 32
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c
b/drivers/gpu/drm/i915/intel_sdvo.c
index 64ad2b4..9e554c2 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1247,7 +1247,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder
*intel_encoder)
switch (crtc->config->pixel_multiplier) {
default:
- WARN(1, "unknown pixel mutlipler specified\n");
+ WARN(1, "unknown pixel multiplier specified\n");
case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
--
1.9.5.msysgit.0
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[Intel-gfx] Intel Driver graphics - Failure
Hello, I installed the Ubuntu 14.04 based derivate Mint L. 17.1. I tried your installer on the web page. The installer denied the installing stating the false Os is installed. Could do me favour and add The Mint derivate to the installer. Would be great. In the moment my resolution is not correct and can't be adjusted to the right.Thanks in advance. Markus ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/12] drm/i915/bdw: implement alloc/free for 4lvl
On Fri, Feb 20, 2015 at 11:15 PM, Michel Thierry
wrote:
> From: Ben Widawsky
>
> The code for 4lvl works just as one would expect, and nicely it is able
> to call into the existing 3lvl page table code to handle all of the
> lower levels.
>
> PML4 has no special attributes, and there will always be a PML4.
> So simply initialize it at creation, and destroy it at the end.
>
> v2: Return something at the end of gen8_alloc_va_range_4lvl to keep the
> compiler happy. And define ret only in one place.
> Updated gen8_ppgtt_unmap_pages and gen8_ppgtt_free to handle 4lvl.
>
> Signed-off-by: Ben Widawsky
> Signed-off-by: Michel Thierry (v2)
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 240
> +++-
> drivers/gpu/drm/i915/i915_gem_gtt.h | 11 +-
> 2 files changed, 217 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 1edcc17..edada33 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -483,9 +483,12 @@ static void __pdp_fini(struct
> i915_page_directory_pointer_entry *pdp)
> static void unmap_and_free_pdp(struct i915_page_directory_pointer_entry *pdp,
> struct drm_device *dev)
> {
> - __pdp_fini(pdp);
> - if (USES_FULL_48BIT_PPGTT(dev))
> + if (USES_FULL_48BIT_PPGTT(dev)) {
> + __pdp_fini(pdp);
Call to __pdp_fini should be made for the 32 bit also.
The 'used_pdpes' bitmap & 'page_directory' double pointer needs to be freed
in 32 bit case also (allocated inside __pdp_init, called from
gen8_ppgtt_init_common).
> + i915_dma_unmap_single(pdp, dev);
> + __free_page(pdp->page);
> kfree(pdp);
> + }
> }
>
> static int __pdp_init(struct i915_page_directory_pointer_entry *pdp,
> @@ -511,6 +514,60 @@ static int __pdp_init(struct
> i915_page_directory_pointer_entry *pdp,
> return 0;
> }
>
> +static struct i915_page_directory_pointer_entry *alloc_pdp_single(struct
> i915_hw_ppgtt *ppgtt,
> + struct i915_pml4 *pml4)
> +{
> + struct drm_device *dev = ppgtt->base.dev;
> + struct i915_page_directory_pointer_entry *pdp;
> + int ret;
> +
> + BUG_ON(!USES_FULL_48BIT_PPGTT(dev));
> +
> + pdp = kmalloc(sizeof(*pdp), GFP_KERNEL);
> + if (!pdp)
> + return ERR_PTR(-ENOMEM);
> +
> + pdp->page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
> + if (!pdp->page) {
> + kfree(pdp);
> + return ERR_PTR(-ENOMEM);
> + }
> +
> + ret = __pdp_init(pdp, dev);
> + if (ret) {
> + __free_page(pdp->page);
> + kfree(pdp);
> + return ERR_PTR(ret);
> + }
> +
> + i915_dma_map_px_single(pdp, dev);
> +
> + return pdp;
> +}
> +
> +static void pml4_fini(struct i915_pml4 *pml4)
> +{
> + struct i915_hw_ppgtt *ppgtt =
> + container_of(pml4, struct i915_hw_ppgtt, pml4);
> + i915_dma_unmap_single(pml4, ppgtt->base.dev);
> + __free_page(pml4->page);
> + /* HACK */
> + pml4->page = NULL;
> +}
> +
> +static int pml4_init(struct i915_hw_ppgtt *ppgtt)
> +{
> + struct i915_pml4 *pml4 = &ppgtt->pml4;
> +
> + pml4->page = alloc_page(GFP_KERNEL | __GFP_ZERO);
> + if (!pml4->page)
> + return -ENOMEM;
> +
> + i915_dma_map_px_single(pml4, ppgtt->base.dev);
> +
> + return 0;
> +}
> +
> /* Broadwell Page Directory Pointer Descriptors */
> static int gen8_write_pdp(struct intel_engine_cs *ring,
> unsigned entry,
> @@ -712,14 +769,13 @@ static void gen8_free_page_tables(struct
> i915_page_directory_entry *pd, struct d
> }
> }
>
> -static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
> +static void gen8_ppgtt_unmap_pages_3lvl(struct
> i915_page_directory_pointer_entry *pdp,
> + struct drm_device *dev)
> {
> - struct pci_dev *hwdev = ppgtt->base.dev->pdev;
> - struct i915_page_directory_pointer_entry *pdp = &ppgtt->pdp; /*
> FIXME: 48b */
> + struct pci_dev *hwdev = dev->pdev;
> int i, j;
>
> - for_each_set_bit(i, pdp->used_pdpes,
> - I915_PDPES_PER_PDP(ppgtt->base.dev)) {
> + for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
> struct i915_page_directory_entry *pd;
>
> if (WARN_ON(!pdp->page_directory[i]))
> @@ -747,27 +803,73 @@ static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt
> *ppgtt)
> }
> }
>
> -static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
> +static void gen8_ppgtt_unmap_pages_4lvl(struct i915_hw_ppgtt *ppgtt)
> {
> + struct pci_dev *hwdev = ppgtt->base.dev->pdev;
> int i;
>
> - if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
> - for_each_s
[Intel-gfx] [PATCH] drm/i915: Changes for calculating dsi clk for CHT
Depending on the correct refclk, n ,p for CHT, calculate
the dsi clk during readout DSI HW state.
Signed-off-by: Gaurav K Singh
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 5e44c9b..c7d55e8 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -357,9 +357,17 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int
pipe_bpp)
u32 m = 0, p = 0;
int refclk = 25000;
int i;
+ u32 n = 1;
+ u32 m_start = 62;
DRM_DEBUG_KMS("\n");
+ if (IS_CHERRYVIEW(dev_priv->dev)) {
+ refclk = 10;
+ n = 4;
+ m_start = 70;
+ }
+
mutex_lock(&dev_priv->dpio_lock);
pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
@@ -394,9 +402,9 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int
pipe_bpp)
return 0;
}
- m = i + 62;
+ m = i + m_start;
- dsi_clock = (m * refclk) / p;
+ dsi_clock = (m * refclk) / (p * n);
/* pixel_format and pipe_bpp should agree */
assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
--
1.7.9.5
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Re: [Intel-gfx] [PATCH 06/12] drm/i915/bdw: Add 4 level switching infrastructure
On Fri, Feb 20, 2015 at 11:16 PM, Michel Thierry
wrote:
> From: Ben Widawsky
>
> Map is easy, it's the same register as the PDP descriptor 0, but it only
> has one entry.
>
> v2: PML4 update in legacy context switch is left for historic reasons,
> the preferred mode of operation is with lrc context based submission.
>
> Signed-off-by: Ben Widawsky
> Signed-off-by: Michel Thierry
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 56
> +
> drivers/gpu/drm/i915/i915_gem_gtt.h | 4 ++-
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 3 files changed, 55 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index edada33..fb06f67 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -192,6 +192,9 @@ static inline gen8_ppgtt_pde_t gen8_pde_encode(struct
> drm_device *dev,
> return pde;
> }
>
> +#define gen8_pdpe_encode gen8_pde_encode
> +#define gen8_pml4e_encode gen8_pde_encode
> +
> static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
> enum i915_cache_level level,
> bool valid, u32 unused)
> @@ -592,8 +595,8 @@ static int gen8_write_pdp(struct intel_engine_cs *ring,
> return 0;
> }
>
> -static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
> - struct intel_engine_cs *ring)
> +static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt,
> +struct intel_engine_cs *ring)
> {
> int i, ret;
>
> @@ -610,6 +613,12 @@ static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
> return 0;
> }
>
> +static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
> + struct intel_engine_cs *ring)
> +{
> + return gen8_write_pdp(ring, 0, ppgtt->pml4.daddr);
> +}
> +
> static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
>uint64_t start,
>uint64_t length,
> @@ -753,6 +762,37 @@ static void gen8_map_pagetable_range(struct
> i915_address_space *vm,
> kunmap_atomic(page_directory);
> }
>
> +static void gen8_map_page_directory(struct i915_page_directory_pointer_entry
> *pdp,
> + struct i915_page_directory_entry *pd,
> + int index,
> + struct drm_device *dev)
> +{
> + gen8_ppgtt_pdpe_t *page_directorypo;
> + gen8_ppgtt_pdpe_t pdpe;
> +
> + /* We do not need to clflush because no platform requiring flush
> +* supports 64b pagetables. */
Would be more appropriate to place this comment, either after the ‘if’
condition or
at the end of the function (where clflush would have been placed, had
LLC not been there for platforms supporting 64 bit).
And same comment can be probably added, at the end of
gen8_map_page_directory_pointer function also.
> + if (!USES_FULL_48BIT_PPGTT(dev))
> + return;
> +
> + page_directorypo = kmap_atomic(pdp->page);
> + pdpe = gen8_pdpe_encode(dev, pd->daddr, I915_CACHE_LLC);
> + page_directorypo[index] = pdpe;
> + kunmap_atomic(page_directorypo);
> +}
> +
> +static void gen8_map_page_directory_pointer(struct i915_pml4 *pml4,
> + struct
> i915_page_directory_pointer_entry *pdp,
> + int index,
> + struct drm_device *dev)
> +{
> + gen8_ppgtt_pml4e_t *pagemap = kmap_atomic(pml4->page);
> + gen8_ppgtt_pml4e_t pml4e = gen8_pml4e_encode(dev, pdp->daddr,
> I915_CACHE_LLC);
> + BUG_ON(!USES_FULL_48BIT_PPGTT(dev));
> + pagemap[index] = pml4e;
> + kunmap_atomic(pagemap);
> +}
> +
> static void gen8_free_page_tables(struct i915_page_directory_entry *pd,
> struct drm_device *dev)
> {
> int i;
> @@ -1124,6 +1164,7 @@ static int gen8_alloc_va_range_3lvl(struct
> i915_address_space *vm,
>
> set_bit(pdpe, pdp->used_pdpes);
> gen8_map_pagetable_range(vm, pd, start, length);
> + gen8_map_page_directory(pdp, pd, pdpe, dev);
> }
>
> free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
> @@ -1192,6 +1233,8 @@ static int gen8_alloc_va_range_4lvl(struct
> i915_address_space *vm,
> ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length);
> if (ret)
> goto err_out;
> +
> + gen8_map_page_directory_pointer(pml4, pdp, pml4e, vm->dev);
> }
>
> bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es,
> @@ -1251,14 +1294,14 @@ static int gen8_ppgtt_init_common(struct
> i915_hw_ppgtt *ppgtt, uint64_t size)
> ppgtt->base.cleanup = gen8_ppgtt_cleanup;
> ppgtt->base.insert_entries = gen8_ppgtt
Re: [Intel-gfx] i915 driver doesn't find all Modelines that nouveau driver finds
On Mon, Mar 02, 2015 at 03:16:16PM -0500, Brian J. Murrell wrote: > On Mon, 2015-03-02 at 20:44 +0200, Ville Syrjälä wrote: > > On Mon, Mar 02, 2015 at 07:07:47PM +0100, Daniel Vetter wrote: > > > On Mon, Mar 02, 2015 at 11:33:39AM -0500, Brian J. Murrell wrote: > > > > > > > > [ 50.508381] [drm:drm_mode_debug_printmodeline] Modeline > > > > 27:"1600x1200" 0 202500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 > > > > [ 50.508383] [drm:drm_mode_prune_invalid] Not using 1600x1200 mode 15 > > > > [ 50.508385] [drm:drm_mode_debug_printmodeline] Modeline > > > > 28:"1600x1200" 0 189000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 > > > > [ 50.508385] [drm:drm_mode_prune_invalid] Not using 1600x1200 mode 15 > > > > [ 50.508387] [drm:drm_mode_debug_printmodeline] Modeline > > > > 66:"1400x1050" 0 179500 1400 1504 1656 1912 1050 1053 1057 1105 0x40 0x6 > > > > [ 50.508388] [drm:drm_mode_prune_invalid] Not using 1400x1050 mode 15 > > > > [ 50.508390] [drm:drm_mode_debug_printmodeline] Modeline > > > > 71:"1600x1200" 0 175500 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 > > > > [ 50.508390] [drm:drm_mode_prune_invalid] Not using 1600x1200 mode 15 > > > > > > > The <180MHz modes are dropped only due to the +5% we add to account for SSC > > on > > FDI. I wonder if we really need that much? > > I guess this would get me the "71" modeline but not the "27" one. Any > idea what refresh rate that "71" would be at? I forget how to do all of > that video timing math. 175500*1000/2160/1250 = 65 Oh that's an a CRT monitor you have there. Been a while since I've come across one of those :) 65Hz on a CRT sounds like a good way to get a headache to me. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915: DP link training optimization
This is a first of series patches that optimize DP link
training. The first patch is for eDP only where we reuse
the previously trained link training values from cache
i.e. voltage swing and pre-emphasis levels.
In case we are not able to train the link by reusing
the known values, the link training parameters are set
to zero and training is restarted.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_dp.c | 75 +++-
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 67 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d1141d3..9497eb6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3294,6 +3294,25 @@ intel_dp_reset_link_train(struct intel_dp *intel_dp,
uint32_t *DP,
}
static bool
+intel_dp_reuse_link_train(struct intel_dp *intel_dp, uint32_t *DP,
+ uint8_t dp_train_pat)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ intel_dp_set_signal_levels(intel_dp, DP);
+
+ I915_WRITE(intel_dp->output_reg, *DP);
+ POSTING_READ(intel_dp->output_reg);
+
+ drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
+ intel_dp->train_set, intel_dp->lane_count);
+
+ return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
+}
+
+static bool
intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
const uint8_t link_status[DP_LINK_STATUS_SIZE])
{
@@ -3356,6 +3375,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
int voltage_tries, loop_tries;
uint32_t DP = intel_dp->DP;
uint8_t link_config[2];
+ uint8_t link_status[DP_LINK_STATUS_SIZE];
if (HAS_DDI(dev))
intel_ddi_prepare_link_retrain(encoder);
@@ -3373,20 +3393,33 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
DP |= DP_PORT_EN;
- /* clock recovery */
- if (!intel_dp_reset_link_train(intel_dp, &DP,
- DP_TRAINING_PATTERN_1 |
- DP_LINK_SCRAMBLING_DISABLE)) {
- DRM_ERROR("failed to enable link training\n");
- return;
+ /*
+* check if eDP has already trained. Reset voltage swing and
+* pre-emphasis levels if that's not the case.
+*/
+ if (intel_dp->link_trained) {
+ DRM_DEBUG_KMS("reuse current link train set\n");
+ if (!intel_dp_reuse_link_train(intel_dp, &DP,
+ DP_TRAINING_PATTERN_1 |
+ DP_LINK_SCRAMBLING_DISABLE)) {
+ DRM_DEBUG_KMS("failed to set link training\n");
+ return;
+ }
+ } else {
+ /* reset link training values */
+ DRM_DEBUG_KMS("reset link train set\n");
+ if (!intel_dp_reset_link_train(intel_dp, &DP,
+ DP_TRAINING_PATTERN_1 |
+ DP_LINK_SCRAMBLING_DISABLE)) {
+ DRM_ERROR("failed to enable link training\n");
+ return;
+ }
}
voltage = 0xff;
voltage_tries = 0;
loop_tries = 0;
for (;;) {
- uint8_t link_status[DP_LINK_STATUS_SIZE];
-
drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
if (!intel_dp_get_link_status(intel_dp, link_status)) {
DRM_ERROR("failed to get link status\n");
@@ -3398,6 +3431,24 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
break;
}
+ /*
+* if we used previously trained voltage and pre-emphasis values
+* and we don't get clock recovery, reset link training values
+*/
+ if (intel_dp->link_trained) {
+ DRM_DEBUG_KMS("clock recovery not ok, reset");
+ if (!intel_dp_reset_link_train(intel_dp, &DP,
+ DP_TRAINING_PATTERN_1 |
+
DP_LINK_SCRAMBLING_DISABLE)) {
+ DRM_ERROR("failed to enable link training\n");
+ return;
+ }
+
+ /* clear the flag as we are not reusing train set */
+ intel_dp->link_trained = false;
+ continue;
+ }
+
/* Check to see if we've tried the max voltage */
for (i = 0; i < intel_dp->lane_count; i++)
Re: [Intel-gfx] [PATCH 07/12] drm/i915/bdw: Support 64 bit PPGTT in lrc mode
On Fri, Feb 20, 2015 at 11:16 PM, Michel Thierry
wrote:
> In 64b (48bit canonical) PPGTT addressing, the PDP0 register contains
> the base address to PML4, while the other PDP registers are ignored.
>
> Also, the addressing mode must be specified in every context descriptor.
>
> Signed-off-by: Michel Thierry
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 167
> ++-
> 1 file changed, 114 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index f461631..2b6d262 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -255,7 +255,8 @@ u32 intel_execlists_ctx_id(struct drm_i915_gem_object
> *ctx_obj)
> }
>
> static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
> -struct drm_i915_gem_object *ctx_obj)
> +struct drm_i915_gem_object *ctx_obj,
> +bool legacy_64bit_ctx)
The 'legacy_64bit_ctx' flag can be derived within the
execlists_ctx_descriptor function also,
through USES_FULL_48BIT_PPGTT macro, as 'dev' pointer is already available.
Doing so, will avoid the modification of function’s prototype and
modification to ‘execlists_elsp_write’.
> {
> struct drm_device *dev = ring->dev;
> uint64_t desc;
> @@ -264,7 +265,10 @@ static uint64_t execlists_ctx_descriptor(struct
> intel_engine_cs *ring,
> WARN_ON(lrca & 0x0FFFULL);
>
> desc = GEN8_CTX_VALID;
> - desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
> + if (legacy_64bit_ctx)
> + desc |= LEGACY_64B_CONTEXT << GEN8_CTX_MODE_SHIFT;
> + else
> + desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
> desc |= GEN8_CTX_L3LLC_COHERENT;
> desc |= GEN8_CTX_PRIVILEGE;
> desc |= lrca;
> @@ -292,16 +296,17 @@ static void execlists_elsp_write(struct intel_engine_cs
> *ring,
> struct drm_i915_private *dev_priv = dev->dev_private;
> uint64_t temp = 0;
> uint32_t desc[4];
> + bool legacy_64bit_ctx = USES_FULL_48BIT_PPGTT(dev);
>
> /* XXX: You must always write both descriptors in the order below. */
> if (ctx_obj1)
> - temp = execlists_ctx_descriptor(ring, ctx_obj1);
> + temp = execlists_ctx_descriptor(ring, ctx_obj1,
> legacy_64bit_ctx);
> else
> temp = 0;
> desc[1] = (u32)(temp >> 32);
> desc[0] = (u32)temp;
>
> - temp = execlists_ctx_descriptor(ring, ctx_obj0);
> + temp = execlists_ctx_descriptor(ring, ctx_obj0, legacy_64bit_ctx);
> desc[3] = (u32)(temp >> 32);
> desc[2] = (u32)temp;
>
> @@ -332,37 +337,60 @@ static int execlists_update_context(struct
> drm_i915_gem_object *ctx_obj,
> reg_state[CTX_RING_TAIL+1] = tail;
> reg_state[CTX_RING_BUFFER_START+1] =
> i915_gem_obj_ggtt_offset(ring_obj);
>
> - /* True PPGTT with dynamic page allocation: update PDP registers and
> -* point the unallocated PDPs to the scratch page
> -*/
> - if (ppgtt) {
> + if (ppgtt && USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
> + /* True 64b PPGTT (48bit canonical)
> +* PDP0_DESCRIPTOR contains the base address to PML4 and
> +* other PDP Descriptors are ignored
> +*/
> + reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pml4.daddr);
> + reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pml4.daddr);
> + } else if (ppgtt) {
> + /* True 32b PPGTT with dynamic page allocation: update PDP
> +* registers and point the unallocated PDPs to the scratch
> page
> +*/
> if (test_bit(3, ppgtt->pdp.used_pdpes)) {
> - reg_state[CTX_PDP3_UDW+1] =
> upper_32_bits(ppgtt->pdp.page_directory[3]->daddr);
> - reg_state[CTX_PDP3_LDW+1] =
> lower_32_bits(ppgtt->pdp.page_directory[3]->daddr);
> + reg_state[CTX_PDP3_UDW+1] =
> +
> upper_32_bits(ppgtt->pdp.page_directory[3]->daddr);
> + reg_state[CTX_PDP3_LDW+1] =
> +
> lower_32_bits(ppgtt->pdp.page_directory[3]->daddr);
> } else {
> - reg_state[CTX_PDP3_UDW+1] =
> upper_32_bits(ppgtt->scratch_pd->daddr);
> - reg_state[CTX_PDP3_LDW+1] =
> lower_32_bits(ppgtt->scratch_pd->daddr);
> + reg_state[CTX_PDP3_UDW+1] =
> +
> upper_32_bits(ppgtt->scratch_pd->daddr);
> + reg_state[CTX_PDP3_LDW+1] =
> +
> lower_32_bits(ppgtt->scratch_pd->daddr);
> }
> if (test_bit(2, ppgtt->pdp.used_p
Re: [Intel-gfx] i915 driver doesn't find all Modelines that nouveau driver finds
On Tue, 2015-03-03 at 15:03 +0200, Ville Syrjälä wrote: > > Oh that's an a CRT monitor you have there. Been a while since I've > come across one of those :) Heh. Yeah. I have been in the market to replace it but no good enough deals yet. :-) > 65Hz on a CRT sounds like a good way to > get a headache to me. Worse than the 60Hz that I am stuck with right now though? On paper +5Hz should be slightly better but maybe there is something particular about 65Hz that makes it worse than 60Hz? b. signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/23] drm/i915: Improve staged config logging
When logging that full mode switch is necessary, log which connector,
encoder or crtc has caused it, so it is easier to figure out what is
goind on by just looking at the log.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3417e17..798de7b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11503,7 +11503,9 @@ intel_modeset_stage_output_state(struct drm_device *dev,
if (&connector->new_encoder->base != connector->base.encoder) {
- DRM_DEBUG_KMS("encoder changed, full mode switch\n");
+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full
mode switch\n",
+ connector->base.base.id,
+ connector->base.name);
config->mode_changed = true;
}
}
@@ -11554,7 +11556,9 @@ intel_modeset_stage_output_state(struct drm_device *dev,
/* Only now check for crtc changes so we don't miss encoders
* that will be disabled. */
if (&encoder->new_crtc->base != encoder->base.crtc) {
- DRM_DEBUG_KMS("crtc changed, full mode switch\n");
+ DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode
switch\n",
+ encoder->base.base.id,
+ encoder->base.name);
config->mode_changed = true;
}
}
@@ -11575,7 +11579,8 @@ intel_modeset_stage_output_state(struct drm_device *dev,
}
if (crtc->new_enabled != crtc->base.state->enable) {
- DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
+ DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
+ crtc->base.base.id,
crtc->new_enabled ? "en" : "dis");
config->mode_changed = true;
}
--
2.1.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/23] drm/i915: Don't use encoder->new_crtc in intel_modeset_pipe_config()
Move towards atomic by using the legacy modeset's drm_atomic_state
instead.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4e90cb4..0dbd20f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10378,8 +10378,11 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
{
struct drm_device *dev = crtc->dev;
struct intel_encoder *encoder;
+ struct intel_connector *connector;
+ struct drm_connector_state *connector_state;
struct intel_crtc_state *pipe_config;
int plane_bpp, ret = -EINVAL;
+ int i;
bool retry = true;
if (!check_encoder_cloning(to_intel_crtc(crtc))) {
@@ -10449,15 +10452,27 @@ encoder_retry:
drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
CRTC_STEREO_DOUBLE);
+ ret = drm_atomic_add_affected_connectors(state, crtc);
+ if (ret) {
+ DRM_DEBUG_KMS("Failed to add affected connectors\n");
+ goto fail;
+ }
+
/* Pass our mode to the connectors and the CRTC to give them a chance to
* adjust it according to limitations or connector properties, and also
* a chance to reject the mode entirely.
*/
- for_each_intel_encoder(dev, encoder) {
+ for (i = 0; i < state->num_connector; i++) {
+ connector = to_intel_connector(state->connectors[i]);
+ if (!connector)
+ continue;
- if (&encoder->new_crtc->base != crtc)
+ connector_state = state->connector_states[i];
+ if (connector_state->crtc != crtc)
continue;
+ encoder = to_intel_encoder(connector_state->best_encoder);
+
if (!(encoder->compute_config(encoder, pipe_config))) {
DRM_DEBUG_KMS("Encoder config failure\n");
goto fail;
--
2.1.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/23] drm/i915: Add a for_each_intel_connector macro
We have similar macros for crtcs and encoders, and the pattern happens
often enough to justify the macro.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/i915_drv.h | 6
drivers/gpu/drm/i915/intel_display.c | 55
drivers/gpu/drm/i915/intel_dp_mst.c | 4 +--
4 files changed, 27 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 6717052..f9b5a97 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2308,8 +2308,7 @@ static int i915_sink_crc(struct seq_file *m, void *data)
u8 crc[6];
drm_modeset_lock_all(dev);
- list_for_each_entry(connector, &dev->mode_config.connector_list,
- base.head) {
+ for_each_intel_encoder(dev, connector) {
if (connector->base.dpms != DRM_MODE_DPMS_ON)
continue;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 92f8300..29c6fbc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -243,6 +243,12 @@ enum hpd_pin {
&(dev)->mode_config.encoder_list, \
base.head)
+#define for_each_intel_connector(dev, intel_connector) \
+ list_for_each_entry(intel_connector,\
+ &dev->mode_config.connector_list, \
+ base.head)
+
+
#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list,
base.head) \
if ((intel_encoder)->base.crtc == (__crtc))
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 589addf..3417e17 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10013,8 +10013,7 @@ static void
intel_modeset_update_staged_output_state(struct drm_device *dev)
struct intel_encoder *encoder;
struct intel_connector *connector;
- list_for_each_entry(connector, &dev->mode_config.connector_list,
- base.head) {
+ for_each_intel_connector(dev, connector) {
connector->new_encoder =
to_intel_encoder(connector->base.encoder);
}
@@ -10045,8 +10044,7 @@ static void intel_modeset_commit_output_state(struct
drm_device *dev)
struct intel_encoder *encoder;
struct intel_connector *connector;
- list_for_each_entry(connector, &dev->mode_config.connector_list,
- base.head) {
+ for_each_intel_connector(dev, connector) {
connector->base.encoder = &connector->new_encoder->base;
}
@@ -10134,8 +10132,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
pipe_config->pipe_bpp = bpp;
/* Clamp display bpp to EDID value */
- list_for_each_entry(connector, &dev->mode_config.connector_list,
- base.head) {
+ for_each_intel_connector(dev, connector) {
if (!connector->new_encoder ||
connector->new_encoder->new_crtc != crtc)
continue;
@@ -10262,8 +10259,7 @@ static bool check_digital_port_conflicts(struct
drm_device *dev)
* list to detect the problem on ddi platforms
* where there's just one encoder per digital port.
*/
- list_for_each_entry(connector,
- &dev->mode_config.connector_list, base.head) {
+ for_each_intel_connector(dev, connector) {
struct intel_encoder *encoder = connector->new_encoder;
if (!encoder)
@@ -10436,8 +10432,7 @@ intel_modeset_affected_pipes(struct drm_crtc *crtc,
unsigned *modeset_pipes,
* to be part of the prepare_pipes mask. We don't (yet) support global
* modeset across multiple crtcs, so modeset_pipes will only have one
* bit set at most. */
- list_for_each_entry(connector, &dev->mode_config.connector_list,
- base.head) {
+ for_each_intel_connector(dev, connector) {
if (connector->base.encoder == &connector->new_encoder->base)
continue;
@@ -10840,8 +10835,7 @@ check_connector_state(struct drm_device *dev)
{
struct intel_connector *connector;
- list_for_each_entry(connector, &dev->mode_config.connector_list,
- base.head) {
+ for_each_intel_connector(dev, connector) {
/* This also checks the encoder/connector hw state with the
* ->get_hw_state callbacks. */
intel_connector_check_state(connector);
@@ -10871,8 +10865,7 @@ check_encoder_state(struct drm_device *dev)
I915_STATE_
[Intel-gfx] [PATCH 13/23] drm/i915: Don't use encoder->new_crtc in compute_baseline_pipe_bpp()
Move towards atomic by using the legacy modeset's drm_atomic_state
instead.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 0dbd20f..9905200 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10159,8 +10159,9 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
+ struct drm_atomic_state *state;
struct intel_connector *connector;
- int bpp;
+ int bpp, i;
switch (fb->pixel_format) {
case DRM_FORMAT_C8:
@@ -10200,10 +10201,13 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
pipe_config->pipe_bpp = bpp;
+ state = pipe_config->base.state;
+
/* Clamp display bpp to EDID value */
- for_each_intel_connector(dev, connector) {
- if (!connector->new_encoder ||
- connector->new_encoder->new_crtc != crtc)
+ for (i = 0; i < state->num_connector; i++) {
+ connector = to_intel_connector(state->connectors[i]);
+ if (!connector ||
+ state->connector_states[i]->crtc != &crtc->base)
continue;
connected_sink_compute_bpp(connector, pipe_config);
--
2.1.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/23] drm/i915: Allocate a drm_atomic_state for the legacy modeset code
For the atomic conversion, the mode set paths need to be changed to rely
on an atomic state instead of using the staged config. By using an
atomic state for the legacy code, we will be able to convert the code
base in small chunks.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 118 +++
1 file changed, 91 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 798de7b..97d4df5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -37,6 +37,7 @@
#include
#include "i915_drv.h"
#include "i915_trace.h"
+#include
#include
#include
#include
@@ -10290,10 +10291,22 @@ static bool check_digital_port_conflicts(struct
drm_device *dev)
return true;
}
-static struct intel_crtc_state *
+static void
+clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
+{
+ struct drm_crtc_state tmp_state;
+
+ /* Clear only the intel specific part of the crtc state */
+ tmp_state = crtc_state->base;
+ memset(crtc_state, 0, sizeof *crtc_state);
+ crtc_state->base = tmp_state;
+}
+
+static int
intel_modeset_pipe_config(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
- struct drm_display_mode *mode)
+ struct drm_display_mode *mode,
+ struct drm_atomic_state *state)
{
struct drm_device *dev = crtc->dev;
struct intel_encoder *encoder;
@@ -10303,17 +10316,19 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
if (!check_encoder_cloning(to_intel_crtc(crtc))) {
DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
- return ERR_PTR(-EINVAL);
+ return -EINVAL;
}
if (!check_digital_port_conflicts(dev)) {
DRM_DEBUG_KMS("rejecting conflicting digital port
configuration\n");
- return ERR_PTR(-EINVAL);
+ return -EINVAL;
}
- pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
- if (!pipe_config)
- return ERR_PTR(-ENOMEM);
+ pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
+ if (IS_ERR(pipe_config))
+ return PTR_ERR(pipe_config);
+
+ clear_intel_crtc_state(pipe_config);
pipe_config->base.crtc = crtc;
drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
@@ -10408,10 +10423,9 @@ encoder_retry:
DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
- return pipe_config;
+ return 0;
fail:
- kfree(pipe_config);
- return ERR_PTR(ret);
+ return ret;
}
/* Computes which crtcs are affected and sets the relevant bits in the mask.
For
@@ -11089,17 +11103,19 @@ static struct intel_crtc_state *
intel_modeset_compute_config(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_framebuffer *fb,
+struct drm_atomic_state *state,
unsigned *modeset_pipes,
unsigned *prepare_pipes,
unsigned *disable_pipes)
{
struct intel_crtc_state *pipe_config = NULL;
+ int ret = 0;
intel_modeset_affected_pipes(crtc, modeset_pipes,
prepare_pipes, disable_pipes);
if ((*modeset_pipes) == 0)
- goto out;
+ return NULL;
/*
* Note this needs changes when we start tracking multiple modes
@@ -11107,14 +11123,17 @@ intel_modeset_compute_config(struct drm_crtc *crtc,
* (i.e. one pipe_config for each crtc) rather than just the one
* for this crtc.
*/
- pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
- if (IS_ERR(pipe_config)) {
- goto out;
- }
+ ret = intel_modeset_pipe_config(crtc, fb, mode, state);
+ if (ret)
+ return ERR_PTR(ret);
+
+ pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
+ if (IS_ERR(pipe_config))
+ return pipe_config;
+
intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
"[modeset]");
-out:
return pipe_config;
}
@@ -11159,6 +11178,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_display_mode *saved_mode;
+ struct intel_crtc_state *crtc_state_copy = NULL;
struct intel_crtc *intel_crtc;
int ret = 0;
@@ -11166,6 +11186,12 @@ static int __intel_set_mode(struct drm_crtc *crtc,
if (!saved_mode)
retu
[Intel-gfx] [PATCH 08/23] drm/i915: Allocate a crtc_state also when the crtc is being disabled
For consistency, allocate a new crtc_state for a crtc that is being
disabled. Previously only the enabled value of the current state would
change.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 36 +---
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 080a197..f020ee5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11153,14 +11153,21 @@ intel_modeset_compute_config(struct drm_crtc *crtc,
unsigned *prepare_pipes,
unsigned *disable_pipes)
{
+ struct drm_device *dev = crtc->dev;
struct intel_crtc_state *pipe_config = NULL;
+ struct intel_crtc *intel_crtc;
int ret = 0;
intel_modeset_affected_pipes(crtc, modeset_pipes,
prepare_pipes, disable_pipes);
- if ((*modeset_pipes) == 0)
- return NULL;
+ for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) {
+ pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
+ if (IS_ERR(pipe_config))
+ return pipe_config;
+
+ pipe_config->base.enable = false;
+ }
/*
* Note this needs changes when we start tracking multiple modes
@@ -11168,18 +11175,25 @@ intel_modeset_compute_config(struct drm_crtc *crtc,
* (i.e. one pipe_config for each crtc) rather than just the one
* for this crtc.
*/
- ret = intel_modeset_pipe_config(crtc, fb, mode, state);
- if (ret)
- return ERR_PTR(ret);
+ for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) {
+ /* FIXME: For now we still expect modeset_pipes has at most
+* one bit set. */
+ if (WARN_ON(&intel_crtc->base != crtc))
+ continue;
- pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
- if (IS_ERR(pipe_config))
- return pipe_config;
+ ret = intel_modeset_pipe_config(crtc, fb, mode, state);
+ if (ret)
+ return ERR_PTR(ret);
+
+ pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
+ if (IS_ERR(pipe_config))
+ return pipe_config;
- intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
- "[modeset]");
+ intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
+ "[modeset]");
+ }
- return pipe_config;
+ return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
}
static int __intel_set_mode_setup_plls(struct drm_device *dev,
--
2.1.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/23] drm/i915: Update dummy connector atomic state with current config
Keep that state updated so that we can write code that depends on it on
the follow up patches.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 41
1 file changed, 32 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f020ee5..108d3d2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10079,6 +10079,27 @@ static void
intel_modeset_update_staged_output_state(struct drm_device *dev)
}
}
+/* Transitional helper to copy current connector/encoder state to
+ * connector->state. This is needed so that code that is partially
+ * converted to atomic does the right thing.
+ */
+static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
+{
+ struct intel_encoder *encoder;
+ struct intel_connector *connector;
+
+ for_each_intel_encoder(dev, encoder) {
+ if (encoder->base.crtc &&
+ to_intel_crtc(encoder->base.crtc)->active)
+
+ for_each_intel_connector(dev, connector) {
+ if (connector->base.encoder != &encoder->base)
+ continue;
+
+ connector->base.state->crtc = encoder->base.crtc;
+ }
+ }
+}
/**
* intel_modeset_commit_output_state
*
@@ -10102,6 +10123,8 @@ static void intel_modeset_commit_output_state(struct
drm_device *dev)
crtc->base.state->enable = crtc->new_enabled;
crtc->base.enabled = crtc->new_enabled;
}
+
+ intel_modeset_update_connector_atomic_state(dev);
}
static void
@@ -12828,15 +12851,13 @@ static void intel_setup_outputs(struct drm_device
*dev)
* be removed since we'll be setting up real connector state, which
* will contain Intel-specific properties.
*/
- if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
- list_for_each_entry(connector,
- &dev->mode_config.connector_list,
- head) {
- if (!WARN_ON(connector->state)) {
- connector->state =
- kzalloc(sizeof(*connector->state),
- GFP_KERNEL);
- }
+ /* FIXME: need to update the comment above. */
+ list_for_each_entry(connector,
+ &dev->mode_config.connector_list,
+ head) {
+ if (!WARN_ON(connector->state)) {
+ connector->state = kzalloc(sizeof(*connector->state),
+ GFP_KERNEL);
}
}
@@ -13891,6 +13912,8 @@ void intel_modeset_setup_hw_state(struct drm_device
*dev,
"[setup_hw_state]");
}
+ intel_modeset_update_connector_atomic_state(dev);
+
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
--
2.1.0
___
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[Intel-gfx] [PATCH 20/23] drm/i915: Use atomic state in pipe_has_enabled_pch()
This function is called indirectly by intel_crtc_compute_config(),
which needs to be converted to work only with an atomic state.
---
I'm not sure what are the implications of ignoring intel_crtc->active in
pipe_has_enabled_pch(). If we allow a config because the third pipe is
enabled but not active, wouldn't we run into trouble when we tried to
activate the crtc?
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 64751b6..518903e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3150,10 +3150,9 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
FDI_FE_ERRC_ENABLE);
}
-static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
+static bool pipe_has_enabled_pch(struct intel_crtc_state *crtc_state)
{
- return crtc->base.state->enable && crtc->active &&
- crtc->config->has_pch_encoder;
+ return crtc_state->base.enable && crtc_state->has_pch_encoder;
}
static void ivb_modeset_global_resources(struct drm_atomic_state *state)
@@ -3164,15 +3163,21 @@ static void ivb_modeset_global_resources(struct
drm_atomic_state *state)
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
struct intel_crtc *pipe_C_crtc =
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
+ struct intel_crtc_state *pipe_B_crtc_state, *pipe_C_crtc_state;
uint32_t temp;
+ pipe_B_crtc_state = intel_atomic_get_crtc_state(state, pipe_B_crtc);
+ pipe_C_crtc_state = intel_atomic_get_crtc_state(state, pipe_C_crtc);
+ if (WARN_ON(IS_ERR(pipe_B_crtc_state) || IS_ERR(pipe_C_crtc_state)))
+ return;
+
/*
* When everything is off disable fdi C so that we could enable fdi B
* with all lanes. Note that we don't care about enabled pipes without
* an enabled pch encoder.
*/
- if (!pipe_has_enabled_pch(pipe_B_crtc) &&
- !pipe_has_enabled_pch(pipe_C_crtc)) {
+ if (!pipe_has_enabled_pch(pipe_B_crtc_state) &&
+ !pipe_has_enabled_pch(pipe_C_crtc_state)) {
WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
@@ -5528,6 +5533,9 @@ static bool ironlake_check_fdi_lanes(struct drm_device
*dev, enum pipe pipe,
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *pipe_B_crtc =
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
+ struct intel_crtc_state *pipe_B_crtc_state =
+ intel_atomic_get_crtc_state(pipe_config->base.state,
+ pipe_B_crtc);
DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
pipe_name(pipe), pipe_config->fdi_lanes);
@@ -5563,8 +5571,8 @@ static bool ironlake_check_fdi_lanes(struct drm_device
*dev, enum pipe pipe,
}
return true;
case PIPE_C:
- if (!pipe_has_enabled_pch(pipe_B_crtc) ||
- pipe_B_crtc->config->fdi_lanes <= 2) {
+ if (!pipe_has_enabled_pch(pipe_B_crtc_state) ||
+ pipe_B_crtc_state->fdi_lanes <= 2) {
if (pipe_config->fdi_lanes > 2) {
DRM_DEBUG_KMS("invalid shared fdi lane config
on pipe %c: %i lanes\n",
pipe_name(pipe),
pipe_config->fdi_lanes);
--
2.1.0
___
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[Intel-gfx] [PATCH 18/23] drm/i915: Don't use encoder->new_crtc in intel_lvds_compute_config()
Move towards atomic by using the legacy modeset's drm_atomic_state instead. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_lvds.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 2b008b02..06d2da3 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -286,7 +286,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, struct intel_connector *intel_connector = &lvds_encoder->attached_connector->base; struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; - struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc; + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); unsigned int lvds_bpp; /* Should never happen!! */ -- 2.1.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/23] drm/i915: Add intel_atomic_get_crtc_state() helper function
The pattern of getting the crtc state with drm_atomic_get_crtc_state()
and then converting it to intel_crtc_state will repeat quite often in
the following patches, so add a helper function to save some typing.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_drv.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 632df1c..c1959e0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -35,6 +35,7 @@
#include
#include
#include
+#include
#define DIV_ROUND_CLOSEST_ULL(ll, d) \
({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
@@ -564,6 +565,7 @@ struct cxsr_latency {
};
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
+#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
#define to_intel_connector(x) container_of(x, struct intel_connector, base)
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
@@ -1273,6 +1275,14 @@ int intel_connector_atomic_get_property(struct
drm_connector *connector,
struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
void intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state);
+static inline struct intel_crtc_state *
+intel_atomic_get_crtc_state(struct drm_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_crtc_state *crtc_state;
+ crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
+ return to_intel_crtc_state(crtc_state);
+}
/* intel_atomic_plane.c */
struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
--
2.1.0
___
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[Intel-gfx] [PATCH 01/23] drm/i915: Set crtc backpointer when duplicating crtc state
In the path were there is no state to duplicate, the allocated crtc
state wouldn't have the crtc backpointer initialized.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_atomic.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index 011b896..3903b90 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -214,12 +214,18 @@ struct drm_crtc_state *
intel_crtc_duplicate_state(struct drm_crtc *crtc)
{
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_crtc_state *crtc_state;
if (WARN_ON(!intel_crtc->config))
- return kzalloc(sizeof(*intel_crtc->config), GFP_KERNEL);
+ crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
+ else
+ crtc_state = kmemdup(intel_crtc->config,
+sizeof(*intel_crtc->config), GFP_KERNEL);
- return kmemdup(intel_crtc->config, sizeof(*intel_crtc->config),
- GFP_KERNEL);
+ if (crtc_state)
+ crtc_state->base.crtc = crtc;
+
+ return &crtc_state->base;
}
/**
--
2.1.0
___
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[Intel-gfx] [PATCH 00/23] Remove depencies on staged config for atomic transition
This patch series starts to remove dependencies from the modeset code to enable the transition to atomic. That is achieved by using an atomic state struct for the legacy modeset, and changing related functiond to depend on it. I wasn't able to test all of the changes, so I'm very interested on PRTS results for this. In particular, I expect support for 3 pipes and the load detect pipe to be problematic. Ander Ander Conselvan de Oliveira (23): drm/i915: Set crtc backpointer when duplicating crtc state drm/i915: Add a for_each_intel_connector macro drm/i915: Improve staged config logging drm/i915: Add intel_atomic_get_crtc_state() helper function drm/i915: Allocate a drm_atomic_state for the legacy modeset code drm/i915: Add an optional atomic state argument to intel_set_mode() drm/i915: Use an atomic state for the load detect modeset drm/i915: Allocate a crtc_state also when the crtc is being disabled drm/i915: Update dummy connector atomic state with current config drm/i915: Implement connector state duplication drm/i915: Copy the staged connector config to the legacy atomic state drm/i915: Don't use encoder->new_crtc in intel_modeset_pipe_config() drm/i915: Don't use encoder->new_crtc in compute_baseline_pipe_bpp() drm/i915: Don't depend on encoder->new_crtc in intel_dp_compute_config() drm/i915: Don't depend on encoder->new_crtc in intel_hdmi_compute_config drm/i915: Use atomic state in intel_ddi_crtc_get_new_encoder() drm/i915: Don't use staged config in intel_dp_mst_compute_config() drm/i915: Don't use encoder->new_crtc in intel_lvds_compute_config() drm/i915: Pass an atomic state to modeset_global_resources() functions drm/i915: Use atomic state in pipe_has_enabled_pch() drm/i915: Convert intel_pipe_will_have_type() to using atomic state drm/i915: Don't look at staged config crtc when changing DRRS state drm/i915: Remove usage of encoder->new_crtc from clock computations drivers/gpu/drm/i915/i915_debugfs.c | 3 +- drivers/gpu/drm/i915/i915_drv.h | 10 +- drivers/gpu/drm/i915/intel_atomic.c | 12 +- drivers/gpu/drm/i915/intel_crt.c | 3 +- drivers/gpu/drm/i915/intel_ddi.c | 24 +- drivers/gpu/drm/i915/intel_display.c | 578 --- drivers/gpu/drm/i915/intel_dp.c | 5 +- drivers/gpu/drm/i915/intel_dp_mst.c | 20 +- drivers/gpu/drm/i915/intel_drv.h | 13 +- drivers/gpu/drm/i915/intel_dsi.c | 1 + drivers/gpu/drm/i915/intel_dvo.c | 1 + drivers/gpu/drm/i915/intel_hdmi.c| 22 +- drivers/gpu/drm/i915/intel_lvds.c| 3 +- drivers/gpu/drm/i915/intel_sdvo.c| 1 + drivers/gpu/drm/i915/intel_tv.c | 3 +- 15 files changed, 492 insertions(+), 207 deletions(-) -- 2.1.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/23] drm/i915: Add an optional atomic state argument to intel_set_mode()
In the set config modeset path, the atomic state is updated when
changing the staged config in intel_modeset_stage_output_config(). The
load detect code also causes a modeset, but it changes the staged config
before calling intel_set_mode(). A follow up patch will change that
function to also update a drm_atomic_state, and it will need to be able
to pass that to intel_set_mode().
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 97d4df5..3c3b5b2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -83,7 +83,8 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config);
static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
- int x, int y, struct drm_framebuffer *old_fb);
+ int x, int y, struct drm_framebuffer *old_fb,
+ struct drm_atomic_state *state);
static int intel_framebuffer_init(struct drm_device *dev,
struct intel_framebuffer *ifb,
struct drm_mode_fb_cmd2 *mode_cmd,
@@ -8854,7 +8855,7 @@ retry:
goto fail;
}
- if (intel_set_mode(crtc, mode, 0, 0, fb)) {
+ if (intel_set_mode(crtc, mode, 0, 0, fb, NULL)) {
DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
if (old->release_fb)
old->release_fb->funcs->destroy(old->release_fb);
@@ -8898,7 +8899,7 @@ void intel_release_load_detect_pipe(struct drm_connector
*connector,
intel_encoder->new_crtc = NULL;
intel_crtc->new_enabled = false;
intel_crtc->new_config = NULL;
- intel_set_mode(crtc, NULL, 0, 0, NULL);
+ intel_set_mode(crtc, NULL, 0, 0, NULL, NULL);
if (old->release_fb) {
drm_framebuffer_unregister_private(old->release_fb);
@@ -11316,19 +11317,21 @@ static int intel_set_mode_pipes(struct drm_crtc *crtc,
static int intel_set_mode(struct drm_crtc *crtc,
struct drm_display_mode *mode,
- int x, int y, struct drm_framebuffer *fb)
+ int x, int y, struct drm_framebuffer *fb,
+ struct drm_atomic_state *state)
{
struct drm_device *dev = crtc->dev;
- struct drm_atomic_state *state;
struct intel_crtc_state *pipe_config;
unsigned modeset_pipes, prepare_pipes, disable_pipes;
int ret = 0;
- state = drm_atomic_state_alloc(dev);
- if (!state)
- return -ENOMEM;
+ if (!state) {
+ state = drm_atomic_state_alloc(dev);
+ if (!state)
+ return -ENOMEM;
- state->acquire_ctx = dev->mode_config.acquire_ctx;
+ state->acquire_ctx = dev->mode_config.acquire_ctx;
+ }
pipe_config = intel_modeset_compute_config(crtc, mode, fb, state,
&modeset_pipes,
@@ -11353,7 +11356,8 @@ out:
void intel_crtc_restore_mode(struct drm_crtc *crtc)
{
- intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
+ intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb,
+ NULL);
}
#undef for_each_intel_crtc_masked
@@ -11813,7 +11817,8 @@ fail:
/* Try to restore the config */
if (config->mode_changed &&
intel_set_mode(save_set.crtc, save_set.mode,
- save_set.x, save_set.y, save_set.fb))
+ save_set.x, save_set.y, save_set.fb,
+ NULL))
DRM_ERROR("failed to restore config after modeset
failure\n");
}
@@ -13857,7 +13862,7 @@ void intel_modeset_setup_hw_state(struct drm_device
*dev,
dev_priv->pipe_to_crtc_mapping[pipe];
intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
- crtc->primary->fb);
+ crtc->primary->fb, NULL);
}
} else {
intel_modeset_update_staged_output_state(dev);
--
2.1.0
___
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[Intel-gfx] [PATCH 11/23] drm/i915: Copy the staged connector config to the legacy atomic state
With this in place, we can start converting pieces of the modeset code
to look at the connector atomic state instead of the staged config.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 23 ---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 108d3d2..4e90cb4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11607,9 +11607,11 @@ intel_set_config_compute_mode_changes(struct
drm_mode_set *set,
static int
intel_modeset_stage_output_state(struct drm_device *dev,
struct drm_mode_set *set,
-struct intel_set_config *config)
+struct intel_set_config *config,
+struct drm_atomic_state *state)
{
struct intel_connector *connector;
+ struct drm_connector_state *connector_state;
struct intel_encoder *encoder;
struct intel_crtc *crtc;
int ro;
@@ -11673,6 +11675,14 @@ intel_modeset_stage_output_state(struct drm_device
*dev,
}
connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
+ connector_state =
+ drm_atomic_get_connector_state(state, &connector->base);
+ if (IS_ERR(connector_state))
+ return PTR_ERR(connector_state);
+
+ connector_state->crtc = new_crtc;
+ connector_state->best_encoder = &connector->new_encoder->base;
+
DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
connector->base.base.id,
connector->base.name,
@@ -11705,9 +11715,16 @@ intel_modeset_stage_output_state(struct drm_device
*dev,
}
/* Now we've also updated encoder->new_crtc for all encoders. */
for_each_intel_connector(dev, connector) {
- if (connector->new_encoder)
+ connector_state =
+ drm_atomic_get_connector_state(state, &connector->base);
+
+ if (connector->new_encoder) {
if (connector->new_encoder != connector->encoder)
connector->encoder = connector->new_encoder;
+ } else {
+ connector_state->crtc = NULL;
+ }
+
}
for_each_intel_crtc(dev, crtc) {
crtc->new_enabled = false;
@@ -11816,7 +11833,7 @@ static int intel_crtc_set_config(struct drm_mode_set
*set)
state->acquire_ctx = dev->mode_config.acquire_ctx;
- ret = intel_modeset_stage_output_state(dev, set, config);
+ ret = intel_modeset_stage_output_state(dev, set, config, state);
if (ret)
goto fail;
--
2.1.0
___
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[Intel-gfx] [PATCH 07/23] drm/i915: Use an atomic state for the load detect modeset
Create an atomic state and initialize it for the load detect pipe
modesets, so it doesn't break once the rest of the mode set code starts
using atomic states instead of the staged config.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_crt.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 52 +---
drivers/gpu/drm/i915/intel_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_tv.c | 2 +-
4 files changed, 52 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index e66e17a..974534e 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -708,7 +708,7 @@ intel_crt_detect(struct drm_connector *connector, bool
force)
status = connector_status_connected;
else
status = intel_crt_load_detect(crt);
- intel_release_load_detect_pipe(connector, &tmp);
+ intel_release_load_detect_pipe(connector, &tmp, &ctx);
} else
status = connector_status_unknown;
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3c3b5b2..080a197 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8752,6 +8752,8 @@ bool intel_get_load_detect_pipe(struct drm_connector
*connector,
struct drm_device *dev = encoder->dev;
struct drm_framebuffer *fb;
struct drm_mode_config *config = &dev->mode_config;
+ struct drm_atomic_state *state = NULL;
+ struct drm_connector_state *connector_state;
int ret, i = -1;
DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
@@ -8833,6 +8835,21 @@ retry:
old->load_detect_temp = true;
old->release_fb = NULL;
+ state = drm_atomic_state_alloc(dev);
+ if (!state)
+ return false;
+
+ state->acquire_ctx = ctx;
+
+ connector_state = drm_atomic_get_connector_state(state, connector);
+ if (IS_ERR(connector_state)) {
+ ret = PTR_ERR(connector_state);
+ goto fail;
+ }
+
+ connector_state->crtc = crtc;
+ connector_state->best_encoder = &intel_encoder->base;
+
if (!mode)
mode = &load_detect_mode;
@@ -8855,7 +8872,7 @@ retry:
goto fail;
}
- if (intel_set_mode(crtc, mode, 0, 0, fb, NULL)) {
+ if (intel_set_mode(crtc, mode, 0, 0, fb, state)) {
DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
if (old->release_fb)
old->release_fb->funcs->destroy(old->release_fb);
@@ -8873,6 +8890,11 @@ retry:
else
intel_crtc->new_config = NULL;
fail_unlock:
+ if (state) {
+ drm_atomic_state_free(state);
+ state = NULL;
+ }
+
if (ret == -EDEADLK) {
drm_modeset_backoff(ctx);
goto retry;
@@ -8882,24 +8904,41 @@ fail_unlock:
}
void intel_release_load_detect_pipe(struct drm_connector *connector,
- struct intel_load_detect_pipe *old)
+ struct intel_load_detect_pipe *old,
+ struct drm_modeset_acquire_ctx *ctx)
{
struct intel_encoder *intel_encoder =
intel_attached_encoder(connector);
struct drm_encoder *encoder = &intel_encoder->base;
struct drm_crtc *crtc = encoder->crtc;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct drm_atomic_state *state;
+ struct drm_connector_state *connector_state;
DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
connector->base.id, connector->name,
encoder->base.id, encoder->name);
if (old->load_detect_temp) {
+ state = drm_atomic_state_alloc(connector->dev);
+ if (!state)
+ goto fail;
+
+ state->acquire_ctx = ctx;
+
+ connector_state = drm_atomic_get_connector_state(state,
connector);
+ if (IS_ERR(connector_state))
+ goto fail;
+
to_intel_connector(connector)->new_encoder = NULL;
intel_encoder->new_crtc = NULL;
intel_crtc->new_enabled = false;
intel_crtc->new_config = NULL;
- intel_set_mode(crtc, NULL, 0, 0, NULL, NULL);
+
+ connector_state->best_encoder = NULL;
+ connector_state->crtc = NULL;
+
+ intel_set_mode(crtc, NULL, 0, 0, NULL, state);
if (old->release_fb) {
drm_framebuffer_unregister_private(old->release_fb);
@@ -8912,6 +8951,11 @@ void intel_release_load_detect_pipe(struct drm_connector
*connector,
/* Switch crtc and encoder back off if necessary */
[Intel-gfx] [PATCH 17/23] drm/i915: Don't use staged config in intel_dp_mst_compute_config()
Move towards atomic by using the legacy modeset's drm_atomic_state
instead.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_dp_mst.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 5c06a06..b132fe6 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -36,11 +36,11 @@ static bool intel_dp_mst_compute_config(struct
intel_encoder *encoder,
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
struct intel_digital_port *intel_dig_port = intel_mst->primary;
struct intel_dp *intel_dp = &intel_dig_port->dp;
- struct drm_device *dev = encoder->base.dev;
- int bpp;
+ struct drm_atomic_state *state;
+ int bpp, i;
int lane_count, slots;
struct drm_display_mode *adjusted_mode =
&pipe_config->base.adjusted_mode;
- struct intel_connector *found = NULL, *intel_connector;
+ struct intel_connector *found = NULL;
int mst_pbn;
pipe_config->dp_encoder_is_mst = true;
@@ -58,9 +58,14 @@ static bool intel_dp_mst_compute_config(struct intel_encoder
*encoder,
pipe_config->pipe_bpp = 24;
pipe_config->port_clock =
drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
- for_each_intel_connector(dev, intel_connector) {
- if (intel_connector->new_encoder == encoder) {
- found = intel_connector;
+ state = pipe_config->base.state;
+
+ for (i = 0; i < state->num_connector; i++) {
+ if (!state->connectors[i])
+ continue;
+
+ if (state->connector_states[i]->best_encoder == &encoder->base)
{
+ found = to_intel_connector(state->connectors[i]);
break;
}
}
--
2.1.0
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[Intel-gfx] [PATCH 10/23] drm/i915: Implement connector state duplication
So that we can add connector states to the drm_atomic_state used in the
legacy modeset.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_crt.c| 1 +
drivers/gpu/drm/i915/intel_dp.c | 1 +
drivers/gpu/drm/i915/intel_dp_mst.c | 1 +
drivers/gpu/drm/i915/intel_dsi.c| 1 +
drivers/gpu/drm/i915/intel_dvo.c| 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 1 +
drivers/gpu/drm/i915/intel_lvds.c | 1 +
drivers/gpu/drm/i915/intel_sdvo.c | 1 +
drivers/gpu/drm/i915/intel_tv.c | 1 +
9 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 974534e..573aaff 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -794,6 +794,7 @@ static const struct drm_connector_funcs
intel_crt_connector_funcs = {
.destroy = intel_crt_destroy,
.set_property = intel_crt_set_property,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
.atomic_get_property = intel_connector_atomic_get_property,
};
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d1141d3..5accf3f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4398,6 +4398,7 @@ static const struct drm_connector_funcs
intel_dp_connector_funcs = {
.atomic_get_property = intel_connector_atomic_get_property,
.destroy = intel_dp_connector_destroy,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
};
static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
b/drivers/gpu/drm/i915/intel_dp_mst.c
index be12492..5c06a06 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -317,6 +317,7 @@ static const struct drm_connector_funcs
intel_dp_mst_connector_funcs = {
.atomic_get_property = intel_connector_atomic_get_property,
.destroy = intel_dp_mst_connector_destroy,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
};
static int intel_dp_mst_get_modes(struct drm_connector *connector)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index c8c8b24..572251e 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -975,6 +975,7 @@ static const struct drm_connector_funcs
intel_dsi_connector_funcs = {
.fill_modes = drm_helper_probe_single_connector_modes,
.atomic_get_property = intel_connector_atomic_get_property,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
};
void intel_dsi_init(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index d857951..4ccd6c3 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -393,6 +393,7 @@ static const struct drm_connector_funcs
intel_dvo_connector_funcs = {
.fill_modes = drm_helper_probe_single_connector_modes,
.atomic_get_property = intel_connector_atomic_get_property,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
};
static const struct drm_connector_helper_funcs
intel_dvo_connector_helper_funcs = {
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 995c5b2..b13a8be 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1618,6 +1618,7 @@ static const struct drm_connector_funcs
intel_hdmi_connector_funcs = {
.atomic_get_property = intel_connector_atomic_get_property,
.destroy = intel_hdmi_destroy,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
};
static const struct drm_connector_helper_funcs
intel_hdmi_connector_helper_funcs = {
diff --git a/drivers/gpu/drm/i915/intel_lvds.c
b/drivers/gpu/drm/i915/intel_lvds.c
index 24e8730..2b008b02 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -535,6 +535,7 @@ static const struct drm_connector_funcs
intel_lvds_connector_funcs = {
.atomic_get_property = intel_connector_atomic_get_property,
.destroy = intel_lvds_destroy,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
};
static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
diff --git a/drivers/gpu/drm/i91
[Intel-gfx] [PATCH 16/23] drm/i915: Use atomic state in intel_ddi_crtc_get_new_encoder()
Instead of using connector->new_encoder, get the same information from
the pipe_config, thus making the function ready for the atomic
conversion.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_ddi.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 985d531..91e7cb1 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -494,17 +494,23 @@ intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
}
static struct intel_encoder *
-intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc)
+intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = crtc->base.dev;
- struct intel_encoder *intel_encoder, *ret = NULL;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct intel_encoder *ret = NULL;
+ struct drm_atomic_state *state;
int num_encoders = 0;
+ int i;
- for_each_intel_encoder(dev, intel_encoder) {
- if (intel_encoder->new_crtc == crtc) {
- ret = intel_encoder;
- num_encoders++;
- }
+ state = crtc_state->base.state;
+
+ for (i = 0; i < state->num_connector; i++) {
+ if (!state->connectors[i] ||
+ state->connector_states[i]->crtc != crtc_state->base.crtc)
+ continue;
+
+ ret =
to_intel_encoder(state->connector_states[i]->best_encoder);
+ num_encoders++;
}
WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n",
num_encoders,
@@ -1209,7 +1215,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
{
struct drm_device *dev = intel_crtc->base.dev;
struct intel_encoder *intel_encoder =
- intel_ddi_get_crtc_new_encoder(intel_crtc);
+ intel_ddi_get_crtc_new_encoder(crtc_state);
int clock = crtc_state->port_clock;
if (IS_SKYLAKE(dev))
--
2.1.0
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[Intel-gfx] [PATCH 15/23] drm/i915: Don't depend on encoder->new_crtc in intel_hdmi_compute_config
Move towards atomic by using the legacy modeset's drm_atomic_state
instead.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_hdmi.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index b13a8be..cacbafd 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -951,19 +951,30 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
return MODE_OK;
}
-static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
+static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = crtc->base.dev;
+ struct drm_device *dev = crtc_state->base.crtc->dev;
+ struct drm_atomic_state *state;
struct intel_encoder *encoder;
+ struct drm_connector_state *connector_state;
int count = 0, count_hdmi = 0;
+ int i;
if (HAS_GMCH_DISPLAY(dev))
return false;
- for_each_intel_encoder(dev, encoder) {
- if (encoder->new_crtc != crtc)
+ state = crtc_state->base.state;
+
+ for (i = 0; i < state->num_connector; i++) {
+ if (!state->connectors[i])
continue;
+ connector_state = state->connector_states[i];
+ if (connector_state->crtc != crtc_state->base.crtc)
+ continue;
+
+ encoder = to_intel_encoder(connector_state->best_encoder);
+
count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
count++;
}
@@ -1020,7 +1031,7 @@ bool intel_hdmi_compute_config(struct intel_encoder
*encoder,
*/
if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
clock_12bpc <= portclock_limit &&
- hdmi_12bpc_possible(encoder->new_crtc)) {
+ hdmi_12bpc_possible(pipe_config)) {
DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
desired_bpp = 12*3;
--
2.1.0
___
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[Intel-gfx] [PATCH 22/23] drm/i915: Don't look at staged config crtc when changing DRRS state
The function intel_dp_set_drrs_state() would decide which pipe to
downclock based on the staged config for the given connector. However,
the result of that function is immediate, and it uses input values from
crtc->config, so it should be looking at the current crtc instead.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a477e07..6cd4c56 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4785,7 +4785,7 @@ static void intel_dp_set_drrs_state(struct drm_device
*dev, int refresh_rate)
dig_port = dp_to_dig_port(intel_dp);
encoder = &dig_port->base;
- intel_crtc = encoder->new_crtc;
+ intel_crtc = to_intel_crtc(encoder->base.crtc);
if (!intel_crtc) {
DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
--
2.1.0
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Re: [Intel-gfx] i915 when using vaapi, screen only refreshes on mouse movement
On Mon, 2015-03-02 at 14:27 +, Chris Wilson wrote: > > Mixing ZaphodHeads and DRI, Oh wait! You said "mixing" not "missing". But yeah, I'm an old-timer trying to maintain his 20+ year old preference for truly separate screens -- like from way back when even Xinerama didn't even exist. :-) > you probably want to grab -intel-2.99.917 or > linux-4.0. Is that really an either/or? If I were to just update xorg-x11-drv-intel-2.99.916-3.20141117.fc21.x86_64 to 2.99.917 would that solve the problem or do I also need the 4.0 kernel? Cheers, b. signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 19/23] drm/i915: Pass an atomic state to modeset_global_resources() functions
Follow up patches will convert some functions called from there to use
the atomic state, instead of directly accessing the new or current
config. This patch just changes the parameters, but shouldn't have any
functional changes.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 13 -
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 29c6fbc..0c6ba2d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -550,7 +550,7 @@ struct drm_i915_display_funcs {
struct drm_crtc *crtc,
uint32_t sprite_width, uint32_t sprite_height,
int pixel_size, bool enable, bool scaled);
- void (*modeset_global_resources)(struct drm_device *dev);
+ void (*modeset_global_resources)(struct drm_atomic_state *state);
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
bool (*get_pipe_config)(struct intel_crtc *,
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9905200..64751b6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3156,8 +3156,9 @@ static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
crtc->config->has_pch_encoder;
}
-static void ivb_modeset_global_resources(struct drm_device *dev)
+static void ivb_modeset_global_resources(struct drm_atomic_state *state)
{
+ struct drm_device *dev = state->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *pipe_B_crtc =
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
@@ -4845,8 +4846,9 @@ static unsigned long get_crtc_power_domains(struct
drm_crtc *crtc)
return mask;
}
-static void modeset_update_crtc_power_domains(struct drm_device *dev)
+static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
{
+ struct drm_device *dev = state->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
struct intel_crtc *crtc;
@@ -4868,7 +4870,7 @@ static void modeset_update_crtc_power_domains(struct
drm_device *dev)
}
if (dev_priv->display.modeset_global_resources)
- dev_priv->display.modeset_global_resources(dev);
+ dev_priv->display.modeset_global_resources(state);
for_each_intel_crtc(dev, crtc) {
enum intel_display_power_domain domain;
@@ -5083,8 +5085,9 @@ static void valleyview_modeset_global_pipes(struct
drm_device *dev,
*prepare_pipes |= (1 << intel_crtc->pipe);
}
-static void valleyview_modeset_global_resources(struct drm_device *dev)
+static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
{
+ struct drm_device *dev = state->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
int max_pixclk = intel_mode_max_pixclk(dev_priv);
int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
@@ -11350,7 +11353,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
* update the the output configuration. */
intel_modeset_update_state(dev, prepare_pipes);
- modeset_update_crtc_power_domains(dev);
+ modeset_update_crtc_power_domains(pipe_config->base.state);
/* Set up the DPLL and any encoders state that needs to adjust or depend
* on the DPLL.
--
2.1.0
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[Intel-gfx] [PATCH 21/23] drm/i915: Convert intel_pipe_will_have_type() to using atomic state
Pass a crtc_state to it and find whether the pipe has an encoder of a
given type by looking at the drm_atomic_state the crtc_state points to.
Note that is possible to reach i9xx_get_refclk() without a proper atomic
state, since in the function vlv_force_pll_on() a minimally initialized
crtc_state is allocated in the stack. With the current code, it is not
possible to end up in a call to intel_pipe_will_have_type() with that
bogus atomic state. To avoid future problems, a comment is added to warn
people changing that code.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 134 +--
2 files changed, 83 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0c6ba2d..aab4421 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -541,7 +541,7 @@ struct drm_i915_display_funcs {
* Returns true on success, false on failure.
*/
bool (*find_dpll)(const struct intel_limit *limit,
- struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state,
int target, int refclk,
struct dpll *match_clock,
struct dpll *best_clock);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 518903e..f3652f9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -431,25 +431,37 @@ bool intel_pipe_has_type(struct intel_crtc *crtc, enum
intel_output_type type)
* intel_pipe_has_type() but looking at encoder->new_crtc instead of
* encoder->crtc.
*/
-static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
+static bool intel_pipe_will_have_type(const struct intel_crtc_state
*crtc_state,
+ int type)
{
- struct drm_device *dev = crtc->base.dev;
+ struct drm_atomic_state *state = crtc_state->base.state;
+ struct drm_connector_state *connector_state;
struct intel_encoder *encoder;
+ int i;
+
+ for (i = 0; i < state->num_connector; i++) {
+ if (!state->connectors[i])
+ continue;
+
+ connector_state = state->connector_states[i];
+ if (connector_state->crtc != crtc_state->base.crtc)
+ continue;
- for_each_intel_encoder(dev, encoder)
- if (encoder->new_crtc == crtc && encoder->type == type)
+ encoder = to_intel_encoder(connector_state->best_encoder);
+ if (encoder->type == type)
return true;
+ }
return false;
}
-static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
- int refclk)
+static const intel_limit_t *
+intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
{
- struct drm_device *dev = crtc->base.dev;
+ struct drm_device *dev = crtc_state->base.crtc->dev;
const intel_limit_t *limit;
- if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
+ if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_is_dual_link_lvds(dev)) {
if (refclk == 10)
limit = &intel_limits_ironlake_dual_lvds_100m;
@@ -467,20 +479,21 @@ static const intel_limit_t *intel_ironlake_limit(struct
intel_crtc *crtc,
return limit;
}
-static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
+static const intel_limit_t *
+intel_g4x_limit(struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = crtc->base.dev;
+ struct drm_device *dev = crtc_state->base.crtc->dev;
const intel_limit_t *limit;
- if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
+ if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_is_dual_link_lvds(dev))
limit = &intel_limits_g4x_dual_channel_lvds;
else
limit = &intel_limits_g4x_single_channel_lvds;
- } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
- intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
+ } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
+ intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
limit = &intel_limits_g4x_hdmi;
- } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
+ } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
limit = &intel_limits_g4x_sdvo;
} else /* The option is for other outputs */
limit = &intel_limits_i9xx_sdvo;
@@ -488,17 +501,18 @@ static c
[Intel-gfx] [PATCH 14/23] drm/i915: Don't depend on encoder->new_crtc in intel_dp_compute_config()
Move towards atomic by using the legacy modeset's drm_atomic_state instead. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 5accf3f..a477e07 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1159,7 +1159,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); enum port port = dp_to_dig_port(intel_dp)->port; - struct intel_crtc *intel_crtc = encoder->new_crtc; + struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); struct intel_connector *intel_connector = intel_dp->attached_connector; int lane_count, clock; int min_lane_count = 1; -- 2.1.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 23/23] drm/i915: Remove usage of encoder->new_crtc from clock computations
Some of the crtc_compute_clock() still depended on encoder->new_crtc
since they didn't use intel_pipe_will_have_type() and used an open
coded version of that function instead. This patch replaces those with
the appropriate code that checks the atomic state intead.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/intel_display.c | 45 +---
1 file changed, 32 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f3652f9..8864484 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6617,11 +6617,18 @@ static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc,
bool is_lvds = false, is_dsi = false;
struct intel_encoder *encoder;
const intel_limit_t *limit;
+ struct drm_atomic_state *state = crtc_state->base.state;
+ struct drm_connector_state *connector_state;
+ int i;
- for_each_intel_encoder(dev, encoder) {
- if (encoder->new_crtc != crtc)
+ for (i = 0; i < state->num_connector; i++) {
+ connector_state = state->connector_states[i];
+ if (!state->connectors[i] ||
+ connector_state->crtc != &crtc->base)
continue;
+ encoder = to_intel_encoder(connector_state->best_encoder);
+
switch (encoder->type) {
case INTEL_OUTPUT_LVDS:
is_lvds = true;
@@ -7295,18 +7302,24 @@ void intel_init_pch_refclk(struct drm_device *dev)
lpt_init_pch_refclk(dev);
}
-static int ironlake_get_refclk(struct drm_crtc *crtc)
+static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = crtc->dev;
+ struct drm_device *dev = crtc_state->base.crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_atomic_state *state = crtc_state->base.state;
+ struct drm_connector_state *connector_state;
struct intel_encoder *encoder;
- int num_connectors = 0;
+ int num_connectors = 0, i;
bool is_lvds = false;
- for_each_intel_encoder(dev, encoder) {
- if (encoder->new_crtc != to_intel_crtc(crtc))
+ for (i = 0; i < state->num_connector; i++) {
+ connector_state = state->connector_states[i];
+ if (!state->connectors[i] ||
+ connector_state->crtc != crtc_state->base.crtc)
continue;
+ encoder = to_intel_encoder(connector_state->best_encoder);
+
switch (encoder->type) {
case INTEL_OUTPUT_LVDS:
is_lvds = true;
@@ -7499,7 +7512,7 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
- refclk = ironlake_get_refclk(crtc);
+ refclk = ironlake_get_refclk(crtc_state);
/*
* Returns a set of divisors for the desired target clock with the given
@@ -7554,16 +7567,22 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc,
struct drm_crtc *crtc = &intel_crtc->base;
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_encoder *intel_encoder;
+ struct drm_atomic_state *state = crtc_state->base.state;
+ struct drm_connector_state *connector_state;
+ struct intel_encoder *encoder;
uint32_t dpll;
- int factor, num_connectors = 0;
+ int factor, num_connectors = 0, i;
bool is_lvds = false, is_sdvo = false;
- for_each_intel_encoder(dev, intel_encoder) {
- if (intel_encoder->new_crtc != to_intel_crtc(crtc))
+ for (i = 0; i < state->num_connector; i++) {
+ connector_state = state->connector_states[i];
+ if (!state->connectors[i] ||
+ connector_state->crtc != crtc_state->base.crtc)
continue;
- switch (intel_encoder->type) {
+ encoder = to_intel_encoder(connector_state->best_encoder);
+
+ switch (encoder->type) {
case INTEL_OUTPUT_LVDS:
is_lvds = true;
break;
--
2.1.0
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Re: [Intel-gfx] i915 driver doesn't find all Modelines that nouveau driver finds
On Tue, Mar 03, 2015 at 08:16:56AM -0500, Brian J. Murrell wrote: > On Tue, 2015-03-03 at 15:03 +0200, Ville Syrjälä wrote: > > > > Oh that's an a CRT monitor you have there. Been a while since I've > > come across one of those :) > > Heh. Yeah. I have been in the market to replace it but no good enough > deals yet. :-) > > > 65Hz on a CRT sounds like a good way to > > get a headache to me. > > Worse than the 60Hz that I am stuck with right now though? On paper > +5Hz should be slightly better but maybe there is something particular > about 65Hz that makes it worse than 60Hz? I suppose any increase is good. But personally I just couldn't stand anything below 75Hz when I was still using a CRT. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] eDP display control registers in Linux kernel
On Sat, 28 Feb 2015, Michael Leuchtenburg wrote: > No changes, even while the brightness is in the process of changing. Is it > possible there's some other bit used on this hardware? The Broadwell chips > are pretty new. I haven't had a chance to look for specs yet. The DPCD info is specific to your panel, not the platform. BR, Jani. -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] acpi/video: Propagate the error code for acpi_video_register
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5867 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -4 278/278 274/278 ILK 308/308 308/308 SNB -1 284/284 283/284 IVB 380/380 380/380 BYT 294/294 294/294 HSW 387/387 387/387 BDW -1 316/316 315/316 -Detailed- Platform Testdrm-intel-nightly Series Applied *PNV igt_gem_userptr_blits_minor-normal-sync PASS(2) DMESG_WARN(1)PASS(1) *PNV igt_gem_userptr_blits_minor-unsync-interruptible PASS(4) DMESG_WARN(2) PNV igt_gen3_render_linear_blits FAIL(3)PASS(6) FAIL(2) PNV igt_gen3_render_mixed_blits FAIL(2)PASS(9) FAIL(2) *SNB igt_gem_flink_bad-open PASS(4) DMESG_WARN(1)PASS(1) *BDW igt_gem_gtt_hog PASS(12) DMESG_WARN(1)PASS(1) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] i915 when using vaapi, screen only refreshes on mouse movement
On Tue, Mar 03, 2015 at 08:23:04AM -0500, Brian J. Murrell wrote: > On Mon, 2015-03-02 at 14:27 +, Chris Wilson wrote: > > > > Mixing ZaphodHeads and DRI, > > Oh wait! You said "mixing" not "missing". But yeah, I'm an old-timer > trying to maintain his 20+ year old preference for truly separate > screens -- like from way back when even Xinerama didn't even exist. :-) > > > you probably want to grab -intel-2.99.917 or > > linux-4.0. > > Is that really an either/or? If I were to just update > xorg-x11-drv-intel-2.99.916-3.20141117.fc21.x86_64 to 2.99.917 would > that solve the problem or do I also need the 4.0 kernel? It's an OR. The bug I am thinking about has a w/a in the ddx and a real fix in the kernel. Either one should do, and I think will resolve your issue. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 00/12] PPGTT with 48b addressing
On Fri, Feb 20, 2015 at 05:45:54PM +, Michel Thierry wrote: > These patches rely on "PPGTT dynamic page allocations", currently under > review, > to provide GEN8 dynamic page table support with 64b addresses. As the review > progresses, these patches may be combined. > > In order expand the GPU address space, a 4th level translation is added, the > Page Map Level 4 (PML4). This PML4 has 256 PML4 Entries (PML4E), PML4[0-255], > each pointing to a PDP. > > For now, this feature will only be available in BDW, in LRC submission mode > (execlists) and when i915.enable_ppgtt=3 is set. > Also note that this expanded address space is only available for full PPGTT, > aliasing PPGTT remains 32b. FWIW, I don't think it sounds like a good idea to enable 48bits address spaces without having implemented Wa32bitGeneralStateOffset and Wa32bitInstructionBaseOffset. -- Damien ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 02/13] lib: Extract igt_buf_write_to_png() from gem_render_copy
From: Damien Lespiau
Now that the Android build has cairo, we can put cairo-dependant code
back into lib/
v2: Document image format. (Daniel Vetter)
Signed-off-by: Damien Lespiau
---
lib/intel_batchbuffer.c | 26 ++
lib/intel_batchbuffer.h | 2 ++
tests/gem_render_copy.c | 24 +++-
3 files changed, 31 insertions(+), 21 deletions(-)
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index c70f6d8..d3efc1e 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -31,6 +31,8 @@
#include
#include
+#include
+
#include "drm.h"
#include "drmtest.h"
#include "intel_batchbuffer.h"
@@ -458,6 +460,30 @@ unsigned igt_buf_height(struct igt_buf *buf)
}
/**
+ * igt_buf_write_to_png:
+ * @buf: an i-g-t buffer object
+ *
+ * Writes the content of @buf as a PNG file.
+ * Buffer is interpreted as in RGBX format.
+ */
+void igt_buf_write_to_png(struct igt_buf *buf, const char *filename)
+{
+ cairo_surface_t *surface;
+ cairo_status_t ret;
+
+ drm_intel_bo_map(buf->bo, 0);
+ surface = cairo_image_surface_create_for_data(buf->bo->virtual,
+ CAIRO_FORMAT_RGB24,
+ igt_buf_width(buf),
+ igt_buf_height(buf),
+ buf->stride);
+ ret = cairo_surface_write_to_png(surface, filename);
+ igt_assert(ret == CAIRO_STATUS_SUCCESS);
+ cairo_surface_destroy(surface);
+ drm_intel_bo_unmap(buf->bo);
+}
+
+/**
* igt_get_render_copyfunc:
* @devid: pci device id
*
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 12f7be1..e2afc3b 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -210,6 +210,8 @@ struct igt_buf {
unsigned igt_buf_width(struct igt_buf *buf);
unsigned igt_buf_height(struct igt_buf *buf);
+void igt_buf_write_to_png(struct igt_buf *buf, const char *filename);
+
/**
* igt_render_copyfunc_t:
* @batch: batchbuffer object
diff --git a/tests/gem_render_copy.c b/tests/gem_render_copy.c
index df1ac88..76f8c63 100644
--- a/tests/gem_render_copy.c
+++ b/tests/gem_render_copy.c
@@ -31,7 +31,6 @@
#include
#include
-#include
#include
#include
#include
@@ -71,23 +70,6 @@ typedef struct {
static int opt_dump_png = false;
static int check_all_pixels = false;
-static void scratch_buf_write_to_png(struct igt_buf *buf, const char *filename)
-{
- cairo_surface_t *surface;
- cairo_status_t ret;
-
- drm_intel_bo_map(buf->bo, 0);
- surface = cairo_image_surface_create_for_data(buf->bo->virtual,
- CAIRO_FORMAT_RGB24,
- igt_buf_width(buf),
- igt_buf_height(buf),
- buf->stride);
- ret = cairo_surface_write_to_png(surface, filename);
- igt_assert(ret == CAIRO_STATUS_SUCCESS);
- cairo_surface_destroy(surface);
- drm_intel_bo_unmap(buf->bo);
-}
-
static void scratch_buf_init(data_t *data, struct igt_buf *buf,
int width, int height, int stride, uint32_t color)
{
@@ -165,8 +147,8 @@ int main(int argc, char **argv)
scratch_buf_check(&data, &dst, WIDTH / 2, HEIGHT / 2, DST_COLOR);
if (opt_dump_png) {
- scratch_buf_write_to_png(&src, "source.png");
- scratch_buf_write_to_png(&dst, "destination.png");
+ igt_buf_write_to_png(&src, "source.png");
+ igt_buf_write_to_png(&dst, "destination.png");
}
if (opt_dump_aub) {
@@ -188,7 +170,7 @@ int main(int argc, char **argv)
&dst, WIDTH / 2, HEIGHT / 2);
if (opt_dump_png)
- scratch_buf_write_to_png(&dst, "result.png");
+ igt_buf_write_to_png(&dst, "result.png");
if (opt_dump_aub) {
drm_intel_gem_bo_aub_dump_bmp(dst.bo,
--
2.3.0
___
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[Intel-gfx] [PATCH i-g-t v3 00/13] Testing the Y tiled display
From: Tvrtko Ursulin Starting with Skylake the display engine can scan out Y tiled objects. (Both legacy Y tiled, and the new Yf format.) This series takes the original work by Damien Lespiau and converts it to use the new frame buffer modifiers instead of object set/get tiling. Some patches needed to be dropped, some added and some refactored. v2: Refactored for fb modifier changes. v3: * Addressing review comments. * Added Y(f) tiling sub tests to kms_flip_tiling. Damien Lespiau (7): lib: Extract igt_buf_write_to_png() from gem_render_copy lib/skl: Add gen9 specific igt_blitter_fast_copy() lib: Don't give a struct igt_buf * to fast_copy_pitch() lib: Split two helpers to build fast copy's dword0 and dword1 lib: Provide a raw version of the gen9 fast copy blits lib: Allow the creation of Ys/Yf tiled FBs testdisplay/skl: Add command line options for Yb/Yf tiled fbs Tvrtko Ursulin (6): tests/kms_addfb: Add support for fb modifiers tests/kms_addfb: Y tiled testcases tiling: Convert framebuffer helpers to use fb modifiers lib: Add support for new extension to the ADDFB2 ioctl. lib/igt_fb: Use new ADDFB2 extension for new tiling modes tests/kms_flip_tiling: Exercise Y tiling modes on Gen9+ lib/igt_fb.c| 163 + lib/igt_fb.h| 10 +- lib/igt_kms.h | 1 + lib/intel_batchbuffer.c | 282 lib/intel_batchbuffer.h | 37 ++ lib/intel_reg.h | 18 +++ lib/ioctl_wrappers.c| 49 lib/ioctl_wrappers.h| 41 +++ tests/gem_render_copy.c | 24 +--- tests/kms_3d.c | 2 +- tests/kms_addfb.c | 145 ++- tests/kms_cursor_crc.c | 8 +- tests/kms_fbc_crc.c | 4 +- tests/kms_fence_pin_leak.c | 4 +- tests/kms_flip.c| 8 +- tests/kms_flip_event_leak.c | 4 +- tests/kms_flip_tiling.c | 33 +- tests/kms_mmio_vs_cs_flip.c | 12 +- tests/kms_pipe_crc_basic.c | 2 +- tests/kms_plane.c | 8 +- tests/kms_psr_sink_crc.c| 8 +- tests/kms_pwrite_crc.c | 4 +- tests/kms_render.c | 8 +- tests/kms_rotation_crc.c| 4 +- tests/kms_setmode.c | 2 +- tests/kms_sink_crc_basic.c | 6 +- tests/kms_universal_plane.c | 18 +-- tests/pm_lpsp.c | 2 +- tests/pm_rpm.c | 26 ++-- tests/testdisplay.c | 20 +++- 30 files changed, 831 insertions(+), 122 deletions(-) -- 2.3.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 01/13] tests/kms_addfb: Add support for fb modifiers
From: Tvrtko Ursulin
Just a few basic tests to make sure fb modifiers can be used and
behave sanely when mixed with the old set_tiling API.
v2:
* Review feedback from Daniel Vetter:
1. Move cap detection into the subtest so skipping works.
2. Added some gtkdoc comments.
3. Two more test cases.
4. Removed unused parts for now.
v3:
* Removed two tests which do not make sense any more after the
fb modifier rewrite.
v4:
* Moved gtkdoc comments into .c file.
* Moved all initialization into fixtures.
* Rebased for fb modifier changes.
v5:
* Added bad modifier subtest.
Signed-off-by: Tvrtko Ursulin
---
lib/ioctl_wrappers.c | 23
lib/ioctl_wrappers.h | 30 +
tests/kms_addfb.c| 75
3 files changed, 128 insertions(+)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 66c90de..5cbb873 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -1142,3 +1142,26 @@ off_t prime_get_size(int dma_buf_fd)
return ret;
}
+
+/**
+ * igt_require_fb_modifiers:
+ * @fd: Open DRM file descriptor.
+ *
+ * Requires presence of DRM_CAP_ADDFB2_MODIFIERS.
+ */
+void igt_require_fb_modifiers(int fd)
+{
+ static bool has_modifiers, cap_modifiers_tested;
+
+ if (!cap_modifiers_tested) {
+ uint64_t cap_modifiers;
+ int ret;
+
+ ret = drmGetCap(fd, LOCAL_DRM_CAP_ADDFB2_MODIFIERS,
&cap_modifiers);
+ igt_assert(ret == 0 || errno == EINVAL);
+ has_modifiers = ret == 0 && cap_modifiers == 1;
+ cap_modifiers_tested = true;
+ }
+
+ igt_require(has_modifiers);
+}
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index 7c0c87e..3c85e8b 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -135,4 +135,34 @@ int prime_handle_to_fd(int fd, uint32_t handle);
uint32_t prime_fd_to_handle(int fd, int dma_buf_fd);
off_t prime_get_size(int dma_buf_fd);
+/* addfb2 fb modifiers */
+struct local_drm_mode_fb_cmd2 {
+ uint32_t fb_id;
+ uint32_t width, height;
+ uint32_t pixel_format;
+ uint32_t flags;
+ uint32_t handles[4];
+ uint32_t pitches[4];
+ uint32_t offsets[4];
+ uint64_t modifier[4];
+};
+
+#define LOCAL_DRM_MODE_FB_MODIFIERS(1<<1)
+
+#define LOCAL_DRM_FORMAT_MOD_VENDOR_INTEL 0x01
+
+#define local_fourcc_mod_code(vendor, val) \
+ uint64_t)LOCAL_DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | \
+ (val & 0x00ffL))
+
+#define LOCAL_DRM_FORMAT_MOD_NONE (0)
+#define LOCAL_I915_FORMAT_MOD_X_TILED local_fourcc_mod_code(INTEL, 1)
+
+#define LOCAL_DRM_IOCTL_MODE_ADDFB2DRM_IOWR(0xB8, \
+struct local_drm_mode_fb_cmd2)
+
+#define LOCAL_DRM_CAP_ADDFB2_MODIFIERS 0x10
+
+void igt_require_fb_modifiers(int fd);
+
#endif /* IOCTL_WRAPPERS_H */
diff --git a/tests/kms_addfb.c b/tests/kms_addfb.c
index 756589e..58a23ea 100644
--- a/tests/kms_addfb.c
+++ b/tests/kms_addfb.c
@@ -213,6 +213,79 @@ static void size_tests(int fd)
}
}
+static void addfb25_tests(int fd)
+{
+ struct local_drm_mode_fb_cmd2 f = {};
+
+ igt_fixture {
+ gem_bo = gem_create(fd, 1024*1024*4);
+ igt_assert(gem_bo);
+
+ memset(&f, 0, sizeof(f));
+
+ f.width = 1024;
+ f.height = 1024;
+ f.pixel_format = DRM_FORMAT_XRGB;
+ f.pitches[0] = 1024*4;
+ f.modifier[0] = LOCAL_DRM_FORMAT_MOD_NONE;
+
+ f.handles[0] = gem_bo;
+ }
+
+ igt_subtest("addfb25-modifier-no-flag") {
+ igt_require_fb_modifiers(fd);
+
+ f.modifier[0] = LOCAL_I915_FORMAT_MOD_X_TILED;
+ igt_assert(drmIoctl(fd, LOCAL_DRM_IOCTL_MODE_ADDFB2, &f) < 0 &&
errno == EINVAL);
+ }
+
+ igt_fixture {
+ f.flags = LOCAL_DRM_MODE_FB_MODIFIERS;
+ }
+
+ igt_subtest("addfb25-bad-modifier") {
+ igt_require_fb_modifiers(fd);
+
+ f.modifier[0] = ~0;
+ igt_assert(drmIoctl(fd, LOCAL_DRM_IOCTL_MODE_ADDFB2, &f) < 0 &&
errno == EINVAL);
+ }
+
+ igt_fixture {
+ gem_set_tiling(fd, gem_bo, I915_TILING_X, 1024*4);
+ }
+
+ igt_subtest("addfb25-X-tiled-mismatch") {
+ igt_require_fb_modifiers(fd);
+
+ f.modifier[0] = LOCAL_DRM_FORMAT_MOD_NONE;
+ igt_assert(drmIoctl(fd, LOCAL_DRM_IOCTL_MODE_ADDFB2, &f) < 0 &&
errno == EINVAL);
+ }
+
+ igt_subtest("addfb25-X-tiled") {
+ igt_require_fb_modifiers(fd);
+
+ f.modifier[0] = LOCAL_I915_FORMAT_MOD_X_TILED;
+ igt_assert(drmIoctl(fd, LOCAL_DRM_IOCTL_MODE_ADDFB2, &f) == 0);
+ igt_assert(drmIoctl(fd, DRM_IOCTL_MODE_RMFB, &f.fb_id) == 0);
+ f.fb_
[Intel-gfx] [PATCH i-g-t 10/13] lib/igt_fb: Use new ADDFB2 extension for new tiling modes
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
---
lib/igt_fb.c | 36 +++-
1 file changed, 23 insertions(+), 13 deletions(-)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 853b2f9..c54907e 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -404,16 +404,10 @@ igt_create_fb_with_bo_size(int fd, int width, int height,
uint32_t format, uint64_t tiling,
struct igt_fb *fb, unsigned bo_size)
{
- uint32_t handles[4];
- uint32_t pitches[4];
- uint32_t offsets[4];
uint32_t fb_id;
int bpp;
memset(fb, 0, sizeof(*fb));
- memset(handles, 0, sizeof(handles));
- memset(pitches, 0, sizeof(pitches));
- memset(offsets, 0, sizeof(offsets));
bpp = igt_drm_format_to_bpp(format);
@@ -422,14 +416,30 @@ igt_create_fb_with_bo_size(int fd, int width, int height,
do_or_die(create_bo_for_fb(fd, width, height, bpp, tiling, bo_size,
&fb->gem_handle, &fb->size, &fb->stride));
- handles[0] = fb->gem_handle;
- pitches[0] = fb->stride;
-
igt_debug("%s(handle=%d, pitch=%d)\n",
- __func__, handles[0], pitches[0]);
- do_or_die(drmModeAddFB2(fd, width, height, format,
- handles, pitches, offsets,
- &fb_id, 0));
+ __func__, fb->gem_handle, fb->stride);
+
+ if (tiling != LOCAL_DRM_FORMAT_MOD_NONE &&
+ tiling != LOCAL_I915_FORMAT_MOD_X_TILED) {
+ do_or_die(__kms_addfb(fd, fb->gem_handle, width, height,
+ fb->stride, format, tiling,
+ LOCAL_DRM_MODE_FB_MODIFIERS, &fb_id));
+ } else {
+ uint32_t handles[4];
+ uint32_t pitches[4];
+ uint32_t offsets[4];
+
+ memset(handles, 0, sizeof(handles));
+ memset(pitches, 0, sizeof(pitches));
+ memset(offsets, 0, sizeof(offsets));
+
+ handles[0] = fb->gem_handle;
+ pitches[0] = fb->stride;
+
+ do_or_die(drmModeAddFB2(fd, width, height, format,
+ handles, pitches, offsets,
+ &fb_id, 0));
+ }
fb->width = width;
fb->height = height;
--
2.3.0
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[Intel-gfx] [PATCH i-g-t 06/13] lib: Split two helpers to build fast copy's dword0 and dword1
From: Damien Lespiau
Again, these helpers will be useful for a raw version of the gen9 fast
copy.
Signed-off-by: Damien Lespiau
---
lib/intel_batchbuffer.c | 96 +
1 file changed, 57 insertions(+), 39 deletions(-)
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index f964d12..1eeabe4 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -495,46 +495,14 @@ static uint32_t fast_copy_pitch(unsigned int stride, enum
i915_tiling tiling)
return stride;
}
-/**
- * igt_blitter_fast_copy:
- * @batch: batchbuffer object
- * @context: libdrm hardware context to use
- * @src: source i-g-t buffer object
- * @src_x: source pixel x-coordination
- * @src_y: source pixel y-coordination
- * @width: width of the copied rectangle
- * @height: height of the copied rectangle
- * @dst: destination i-g-t buffer object
- * @dst_x: destination pixel x-coordination
- * @dst_y: destination pixel y-coordination
- *
- * Copy @src into @dst using the gen9 fast copy blitter comamnd.
- *
- * The source and destination surfaces cannot overlap.
- */
-void igt_blitter_fast_copy(struct intel_batchbuffer *batch,
- struct igt_buf *src, unsigned src_x, unsigned src_y,
- unsigned width, unsigned height,
- struct igt_buf *dst, unsigned dst_x, unsigned dst_y)
+static uint32_t fast_copy_dword0(unsigned int src_tiling,
+unsigned int dst_tiling)
{
- uint32_t src_pitch, dst_pitch;
- uint32_t dword0 = 0, dword1 = 0;
-
- src_pitch = fast_copy_pitch(src->stride, src->tiling);
- dst_pitch = fast_copy_pitch(dst->stride, src->tiling);
-
-#define CHECK_RANGE(x) ((x) >= 0 && (x) < (1 << 15))
- assert(CHECK_RANGE(src_x) && CHECK_RANGE(src_y) &&
- CHECK_RANGE(dst_x) && CHECK_RANGE(dst_y) &&
- CHECK_RANGE(width) && CHECK_RANGE(height) &&
- CHECK_RANGE(src_x + width) && CHECK_RANGE(src_y + height) &&
- CHECK_RANGE(dst_x + width) && CHECK_RANGE(dst_y + height) &&
- CHECK_RANGE(src_pitch) && CHECK_RANGE(dst_pitch));
-#undef CHECK_RANGE
+ uint32_t dword0 = 0;
dword0 |= XY_FAST_COPY_BLT;
- switch (src->tiling) {
+ switch (src_tiling) {
case I915_TILING_X:
dword0 |= XY_FAST_COPY_SRC_TILING_X;
break;
@@ -550,7 +518,7 @@ void igt_blitter_fast_copy(struct intel_batchbuffer *batch,
break;
}
- switch (dst->tiling) {
+ switch (dst_tiling) {
case I915_TILING_X:
dword0 |= XY_FAST_COPY_DST_TILING_X;
break;
@@ -566,13 +534,63 @@ void igt_blitter_fast_copy(struct intel_batchbuffer
*batch,
break;
}
- if (src->tiling == I915_TILING_Yf)
+ return dword0;
+}
+
+static uint32_t fast_copy_dword1(unsigned int src_tiling,
+unsigned int dst_tiling)
+{
+ uint32_t dword1 = 0;
+
+ if (src_tiling == I915_TILING_Yf)
dword1 |= XY_FAST_COPY_SRC_TILING_Yf;
- if (dst->tiling == I915_TILING_Yf)
+ if (dst_tiling == I915_TILING_Yf)
dword1 |= XY_FAST_COPY_DST_TILING_Yf;
dword1 |= XY_FAST_COPY_COLOR_DEPTH_32;
+ return dword1;
+}
+
+/**
+ * igt_blitter_fast_copy:
+ * @batch: batchbuffer object
+ * @context: libdrm hardware context to use
+ * @src: source i-g-t buffer object
+ * @src_x: source pixel x-coordination
+ * @src_y: source pixel y-coordination
+ * @width: width of the copied rectangle
+ * @height: height of the copied rectangle
+ * @dst: destination i-g-t buffer object
+ * @dst_x: destination pixel x-coordination
+ * @dst_y: destination pixel y-coordination
+ *
+ * Copy @src into @dst using the gen9 fast copy blitter comamnd.
+ *
+ * The source and destination surfaces cannot overlap.
+ */
+void igt_blitter_fast_copy(struct intel_batchbuffer *batch,
+ struct igt_buf *src, unsigned src_x, unsigned src_y,
+ unsigned width, unsigned height,
+ struct igt_buf *dst, unsigned dst_x, unsigned dst_y)
+{
+ uint32_t src_pitch, dst_pitch;
+ uint32_t dword0, dword1;
+
+ src_pitch = fast_copy_pitch(src->stride, src->tiling);
+ dst_pitch = fast_copy_pitch(dst->stride, src->tiling);
+ dword0 = fast_copy_dword0(src->tiling, dst->tiling);
+ dword1 = fast_copy_dword1(src->tiling, dst->tiling);
+
+#define CHECK_RANGE(x) ((x) >= 0 && (x) < (1 << 15))
+ assert(CHECK_RANGE(src_x) && CHECK_RANGE(src_y) &&
+ CHECK_RANGE(dst_x) && CHECK_RANGE(dst_y) &&
+ CHECK_RANGE(width) && CHECK_RANGE(height) &&
+ CHECK_RANGE(src_x + width) && CHECK_RANGE(src_y + height) &&
+ CHECK_RANGE(dst_x + width) && CHECK_RANGE(dst_y + height) &&
+ CHECK_RANGE(src_pitch) && CHE
[Intel-gfx] [PATCH i-g-t 12/13] testdisplay/skl: Add command line options for Yb/Yf tiled fbs
From: Damien Lespiau
Signed-off-by: Damien Lespiau
---
tests/testdisplay.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/tests/testdisplay.c b/tests/testdisplay.c
index 64ce4d7..dab9e12 100644
--- a/tests/testdisplay.c
+++ b/tests/testdisplay.c
@@ -51,6 +51,7 @@
#include
#include
+#include
#include
#include
#include
@@ -71,8 +72,10 @@
#include
#include
-#define SUBTEST_OPTS 1
+#define SUBTEST_OPTS1
#define HELP_DESCRIPTION 2
+#define Yb_OPT 3
+#define Yf_OPT 4
static int tio_fd;
struct termios saved_tio;
@@ -544,7 +547,7 @@ int update_display(void)
return 1;
}
-static char optstr[] = "3hiaf:s:d:p:mrto:j:";
+static char optstr[] = "3hiaf:s:d:p:mrto:j:y";
static void __attribute__((noreturn)) usage(char *name, char opt)
{
@@ -645,6 +648,8 @@ int main(int argc, char **argv)
{"run-subtest", 1, 0, SUBTEST_OPTS},
{"help-description", 0, 0, HELP_DESCRIPTION},
{"help", 0, 0, 'h'},
+ {"yb", 0, 0, Yb_OPT},
+ {"yf", 0, 0, Yf_OPT},
{ 0, 0, 0, 0 }
};
@@ -697,6 +702,13 @@ int main(int argc, char **argv)
case 't':
tiling = LOCAL_I915_FORMAT_MOD_X_TILED;
break;
+ case 'y':
+ case Yb_OPT:
+ tiling = LOCAL_I915_FORMAT_MOD_Y_TILED;
+ break;
+ case Yf_OPT:
+ tiling = LOCAL_I915_FORMAT_MOD_Yf_TILED;
+ break;
case 'r':
qr_code = 1;
break;
--
2.3.0
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[Intel-gfx] [PATCH i-g-t 05/13] lib: Don't give a struct igt_buf * to fast_copy_pitch()
From: Damien Lespiau
So we can use this function in a "raw" (ie without igt_buf) version.
Signed-off-by: Damien Lespiau
---
lib/intel_batchbuffer.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 9b8ae0d..f964d12 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -487,12 +487,12 @@ void igt_buf_write_to_png(struct igt_buf *buf, const char
*filename)
* pitches are in bytes if the surfaces are linear, number of dwords
* otherwise
*/
-static uint32_t fast_copy_pitch(struct igt_buf *buf)
+static uint32_t fast_copy_pitch(unsigned int stride, enum i915_tiling tiling)
{
- if (buf->tiling != I915_TILING_NONE)
- return buf->stride / 4;
+ if (tiling != I915_TILING_NONE)
+ return stride / 4;
else
- return buf->stride;
+ return stride;
}
/**
@@ -520,8 +520,8 @@ void igt_blitter_fast_copy(struct intel_batchbuffer *batch,
uint32_t src_pitch, dst_pitch;
uint32_t dword0 = 0, dword1 = 0;
- src_pitch = fast_copy_pitch(src);
- dst_pitch = fast_copy_pitch(dst);
+ src_pitch = fast_copy_pitch(src->stride, src->tiling);
+ dst_pitch = fast_copy_pitch(dst->stride, src->tiling);
#define CHECK_RANGE(x) ((x) >= 0 && (x) < (1 << 15))
assert(CHECK_RANGE(src_x) && CHECK_RANGE(src_y) &&
--
2.3.0
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[Intel-gfx] [PATCH i-g-t 13/13] tests/kms_flip_tiling: Exercise Y tiling modes on Gen9+
From: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
---
tests/kms_flip_tiling.c | 28 +---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/tests/kms_flip_tiling.c b/tests/kms_flip_tiling.c
index 9adf143..9ca12f7 100644
--- a/tests/kms_flip_tiling.c
+++ b/tests/kms_flip_tiling.c
@@ -33,6 +33,7 @@
#include "igt_debugfs.h"
#include "igt_kms.h"
#include "ioctl_wrappers.h"
+#include "intel_chipset.h"
IGT_TEST_DESCRIPTION("Test that a page flip from a tiled buffer to a linear"
" one works correctly.");
@@ -40,6 +41,7 @@ IGT_TEST_DESCRIPTION("Test that a page flip from a tiled
buffer to a linear"
typedef struct {
int drm_fd;
igt_display_t display;
+ int gen;
} data_t;
/*
@@ -61,7 +63,7 @@ fill_linear_fb(struct igt_fb *fb, data_t *data,
drmModeModeInfo *mode)
}
static void
-test_flip_changes_tiling(data_t *data, igt_output_t *output)
+test_flip_changes_tiling(data_t *data, igt_output_t *output, uint64_t tiling)
{
struct igt_fb linear, tiled;
drmModeModeInfo *mode;
@@ -97,7 +99,7 @@ test_flip_changes_tiling(data_t *data, igt_output_t *output)
/* allocate a tiled buffer and set the crtc with it */
igt_create_color_fb(data->drm_fd, width, mode->vdisplay,
- DRM_FORMAT_XRGB, LOCAL_I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_XRGB, tiling,
0.0, 0.0, 0.0, &tiled);
igt_plane_set_fb(primary, &tiled);
igt_display_commit(&data->display);
@@ -132,6 +134,7 @@ igt_main
igt_fixture {
data.drm_fd = drm_open_any_master();
+ data.gen = intel_gen(intel_get_drm_devid(data.drm_fd));
kmstest_set_vt_graphics_mode();
@@ -141,7 +144,26 @@ igt_main
igt_subtest_f("flip-changes-tiling") {
for_each_connected_output(&data.display, output)
- test_flip_changes_tiling(&data, output);
+ test_flip_changes_tiling(&data, output,
+ LOCAL_I915_FORMAT_MOD_X_TILED);
+ }
+
+ igt_subtest_f("flip-changes-tiling-Y") {
+ igt_require_fb_modifiers(data.drm_fd);
+ igt_require(data.gen >= 9);
+
+ for_each_connected_output(&data.display, output)
+ test_flip_changes_tiling(&data, output,
+ LOCAL_I915_FORMAT_MOD_Y_TILED);
+ }
+
+ igt_subtest_f("flip-changes-tiling-Yf") {
+ igt_require_fb_modifiers(data.drm_fd);
+ igt_require(data.gen >= 9);
+
+ for_each_connected_output(&data.display, output)
+ test_flip_changes_tiling(&data, output,
+ LOCAL_I915_FORMAT_MOD_Yf_TILED);
}
igt_fixture {
--
2.3.0
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[Intel-gfx] [PATCH i-g-t 09/13] lib: Add support for new extension to the ADDFB2 ioctl.
From: Tvrtko Ursulin
New functionality accessesed via the __kms_addfb wrapper.
Signed-off-by: Tvrtko Ursulin
---
lib/ioctl_wrappers.c | 26 ++
lib/ioctl_wrappers.h | 9 +
2 files changed, 35 insertions(+)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 5cbb873..baebf5c 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -1165,3 +1165,29 @@ void igt_require_fb_modifiers(int fd)
igt_require(has_modifiers);
}
+
+int __kms_addfb(int fd, uint32_t handle, uint32_t width, uint32_t height,
+ uint32_t stride, uint32_t pixel_format, uint64_t modifier,
+ uint32_t flags, uint32_t *buf_id)
+{
+ struct local_drm_mode_fb_cmd2 f;
+ int ret;
+
+ igt_require_fb_modifiers(fd);
+
+ memset(&f, 0, sizeof(f));
+
+ f.width = width;
+ f.height = height;
+ f.pixel_format = pixel_format;
+ f.flags = flags;
+ f.handles[0] = handle;
+ f.pitches[0] = stride;
+ f.modifier[0] = modifier;
+
+ ret = drmIoctl(fd, LOCAL_DRM_IOCTL_MODE_ADDFB2, &f);
+
+ *buf_id = f.fb_id;
+
+ return ret < 0 ? -errno : ret;
+}
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index 99fc7fd..ced7ef3 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -167,4 +167,13 @@ struct local_drm_mode_fb_cmd2 {
void igt_require_fb_modifiers(int fd);
+/**
+ * __kms_addfb:
+ *
+ * Creates a framebuffer object.
+ */
+int __kms_addfb(int fd, uint32_t handle, uint32_t width, uint32_t height,
+ uint32_t stride, uint32_t pixel_format, uint64_t modifier,
+ uint32_t flags, uint32_t *buf_id);
+
#endif /* IOCTL_WRAPPERS_H */
--
2.3.0
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[Intel-gfx] [PATCH i-g-t 11/13] lib: Allow the creation of Ys/Yf tiled FBs
From: Damien Lespiau
There's no fencing for those tiling layouts, so we create a linear bo
for cairo to play with, and when cairo is finished with it, we do a fast
copy blit to the fb BO with its final tiling.
v2: Move to correct domain after CPU is done with the object (-EINVAL). (Tvrtko
Ursulin)
Correct arguments passed in to framebuffer creation (segfault). (Tvrtko
Ursulin)
Pass zero stride to kernel as it expects for Yf&Ys. (Tvrtko Ursulin)
v3: Rebase for gem_mmap__cpu changes. (Tvrtko Ursulin)
v4: Rebase for addfb2.5. (Tvrtko Ursulin)
Signed-off-by: Damien Lespiau
Signed-off-by: Tvrtko Ursulin
---
lib/igt_fb.c | 109 +--
1 file changed, 106 insertions(+), 3 deletions(-)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index c54907e..5c92fac 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -112,7 +112,7 @@ static int create_bo_for_fb(int fd, int width, int height,
int bpp,
bo_size = size;
gem_handle = gem_create(fd, bo_size);
- if (tiling != LOCAL_DRM_FORMAT_MOD_NONE)
+ if (tiling == LOCAL_I915_FORMAT_MOD_X_TILED)
ret = __gem_set_tiling(fd, gem_handle, I915_TILING_X, stride);
*stride_ret = stride;
@@ -629,6 +629,104 @@ static cairo_format_t drm_format_to_cairo(uint32_t
drm_format)
drm_format, igt_format_str(drm_format));
}
+struct fb_blit_upload {
+ int fd;
+ struct igt_fb *fb;
+ struct {
+ uint32_t handle;
+ unsigned size, stride;
+ uint8_t *map;
+ } linear;
+};
+
+static void destroy_cairo_surface__blit(void *arg)
+{
+ struct fb_blit_upload *blit = arg;
+ struct igt_fb *fb = blit->fb;
+ unsigned int obj_tiling = I915_TILING_NONE;
+
+ munmap(blit->linear.map, blit->linear.size);
+ fb->cairo_surface = NULL;
+
+ gem_set_domain(blit->fd, blit->linear.handle,
+ I915_GEM_DOMAIN_GTT, 0);
+
+ switch (fb->tiling) {
+ case LOCAL_I915_FORMAT_MOD_X_TILED:
+ obj_tiling = I915_TILING_X;
+ break;
+ case LOCAL_I915_FORMAT_MOD_Y_TILED:
+ obj_tiling = I915_TILING_Y;
+ break;
+ case LOCAL_I915_FORMAT_MOD_Yf_TILED:
+ obj_tiling = I915_TILING_Yf;
+ break;
+ }
+
+ igt_blitter_fast_copy__raw(blit->fd,
+ blit->linear.handle,
+ blit->linear.stride,
+ I915_TILING_NONE,
+ 0, 0, /* src_x, src_y */
+ fb->width, fb->height,
+ fb->gem_handle,
+ fb->stride,
+ obj_tiling,
+ 0, 0 /* dst_x, dst_y */);
+
+ gem_sync(blit->fd, blit->linear.handle);
+ gem_close(blit->fd, blit->linear.handle);
+
+ free(blit);
+}
+
+static void create_cairo_surface__blit(int fd, struct igt_fb *fb)
+{
+ struct fb_blit_upload *blit;
+ cairo_format_t cairo_format;
+ int bpp, ret;
+
+ blit = malloc(sizeof(*blit));
+ igt_assert(blit);
+
+ /*
+* We create a linear BO that we'll map for the CPU to write to (using
+* cairo). This linear bo will be then blitted to its final
+* destination, tiling it at the same time.
+*/
+ bpp = igt_drm_format_to_bpp(fb->drm_format);
+ ret = create_bo_for_fb(fd, fb->width, fb->height, bpp,
+ LOCAL_DRM_FORMAT_MOD_NONE, 0,
+ &blit->linear.handle,
+ &blit->linear.size,
+ &blit->linear.stride);
+
+ igt_assert(ret == 0);
+
+ blit->fd = fd;
+ blit->fb = fb;
+ blit->linear.map = gem_mmap__cpu(fd,
+blit->linear.handle,
+0,
+blit->linear.size,
+PROT_READ | PROT_WRITE);
+ igt_assert(blit->linear.map);
+
+ gem_set_domain(fd, blit->linear.handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+
+ cairo_format = drm_format_to_cairo(fb->drm_format);
+ fb->cairo_surface =
+ cairo_image_surface_create_for_data(blit->linear.map,
+ cairo_format,
+ fb->width, fb->height,
+ blit->linear.stride);
+
+ cairo_surface_set_user_data(fb->cairo_surface,
+ (cairo_user_data_key_t
*)create_cairo_surface__blit,
+ blit, destroy_cairo_surface__blit);
+}
+
static void destroy_cairo_surface__gtt(void *arg)
{
[Intel-gfx] [PATCH i-g-t 08/13] tiling: Convert framebuffer helpers to use fb modifiers
From: Tvrtko Ursulin
This converts the IGT API only, underneath legacy set_tiling is still used.
v2: One got away in kms_flip.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_fb.c| 20 ++--
lib/igt_fb.h| 10 +-
lib/igt_kms.h | 1 +
tests/kms_3d.c | 2 +-
tests/kms_cursor_crc.c | 8 +---
tests/kms_fbc_crc.c | 4 ++--
tests/kms_fence_pin_leak.c | 4 ++--
tests/kms_flip.c| 8
tests/kms_flip_event_leak.c | 4 ++--
tests/kms_flip_tiling.c | 7 ---
tests/kms_mmio_vs_cs_flip.c | 12 ++--
tests/kms_pipe_crc_basic.c | 2 +-
tests/kms_plane.c | 8
tests/kms_psr_sink_crc.c| 8 +---
tests/kms_pwrite_crc.c | 4 ++--
tests/kms_render.c | 8
tests/kms_rotation_crc.c| 4 ++--
tests/kms_setmode.c | 2 +-
tests/kms_sink_crc_basic.c | 6 --
tests/kms_universal_plane.c | 18 +-
tests/pm_lpsp.c | 2 +-
tests/pm_rpm.c | 26 ++
tests/testdisplay.c | 4 ++--
23 files changed, 91 insertions(+), 81 deletions(-)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 9b41301..853b2f9 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -75,7 +75,7 @@ static struct format_desc_struct {
/* helpers to create nice-looking framebuffers */
static int create_bo_for_fb(int fd, int width, int height, int bpp,
- unsigned int tiling, unsigned bo_size,
+ uint64_t tiling, unsigned bo_size,
uint32_t *gem_handle_ret,
unsigned *size_ret,
unsigned *stride_ret)
@@ -84,7 +84,7 @@ static int create_bo_for_fb(int fd, int width, int height,
int bpp,
int size, ret = 0;
unsigned stride;
- if (tiling) {
+ if (tiling != LOCAL_DRM_FORMAT_MOD_NONE) {
int v;
/* Round the tiling up to the next power-of-two and the
@@ -112,8 +112,8 @@ static int create_bo_for_fb(int fd, int width, int height,
int bpp,
bo_size = size;
gem_handle = gem_create(fd, bo_size);
- if (tiling)
- ret = __gem_set_tiling(fd, gem_handle, tiling, stride);
+ if (tiling != LOCAL_DRM_FORMAT_MOD_NONE)
+ ret = __gem_set_tiling(fd, gem_handle, I915_TILING_X, stride);
*stride_ret = stride;
*size_ret = size;
@@ -385,7 +385,7 @@ void igt_paint_image(cairo_t *cr, const char *filename,
* @width: width of the framebuffer in pixel
* @height: height of the framebuffer in pixel
* @format: drm fourcc pixel format code
- * @tiling: tiling layout of the framebuffer
+ * @tiling: tiling layout of the framebuffer (as framebuffer modifier)
* @fb: pointer to an #igt_fb structure
* @bo_size: size of the backing bo (0 for minimum needed size)
*
@@ -401,7 +401,7 @@ void igt_paint_image(cairo_t *cr, const char *filename,
*/
unsigned int
igt_create_fb_with_bo_size(int fd, int width, int height,
- uint32_t format, unsigned int tiling,
+ uint32_t format, uint64_t tiling,
struct igt_fb *fb, unsigned bo_size)
{
uint32_t handles[4];
@@ -417,7 +417,7 @@ igt_create_fb_with_bo_size(int fd, int width, int height,
bpp = igt_drm_format_to_bpp(format);
- igt_debug("%s(width=%d, height=%d, format=0x%x [bpp=%d], tiling=%d,
size=%d\n",
+ igt_debug("%s(width=%d, height=%d, format=0x%x [bpp=%d], tiling=%llx,
size=%d\n",
__func__, width, height, format, bpp, tiling, bo_size);
do_or_die(create_bo_for_fb(fd, width, height, bpp, tiling, bo_size,
&fb->gem_handle, &fb->size, &fb->stride));
@@ -460,7 +460,7 @@ igt_create_fb_with_bo_size(int fd, int width, int height,
* The kms id of the created framebuffer.
*/
unsigned int igt_create_fb(int fd, int width, int height, uint32_t format,
- unsigned int tiling, struct igt_fb *fb)
+ uint64_t tiling, struct igt_fb *fb)
{
return igt_create_fb_with_bo_size(fd, width, height, format, tiling,
fb, 0);
}
@@ -489,7 +489,7 @@ unsigned int igt_create_fb(int fd, int width, int height,
uint32_t format,
* failure.
*/
unsigned int igt_create_color_fb(int fd, int width, int height,
-uint32_t format, unsigned int tiling,
+uint32_t format, uint64_t tiling,
double r, double g, double b,
struct igt_fb *fb /* out */)
{
@@ -583,7 +583,7 @@ static void stereo_fb_layout_from_mode(struct
stereo_fb_layout *layout,
* failure.
*/
unsigned int igt_create_stereo_fb(int drm_fd, drmModeModeInfo *mode,
- uint32_t format, unsigned int tiling)
+
[Intel-gfx] [PATCH i-g-t 03/13] tests/kms_addfb: Y tiled testcases
From: Tvrtko Ursulin
v2: Moved all init into fixtures.
Signed-off-by: Tvrtko Ursulin
---
lib/ioctl_wrappers.h | 2 ++
tests/kms_addfb.c| 70 +++-
2 files changed, 71 insertions(+), 1 deletion(-)
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index 3c85e8b..99fc7fd 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -157,6 +157,8 @@ struct local_drm_mode_fb_cmd2 {
#define LOCAL_DRM_FORMAT_MOD_NONE (0)
#define LOCAL_I915_FORMAT_MOD_X_TILED local_fourcc_mod_code(INTEL, 1)
+#define LOCAL_I915_FORMAT_MOD_Y_TILED local_fourcc_mod_code(INTEL, 2)
+#define LOCAL_I915_FORMAT_MOD_Yf_TILED local_fourcc_mod_code(INTEL, 3)
#define LOCAL_DRM_IOCTL_MODE_ADDFB2DRM_IOWR(0xB8, \
struct local_drm_mode_fb_cmd2)
diff --git a/tests/kms_addfb.c b/tests/kms_addfb.c
index 58a23ea..28afdf0 100644
--- a/tests/kms_addfb.c
+++ b/tests/kms_addfb.c
@@ -38,6 +38,7 @@
#include "ioctl_wrappers.h"
#include "drmtest.h"
#include "drm_fourcc.h"
+#include "intel_chipset.h"
uint32_t gem_bo;
uint32_t gem_bo_small;
@@ -286,12 +287,77 @@ static void addfb25_tests(int fd)
}
}
+static void addfb25_ytile(int fd, int gen)
+{
+ struct local_drm_mode_fb_cmd2 f = {};
+ int shouldret;
+
+ igt_fixture {
+ gem_bo = gem_create(fd, 1024*1024*4);
+ igt_assert(gem_bo);
+ gem_bo_small = gem_create(fd, 1024*1023*4);
+ igt_assert(gem_bo_small);
+
+ shouldret = gen >= 9 ? 0 : -1;
+
+ memset(&f, 0, sizeof(f));
+
+ f.width = 1024;
+ f.height = 1024;
+ f.pixel_format = DRM_FORMAT_XRGB;
+ f.pitches[0] = 1024*4;
+ f.flags = LOCAL_DRM_MODE_FB_MODIFIERS;
+ f.modifier[0] = LOCAL_DRM_FORMAT_MOD_NONE;
+
+ f.handles[0] = gem_bo;
+ }
+
+ igt_subtest("addfb25-Y-tiled") {
+ igt_require_fb_modifiers(fd);
+
+ f.modifier[0] = LOCAL_I915_FORMAT_MOD_Y_TILED;
+ igt_assert(drmIoctl(fd, LOCAL_DRM_IOCTL_MODE_ADDFB2, &f) ==
shouldret);
+ if (!shouldret)
+ igt_assert(drmIoctl(fd, DRM_IOCTL_MODE_RMFB, &f.fb_id)
== 0);
+ f.fb_id = 0;
+ }
+
+ igt_subtest("addfb25-Yf-tiled") {
+ igt_require_fb_modifiers(fd);
+
+ f.modifier[0] = LOCAL_I915_FORMAT_MOD_Yf_TILED;
+ igt_assert(drmIoctl(fd, LOCAL_DRM_IOCTL_MODE_ADDFB2, &f) ==
shouldret);
+ if (!shouldret)
+ igt_assert(drmIoctl(fd, DRM_IOCTL_MODE_RMFB, &f.fb_id)
== 0);
+ f.fb_id = 0;
+ }
+
+ igt_subtest("addfb25-Y-tiled-small") {
+ igt_require_fb_modifiers(fd);
+ igt_require(gen >= 9);
+
+ f.modifier[0] = LOCAL_I915_FORMAT_MOD_Y_TILED;
+ f.height = 1023;
+ f.handles[0] = gem_bo_small;
+ igt_assert(drmIoctl(fd, LOCAL_DRM_IOCTL_MODE_ADDFB2, &f) < 0 &&
errno == EINVAL);
+ f.fb_id = 0;
+ }
+
+ igt_fixture {
+ gem_close(fd, gem_bo);
+ gem_close(fd, gem_bo_small);
+ }
+}
+
int fd;
+int gen;
igt_main
{
- igt_fixture
+ igt_fixture {
fd = drm_open_any_master();
+ gen = intel_gen(intel_get_drm_devid(fd));
+ }
pitch_tests(fd);
@@ -299,6 +365,8 @@ igt_main
addfb25_tests(fd);
+ addfb25_ytile(fd, gen);
+
igt_fixture
close(fd);
}
--
2.3.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 04/13] lib/skl: Add gen9 specific igt_blitter_fast_copy()
From: Damien Lespiau
v2: Adjust for BB handling changes. (Tvrtko Ursulin)
Correct XY_FAST_COPY_DST_TILING_Yf. (Tvrtko Ursulin)
v3: New tiling modes are not defined in the kernel any more. (Tvrtko Ursulin)
Signed-off-by: Damien Lespiau
Signed-off-by: Tvrtko Ursulin
---
lib/intel_batchbuffer.c | 106
lib/intel_batchbuffer.h | 17
lib/intel_reg.h | 18
3 files changed, 141 insertions(+)
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index d3efc1e..9b8ae0d 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -483,6 +483,112 @@ void igt_buf_write_to_png(struct igt_buf *buf, const char
*filename)
drm_intel_bo_unmap(buf->bo);
}
+/*
+ * pitches are in bytes if the surfaces are linear, number of dwords
+ * otherwise
+ */
+static uint32_t fast_copy_pitch(struct igt_buf *buf)
+{
+ if (buf->tiling != I915_TILING_NONE)
+ return buf->stride / 4;
+ else
+ return buf->stride;
+}
+
+/**
+ * igt_blitter_fast_copy:
+ * @batch: batchbuffer object
+ * @context: libdrm hardware context to use
+ * @src: source i-g-t buffer object
+ * @src_x: source pixel x-coordination
+ * @src_y: source pixel y-coordination
+ * @width: width of the copied rectangle
+ * @height: height of the copied rectangle
+ * @dst: destination i-g-t buffer object
+ * @dst_x: destination pixel x-coordination
+ * @dst_y: destination pixel y-coordination
+ *
+ * Copy @src into @dst using the gen9 fast copy blitter comamnd.
+ *
+ * The source and destination surfaces cannot overlap.
+ */
+void igt_blitter_fast_copy(struct intel_batchbuffer *batch,
+ struct igt_buf *src, unsigned src_x, unsigned src_y,
+ unsigned width, unsigned height,
+ struct igt_buf *dst, unsigned dst_x, unsigned dst_y)
+{
+ uint32_t src_pitch, dst_pitch;
+ uint32_t dword0 = 0, dword1 = 0;
+
+ src_pitch = fast_copy_pitch(src);
+ dst_pitch = fast_copy_pitch(dst);
+
+#define CHECK_RANGE(x) ((x) >= 0 && (x) < (1 << 15))
+ assert(CHECK_RANGE(src_x) && CHECK_RANGE(src_y) &&
+ CHECK_RANGE(dst_x) && CHECK_RANGE(dst_y) &&
+ CHECK_RANGE(width) && CHECK_RANGE(height) &&
+ CHECK_RANGE(src_x + width) && CHECK_RANGE(src_y + height) &&
+ CHECK_RANGE(dst_x + width) && CHECK_RANGE(dst_y + height) &&
+ CHECK_RANGE(src_pitch) && CHECK_RANGE(dst_pitch));
+#undef CHECK_RANGE
+
+ dword0 |= XY_FAST_COPY_BLT;
+
+ switch (src->tiling) {
+ case I915_TILING_X:
+ dword0 |= XY_FAST_COPY_SRC_TILING_X;
+ break;
+ case I915_TILING_Y:
+ case I915_TILING_Yf:
+ dword0 |= XY_FAST_COPY_SRC_TILING_Yb_Yf;
+ break;
+ case I915_TILING_Ys:
+ dword0 |= XY_FAST_COPY_SRC_TILING_Ys;
+ break;
+ case I915_TILING_NONE:
+ default:
+ break;
+ }
+
+ switch (dst->tiling) {
+ case I915_TILING_X:
+ dword0 |= XY_FAST_COPY_DST_TILING_X;
+ break;
+ case I915_TILING_Y:
+ case I915_TILING_Yf:
+ dword0 |= XY_FAST_COPY_DST_TILING_Yb_Yf;
+ break;
+ case I915_TILING_Ys:
+ dword0 |= XY_FAST_COPY_DST_TILING_Ys;
+ break;
+ case I915_TILING_NONE:
+ default:
+ break;
+ }
+
+ if (src->tiling == I915_TILING_Yf)
+ dword1 |= XY_FAST_COPY_SRC_TILING_Yf;
+ if (dst->tiling == I915_TILING_Yf)
+ dword1 |= XY_FAST_COPY_DST_TILING_Yf;
+
+ dword1 |= XY_FAST_COPY_COLOR_DEPTH_32;
+
+ BEGIN_BATCH(10, 2);
+ OUT_BATCH(dword0);
+ OUT_BATCH(dword1 | dst_pitch);
+ OUT_BATCH((dst_y << 16) | dst_x); /* dst x1,y1 */
+ OUT_BATCH(((dst_y + height) << 16) | (dst_x + width)); /* dst x2,y2 */
+ OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ OUT_BATCH(0); /* dst address upper bits */
+ OUT_BATCH((src_y << 16) | src_x); /* src x1,y1 */
+ OUT_BATCH(src_pitch);
+ OUT_RELOC(src->bo, I915_GEM_DOMAIN_RENDER, 0, 0);
+ OUT_BATCH(0); /* src address upper bits */
+ ADVANCE_BATCH();
+
+ intel_batchbuffer_flush(batch);
+}
+
/**
* igt_get_render_copyfunc:
* @devid: pci device id
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index e2afc3b..0f22cd6 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -186,6 +186,18 @@ void intel_copy_bo(struct intel_batchbuffer *batch,
long int size);
/**
+ * Yf/Ys tiling
+ *
+ * Tiling mode in the I915_TILING_... namespace for new tiling modes which are
+ * defined in the kernel. (They are not fenceable so the kernel does not need
+ * to know about them.)
+ *
+ * They are to be used the the blitting routines below.
+ */
+#defin
[Intel-gfx] [PATCH i-g-t 07/13] lib: Provide a raw version of the gen9 fast copy blits
From: Damien Lespiau
So we can use it with bare kernel types, without going through libdrm
bos.
v2: Don't forget the object handle. (Tvrtko)
Correct surface pitch calculation. (Tvrtko)
Signed-off-by: Damien Lespiau
Signed-off-by: Tvrtko Ursulin
---
lib/intel_batchbuffer.c | 134 +++-
lib/intel_batchbuffer.h | 18 +++
2 files changed, 151 insertions(+), 1 deletion(-)
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 1eeabe4..2733b14 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -41,6 +41,8 @@
#include "intel_reg.h"
#include "rendercopy.h"
#include "media_fill.h"
+#include "ioctl_wrappers.h"
+
#include
/**
@@ -487,7 +489,7 @@ void igt_buf_write_to_png(struct igt_buf *buf, const char
*filename)
* pitches are in bytes if the surfaces are linear, number of dwords
* otherwise
*/
-static uint32_t fast_copy_pitch(unsigned int stride, enum i915_tiling tiling)
+static uint32_t fast_copy_pitch(unsigned int stride, unsigned int tiling)
{
if (tiling != I915_TILING_NONE)
return stride / 4;
@@ -552,6 +554,136 @@ static uint32_t fast_copy_dword1(unsigned int src_tiling,
return dword1;
}
+static void
+fill_relocation(struct drm_i915_gem_relocation_entry *reloc,
+ uint32_t gem_handle, uint32_t offset, /* in dwords */
+ uint32_t read_domains, uint32_t write_domains)
+{
+ reloc->target_handle = gem_handle;
+ reloc->delta = 0;
+ reloc->offset = offset * sizeof(uint32_t);
+ reloc->presumed_offset = 0;
+ reloc->read_domains = read_domains;
+ reloc->write_domain = write_domains;
+}
+
+static void
+fill_object(struct drm_i915_gem_exec_object2 *obj, uint32_t gem_handle,
+ struct drm_i915_gem_relocation_entry *relocs, uint32_t count)
+{
+ memset(obj, 0, sizeof(*obj));
+ obj->handle = gem_handle;
+ obj->relocation_count = count;
+ obj->relocs_ptr = (uint64_t)relocs;
+}
+
+static void exec_blit(int fd,
+ struct drm_i915_gem_exec_object2 *objs, uint32_t count,
+ uint32_t batch_len /* in dwords */)
+{
+ struct drm_i915_gem_execbuffer2 exec;
+
+ exec.buffers_ptr = (uint64_t)objs;
+ exec.buffer_count = count;
+ exec.batch_start_offset = 0;
+ exec.batch_len = batch_len * 4;
+ exec.DR1 = exec.DR4 = 0;
+ exec.num_cliprects = 0;
+ exec.cliprects_ptr = 0;
+ exec.flags = I915_EXEC_BLT;
+ i915_execbuffer2_set_context_id(exec, 0);
+ exec.rsvd2 = 0;
+
+ gem_execbuf(fd, &exec);
+}
+
+/**
+ * igt_blitter_fast_copy__raw:
+ * @fd: file descriptor of the i915 driver
+ * @src_handle: GEM handle of the source buffer
+ * @src_stride: Stride (in bytes) of the source buffer
+ * @src_tiling: Tiling mode of the source buffer
+ * @src_x: X coordinate of the source region to copy
+ * @src_y: Y coordinate of the source region to copy
+ * @width: Width of the region to copy
+ * @height: Height of the region to copy
+ * @dst_handle: GEM handle of the source buffer
+ * @dst_stride: Stride (in bytes) of the destination buffer
+ * @dst_tiling: Tiling mode of the destination buffer
+ * @dst_x: X coordinate of destination
+ * @dst_y: Y coordinate of destination
+ *
+ * Like igt_blitter_fast_copy(), but talking to the kernel directly.
+ */
+void igt_blitter_fast_copy__raw(int fd,
+ /* src */
+ uint32_t src_handle,
+ unsigned int src_stride,
+ unsigned int src_tiling,
+ unsigned int src_x, unsigned src_y,
+
+ /* size */
+ unsigned int width, unsigned int height,
+
+ /* dst */
+ uint32_t dst_handle,
+ unsigned int dst_stride,
+ unsigned int dst_tiling,
+ unsigned int dst_x, unsigned dst_y)
+{
+ uint32_t batch[12];
+ struct drm_i915_gem_exec_object2 objs[3];
+ struct drm_i915_gem_relocation_entry relocs[2];
+ uint32_t batch_handle;
+ uint32_t dword0, dword1;
+ uint32_t src_pitch, dst_pitch;
+ int i = 0;
+
+ src_pitch = fast_copy_pitch(src_stride, src_tiling);
+ dst_pitch = fast_copy_pitch(dst_stride, dst_tiling);
+ dword0 = fast_copy_dword0(src_tiling, dst_tiling);
+ dword1 = fast_copy_dword1(src_tiling, dst_tiling);
+
+#define CHECK_RANGE(x) ((x) >= 0 && (x) < (1 << 15))
+ assert(CHECK_RANGE(src_x) && CHECK_RANGE(src_y) &&
+ CHECK_RANGE(dst_x) && CHECK_RANGE(dst_y) &&
+ CHECK_RANGE(width) && CHECK_RANGE(height) &&
+ CHECK_RANGE(src_x + width) && CHECK_RANGE(src_y + height) &&
+ CHECK_RANGE(dst_x + width) && CHECK_RANGE(dst_y + height) &&
+
Re: [Intel-gfx] [PATCH v3] intel: New libdrm interface to create unbound wc user mappings for objects
On Tue, Dec 09, 2014 at 04:53:01PM +, Damien Lespiau wrote: > Right that leaves the last point in my answer to v3. With that addressed > this is: > > Reviewed-by: Damien Lespiau Hum it seems that we've upstreamed the kernel part without the libdrm API. Is it time to fix this? Akash, Chris, any objection if I push this v3? is there a more up-to-date patch that was exercised by some driver? Thanks, -- Damien ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 7/8] drm/i915/skl: Query display address through a wrapper
From: Tvrtko Ursulin
Need to do this in order to support 90/270 rotated display.
v2: Pass in drm_plane instead of plane index to intel_obj_display_address.
v3:
* Renamed intel_obj_display_address to intel_plane_obj_offset.
(Chris Wilson)
* Simplified rotation check to bitwise AND. (Chris Wilson)
v4:
* Extracted 90/270 rotation check into a helper function. (Michel Thierry)
For: VIZ-4545
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++
drivers/gpu/drm/i915/i915_gem.c | 4 ++--
drivers/gpu/drm/i915/intel_display.c | 24 ++--
drivers/gpu/drm/i915/intel_drv.h | 8
drivers/gpu/drm/i915/intel_sprite.c | 5 -
5 files changed, 39 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 79d3f2c..98a4ac5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2861,6 +2861,13 @@ i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
}
static inline unsigned long
+i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *obj,
+ enum i915_ggtt_view_type view)
+{
+ return i915_gem_obj_offset_view(obj, i915_obj_to_ggtt(obj), view);
+}
+
+static inline unsigned long
i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
{
return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 04c0cb1..f752c7f5a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5168,8 +5168,8 @@ unsigned long i915_gem_obj_offset_view(struct
drm_i915_gem_object *o,
return vma->node.start;
}
- WARN(1, "%s vma for this object not found.\n",
-i915_is_ggtt(vm) ? "global" : "ppgtt");
+ WARN(1, "%s vma for this object not found. (view=%u)\n",
+i915_is_ggtt(vm) ? "global" : "ppgtt", view);
return -1;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4174d52..6cb878b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2360,8 +2360,7 @@ int intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
if (!plane_state)
return 0;
- if (!(plane_state->rotation &
- (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270
+ if (!intel_rotation_90_or_270(plane_state->rotation))
return 0;
*view = rotated_view;
@@ -2966,6 +2965,17 @@ u32 intel_fb_stride_alignment(struct drm_device *dev,
uint64_t fb_modifier,
}
}
+unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
+struct drm_i915_gem_object *obj)
+{
+ enum i915_ggtt_view_type view = I915_GGTT_VIEW_NORMAL;
+
+ if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
+ view = I915_GGTT_VIEW_ROTATED;
+
+ return i915_gem_obj_ggtt_offset_view(obj, view);
+}
+
static void skylake_update_primary_plane(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
int x, int y)
@@ -2976,6 +2986,7 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
struct drm_i915_gem_object *obj;
int pipe = intel_crtc->pipe;
u32 plane_ctl, stride_div;
+ unsigned long surf_addr;
if (!intel_crtc->primary_enabled) {
I915_WRITE(PLANE_CTL(pipe, 0), 0);
@@ -3042,11 +3053,12 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
obj = intel_fb_obj(fb);
stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
fb->pixel_format);
+ surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj);
I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
- i915_gem_obj_ggtt_offset(obj),
+ surf_addr,
x, y, fb->width, fb->height,
fb->pitches[0]);
@@ -3056,7 +3068,7 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
(intel_crtc->config->pipe_src_h - 1) << 16 |
(intel_crtc->config->pipe_src_w - 1));
I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
- I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
+ I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
POSTING_READ(PLANE_SURF(pipe, 0));
}
@@ -10088,8 +10100,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
if (ret)
goto cleanup_pending;
- work->gtt_offset =
- i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
+ work->gtt_offset = intel_plan
[Intel-gfx] [PATCH 6/8] drm/i915/skl: Support secondary (rotated) frame buffer mapping
From: Tvrtko Ursulin
90/270 rotated scanout needs a rotated GTT view of the framebuffer.
This is put in a separate VMA with a dedicated ggtt view and wired such that
it is created when a framebuffer is pinned to a 90/270 rotated plane.
Rotation is only possible with Yb/Yf buffers and error is propagated to
user space in case of a mismatch.
Special rotated page view is constructed at the VMA creation time by
borrowing the DMA addresses from obj->pages.
v2:
* Do not bother with pages for rotated sg list, just populate the DMA
addresses. (Daniel Vetter)
* Checkpatch cleanup.
v3:
* Rebased on top of new plane handling (create rotated mapping when
setting the rotation property).
* Unpin rotated VMA on unpinning from display plane.
* Simplify rotation check using bitwise AND. (Chris Wilson)
v4:
* Fix unpinning of optional rotated mapping so it is really considered
to be optional.
v5:
* Rebased for fb modifier changes.
* Rebased for atomic commit.
* Only pin needed view for display. (Ville Syrjälä, Daniel Vetter)
v6:
* Rebased after preparatory work has been extracted out. (Daniel Vetter)
For: VIZ-4726
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Michel Thierry (v4)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 14 +++-
drivers/gpu/drm/i915/i915_gem_gtt.h | 12
drivers/gpu/drm/i915/intel_display.c | 129 ++-
drivers/gpu/drm/i915/intel_drv.h | 3 +
4 files changed, 155 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index bd95776..9336142 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2375,11 +2375,16 @@ i915_gem_obj_lookup_or_create_vma_view(struct
drm_i915_gem_object *obj,
static inline
int i915_get_vma_pages(struct i915_vma *vma)
{
+ int ret = 0;
+
if (vma->ggtt_view.pages)
return 0;
if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
vma->ggtt_view.pages = vma->obj->pages;
+ else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
+ vma->ggtt_view.pages =
+ intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
else
WARN_ONCE(1, "GGTT view %u not implemented!\n",
vma->ggtt_view.type);
@@ -2387,10 +2392,15 @@ int i915_get_vma_pages(struct i915_vma *vma)
if (!vma->ggtt_view.pages) {
DRM_ERROR("Failed to get pages for VMA view type %u!\n",
vma->ggtt_view.type);
- return -EINVAL;
+ ret = -EINVAL;
+ } else if (IS_ERR(vma->ggtt_view.pages)) {
+ ret = PTR_ERR(vma->ggtt_view.pages);
+ vma->ggtt_view.pages = NULL;
+ DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
+ vma->ggtt_view.type, ret);
}
- return 0;
+ return ret;
}
/**
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index c9e93f5..56a2356 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -111,12 +111,24 @@ typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
enum i915_ggtt_view_type {
I915_GGTT_VIEW_NORMAL = 0,
+ I915_GGTT_VIEW_ROTATED
+};
+
+struct intel_rotation_info {
+ unsigned int pixel_size;
+ unsigned int height;
+ unsigned int pitch;
+ uint64_t fb_modifier;
};
struct i915_ggtt_view {
enum i915_ggtt_view_type type;
struct sg_table *pages;
+
+ union {
+ struct intel_rotation_info rotation_info;
+ };
};
extern const struct i915_ggtt_view i915_ggtt_view_normal;
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 234a649..4174d52 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2245,13 +2245,140 @@ intel_fb_align_height(struct drm_device *dev, int
height, uint32_t pixel_format,
}
static
+void rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height,
+ struct sg_table *st)
+{
+ unsigned int column, row;
+ unsigned int src_idx;
+ struct scatterlist *sg = st->sgl;
+
+ st->nents = 0;
+
+ for (column = 0; column < width; column++) {
+ src_idx = width * (height - 1) + column;
+ for (row = 0; row < height; row++) {
+ st->nents++;
+ /* We don't need the pages, but need to initialize
+* the entries so the sg list can be happily traversed.
+* The only thing we need are DMA addresses.
+*/
+ sg_set_page(sg, NULL, PAGE_SIZE, 0);
+ sg_dma_address(sg) = in[src_idx];
+ sg_dma_len(sg) = PAGE_SIZE;
+
[Intel-gfx] [PATCH 1/8] drm: Pass in new and old plane state to prepare_fb and cleanup_fb
From: Tvrtko Ursulin
Use cases like rotation require these hooks to have some context so they
know how to prepare and cleanup the frame buffer correctly.
For i915 specifically, object backing pages need to be mapped differently
for different rotation modes and the driver needs to know which mapping to
instantiate and which to tear down when transitioning between them.
v2: Made passed in states const. (Daniel Vetter)
Signed-off-by: Tvrtko Ursulin
Cc: Daniel Vetter
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/drm_atomic_helper.c | 13 -
drivers/gpu/drm/drm_plane_helper.c| 5 +++--
drivers/gpu/drm/i915/intel_display.c | 6 --
drivers/gpu/drm/i915/intel_drv.h | 6 --
drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c | 6 --
drivers/gpu/drm/tegra/dc.c| 6 --
include/drm/drm_plane_helper.h| 6 --
7 files changed, 31 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index 3ce57f4..a745881 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -1116,6 +1116,7 @@ int drm_atomic_helper_prepare_planes(struct drm_device
*dev,
for (i = 0; i < nplanes; i++) {
struct drm_plane_helper_funcs *funcs;
struct drm_plane *plane = state->planes[i];
+ struct drm_plane_state *plane_state = state->plane_states[i];
struct drm_framebuffer *fb;
if (!plane)
@@ -1123,10 +1124,10 @@ int drm_atomic_helper_prepare_planes(struct drm_device
*dev,
funcs = plane->helper_private;
- fb = state->plane_states[i]->fb;
+ fb = plane_state->fb;
if (fb && funcs->prepare_fb) {
- ret = funcs->prepare_fb(plane, fb);
+ ret = funcs->prepare_fb(plane, fb, plane_state);
if (ret)
goto fail;
}
@@ -1138,6 +1139,7 @@ fail:
for (i--; i >= 0; i--) {
struct drm_plane_helper_funcs *funcs;
struct drm_plane *plane = state->planes[i];
+ struct drm_plane_state *plane_state = state->plane_states[i];
struct drm_framebuffer *fb;
if (!plane)
@@ -1148,7 +1150,7 @@ fail:
fb = state->plane_states[i]->fb;
if (fb && funcs->cleanup_fb)
- funcs->cleanup_fb(plane, fb);
+ funcs->cleanup_fb(plane, fb, plane_state);
}
@@ -1254,6 +1256,7 @@ void drm_atomic_helper_cleanup_planes(struct drm_device
*dev,
for (i = 0; i < nplanes; i++) {
struct drm_plane_helper_funcs *funcs;
struct drm_plane *plane = old_state->planes[i];
+ struct drm_plane_state *plane_state =
old_state->plane_states[i];
struct drm_framebuffer *old_fb;
if (!plane)
@@ -1261,10 +1264,10 @@ void drm_atomic_helper_cleanup_planes(struct drm_device
*dev,
funcs = plane->helper_private;
- old_fb = old_state->plane_states[i]->fb;
+ old_fb = plane_state->fb;
if (old_fb && funcs->cleanup_fb)
- funcs->cleanup_fb(plane, old_fb);
+ funcs->cleanup_fb(plane, old_fb, plane_state);
}
}
EXPORT_SYMBOL(drm_atomic_helper_cleanup_planes);
diff --git a/drivers/gpu/drm/drm_plane_helper.c
b/drivers/gpu/drm/drm_plane_helper.c
index 5ba5792..813a066 100644
--- a/drivers/gpu/drm/drm_plane_helper.c
+++ b/drivers/gpu/drm/drm_plane_helper.c
@@ -437,7 +437,8 @@ int drm_plane_helper_commit(struct drm_plane *plane,
if (plane_funcs->prepare_fb && plane_state->fb &&
plane_state->fb != old_fb) {
- ret = plane_funcs->prepare_fb(plane, plane_state->fb);
+ ret = plane_funcs->prepare_fb(plane, plane_state->fb,
+ plane_state);
if (ret)
goto out;
}
@@ -487,7 +488,7 @@ int drm_plane_helper_commit(struct drm_plane *plane,
}
if (plane_funcs->cleanup_fb && old_fb)
- plane_funcs->cleanup_fb(plane, old_fb);
+ plane_funcs->cleanup_fb(plane, old_fb, plane_state);
out:
if (plane_state) {
if (plane->funcs->atomic_destroy_state)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3156d77..abeef74 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11891,7 +11891,8 @@ static void intel_shared_dpll_init(struct drm_device
*dev)
*/
int
intel_prepare_plane_fb(struct drm_plane *plane,
- struct drm_framebuffer *fb)
+ struct drm_framebuffer *fb,
+ const struct drm
[Intel-gfx] [PATCH 4/8] drm/i915: Pass in plane state when (un)pinning frame buffers
From: Tvrtko Ursulin
Plane state carries the rotation information which is needed for determining
the appropriate GGTT view type.
This just adds the parameter with the actual usage coming in future patches.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_display.c | 18 --
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
3 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8b210fc..daa7ee2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2247,6 +2247,7 @@ intel_fb_align_height(struct drm_device *dev, int height,
uint32_t pixel_format,
int
intel_pin_and_fence_fb_obj(struct drm_plane *plane,
struct drm_framebuffer *fb,
+ const struct drm_plane_state *plane_state,
struct intel_engine_cs *pipelined)
{
struct drm_device *dev = fb->dev;
@@ -2334,8 +2335,11 @@ err_interruptible:
return ret;
}
-static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
+static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
+ const struct drm_plane_state *plane_state)
{
+ struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+
WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
i915_gem_object_unpin_fence(obj);
@@ -9224,7 +9228,7 @@ static void intel_unpin_work_fn(struct work_struct
*__work)
enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
mutex_lock(&dev->struct_mutex);
- intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
+ intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
drm_gem_object_unreference(&work->pending_flip_obj->base);
drm_framebuffer_unreference(work->old_fb);
@@ -9932,7 +9936,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
ring = &dev_priv->ring[RCS];
}
- ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
+ ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
+crtc->primary->state, ring);
if (ret)
goto cleanup_pending;
@@ -9972,7 +9977,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
return 0;
cleanup_unpin:
- intel_unpin_fb_obj(obj);
+ intel_unpin_fb_obj(fb, crtc->primary->state);
cleanup_pending:
atomic_dec(&intel_crtc->unpin_work_count);
crtc->primary->fb = old_fb;
@@ -11934,7 +11939,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
if (ret)
DRM_DEBUG_KMS("failed to attach phys object\n");
} else {
- ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
+ ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
}
if (ret == 0)
@@ -11966,7 +11971,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
if (plane->type != DRM_PLANE_TYPE_CURSOR ||
!INTEL_INFO(dev)->cursor_needs_physical) {
mutex_lock(&dev->struct_mutex);
- intel_unpin_fb_obj(obj);
+ intel_unpin_fb_obj(fb, old_state);
mutex_unlock(&dev->struct_mutex);
}
}
@@ -13863,6 +13868,7 @@ void intel_modeset_gem_init(struct drm_device *dev)
if (intel_pin_and_fence_fb_obj(c->primary,
c->primary->fb,
+ c->primary->state,
NULL)) {
DRM_ERROR("failed to pin boot fb on pipe %d\n",
to_intel_crtc(c)->pipe);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8e0c3f9..5b82470 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -956,6 +956,7 @@ void intel_release_load_detect_pipe(struct drm_connector
*connector,
struct intel_load_detect_pipe *old);
int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
struct drm_framebuffer *fb,
+ const struct drm_plane_state *plane_state,
struct intel_engine_cs *pipelined);
struct drm_framebuffer *
__intel_framebuffer_create(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
b/drivers/gpu/drm/i915/intel_fbdev.c
index 234a699..d8204ae 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -126,7 +126,7 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
}
/* Flush everything out, we'll be doing GTT only from now on */
- ret = intel_pin_and_fence_fb_obj(NULL, fb, NULL);
+ ret = intel_pin_and_fence_fb_obj(NULL, fb, NULL, NULL);
if (ret) {
[Intel-gfx] [PATCH 8/8] drm/i915/skl: Take 90/270 rotation into account in watermark calculations
From: Tvrtko Ursulin
v2: Pass in rotation info to sprite plane updates as well.
v3: Use helper to determine 90/270 rotation. (Michel Thierry)
v4: Rebased for fb modifiers and atomic changes.
For: VIZ-4546
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Michel Thierry (v3)
---
drivers/gpu/drm/i915/intel_display.c | 27 +++
drivers/gpu/drm/i915/intel_drv.h | 4
drivers/gpu/drm/i915/intel_pm.c | 18 +-
drivers/gpu/drm/i915/intel_sprite.c | 5 +
4 files changed, 45 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 6cb878b..f3c6a0d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12050,6 +12050,28 @@ static void intel_shared_dpll_init(struct drm_device
*dev)
}
/**
+ * intel_wm_need_update - Check whether watermarks need updating
+ * @plane: drm plane
+ * @state: new plane state
+ *
+ * Check current plane state versus the new one to determine whether
+ * watermarks need to be recalculated.
+ *
+ * Returns true or false.
+ */
+bool intel_wm_need_update(struct drm_plane *plane,
+ struct drm_plane_state *state)
+{
+ /* Update watermarks on tiling changes. */
+ if (!plane->state->fb || !state->fb ||
+ plane->state->fb->modifier[0] != state->fb->modifier[0] ||
+ plane->state->rotation != state->rotation)
+ return true;
+
+ return false;
+}
+
+/**
* intel_prepare_plane_fb - Prepare fb for usage on plane
* @plane: drm plane to prepare for
* @fb: framebuffer to prepare for presentation
@@ -12195,10 +12217,7 @@ intel_check_primary_plane(struct drm_plane *plane,
intel_crtc->atomic.update_fbc = true;
- /* Update watermarks on tiling changes. */
- if (!plane->state->fb || !state->base.fb ||
- plane->state->fb->modifier[0] !=
- state->base.fb->modifier[0])
+ if (intel_wm_need_update(plane, &state->base))
intel_crtc->atomic.update_wm = true;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9fabe37..e0a4e4e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -501,6 +501,7 @@ struct intel_plane_wm_parameters {
bool enabled;
bool scaled;
u64 tiling;
+ unsigned int rotation;
};
struct intel_plane {
@@ -989,6 +990,9 @@ intel_rotation_90_or_270(unsigned int rotation)
struct sg_table *intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
struct drm_i915_gem_object *obj);
+bool intel_wm_need_update(struct drm_plane *plane,
+ struct drm_plane_state *state);
+
/* shared dpll functions */
struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
void assert_shared_dpll(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0bf6767..bc90a14 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2712,6 +2712,7 @@ static void skl_compute_wm_pipe_parameters(struct
drm_crtc *crtc,
*/
if (fb)
p->plane[0].tiling = fb->modifier[0];
+ p->plane[0].rotation = crtc->primary->state->rotation;
p->cursor.enabled = true;
p->cursor.bytes_per_pixel = 4;
@@ -2761,7 +2762,21 @@ static bool skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
- uint32_t y_tile_minimum = plane_blocks_per_line * 4;
+ uint32_t min_scanlines = 4;
+ uint32_t y_tile_minimum;
+ if (intel_rotation_90_or_270(p_params->rotation)) {
+ switch (p_params->bytes_per_pixel) {
+ case 1:
+ min_scanlines = 16;
+ break;
+ case 2:
+ min_scanlines = 8;
+ break;
+ case 8:
+ WARN(1, "Unsupported pixel depth for rotation");
+ };
+ }
+ y_tile_minimum = plane_blocks_per_line * min_scanlines;
selected_result = max(method2, y_tile_minimum);
} else {
if ((ddb_allocation / plane_blocks_per_line) >= 1)
@@ -3222,6 +3237,7 @@ skl_update_sprite_wm(struct drm_plane *plane, struct
drm_crtc *crtc,
*/
if (fb)
intel_plane->wm.tiling = fb->modifier[0];
+ intel_plane->wm.rotation = plane->state->rotation;
skl_update_wm(crtc);
}
diff --git a/drivers/gpu/dr
[Intel-gfx] [PATCH 2/8] drm/i915/skl: Extract tile height code into a helper function
From: Tvrtko Ursulin
It will be used in a later patch.
v2: Rebased for fb modifiers.
v3: Fixed v2 rebase.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Michel Thierry (v1)
---
drivers/gpu/drm/i915/intel_display.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index abeef74..e6f2533 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2189,13 +2189,11 @@ static bool need_vtd_wa(struct drm_device *dev)
return false;
}
-int
-intel_fb_align_height(struct drm_device *dev, int height,
- uint32_t pixel_format,
- uint64_t fb_format_modifier)
+static int
+intel_tile_height(struct drm_device *dev, uint32_t bits_per_pixel,
+ uint64_t fb_format_modifier)
{
int tile_height;
- uint32_t bits_per_pixel;
switch (fb_format_modifier) {
case DRM_FORMAT_MOD_NONE:
@@ -2208,7 +2206,6 @@ intel_fb_align_height(struct drm_device *dev, int height,
tile_height = 32;
break;
case I915_FORMAT_MOD_Yf_TILED:
- bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
switch (bits_per_pixel) {
default:
case 8:
@@ -2234,7 +2231,17 @@ intel_fb_align_height(struct drm_device *dev, int height,
break;
}
- return ALIGN(height, tile_height);
+ return tile_height;
+}
+
+int
+intel_fb_align_height(struct drm_device *dev, int height, uint32_t
pixel_format,
+ uint64_t fb_format_modifier)
+{
+ uint32_t bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
+
+ return ALIGN(height, intel_tile_height(dev, bits_per_pixel,
+ fb_format_modifier));
}
int
--
2.3.0
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[Intel-gfx] [PATCH v2 0/8] Skylake 90/270 display rotation
From: Tvrtko Ursulin Display engine on Skylake can scan out specially prepared frame buffers rotated by 90 or 270 degrees. This adds partial support for that - display programming patches are missing from this initial posting because for now the only purpose is to see if people now like the approach I have taken. v2: * Individual review comments. * Main patch split into four smaller ones. Tvrtko Ursulin (8): drm: Pass in new and old plane state to prepare_fb and cleanup_fb drm/i915/skl: Extract tile height code into a helper function drm/i915: Use GGTT view when (un)pinning objects to planes drm/i915: Pass in plane state when (un)pinning frame buffers drm/i915: Helper function to determine GGTT view from plane state drm/i915/skl: Support secondary (rotated) frame buffer mapping drm/i915/skl: Query display address through a wrapper drm/i915/skl: Take 90/270 rotation into account in watermark calculations drivers/gpu/drm/drm_atomic_helper.c | 13 +- drivers/gpu/drm/drm_plane_helper.c| 5 +- drivers/gpu/drm/i915/i915_drv.h | 40 - drivers/gpu/drm/i915/i915_gem.c | 31 ++-- drivers/gpu/drm/i915/i915_gem_gtt.c | 14 +- drivers/gpu/drm/i915/i915_gem_gtt.h | 12 ++ drivers/gpu/drm/i915/intel_display.c | 246 ++ drivers/gpu/drm/i915/intel_drv.h | 22 ++- drivers/gpu/drm/i915/intel_fbdev.c| 2 +- drivers/gpu/drm/i915/intel_overlay.c | 3 +- drivers/gpu/drm/i915/intel_pm.c | 18 ++- drivers/gpu/drm/i915/intel_sprite.c | 10 +- drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c | 6 +- drivers/gpu/drm/tegra/dc.c| 6 +- include/drm/drm_plane_helper.h| 6 +- 15 files changed, 367 insertions(+), 67 deletions(-) -- 2.3.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/8] drm/i915: Helper function to determine GGTT view from plane state
From: Tvrtko Ursulin
For now only default implementation defaulting to normal view.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_display.c | 26 +++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index daa7ee2..234a649 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2244,6 +2244,16 @@ intel_fb_align_height(struct drm_device *dev, int
height, uint32_t pixel_format,
fb_format_modifier));
}
+static
+int intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
+ struct drm_framebuffer *fb,
+ const struct drm_plane_state *plane_state)
+{
+ *view = i915_ggtt_view_normal;
+
+ return 0;
+}
+
int
intel_pin_and_fence_fb_obj(struct drm_plane *plane,
struct drm_framebuffer *fb,
@@ -2253,6 +2263,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
struct drm_device *dev = fb->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+ struct i915_ggtt_view view;
u32 alignment;
int ret;
@@ -2289,6 +2300,10 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
return -EINVAL;
}
+ ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
+ if (ret < 0)
+ return ret;
+
/* Note that the w/a also requires 64 PTE of padding following the
* bo. We currently fill all unused PTE with the shadow page and so
* we should always have valid PTE following the scanout preventing
@@ -2308,7 +2323,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
dev_priv->mm.interruptible = false;
ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
- &i915_ggtt_view_normal);
+ &view);
if (ret)
goto err_interruptible;
@@ -2328,7 +2343,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
return 0;
err_unpin:
- i915_gem_object_unpin_from_display_plane(obj, &i915_ggtt_view_normal);
+ i915_gem_object_unpin_from_display_plane(obj, &view);
err_interruptible:
dev_priv->mm.interruptible = true;
intel_runtime_pm_put(dev_priv);
@@ -2339,11 +2354,16 @@ static void intel_unpin_fb_obj(struct drm_framebuffer
*fb,
const struct drm_plane_state *plane_state)
{
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+ struct i915_ggtt_view view;
+ int ret;
WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
+ ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
+ WARN_ONCE(ret < 0, "Couldn't get view from plane state!");
+
i915_gem_object_unpin_fence(obj);
- i915_gem_object_unpin_from_display_plane(obj, &i915_ggtt_view_normal);
+ i915_gem_object_unpin_from_display_plane(obj, &view);
}
/* Computes the linear offset to the base tile and adjusts x, y. bytes per
pixel
--
2.3.0
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[Intel-gfx] [PATCH 3/8] drm/i915: Use GGTT view when (un)pinning objects to planes
From: Tvrtko Ursulin
To support frame buffer rotation we need to be able to pass on the information
on what kind of GGTT view is required for display.
This patch just adds the parameter and makes all the callers default to the
normal view.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 33 +
drivers/gpu/drm/i915/i915_gem.c | 27 +--
drivers/gpu/drm/i915/intel_display.c | 7 ---
drivers/gpu/drm/i915/intel_overlay.c | 3 ++-
4 files changed, 52 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e07a1cb..79d3f2c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2743,8 +2743,10 @@ i915_gem_object_set_to_cpu_domain(struct
drm_i915_gem_object *obj, bool write);
int __must_check
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
u32 alignment,
-struct intel_engine_cs *pipelined);
-void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
+struct intel_engine_cs *pipelined,
+const struct i915_ggtt_view *view);
+void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
+ const struct i915_ggtt_view
*view);
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
int align);
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
@@ -2813,7 +2815,13 @@ i915_gem_obj_lookup_or_create_vma(struct
drm_i915_gem_object *obj,
&i915_ggtt_view_normal);
}
-struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
+struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
+ enum i915_ggtt_view_type view);
+static inline
+struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
+{
+ return i915_gem_obj_to_ggtt_view(obj, I915_GGTT_VIEW_NORMAL);
+}
static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
struct i915_vma *vma;
list_for_each_entry(vma, &obj->vma_list, vma_link)
@@ -2867,13 +2875,30 @@ i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
alignment, flags | PIN_GLOBAL);
}
+static inline int __must_check
+i915_gem_obj_ggtt_pin_view(struct drm_i915_gem_object *obj,
+ uint32_t alignment,
+ unsigned flags,
+ const struct i915_ggtt_view *ggtt_view)
+{
+ return i915_gem_object_pin_view(obj, i915_obj_to_ggtt(obj),
+ alignment, flags | PIN_GLOBAL,
+ ggtt_view);
+}
+
static inline int
i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
{
return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
}
-void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
+void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
+enum i915_ggtt_view_type view);
+static inline void
+i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
+{
+ i915_gem_object_ggtt_unpin_view(obj, I915_GGTT_VIEW_NORMAL);
+}
/* i915_gem_context.c */
int __must_check i915_gem_context_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0107c2a..04c0cb1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3938,7 +3938,8 @@ static bool is_pin_display(struct drm_i915_gem_object
*obj)
int
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
u32 alignment,
-struct intel_engine_cs *pipelined)
+struct intel_engine_cs *pipelined,
+const struct i915_ggtt_view *view)
{
u32 old_read_domains, old_write_domain;
bool was_pin_display;
@@ -3974,7 +3975,9 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
* (e.g. libkms for the bootup splash), we have to ensure that we
* always use map_and_fenceable for all scanout buffers.
*/
- ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
+ ret = i915_gem_obj_ggtt_pin_view(obj, alignment,
+view->type == I915_GGTT_VIEW_NORMAL ?
+PIN_MAPPABLE : 0, view);
if (ret)
goto err_unpin_display;
@@ -4002,9 +4005,11 @@ err_unpin_display:
}
void
-i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
+i915_gem_object_unpin_from_dis
Re: [Intel-gfx] [v2 5/5] drm/i915: Update prop, int co-eff and gain threshold for CHV
On 2/16/2015 5:02 PM, Ville Syrjälä wrote:
On Mon, Feb 16, 2015 at 03:08:02PM +0530, Vijay Purushothaman wrote:
This patch implements latest PHY changes in Gain, prop and int co-efficients
based on the vco freq.
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 42 --
2 files changed, 31 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5814f67..b5bce4e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1027,6 +1027,7 @@ enum skl_disp_power_wells {
#define _CHV_PLL_DW8_CH0 0x8020
#define _CHV_PLL_DW8_CH1 0x81A0
+#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
#define _CHV_PLL_DW9_CH0 0x8024
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ae2a77f..ca02cf7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6039,10 +6039,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
int pipe = crtc->pipe;
int dpll_reg = DPLL(crtc->pipe);
enum dpio_channel port = vlv_pipe_to_channel(pipe);
- u32 loopfilter, intcoeff;
+ u32 loopfilter, tribuf_calcntr;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
u32 dpio_val;
- int refclk;
+ int vco;
bestn = pipe_config->dpll.n;
bestm2_frac = pipe_config->dpll.m2 & 0x3f;
@@ -6050,7 +6050,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
bestm2 = pipe_config->dpll.m2 >> 22;
bestp1 = pipe_config->dpll.p1;
bestp2 = pipe_config->dpll.p2;
+ vco = pipe_config->dpll.vco;
dpio_val = 0;
+ loopfilter = 0;
/*
* Enable Refclk and SSC
@@ -6104,18 +6106,34 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
}
/* Loop filter */
- refclk = i9xx_get_refclk(crtc, 0);
- loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
- 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
- if (refclk == 10)
- intcoeff = 11;
- else if (refclk == 38400)
- intcoeff = 10;
- else
- intcoeff = 9;
- loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
+ if (vco == 540) {
+ loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0;
In your original patch tribuf_calcntr was 9 here. Which is correct?
9 is correct. Thanks for the catch.
+ } else if (vco <= 620) {
+ loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0x9;
+ } else if (vco <= 648) {
+ loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0x8;
+ } else {
+ /* Not supported. Apply the same limits as in the max case */
+ loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
These too were different in your original patch, but I guess it doens't
matter either way that much since we should never get here.
Correct. Just for clarity, i wanted to use the max limits.
Thanks,
Vijay
+ tribuf_calcntr = 0;
+ }
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
+ dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
Need to clear out the old bits again. Seems to be 10bits by the looks of it.
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
+
/* AFC Recal */
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
--
1.7.9.5
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Re: [Intel-gfx] [v2 2/5] drm/i915: Limit max VCO supported in CHV to 6.48GHz
On 2/23/2015 9:43 PM, Daniel Vetter wrote:
On Mon, Feb 16, 2015 at 01:21:34PM +0200, Ville Syrjälä wrote:
On Mon, Feb 16, 2015 at 03:07:59PM +0530, Vijay Purushothaman wrote:
As per the recommendation from PHY team, limit the max vco supported in CHV to
6.48 GHz
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3b0fe9f..4e710f6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
* them would make no difference.
*/
.dot = { .min = 25000 * 5, .max = 54 * 5},
- .vco = { .min = 486, .max = 670 },
+ .vco = { .min = 486, .max = 648 },
I have a patch here to reduce the minimum to 4.80 GHz, otherwise I can't
get my 2560x1440 HDMI display working (241.5 MHz clock). With that change
we still have a gap (233-240 MHz) in the frequencies we can produce.
Reducing the max to 6.48 GHz will increase that gap to 216-240 MHz, which
is a bit unfortunate. But if that's the recommendation we should follow
it I suppose, and hope no HDMI displays will want such frequencies.
Is there an updated spreadsheet available with the new limits? Quite a
few of the frequencies in the original spreadsheet did have vco>6.48
GHz.
Has the updated doc been dug up meanwhile? A big part of review is getting
access to docs and making sure they're up-to-date too ...
-Daniel
I sent the copy of excel sheet that i am using to both of you in another
mail. I still end up relying on windows driver folks since they seem to
be having latest information about PHY.
Thanks,
Vijay
I any case this seems OK, so
Acked-by: Ville Syrjälä
.n = { .min = 1, .max = 1 },
.m1 = { .min = 2, .max = 2 },
.m2 = { .min = 24 << 22, .max = 175 << 22 },
--
1.7.9.5
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--
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[Intel-gfx] [PATCH 1/3] drm/i915: Disable M2 frac division for integer case
v2 : Handle M2 frac division for both M2 frac and int cases
v3 : Addressed Ville's review comments. Cleared the old bits for RMW
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 24 ++--
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 55143cb..8200e98 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1029,6 +1029,7 @@ enum skl_disp_power_wells {
#define DPIO_CHV_FIRST_MOD(0 << 8)
#define DPIO_CHV_SECOND_MOD (1 << 8)
#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
+#define DPIO_CHV_FEEDFWD_GAIN_MASK(0xF << 0)
#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
#define _CHV_PLL_DW6_CH0 0x8018
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7298796..15904a8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6131,6 +6131,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
enum dpio_channel port = vlv_pipe_to_channel(pipe);
u32 loopfilter, intcoeff;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
+ u32 dpio_val;
int refclk;
bestn = pipe_config->dpll.n;
@@ -6139,6 +6140,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
bestm2 = pipe_config->dpll.m2 >> 22;
bestp1 = pipe_config->dpll.p1;
bestp2 = pipe_config->dpll.p2;
+ dpio_val = 0;
/*
* Enable Refclk and SSC
@@ -6163,13 +6165,23 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
DPIO_CHV_M1_DIV_BY_2 |
1 << DPIO_CHV_N_DIV_SHIFT);
- /* M2 fraction division */
- vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+ if (bestm2_frac) {
+ /* M2 fraction division */
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
- /* M2 fraction division enable */
- vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
- DPIO_CHV_FRAC_DIV_EN |
- (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
+ /* M2 fraction division enable */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+ dpio_val |= DPIO_CHV_FRAC_DIV_EN;
+ dpio_val &= ~DPIO_CHV_FEEDFWD_GAIN_MASK;
+ dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+
+ } else {
+ /* M2 fraction division disable */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+ dpio_val &= ~DPIO_CHV_FRAC_DIV_EN;
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+ }
/* Loop filter */
refclk = i9xx_get_refclk(crtc, 0);
--
1.7.9.5
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[Intel-gfx] [PATCH 3/3] drm/i915: Update prop, int co-eff and gain threshold for CHV
This patch implements latest PHY changes in Gain, prop and int co-efficients
based on the vco freq.
v2: Split the original changes into multiple smaller patches based on
review by Ville
v3: Addressed Ville's review comments. Fixed the error introduced in v2.
Clear the old bits before we modify those bits as part of RMW.
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h |2 ++
drivers/gpu/drm/i915/intel_display.c | 43 --
2 files changed, 33 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1a0f94e..5000184 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1041,6 +1041,8 @@ enum skl_disp_power_wells {
#define _CHV_PLL_DW8_CH0 0x8020
#define _CHV_PLL_DW8_CH1 0x81A0
+#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
+#define DPIO_CHV_TDC_TARGET_CNT_MASK (0xFF << 0)
#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
#define _CHV_PLL_DW9_CH0 0x8024
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a6b5786..4e08a14 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6129,10 +6129,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
int pipe = crtc->pipe;
int dpll_reg = DPLL(crtc->pipe);
enum dpio_channel port = vlv_pipe_to_channel(pipe);
- u32 loopfilter, intcoeff;
+ u32 loopfilter, tribuf_calcntr;
u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
u32 dpio_val;
- int refclk;
+ int vco;
bestn = pipe_config->dpll.n;
bestm2_frac = pipe_config->dpll.m2 & 0x3f;
@@ -6140,7 +6140,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
bestm2 = pipe_config->dpll.m2 >> 22;
bestp1 = pipe_config->dpll.p1;
bestp2 = pipe_config->dpll.p2;
+ vco = pipe_config->dpll.vco;
dpio_val = 0;
+ loopfilter = 0;
/*
* Enable Refclk and SSC
@@ -6197,18 +6199,35 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
}
/* Loop filter */
- refclk = i9xx_get_refclk(crtc, 0);
- loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
- 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
- if (refclk == 10)
- intcoeff = 11;
- else if (refclk == 38400)
- intcoeff = 10;
- else
- intcoeff = 9;
- loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
+ if (vco == 540) {
+ loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 9;
+ } else if (vco <= 620) {
+ loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0x9;
+ } else if (vco <= 648) {
+ loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0x8;
+ } else {
+ /* Not supported. Apply the same limits as in the max case */
+ loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+ loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+ loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+ tribuf_calcntr = 0;
+ }
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
+ dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
+ dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
+
/* AFC Recal */
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
--
1.7.9.5
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[Intel-gfx] [PATCH 2/3] drm/i915: Initialize CHV digital lock detect threshold
Initialize lock detect threshold and select coarse threshold for the
case where M2 fraction division is disabled.
v2: Split the changes into multiple smaller patches based on review by
Ville
v3: Addressed rest of the review comments. Clear out the old bits before
we modify those bits as part of RMW
Signed-off-by: Vijay Purushothaman
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 13 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8200e98..1a0f94e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1046,6 +1046,7 @@ enum skl_disp_power_wells {
#define _CHV_PLL_DW9_CH0 0x8024
#define _CHV_PLL_DW9_CH1 0x81A4
#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
+#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE1 /* 1: coarse & 0 :
fine */
#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 15904a8..a6b5786 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6176,11 +6176,24 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+ /* Program digital lock detect threshold */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+ dpio_val &= ~DPIO_CHV_INT_LOCK_THRESHOLD_MASK;
+ dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
+
} else {
/* M2 fraction division disable */
dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
dpio_val &= ~DPIO_CHV_FRAC_DIV_EN;
vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+
+ /* Program digital lock detect threshold */
+ dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+ dpio_val &= ~DPIO_CHV_INT_LOCK_THRESHOLD_MASK;
+ dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+ dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
+ vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
}
/* Loop filter */
--
1.7.9.5
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[Intel-gfx] [PATCH] drm/i915: Setup all page directories for gen8
If the mappable size is less than what the full range
of pdps can address, we end up setting pdps for only the
mappable area.
The logical context however needs valid pdp entries.
Prior to commit 06fda602dbca ("drm/i915: Create page table allocators")
we just have been writing pdp entries with dma address of zero instead
of valid pdps. This is supposedly bad even if those pdps are not
addressed.
As commit 06fda602dbca ("drm/i915: Create page table allocators")
introduced more dynamic structure for pdps, we ended up oopsing
when we populated the lrc context. Analyzing this oops revealed
the fact that we have not been writing valid pdps with bsw, as
it is doing the ppgtt init with 2gb limit.
We should do the right thing and setup the non addressable part
pdps/pde/pte to scratch page through the minimal structure by
having just pdp with pde entries pointing to same page with
pte entries pointing to scratch page.
But instead of going through that trouble, setup all the pdps
through individual pd pages and pt entries, even for non
addressable parts. This way we populate the lrc with valid
pdps and gives us a base for dynamic page allocation to
introduce code that truncates the page table structure.
The regression of oopsing in init was introduced by
commit 06fda602dbca ("drm/i915: Create page table allocators")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89350
Tested-by: Valtteri Rantala
Cc: Michel Thierry
Cc: Ben Widawsky
Cc: Ville Syrjälä
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index bd95776..848a821 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -709,7 +709,7 @@ static int gen8_ppgtt_setup_page_tables(struct
i915_hw_ppgtt *ppgtt,
*/
static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
{
- const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
+ const int max_pdp = GEN8_LEGACY_PDPES;
const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
int i, j, ret;
--
1.9.1
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Re: [Intel-gfx] [PATCH v2] drm/i915: gen4: work around hang during hibernation
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5868 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -5 278/278 273/278 ILK 308/308 308/308 SNB -1 284/284 283/284 IVB 380/380 380/380 BYT 294/294 294/294 HSW 387/387 387/387 BDW -1 316/316 315/316 -Detailed- Platform Testdrm-intel-nightly Series Applied PNV igt_gem_userptr_blits_coherency-sync CRASH(4)PASS(7) CRASH(1)PASS(1) PNV igt_gem_userptr_blits_coherency-unsync NO_RESULT(1)CRASH(3)PASS(5) CRASH(1)PASS(1) PNV igt_gen3_render_linear_blits FAIL(3)PASS(7) FAIL(2) PNV igt_gen3_render_mixed_blits FAIL(3)PASS(9) FAIL(2) PNV igt_gem_fence_thrash_bo-write-verify-threaded-none FAIL(2)CRASH(2)PASS(3) CRASH(2) *SNB igt_gem_flink_basic PASS(2) DMESG_WARN(1)PASS(1) *BDW igt_gem_gtt_hog PASS(12) DMESG_WARN(1)PASS(1) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Add debugfs entry for DRRS
From: Vandana Kannan
Adding a debugfs entry to determine if DRRS is supported or not
V2: [By Ram]: Following details about the active crtc will be filled
in seq-file of the debugfs
1. Encoder output type
2. DRRS Support on this CRTC
3. DRRS current state
4. Current Vrefresh
Format is as follows:
CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_HIGH_RR,
Vrefresh: 60
CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_LOW_RR,
Vrefresh: 40
CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless
V3: [By Ram]: Readability is improved.
Another error case is covered [Daniel]
V4: [By Ram]: Current status of the Idleness DRRS along with
the Front buffer bits are added to the debugfs. [Rodrigo]
V5: [By Ram]: Rephrased to make it easy to understand.
And format is modified. [Rodrigo]
V6: [By Ram]: Modeset mutex are acquired for each crtc along with
renaming the Idleness detection states [Daniel]
Signed-off-by: Vandana Kannan
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_debugfs.c | 141 +++
1 file changed, 141 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 94b3984..90e56ca 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2870,6 +2870,146 @@ static int i915_ddb_info(struct seq_file *m, void
*unused)
return 0;
}
+static void drrs_status_per_crtc(struct seq_file *m,
+ struct drm_device *dev, struct intel_crtc *intel_crtc)
+{
+ struct intel_encoder *intel_encoder;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct i915_drrs *drrs = &dev_priv->drrs;
+ int vrefresh = 0;
+ u32 work_status;
+
+ for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
+ /* Encoder connected on this CRTC */
+ switch (intel_encoder->type) {
+ case INTEL_OUTPUT_EDP:
+ seq_puts(m, "eDP:\n");
+ break;
+ case INTEL_OUTPUT_DSI:
+ seq_puts(m, "DSI:\n");
+ break;
+ case INTEL_OUTPUT_HDMI:
+ seq_puts(m, "HDMI:\n");
+ break;
+ case INTEL_OUTPUT_DISPLAYPORT:
+ seq_puts(m, "DP:\n");
+ break;
+ default:
+ seq_printf(m, "Other encoder (id=%d).\n",
+ intel_encoder->type);
+ return;
+ }
+ }
+
+ if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
+ seq_puts(m, "\tVBT: DRRS_type: Static");
+ else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
+ seq_puts(m, "\tVBT: DRRS_type: Seamless");
+ else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
+ seq_puts(m, "\tVBT: DRRS_type: None");
+ else
+ seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
+
+ seq_puts(m, "\n\n");
+
+ /*
+* Idleness DRRS detection states:
+* Enabled : Idleness detection is active. When system is
+* Idle for the defined duration DRRS_LOW_RR
+* will be set. Or Idleness is already detected
+* and DRRS_LOW_RR is applied.
+* Suspended : Due to frontbuffer's busy state, Idleness
+* detection is suspended.
+* Disabled : Idleness detection is disabled until a call is
+* made to enable. No encoder pointer will be
+* available.
+*/
+ if (intel_crtc->config->has_drrs) {
+ struct intel_panel *panel;
+
+ mutex_lock(&drrs->mutex);
+ /* DRRS Supported */
+ seq_puts(m, "\tDRRS Supported: Yes\n");
+
+ /* disable_drrs() will make drrs->dp NULL */
+ if (!drrs->dp) {
+ seq_puts(m, "Idleness DRRS: Disabled");
+ mutex_unlock(&drrs->mutex);
+ return;
+ }
+
+ panel = &drrs->dp->attached_connector->panel;
+ seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
+ drrs->busy_frontbuffer_bits);
+
+ seq_puts(m, "\n\t\t");
+ if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
+ seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
+ vrefresh = panel->fixed_mode->vrefresh;
+ } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
+ seq_puts(m, "DRRS_S
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Disable M2 frac division for integer case
On Tue, Mar 03, 2015 at 08:41:54PM +0530, Vijay Purushothaman wrote:
> v2 : Handle M2 frac division for both M2 frac and int cases
>
> v3 : Addressed Ville's review comments. Cleared the old bits for RMW
>
> Signed-off-by: Vijay Purushothaman
> ---
> drivers/gpu/drm/i915/i915_reg.h |1 +
> drivers/gpu/drm/i915/intel_display.c | 24 ++--
> 2 files changed, 19 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 55143cb..8200e98 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1029,6 +1029,7 @@ enum skl_disp_power_wells {
> #define DPIO_CHV_FIRST_MOD (0 << 8)
> #define DPIO_CHV_SECOND_MOD (1 << 8)
> #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
> +#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
> #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
>
> #define _CHV_PLL_DW6_CH0 0x8018
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 7298796..15904a8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6131,6 +6131,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> enum dpio_channel port = vlv_pipe_to_channel(pipe);
> u32 loopfilter, intcoeff;
> u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
> + u32 dpio_val;
> int refclk;
>
> bestn = pipe_config->dpll.n;
> @@ -6139,6 +6140,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> bestm2 = pipe_config->dpll.m2 >> 22;
> bestp1 = pipe_config->dpll.p1;
> bestp2 = pipe_config->dpll.p2;
> + dpio_val = 0;
>
> /*
>* Enable Refclk and SSC
> @@ -6163,13 +6165,23 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> DPIO_CHV_M1_DIV_BY_2 |
> 1 << DPIO_CHV_N_DIV_SHIFT);
>
> - /* M2 fraction division */
> - vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
> + if (bestm2_frac) {
> + /* M2 fraction division */
> + vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
>
> - /* M2 fraction division enable */
> - vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
> -DPIO_CHV_FRAC_DIV_EN |
> -(2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
> + /* M2 fraction division enable */
> + dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
> + dpio_val |= DPIO_CHV_FRAC_DIV_EN;
> + dpio_val &= ~DPIO_CHV_FEEDFWD_GAIN_MASK;
> + dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
> + vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
> +
> + } else {
> + /* M2 fraction division disable */
> + dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
> + dpio_val &= ~DPIO_CHV_FRAC_DIV_EN;
> + vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
You're not writing the feedfwd gain here. The register docs list it as
'Feedforwad gain for fractional mode/SSC mode PLL'. The SSC part there
makes me think these bits might mean something even if the fractional
divider is not used.
At least I don't see any harm in setting it even if the fractional
divider is not used. So with that in mind I'd probably write this as
something like:
val = read(PLL_DW3)
val &= ~(FRAC_DIV_EN | FEEDFWD_GAIN_MASK)
val |= 2 << FEEDFWD_GAIN_SHIFT;
if (bestm2_trac)
val |= FRAC_DIV_EN;
write(PLL_DW3, val);
This should also make it less likely we will accidentally update
only one of the branches in the future when both need changing.
> + }
>
> /* Loop filter */
> refclk = i9xx_get_refclk(crtc, 0);
> --
> 1.7.9.5
>
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use plane->state->fb in watermark code (v2)
On Tue, Mar 03, 2015 at 08:21:44AM -0300, Paulo Zanoni wrote:
> Hi
>
> 2015-02-27 15:12 GMT-03:00 Matt Roper :
> > plane->fb is a legacy pointer that not always be up-to-date (or updated
> > early enough). Make sure the watermark code uses plane->state->fb so
> > that we're always doing our calculations based on the correct
> > framebuffers.
>
> QA reported a regression caused by this patch: Kernel NULL pointer
> dereference.
>
> https://bugs.freedesktop.org/show_bug.cgi?id=89388
>
Yeah, I just saw this. I'll have to look more closely later today, but
I'm wondering whether I should have just done this replacement
driver-wide instead of restricted to just the watermark code. I suspect
killing off all of our uses of the old, legacy fields and using the new
atomic state values instead will make the driver more internally
consistent so we quit running into issues like this.
Matt
>
> >
> > This patch was generated by Coccinelle with the following semantic
> > patch:
> >
> > @@
> > struct drm_plane *P;
> > @@
> > - P->fb
> > + P->state->fb
> >
> > v2: Rebase
> >
> > Signed-off-by: Matt Roper
> > ---
> > drivers/gpu/drm/i915/intel_wm.c | 22 +++---
> > 1 file changed, 11 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_wm.c
> > b/drivers/gpu/drm/i915/intel_wm.c
> > index 47a5175..e877e02 100644
> > --- a/drivers/gpu/drm/i915/intel_wm.c
> > +++ b/drivers/gpu/drm/i915/intel_wm.c
> > @@ -496,7 +496,7 @@ static void pineview_update_wm(struct drm_crtc
> > *unused_crtc)
> > crtc = single_enabled_crtc(dev);
> > if (crtc) {
> > const struct drm_display_mode *adjusted_mode;
> > - int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
> > + int pixel_size = crtc->primary->state->fb->bits_per_pixel /
> > 8;
> > int clock;
> >
> > adjusted_mode =
> > &to_intel_crtc(crtc)->config->base.adjusted_mode;
> > @@ -572,7 +572,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
> > clock = adjusted_mode->crtc_clock;
> > htotal = adjusted_mode->crtc_htotal;
> > hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
> > - pixel_size = crtc->primary->fb->bits_per_pixel / 8;
> > + pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
> >
> > /* Use the small buffer method to calculate plane watermark */
> > entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
> > @@ -659,7 +659,7 @@ static bool g4x_compute_srwm(struct drm_device *dev,
> > clock = adjusted_mode->crtc_clock;
> > htotal = adjusted_mode->crtc_htotal;
> > hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
> > - pixel_size = crtc->primary->fb->bits_per_pixel / 8;
> > + pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
> >
> > line_time_us = max(htotal * 1000 / clock, 1);
> > line_count = (latency_ns / line_time_us + 1000) / 1000;
> > @@ -742,7 +742,7 @@ static void vlv_update_drain_latency(struct drm_crtc
> > *crtc)
> > }
> >
> > /* Primary plane Drain Latency */
> > - pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
> > + pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; /*
> > BPP */
> > if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
> > &drain_latency)) {
> > plane_prec = (prec_mult == high_precision) ?
> >DDL_PLANE_PRECISION_HIGH :
> > @@ -1023,7 +1023,7 @@ static void i965_update_wm(struct drm_crtc
> > *unused_crtc)
> > int clock = adjusted_mode->crtc_clock;
> > int htotal = adjusted_mode->crtc_htotal;
> > int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
> > - int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
> > + int pixel_size = crtc->primary->state->fb->bits_per_pixel /
> > 8;
> > unsigned long line_time_us;
> > int entries;
> >
> > @@ -1100,7 +1100,7 @@ static void i9xx_update_wm(struct drm_crtc
> > *unused_crtc)
> > crtc = intel_get_crtc_for_plane(dev, 0);
> > if (intel_crtc_active(crtc)) {
> > const struct drm_display_mode *adjusted_mode;
> > - int cpp = crtc->primary->fb->bits_per_pixel / 8;
> > + int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
> > if (IS_GEN2(dev))
> > cpp = 4;
> >
> > @@ -1122,7 +1122,7 @@ static void i9xx_update_wm(struct drm_crtc
> > *unused_crtc)
> > crtc = intel_get_crtc_for_plane(dev, 1);
> > if (intel_crtc_active(crtc)) {
> > const struct drm_display_mode *adjusted_mode;
> > - int cpp = crtc->primary->fb->bits_per_pixel / 8;
> > + int cpp = crtc->primary->state->fb->bits_per_pixel /
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Initialize CHV digital lock detect threshold
On Tue, Mar 03, 2015 at 08:43:12PM +0530, Vijay Purushothaman wrote:
> Initialize lock detect threshold and select coarse threshold for the
> case where M2 fraction division is disabled.
>
> v2: Split the changes into multiple smaller patches based on review by
> Ville
>
> v3: Addressed rest of the review comments. Clear out the old bits before
> we modify those bits as part of RMW
>
> Signed-off-by: Vijay Purushothaman
> ---
> drivers/gpu/drm/i915/i915_reg.h |1 +
> drivers/gpu/drm/i915/intel_display.c | 13 +
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8200e98..1a0f94e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1046,6 +1046,7 @@ enum skl_disp_power_wells {
> #define _CHV_PLL_DW9_CH0 0x8024
> #define _CHV_PLL_DW9_CH1 0x81A4
> #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
> +#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK(7 << 1)
> #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 :
> fine */
> #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 15904a8..a6b5786 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6176,11 +6176,24 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
> vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
>
> + /* Program digital lock detect threshold */
> + dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
> + dpio_val &= ~DPIO_CHV_INT_LOCK_THRESHOLD_MASK;
> + dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
Missing
dpio_val &= ~DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
here.
So I think to avoid such mistakes it's best to rewrite this too as:
val = read(PLL_DW9)
val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
val |= 0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT)
if (!bestm2_frac)
val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
write(PLL_DW9, val);
> + vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
> +
> } else {
> /* M2 fraction division disable */
> dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
> dpio_val &= ~DPIO_CHV_FRAC_DIV_EN;
> vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
> +
> + /* Program digital lock detect threshold */
> + dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
> + dpio_val &= ~DPIO_CHV_INT_LOCK_THRESHOLD_MASK;
> + dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
> + dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
> + vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
> }
>
> /* Loop filter */
> --
> 1.7.9.5
>
> ___
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Update prop, int co-eff and gain threshold for CHV
On Tue, Mar 03, 2015 at 08:44:04PM +0530, Vijay Purushothaman wrote:
> This patch implements latest PHY changes in Gain, prop and int co-efficients
> based on the vco freq.
>
> v2: Split the original changes into multiple smaller patches based on
> review by Ville
>
> v3: Addressed Ville's review comments. Fixed the error introduced in v2.
> Clear the old bits before we modify those bits as part of RMW.
>
> Signed-off-by: Vijay Purushothaman
> ---
> drivers/gpu/drm/i915/i915_reg.h |2 ++
> drivers/gpu/drm/i915/intel_display.c | 43
> --
> 2 files changed, 33 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1a0f94e..5000184 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1041,6 +1041,8 @@ enum skl_disp_power_wells {
>
> #define _CHV_PLL_DW8_CH0 0x8020
> #define _CHV_PLL_DW8_CH1 0x81A0
> +#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
> +#define DPIO_CHV_TDC_TARGET_CNT_MASK (0xFF << 0)
This mask should be 10 bits AFAICS.
> #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
>
> #define _CHV_PLL_DW9_CH0 0x8024
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index a6b5786..4e08a14 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6129,10 +6129,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> int pipe = crtc->pipe;
> int dpll_reg = DPLL(crtc->pipe);
> enum dpio_channel port = vlv_pipe_to_channel(pipe);
> - u32 loopfilter, intcoeff;
> + u32 loopfilter, tribuf_calcntr;
> u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
> u32 dpio_val;
> - int refclk;
> + int vco;
>
> bestn = pipe_config->dpll.n;
> bestm2_frac = pipe_config->dpll.m2 & 0x3f;
> @@ -6140,7 +6140,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> bestm2 = pipe_config->dpll.m2 >> 22;
> bestp1 = pipe_config->dpll.p1;
> bestp2 = pipe_config->dpll.p2;
> + vco = pipe_config->dpll.vco;
> dpio_val = 0;
> + loopfilter = 0;
>
> /*
>* Enable Refclk and SSC
> @@ -6197,18 +6199,35 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> }
>
> /* Loop filter */
> - refclk = i9xx_get_refclk(crtc, 0);
> - loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
> - 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
> - if (refclk == 10)
> - intcoeff = 11;
> - else if (refclk == 38400)
> - intcoeff = 10;
> - else
> - intcoeff = 9;
> - loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
> + if (vco == 540) {
> + loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
> + loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
> + loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
> + tribuf_calcntr = 9;
Nit: inconsistent use of hex vs. decimal values for tribuf_calcntr.
> + } else if (vco <= 620) {
> + loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
> + loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
> + loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> + tribuf_calcntr = 0x9;
> + } else if (vco <= 648) {
> + loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
> + loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
> + loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> + tribuf_calcntr = 0x8;
> + } else {
> + /* Not supported. Apply the same limits as in the max case */
> + loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
> + loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
> + loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> + tribuf_calcntr = 0;
> + }
> vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
>
> + dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
> + dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
> + dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
> + vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
> +
> /* AFC Recal */
> vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
> vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
> --
> 1.7.9.5
>
> ___
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Re: [Intel-gfx] [PATCH i-g-t 02/13] lib: Extract igt_buf_write_to_png() from gem_render_copy
On 03/03/2015 02:10 PM, Tvrtko Ursulin wrote: From: Damien Lespiau Now that the Android build has cairo, we can put cairo-dependant code back into lib/ Looks like we'll have to drop this one - Cairo is not available in Android after all. I looked at the following patches and couldn't see anything actually needing this so dropping looks safe. Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t 02/13] lib: Extract igt_buf_write_to_png() from gem_render_copy
> -Original Message- > From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com] > Sent: Tuesday, March 03, 2015 4:04 PM > To: Intel-gfx@lists.freedesktop.org; Lespiau, Damien > Cc: Ceraolo Spurio, Daniele; Gore, Tim > Subject: Re: [Intel-gfx] [PATCH i-g-t 02/13] lib: Extract > igt_buf_write_to_png() from gem_render_copy > > > On 03/03/2015 02:10 PM, Tvrtko Ursulin wrote: > > From: Damien Lespiau > > > > Now that the Android build has cairo, we can put cairo-dependant code > > back into lib/ > > Looks like we'll have to drop this one - Cairo is not available in Android > after > all. > > I looked at the following patches and couldn't see anything actually needing > this so dropping looks safe. > > Tvrtko IF you want to move cairo dependent code into the igt library you can put it in igt_fb.c, since this is excluded in Android builds unless the ANDROID_HAS_CAIRO env var is set. (igt_kms is likewise excluded in this case) Tim ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Setup all page directories for gen8
On Tue, Mar 03, 2015 at 05:03:29PM +0200, Mika Kuoppala wrote:
> If the mappable size is less than what the full range
> of pdps can address, we end up setting pdps for only the
> mappable area.
mappable is not a factor here. The global gtt is 2GiB and we just used
the same size for the ppgtt, which made sense for aliasing ppgtt I
suppose.
>
> The logical context however needs valid pdp entries.
> Prior to commit 06fda602dbca ("drm/i915: Create page table allocators")
> we just have been writing pdp entries with dma address of zero instead
> of valid pdps. This is supposedly bad even if those pdps are not
> addressed.
>
> As commit 06fda602dbca ("drm/i915: Create page table allocators")
> introduced more dynamic structure for pdps, we ended up oopsing
> when we populated the lrc context. Analyzing this oops revealed
> the fact that we have not been writing valid pdps with bsw, as
> it is doing the ppgtt init with 2gb limit.
>
> We should do the right thing and setup the non addressable part
> pdps/pde/pte to scratch page through the minimal structure by
> having just pdp with pde entries pointing to same page with
> pte entries pointing to scratch page.
>
> But instead of going through that trouble, setup all the pdps
> through individual pd pages and pt entries, even for non
> addressable parts. This way we populate the lrc with valid
> pdps and gives us a base for dynamic page allocation to
> introduce code that truncates the page table structure.
This means using an extra 4+MiB of kernel memroy per address space. But
I guess the dynamic page table stuff is coming along so it'll get sorted
out eventually.
But this won't actually prevent the GPU from faulting for >=2GiB
addresses since we leave the extra PTEs zeroed (ie. valid=0). We'd
need to extend the initial .clear_range() to make sure all the new
PTEs point to the scratch page. If we go to the trouble of allocating
the page tables I think we might as well set them up fully.
Previously when we just left the PDPs zeroed the GPU might or might not
fault depending on what kind of data was in the page at bus address 0.
I've occasionally wondered why the hardware designers didn't use the the
normal PTE/PDE encoding for the PDP registers so that you could have a
valid bit already at the top level.
>
> The regression of oopsing in init was introduced by
> commit 06fda602dbca ("drm/i915: Create page table allocators")
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89350
> Tested-by: Valtteri Rantala
> Cc: Michel Thierry
> Cc: Ben Widawsky
> Cc: Ville Syrjälä
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index bd95776..848a821 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -709,7 +709,7 @@ static int gen8_ppgtt_setup_page_tables(struct
> i915_hw_ppgtt *ppgtt,
> */
> static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
> {
> - const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
> + const int max_pdp = GEN8_LEGACY_PDPES;
> const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
> int i, j, ret;
>
> --
> 1.9.1
--
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[Intel-gfx] [PATCH] drm/i915: Fix modeset state confusion in the load detect code
This is a tricky story of the new atomic state handling and the legacy code fighting over each another. The bug at hand is an underrun of the framebuffer reference with subsequent hilarity caused by the load detect code. Which is peculiar since the the exact same code works fine as the implementation of the legacy setcrtc ioctl. Let's look at the ingredients: - Currently our code is a crazy mix of legacy modeset interfaces to set the parameters and half-baked atomic state tracking underneath. While this transition is going we're using the transitional plane helpers to update the atomic side (drm_plane_helper_disable/update and friends), i.e. plane->state->fb. Since the state structure owns the fb those functions take care of that themselves. The legacy state (specifically crtc->primary->fb) is still managed by the old code (and mostly by the drm core), with the fb reference counting done by callers (core drm for the ioctl or the i915 load detect code). The relevant commit is commit ea2c67bb4affa84080c616920f3899f123786e56 Author: Matt Roper Date: Tue Dec 23 10:41:52 2014 -0800 drm/i915: Move to atomic plane helpers (v9) - drm_plane_helper_disable has special code to handle multiple calls in a row - it checks plane->crtc == NULL and bails out. This is to match the proper atomic implementation which needs the crtc to get at the implied locking context atomic updates always need. See commit acf24a395c5a9290189b080383564437101d411c Author: Daniel Vetter Date: Tue Jul 29 15:33:05 2014 +0200 drm/plane-helper: transitional atomic plane helpers - The universal plane code split out the implicit primary plane from the CRTC into it's own full-blown drm_plane object. As part of that the setcrtc ioctl (which updated both the crtc mode and primary plane) learned to set crtc->primary->crtc on modeset to make sure the plane->crtc assignments statate up to date in commit e13161af80c185ecd8dc4641d0f5df58f9e3e0af Author: Matt Roper Date: Tue Apr 1 15:22:38 2014 -0700 drm: Add drm_crtc_init_with_planes() (v2) Unfortunately we've forgotten to update the load detect code. Which wasn't a problem since the load detect modeset is temporary and always undone before we drop the locks. - Finally there is a organically grown history (i.e. don't ask) around who sets the legacy plane->fb for the various driver entry points. Originally updating that was the drivers duty, but for almost all places we've moved that (plus updating the refcounts) into the core. Again the exception is the load detect code. Taking all together the following happens: - The load detect code doesn't set crtc->primary->crtc. This is only really an issue on crtcs never before used or when userspace explicitly disabled the primary plane. - The plane helper glue code short-circuits because of that and leaves a non-NULL fb behind in plane->state->fb and plane->fb. The state fb isn't a real problem (it's properly refcounted on its own), it's just the canary. - Load detect code drops the reference for that fb, but doesn't set plane->fb = NULL. This is ok since it's still living in that old world where drivers had to clear the pointer but the core/callers handled the refcounting. - On the next modeset the drm core notices plane->fb and takes care of refcounting it properly by doing another unref. This drops the refcount to zero, leaving state->plane now pointing at freed memory. - intel_plane_duplicate_state still assume it owns a reference to that very state->fb and bad things start to happen. Fix this all by applying the same duct-tape as for the legacy setcrtc ioctl code and set crtc->primary->crtc properly. Cc: Matt Roper Cc: Linus Torvalds Cc: Paul Bolle Cc: Rob Clark Cc: Paulo Zanoni Cc: Sean Paul Cc: Matt Roper Reported-by: Linus Torvalds Reported-by: Paul Bolle Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index cc3305e30c1b..d116caf98a72 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8859,6 +8859,7 @@ retry: old->release_fb->funcs->destroy(old->release_fb); goto fail; } + crtc->primary->crtc = crtc; /* let the connector get through one full cycle before testing */ intel_wait_for_vblank(dev, intel_crtc->pipe); -- 2.1.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/12] drm/i915/bdw: Add 4 level support in insert_entries and clear_range
On Fri, Feb 20, 2015 at 11:16 PM, Michel Thierry
wrote:
> When 48b is enabled, gen8_ppgtt_insert_entries needs to read the Page Map
> Level 4 (PML4), before it selects which Page Directory Pointer (PDP)
> it will write to.
>
> Similarly, gen8_ppgtt_clear_range needs to get the correct PDP/PD range.
>
> Also add a scratch page for PML4.
>
> This patch was inspired by Ben's "Depend exclusively on map and
> unmap_vma".
>
> Signed-off-by: Michel Thierry
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 66
> ++---
> drivers/gpu/drm/i915/i915_gem_gtt.h | 12 +++
> 2 files changed, 67 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index a1396cb..0954827 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -676,24 +676,52 @@ static void gen8_ppgtt_clear_pte_range(struct
> i915_page_directory_pointer_entry
> }
> }
>
> +static void gen8_ppgtt_clear_range_4lvl(struct i915_hw_ppgtt *ppgtt,
> + gen8_gtt_pte_t scratch_pte,
> + uint64_t start,
> + uint64_t length)
> +{
> + struct i915_page_directory_pointer_entry *pdp;
> + uint64_t templ4, templ3, pml4e, pdpe;
> +
> + gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
> + struct i915_page_directory_entry *pd;
> + uint64_t pdp_len = gen8_clamp_pdp(start, length);
> + uint64_t pdp_start = start;
> +
> + gen8_for_each_pdpe(pd, pdp, pdp_start, pdp_len, templ3, pdpe)
> {
The 'gen8_ppgtt_clear_pte_range' function is equipped to switch to a
new page directory appropriately.
So having just an outer loop of pml4 entries should suffice, with the
use of gen8_clamp_pdp.
The inner loop 'gen8_for_each_pdpe' is not really needed.
> + uint64_t pd_len = gen8_clamp_pd(pdp_start, pdp_len);
> + uint64_t pd_start = pdp_start;
> +
> + gen8_ppgtt_clear_pte_range(pdp, pd_start, pd_len,
> + scratch_pte,
> !HAS_LLC(ppgtt->base.dev));
> + }
> + }
> +}
> +
> static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
> - uint64_t start,
> - uint64_t length,
> + uint64_t start, uint64_t length,
>bool use_scratch)
> {
> struct i915_hw_ppgtt *ppgtt =
> - container_of(vm, struct i915_hw_ppgtt, base);
> - struct i915_page_directory_pointer_entry *pdp = &ppgtt->pdp; /*
> FIXME: 48b */
> -
> + container_of(vm, struct i915_hw_ppgtt, base);
> gen8_gtt_pte_t scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
> I915_CACHE_LLC,
> use_scratch);
>
> - gen8_ppgtt_clear_pte_range(pdp, start, length, scratch_pte,
> !HAS_LLC(vm->dev));
> + if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
> + struct i915_page_directory_pointer_entry *pdp = &ppgtt->pdp;
> +
> + gen8_ppgtt_clear_pte_range(pdp, start, length, scratch_pte,
> + !HAS_LLC(ppgtt->base.dev));
> + } else {
> + gen8_ppgtt_clear_range_4lvl(ppgtt, scratch_pte, start,
> length);
> + }
> }
>
> static void gen8_ppgtt_insert_pte_entries(struct
> i915_page_directory_pointer_entry *pdp,
> struct sg_page_iter *sg_iter,
> uint64_t start,
> + size_t pages,
> enum i915_cache_level cache_level,
> const bool flush)
> {
> @@ -704,7 +732,7 @@ static void gen8_ppgtt_insert_pte_entries(struct
> i915_page_directory_pointer_ent
>
> pt_vaddr = NULL;
>
> - while (__sg_page_iter_next(sg_iter)) {
> + while (pages-- && __sg_page_iter_next(sg_iter)) {
> if (pt_vaddr == NULL) {
> struct i915_page_directory_entry *pd =
> pdp->page_directory[pdpe];
> struct i915_page_table_entry *pt =
> pd->page_tables[pde];
> @@ -742,11 +770,26 @@ static void gen8_ppgtt_insert_entries(struct
> i915_address_space *vm,
> u32 unused)
> {
> struct i915_hw_ppgtt *ppgtt = container_of(vm, struct i915_hw_ppgtt,
> base);
> - struct i915_page_directory_pointer_entry *pdp = &ppgtt->pdp; /*
> FIXME: 48b */
> + struct i915_page_directory_pointer_entry *pdp;
> struct sg_page_iter sg_iter;
>
> __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
> - gen8_ppgtt_i
Re: [Intel-gfx] [PATCH 11/12] drm/i915: Expand error state's address width to 64b
On Fri, Feb 20, 2015 at 11:16 PM, Michel Thierry
wrote:
> From: Ben Widawsky
>
> v2: 0 pad the new 8B fields or else intel_error_decode has a hard time.
> Note, regardless we need an igt update.
>
> v3: Make reloc_offset 64b also.
>
> Signed-off-by: Ben Widawsky
> Signed-off-by: Michel Thierry
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> drivers/gpu/drm/i915/i915_gpu_error.c | 17 +
> 2 files changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index af0d149..056ced5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -459,7 +459,7 @@ struct drm_i915_error_state {
>
> struct drm_i915_error_object {
> int page_count;
> - u32 gtt_offset;
> + u64 gtt_offset;
> u32 *pages[0];
> } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
>
> @@ -485,7 +485,7 @@ struct drm_i915_error_state {
> u32 size;
> u32 name;
> u32 rseqno, wseqno;
> - u32 gtt_offset;
> + u64 gtt_offset;
> u32 read_domains;
> u32 write_domain;
> s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index a982849..bbf25d0 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -195,7 +195,7 @@ static void print_error_buffers(struct
> drm_i915_error_state_buf *m,
> err_printf(m, " %s [%d]:\n", name, count);
>
> while (count--) {
> - err_printf(m, "%08x %8u %02x %02x %x %x",
> + err_printf(m, "%016llx %8u %02x %02x %x %x",
>err->gtt_offset,
>err->size,
>err->read_domains,
> @@ -415,7 +415,7 @@ int i915_error_state_to_str(struct
> drm_i915_error_state_buf *m,
> err_printf(m, " (submitted by %s [%d])",
>error->ring[i].comm,
>error->ring[i].pid);
> - err_printf(m, " --- gtt_offset = 0x%08x\n",
> + err_printf(m, " --- gtt_offset = 0x%016llx\n",
>obj->gtt_offset);
> print_error_obj(m, obj);
> }
> @@ -423,7 +423,8 @@ int i915_error_state_to_str(struct
> drm_i915_error_state_buf *m,
> obj = error->ring[i].wa_batchbuffer;
> if (obj) {
> err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
> - dev_priv->ring[i].name, obj->gtt_offset);
> + dev_priv->ring[i].name,
> + lower_32_bits(obj->gtt_offset));
> print_error_obj(m, obj);
> }
>
> @@ -442,14 +443,14 @@ int i915_error_state_to_str(struct
> drm_i915_error_state_buf *m,
> if ((obj = error->ring[i].ringbuffer)) {
> err_printf(m, "%s --- ringbuffer = 0x%08x\n",
>dev_priv->ring[i].name,
> - obj->gtt_offset);
> + lower_32_bits(obj->gtt_offset));
> print_error_obj(m, obj);
> }
>
> if ((obj = error->ring[i].hws_page)) {
> err_printf(m, "%s --- HW Status = 0x%08x\n",
>dev_priv->ring[i].name,
> - obj->gtt_offset);
> + lower_32_bits(obj->gtt_offset));
> offset = 0;
> for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
> err_printf(m, "[%04x] %08x %08x %08x %08x\n",
> @@ -465,13 +466,13 @@ int i915_error_state_to_str(struct
> drm_i915_error_state_buf *m,
> if ((obj = error->ring[i].ctx)) {
> err_printf(m, "%s --- HW Context = 0x%08x\n",
>dev_priv->ring[i].name,
> - obj->gtt_offset);
> + lower_32_bits(obj->gtt_offset));
> print_error_obj(m, obj);
> }
> }
>
> if ((obj = error->semaphore_obj)) {
> - err_printf(m, "Semaphore page = 0x%08x\n", obj->gtt_offset);
> + err_printf(m, "Semaphore page = 0x%016llx\n",
> obj->gtt_offset);
Can the 'lower_32_bits' be used for the semaphore object also.
Its mapped into GGTT during render ring init time, so may never have
an offset of > 4 GB.
> for (elt = 0; elt <
Re: [Intel-gfx] [PATCH] Revert "drm/i915: Switch planes from transitional helpers to full atomic helpers"
On Mon, Mar 02, 2015 at 04:35:20PM +0100, Daniel Vetter wrote:
> This reverts commit 3f678c96abb43a977d2ea41aefccdc49e8a3e896.
>
> We've been a bit too optimistic with this one here :(
>
> The trouble is that internally we're still using these plane
> update/disable hooks. Which was totally ok pre-atomic since the drm
> core did all the book-keeping updating and these just mostly updated
> hw state. But with atomic there's lots more going on, and it causes
> heaps of trouble with the load detect code.
>
> This one specifically cause a deadlock since both the load detect code
> and the nested plane atomic helper functions tried to grab the same
> locks. It only blows up because of the evil tricks though we play with
> the implicit ww acquire context.
>
> Applying this revert unearths the NULL deref on already freed
> framebuffer objects reported as a regression in 4.0 by various people.
>
> Fixing this will be fairly invasive, hence revert even for the
> 4.1-next queue.
>
> Cc: Matt Roper
> Cc: Linus Torvalds
> Cc: Paul Bolle
> Signed-off-by: Daniel Vetter
Queued for -next with Matt's ack.
-Daniel
> ---
> Just to make it really clear: This is 4.1-next material. It's simply
> the explanation for why we didn't notice the oops ourselves. The 4.0
> oops itself looks like some glue lacking in the load detect code,
> still working on that one.
> -Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 3156d77b2215..cc3305e30c1b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12179,8 +12179,8 @@ void intel_plane_destroy(struct drm_plane *plane)
> }
>
> const struct drm_plane_funcs intel_plane_funcs = {
> - .update_plane = drm_atomic_helper_update_plane,
> - .disable_plane = drm_atomic_helper_disable_plane,
> + .update_plane = drm_plane_helper_update,
> + .disable_plane = drm_plane_helper_disable,
> .destroy = intel_plane_destroy,
> .set_property = drm_atomic_helper_plane_set_property,
> .atomic_get_property = intel_plane_atomic_get_property,
> --
> 1.8.4.rc3
>
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] i915 driver doesn't find all Modelines that nouveau driver finds
On Tue, 2015-03-03 at 15:31 +0200, Ville Syrjälä wrote: > > I suppose any increase is good. But personally I just couldn't stand > anything below 75Hz when I was still using a CRT. Yeah. 75Hz is what I was using with the nVidia card I replaced with this new motherboard and Celeron G1840. Slightly off on a tangent... do LCD screens driven through the DSUB have the same flicker issues as CRTs or does that somehow get washed out by the difference between LCD and CRT technology? Just thinking about when I do replace this CRT with an LCD or LED if I eventually will be wanting a new (or the old nVidia that I was using) video card to get that analog refresh rate up. Although I suppose if I get a second digital monitor and a new video card, they could both just be DVI/HDMI. Cheers, b. signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Add module param to test the load detect code
This is useful for writing igts to make sure we don't break this,
without being forced to own a one of these dinosaurs.
Suggested-by: Jesse Barnes
Cc: Matt Roper
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/i915_params.c | 8 +++-
drivers/gpu/drm/i915/intel_crt.c | 6 --
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e07a1cb5db67..878b16ed61b3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2429,6 +2429,7 @@ struct i915_params {
bool enable_hangcheck;
bool fastboot;
bool prefault_disable;
+ bool load_detect_test;
bool reset;
bool disable_display;
bool disable_vtd_wa;
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 44f2262a5553..9f7f9a644c45 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -44,6 +44,7 @@ struct i915_params i915 __read_mostly = {
.enable_ips = 1,
.fastboot = 0,
.prefault_disable = 0,
+ .load_detect_test = 0,
.reset = true,
.invert_brightness = 0,
.disable_display = 0,
@@ -144,11 +145,16 @@ module_param_named(fastboot, i915.fastboot, bool, 0600);
MODULE_PARM_DESC(fastboot,
"Try to skip unnecessary mode sets at boot time (default: false)");
-module_param_named(prefault_disable, i915.prefault_disable, bool, 0600);
+module_param_named_unsafe(prefault_disable, i915.prefault_disable, bool, 0600);
MODULE_PARM_DESC(prefault_disable,
"Disable page prefaulting for pread/pwrite/reloc (default:false). "
"For developers only.");
+module_param_named_unsafe(load_detect_test, i915.load_detect_test, bool, 0600);
+MODULE_PARM_DESC(load_detect_test,
+ "Force-enable the VGA load detect code for testing (default:false). "
+ "For developers only.");
+
module_param_named(invert_brightness, i915.invert_brightness, int, 0600);
MODULE_PARM_DESC(invert_brightness,
"Invert backlight brightness "
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index e66e17af0a56..b3421ac0be57 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -690,7 +690,7 @@ intel_crt_detect(struct drm_connector *connector, bool
force)
* broken monitor (without edid) to work behind a broken kvm (that fails
* to have the right resistors for HP detection) needs to fix this up.
* For now just bail out. */
- if (I915_HAS_HOTPLUG(dev)) {
+ if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) {
status = connector_status_disconnected;
goto out;
}
@@ -706,8 +706,10 @@ intel_crt_detect(struct drm_connector *connector, bool
force)
if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) {
if (intel_crt_detect_ddc(connector))
status = connector_status_connected;
- else
+ else if (INTEL_INFO(dev)->gen < 4)
status = intel_crt_load_detect(crt);
+ else
+ status = connector_status_unknown;
intel_release_load_detect_pipe(connector, &tmp);
} else
status = connector_status_unknown;
--
2.1.4
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