Re: [Intel-gfx] [PATCH] drm/i915: Don't do posting reads on getting forcewake
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5675 -Summary- Platform Delta drm-intel-nightly Series Applied PNV -1 353/353 352/353 ILK 200/200 200/200 SNB 400/422 400/422 IVB +1 485/487 486/487 BYT 296/296 296/296 HSW +1-2 507/508 506/508 BDW 401/402 401/402 -Detailed- Platform Testdrm-intel-nightly Series Applied *PNV igt_gen3_render_linear_blits PASS(4, M25M23) CRASH(1, M23) IVB igt_gem_storedw_batches_loop_normal DMESG_WARN(5, M34M4)PASS(15, M34M4M21) PASS(1, M21) *HSW igt_gem_pwrite_pread_snooped-copy-performance PASS(2, M40) DMESG_WARN(1, M40) HSW igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance DMESG_WARN(1, M40)PASS(18, M40M20) PASS(1, M40) *HSW igt_gem_storedw_loop_blt PASS(2, M40) DMESG_WARN(1, M40) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] drm/i915: Enable asynchronous nuclear flips
On Fri, Jan 30, 2015 at 04:22:38PM -0800, Matt Roper wrote:
> The initial i915 nuclear pageflip support rejected asynchronous updates.
> Allow all work after we swap in the new state structures to run
> asynchronously. We also need to start sending completion events to
> userspace if they were requested.
>
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> drivers/gpu/drm/i915/intel_atomic.c | 162
> +++-
> drivers/gpu/drm/i915/intel_drv.h| 8 ++
> 3 files changed, 150 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8fad702..c7a520a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1777,6 +1777,9 @@ struct drm_i915_private {
> struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
> wait_queue_head_t pending_flip_queue;
>
> + /* CRTC mask of pending atomic flips */
> + uint32_t pending_atomic;
> +
> #ifdef CONFIG_DEBUG_FS
> struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c
> b/drivers/gpu/drm/i915/intel_atomic.c
> index 19a9dd5..5dd7897 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -76,6 +76,8 @@ int intel_atomic_check(struct drm_device *dev,
> state->allow_modeset = false;
> for (i = 0; i < ncrtcs; i++) {
> struct intel_crtc *crtc = to_intel_crtc(state->crtcs[i]);
> + if (crtc)
> + state->crtc_states[i]->enable = crtc->active;
> if (crtc && crtc->pipe != nuclear_pipe)
> not_nuclear = true;
> }
> @@ -96,6 +98,87 @@ int intel_atomic_check(struct drm_device *dev,
> }
>
>
> +/*
> + * Wait until CRTC's have no pending flip, then atomically mark those CRTC's
> + * as busy.
> + */
> +static int wait_for_pending_flip(uint32_t crtc_mask,
> + struct intel_pending_atomic *commit)
> +{
> + struct drm_i915_private *dev_priv = commit->dev->dev_private;
> + int ret;
> +
> + spin_lock_irq(&dev_priv->pending_flip_queue.lock);
> + ret = wait_event_interruptible_locked(dev_priv->pending_flip_queue,
> + !(dev_priv->pending_atomic &
> crtc_mask));
> + if (ret == 0)
> + dev_priv->pending_atomic |= crtc_mask;
> + spin_unlock_irq(&dev_priv->pending_flip_queue.lock);
> +
> + return ret;
> +}
> +
> +/* Finish pending flip operation on specified CRTC's */
> +static void flip_completion(struct intel_pending_atomic *commit)
> +{
> + struct drm_i915_private *dev_priv = commit->dev->dev_private;
> +
> + spin_lock_irq(&dev_priv->pending_flip_queue.lock);
> + dev_priv->pending_atomic &= ~commit->crtc_mask;
> + wake_up_all_locked(&dev_priv->pending_flip_queue);
> + spin_unlock_irq(&dev_priv->pending_flip_queue.lock);
> +}
> +
> +/*
> + * Finish an atomic commit. The work here can be performed asynchronously
> + * if desired. The new state has already been applied to the DRM objects
> + * and no modeset locks are needed.
> + */
> +static void finish_atomic_commit(struct work_struct *work)
> +{
> + struct intel_pending_atomic *commit =
> + container_of(work, struct intel_pending_atomic, work);
> + struct drm_device *dev = commit->dev;
> + struct drm_crtc *crtc;
> + struct drm_atomic_state *state = commit->state;
> + int i;
> +
> + /*
> + * FIXME: The proper sequence here will eventually be:
> + *
> + * drm_atomic_helper_commit_pre_planes(dev, state);
> + * drm_atomic_helper_commit_planes(dev, state);
> + * drm_atomic_helper_commit_post_planes(dev, state);
> + * drm_atomic_helper_wait_for_vblanks(dev, state);
> + * drm_atomic_helper_cleanup_planes(dev, state);
> + * drm_atomic_state_free(state);
> + *
> + * once we have full atomic modeset. For now, just manually update
> + * plane states to avoid clobbering good states with dummy states
> + * while nuclear pageflipping.
> + */
> + drm_atomic_helper_commit_planes(dev, state);
> + drm_atomic_helper_wait_for_vblanks(dev, state);
> +
> + /* Send CRTC completion events. */
> + for (i = 0; i < dev->mode_config.num_crtc; i++) {
> + crtc = state->crtcs[i];
> + if (crtc && crtc->state->event) {
> + spin_lock_irq(&dev->event_lock);
> + drm_send_vblank_event(dev, to_intel_crtc(crtc)->pipe,
> + crtc->state->event);
> + spin_unlock_irq(&dev->event_lock);
> + crtc->state->event = NULL;
> + }
> + }
> +
> + drm_atomic_helper_cleanup_planes(dev, state);
> + drm_atomic_state_free(state);
> +
> + flip_completion(commit);
> + kfree(commit);
> +}
> +
> /*
Re: [Intel-gfx] [PATCH 0/4] More nuclear pageflip
On Fri, Jan 30, 2015 at 04:22:35PM -0800, Matt Roper wrote: > The first two patches here were already posted earlier this week; they allow > our legacy plane updates to make use of the main atomic helpers rather than > the > transitional atomic helpers. This shouldn't have any functional change, but > it > will cause us to exercise the full atomic pipeline rather than just the plane > subset of it. > > The third patch is the interesting one; it allows us to handle nuclear > pageflip > requests in a non-blocking manner and deliver a uevent upon completion. This > is important functionality for compositors since it allows them to request > that > the kernel perform a flip, then continue on doing other work while they wait > for the flip to actually happen. > > The final patch here switches our legacy pageflip ioctl to use the atomic > helper (thus exercising the new asynchronous support added in patch #3). > Removing the i915-specific pageflip handling should allow us to drop a bunch > of > our display code; I've been somewhat conservative in my code removal for now > (just enough to get rid of the 'function unused' compiler warnings); we can do > further cleanup of code that relates to the legacy pageflip pipeline in a > future patchset. Our current mmio flip doesn't work on gen4 and earlier because the flip completion event generation only works with MI_ flips. So I think we need to (at least for now) keep the legacy flip code around and wired up for those platforms. But we need to redo the flip completion anyway (and probably just key off the next vblank interrupt) since if you'd do an atomic flip with just sprites the event stuff wont work on any platform. Once we have that we can then also roll out the legacy-pageflip-on-atomic for older platforms. -Daniel > > Matt Roper (4): > drm/i915: Keep plane->state updated on pageflip > drm/i915: Switch planes from transitional helpers to full atomic > helpers > drm/i915: Enable asynchronous nuclear flips > drm/i915: Use atomic helper for pageflips > > drivers/gpu/drm/i915/i915_drv.h | 9 +- > drivers/gpu/drm/i915/i915_params.c | 5 - > drivers/gpu/drm/i915/intel_atomic.c | 162 ++-- > drivers/gpu/drm/i915/intel_display.c | 716 > +-- > drivers/gpu/drm/i915/intel_drv.h | 8 + > drivers/gpu/drm/i915/intel_lrc.c | 3 +- > 6 files changed, 155 insertions(+), 748 deletions(-) > > -- > 1.8.5.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/i915: Keep plane->state updated on pageflip
On Fri, Jan 30, 2015 at 04:22:36PM -0800, Matt Roper wrote: > Until all drivers have transitioned to atomic, the framebuffer > associated with a plane is tracked in both plane->fb (for legacy) and > plane->state->fb (for all the new atomic codeflow). All of our modeset > and plane updates use drm_plane->update_plane(), so in theory plane->fb > and plane->state->fb should always stay in sync and point at the same > thing for i915. However we forgot about the pageflip ioctl case, which > currently only updates plane->fb and leaves plane->state->fb at a stale > value. > > Surprisingly, this doesn't cause any real problems at the moment since > internally we use the plane->fb pointer in most of the places that > matter, and on the next .update_plane() call, we use plane->fb to figure > out which framebuffer to cleanup. However when we switch to the full > atomic helpers for update_plane()/disable_plane(), those helpers use > plane->state->fb to figure out which framebuffer to cleanup, so not > having updated the plane->state->fb pointer causes things to blow up > following a pageflip ioctl. > > The fix here is to just make sure we update plane->state->fb at the same > time we update plane->fb in the pageflip ioctl. > > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/i915/intel_display.c | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 3d220a6..08e2bab 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -9801,6 +9801,13 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, > > crtc->primary->fb = fb; > > + /* Keep state structure in sync */ > + if (crtc->primary->state->fb) > + drm_framebuffer_unreference(crtc->primary->state->fb); > + crtc->primary->state->fb = fb; > + if (crtc->primary->state->fb) > + drm_framebuffer_reference(crtc->primary->state->fb); Yeah, I had the same fixup in my own testconversion. So merged this and the 2nd patch to dinq (for 3.21). Thanks, Daniel > + > work->pending_flip_obj = obj; > > atomic_inc(&intel_crtc->unpin_work_count); > -- > 1.8.5.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [Intel HD 4400] strongly irritating artefacts on 2560x1440 laptop display
On 01/29/2015 10:47 PM, Martin Wilck wrote:> PS: I have just done a > thing I thought I'd never do - I am downloading > an evaluation copy of Windows in order to check whether my HW is faulty. Just did that - the problem occurs on Windows, too. So this was a case of a broken display. I am sorry for having bothered, and would like to thank Chris and Jani for replying. Martin ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [Intel HD 4400] strongly irritating artefacts on 2560x1440 laptop display
On Sat, 31 Jan 2015, Martin Wilck wrote: > On 01/29/2015 10:47 PM, Martin Wilck wrote:> PS: I have just done a >> thing I thought I'd never do - I am downloading >> an evaluation copy of Windows in order to check whether my HW is faulty. > > Just did that - the problem occurs on Windows, too. So this was a case > of a broken display. > > I am sorry for having bothered, and would like to thank Chris and Jani > for replying. No problem, thanks for following up with this. Sorry to hear about the display. BR, Jani. -- Jani Nikula, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915/skl: Remove the check enforcing VCS2 to be gen8 only
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5682 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 353/353 353/353 ILK 353/353 353/353 SNB 400/422 400/422 IVB +1-2 485/487 484/487 BYT 296/296 296/296 HSW +1-1 507/508 507/508 BDW -2 401/402 399/402 -Detailed- Platform Testdrm-intel-nightly Series Applied *IVB igt_gem_evict_everything_minor-normal PASS(2, M34) DMESG_WARN(1, M34) IVB igt_gem_storedw_batches_loop_normal DMESG_WARN(5, M34M4)PASS(15, M34M4M21) PASS(1, M34) IVB igt_gem_storedw_batches_loop_secure-dispatch DMESG_WARN(1, M34)PASS(6, M34M4) DMESG_WARN(1, M34) HSW igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance DMESG_WARN(1, M40)PASS(18, M40M20) PASS(1, M20) HSW igt_gem_storedw_loop_vebox DMESG_WARN(2, M20)PASS(3, M40M20) DMESG_WARN(1, M20) BDW igt_gem_pwrite_pread_display-pwrite-blt-gtt_mmap-performance DMESG_WARN(4, M28)PASS(2, M30) DMESG_WARN(1, M28) *BDW igt_gem_pwrite_pread_uncached-pwrite-blt-gtt_mmap-performance PASS(6, M30M28) DMESG_WARN(1, M28) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [Intel HD 4400] strongly irritating artefacts on 2560x1440 laptop display
Am 31. Januar 2015 16:36:47 MEZ, schrieb Jani Nikula : >> I am sorry for having bothered, and would like to thank Chris and >Jani >> for replying. > >No problem, thanks for following up with this. Sorry to hear about the >display. It'll be a warranty issue. Actually I'm relieved because if the display had worked well under Windows, I wouldn't have known what to do. Martin > >BR, >Jani. -- Diese Nachricht wurde von meinem Android-Mobiltelefon mit K-9 Mail gesendet. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/skl: Enable eDRAM for gen9 as well
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5681 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 353/353 353/353 ILK 200/200 200/200 SNB 400/422 400/422 IVB +2 485/487 487/487 BYT 296/296 296/296 HSW +1-1 507/508 507/508 BDW 401/402 401/402 -Detailed- Platform Testdrm-intel-nightly Series Applied IVB igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance DMESG_WARN(6, M34M21)PASS(8, M4M34) PASS(1, M4) IVB igt_gem_storedw_batches_loop_normal DMESG_WARN(5, M34M4)PASS(15, M34M4M21) PASS(1, M4) HSW igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance DMESG_WARN(1, M40)PASS(18, M40M20) PASS(1, M40) *HSW igt_gem_pwrite_pread_uncached-copy-performance PASS(2, M40) DMESG_WARN(1, M40) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/4] More nuclear pageflip
On Sat, Jan 31, 2015 at 10:35:32AM +0100, Daniel Vetter wrote: > On Fri, Jan 30, 2015 at 04:22:35PM -0800, Matt Roper wrote: > > The first two patches here were already posted earlier this week; they allow > > our legacy plane updates to make use of the main atomic helpers rather than > > the > > transitional atomic helpers. This shouldn't have any functional change, > > but it > > will cause us to exercise the full atomic pipeline rather than just the > > plane > > subset of it. > > > > The third patch is the interesting one; it allows us to handle nuclear > > pageflip > > requests in a non-blocking manner and deliver a uevent upon completion. > > This > > is important functionality for compositors since it allows them to request > > that > > the kernel perform a flip, then continue on doing other work while they wait > > for the flip to actually happen. > > > > The final patch here switches our legacy pageflip ioctl to use the atomic > > helper (thus exercising the new asynchronous support added in patch #3). > > Removing the i915-specific pageflip handling should allow us to drop a > > bunch of > > our display code; I've been somewhat conservative in my code removal for now > > (just enough to get rid of the 'function unused' compiler warnings); we can > > do > > further cleanup of code that relates to the legacy pageflip pipeline in a > > future patchset. > > Our current mmio flip doesn't work on gen4 and earlier because the flip > completion event generation only works with MI_ flips. So I think we need > to (at least for now) keep the legacy flip code around and wired up for > those platforms. > > But we need to redo the flip completion anyway (and probably just key off > the next vblank interrupt) since if you'd do an atomic flip with just > sprites the event stuff wont work on any platform. Once we have that we > can then also roll out the legacy-pageflip-on-atomic for older platforms. > -Daniel Hmm, my code at the moment sends the completion event to userspace and marks the CRTC as no longer having a flip pending after drm_atomic_helper_wait_for_vblanks(dev, state) call, which probably works when we're actually updating the framebuffer, but I guess that will send the uevent too early in cases where the fb doesn't change (since we already made a point of optimizing out that unnecessary vblank wait). So maybe I should just get the "schedule stuff for future vblank" mechanism done that I already had on my plate for the watermark stuff, and then use that to send the uevent once the next vblank following the commit happens. It occurs to me that I probably need to take a look at all the i915 hangcheck/recovery stuff too; I haven't paid much attention to how that works, but I'm guessing it probably needs to be updated a bit now as well. Matt > > > > > Matt Roper (4): > > drm/i915: Keep plane->state updated on pageflip > > drm/i915: Switch planes from transitional helpers to full atomic > > helpers > > drm/i915: Enable asynchronous nuclear flips > > drm/i915: Use atomic helper for pageflips > > > > drivers/gpu/drm/i915/i915_drv.h | 9 +- > > drivers/gpu/drm/i915/i915_params.c | 5 - > > drivers/gpu/drm/i915/intel_atomic.c | 162 ++-- > > drivers/gpu/drm/i915/intel_display.c | 716 > > +-- > > drivers/gpu/drm/i915/intel_drv.h | 8 + > > drivers/gpu/drm/i915/intel_lrc.c | 3 +- > > 6 files changed, 155 insertions(+), 748 deletions(-) > > > > -- > > 1.8.5.1 > > > > ___ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/4] drm/i915: Enable asynchronous nuclear flips
On Sat, Jan 31, 2015 at 10:30:29AM +0100, Daniel Vetter wrote:
> On Fri, Jan 30, 2015 at 04:22:38PM -0800, Matt Roper wrote:
> > The initial i915 nuclear pageflip support rejected asynchronous updates.
> > Allow all work after we swap in the new state structures to run
> > asynchronously. We also need to start sending completion events to
> > userspace if they were requested.
> >
> > Signed-off-by: Matt Roper
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 3 +
> > drivers/gpu/drm/i915/intel_atomic.c | 162
> > +++-
> > drivers/gpu/drm/i915/intel_drv.h| 8 ++
> > 3 files changed, 150 insertions(+), 23 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 8fad702..c7a520a 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1777,6 +1777,9 @@ struct drm_i915_private {
> > struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
> > wait_queue_head_t pending_flip_queue;
> >
> > + /* CRTC mask of pending atomic flips */
> > + uint32_t pending_atomic;
> > +
> > #ifdef CONFIG_DEBUG_FS
> > struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
> > #endif
> > diff --git a/drivers/gpu/drm/i915/intel_atomic.c
> > b/drivers/gpu/drm/i915/intel_atomic.c
> > index 19a9dd5..5dd7897 100644
> > --- a/drivers/gpu/drm/i915/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/intel_atomic.c
> > @@ -76,6 +76,8 @@ int intel_atomic_check(struct drm_device *dev,
> > state->allow_modeset = false;
> > for (i = 0; i < ncrtcs; i++) {
> > struct intel_crtc *crtc = to_intel_crtc(state->crtcs[i]);
> > + if (crtc)
> > + state->crtc_states[i]->enable = crtc->active;
> > if (crtc && crtc->pipe != nuclear_pipe)
> > not_nuclear = true;
> > }
> > @@ -96,6 +98,87 @@ int intel_atomic_check(struct drm_device *dev,
> > }
> >
> >
> > +/*
> > + * Wait until CRTC's have no pending flip, then atomically mark those
> > CRTC's
> > + * as busy.
> > + */
> > +static int wait_for_pending_flip(uint32_t crtc_mask,
> > +struct intel_pending_atomic *commit)
> > +{
> > + struct drm_i915_private *dev_priv = commit->dev->dev_private;
> > + int ret;
> > +
> > + spin_lock_irq(&dev_priv->pending_flip_queue.lock);
> > + ret = wait_event_interruptible_locked(dev_priv->pending_flip_queue,
> > + !(dev_priv->pending_atomic &
> > crtc_mask));
> > + if (ret == 0)
> > + dev_priv->pending_atomic |= crtc_mask;
> > + spin_unlock_irq(&dev_priv->pending_flip_queue.lock);
> > +
> > + return ret;
> > +}
> > +
> > +/* Finish pending flip operation on specified CRTC's */
> > +static void flip_completion(struct intel_pending_atomic *commit)
> > +{
> > + struct drm_i915_private *dev_priv = commit->dev->dev_private;
> > +
> > + spin_lock_irq(&dev_priv->pending_flip_queue.lock);
> > + dev_priv->pending_atomic &= ~commit->crtc_mask;
> > + wake_up_all_locked(&dev_priv->pending_flip_queue);
> > + spin_unlock_irq(&dev_priv->pending_flip_queue.lock);
> > +}
> > +
> > +/*
> > + * Finish an atomic commit. The work here can be performed asynchronously
> > + * if desired. The new state has already been applied to the DRM objects
> > + * and no modeset locks are needed.
> > + */
> > +static void finish_atomic_commit(struct work_struct *work)
> > +{
> > + struct intel_pending_atomic *commit =
> > + container_of(work, struct intel_pending_atomic, work);
> > + struct drm_device *dev = commit->dev;
> > + struct drm_crtc *crtc;
> > + struct drm_atomic_state *state = commit->state;
> > + int i;
> > +
> > + /*
> > +* FIXME: The proper sequence here will eventually be:
> > +*
> > +* drm_atomic_helper_commit_pre_planes(dev, state);
> > +* drm_atomic_helper_commit_planes(dev, state);
> > +* drm_atomic_helper_commit_post_planes(dev, state);
> > +* drm_atomic_helper_wait_for_vblanks(dev, state);
> > +* drm_atomic_helper_cleanup_planes(dev, state);
> > +* drm_atomic_state_free(state);
> > +*
> > +* once we have full atomic modeset. For now, just manually update
> > +* plane states to avoid clobbering good states with dummy states
> > +* while nuclear pageflipping.
> > +*/
> > + drm_atomic_helper_commit_planes(dev, state);
> > + drm_atomic_helper_wait_for_vblanks(dev, state);
> > +
> > + /* Send CRTC completion events. */
> > + for (i = 0; i < dev->mode_config.num_crtc; i++) {
> > + crtc = state->crtcs[i];
> > + if (crtc && crtc->state->event) {
> > + spin_lock_irq(&dev->event_lock);
> > + drm_send_vblank_event(dev, to_intel_crtc(crtc)->pipe,
> > + crtc->state->event);
> > + spin_unlock_irq(&dev->event_lock);
> > + crtc->state->event = NULL;
> > +
[Intel-gfx] [BISECTED REGRESSION in 3.19-rc1] [drm/i915] WARNING: drivers/gpu/drm/drm_irq.c:1077 drm_wait_one_vblank
Hi, this warning exist in v3.19-rc6 and does not in v3.18. Bisection points to the commit 51e31d49c890552 "drm/i915: Use generic vblank wait". I have two machines with integrated Intel graphics and the problem happens only on the old one with GM965 chipset and X3100 integrated graphics. backtrace information: [ 31.780813] WARNING: CPU: 0 PID: 718 at drivers/gpu/drm/drm_irq.c:1077 drm_wait_one_vblank+0x33/0x141 [drm]() [ 31.780815] Modules linked in: ecb(E) i915(E+) snd_hda_codec_generic(E) coretemp(E) btusb(E) kvm_intel(E) snd_hda_intel(E) snd_hda_controller(E) kvm(E) drm_kms_helper(E) snd_hda_code c(E) snd_pcsp(E) bluetooth(E) snd_hwdep(E) drm(E) lpc_ich(E) evdev(E) mfd_core(E) snd_pcm(E) snd_timer(E) snd(E) psmouse(E) serio_raw(E) i2c_algo_bit(E) i2c_i801(E) rfkill(E) soundcore( E) battery(E) button(E) video(E) ac(E) i2ccore(E) acpi_cpufreq(E) processor(E) fuse(E) parport_pc(E) ppdev(E) lp(E) parport(E) autofs4(E) ext4(E) crc16(E) jbd2(E) mbcache(E) sd_mod(E) a ta_generic(E) ahci(E) libahci(E) sdhci_pci(E) sdhci(E) firewire_ohci(E) b44(E) mii(E) ssb(E) ata_piix(E) firewire_core(E) crc_itu_t(E) mmc_core(E) libphy(E) libata(E) scsi_mod(E) xhci_h cd(E) ehci_pci(E) uhci_hcd(E) ehci_hcd(E) usbcore(E) usb_common(E) thermal(E) [ 31.780862] thermal_sys(E) [ 31.780866] CPU: 0 PID: 718 Comm: kworker/u4:3 Tainted: GE 3.17.0-rc5-150116--00578-g51e31d4 #16 [ 31.780868] Hardware name: Dell Inc. Vostro 1500 /0NX907, BIOS A06 04/21/2008 [ 31.780873] Workqueue: events_unbound async_run_entry_fn [ 31.780875] a0544b9d 813d4e81 [ 31.780879] 8103dec3 8800d84e0068 a0521c73 00070008 [ 31.780882] 8800d84e 8801973e0800 6014 [ 31.780886] Call Trace: [ 31.780890] [] ? dump_stack+0x4a/0x75 [ 31.780894] [] ? warn_slowpath_common+0x7e/0x97 [ 31.781050] [] ? drm_wait_one_vblank+0x33/0x141 [drm] [ 31.781078] [] ? drm_wait_one_vblank+0x33/0x141 [drm] [ 31.781122] [] ? intel_enable_tv+0x22/0x58 [i915] [ 31.781153] [] ? i9xx_crtc_enable+0x33b/0x397 [i915] [ 31.781184] [] ? __intel_set_mode+0x1160/0x1209 [i915] [ 31.781216] [] ? intel_set_mode+0x12/0x2c [i915] [ 31.781247] [] ? intel_get_load_detect_pipe+0x367/0x408 [i915] [ 31.781281] [] ? intel_tv_detect+0x103/0x444 [i915] [ 31.781289] [] ? drm_helper_probe_single_connector_modes_merge_bits+0xc0/0x327 [drm_kms_helper] [ 31.781296] [] ? drm_fb_helper_probe_connector_modes+0x3d/0x51 [drm_kms_helper] [ 31.781303] [] ? drm_fb_helper_initial_config+0x3d/0x303 [drm_kms_helper] [ 31.781306] [] ? async_run_entry_fn+0x5a/0x110 [ 31.781310] [] ? process_one_work+0x194/0x292 [ 31.781313] [] ? worker_thread+0x236/0x298 [ 31.781316] [] ? process_scheduled_works+0x2a/0x2a [ 31.781319] [] ? kthread+0x9e/0xa6 [ 31.781322] [] ? kthread_freezable_should_stop+0x36/0x36 [ 31.781326] [] ? ret_from_fork+0x7c/0xb0 [ 31.781329] [] ? kthread_freezable_should_stop+0x36/0x36 [ 31.782726] ---[ end trace e2b78017f1a10054 ]--- lspci: 00:02.0 VGA compatible controller [0300]: Intel Corporation Mobile GM965/GL960 Integrated Graphics Controller (primary) [8086:2a02] (rev 0c) 00:02.1 Display controller [0380]: Intel Corporation Mobile GM965/GL960 Integrated Graphics Controller (secondary) [8086:2a03] (rev 0c) -- Best regards, Andrey Skvortsov Secure e-mail with gnupg: See http://www.gnupg.org/ PGP Key ID: 0x57A3AEAD ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Simplify pll state commit by swapping new and old state
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5683 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 353/353 353/353 ILK 353/353 353/353 SNB 400/422 400/422 IVB +1 485/487 486/487 BYT 296/296 296/296 HSW +1-11 404/405 394/405 BDW -1 401/402 400/402 -Detailed- Platform Testdrm-intel-nightly Series Applied IVB igt_gem_storedw_batches_loop_normal DMESG_WARN(5, M34M4)PASS(15, M34M4M21) PASS(1, M21) *HSW igt_gem_pwrite_pread_display-copy-performance PASS(5, M40M20) DMESG_WARN(1, M40) HSW igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance DMESG_WARN(1, M40)PASS(18, M40M20) PASS(1, M40) *HSW igt_kms_cursor_crc_cursor-size-change PASS(2, M40) TIMEOUT(1, M40) *HSW igt_kms_fence_pin_leak PASS(2, M40) TIMEOUT(1, M40) *HSW igt_kms_flip_bo-too-big PASS(2, M40) TIMEOUT(1, M40) *HSW igt_kms_flip_bo-too-big-interruptible PASS(2, M40) CRASH(1, M40) *HSW igt_kms_flip_dpms-vs-vblank-race PASS(2, M40) TIMEOUT(1, M40) *HSW igt_kms_flip_event_leak PASS(2, M40) TIMEOUT(1, M40) *HSW igt_kms_flip_flip-vs-dpms-off-vs-modeset PASS(2, M40) TIMEOUT(1, M40) *HSW igt_kms_flip_flip-vs-expired-vblank PASS(2, M40) TIMEOUT(1, M40) *HSW igt_kms_flip_flip-vs-expired-vblank-interruptible PASS(2, M40) CRASH(1, M40) *HSW igt_kms_flip_nonexisting-fb PASS(3, M40M20) TIMEOUT(1, M40) *BDW igt_kms_fence_pin_leak PASS(2, M30) TIMEOUT(1, M30) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fix a use-after-free in intel_execlists_retire_requests
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5684 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 353/353 353/353 ILK 200/200 200/200 SNB 400/422 400/422 IVB +2 485/487 487/487 BYT 296/296 296/296 HSW +1 507/508 508/508 BDW -2 401/402 399/402 -Detailed- Platform Testdrm-intel-nightly Series Applied IVB igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance DMESG_WARN(6, M34M21)PASS(8, M4M34) PASS(1, M4) IVB igt_gem_storedw_batches_loop_normal DMESG_WARN(5, M34M4)PASS(15, M34M4M21) PASS(1, M4) HSW igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance DMESG_WARN(1, M40)PASS(18, M40M20) PASS(1, M20) BDW igt_gem_pwrite_pread_display-pwrite-blt-gtt_mmap-performance DMESG_WARN(4, M28)PASS(2, M30) DMESG_WARN(1, M28) *BDW igt_gem_pwrite_pread_uncached-pwrite-blt-gtt_mmap-performance PASS(6, M30M28) DMESG_WARN(1, M28) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] RFC: drm: add support for tiled/compressed/etc modifier in addfb2
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5685 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 353/353 353/353 ILK 353/353 353/353 SNB 400/422 400/422 IVB +1-2 485/487 484/487 BYT 296/296 296/296 HSW 507/508 507/508 BDW 401/402 401/402 -Detailed- Platform Testdrm-intel-nightly Series Applied *IVB igt_gem_pwrite_pread_snooped-copy-performance PASS(2, M34) DMESG_WARN(1, M34) IVB igt_gem_storedw_batches_loop_normal DMESG_WARN(5, M34M4)PASS(15, M34M4M21) PASS(1, M34) IVB igt_gem_storedw_batches_loop_secure-dispatch DMESG_WARN(1, M34)PASS(6, M34M4) DMESG_WARN(1, M34) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Use pipe_config's cpu_transcoder for reading dp_mst hw state
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 5687 -Summary- Platform Delta drm-intel-nightly Series Applied PNV 353/353 353/353 ILK -1 353/353 352/353 SNB 400/422 400/422 IVB +2-1 485/487 486/487 BYT 296/296 296/296 HSW +1-1 507/508 507/508 BDW 401/402 401/402 -Detailed- Platform Testdrm-intel-nightly Series Applied *ILK igt_gem_unfence_active_buffers PASS(2, M26) DMESG_WARN(1, M26) IVB igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance DMESG_WARN(6, M34M21)PASS(8, M4M34) PASS(1, M34) IVB igt_gem_storedw_batches_loop_normal DMESG_WARN(5, M34M4)PASS(15, M34M4M21) PASS(1, M34) IVB igt_gem_storedw_batches_loop_secure-dispatch DMESG_WARN(1, M34)PASS(6, M34M4) DMESG_WARN(1, M34) *HSW igt_gem_pwrite_pread_display-copy-performance PASS(5, M40M20) DMESG_WARN(1, M40) HSW igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance DMESG_WARN(1, M40)PASS(19, M40M20) PASS(1, M40) Note: You need to pay more attention to line start with '*' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
