Re: [Intel-gfx] [PATCH] drm/i915: Use BUILD_BUG if possible in the i915 WARN_ON

[Jani Nikula]

On Wed, 10 Dec 2014, Daniel Vetter  wrote:
> Faster feedback to errors is always better. This is inspired by the
> addition to WARN_ONs to mask/enable helpers for registers to make sure
> callers have the arguments ordered correctly: Pretty much always the
> arguments are static.
>
> We use WARN_ON(1) a lot in default switch statements though where we
> should always handle all cases. So add a new macro specifically for
> that.
>
> The idea to use __builtin_constant_p is from Chris Wilson.
>
> v2: Use the ({}) gcc-ism to avoid the static inline, suggested by
> Dave. My first attempt used __cond as the temp var, which is the same
> used by BUILD_BUG_ON, but with inverted sense. Hilarity ensued, so
> sprinkle i915 into the name.
>
> Also use a temporary variable to only evaluate the condition once,
> suggested by Damien.
>
> v3: It's crazy but apparently 32bit gcc can't compile out the
> BUILD_BUG_ON in a lot of cases and just falls over. I have no idea
> why, but until clue grows just disable this nifty idea on 32bit
> builds. Reported by 0-day builder.
>
> v4: Got it all wrong, apparently its the gcc version. We need 4.9+.
> Now reported by Imre.
>
> v5: Chris suggested to add the case to MISSING_CASE for speedier
> debug.

Still fails here. :(

$ gcc --version
gcc (Debian 4.9.1-19) 4.9.1

$ make
  CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CALLscripts/checksyscalls.sh
  CHK include/generated/compile.h
  CHK kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/i915_drv.o
In file included from include/linux/ioport.h:12:0,
 from include/linux/device.h:16,
 from drivers/gpu/drm/i915/i915_drv.c:30:
drivers/gpu/drm/i915/i915_drv.c: In function ‘intel_detect_pch’:
include/linux/compiler.h:363:38: error: call to ‘__compiletime_assert_477’ 
declared with attribute error: BUILD_BUG_ON failed: __i915_warn_cond
  _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
  ^
include/linux/compiler.h:346:4: note: in definition of macro 
‘__compiletime_assert’
prefix ## suffix();\
^
include/linux/compiler.h:363:2: note: in expansion of macro 
‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
  ^
include/linux/bug.h:50:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
 ^
include/linux/bug.h:74:2: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
  ^
drivers/gpu/drm/i915/i915_drv.h:66:3: note: in expansion of macro ‘BUILD_BUG_ON’
   BUILD_BUG_ON(__i915_warn_cond); \
   ^
drivers/gpu/drm/i915/i915_drv.c:477:5: note: in expansion of macro ‘WARN_ON’
 WARN_ON(!IS_HSW_ULT(dev));
 ^
include/linux/compiler.h:363:38: error: call to ‘__compiletime_assert_456’ 
declared with attribute error: BUILD_BUG_ON failed: __i915_warn_cond
  _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
  ^
include/linux/compiler.h:346:4: note: in definition of macro 
‘__compiletime_assert’
prefix ## suffix();\
^
include/linux/compiler.h:363:2: note: in expansion of macro 
‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
  ^
include/linux/bug.h:50:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
 ^
include/linux/bug.h:74:2: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
  ^
drivers/gpu/drm/i915/i915_drv.h:66:3: note: in expansion of macro ‘BUILD_BUG_ON’
   BUILD_BUG_ON(__i915_warn_cond); \
   ^
drivers/gpu/drm/i915/i915_drv.c:456:5: note: in expansion of macro ‘WARN_ON’
 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 ^
include/linux/compiler.h:363:38: error: call to ‘__compiletime_assert_461’ 
declared with attribute error: BUILD_BUG_ON failed: __i915_warn_cond
  _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
  ^
include/linux/compiler.h:346:4: note: in definition of macro 
‘__compiletime_assert’
prefix ## suffix();\
^
include/linux/compiler.h:363:2: note: in expansion of macro 
‘_compiletime_assert’
  _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
  ^
include/linux/bug.h:50:37: note: in expansion of macro ‘compiletime_assert’
 #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
 ^
include/linux/bug.h:74:2: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
  BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
  ^
drivers/gpu/drm/i915/i915_drv.h:66:3: note: in expansion of macro ‘BUILD_BUG_ON’
   BUILD_BUG_ON(_

[Intel-gfx] [PATCH 3/3] drm/i915: Disable PMSI sleep messages on all rings around context switches

[Chris Wilson]

There exists a current workaround to prevent a hang on context switch
should the ring go to sleep in the middle of the restore,
WaProgramMiArbOnOffAroundMiSetContext (applicable to all gen7+). In
spite of disabling arbitration (which prevents the ring from powering
down during the critical section) we were still hitting hangs that had
the hallmarks of the known erratum. That is we are still seeing hangs
"on the last instruction in the context restore". By comparing -nightly
(broken) with requests (working), we were able to deduce that it was the
semaphore LRI cross-talk that reproduced the original failure.
Explicitly disabling PMSI sleep on the RCS ring was insufficient, all
the rings had to be awake to prevent the hangs. Fortunately, we can
reduce the wakelock to the MI_SET_CONTEXT operation itself, and so
should be able to limit the extra power implications.

Since the MI_ARB_ON_OFF workaround is listed for all gen7 and above
products, we should apply this extra hammer for all of the same
platforms despite so far that we have only been able to reproduce the
hang on certain ivb and hsw models. The last question is whether we want
to always use the extra hammer or only when we know semaphores are in
operation. At the moment, we only use LRI on non-RCS rings for
semaphores, but that may change in the future with the possibility of
reintroducing this bug under subtle conditions.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80660
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83677
Cc: Simon Farnsworth 
Signed-off-by: Chris Wilson 
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/i915/i915_gem_context.c | 39 -
 drivers/gpu/drm/i915/i915_reg.h |  2 ++
 2 files changed, 31 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 2acf5803cf32..724ccecea06a 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -484,7 +484,9 @@ mi_set_context(struct intel_engine_cs *ring,
   u32 hw_flags)
 {
u32 flags = hw_flags | MI_MM_SPACE_GTT;
-   int ret;
+   struct intel_engine_cs *engine;
+   const int num_rings = i915_semaphore_is_enabled(ring->dev) ? 
hweight32(INTEL_INFO(ring->dev)->ring_mask) : 0;
+   int len, i, ret;
 
/* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
@@ -501,15 +503,26 @@ mi_set_context(struct intel_engine_cs *ring,
if (!IS_HASWELL(ring->dev) && INTEL_INFO(ring->dev)->gen < 8)
flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
 
-   ret = intel_ring_begin(ring, 6);
+
+   len = 4;
+   if (INTEL_INFO(ring->dev)->gen >= 7)
+   len += 4*num_rings + 2;
+
+   ret = intel_ring_begin(ring, len);
if (ret)
return ret;
 
/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
-   if (INTEL_INFO(ring->dev)->gen >= 7)
-   intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
-   else
-   intel_ring_emit(ring, MI_NOOP);
+   if (INTEL_INFO(ring->dev)->gen >= 7) {
+   if (num_rings) {
+   intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
+   for_each_ring(engine, to_i915(ring->dev), i) {
+   intel_ring_emit(ring, 
RING_PSMI_CTL(engine->mmio_base));
+   intel_ring_emit(ring, 
_MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
+   }
+   } else
+   intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
+   }
 
intel_ring_emit(ring, MI_NOOP);
intel_ring_emit(ring, MI_SET_CONTEXT);
@@ -521,10 +534,16 @@ mi_set_context(struct intel_engine_cs *ring,
 */
intel_ring_emit(ring, MI_NOOP);
 
-   if (INTEL_INFO(ring->dev)->gen >= 7)
-   intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
-   else
-   intel_ring_emit(ring, MI_NOOP);
+   if (INTEL_INFO(ring->dev)->gen >= 7) {
+   if (num_rings) {
+   intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
+   for_each_ring(engine, to_i915(ring->dev), i) {
+   intel_ring_emit(ring, 
RING_PSMI_CTL(engine->mmio_base));
+   intel_ring_emit(ring, 
_MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
+   }
+   } else
+   intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
+   }
 
intel_ring_advance(ring);
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0ddef7256d02..1ce303cb8852 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1134,6 +1134,7 @@ enum p

[Intel-gfx] [PATCH 1/3] drm/i915: Invalidate media caches on gen7

[Chris Wilson]

In the gen7 pipe control there is an extra bit to flush the media
caches, so let's set it during cache invalidation flushes.

Cc: Simon Farnsworth 
Signed-off-by: Chris Wilson 
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 93fdad8a7447..0ddef7256d02 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -400,6 +400,7 @@
 #define   PIPE_CONTROL_STORE_DATA_INDEX(1<<21)
 #define   PIPE_CONTROL_CS_STALL(1<<20)
 #define   PIPE_CONTROL_TLB_INVALIDATE  (1<<18)
+#define   PIPE_CONTROL_MEDIA_CACHE_INVALIDATE  (1<<16)
 #define   PIPE_CONTROL_QW_WRITE(1<<14)
 #define   PIPE_CONTROL_POST_SYNC_OP_MASK(3<<14)
 #define   PIPE_CONTROL_DEPTH_STALL (1<<13)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 4702e7bcd71c..282279b83ca4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -373,6 +373,7 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
+   flags |= PIPE_CONTROL_MEDIA_CACHE_INVALIDATE;
/*
 * TLB invalidate requires a post-sync write.
 */
-- 
2.1.3

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[Intel-gfx] [PATCH 2/3] drm/i915: Force the CS stall for invalidate flushes

[Chris Wilson]

In order to act as a full command barrier by itself, we need to tell the
pipecontrol to actually stall the command streamer while the flush runs.
We require the full command barrier before operations like
MI_SET_CONTEXT, which currently rely on a prior invalidate flush.

References: https://bugs.freedesktop.org/show_bug.cgi?id=83677
Cc: Simon Farnsworth 
Signed-off-by: Chris Wilson 
Cc: sta...@vger.kernel.org
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 282279b83ca4..02fb478a2867 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -380,6 +380,8 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
flags |= PIPE_CONTROL_QW_WRITE;
flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 
+   flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
+
/* Workaround: we must issue a pipe_control with CS-stall bit
 * set before a pipe_control command that has the state cache
 * invalidate bit set. */
-- 
2.1.3

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Re: [Intel-gfx] [PATCH] drm/i915/i9xx: check for panel on pipe before asserting panel unlock bits

[shuang . he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: 
shuang...@intel.com)
-Summary-
Platform  Delta  drm-intel-nightly  Series Applied
PNV  364/364  364/364
ILK  +1-4  364/366  361/366
SNB  448/450  448/450
IVB  497/498  497/498
BYT  289/289  289/289
HSW  563/564  563/564
BDW  417/417  417/417
-Detailed-
Platform  Testdrm-intel-nightly  Series 
Applied
*ILK  igt_kms_pipe_crc_basic_bad-pipe  PASS(2, M26)  DMESG_WARN(1, M26)
*ILK  igt_kms_flip_busy-flip-interruptible  PASS(5, M26)  DMESG_WARN(1, 
M26)
*ILK  igt_kms_flip_flip-vs-rmfb-interruptible  NSPT(1, M26)PASS(5, M26) 
 DMESG_WARN(1, M26)
 ILK  igt_kms_flip_plain-flip-ts-check-interruptible  DMESG_WARN(1, 
M26)PASS(4, M26)  DMESG_WARN(1, M26)
 ILK  igt_kms_flip_wf_vblank-ts-check  DMESG_WARN(7, M26)PASS(21, M26M37)   
   PASS(1, M26)
Note: You need to pay more attention to line start with '*'
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[Intel-gfx] [PATCH 4/4] drm/i915: Skip gunit save/restore for cherryview

[deepak . s]

From: Deepak S 

With cherryview onwards, Gunit hardware itself save and restore all the
Gunit registers. Skipping the "vlv_save_gunit_s0ix_state" &
"vlv_restore_gunit_s0ix_state" for cherryview in S3/S0ix sequence.

Signed-off-by: Deepak S 
---
 drivers/gpu/drm/i915/i915_drv.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6c09bf8..6257f66 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1299,7 +1299,9 @@ static int vlv_suspend_complete(struct drm_i915_private 
*dev_priv)
err = vlv_allow_gt_wake(dev_priv, false);
if (err)
goto err2;
-   vlv_save_gunit_s0ix_state(dev_priv);
+
+   if (!IS_CHERRYVIEW(dev_priv->dev))
+   vlv_save_gunit_s0ix_state(dev_priv);
 
err = vlv_force_gfx_clock(dev_priv, false);
if (err)
@@ -1330,7 +1332,8 @@ static int vlv_resume_prepare(struct drm_i915_private 
*dev_priv,
 */
ret = vlv_force_gfx_clock(dev_priv, true);
 
-   vlv_restore_gunit_s0ix_state(dev_priv);
+   if (!IS_CHERRYVIEW(dev_priv->dev))
+   vlv_restore_gunit_s0ix_state(dev_priv);
 
err = vlv_allow_gt_wake(dev_priv, true);
if (!ret)
-- 
1.9.1

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[Intel-gfx] [PATCH 3/4] drm/i915: New offset for reading frequencies on CHV.

[deepak . s]

From: Deepak S 

Use new Sideband offset to read max/min/gaur freq based on the SKU it
is running on. Based on the Number of EU, we read different bits to
identify the max frequencies at which system can run.

Signed-off-by: Deepak S 
---
 drivers/gpu/drm/i915/i915_drv.h   |  4 +--
 drivers/gpu/drm/i915/i915_reg.h   | 12 
 drivers/gpu/drm/i915/intel_pm.c   | 52 ++-
 drivers/gpu/drm/i915/intel_sideband.c |  4 +--
 4 files changed, 61 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b58bad4..0690dff 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3016,8 +3016,8 @@ int sandybridge_pcode_read(struct drm_i915_private 
*dev_priv, u32 mbox, u32 *val
 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 
val);
 
 /* intel_sideband.c */
-u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
-void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
+u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
+void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b57cba3..f41290c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -602,6 +602,18 @@ enum punit_power_well {
 #define PUNIT_FUSE_BUS20xf6 /* bits 47:40 */
 #define PUNIT_FUSE_BUS10xf5 /* bits 55:48 */
 
+#define FB_GFX_FMAX_AT_VMAX_FUSE   0x136
+#define FB_GFX_FMAX_AT_VMAX_FUSE_MASK  0xff
+#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT  24
+#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT  16
+#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT  8
+
+#define FB_GFX_GUAR_FREQ_FUSE_MASK 0xff
+
+#define FB_GFX_FMIN_AT_VMIN_FUSE   0x137
+#define FB_GFX_FMIN_AT_VMIN_FUSE_MASK  0xff
+#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
+
 #define PUNIT_GPU_STATUS_REG   0xdb
 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT16
 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2acb3de..71b8e2f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4346,11 +4346,29 @@ void gen6_update_ring_freq(struct drm_device *dev)
 
 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
 {
+   struct drm_device *dev = dev_priv->dev;
+   struct intel_device_info *info;
u32 val, rp0;
 
-   val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
-   rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & 
PUNIT_GPU_STATUS_MAX_FREQ_MASK;
-
+   info = (struct intel_device_info *)&dev_priv->info;
+
+   if (dev->pdev->revision >= 0x20) {
+   val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
+
+   if (info->eu_total == 8) /* (2 * 4) config */
+   rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
+   else if (info->eu_total == 12) /* (2 * 6) config */
+   rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
+   else if (info->eu_total == 16) /* (2 * 8) config */
+   rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
+   else /* Setting (2 * 8) Min RP0 for any other combination */
+   rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
+   rp0 = (rp0 & FB_GFX_FMAX_AT_VMAX_FUSE_MASK);
+   } else { /* For pre-production hardware */
+   val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
+   rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
+  PUNIT_GPU_STATUS_MAX_FREQ_MASK;
+   }
return rp0;
 }
 
@@ -4366,20 +4384,40 @@ static int cherryview_rps_rpe_freq(struct 
drm_i915_private *dev_priv)
 
 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
 {
+   struct drm_device *dev = dev_priv->dev;
+   struct intel_device_info *info;
u32 val, rp1;
 
-   val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
-   rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & 
PUNIT_GPU_STATUS_MAX_FREQ_MASK;
+   info = (struct intel_device_info *)&dev_priv->info;
 
+   if (dev->pdev->revision >= 0x20) {
+   val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
+   rp1 = (val & FB_GFX_GUAR_FREQ_FUSE_MASK);
+   } else { /* For pre-production hardware */
+   val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+   rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT

[Intel-gfx] [PATCH 2/4] drm/i915/chv: Populate total EU count on Cherryview

[deepak . s]

From: Deepak S 

Starting with Cherryview, devices may have a varying number of EU for
a given ID due to creative fusing. Punit support different frequency for
different fuse data. We use this patch to help get total eu enabled and
read the right offset to get RP0

Based upon a patch from Jeff, but reworked to only store eu_total and
avoid sending info to userspace

Signed-off-by: Deepak S 
Signed-off-by: Jeff McGee 
---
 drivers/gpu/drm/i915/i915_dma.c | 11 +++
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_reg.h | 11 +++
 3 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 887d88f..2bd36b6 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -598,6 +598,17 @@ static void intel_device_info_runtime_init(struct 
drm_device *dev)
info->num_pipes = 0;
}
}
+
+   if (IS_CHERRYVIEW(dev)) {
+   u32 fuse, mask_eu;
+
+   fuse = I915_READ(CHV_FUSE_GT);
+   mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
+ CHV_FGT_EU_DIS_SS0_R1_MASK |
+ CHV_FGT_EU_DIS_SS1_R0_MASK |
+ CHV_FGT_EU_DIS_SS1_R1_MASK);
+   info->eu_total = 16 - hweight32(mask_eu);
+   }
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9381504..b58bad4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -624,6 +624,7 @@ struct intel_device_info {
int trans_offsets[I915_MAX_TRANSCODERS];
int palette_offsets[I915_MAX_PIPES];
int cursor_offsets[I915_MAX_PIPES];
+   unsigned int eu_total;
 };
 
 #undef DEFINE_FLAG
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 93fdad8..b57cba3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1466,6 +1466,17 @@ enum punit_power_well {
 #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE(1 << 12)
 #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE   (1<<10)
 
+/* Fuse readout registers for GT */
+#define CHV_FUSE_GT0x182168
+#define   CHV_FGT_EU_DIS_SS0_R0_SHIFT  16
+#define   CHV_FGT_EU_DIS_SS0_R0_MASK   (0xf

[Intel-gfx] [PATCH 1/4] drm/i915/chv: Use timeout mode for RC6 on chv

[deepak . s]

From: Deepak S 

Higher RC6 residency is observed using timeout mode
instead of EI mode. It's Recommended to use TO Method for RC6.

Signed-off-by: Deepak S 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_pm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2316d23..2acb3de 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4689,7 +4689,8 @@ static void cherryview_enable_rps(struct drm_device *dev)
I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
I915_WRITE(GEN6_RC_SLEEP, 0);
 
-   I915_WRITE(GEN6_RC6_THRESHOLD, 5); /* 50/125ms per EI */
+   /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */
+   I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
 
/* allows RC6 residency counter to work */
I915_WRITE(VLV_COUNTER_CONTROL,
@@ -4703,7 +4704,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
/* 3: Enable RC6 */
if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
(pcbr >> VLV_PCBR_ADDR_SHIFT))
-   rc6_mode = GEN6_RC_CTL_EI_MODE(1);
+   rc6_mode = GEN7_RC_CTL_TO_MODE;
 
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
 
-- 
1.9.1

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Re: [Intel-gfx] [PATCH 1/8] drm/i915: Rebalance runtime pm vs forcewake

[Deepak S]

On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:

From: Chris Wilson 

Calling intel_runtime_pm_put() is illegal from a soft-irq context, so
revert the crude hack

commit aa0b3b5bb8768c1a6a6788869d9c7015eae7e80c
Author: Paulo Zanoni 
Date:   Tue Apr 1 14:55:07 2014 -0300

 drm/i915: don't schedule force_wake_timer at gen6_read

and apply the single line corrective instead.

References: https://bugs.freedesktop.org/show_bug.cgi?id=80913
Cc: Paulo Zanoni 
Cc: Daniel Vetter 
Signed-off-by: Chris Wilson 
---
  drivers/gpu/drm/i915/i915_drv.c |  1 +
  drivers/gpu/drm/i915/intel_uncore.c | 18 ++
  2 files changed, 7 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 71be3c9..706b122 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1402,6 +1402,7 @@ static int intel_runtime_suspend(struct device *device)
}
  
  	del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);

+   intel_uncore_forcewake_reset(dev, false);
dev_priv->pm.suspended = true;
  
  	/*

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 46de8d7..38ac389 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -449,8 +449,6 @@ static void gen6_force_wake_timer(unsigned long arg)
if (--dev_priv->uncore.forcewake_count == 0)
dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
-
-   intel_runtime_pm_put(dev_priv);
  }
  
  void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)

@@ -586,7 +584,6 @@ void gen6_gt_force_wake_get(struct drm_i915_private 
*dev_priv, int fw_engine)
  void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
  {
unsigned long irqflags;
-   bool delayed = false;
  
  	if (!dev_priv->uncore.funcs.force_wake_put)

return;
@@ -603,21 +600,19 @@ void gen6_gt_force_wake_put(struct drm_i915_private 
*dev_priv, int fw_engine)
goto out;
}
  
-

spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
WARN_ON(!dev_priv->uncore.forcewake_count);
  
  	if (--dev_priv->uncore.forcewake_count == 0) {

dev_priv->uncore.forcewake_count++;
-   delayed = true;
mod_timer_pinned(&dev_priv->uncore.force_wake_timer,
 jiffies + 1);
}
+
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
  
  out:

-   if (!delayed)
-   intel_runtime_pm_put(dev_priv);
+   intel_runtime_pm_put(dev_priv);
  }
  
  void assert_force_wake_inactive(struct drm_i915_private *dev_priv)

@@ -777,12 +772,11 @@ gen6_read##x(struct drm_i915_private *dev_priv, off_t 
reg, bool trace) { \
NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
dev_priv->uncore.funcs.force_wake_get(dev_priv, \
  FORCEWAKE_ALL); \
-   val = __raw_i915_read##x(dev_priv, reg); \
-   dev_priv->uncore.funcs.force_wake_put(dev_priv, \
- FORCEWAKE_ALL); \
-   } else { \
-   val = __raw_i915_read##x(dev_priv, reg); \
+   dev_priv->uncore.forcewake_count++; \
+   mod_timer_pinned(&dev_priv->uncore. , \
+jiffies + 1); \


why timer, we can do a put after register read right?

Other changes looks fine to me
Reviewed-by: Deepak S 


} \
+   val = __raw_i915_read##x(dev_priv, reg); \
hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
REG_READ_FOOTER; \
  }


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Re: [Intel-gfx] [PATCH 1/8] drm/i915: Rebalance runtime pm vs forcewake

[Chris Wilson]

On Fri, Dec 12, 2014 at 03:30:14PM +0530, Deepak S wrote:
> 
> On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:
> >From: Chris Wilson 
> >
> >Calling intel_runtime_pm_put() is illegal from a soft-irq context, so
> >revert the crude hack
> >
> >commit aa0b3b5bb8768c1a6a6788869d9c7015eae7e80c
> >Author: Paulo Zanoni 
> >Date:   Tue Apr 1 14:55:07 2014 -0300
> >
> > drm/i915: don't schedule force_wake_timer at gen6_read
> >
> >and apply the single line corrective instead.
> >
> >References: https://bugs.freedesktop.org/show_bug.cgi?id=80913
> >Cc: Paulo Zanoni 
> >Cc: Daniel Vetter 
> >Signed-off-by: Chris Wilson 
> >---
> >@@ -777,12 +772,11 @@ gen6_read##x(struct drm_i915_private *dev_priv, off_t 
> >reg, bool trace) { \
> > NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
> > dev_priv->uncore.funcs.force_wake_get(dev_priv, \
> >   FORCEWAKE_ALL); \
> >-val = __raw_i915_read##x(dev_priv, reg); \
> >-dev_priv->uncore.funcs.force_wake_put(dev_priv, \
> >-  FORCEWAKE_ALL); \
> >-} else { \
> >-val = __raw_i915_read##x(dev_priv, reg); \
> >+dev_priv->uncore.forcewake_count++; \
> >+mod_timer_pinned(&dev_priv->uncore. , \
> >+ jiffies + 1); \
> 
> why timer, we can do a put after register read right?

The presumption is that we will do another mmio access requiring the
forcewake very shortly, and we want to avoid the forcewake clear/ack
cycle. So we defer dropping the forcewake until the end of the kernel
context on this cpu (the goal being that as the scheduler switches back
to the userspace context, we release the wakelock, it would be great if
there was an explicit callback for that...).
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Infrastructure for supporting different GGTT views per object

[Michel Thierry]

On 12/10/2014 5:27 PM, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

Things like reliable GGTT mappings and mirrored 2d-on-3d display will need
to map objects into the same address space multiple times.

Added a GGTT view concept and linked it with the VMA to distinguish between
multiple instances per address space.

New objects and GEM functions which do not take this new view as a parameter
assume the default of zero (I915_GGTT_VIEW_NORMAL) which preserves the
previous behaviour.

This now means that objects can have multiple VMA entries so the code which
assumed there will only be one also had to be modified.

Alternative GGTT views are supposed to borrow DMA addresses from obj->pages
which is DMA mapped on first VMA instantiation and unmapped on the last one
going away.

v2:
 * Removed per view special casing in i915_gem_ggtt_prepare /
   finish_object in favour of creating and destroying DMA mappings
   on first VMA instantiation and last VMA destruction. (Daniel Vetter)
 * Simplified i915_vma_unbind which does not need to count the GGTT views.
   (Daniel Vetter)
 * Also moved obj->map_and_fenceable reset under the same check.
 * Checkpatch cleanups.

v3:
 * Only retire objects once the last VMA is unbound.

v4:
 * Keep scatter-gather table for alternative views persistent for the
   lifetime of the VMA.
 * Propagate binding errors to callers and handle appropriately.

v5:
 * Explicitly look for normal GGTT view in i915_gem_obj_bound to align
   usage in i915_gem_object_ggtt_unpin. (Michel Thierry)
 * Change to single if statement in i915_gem_obj_to_ggtt. (Michel Thierry)
 * Removed stray semi-colon in i915_gem_object_set_cache_level.

For: VIZ-4544
Signed-off-by: Tvrtko Ursulin 
Cc: Daniel Vetter 

Good catch in i915_gem_object_set_cache_level.

Reviewed-by: Michel Thierry 




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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Documentation for multiple GGTT views

[Michel Thierry]

On 12/10/2014 5:27 PM, Tvrtko Ursulin wrote:

From: Tvrtko Ursulin 

A short section describing background, implementation and intended usage.

v2:
 * Align section name between template and DOC comment. (Michel Thierry)

For: VIZ-4544
Signed-off-by: Tvrtko Ursulin 


Reviewed-by: Michel Thierry 



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[Intel-gfx] [PATCH] drm/i915/bdw: Enable execlists by default where supported

[Thomas Daniel]

Execlist support in the i915 driver is now considered good enough for the
feature to be enabled by default on Gen8 and later and routinely tested.
Adjusted i915 parameters structure initialization to reflect this and updated
the comment in intel_sanitize_enable_execlists().

Issue: VIZ-2020
Signed-off-by: Thomas Daniel 
---
 drivers/gpu/drm/i915/i915_params.c |2 +-
 drivers/gpu/drm/i915/intel_lrc.c   |3 +--
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index c91cb20..ad685d8 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -35,7 +35,7 @@ struct i915_params i915 __read_mostly = {
.vbt_sdvo_panel_type = -1,
.enable_rc6 = -1,
.enable_fbc = -1,
-   .enable_execlists = 0,
+   .enable_execlists = -1,
.enable_hangcheck = true,
.enable_ppgtt = -1,
.enable_psr = 0,
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 89b5577..4dc6d42 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -212,8 +212,7 @@ static int intel_lr_context_pin(struct intel_engine_cs 
*ring,
  * @enable_execlists: value of i915.enable_execlists module parameter.
  *
  * Only certain platforms support Execlists (the prerequisites being
- * support for Logical Ring Contexts and Aliasing PPGTT or better),
- * and only when enabled via module parameter.
+ * support for Logical Ring Contexts and Aliasing PPGTT or better).
  *
  * Return: 1 if Execlists is supported and has to be enabled.
  */
-- 
1.7.9.5

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Re: [Intel-gfx] [PATCH 1/8] drm/i915: Rebalance runtime pm vs forcewake

[Deepak S]

On Thursday 11 December 2014 03:45 PM, Chris Wilson wrote:

On Fri, Dec 12, 2014 at 03:30:14PM +0530, Deepak S wrote:

On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:

From: Chris Wilson 

Calling intel_runtime_pm_put() is illegal from a soft-irq context, so
revert the crude hack

commit aa0b3b5bb8768c1a6a6788869d9c7015eae7e80c
Author: Paulo Zanoni 
Date:   Tue Apr 1 14:55:07 2014 -0300

 drm/i915: don't schedule force_wake_timer at gen6_read

and apply the single line corrective instead.

References: https://bugs.freedesktop.org/show_bug.cgi?id=80913
Cc: Paulo Zanoni 
Cc: Daniel Vetter 
Signed-off-by: Chris Wilson 
---
@@ -777,12 +772,11 @@ gen6_read##x(struct drm_i915_private *dev_priv, off_t 
reg, bool trace) { \
NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
dev_priv->uncore.funcs.force_wake_get(dev_priv, \
  FORCEWAKE_ALL); \
-   val = __raw_i915_read##x(dev_priv, reg); \
-   dev_priv->uncore.funcs.force_wake_put(dev_priv, \
- FORCEWAKE_ALL); \
-   } else { \
-   val = __raw_i915_read##x(dev_priv, reg); \
+   dev_priv->uncore.forcewake_count++; \
+   mod_timer_pinned(&dev_priv->uncore. , \
+jiffies + 1); \

why timer, we can do a put after register read right?

The presumption is that we will do another mmio access requiring the
forcewake very shortly, and we want to avoid the forcewake clear/ack
cycle. So we defer dropping the forcewake until the end of the kernel
context on this cpu (the goal being that as the scheduler switches back
to the userspace context, we release the wakelock, it would be great if
there was an explicit callback for that...).
-Chris


Thanks Chris. got it :)


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Re: [Intel-gfx] [PATCH 2/8] drm/i915: Assert that runtime pm is active on user fw access

[Deepak S]

On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:

From: Chris Wilson 

On user forcewake access, assert that runtime pm reference is held.
Fix and cleanup the callsites accordingly.

Signed-off-by: Chris Wilson 
Signed-off-by: Mika Kuoppala 
---
  drivers/gpu/drm/i915/i915_debugfs.c  |  2 +
  drivers/gpu/drm/i915/intel_display.c | 19 +
  drivers/gpu/drm/i915/intel_lrc.c | 53 ++---
  drivers/gpu/drm/i915/intel_uncore.c  | 76 
  4 files changed, 31 insertions(+), 119 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index d0e445e..e142629 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4250,6 +4250,7 @@ static int i915_forcewake_open(struct inode *inode, 
struct file *file)
if (INTEL_INFO(dev)->gen < 6)
return 0;
  
+	intel_runtime_pm_get(dev_priv);

gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
  
  	return 0;

@@ -4264,6 +4265,7 @@ static int i915_forcewake_release(struct inode *inode, 
struct file *file)
return 0;
  
  	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);

+   intel_runtime_pm_put(dev_priv);
  
  	return 0;

  }
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index d5153a4..86c2885 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7862,19 +7862,8 @@ static void hsw_restore_lcpll(struct drm_i915_private 
*dev_priv)
/*
 * Make sure we're not on PC8 state before disabling PC8, otherwise
 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
-*
-* The other problem is that hsw_restore_lcpll() is called as part of
-* the runtime PM resume sequence, so we can't just call
-* gen6_gt_force_wake_get() because that function calls
-* intel_runtime_pm_get(), and we can't change the runtime PM refcount
-* while we are on the resume sequence. So to solve this problem we have
-* to call special forcewake code that doesn't touch runtime PM and
-* doesn't enable the forcewake delayed work.
 */
-   spin_lock_irq(&dev_priv->uncore.lock);
-   if (dev_priv->uncore.forcewake_count++ == 0)
-   dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
-   spin_unlock_irq(&dev_priv->uncore.lock);
+   gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
  
  	if (val & LCPLL_POWER_DOWN_ALLOW) {

val &= ~LCPLL_POWER_DOWN_ALLOW;
@@ -7904,11 +7893,7 @@ static void hsw_restore_lcpll(struct drm_i915_private 
*dev_priv)
DRM_ERROR("Switching back to LCPLL failed\n");
}
  
-	/* See the big comment above. */

-   spin_lock_irq(&dev_priv->uncore.lock);
-   if (--dev_priv->uncore.forcewake_count == 0)
-   dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
-   spin_unlock_irq(&dev_priv->uncore.lock);
+   gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
  }
  
  /*

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index a82020e..fcb5140 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -284,7 +284,6 @@ static void execlists_elsp_write(struct intel_engine_cs 
*ring,
struct drm_i915_private *dev_priv = dev->dev_private;
uint64_t temp = 0;
uint32_t desc[4];
-   unsigned long flags;
  
  	/* XXX: You must always write both descriptors in the order below. */

if (ctx_obj1)
@@ -298,63 +297,17 @@ static void execlists_elsp_write(struct intel_engine_cs 
*ring,
desc[3] = (u32)(temp >> 32);
desc[2] = (u32)temp;
  
-	/* Set Force Wakeup bit to prevent GT from entering C6 while ELSP writes

-* are in progress.
-*
-* The other problem is that we can't just call gen6_gt_force_wake_get()
-* because that function calls intel_runtime_pm_get(), which might 
sleep.
-* Instead, we do the runtime_pm_get/put when creating/destroying 
requests.
-*/
-   spin_lock_irqsave(&dev_priv->uncore.lock, flags);
-   if (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) {
-   if (dev_priv->uncore.fw_rendercount++ == 0)
-   dev_priv->uncore.funcs.force_wake_get(dev_priv,
- FORCEWAKE_RENDER);
-   if (dev_priv->uncore.fw_mediacount++ == 0)
-   dev_priv->uncore.funcs.force_wake_get(dev_priv,
- FORCEWAKE_MEDIA);
-   if (INTEL_INFO(dev)->gen >= 9) {
-   if (dev_priv->uncore.fw_blittercount++ == 0)
-   dev_priv->uncore.funcs.force_wake_get(dev_priv,
-   FORCEWAKE_

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Assert that runtime pm is active on user fw access

[Chris Wilson]

On Fri, Dec 12, 2014 at 05:09:26PM +0530, Deepak S wrote:
> >@@ -564,17 +542,20 @@ void gen6_gt_force_wake_get(struct drm_i915_private 
> >*dev_priv, int fw_engine)
> > intel_runtime_pm_get(dev_priv);
> 
> I think we need to remove "intel_runtime_pm_get" here?
> I see runtime_put is removed from "gen6_gt_force_wake_put"
> 
> >-/* Redirect to Gen9 specific routine */
> >-if (IS_GEN9(dev_priv->dev))
> >-return gen9_force_wake_get(dev_priv, fw_engine);
> >-
> >-/* Redirect to VLV specific routine */
> >-if (IS_VALLEYVIEW(dev_priv->dev))
> >-return vlv_force_wake_get(dev_priv, fw_engine);
> >+WARN_ON(!pm_runtime_active(&dev_priv->dev->pdev->dev));

Indeed, the purpose of this patch was to remove the rpm_get() and
replace it with this WARN_ON (and so make sure that all call paths here
already held the rpm reference). Something went wrong in the rebase I
hope.
-Chris

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Re: [Intel-gfx] [PATCH 3/8] drm/i915: Skip uncore lock on earlier gens

[Deepak S]

On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:

From: Chris Wilson 

With gen < 6 we don't need to take uncore lock as we
don't have anything to protect from concurrent access.

v2: rebase and account for gen9 changes

Signed-off-by: Chris Wilson  (v1)
Signed-off-by: Mika Kuoppala 
---
  drivers/gpu/drm/i915/intel_uncore.c | 158 +---
  1 file changed, 91 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index a1ceb92..069fe7a 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -707,38 +707,61 @@ hsw_unclaimed_reg_detect(struct drm_i915_private 
*dev_priv)
}
  }
  
-#define REG_READ_HEADER(x) \

-   unsigned long irqflags; \
+#define GEN2_READ_HEADER(x) \
u##x val = 0; \
-   assert_device_not_suspended(dev_priv); \
-   spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
+   assert_device_not_suspended(dev_priv);
  
-#define REG_READ_FOOTER \

-   spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
+#define GEN2_READ_FOOTER \
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
return val
  
-#define __gen4_read(x) \

+#define __gen2_read(x) \
  static u##x \
-gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
-   REG_READ_HEADER(x); \
+gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+   GEN2_READ_HEADER(x); \
val = __raw_i915_read##x(dev_priv, reg); \
-   REG_READ_FOOTER; \
+   GEN2_READ_FOOTER; \
  }
  
  #define __gen5_read(x) \

  static u##x \
  gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
-   REG_READ_HEADER(x); \
+   GEN2_READ_HEADER(x); \
ilk_dummy_write(dev_priv); \
val = __raw_i915_read##x(dev_priv, reg); \
-   REG_READ_FOOTER; \
+   GEN2_READ_FOOTER; \
  }
  
+__gen5_read(8)

+__gen5_read(16)
+__gen5_read(32)
+__gen5_read(64)
+__gen2_read(8)
+__gen2_read(16)
+__gen2_read(32)
+__gen2_read(64)
+
+#undef __gen5_read
+#undef __gen2_read
+
+#undef GEN2_READ_FOOTER
+#undef GEN2_READ_HEADER
+
+#define GEN6_READ_HEADER(x) \
+   unsigned long irqflags; \
+   u##x val = 0; \
+   assert_device_not_suspended(dev_priv); \
+   spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
+
+#define GEN6_READ_FOOTER \
+   spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
+   trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
+   return val
+
  #define __gen6_read(x) \
  static u##x \
  gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
-   REG_READ_HEADER(x); \
+   GEN6_READ_HEADER(x); \
hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
if (dev_priv->uncore.forcewake_count == 0 && \
NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
@@ -750,14 +773,14 @@ gen6_read##x(struct drm_i915_private *dev_priv, off_t 
reg, bool trace) { \
} \
val = __raw_i915_read##x(dev_priv, reg); \
hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
-   REG_READ_FOOTER; \
+   GEN6_READ_FOOTER; \
  }
  
  #define __vlv_read(x) \

  static u##x \
  vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
unsigned fwengine = 0; \
-   REG_READ_HEADER(x); \
+   GEN6_READ_HEADER(x); \
if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
if (dev_priv->uncore.fw_rendercount == 0) \
fwengine = FORCEWAKE_RENDER; \
@@ -770,14 +793,14 @@ vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, 
bool trace) { \
val = __raw_i915_read##x(dev_priv, reg); \
if (fwengine) \
dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
-   REG_READ_FOOTER; \
+   GEN6_READ_FOOTER; \
  }
  
  #define __chv_read(x) \

  static u##x \
  chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
unsigned fwengine = 0; \
-   REG_READ_HEADER(x); \
+   GEN6_READ_HEADER(x); \
if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
if (dev_priv->uncore.fw_rendercount == 0) \
fwengine = FORCEWAKE_RENDER; \
@@ -795,7 +818,7 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, 
bool trace) { \
val = __raw_i915_read##x(dev_priv, reg); \
if (fwengine) \
dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
-   REG_READ_FOOTER; \
+   GEN6_READ_FOOTER; \
  }
  
  #define SKL_NEEDS_FORCE_WAKE(dev_priv, reg)	\

@@ -804,7 +827,7 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, 
bool trace) { \
  #define __gen9_read(x) \
  static u##x \
  gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
-   REG_READ_HEADER(x); \
+   GEN6_READ_HEADER(x); \
if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
val = _

Re: [Intel-gfx] [PATCH] drm/i915/bdw: Enable execlists by default where supported

[Jani Nikula]

On Thu, 11 Dec 2014, Thomas Daniel  wrote:
> Execlist support in the i915 driver is now considered good enough for the
> feature to be enabled by default on Gen8 and later and routinely tested.
> Adjusted i915 parameters structure initialization to reflect this and updated
> the comment in intel_sanitize_enable_execlists().

Please update the MODULE_PARM_DESC too.

BR,
Jani.


>
> Issue: VIZ-2020
> Signed-off-by: Thomas Daniel 
> ---
>  drivers/gpu/drm/i915/i915_params.c |2 +-
>  drivers/gpu/drm/i915/intel_lrc.c   |3 +--
>  2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_params.c 
> b/drivers/gpu/drm/i915/i915_params.c
> index c91cb20..ad685d8 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -35,7 +35,7 @@ struct i915_params i915 __read_mostly = {
>   .vbt_sdvo_panel_type = -1,
>   .enable_rc6 = -1,
>   .enable_fbc = -1,
> - .enable_execlists = 0,
> + .enable_execlists = -1,
>   .enable_hangcheck = true,
>   .enable_ppgtt = -1,
>   .enable_psr = 0,
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 89b5577..4dc6d42 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -212,8 +212,7 @@ static int intel_lr_context_pin(struct intel_engine_cs 
> *ring,
>   * @enable_execlists: value of i915.enable_execlists module parameter.
>   *
>   * Only certain platforms support Execlists (the prerequisites being
> - * support for Logical Ring Contexts and Aliasing PPGTT or better),
> - * and only when enabled via module parameter.
> + * support for Logical Ring Contexts and Aliasing PPGTT or better).
>   *
>   * Return: 1 if Execlists is supported and has to be enabled.
>   */
> -- 
> 1.7.9.5
>
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Re: [Intel-gfx] [PATCH 2/8] drm/i915: Assert that runtime pm is active on user fw access

[Deepak S]

On Thursday 11 December 2014 05:23 PM, Chris Wilson wrote:

On Fri, Dec 12, 2014 at 05:09:26PM +0530, Deepak S wrote:

@@ -564,17 +542,20 @@ void gen6_gt_force_wake_get(struct drm_i915_private 
*dev_priv, int fw_engine)
intel_runtime_pm_get(dev_priv);

I think we need to remove "intel_runtime_pm_get" here?
I see runtime_put is removed from "gen6_gt_force_wake_put"


-   /* Redirect to Gen9 specific routine */
-   if (IS_GEN9(dev_priv->dev))
-   return gen9_force_wake_get(dev_priv, fw_engine);
-
-   /* Redirect to VLV specific routine */
-   if (IS_VALLEYVIEW(dev_priv->dev))
-   return vlv_force_wake_get(dev_priv, fw_engine);
+   WARN_ON(!pm_runtime_active(&dev_priv->dev->pdev->dev));

Indeed, the purpose of this patch was to remove the rpm_get() and
replace it with this WARN_ON (and so make sure that all call paths here
already held the rpm reference). Something went wrong in the rebase I
hope.
-Chris


Yeah, Looks like it got missed.

Hi Mika,
once we fix the issue, you can add my r-b, Other changes looks fine


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Re: [Intel-gfx] [PATCH 4/4] drm/i915: Skip gunit save/restore for cherryview

[Ville Syrjälä]

On Fri, Dec 12, 2014 at 02:18:16PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S 
> 
> With cherryview onwards, Gunit hardware itself save and restore all the
> Gunit registers. Skipping the "vlv_save_gunit_s0ix_state" &
> "vlv_restore_gunit_s0ix_state" for cherryview in S3/S0ix sequence.
> 
> Signed-off-by: Deepak S 

I had the same patch tucked away somewhere, but didn't bother to send it
since I've not yet looked into s0ix. In any case the docs agree with
this so:

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 6c09bf8..6257f66 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1299,7 +1299,9 @@ static int vlv_suspend_complete(struct drm_i915_private 
> *dev_priv)
>   err = vlv_allow_gt_wake(dev_priv, false);
>   if (err)
>   goto err2;
> - vlv_save_gunit_s0ix_state(dev_priv);
> +
> + if (!IS_CHERRYVIEW(dev_priv->dev))
> + vlv_save_gunit_s0ix_state(dev_priv);
>  
>   err = vlv_force_gfx_clock(dev_priv, false);
>   if (err)
> @@ -1330,7 +1332,8 @@ static int vlv_resume_prepare(struct drm_i915_private 
> *dev_priv,
>*/
>   ret = vlv_force_gfx_clock(dev_priv, true);
>  
> - vlv_restore_gunit_s0ix_state(dev_priv);
> + if (!IS_CHERRYVIEW(dev_priv->dev))
> + vlv_restore_gunit_s0ix_state(dev_priv);
>  
>   err = vlv_allow_gt_wake(dev_priv, true);
>   if (!ret)
> -- 
> 1.9.1

-- 
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[Intel-gfx] [PATCH] drm/i915: Use true PPGTT in Gen8 if execlists are enabled

[Michel Thierry]

When execlists submission is enabled, try full ppgtt by default.

Note, this patch considers that execlist support has been enabled by
default on Gen8.

Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 171f6ea..4ed3904 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -40,8 +40,8 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int 
enable_ppgtt)
 
has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
-   if (IS_GEN8(dev))
-   has_full_ppgtt = false; /* XXX why? */
+   if (IS_GEN8(dev) && !i915.enable_execlists)
+   has_full_ppgtt = false; /* Only enforce with execlists */
 
/*
 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
@@ -72,7 +72,10 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int 
enable_ppgtt)
return 0;
}
 
-   return has_aliasing_ppgtt ? 1 : 0;
+   if (INTEL_INFO(dev)->gen < 8)
+   return has_aliasing_ppgtt ? 1 : 0;
+   else
+   return has_full_ppgtt ? 2 : has_aliasing_ppgtt ? 1 : 0;
 }
 
 
-- 
2.1.1

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Re: [Intel-gfx] [PATCH 2/4] drm/i915/chv: Populate total EU count on Cherryview

[Jani Nikula]

On Fri, 12 Dec 2014, deepa...@linux.intel.com wrote:
> From: Deepak S 
>
> Starting with Cherryview, devices may have a varying number of EU for
> a given ID due to creative fusing. Punit support different frequency for
> different fuse data. We use this patch to help get total eu enabled and
> read the right offset to get RP0
>
> Based upon a patch from Jeff, but reworked to only store eu_total and
> avoid sending info to userspace
>
> Signed-off-by: Deepak S 
> Signed-off-by: Jeff McGee 
> ---
>  drivers/gpu/drm/i915/i915_dma.c | 11 +++
>  drivers/gpu/drm/i915/i915_drv.h |  1 +
>  drivers/gpu/drm/i915/i915_reg.h | 11 +++
>  3 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 887d88f..2bd36b6 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -598,6 +598,17 @@ static void intel_device_info_runtime_init(struct 
> drm_device *dev)
>   info->num_pipes = 0;
>   }
>   }
> +
> + if (IS_CHERRYVIEW(dev)) {
> + u32 fuse, mask_eu;
> +
> + fuse = I915_READ(CHV_FUSE_GT);
> + mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
> +   CHV_FGT_EU_DIS_SS0_R1_MASK |
> +   CHV_FGT_EU_DIS_SS1_R0_MASK |
> +   CHV_FGT_EU_DIS_SS1_R1_MASK);
> + info->eu_total = 16 - hweight32(mask_eu);
> + }
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9381504..b58bad4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -624,6 +624,7 @@ struct intel_device_info {
>   int trans_offsets[I915_MAX_TRANSCODERS];
>   int palette_offsets[I915_MAX_PIPES];
>   int cursor_offsets[I915_MAX_PIPES];
> + unsigned int eu_total;
>  };
>  
>  #undef DEFINE_FLAG
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 93fdad8..b57cba3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1466,6 +1466,17 @@ enum punit_power_well {
>  #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE  (1 << 12)
>  #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
>  
> +/* Fuse readout registers for GT */
> +#define CHV_FUSE_GT  0x182168

Should this be (VLV_DISPLAY_BASE + 0x2168)?

> +#define   CHV_FGT_EU_DIS_SS0_R0_SHIFT16
> +#define   CHV_FGT_EU_DIS_SS0_R0_MASK (0xf< +#define   CHV_FGT_EU_DIS_SS0_R1_SHIFT20
> +#define   CHV_FGT_EU_DIS_SS0_R1_MASK (0xf< +#define   CHV_FGT_EU_DIS_SS1_R0_SHIFT24
> +#define   CHV_FGT_EU_DIS_SS1_R0_MASK (0xf< +#define   CHV_FGT_EU_DIS_SS1_R1_SHIFT28
> +#define   CHV_FGT_EU_DIS_SS1_R1_MASK (0xf< +
>  #define GEN6_BSD_SLEEP_PSMI_CONTROL  0x12050
>  #define   GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
>  #define   GEN6_BSD_SLEEP_FLUSH_DISABLE   (1 << 2)
> -- 
> 1.9.1
>
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Re: [Intel-gfx] [PATCH 2/4] drm/i915/chv: Populate total EU count on Cherryview

[Deepak S]

On Thursday 11 December 2014 05:39 PM, Jani Nikula wrote:

On Fri, 12 Dec 2014, deepa...@linux.intel.com wrote:

From: Deepak S 

Starting with Cherryview, devices may have a varying number of EU for
a given ID due to creative fusing. Punit support different frequency for
different fuse data. We use this patch to help get total eu enabled and
read the right offset to get RP0

Based upon a patch from Jeff, but reworked to only store eu_total and
avoid sending info to userspace

Signed-off-by: Deepak S 
Signed-off-by: Jeff McGee 
---
  drivers/gpu/drm/i915/i915_dma.c | 11 +++
  drivers/gpu/drm/i915/i915_drv.h |  1 +
  drivers/gpu/drm/i915/i915_reg.h | 11 +++
  3 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 887d88f..2bd36b6 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -598,6 +598,17 @@ static void intel_device_info_runtime_init(struct 
drm_device *dev)
info->num_pipes = 0;
}
}
+
+   if (IS_CHERRYVIEW(dev)) {
+   u32 fuse, mask_eu;
+
+   fuse = I915_READ(CHV_FUSE_GT);
+   mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
+ CHV_FGT_EU_DIS_SS0_R1_MASK |
+ CHV_FGT_EU_DIS_SS1_R0_MASK |
+ CHV_FGT_EU_DIS_SS1_R1_MASK);
+   info->eu_total = 16 - hweight32(mask_eu);
+   }
  }
  
  /**

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9381504..b58bad4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -624,6 +624,7 @@ struct intel_device_info {
int trans_offsets[I915_MAX_TRANSCODERS];
int palette_offsets[I915_MAX_PIPES];
int cursor_offsets[I915_MAX_PIPES];
+   unsigned int eu_total;
  };
  
  #undef DEFINE_FLAG

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 93fdad8..b57cba3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1466,6 +1466,17 @@ enum punit_power_well {
  #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE   (1 << 12)
  #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE  (1<<10)
  
+/* Fuse readout registers for GT */

+#define CHV_FUSE_GT0x182168

Should this be (VLV_DISPLAY_BASE + 0x2168)?
  

+#define   CHV_FGT_EU_DIS_SS0_R0_SHIFT  16
+#define   CHV_FGT_EU_DIS_SS0_R0_MASK   (0xf<
Please add spaces both sides of "<<" if you end up sending a v2.


Thanks for review.
I will address both the comment and send v2


+
  #define GEN6_BSD_SLEEP_PSMI_CONTROL   0x12050
  #define   GEN6_BSD_SLEEP_MSG_DISABLE  (1 << 0)
  #define   GEN6_BSD_SLEEP_FLUSH_DISABLE(1 << 2)
--
1.9.1

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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Invalidate media caches on gen7

[Ville Syrjälä]

On Thu, Dec 11, 2014 at 08:16:59AM +, Chris Wilson wrote:
> In the gen7 pipe control there is an extra bit to flush the media
> caches, so let's set it during cache invalidation flushes.

Bspec is telling me this bit is already present in snb, and calls it
'Generic Media State Clear'. Older Bspec seems to suggest we should set
it here, and maybe that we should also issue another PIPE_CONTROL with
the bit set after MI_SET_CONTEXT when switching from media to 3D context.
These notes don't seem to be present in the current BSpec, so I'm not
sure what the deal is.

> 
> Cc: Simon Farnsworth 
> Signed-off-by: Chris Wilson 
> Cc: sta...@vger.kernel.org
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 1 +
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 93fdad8a7447..0ddef7256d02 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -400,6 +400,7 @@
>  #define   PIPE_CONTROL_STORE_DATA_INDEX  (1<<21)
>  #define   PIPE_CONTROL_CS_STALL  (1<<20)
>  #define   PIPE_CONTROL_TLB_INVALIDATE(1<<18)
> +#define   PIPE_CONTROL_MEDIA_CACHE_INVALIDATE(1<<16)
>  #define   PIPE_CONTROL_QW_WRITE  (1<<14)
>  #define   PIPE_CONTROL_POST_SYNC_OP_MASK(3<<14)
>  #define   PIPE_CONTROL_DEPTH_STALL   (1<<13)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 4702e7bcd71c..282279b83ca4 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -373,6 +373,7 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
>   flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
>   flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
>   flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
> + flags |= PIPE_CONTROL_MEDIA_CACHE_INVALIDATE;
>   /*
>* TLB invalidate requires a post-sync write.
>*/
> -- 
> 2.1.3
> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] [PATCH] drm/i915/skl: Correcting the flushing of pipe

[sonika . jindal]

From: Sonika Jindal 

We were incorreectly bypassing the flush everytime which led to fifo
underrun when more than one plane is enabled.

Signed-off-by: Sonika Jindal 
---
 drivers/gpu/drm/i915/intel_pm.c |3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5748bf9..8cd045a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3633,9 +3633,8 @@ static void skl_flush_wm_values(struct drm_i915_private 
*dev_priv,
skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
skl_wm_flush_pipe(dev_priv, pipe, 2);
intel_wait_for_vblank(dev, pipe);
+   reallocated[pipe] = true;
}
-
-   reallocated[pipe] = true;
}
 
/*
-- 
1.7.10.4

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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Disable PMSI sleep messages on all rings around context switches

[shuang . he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: 
shuang...@intel.com)
-Summary-
Platform  Delta  drm-intel-nightly  Series Applied
PNV  364/364  364/364
ILK  +1 364/366  365/366
SNB  448/450  448/450
IVB  497/498  497/498
BYT  289/289  289/289
HSW  563/564  563/564
BDW  417/417  417/417
-Detailed-
Platform  Testdrm-intel-nightly  Series 
Applied
 ILK  igt_kms_flip_wf_vblank-ts-check  DMESG_WARN(7, M26)PASS(22, M26M37)   
   PASS(1, M37)
Note: You need to pay more attention to line start with '*'
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[Intel-gfx] [PATCH v2] drm/i915/chv: Populate total EU count on Cherryview

[deepak . s]

From: Deepak S 

Starting with Cherryview, devices may have a varying number of EU for
a given ID due to creative fusing. Punit support different frequency for
different fuse data. We use this patch to help get total eu enabled and
read the right offset to get RP0

Based upon a patch from Jeff, but reworked to only store eu_total and
avoid sending info to userspace

v2: Format register definitions (Jani)

Signed-off-by: Deepak S 
Signed-off-by: Jeff McGee 
---
 drivers/gpu/drm/i915/i915_dma.c | 11 +++
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_reg.h | 11 +++
 3 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 887d88f..2bd36b6 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -598,6 +598,17 @@ static void intel_device_info_runtime_init(struct 
drm_device *dev)
info->num_pipes = 0;
}
}
+
+   if (IS_CHERRYVIEW(dev)) {
+   u32 fuse, mask_eu;
+
+   fuse = I915_READ(CHV_FUSE_GT);
+   mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
+ CHV_FGT_EU_DIS_SS0_R1_MASK |
+ CHV_FGT_EU_DIS_SS1_R0_MASK |
+ CHV_FGT_EU_DIS_SS1_R1_MASK);
+   info->eu_total = 16 - hweight32(mask_eu);
+   }
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9381504..b58bad4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -624,6 +624,7 @@ struct intel_device_info {
int trans_offsets[I915_MAX_TRANSCODERS];
int palette_offsets[I915_MAX_PIPES];
int cursor_offsets[I915_MAX_PIPES];
+   unsigned int eu_total;
 };
 
 #undef DEFINE_FLAG
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 93fdad8..09442c3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1466,6 +1466,17 @@ enum punit_power_well {
 #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE(1 << 12)
 #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE   (1<<10)
 
+/* Fuse readout registers for GT */
+#define CHV_FUSE_GT(VLV_DISPLAY_BASE + 0x2168)
+#define   CHV_FGT_EU_DIS_SS0_R0_SHIFT  16
+#define   CHV_FGT_EU_DIS_SS0_R0_MASK   (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
+#define   CHV_FGT_EU_DIS_SS0_R1_SHIFT  20
+#define   CHV_FGT_EU_DIS_SS0_R1_MASK   (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
+#define   CHV_FGT_EU_DIS_SS1_R0_SHIFT  24
+#define   CHV_FGT_EU_DIS_SS1_R0_MASK   (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
+#define   CHV_FGT_EU_DIS_SS1_R1_SHIFT  28
+#define   CHV_FGT_EU_DIS_SS1_R1_MASK   (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL0x12050
 #define   GEN6_BSD_SLEEP_MSG_DISABLE   (1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
-- 
1.9.1

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[Intel-gfx] [PATCH 0/8] Resend of drm/i915: Keep drm_crtc->state in sync

[Ander Conselvan de Oliveira]

I'm resending this series, now without the RFC status. Code is
unchanged from the RFC.

Ander Conselvan de Oliveira (8):
  drm/i915: Rename struct intel_crtc_config to intel_crtc_state
  drm/i915: Embedded struct drm_crtc_state in intel_crtc_state
  drm/i915: Pass new_config down do crtc_compute_clock
  drm/i915: Use local pipe_config varariable when available
  drm/i915: Don't access to crtc->new_config from
intel_mode_max_pixclk()
  drm/i915: Remove intel_crtc->new_config pointer
  drm/i915: Make intel_crtc->config a pointer
  drm/i915: Keep drm_crtc->state in sync with intel_crtc->config

 drivers/gpu/drm/i915/i915_debugfs.c  |  12 +-
 drivers/gpu/drm/i915/i915_drv.h  |   7 +-
 drivers/gpu/drm/i915/i915_irq.c  |   8 +-
 drivers/gpu/drm/i915/intel_audio.c   |   2 +-
 drivers/gpu/drm/i915/intel_crt.c |  16 +-
 drivers/gpu/drm/i915/intel_ddi.c | 103 ++---
 drivers/gpu/drm/i915/intel_display.c | 714 ++-
 drivers/gpu/drm/i915/intel_dp.c  |  34 +-
 drivers/gpu/drm/i915/intel_dp_mst.c  |  15 +-
 drivers/gpu/drm/i915/intel_drv.h |  45 +--
 drivers/gpu/drm/i915/intel_dsi.c |  18 +-
 drivers/gpu/drm/i915/intel_dvo.c |  20 +-
 drivers/gpu/drm/i915/intel_fbdev.c   |  10 +-
 drivers/gpu/drm/i915/intel_hdmi.c|  48 +--
 drivers/gpu/drm/i915/intel_lvds.c|  16 +-
 drivers/gpu/drm/i915/intel_overlay.c |   2 +-
 drivers/gpu/drm/i915/intel_panel.c   |  16 +-
 drivers/gpu/drm/i915/intel_pm.c  |  60 +--
 drivers/gpu/drm/i915/intel_psr.c |   8 +-
 drivers/gpu/drm/i915/intel_sdvo.c|  28 +-
 drivers/gpu/drm/i915/intel_sprite.c  |   2 +-
 drivers/gpu/drm/i915/intel_tv.c  |  10 +-
 22 files changed, 604 insertions(+), 590 deletions(-)

-- 
1.9.1

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[Intel-gfx] [PATCH 5/8] drm/i915: Don't access to crtc->new_config from intel_mode_max_pixclk()

[Ander Conselvan de Oliveira]

So that we can get rid of the new_config pointer later.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_display.c | 30 ++
 1 file changed, 22 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index da5af23..a9f3034 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4897,27 +4897,39 @@ static int valleyview_calc_cdclk(struct 
drm_i915_private *dev_priv,
 }
 
 /* compute the max pixel clock for new configuration */
-static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
+static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
+struct intel_crtc *mode_set_crtc,
+struct intel_crtc_state *crtc_new_state)
 {
struct drm_device *dev = dev_priv->dev;
struct intel_crtc *intel_crtc;
int max_pixclk = 0;
+   int pixclk;
 
for_each_intel_crtc(dev, intel_crtc) {
-   if (intel_crtc->new_enabled)
-   max_pixclk = max(max_pixclk,
-
intel_crtc->new_config->base.adjusted_mode.crtc_clock);
+   if (!intel_crtc->new_enabled)
+   continue;
+
+   if (intel_crtc == mode_set_crtc)
+   pixclk = crtc_new_state->base.adjusted_mode.crtc_clock;
+   else
+   pixclk = 
intel_crtc->config->base.adjusted_mode.crtc_clock;
+
+   max_pixclk = max(max_pixclk, pixclk);
}
 
return max_pixclk;
 }
 
 static void valleyview_modeset_global_pipes(struct drm_device *dev,
-   unsigned *prepare_pipes)
+   unsigned *prepare_pipes,
+   struct intel_crtc *mode_set_crtc,
+   struct intel_crtc_state 
*crtc_new_state)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc;
-   int max_pixclk = intel_mode_max_pixclk(dev_priv);
+   int max_pixclk =
+   intel_mode_max_pixclk(dev_priv, mode_set_crtc, crtc_new_state);
 
if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
dev_priv->vlv_cdclk_freq)
@@ -4932,7 +4944,7 @@ static void valleyview_modeset_global_pipes(struct 
drm_device *dev,
 static void valleyview_modeset_global_resources(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
-   int max_pixclk = intel_mode_max_pixclk(dev_priv);
+   int max_pixclk = intel_mode_max_pixclk(dev_priv, NULL, NULL);
int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
 
if (req_cdclk != dev_priv->vlv_cdclk_freq) {
@@ -10956,7 +10968,9 @@ static int __intel_set_mode(struct drm_crtc *crtc,
 * adjusted_mode bits in the crtc directly.
 */
if (IS_VALLEYVIEW(dev)) {
-   valleyview_modeset_global_pipes(dev, &prepare_pipes);
+   valleyview_modeset_global_pipes(dev, &prepare_pipes,
+   to_intel_crtc(crtc),
+   pipe_config);
 
/* may have added more to prepare_pipes than we should */
prepare_pipes &= ~disable_pipes;
-- 
1.9.1

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[Intel-gfx] [PATCH 6/8] drm/i915: Remove intel_crtc->new_config pointer

[Ander Conselvan de Oliveira]

There are no more users of that pointer since the new config is now
passed down the call chain during mode set. Also, when the switch to
atomic happens, the right config (state) should be derived from an
atomic state structure.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_display.c | 46 
 drivers/gpu/drm/i915/intel_drv.h |  1 -
 2 files changed, 10 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index a9f3034..a032a1d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8583,7 +8583,6 @@ retry:
 
intel_crtc = to_intel_crtc(crtc);
intel_crtc->new_enabled = true;
-   intel_crtc->new_config = &intel_crtc->config;
old->dpms_mode = connector->dpms;
old->load_detect_temp = true;
old->release_fb = NULL;
@@ -8623,10 +8622,6 @@ retry:
 
  fail:
intel_crtc->new_enabled = crtc->enabled;
-   if (intel_crtc->new_enabled)
-   intel_crtc->new_config = &intel_crtc->config;
-   else
-   intel_crtc->new_config = NULL;
 fail_unlock:
if (ret == -EDEADLK) {
drm_modeset_backoff(ctx);
@@ -8653,7 +8648,6 @@ void intel_release_load_detect_pipe(struct drm_connector 
*connector,
to_intel_connector(connector)->new_encoder = NULL;
intel_encoder->new_crtc = NULL;
intel_crtc->new_enabled = false;
-   intel_crtc->new_config = NULL;
intel_set_mode(crtc, NULL, 0, 0, NULL);
 
if (old->release_fb) {
@@ -9839,14 +9833,8 @@ static void 
intel_modeset_update_staged_output_state(struct drm_device *dev)
to_intel_crtc(encoder->base.crtc);
}
 
-   for_each_intel_crtc(dev, crtc) {
+   for_each_intel_crtc(dev, crtc)
crtc->new_enabled = crtc->base.enabled;
-
-   if (crtc->new_enabled)
-   crtc->new_config = &crtc->config;
-   else
-   crtc->new_config = NULL;
-   }
 }
 
 /**
@@ -10355,12 +10343,8 @@ intel_modeset_update_state(struct drm_device *dev, 
unsigned prepare_pipes)
intel_modeset_commit_output_state(dev);
 
/* Double check state. */
-   for_each_intel_crtc(dev, intel_crtc) {
+   for_each_intel_crtc(dev, intel_crtc)
WARN_ON(intel_crtc->base.enabled != 
intel_crtc_in_use(&intel_crtc->base));
-   WARN_ON(intel_crtc->new_config &&
-   intel_crtc->new_config != &intel_crtc->config);
-   WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
-   }
 
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
if (!connector->encoder || !connector->encoder->crtc)
@@ -10957,9 +10941,6 @@ static int __intel_set_mode(struct drm_crtc *crtc,
 
*saved_mode = crtc->mode;
 
-   if (modeset_pipes)
-   to_intel_crtc(crtc)->new_config = pipe_config;
-
/*
 * See if the config requires any additional preparation, e.g.
 * to adjust global state with pipes off.  We need to do this
@@ -10984,7 +10965,13 @@ static int __intel_set_mode(struct drm_crtc *crtc,
goto done;
 
for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
-   struct intel_crtc_state *state = intel_crtc->new_config;
+   struct intel_crtc_state *state;
+
+   if (&intel_crtc->base == crtc)
+   state = pipe_config;
+   else
+   state = intel_crtc->config;
+
ret = dev_priv->display.crtc_compute_clock(intel_crtc,
   state);
if (ret) {
@@ -11014,7 +11001,6 @@ static int __intel_set_mode(struct drm_crtc *crtc,
/* mode_set/enable/disable functions rely on a correct pipe
 * config. */
to_intel_crtc(crtc)->config = *pipe_config;
-   to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
 
/*
 * Calculate and store various constants which
@@ -11177,15 +11163,9 @@ static void intel_set_config_restore_state(struct 
drm_device *dev,
int count;
 
count = 0;
-   for_each_intel_crtc(dev, crtc) {
+   for_each_intel_crtc(dev, crtc)
crtc->new_enabled = config->save_crtc_enabled[count++];
 
-   if (crtc->new_enabled)
-   crtc->new_config = &crtc->config;
-   else
-   crtc->new_config = NULL;
-   }
-
count = 0;
for_each_intel_encoder(dev, encoder) {
encoder->new_crtc =
@@ -11391,11 +11371,6 @@ intel_modeset_stage_o

[Intel-gfx] [PATCH 1/8] drm/i915: Rename struct intel_crtc_config to intel_crtc_state

[Ander Conselvan de Oliveira]

The objective is to make this structure usable with the atomic helpers,
so let's start with the rename. Patch generated with coccinelle:

@@ @@
-struct intel_crtc_config
+struct intel_crtc_state

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/i915_drv.h  |   4 +-
 drivers/gpu/drm/i915/intel_crt.c |   6 +--
 drivers/gpu/drm/i915/intel_ddi.c |  10 ++--
 drivers/gpu/drm/i915/intel_display.c | 100 +--
 drivers/gpu/drm/i915/intel_dp.c  |  12 ++---
 drivers/gpu/drm/i915/intel_dp_mst.c  |   4 +-
 drivers/gpu/drm/i915/intel_drv.h |  28 +-
 drivers/gpu/drm/i915/intel_dsi.c |   4 +-
 drivers/gpu/drm/i915/intel_dvo.c |   6 +--
 drivers/gpu/drm/i915/intel_hdmi.c|   4 +-
 drivers/gpu/drm/i915/intel_lvds.c|   4 +-
 drivers/gpu/drm/i915/intel_panel.c   |   8 +--
 drivers/gpu/drm/i915/intel_pm.c  |   2 +-
 drivers/gpu/drm/i915/intel_sdvo.c|   6 +--
 drivers/gpu/drm/i915/intel_tv.c  |   4 +-
 15 files changed, 101 insertions(+), 101 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 11e85cb..7d60d38 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -458,7 +458,7 @@ struct drm_i915_error_state {
 
 struct intel_connector;
 struct intel_encoder;
-struct intel_crtc_config;
+struct intel_crtc_state;
 struct intel_plane_config;
 struct intel_crtc;
 struct intel_limit;
@@ -497,7 +497,7 @@ struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
 * fills out the pipe-config with the hw state. */
bool (*get_pipe_config)(struct intel_crtc *,
-   struct intel_crtc_config *);
+   struct intel_crtc_state *);
void (*get_plane_config)(struct intel_crtc *,
 struct intel_plane_config *);
int (*crtc_compute_clock)(struct intel_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index a9af9a4..675b85a 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -110,7 +110,7 @@ static unsigned int intel_crt_get_flags(struct 
intel_encoder *encoder)
 }
 
 static void intel_crt_get_config(struct intel_encoder *encoder,
-struct intel_crtc_config *pipe_config)
+struct intel_crtc_state *pipe_config)
 {
struct drm_device *dev = encoder->base.dev;
int dotclock;
@@ -126,7 +126,7 @@ static void intel_crt_get_config(struct intel_encoder 
*encoder,
 }
 
 static void hsw_crt_get_config(struct intel_encoder *encoder,
-  struct intel_crtc_config *pipe_config)
+  struct intel_crtc_state *pipe_config)
 {
intel_ddi_get_config(encoder, pipe_config);
 
@@ -303,7 +303,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
 }
 
 static bool intel_crt_compute_config(struct intel_encoder *encoder,
-struct intel_crtc_config *pipe_config)
+struct intel_crtc_state *pipe_config)
 {
struct drm_device *dev = encoder->base.dev;
 
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4e2e860..9d69b61 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -732,7 +732,7 @@ static int skl_calc_wrpll_link(struct drm_i915_private 
*dev_priv,
 
 
 static void skl_ddi_clock_get(struct intel_encoder *encoder,
-   struct intel_crtc_config *pipe_config)
+   struct intel_crtc_state *pipe_config)
 {
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
int link_clock = 0;
@@ -776,7 +776,7 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder,
 }
 
 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
 {
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
int link_clock = 0;
@@ -832,7 +832,7 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
 }
 
 void intel_ddi_clock_get(struct intel_encoder *encoder,
-struct intel_crtc_config *pipe_config)
+struct intel_crtc_state *pipe_config)
 {
hsw_ddi_clock_get(encoder, pipe_config);
 }
@@ -2022,7 +2022,7 @@ static void intel_ddi_hot_plug(struct intel_encoder 
*intel_encoder)
 }
 
 void intel_ddi_get_config(struct intel_encoder *encoder,
- struct intel_crtc_config *pipe_config)
+ struct intel_crtc_state *pipe_config)
 {
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc

[Intel-gfx] [PATCH 4/8] drm/i915: Use local pipe_config varariable when available

[Ander Conselvan de Oliveira]

In function that define a local pipe_config variable to point to
crtc->config, replace remaining references to crtc->config with
the local variable. This makes the code more consistent and easier
to change in an automated manner.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_display.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3bceacb..da5af23 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4602,7 +4602,7 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc_state *pipe_config = &crtc->config;
 
-   if (!crtc->config.gmch_pfit.control)
+   if (!pipe_config->gmch_pfit.control)
return;
 
/*
@@ -5925,7 +5925,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
 0x00df);
 
-   if (crtc->config.has_dp_encoder) {
+   if (pipe_config->has_dp_encoder) {
/* Use SSC source */
if (pipe == PIPE_A)
vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
@@ -7541,7 +7541,7 @@ static void intel_cpu_transcoder_get_m_n(struct 
intel_crtc *crtc,
 void intel_dp_get_m_n(struct intel_crtc *crtc,
  struct intel_crtc_state *pipe_config)
 {
-   if (crtc->config.has_pch_encoder)
+   if (pipe_config->has_pch_encoder)
intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
else
intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
-- 
1.9.1

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[Intel-gfx] [PATCH 3/8] drm/i915: Pass new_config down do crtc_compute_clock

[Ander Conselvan de Oliveira]

This reduces the number of direct users of crtc->new_config. At some
point we'll be able to get rid of that pointer altogether, in favor
of drm core state structs.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/i915_drv.h  |   3 +-
 drivers/gpu/drm/i915/intel_ddi.c |  29 
 drivers/gpu/drm/i915/intel_display.c | 131 +++
 drivers/gpu/drm/i915/intel_drv.h |   6 +-
 4 files changed, 94 insertions(+), 75 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7d60d38..c1a9af9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -500,7 +500,8 @@ struct drm_i915_display_funcs {
struct intel_crtc_state *);
void (*get_plane_config)(struct intel_crtc *,
 struct intel_plane_config *);
-   int (*crtc_compute_clock)(struct intel_crtc *crtc);
+   int (*crtc_compute_clock)(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state);
void (*crtc_enable)(struct drm_crtc *crtc);
void (*crtc_disable)(struct drm_crtc *crtc);
void (*off)(struct drm_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 79c9776..970ca30 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -904,6 +904,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 
 static bool
 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
+  struct intel_crtc_state *crtc_state,
   struct intel_encoder *intel_encoder,
   int clock)
 {
@@ -918,16 +919,16 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
  WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
  WRPLL_DIVIDER_POST(p);
 
-   intel_crtc->new_config->dpll_hw_state.wrpll = val;
+   crtc_state->dpll_hw_state.wrpll = val;
 
-   pll = intel_get_shared_dpll(intel_crtc);
+   pll = intel_get_shared_dpll(intel_crtc, crtc_state);
if (pll == NULL) {
DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
 pipe_name(intel_crtc->pipe));
return false;
}
 
-   intel_crtc->new_config->ddi_pll_sel = 
PORT_CLK_SEL_WRPLL(pll->id);
+   crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
}
 
return true;
@@ -1090,6 +1091,7 @@ found:
 
 static bool
 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
+  struct intel_crtc_state *crtc_state,
   struct intel_encoder *intel_encoder,
   int clock)
 {
@@ -1139,11 +1141,11 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
} else /* eDP */
return true;
 
-   intel_crtc->new_config->dpll_hw_state.ctrl1 = ctrl1;
-   intel_crtc->new_config->dpll_hw_state.cfgcr1 = cfgcr1;
-   intel_crtc->new_config->dpll_hw_state.cfgcr2 = cfgcr2;
+   crtc_state->dpll_hw_state.ctrl1 = ctrl1;
+   crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
+   crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
 
-   pll = intel_get_shared_dpll(intel_crtc);
+   pll = intel_get_shared_dpll(intel_crtc, crtc_state);
if (pll == NULL) {
DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
 pipe_name(intel_crtc->pipe));
@@ -1151,7 +1153,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
}
 
/* shared DPLL id 0 is DPLL 1 */
-   intel_crtc->new_config->ddi_pll_sel = pll->id + 1;
+   crtc_state->ddi_pll_sel = pll->id + 1;
 
return true;
 }
@@ -1163,17 +1165,20 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
  * For private DPLLs, compute_config() should do the selection for us. This
  * function should be folded into compute_config() eventually.
  */
-bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
+bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state)
 {
struct drm_device *dev = intel_crtc->base.dev;
struct intel_encoder *intel_encoder =
intel_ddi_get_crtc_new_encoder(intel_crtc);
-   int clock = intel_crtc->new_config->port_clock;
+   int clock = crtc_state->port_clock;
 
if (IS_SKYLAKE(dev))
-   return skl_ddi_pll_select(intel_crtc, intel_encoder, clock);
+   return skl_ddi_pll_select(intel_crtc, crtc_state,
+ intel_encoder, clock);
else
-   return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock);
+   return hsw_ddi_pll_select(intel_crtc, crtc_state,
+ intel_encoder, clock);
 }
 
 void intel_ddi_set_pipe_settings(struct 

[Intel-gfx] [PATCH 2/8] drm/i915: Embedded struct drm_crtc_state in intel_crtc_state

[Ander Conselvan de Oliveira]

And get rid of the duplicate mode structures. The bulk of the patch
was generated with the following semantic patch.

@@ struct intel_crtc_state *state; @@
-state->adjusted_mode
+state->base.adjusted_mode
@@ struct intel_crtc_state *state; @@
-state->requested_mode
+state->base.mode
@@ struct intel_crtc_state state; @@
-state.adjusted_mode
+state.base.adjusted_mode
@@ struct intel_crtc_state state; @@
-state.requested_mode
+state.base.mode

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/i915_irq.c  |   8 +-
 drivers/gpu/drm/i915/intel_audio.c   |   2 +-
 drivers/gpu/drm/i915/intel_crt.c |  10 +--
 drivers/gpu/drm/i915/intel_ddi.c |  18 ++---
 drivers/gpu/drm/i915/intel_display.c | 147 ++-
 drivers/gpu/drm/i915/intel_dp.c  |   8 +-
 drivers/gpu/drm/i915/intel_dp_mst.c  |   4 +-
 drivers/gpu/drm/i915/intel_drv.h |  12 +--
 drivers/gpu/drm/i915/intel_dsi.c |   8 +-
 drivers/gpu/drm/i915/intel_dvo.c |  12 +--
 drivers/gpu/drm/i915/intel_fbdev.c   |   8 +-
 drivers/gpu/drm/i915/intel_hdmi.c|  16 ++--
 drivers/gpu/drm/i915/intel_lvds.c|   8 +-
 drivers/gpu/drm/i915/intel_panel.c   |   8 +-
 drivers/gpu/drm/i915/intel_pm.c  |  30 +++
 drivers/gpu/drm/i915/intel_psr.c |   2 +-
 drivers/gpu/drm/i915/intel_sdvo.c|  12 +--
 drivers/gpu/drm/i915/intel_sprite.c  |   2 +-
 drivers/gpu/drm/i915/intel_tv.c  |   6 +-
 19 files changed, 157 insertions(+), 164 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 08a5a4b..11e209e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -567,7 +567,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, 
int pipe)
struct intel_crtc *intel_crtc =
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
const struct drm_display_mode *mode =
-   &intel_crtc->config.adjusted_mode;
+   &intel_crtc->config.base.adjusted_mode;
 
htotal = mode->crtc_htotal;
hsync_start = mode->crtc_hsync_start;
@@ -638,7 +638,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc 
*crtc)
 {
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
+   const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
enum pipe pipe = crtc->pipe;
int position, vtotal;
 
@@ -665,7 +665,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, 
int pipe,
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-   const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
+   const struct drm_display_mode *mode = 
&intel_crtc->config.base.adjusted_mode;
int position;
int vbl_start, vbl_end, hsync_start, htotal, vtotal;
bool in_vbl = true;
@@ -823,7 +823,7 @@ static int i915_get_vblank_timestamp(struct drm_device 
*dev, int pipe,
return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 vblank_time, flags,
 crtc,
-
&to_intel_crtc(crtc)->config.adjusted_mode);
+
&to_intel_crtc(crtc)->config.base.adjusted_mode);
 }
 
 static bool intel_hpd_irq_event(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_audio.c 
b/drivers/gpu/drm/i915/intel_audio.c
index 2c7ed5c..fe8c496 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -397,7 +397,7 @@ void intel_audio_codec_enable(struct intel_encoder 
*intel_encoder)
 {
struct drm_encoder *encoder = &intel_encoder->base;
struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
-   struct drm_display_mode *mode = &crtc->config.adjusted_mode;
+   struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
struct drm_connector *connector;
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 675b85a..e4f6d49 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -115,14 +115,14 @@ static void intel_crt_get_config(struct intel_encoder 
*encoder,
struct drm_device *dev = encoder->base.dev;
int dotclock;
 
-   pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
+   pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 
dotclock = pipe_config->port_clock;
 
if (HAS_PCH_SPLIT

[Intel-gfx] [PATCH 7/8] drm/i915: Make intel_crtc->config a pointer

[Ander Conselvan de Oliveira]

To match the semantics of drm_crtc->state, which this will eventually
become.

@@ struct intel_crtc *crtc; @@
-&crtc->config
+crtc->config
@@ struct intel_crtc *crtc; identifier member; @@
-crtc->config.member
+crtc->config->member
@@ struct drm_crtc *crtc; @@
-&to_intel_crtc(crtc)->config
+to_intel_crtc(crtc)->config
@@ struct drm_crtc *crtc; identifier member; @@
-to_intel_crtc(crtc)->config.member
+to_intel_crtc(crtc)->config->member

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/i915_debugfs.c  |  12 +-
 drivers/gpu/drm/i915/i915_irq.c  |   8 +-
 drivers/gpu/drm/i915/intel_audio.c   |   2 +-
 drivers/gpu/drm/i915/intel_crt.c |   2 +-
 drivers/gpu/drm/i915/intel_ddi.c |  52 +++
 drivers/gpu/drm/i915/intel_display.c | 275 ++-
 drivers/gpu/drm/i915/intel_dp.c  |  16 +-
 drivers/gpu/drm/i915/intel_dp_mst.c  |   7 +-
 drivers/gpu/drm/i915/intel_drv.h |   2 +-
 drivers/gpu/drm/i915/intel_dsi.c |   8 +-
 drivers/gpu/drm/i915/intel_dvo.c |   8 +-
 drivers/gpu/drm/i915/intel_fbdev.c   |  10 +-
 drivers/gpu/drm/i915/intel_hdmi.c|  36 ++---
 drivers/gpu/drm/i915/intel_lvds.c|   6 +-
 drivers/gpu/drm/i915/intel_overlay.c |   2 +-
 drivers/gpu/drm/i915/intel_pm.c  |  56 +++
 drivers/gpu/drm/i915/intel_psr.c |   8 +-
 drivers/gpu/drm/i915/intel_sdvo.c|  14 +-
 drivers/gpu/drm/i915/intel_sprite.c  |   2 +-
 19 files changed, 270 insertions(+), 256 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index d0e445e..a724e8c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2572,7 +2572,7 @@ static int i915_display_info(struct seq_file *m, void 
*unused)
 
seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
   crtc->base.base.id, pipe_name(crtc->pipe),
-  yesno(crtc->active), crtc->config.pipe_src_w, 
crtc->config.pipe_src_h);
+  yesno(crtc->active), crtc->config->pipe_src_w, 
crtc->config->pipe_src_h);
if (crtc->active) {
intel_crtc_info(m, crtc);
 
@@ -3280,9 +3280,9 @@ static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device 
*dev)
 * relevant on hsw with pipe A when using the always-on power well
 * routing.
 */
-   if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&
-   !crtc->config.pch_pfit.enabled) {
-   crtc->config.pch_pfit.force_thru = true;
+   if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
+   !crtc->config->pch_pfit.enabled) {
+   crtc->config->pch_pfit.force_thru = true;
 
intel_display_power_get(dev_priv,
POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
@@ -3306,8 +3306,8 @@ static void hsw_undo_trans_edp_pipe_A_crc_wa(struct 
drm_device *dev)
 * relevant on hsw with pipe A when using the always-on power well
 * routing.
 */
-   if (crtc->config.pch_pfit.force_thru) {
-   crtc->config.pch_pfit.force_thru = false;
+   if (crtc->config->pch_pfit.force_thru) {
+   crtc->config->pch_pfit.force_thru = false;
 
dev_priv->display.crtc_disable(&crtc->base);
dev_priv->display.crtc_enable(&crtc->base);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 11e209e..e55b275 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -567,7 +567,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, 
int pipe)
struct intel_crtc *intel_crtc =
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
const struct drm_display_mode *mode =
-   &intel_crtc->config.base.adjusted_mode;
+   &intel_crtc->config->base.adjusted_mode;
 
htotal = mode->crtc_htotal;
hsync_start = mode->crtc_hsync_start;
@@ -638,7 +638,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc 
*crtc)
 {
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
-   const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;
+   const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
enum pipe pipe = crtc->pipe;
int position, vtotal;
 
@@ -665,7 +665,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, 
int pipe,
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-   const struct drm_display_mode *mode = 
&intel_crtc->config.base.adjusted_mode;
+   const struct drm_display_mode *mode = 
&intel_crtc->config->base.adjusted_mode;
int position;
 

[Intel-gfx] [PATCH 8/8] drm/i915: Keep drm_crtc->state in sync with intel_crtc->config

[Ander Conselvan de Oliveira]

So that atomic operations will reference the right crtc state.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_display.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 462f22a..20b9e9b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10926,6 +10926,7 @@ static void intel_crtc_set_state(struct intel_crtc 
*crtc,
 {
kfree(crtc->config);
crtc->config = crtc_state;
+   crtc->base.state = &crtc_state->base;
 }
 
 static int __intel_set_mode(struct drm_crtc *crtc,
-- 
1.9.1

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[Intel-gfx] [PATCH v2] drm/i915/bdw: Enable execlists by default where supported

[Thomas Daniel]

Execlist support in the i915 driver is now considered good enough for the
feature to be enabled by default on Gen8 and later and routinely tested.
Adjusted i915 parameters structure initialization to reflect this and updated
the comment in intel_sanitize_enable_execlists().

v2: Update the MODULE_PARM_DESC too.

Issue: VIZ-2020
Signed-off-by: Thomas Daniel 
---
 drivers/gpu/drm/i915/i915_params.c |4 ++--
 drivers/gpu/drm/i915/intel_lrc.c   |3 +--
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index c91cb20..f6af6d4 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -35,7 +35,7 @@ struct i915_params i915 __read_mostly = {
.vbt_sdvo_panel_type = -1,
.enable_rc6 = -1,
.enable_fbc = -1,
-   .enable_execlists = 0,
+   .enable_execlists = -1,
.enable_hangcheck = true,
.enable_ppgtt = -1,
.enable_psr = 0,
@@ -122,7 +122,7 @@ MODULE_PARM_DESC(enable_ppgtt,
 module_param_named(enable_execlists, i915.enable_execlists, int, 0400);
 MODULE_PARM_DESC(enable_execlists,
"Override execlists usage. "
-   "(-1=auto, 0=disabled [default], 1=enabled)");
+   "(-1=auto [default], 0=disabled, 1=enabled)");
 
 module_param_named(enable_psr, i915.enable_psr, int, 0600);
 MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 89b5577..4dc6d42 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -212,8 +212,7 @@ static int intel_lr_context_pin(struct intel_engine_cs 
*ring,
  * @enable_execlists: value of i915.enable_execlists module parameter.
  *
  * Only certain platforms support Execlists (the prerequisites being
- * support for Logical Ring Contexts and Aliasing PPGTT or better),
- * and only when enabled via module parameter.
+ * support for Logical Ring Contexts and Aliasing PPGTT or better).
  *
  * Return: 1 if Execlists is supported and has to be enabled.
  */
-- 
1.7.9.5

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Re: [Intel-gfx] [PATCH 8/8] drm/i915: Keep drm_crtc->state in sync with intel_crtc->config

[shuang . he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: 
shuang...@intel.com)
-Summary-
Platform  Delta  drm-intel-nightly  Series Applied
PNV  364/364  364/364
ILK  +1-6  364/366  359/366
SNB  448/450  448/450
IVB  497/498  497/498
BYT  289/289  289/289
HSW  563/564  563/564
BDW  417/417  417/417
-Detailed-
Platform  Testdrm-intel-nightly  Series 
Applied
*ILK  igt_kms_pipe_crc_basic_bad-source  PASS(3, M26)  DMESG_WARN(1, 
M26)
*ILK  igt_kms_setmode_invalid-clone-exclusive-crtc  PASS(5, M26)  
DMESG_WARN(1, M26)
*ILK  igt_kms_flip_rcs-wf_vblank-vs-dpms-interruptible  PASS(7, M26)  
DMESG_WARN(1, M26)
*ILK  igt_kms_render_direct-render  PASS(7, M26)  DMESG_WARN(1, M26)
*ILK  igt_kms_flip_flip-vs-panning  DMESG_WARN(1, M26)PASS(7, M26)  
NSPT(1, M26)
 ILK  igt_kms_flip_plain-flip-fb-recreate-interruptible  DMESG_WARN(1, 
M26)PASS(3, M26)  DMESG_WARN(1, M26)
 ILK  igt_kms_flip_wf_vblank-ts-check  DMESG_WARN(7, M26)PASS(22, M26M37)   
   PASS(1, M26)
Note: You need to pay more attention to line start with '*'
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Re: [Intel-gfx] [PATCH 4/8] drm/i915: Reduce duplicated forcewake logic

[Deepak S]

On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:

From: Chris Wilson 

Introduce a structure to track the individual forcewake domains and use
that to eliminate duplicate logic.

v2: - Rebase on latest dinq (Mika)
 - for_each_fw_domain macro (Mika)
 - Handle reset atomically, keeping the timer running (Mika)
 - for_each_fw_domain parameter ordering (Chris)
 - defer timer on new register access (Mika)

Signed-off-by: Chris Wilson  (v1)
Signed-off-by: Mika Kuoppala 
---
  drivers/gpu/drm/i915/i915_debugfs.c |  65 +++---
  drivers/gpu/drm/i915/i915_drv.h |  54 +++--
  drivers/gpu/drm/i915/intel_uncore.c | 410 +---
  3 files changed, 208 insertions(+), 321 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index e142629..5cc838b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1235,14 +1235,36 @@ static int ironlake_drpc_info(struct seq_file *m)
return 0;
  }
  
-static int vlv_drpc_info(struct seq_file *m)

+static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
  {
+   struct drm_info_node *node = m->private;
+   struct drm_device *dev = node->minor->dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   struct intel_uncore_forcewake_domain *fw_domain;
+   const char *domain_names[] = {
+   "render",
+   "blitter",
+   "media",
+   };
+   int i;
+
+   spin_lock_irq(&dev_priv->uncore.lock);
+   for_each_fw_domain(fw_domain, dev_priv, i) {
+   seq_printf(m, "%s.wake_count = %u\n",
+  domain_names[i],
+  fw_domain->wake_count);
+   }
+   spin_unlock_irq(&dev_priv->uncore.lock);
  
+	return 0;

+}
+
+static int vlv_drpc_info(struct seq_file *m)
+{
struct drm_info_node *node = m->private;
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
u32 rpmodectl1, rcctl1, pw_status;
-   unsigned fw_rendercount = 0, fw_mediacount = 0;
  
  	intel_runtime_pm_get(dev_priv);
  
@@ -1274,22 +1296,11 @@ static int vlv_drpc_info(struct seq_file *m)

seq_printf(m, "Media RC6 residency since boot: %u\n",
   I915_READ(VLV_GT_MEDIA_RC6));
  
-	spin_lock_irq(&dev_priv->uncore.lock);

-   fw_rendercount = dev_priv->uncore.fw_rendercount;
-   fw_mediacount = dev_priv->uncore.fw_mediacount;
-   spin_unlock_irq(&dev_priv->uncore.lock);
-
-   seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
-   seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
-
-
-   return 0;
+   return i915_gen6_forcewake_count_info(m, NULL);
  }
  
-

  static int gen6_drpc_info(struct seq_file *m)
  {
-
struct drm_info_node *node = m->private;
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1303,7 +1314,7 @@ static int gen6_drpc_info(struct seq_file *m)
intel_runtime_pm_get(dev_priv);
  
  	spin_lock_irq(&dev_priv->uncore.lock);

-   forcewake_count = dev_priv->uncore.forcewake_count;
+   forcewake_count = 
dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
spin_unlock_irq(&dev_priv->uncore.lock);
  
  	if (forcewake_count) {

@@ -1931,30 +1942,6 @@ static int i915_execlists(struct seq_file *m, void *data)
return 0;
  }
  
-static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)

-{
-   struct drm_info_node *node = m->private;
-   struct drm_device *dev = node->minor->dev;
-   struct drm_i915_private *dev_priv = dev->dev_private;
-   unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
-
-   spin_lock_irq(&dev_priv->uncore.lock);
-   if (IS_VALLEYVIEW(dev)) {
-   fw_rendercount = dev_priv->uncore.fw_rendercount;
-   fw_mediacount = dev_priv->uncore.fw_mediacount;
-   } else
-   forcewake_count = dev_priv->uncore.forcewake_count;
-   spin_unlock_irq(&dev_priv->uncore.lock);
-
-   if (IS_VALLEYVIEW(dev)) {
-   seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
-   seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
-   } else
-   seq_printf(m, "forcewake count = %u\n", forcewake_count);
-
-   return 0;
-}
-
  static const char *swizzle_string(unsigned swizzle)
  {
switch (swizzle) {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 95dfa2d..410558a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -554,20 +554,45 @@ struct intel_uncore_funcs {
uint64_t val, bool trace);
  };
  
+enum {

+   FW_DOMAIN_ID_RENDER = 0,
+   FW_DOMAIN_ID_BLITTER,
+   FW_DOMAIN_ID_MEDIA,
+
+   FW_DOMAIN_ID_CO

[Intel-gfx] lib: Fix out of tree build of version.h

[Lahtinen, Joonas]

Currently out of tree build fails because the version.h.tmp is generated
into the source directory instead of the build directory where it is
later looked for. This commit fixes it.

From 2c0617e21101d69e7219c6660936c0015f93f8ee Mon Sep 17 00:00:00 2001
From: Joonas Lahtinen 
Date: Thu, 11 Dec 2014 15:05:11 +0200
Subject: [PATCH] lib: Fix out of tree build of version.h

Write the version.h.tmp file into the build directory instead of source
directory. This allows out of tree building when those two are not the
same.

Signed-off-by: Joonas Lahtinen 
---
 lib/Makefile.sources |   12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 819b21a..34a3d31 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -55,16 +55,16 @@ libintel_tools_la_SOURCES = \
 $(IGT_LIB_PATH)/version.h.tmp:
@touch $@
@if test -d $(GPU_TOOLS_PATH)/.git; then \
-   if which git > /dev/null 2>&1; then cd $(@D); \
+   if which git > /dev/null 2>&1; then \
+   cd $(GPU_TOOLS_PATH); \
git log -n 1 --oneline | \
-   sed 's/^\([^ ]*\) .*/#define IGT_GIT_SHA1 "g\1"/' \
-   >> $(@F) ; \
+   sed 's/^\([^ ]*\) .*/#define IGT_GIT_SHA1 "g\1"/' ; \
else \
-   echo '#define IGT_GIT_SHA1 "NO-GIT"' >> $@ ; \
+   echo '#define IGT_GIT_SHA1 "NO-GIT"' ; \
fi \
else \
-   echo '#define IGT_GIT_SHA1 "NOT-GIT"' >> $@ ; \
-   fi
+   echo '#define IGT_GIT_SHA1 "NOT-GIT"' ; \
+   fi >> $@
 
 
 $(IGT_LIB_PATH)/version.h: $(IGT_LIB_PATH)/version.h.tmp
-- 
1.7.9.5
-
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[Intel-gfx] lib: Fix out of tree build of version.h

[Joonas Lahtinen]

Currently out of tree build fails because the version.h.tmp is generated
into the source directory instead of the build directory where it is
later looked for. This commit fixes it.

From 2c0617e21101d69e7219c6660936c0015f93f8ee Mon Sep 17 00:00:00 2001
From: Joonas Lahtinen 
Date: Thu, 11 Dec 2014 15:05:11 +0200
Subject: [PATCH] lib: Fix out of tree build of version.h

Write the version.h.tmp file into the build directory instead of source
directory. This allows out of tree building when those two are not the
same.

Signed-off-by: Joonas Lahtinen 
---
 lib/Makefile.sources |   12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 819b21a..34a3d31 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -55,16 +55,16 @@ libintel_tools_la_SOURCES = \
 $(IGT_LIB_PATH)/version.h.tmp:
@touch $@
@if test -d $(GPU_TOOLS_PATH)/.git; then \
-   if which git > /dev/null 2>&1; then cd $(@D); \
+   if which git > /dev/null 2>&1; then \
+   cd $(GPU_TOOLS_PATH); \
git log -n 1 --oneline | \
-   sed 's/^\([^ ]*\) .*/#define IGT_GIT_SHA1 "g\1"/' \
-   >> $(@F) ; \
+   sed 's/^\([^ ]*\) .*/#define IGT_GIT_SHA1 "g\1"/' ; \
else \
-   echo '#define IGT_GIT_SHA1 "NO-GIT"' >> $@ ; \
+   echo '#define IGT_GIT_SHA1 "NO-GIT"' ; \
fi \
else \
-   echo '#define IGT_GIT_SHA1 "NOT-GIT"' >> $@ ; \
-   fi
+   echo '#define IGT_GIT_SHA1 "NOT-GIT"' ; \
+   fi >> $@
 
 
 $(IGT_LIB_PATH)/version.h: $(IGT_LIB_PATH)/version.h.tmp
-- 
1.7.9.5

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Re: [Intel-gfx] [PATCH 5/8] drm/i915: Consolidate forcewake code

[Deepak S]

On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:

As we now have forcewake domains, take advantage of it
by putting the differences in gen fw handling in data rather
than in code.

In past we have opencoded this quite extensively as the fw handling
is in the fast path. There has also been a lot of cargo-culted
copy'n'pasting from older gens to newer ones.

Now when the releasing of the forcewake is done by deferred timer,
it gives chance to consolidate more. Due to the frequency of actual hw
access being significantly less.

Take advantage of this and generalize the fw handling code
as much as possible. But we still aim to keep the forcewake sequence
particularities for each gen intact. So the access pattern
to fw engines should remain the same.

v2: - s/old_ack/clear_ack (Chris)
 - s/post_read/posting_read (Chris)
 - less polite commit msg (Chris)

Signed-off-by: Mika Kuoppala 
---
  drivers/gpu/drm/i915/i915_debugfs.c |   7 +-
  drivers/gpu/drm/i915/i915_drv.h |   7 +
  drivers/gpu/drm/i915/intel_uncore.c | 469 
  3 files changed, 212 insertions(+), 271 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5cc838b..93390c9 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1241,17 +1241,12 @@ static int i915_gen6_forcewake_count_info(struct 
seq_file *m, void *data)
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_uncore_forcewake_domain *fw_domain;
-   const char *domain_names[] = {
-   "render",
-   "blitter",
-   "media",
-   };
int i;
  
  	spin_lock_irq(&dev_priv->uncore.lock);

for_each_fw_domain(fw_domain, dev_priv, i) {
seq_printf(m, "%s.wake_count = %u\n",
-  domain_names[i],
+  intel_uncore_forcewake_domain_to_str(i),
   fw_domain->wake_count);
}
spin_unlock_irq(&dev_priv->uncore.lock);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 410558a..4263084 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -575,6 +575,12 @@ struct intel_uncore {
int id;
unsigned wake_count;
struct timer_list timer;
+   u32 reg_set;
+   u32 val_set;
+   u32 val_clear;
+   u32 reg_ack;
+   u32 reg_post;
+   u32 val_reset;
} fw_domain[FW_DOMAIN_ID_COUNT];
  #define FORCEWAKE_RENDER  (1 << FW_DOMAIN_ID_RENDER)
  #define FORCEWAKE_BLITTER (1 << FW_DOMAIN_ID_BLITTER)
@@ -2443,6 +2449,7 @@ extern void intel_uncore_init(struct drm_device *dev);
  extern void intel_uncore_check_errors(struct drm_device *dev);
  extern void intel_uncore_fini(struct drm_device *dev);
  extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool 
restore);
+const char *intel_uncore_forcewake_domain_to_str(const int domain_id);
  
  void

  i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 85e46b0..e883790 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -42,6 +42,26 @@
  
  #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
  
+static const char * const forcewake_domain_names[] = {

+   "render",
+   "blitter",
+   "media",
+};
+
+const char *
+intel_uncore_forcewake_domain_to_str(const int id)
+{
+   BUILD_BUG_ON((sizeof(forcewake_domain_names)/sizeof(const char *)) !=
+FW_DOMAIN_ID_COUNT);
+
+   if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
+   return forcewake_domain_names[id];
+
+   WARN_ON(id);
+
+   return "unknown";
+}
+
  static void
  assert_device_not_suspended(struct drm_i915_private *dev_priv)
  {
@@ -49,73 +69,123 @@ assert_device_not_suspended(struct drm_i915_private 
*dev_priv)
  "Device suspended\n");
  }
  
-static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)

+static inline void
+fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
  {
-   /* w/a for a sporadic read returning 0 by waiting for the GT
-* thread to wake up.
-*/
-   if (wait_for_atomic_us((__raw_i915_read32(dev_priv, 
GEN6_GT_THREAD_STATUS_REG) &
-   GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
-   DRM_ERROR("GT thread status wait timed out\n");
+   __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
  }
  
-static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)

+static inline void
+fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
  {
-   __raw_i915_w

Re: [Intel-gfx] [PATCH 6/8] drm/i915: Make vlv and chv forcewake put generic.

[Deepak S]

On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:

These two were using a fw dance logic where posting read was done
after both domain bit were set. When in other gens, the posting
read is done immediately after setting the forcewake bit for each
domain.

Now bring these in line with other gens.

Signed-off-by: Mika Kuoppala 
---
  drivers/gpu/drm/i915/intel_uncore.c | 16 +---
  1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index e883790..8021bec 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -232,16 +232,6 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private 
*dev_priv)
return ret;
  }
  
-static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,

-int fw_engine)
-{
-   fw_domains_put(dev_priv, fw_engine);
-   fw_domains_posting_read(dev_priv);
-
-   if (!IS_CHERRYVIEW(dev_priv->dev))
-   gen6_gt_check_fifodbg(dev_priv);
-}
-
  static void gen6_force_wake_timer(unsigned long arg)
  {
struct intel_uncore_forcewake_domain *domain = (void *)arg;
@@ -958,7 +948,11 @@ void intel_uncore_init(struct drm_device *dev)
   FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
} else if (IS_VALLEYVIEW(dev)) {
dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
-   dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
+   if (!IS_CHERRYVIEW(dev))
+   dev_priv->uncore.funcs.force_wake_put =
+   fw_domains_put_with_fifo;
+   else
+   dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
   FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,


Looks fine
Reviewed-by: Deepak S

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Re: [Intel-gfx] [PATCH 7/8] drm/i915: Rename the forcewake get/put functions

[Deepak S]

On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:

We have multiple forcewake domains now on recent gens. Change the
function naming to reflect this.

v2: More verbose names (Chris)

Signed-off-by: Mika Kuoppala 
---
  drivers/gpu/drm/i915/i915_debugfs.c |  8 
  drivers/gpu/drm/i915/i915_drv.c |  2 +-
  drivers/gpu/drm/i915/i915_drv.h | 15 +--
  drivers/gpu/drm/i915/intel_display.c|  4 ++--
  drivers/gpu/drm/i915/intel_lrc.c|  4 ++--
  drivers/gpu/drm/i915/intel_pm.c | 28 ++--
  drivers/gpu/drm/i915/intel_ringbuffer.c |  4 ++--
  drivers/gpu/drm/i915/intel_uncore.c | 18 +-
  8 files changed, 39 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 93390c9..ecc4b42 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1052,7 +1052,7 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
if (ret)
goto out;
  
-		gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);

+   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
  
  		reqf = I915_READ(GEN6_RPNSWREQ);

reqf &= ~GEN6_TURBO_DISABLE;
@@ -1079,7 +1079,7 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
cagf *= GT_FREQUENCY_MULTIPLIER;
  
-		gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);

+   intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
mutex_unlock(&dev->struct_mutex);
  
  		if (IS_GEN6(dev) || IS_GEN7(dev)) {

@@ -4233,7 +4233,7 @@ static int i915_forcewake_open(struct inode *inode, 
struct file *file)
return 0;
  
  	intel_runtime_pm_get(dev_priv);

-   gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
  
  	return 0;

  }
@@ -4246,7 +4246,7 @@ static int i915_forcewake_release(struct inode *inode, 
struct file *file)
if (INTEL_INFO(dev)->gen < 6)
return 0;
  
-	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);

+   intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
intel_runtime_pm_put(dev_priv);
  
  	return 0;

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 706b122..011caa2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1362,7 +1362,7 @@ static int intel_runtime_suspend(struct device *device)
if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
return -ENODEV;
  
-	assert_force_wake_inactive(dev_priv);

+   assert_forcewakes_inactive(dev_priv);
  
  	DRM_DEBUG_KMS("Suspending device\n");
  
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h

index 4263084..a2a8536 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2450,6 +2450,11 @@ extern void intel_uncore_check_errors(struct drm_device 
*dev);
  extern void intel_uncore_fini(struct drm_device *dev);
  extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool 
restore);
  const char *intel_uncore_forcewake_domain_to_str(const int domain_id);
+void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
+   unsigned fw_domains);
+void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
+   unsigned fw_domains);
+void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
  
  void

  i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
@@ -3026,16 +3031,6 @@ extern void intel_display_print_error_state(struct 
drm_i915_error_state_buf *e,
struct drm_device *dev,
struct intel_display_error_state 
*error);
  
-/* On SNB platform, before reading ring registers forcewake bit

- * must be set to prevent GT core from power down and stale values being
- * returned.
- */
-void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
-   unsigned fw_domains);
-void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
-   unsigned fw_domains);
-void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
-
  int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 
*val);
  int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 
val);
  
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c

index 86c2885..d2d60f0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7863,7 +7863,7 @@ static void hsw_restore_lcpll(struct drm_i915_private 
*dev_priv)
 * Make sure we're not on PC8 state before disabling PC8, otherwi

[Intel-gfx] [PATCH 1/5] drm/i915/opregion: use BUILD_BUG_ON to verify mailbox struct sizes

[Jani Nikula]

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/intel_opregion.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_opregion.c 
b/drivers/gpu/drm/i915/intel_opregion.c
index d8de1d5140a7..bce9bbe05549 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -864,6 +864,11 @@ int intel_opregion_setup(struct drm_device *dev)
char buf[sizeof(OPREGION_SIGNATURE)];
int err = 0;
 
+   BUILD_BUG_ON(sizeof(struct opregion_header) != 0x100);
+   BUILD_BUG_ON(sizeof(struct opregion_acpi) != 0x100);
+   BUILD_BUG_ON(sizeof(struct opregion_swsci) != 0x100);
+   BUILD_BUG_ON(sizeof(struct opregion_asle) != 0x100);
+
pci_read_config_dword(dev->pdev, PCI_ASLS, &asls);
DRM_DEBUG_DRIVER("graphic opregion physical addr: 0x%x\n", asls);
if (asls == 0) {
-- 
2.1.3

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[Intel-gfx] [PATCH 0/5] drm/i915/opregion updates

[Jani Nikula]

Hi all, here's a few updates to opregion. Patches 1-4 should be pretty
trivial and not do anything drastic. Patch 5 starts using the extended
DIDL, but I doubt it will make a huge difference anyway. It might prove
to be useful prep stuff for adding more sense to our CADL handling.

BR,
Jani.


Jani Nikula (5):
  drm/i915/opregion: use BUILD_BUG_ON to verify mailbox struct sizes
  drm/i915/opregion: add new opregion stuff
  drm/i915/opregion: prefer DRM logging functions over pr_warn and
dev_dbg
  drm/i915/opregion: abstract didl and did2 getter and setter
  drm/i915/opregion: start using extended didl

 drivers/gpu/drm/i915/intel_opregion.c | 104 +-
 1 file changed, 78 insertions(+), 26 deletions(-)

-- 
2.1.3

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[Intel-gfx] [PATCH 2/5] drm/i915/opregion: add new opregion stuff

[Jani Nikula]

Inluding extended didl and cpdl fields

Present since opregion version 3.0.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/intel_opregion.c | 15 ---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_opregion.c 
b/drivers/gpu/drm/i915/intel_opregion.c
index bce9bbe05549..10c60199029d 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -53,6 +53,7 @@
 #define MBOX_ACPI  (1<<0)
 #define MBOX_SWSCI (1<<1)
 #define MBOX_ASLE  (1<<2)
+#define MBOX_ASLE_EXT  (1<<4)
 
 struct opregion_header {
u8 signature[16];
@@ -62,7 +63,10 @@ struct opregion_header {
u8 vbios_ver[16];
u8 driver_ver[16];
u32 mboxes;
-   u8 reserved[164];
+   u32 driver_model;
+   u32 pcon;
+   u8 dver[32];
+   u8 rsvd[124];
 } __packed;
 
 /* OpRegion mailbox #1: public ACPI methods */
@@ -84,7 +88,9 @@ struct opregion_acpi {
u32 evts;   /* ASL supported events */
u32 cnot;   /* current OS notification */
u32 nrdy;   /* driver status */
-   u8 rsvd2[60];
+   u32 did2[7];/* extended supported display devices ID list */
+   u32 cpd2[7];/* extended attached display devices list */
+   u8 rsvd2[4];
 } __packed;
 
 /* OpRegion mailbox #2: SWSCI */
@@ -113,7 +119,10 @@ struct opregion_asle {
u32 pcft;   /* power conservation features */
u32 srot;   /* supported rotation angles */
u32 iuer;   /* IUER events */
-   u8 rsvd[86];
+   u64 fdss;
+   u32 fdsp;
+   u32 stat;
+   u8 rsvd[70];
 } __packed;
 
 /* Driver readiness indicator */
-- 
2.1.3

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[Intel-gfx] [PATCH 5/5] drm/i915/opregion: start using extended didl

[Jani Nikula]

Adding support for did2, or the extended support display devices ID
list, increases the total to 15.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/intel_opregion.c | 28 +---
 1 file changed, 21 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_opregion.c 
b/drivers/gpu/drm/i915/intel_opregion.c
index 0da2f146c240..c7fab17c1297 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -669,7 +669,7 @@ static void intel_didl_outputs(struct drm_device *dev)
struct acpi_device *acpi_dev, *acpi_cdev, *acpi_video_bus = NULL;
unsigned long long device_id;
acpi_status status;
-   u32 temp;
+   u32 temp, max_outputs;
int i = 0;
 
handle = ACPI_HANDLE(&dev->pdev->dev);
@@ -692,9 +692,20 @@ static void intel_didl_outputs(struct drm_device *dev)
return;
}
 
+   /*
+* In theory, did2, the extended didl, gets added at opregion version
+* 3.0. In practice, however, we're supposed to set it for earlier
+* versions as well, since a BIOS that doesn't understand did2 should
+* not look at it anyway. Use a variable so we can tweak this if a need
+* arises later.
+*/
+   max_outputs = ARRAY_SIZE(opregion->acpi->didl) +
+   ARRAY_SIZE(opregion->acpi->did2);
+
list_for_each_entry(acpi_cdev, &acpi_video_bus->children, node) {
-   if (i >= 8) {
-   DRM_DEBUG_KMS("More than 8 outputs detected via 
ACPI\n");
+   if (i >= max_outputs) {
+   DRM_DEBUG_KMS("More than %u outputs detected via 
ACPI\n",
+ max_outputs);
return;
}
status = acpi_evaluate_integer(acpi_cdev->handle, "_ADR",
@@ -707,8 +718,10 @@ static void intel_didl_outputs(struct drm_device *dev)
}
 
 end:
-   /* If fewer than 8 outputs, the list must be null terminated */
-   if (i < 8)
+   DRM_DEBUG_KMS("%d outputs detected\n", i);
+
+   /* If fewer than max outputs, the list must be null terminated */
+   if (i < max_outputs)
set_did(opregion, i, 0);
return;
 
@@ -716,8 +729,9 @@ blind_set:
i = 0;
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
int output_type = ACPI_OTHER_OUTPUT;
-   if (i >= 8) {
-   DRM_DEBUG_KMS("More than 8 outputs in connector 
list\n");
+   if (i >= max_outputs) {
+   DRM_DEBUG_KMS("More than %u outputs in connector 
list\n",
+ max_outputs);
return;
}
switch (connector->connector_type) {
-- 
2.1.3

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Re: [Intel-gfx] [PATCH 8/8] drm/i915: Follow the forcewake domains type on hw accessors

[Deepak S]

On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:

Forcewake domain code uses unsigned int as a type for 'domains mask'.
Bring the hw accessors inline with this.

Suggested-by: Chris Wilson 
Signed-off-by: Mika Kuoppala 
---
  drivers/gpu/drm/i915/i915_drv.h | 4 ++--
  drivers/gpu/drm/i915/intel_uncore.c | 8 
  2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a2a8536..917614e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -535,9 +535,9 @@ struct drm_i915_display_funcs {
  
  struct intel_uncore_funcs {

void (*force_wake_get)(struct drm_i915_private *dev_priv,
-   int fw_engine);
+   unsigned fw_domains);
void (*force_wake_put)(struct drm_i915_private *dev_priv,
-   int fw_engine);
+   unsigned fw_domains);
  
  	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);

uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, 
bool trace);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 509b9c9..be02aab 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -122,7 +122,7 @@ fw_domain_posting_read(const struct 
intel_uncore_forcewake_domain *d)
  }
  
  static void

-fw_domains_get(struct drm_i915_private *dev_priv, int fw_domains)
+fw_domains_get(struct drm_i915_private *dev_priv, unsigned fw_domains)
  {
struct intel_uncore_forcewake_domain *d;
int id;
@@ -136,7 +136,7 @@ fw_domains_get(struct drm_i915_private *dev_priv, int 
fw_domains)
  }
  
  static void

-fw_domains_put(struct drm_i915_private *dev_priv, int fw_domains)
+fw_domains_put(struct drm_i915_private *dev_priv, unsigned fw_domains)
  {
struct intel_uncore_forcewake_domain *d;
int id;
@@ -181,7 +181,7 @@ static void __gen6_gt_wait_for_thread_c0(struct 
drm_i915_private *dev_priv)
  }
  
  static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,

- int fw_domains)
+ unsigned fw_domains)
  {
fw_domains_get(dev_priv, fw_domains);
  
@@ -199,7 +199,7 @@ static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)

  }
  
  static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,

-int fw_domains)
+unsigned fw_domains)
  {
fw_domains_put(dev_priv, fw_domains);
gen6_gt_check_fifodbg(dev_priv);


Looks fine

Reviewed-by: Deepak S

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[Intel-gfx] [PATCH 3/5] drm/i915/opregion: prefer DRM logging functions over pr_warn and dev_dbg

[Jani Nikula]

Conform to same style as the rest of the driver.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/intel_opregion.c | 10 +++---
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_opregion.c 
b/drivers/gpu/drm/i915/intel_opregion.c
index 10c60199029d..6644369207e0 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -25,8 +25,6 @@
  *
  */
 
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
 #include 
 #include 
 
@@ -658,14 +656,13 @@ static void intel_didl_outputs(struct drm_device *dev)
}
 
if (!acpi_video_bus) {
-   pr_warn("No ACPI video bus found\n");
+   DRM_ERROR("No ACPI video bus found\n");
return;
}
 
list_for_each_entry(acpi_cdev, &acpi_video_bus->children, node) {
if (i >= 8) {
-   dev_dbg(&dev->pdev->dev,
-   "More than 8 outputs detected via ACPI\n");
+   DRM_DEBUG_KMS("More than 8 outputs detected via 
ACPI\n");
return;
}
status =
@@ -691,8 +688,7 @@ blind_set:
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
int output_type = ACPI_OTHER_OUTPUT;
if (i >= 8) {
-   dev_dbg(&dev->pdev->dev,
-   "More than 8 outputs in connector list\n");
+   DRM_DEBUG_KMS("More than 8 outputs in connector 
list\n");
return;
}
switch (connector->connector_type) {
-- 
2.1.3

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[Intel-gfx] [PATCH 4/5] drm/i915/opregion: abstract didl and did2 getter and setter

[Jani Nikula]

Make it easier to handle the extended didl. No functional changes.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/intel_opregion.c | 50 +++
 1 file changed, 39 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_opregion.c 
b/drivers/gpu/drm/i915/intel_opregion.c
index 6644369207e0..0da2f146c240 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -628,6 +628,38 @@ static struct notifier_block intel_opregion_notifier = {
  * (version 3)
  */
 
+static u32 get_did(struct intel_opregion *opregion, int i)
+{
+   u32 did;
+
+   if (i < ARRAY_SIZE(opregion->acpi->didl)) {
+   did = ioread32(&opregion->acpi->didl[i]);
+   } else {
+   i -= ARRAY_SIZE(opregion->acpi->didl);
+
+   if (WARN_ON(i >= ARRAY_SIZE(opregion->acpi->did2)))
+   return 0;
+
+   did = ioread32(&opregion->acpi->did2[i]);
+   }
+
+   return did;
+}
+
+static void set_did(struct intel_opregion *opregion, int i, u32 val)
+{
+   if (i < ARRAY_SIZE(opregion->acpi->didl)) {
+   iowrite32(val, &opregion->acpi->didl[i]);
+   } else {
+   i -= ARRAY_SIZE(opregion->acpi->didl);
+
+   if (WARN_ON(i >= ARRAY_SIZE(opregion->acpi->did2)))
+   return;
+
+   iowrite32(val, &opregion->acpi->did2[i]);
+   }
+}
+
 static void intel_didl_outputs(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -665,22 +697,19 @@ static void intel_didl_outputs(struct drm_device *dev)
DRM_DEBUG_KMS("More than 8 outputs detected via 
ACPI\n");
return;
}
-   status =
-   acpi_evaluate_integer(acpi_cdev->handle, "_ADR",
-   NULL, &device_id);
+   status = acpi_evaluate_integer(acpi_cdev->handle, "_ADR",
+  NULL, &device_id);
if (ACPI_SUCCESS(status)) {
if (!device_id)
goto blind_set;
-   iowrite32((u32)(device_id & 0x0f0f),
- &opregion->acpi->didl[i]);
-   i++;
+   set_did(opregion, i++, (u32)(device_id & 0x0f0f));
}
}
 
 end:
/* If fewer than 8 outputs, the list must be null terminated */
if (i < 8)
-   iowrite32(0, &opregion->acpi->didl[i]);
+   set_did(opregion, i, 0);
return;
 
 blind_set:
@@ -713,9 +742,8 @@ blind_set:
output_type = ACPI_LVDS_OUTPUT;
break;
}
-   temp = ioread32(&opregion->acpi->didl[i]);
-   iowrite32(temp | (1<<31) | output_type | i,
- &opregion->acpi->didl[i]);
+   temp = get_did(opregion, i);
+   set_did(opregion, i, temp | (1 << 31) | output_type | i);
i++;
}
goto end;
@@ -735,7 +763,7 @@ static void intel_setup_cadls(struct drm_device *dev)
 * display switching hotkeys. Just like DIDL, CADL is NULL-terminated if
 * there are less than eight devices. */
do {
-   disp_id = ioread32(&opregion->acpi->didl[i]);
+   disp_id = get_did(opregion, i);
iowrite32(disp_id, &opregion->acpi->cadl[i]);
} while (++i < 8 && disp_id != 0);
 }
-- 
2.1.3

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Re: [Intel-gfx] [PATCH 8/8] drm/i915: Enum forcewake domains and domain identifiers

[Deepak S]

On Tuesday 09 December 2014 05:16 PM, Mika Kuoppala wrote:

Make the domains and domain identifiers enums. To emphasize
the difference in order to avoid mistakes.

Suggested-by: Daniel Vetter 
Signed-off-by: Mika Kuoppala 
---
  drivers/gpu/drm/i915/i915_drv.h | 41 +
  drivers/gpu/drm/i915/intel_uncore.c | 45 +++--
  2 files changed, 45 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0d47397..5c6c372 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -533,11 +533,28 @@ struct drm_i915_display_funcs {
void (*enable_backlight)(struct intel_connector *connector);
  };
  
+enum fw_domain_id {

+   FW_DOMAIN_ID_RENDER = 0,
+   FW_DOMAIN_ID_BLITTER,
+   FW_DOMAIN_ID_MEDIA,
+
+   FW_DOMAIN_ID_COUNT
+};
+
+enum fw_domains {
+   FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
+   FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
+   FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
+   FORCEWAKE_ALL = (FORCEWAKE_RENDER |
+FORCEWAKE_BLITTER |
+FORCEWAKE_MEDIA)
+};
+
  struct intel_uncore_funcs {
void (*force_wake_get)(struct drm_i915_private *dev_priv,
-   int fw_engine);
+   enum fw_domains 
domains);
void (*force_wake_put)(struct drm_i915_private *dev_priv,
-   int fw_engine);
+   enum fw_domains 
domains);
  
  	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);

uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, 
bool trace);
@@ -554,25 +571,17 @@ struct intel_uncore_funcs {
uint64_t val, bool trace);
  };
  
-enum {

-   FW_DOMAIN_ID_RENDER = 0,
-   FW_DOMAIN_ID_BLITTER,
-   FW_DOMAIN_ID_MEDIA,
-
-   FW_DOMAIN_ID_COUNT
-};
-
  struct intel_uncore {
spinlock_t lock; /** lock is also taken in irq contexts. */
  
  	struct intel_uncore_funcs funcs;
  
  	unsigned fifo_count;

-   unsigned fw_domains;
+   enum fw_domains fw_domains;
  
  	struct intel_uncore_forcewake_domain {

struct drm_i915_private *i915;
-   int id;
+   enum fw_domain_id id;
unsigned wake_count;
struct timer_list timer;
u32 reg_set;
@@ -582,12 +591,6 @@ struct intel_uncore {
u32 reg_post;
u32 val_reset;
} fw_domain[FW_DOMAIN_ID_COUNT];
-#define FORCEWAKE_RENDER   (1 << FW_DOMAIN_ID_RENDER)
-#define FORCEWAKE_BLITTER  (1 << FW_DOMAIN_ID_BLITTER)
-#define FORCEWAKE_MEDIA(1 << FW_DOMAIN_ID_MEDIA)
-#define FORCEWAKE_ALL  (FORCEWAKE_RENDER | \
-FORCEWAKE_BLITTER | \
-FORCEWAKE_MEDIA)
  };
  
  /* Iterate over initialised fw domains */

@@ -2449,7 +2452,7 @@ extern void intel_uncore_init(struct drm_device *dev);
  extern void intel_uncore_check_errors(struct drm_device *dev);
  extern void intel_uncore_fini(struct drm_device *dev);
  extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool 
restore);
-const char *intel_uncore_forcewake_domain_to_str(const int domain_id);
+const char *intel_uncore_forcewake_domain_to_str(const enum fw_domain_id id);
  void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
unsigned fw_domains);
  void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 509b9c9..e802486 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -49,7 +49,7 @@ static const char * const forcewake_domain_names[] = {
  };
  
  const char *

-intel_uncore_forcewake_domain_to_str(const int id)
+intel_uncore_forcewake_domain_to_str(const enum fw_domain_id id)
  {
BUILD_BUG_ON((sizeof(forcewake_domain_names)/sizeof(const char *)) !=
 FW_DOMAIN_ID_COUNT);
@@ -122,10 +122,10 @@ fw_domain_posting_read(const struct 
intel_uncore_forcewake_domain *d)
  }
  
  static void

-fw_domains_get(struct drm_i915_private *dev_priv, int fw_domains)
+fw_domains_get(struct drm_i915_private *dev_priv, enum fw_domains fw_domains)
  {
struct intel_uncore_forcewake_domain *d;
-   int id;
+   enum fw_domain_id id;
  
  	for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {

fw_domain_wait_ack_clear(d);
@@ -136,10 +136,10 @@ fw_domains_get(struct drm_i915_private *dev_priv, int 
fw_domains)
  }
  
  static void

-fw_domains_put(struct drm_i915_private *dev_priv, int fw_domains)
+fw_domains_put(struct d

Re: [Intel-gfx] [PATCH v6 4/5] drm/i915: Mark shadow batch buffers as purgeable

[Bloomfield, Jon]

> -Original Message-
> From: Nguyen, Michael H
> Sent: Monday, December 08, 2014 10:34 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Bloomfield, Jon; Brad Volkin
> Subject: [PATCH v6 4/5] drm/i915: Mark shadow batch buffers as purgeable
> 
> From: Brad Volkin 
> 
> By adding a new exec_entry flag, we cleanly mark the shadow objects as
> purgeable after they are on the active list.
> 
> v2:
> - Move 'shadow_batch_obj->madv = I915_MADV_WILLNEED' inside _get
>   fnc (danvet, from v4 6/7 feedback)
> 
> Issue: VIZ-4719
> Signed-off-by: Brad Volkin 
> ---
>  drivers/gpu/drm/i915/i915_gem_batch_pool.c |  2 ++
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 11 ++-
>  2 files changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_batch_pool.c
> b/drivers/gpu/drm/i915/i915_gem_batch_pool.c
> index e9349e3..9e0ec4b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_batch_pool.c
> +++ b/drivers/gpu/drm/i915/i915_gem_batch_pool.c
> @@ -128,5 +128,7 @@ i915_gem_batch_pool_get(struct
> i915_gem_batch_pool *pool,
>   list_add_tail(&obj->batch_pool_list, &pool->cache_list);
>   }
> 
> + obj->madv = I915_MADV_WILLNEED;
> +
>   return obj;
>  }
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index fccfff5..2071938 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -37,6 +37,7 @@
>  #define  __EXEC_OBJECT_HAS_FENCE (1<<30)  #define
> __EXEC_OBJECT_NEEDS_MAP (1<<29)  #define
> __EXEC_OBJECT_NEEDS_BIAS (1<<28)
> +#define  __EXEC_OBJECT_PURGEABLE (1<<27)
> 
>  #define BATCH_OFFSET_BIAS (256*1024)
> 
> @@ -226,7 +227,12 @@ i915_gem_execbuffer_unreserve_vma(struct
> i915_vma *vma)
>   if (entry->flags & __EXEC_OBJECT_HAS_PIN)
>   vma->pin_count--;
> 
> - entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE |
> __EXEC_OBJECT_HAS_PIN);
> + if (entry->flags & __EXEC_OBJECT_PURGEABLE)
> + obj->madv = I915_MADV_DONTNEED;
> +
> + entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE |
> +   __EXEC_OBJECT_HAS_PIN |
> +   __EXEC_OBJECT_PURGEABLE);
>  }
> 
>  static void eb_destroy(struct eb_vmas *eb) @@ -1410,6 +1416,8 @@
> i915_gem_do_execbuffer(struct drm_device *dev, void *data,
>   goto err;
>   }
> 
> + shadow_batch_obj->madv = I915_MADV_WILLNEED;
> +

Hasn't i915_gem_batch_pool_get() has already marked the buffer as WILLNEED ?


>   ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 4096, 0);
>   if (ret)
>   goto err;
> @@ -1433,6 +1441,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
> void *data,
> 
>   vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
>   vma->exec_entry = &shadow_exec_entry;
> + vma->exec_entry->flags =
> __EXEC_OBJECT_PURGEABLE;
>   drm_gem_object_reference(&shadow_batch_obj-
> >base);
>   list_add_tail(&vma->exec_list, &eb->vmas);
> 
> --
> 1.9.1

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Re: [Intel-gfx] [PATCH] drm/i915: save/restore GMBUS freq across suspend/resume on gen4

[Jani Nikula]

On Wed, 10 Dec 2014, Jesse Barnes  wrote:
> On Wed, 10 Dec 2014 22:35:37 +0200
> Ville Syrjälä  wrote:
>
>> On Wed, Dec 10, 2014 at 12:16:05PM -0800, Jesse Barnes wrote:
>> > Should probably just init this in the GMbus code all the time,
>> > based on the cdclk and HPLL like we do on newer platforms.  Ville
>> > has code for that in a rework branch, but until then we can fix
>> > this bug fairly easily.
>> > 
>> > References: https://bugs.freedesktop.org/show_bug.cgi?id=76301
>> > Signed-off-by: Jesse Barnes 
>> 
>> My cdclk extraction code doesn't seem to agree with this register for
>> this particular bug reporter at least. So I think I need to go double
>> check my code. The other options are that GMBUS clock isn't derived
>> from cdclk on that platform, or that the HPLL/cdclk bits in configdb
>> are simply not valid for this particular chipset.
>> 
>> In the meantime however, we can at least get some machines working
>> with this patch. I'm not entirely sure which platforms have this
>> register, but IS_GEN4() looks safe enough since my 946GZ has it and
>> the reporter has a G41.
>> 
>> Reviewed-by: Ville Syrjälä 
>
> Great, thanks.  Jani, can you pick this up?  I'll bounce the original
> over to stable@ too.

Pushed to drm-intel-next-fixes, with cc: stable added. Thanks for the
patch and review.

BR,
Jani


>
> Thanks,
> Jesse
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[Intel-gfx] [PULL] drm-intel-next-fixes

[Jani Nikula]

Hi Dave -

Here's a batch of i915 fixes for 3.19.

BR,
Jani.

The following changes since commit 00f0b3781028605910cb4662a0f8a4849b445fc2:

  drm/i915: Reject modeset when the same digital port is used more than once 
(2014-12-03 09:31:53 +0100)

are available in the git repository at:

  git://anongit.freedesktop.org/drm-intel tags/drm-intel-next-fixes-2014-12-11

for you to fetch changes up to 9f49c37635d5c2a801f7670d5fbf0b25ec461f2c:

  drm/i915: save/restore GMBUS freq across suspend/resume on gen4 (2014-12-11 
15:31:59 +0200)


Damien Lespiau (3):
  drm/i915/bdw: Fix the write setting up the WIZ hashing mode
  drm/i915: Invert the mask and val arguments in wa_add() and WA_REG()
  drm/i915: Remove '& 0x' from the mask given to WA_REG()

Daniel Vetter (3):
  drm/i915: compute wait_ioctl timeout correctly
  drm/i915: Handle inaccurate time conversion issues
  drm/i915: Don't complain about stolen conflicts on gen3

Dave Airlie (1):
  drm/i915: resume MST after reading back hw state

Jesse Barnes (2):
  drm/i915: don't always do full mode sets when infoframes are enabled
  drm/i915: save/restore GMBUS freq across suspend/resume on gen4

 drivers/gpu/drm/i915/i915_drv.c |  3 ++-
 drivers/gpu/drm/i915/i915_drv.h |  6 ++
 drivers/gpu/drm/i915/i915_gem.c | 13 -
 drivers/gpu/drm/i915/i915_gem_stolen.c  |  6 +-
 drivers/gpu/drm/i915/i915_reg.h | 18 +++---
 drivers/gpu/drm/i915/i915_suspend.c |  8 
 drivers/gpu/drm/i915/intel_display.c| 10 ++
 drivers/gpu/drm/i915/intel_pm.c |  6 +++---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 24 ++--
 kernel/time/time.c  |  1 +
 10 files changed, 72 insertions(+), 23 deletions(-)

-- 
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Re: [Intel-gfx] [PATCH v6 5/5] drm/i915: Tidy up execbuffer command parsing code

[Bloomfield, Jon]

> -Original Message-
> From: Nguyen, Michael H
> Sent: Monday, December 08, 2014 10:34 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Bloomfield, Jon; Brad Volkin
> Subject: [PATCH v6 5/5] drm/i915: Tidy up execbuffer command parsing code
> 
> From: Brad Volkin 
> 
> Move it to a separate function since the main do_execbuffer function
> already has so much going on.
> 
> v2:
> - Move pin/unpin calls inside i915_parse_cmds() (Chris W, v4 7/7
>   feedback)
> 
> Issue: VIZ-4719
> Signed-off-by: Brad Volkin 
> 
> Conflicts:
>   drivers/gpu/drm/i915/i915_gem_execbuffer.c
> ---
>  drivers/gpu/drm/i915/i915_cmd_parser.c |   8 ++
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c | 126 ---
> --
>  2 files changed, 77 insertions(+), 57 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
> b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 118079d..80b1b28 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -1042,10 +1042,17 @@ int i915_parse_cmds(struct intel_engine_cs
> *ring,
>   struct drm_i915_cmd_descriptor default_desc = { 0 };
>   bool oacontrol_set = false; /* OACONTROL tracking. See
> check_cmd() */
> 
> + ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 4096, 0);
> + if (ret) {
> + DRM_DEBUG_DRIVER("CMD: Failed to pin shadow batch\n");
> + return -1;
> + }
> +
>   batch_base = copy_batch(shadow_batch_obj, batch_obj,
>   batch_start_offset, batch_len);
>   if (IS_ERR(batch_base)) {
>   DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n");
> + i915_gem_object_ggtt_unpin(shadow_batch_obj);
>   return PTR_ERR(batch_base);
>   }
> 
> @@ -1116,6 +1123,7 @@ int i915_parse_cmds(struct intel_engine_cs *ring,
>   }
> 
>   vunmap(batch_base);
> + i915_gem_object_ggtt_unpin(shadow_batch_obj);
> 
>   return ret;
>  }
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 2071938..3d36465 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1069,6 +1069,65 @@ i915_emit_box(struct intel_engine_cs *ring,
>   return 0;
>  }
> 
> +static struct drm_i915_gem_object*
> +i915_gem_execbuffer_parse(struct intel_engine_cs *ring,
> +   struct drm_i915_gem_exec_object2
> *shadow_exec_entry,
> +   struct eb_vmas *eb,
> +   struct drm_i915_gem_object *batch_obj,
> +   u32 batch_start_offset,
> +   u32 batch_len,
> +   bool is_master,
> +   u32 *flags)
> +{
> + struct drm_i915_private *dev_priv = to_i915(batch_obj->base.dev);
> + struct drm_i915_gem_object *shadow_batch_obj;
> + int ret;
> +
> + shadow_batch_obj = i915_gem_batch_pool_get(&dev_priv-
> >mm.batch_pool,
> +batch_obj->base.size);
> + if (IS_ERR(shadow_batch_obj))
> + return shadow_batch_obj;
> +
> + ret = i915_parse_cmds(ring,
> +   batch_obj,
> +   shadow_batch_obj,
> +   batch_start_offset,
> +   batch_len,
> +   is_master);
> + if (ret) {
> + if (ret == -EACCES)
> + return batch_obj;

Shouldn't this be returning an error code ?



> + } else {
> + struct i915_vma *vma;
> +
> + memset(shadow_exec_entry, 0,
> sizeof(*shadow_exec_entry));
> +
> + vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
> + vma->exec_entry = shadow_exec_entry;
> + vma->exec_entry->flags = __EXEC_OBJECT_PURGEABLE;
> + drm_gem_object_reference(&shadow_batch_obj->base);
> + list_add_tail(&vma->exec_list, &eb->vmas);
> +
> + shadow_batch_obj->base.pending_read_domains =
> + batch_obj->base.pending_read_domains;
> +
> + /*
> +  * Set the DISPATCH_SECURE bit to remove the
> NON_SECURE
> +  * bit from MI_BATCH_BUFFER_START commands issued in
> the
> +  * dispatch_execbuffer implementations. We specifically
> +  * don't want that set when the command parser is
> +  * enabled.
> +  *
> +  * FIXME: with aliasing ppgtt, buffers that should only
> +  * be in ggtt still end up in the aliasing ppgtt. remove
> +  * this check when that is fixed.
> +  */
> + if (USES_FULL_PPGTT(dev))
> + *flags |= I915_DISPATCH_SECURE;
> + }
> +
> + return ret ? ERR_PTR(ret) : shadow_batch_obj; }
> 
>  int
>  i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file
> *file, @@ -1286,7 +1345,6 @@ i915_gem_do_

Re: [Intel-gfx] [PATCH] drm/i915: vlv: fix IRQ masking when uninstalling interrupts

[Jani Nikula]

On Wed, 10 Dec 2014, Ville Syrjälä  wrote:
> On Thu, Nov 20, 2014 at 04:05:55PM +0200, Imre Deak wrote:
>> irq_mask should include all IRQ bits that we want to mask, but atm we
>> set it incorrectly to the inverse of this. If the mask is used
>> subsequently to enable/disable some IRQ bits, we may unintentionally
>> unmask unrelated IRQs. I can't see any way that this can lead to a real
>> problem in the current -nightly code, since the first place the mask
>> will be used next (after a suspend/resume cycle) is in
>> valleyview_irq_postinstall(), but the mask is reset there to its proper
>> value.
>> 
>> This causes a problem in the upstream kernel though, where - due to another
>> issue - the mask is used in the above way to disable only the display IRQs.
>> This other issue is fixed by:
>> 
>> commit 950eabaf5a87257040e0c207be09487954113f54
>> Author: Imre Deak 
>> Date:   Mon Sep 8 15:21:09 2014 +0300
>> 
>> drm/i915: vlv: fix display IRQ enable/disable
>> 
>> Interestingly, even with the above two bugs, we shouldn't in theory have
>> any real problems (arguably a famous last sentence:). That's because
>> even if we unmask something unintentionally via the VLV_IMR/VLV_IER
>> register the master IRQ masking bit in VLV_MASTER_IER is still set and
>> should prevent all i915 interrupts. According to my testing on an ASUS
>> T100 with DSI output this isn't the case at least with the
>> MIPIA_INTERRUPT. Leaving this one unmasked in IMR/IER, while having
>> VLV_MASTER_IER set to 0 may lead to a lockup during system suspend as
>> shown in the bugzilla ticket below. This fix should get rid of the
>> problem reported there in upstream and older kernels.
>> 
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85920
>> Cc: sta...@vger.kernel.org (v3.15+)
>> Signed-off-by: Imre Deak 
>
> Reviewed-by: Ville Syrjälä 

Pushed to drm-intel-next-fixes, thanks for the patch and review.

BR,
Jani.


>
>> ---
>>  drivers/gpu/drm/i915/i915_irq.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c 
>> b/drivers/gpu/drm/i915/i915_irq.c
>> index 8d169e1..4601f53 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -3597,7 +3597,7 @@ static void vlv_display_irq_uninstall(struct 
>> drm_i915_private *dev_priv)
>>  
>>  vlv_display_irq_reset(dev_priv);
>>  
>> -dev_priv->irq_mask = 0;
>> +dev_priv->irq_mask = ~0;
>>  }
>>  
>>  static void valleyview_irq_uninstall(struct drm_device *dev)
>> -- 
>> 1.8.4
>> 
>> ___
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>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> -- 
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> Intel OTC
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Re: [Intel-gfx] lib: Fix out of tree build of version.h

[Joonas Lahtinen]

This e-mail can be disregarded. It contains no secrets no nothing,
simply sent from wrong address.

On to, 2014-12-11 at 13:11 +, Lahtinen, Joonas wrote:
> Currently out of tree build fails because the version.h.tmp is generated
> into the source directory instead of the build directory where it is
> later looked for. This commit fixes it.
> 
> From 2c0617e21101d69e7219c6660936c0015f93f8ee Mon Sep 17 00:00:00 2001
> From: Joonas Lahtinen 
> Date: Thu, 11 Dec 2014 15:05:11 +0200
> Subject: [PATCH] lib: Fix out of tree build of version.h
> 
> Write the version.h.tmp file into the build directory instead of source
> directory. This allows out of tree building when those two are not the
> same.
> 
> Signed-off-by: Joonas Lahtinen 
> ---
>  lib/Makefile.sources |   12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index 819b21a..34a3d31 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -55,16 +55,16 @@ libintel_tools_la_SOURCES =   \
>  $(IGT_LIB_PATH)/version.h.tmp:
>   @touch $@
>   @if test -d $(GPU_TOOLS_PATH)/.git; then \
> - if which git > /dev/null 2>&1; then cd $(@D); \
> + if which git > /dev/null 2>&1; then \
> + cd $(GPU_TOOLS_PATH); \
>   git log -n 1 --oneline | \
> - sed 's/^\([^ ]*\) .*/#define IGT_GIT_SHA1 "g\1"/' \
> - >> $(@F) ; \
> + sed 's/^\([^ ]*\) .*/#define IGT_GIT_SHA1 "g\1"/' ; \
>   else \
> - echo '#define IGT_GIT_SHA1 "NO-GIT"' >> $@ ; \
> + echo '#define IGT_GIT_SHA1 "NO-GIT"' ; \
>   fi \
>   else \
> - echo '#define IGT_GIT_SHA1 "NOT-GIT"' >> $@ ; \
> - fi
> + echo '#define IGT_GIT_SHA1 "NOT-GIT"' ; \
> + fi >> $@
>  
> 
>  $(IGT_LIB_PATH)/version.h: $(IGT_LIB_PATH)/version.h.tmp


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[Intel-gfx] [PATCH 1/7] drm/plane-helper: Test for plane disable earlier

[Matt Roper]

drm_plane_helper_check_update() currently uses crtc before testing whether
we're disabling the plane (fb == NULL).  Move the fb test before the first crtc
usage so that crtc == NULL doesn't have to be handled by the caller.

Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/drm_plane_helper.c | 16 +++-
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/drm_plane_helper.c 
b/drivers/gpu/drm/drm_plane_helper.c
index ae61fb2..f24c4cf 100644
--- a/drivers/gpu/drm/drm_plane_helper.c
+++ b/drivers/gpu/drm/drm_plane_helper.c
@@ -142,6 +142,17 @@ int drm_plane_helper_check_update(struct drm_plane *plane,
 {
int hscale, vscale;
 
+   if (!fb) {
+   *visible = false;
+   return 0;
+   }
+
+   /* crtc should only be NULL when disabling (i.e., !fb) */
+   if (WARN_ON(!crtc)) {
+   *visible = false;
+   return 0;
+   }
+
if (!crtc->enabled && !can_update_disabled) {
DRM_DEBUG_KMS("Cannot update plane of a disabled CRTC.\n");
return -EINVAL;
@@ -155,11 +166,6 @@ int drm_plane_helper_check_update(struct drm_plane *plane,
return -ERANGE;
}
 
-   if (!fb) {
-   *visible = false;
-   return 0;
-   }
-
*visible = drm_rect_clip_scaled(src, dest, clip, hscale, vscale);
if (!*visible)
/*
-- 
1.8.5.1

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Re: [Intel-gfx] [PATCH] drm/i915/i9xx: check for panel on pipe before asserting panel unlock bits

[Jesse Barnes]

On 11 Dec 2014 00:40:28 -0800
shuang...@intel.com wrote:

> Tested-By: PRC QA PRTS (Patch Regression Test System Contact: 
> shuang...@intel.com)
> -Summary-
> Platform  Delta  drm-intel-nightly  Series Applied
> PNV  364/364  364/364
> ILK  +1-4  364/366  361/366
> SNB  448/450  448/450
> IVB  497/498  497/498
> BYT  289/289  289/289
> HSW  563/564  563/564
> BDW  417/417  417/417
> -Detailed-
> Platform  Testdrm-intel-nightly  
> Series Applied
> *ILK  igt_kms_pipe_crc_basic_bad-pipe  PASS(2, M26)  DMESG_WARN(1, 
> M26)
> *ILK  igt_kms_flip_busy-flip-interruptible  PASS(5, M26)  
> DMESG_WARN(1, M26)
> *ILK  igt_kms_flip_flip-vs-rmfb-interruptible  NSPT(1, M26)PASS(5, M26)   
>DMESG_WARN(1, M26)
>  ILK  igt_kms_flip_plain-flip-ts-check-interruptible  DMESG_WARN(1, 
> M26)PASS(4, M26)  DMESG_WARN(1, M26)
>  ILK  igt_kms_flip_wf_vblank-ts-check  DMESG_WARN(7, M26)PASS(21, M26M37) 
>  PASS(1, M26)
> Note: You need to pay more attention to line start with '*'

Based on this log and the one for saving and restoring the GMbus clock,
it looks like we have some inconsistent results on ILK.  Can you look
into the logs and file bugs against those tests if they're no already
filed?

Thanks,
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Re: [Intel-gfx] [PATCH] drm/i915/skl: Correcting the flushing of pipe

[Tvrtko Ursulin]

On 12/11/2014 12:28 PM, sonika.jin...@intel.com wrote:

From: Sonika Jindal 

We were incorreectly bypassing the flush everytime which led to fifo
underrun when more than one plane is enabled.

Signed-off-by: Sonika Jindal 
---
  drivers/gpu/drm/i915/intel_pm.c |3 +--
  1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5748bf9..8cd045a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3633,9 +3633,8 @@ static void skl_flush_wm_values(struct drm_i915_private 
*dev_priv,
skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
skl_wm_flush_pipe(dev_priv, pipe, 2);
intel_wait_for_vblank(dev, pipe);
+   reallocated[pipe] = true;
}
-
-   reallocated[pipe] = true;
}

/*


Works like a charm now!

Reviewed-by: Tvrtko Ursulin 

Regards,

Tvrtko
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[Intel-gfx] [RFC] drm/i915: Reduce locking in command submission

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Eliminate six needless spin lock/unlock pairs when writing ELSP.

RFC for now with some #define copy and paste.

Signed-off-by: Tvrtko Ursulin 
Cc: Dave Gordon 
---
 drivers/gpu/drm/i915/intel_lrc.c | 16 +---
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index a82020e..f2f4a28 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -276,6 +276,10 @@ static uint64_t execlists_ctx_descriptor(struct 
drm_i915_gem_object *ctx_obj)
return desc;
 }
 
+#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + 
(reg__))
+#define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, 
(dev_priv__)->regs + (reg__))
+#define __raw_posting_read(dev_priv__, reg__) 
(void)__raw_i915_read32(dev_priv__, reg__)
+
 static void execlists_elsp_write(struct intel_engine_cs *ring,
 struct drm_i915_gem_object *ctx_obj0,
 struct drm_i915_gem_object *ctx_obj1)
@@ -323,19 +327,17 @@ static void execlists_elsp_write(struct intel_engine_cs 
*ring,
dev_priv->uncore.funcs.force_wake_get(dev_priv,
  FORCEWAKE_ALL);
}
-   spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
 
-   I915_WRITE(RING_ELSP(ring), desc[1]);
-   I915_WRITE(RING_ELSP(ring), desc[0]);
-   I915_WRITE(RING_ELSP(ring), desc[3]);
+   __raw_i915_write32(dev_priv, RING_ELSP(ring), desc[1]);
+   __raw_i915_write32(dev_priv, RING_ELSP(ring), desc[0]);
+   __raw_i915_write32(dev_priv, RING_ELSP(ring), desc[3]);
/* The context is automatically loaded after the following */
-   I915_WRITE(RING_ELSP(ring), desc[2]);
+   __raw_i915_write32(dev_priv, RING_ELSP(ring), desc[2]);
 
/* ELSP is a wo register, so use another nearby reg for posting instead 
*/
-   POSTING_READ(RING_EXECLIST_STATUS(ring));
+   __raw_posting_read(dev_priv, RING_EXECLIST_STATUS(ring));
 
/* Release Force Wakeup (see the big comment above). */
-   spin_lock_irqsave(&dev_priv->uncore.lock, flags);
if (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) {
if (--dev_priv->uncore.fw_rendercount == 0)
dev_priv->uncore.funcs.force_wake_put(dev_priv,
-- 
2.1.1

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Re: [Intel-gfx] [PATCH 1/7] drm/plane-helper: Test for plane disable earlier

[Daniel Vetter]

On Thu, Dec 11, 2014 at 07:20:57AM -0800, Matt Roper wrote:
> drm_plane_helper_check_update() currently uses crtc before testing whether
> we're disabling the plane (fb == NULL).  Move the fb test before the first 
> crtc
> usage so that crtc == NULL doesn't have to be handled by the caller.
> 
> Signed-off-by: Matt Roper 

Yeah makes sense, pulled into drm misc branch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH v3 0/8] Add enlightenments for vGPU

[Tvrtko Ursulin]

Hi,

I'll try to do the detailed review of your series in the following few 
days. I might ask some questions on the design also to help me 
understand the bigger picture.


First thing, I see that patches are checkpatch.pl clean, apart when run 
in strict mode. I think Daniel prefers "--strict" nowadays, at least I 
needed to fix up those in my patches so you should probably do the same.


On 11/13/2014 12:02 PM, Yu Zhang wrote:
[snip]

The primary change introduced here is to implement so-called
"address space ballooning" technique. XenGT partitions global
graphics memory among multiple VMs, so each VM can directly
access a portion of the memory w/o hypervisor's intervention,
e.g. filling textures or queuing commands. However w/ the
partitioning an unmodified i915 driver would assume a smaller
graphics memory starting from address ZERO, so requires XenGT
core module (vgt) to translate the graphics address between
'guest view' and 'host view', for all registers and command
opcodes which contain a graphics memory address. To reduce the
complexity, XenGT introduces "address space ballooning", by
telling the exact partitioning knowledge to each guest i915
driver, which then reserves and prevents non-allocated portions
from allocation. Then vgt module only needs to scan and validate
graphics addresses w/o complexity of translation.


I couldn't figure this out - is there any hardware protection in there, 
or a virtual i915 instance could access memory outside it's area if 
there was a security bug/exploit in the driver, or the balloon was 
incorrectly set up?


Regards,

Tvrtko
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Re: [Intel-gfx] [PATCH v3 1/8] drm/i915: Introduce a PV INFO page structure for Intel GVT-g.

[Tvrtko Ursulin]

On 11/13/2014 12:02 PM, Yu Zhang wrote:

Introduce a PV INFO structure, to facilitate the Intel GVT-g
technology, which is a GPU virtualization solution with mediated
pass-through. This page contains the shared information between
i915 driver and the host emulator. For now, this structure utilizes
an area of 4K bypes on HSW GPU's unused MMIO space to support


bytes


existing production. Future hardware will have the reserved window


It is slightly unclear to me what "existing production" means?


architecturally defined, and layout of the page will be added in
future BSpec.

The i915 driver load routine detects if it is running in a VM by
reading the contents of this PV INFO page. Thereafter a flag,
vgpu.active is set, and intel_vgpu_active() is used by checking
this flag to conclude if GPU is virtualized with Intel GVT-g. By
now, intel_vgpu_active() will return true, only when the driver
is running as a guest in the Intel GVT-g enhanced environment on
HSW platform.

v2:
take Chris' comments:
- call the i915_check_vgpu() in intel_uncore_init()
- sanitize i915_check_vgpu() by adding BUILD_BUG_ON() and debug info
take Daniel's comments:
- put the definition of PV INFO into a new header - i915_vgt_if.h
other changes:
- access mmio regs by readq/readw in i915_check_vgpu()

v3:
take Daniel's comments:
- move the i915/vgt interfaces into a new i915_vgpu.c
- update makefile
- add kerneldoc to functions which are non-static
- add a DOC: section describing some of the high-level design
- update drm docbook
other changes:
- rename i915_vgt_if.h to i915_vgpu.h

Signed-off-by: Yu Zhang 
Signed-off-by: Jike Song 
Signed-off-by: Eddie Dong 
---
  Documentation/DocBook/drm.tmpl  |  5 +++
  drivers/gpu/drm/i915/Makefile   |  3 ++
  drivers/gpu/drm/i915/i915_drv.h | 11 +
  drivers/gpu/drm/i915/i915_vgpu.c| 85 +
  drivers/gpu/drm/i915/i915_vgpu.h| 85 +
  drivers/gpu/drm/i915/intel_uncore.c |  3 ++
  6 files changed, 192 insertions(+)
  create mode 100644 drivers/gpu/drm/i915/i915_vgpu.c
  create mode 100644 drivers/gpu/drm/i915/i915_vgpu.h

diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index 64d9c1e..e4db4cf 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -3832,6 +3832,11 @@ int num_ioctls;
  !Fdrivers/gpu/drm/i915/i915_irq.c intel_runtime_pm_disable_interrupts
  !Fdrivers/gpu/drm/i915/i915_irq.c intel_runtime_pm_enable_interrupts

+  
+Intel GVT-g Guest Support(vGPU)
+!Pdrivers/gpu/drm/i915/i915_vgpu.c Intel GVT-g guest support
+!Idrivers/gpu/drm/i915/i915_vgpu.c
+  
  
  
Display Hardware Handling
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 891e584..d9aa5ca 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -79,6 +79,9 @@ i915-y += dvo_ch7017.o \
  intel_sdvo.o \
  intel_tv.o

+# virtual gpu code
+i915-y += i915_vgpu.o
+
  # legacy horrors
  i915-y += i915_dma.o \
  i915_ums.o
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 54691bc..e1e221e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1470,6 +1470,10 @@ struct i915_workarounds {
u32 count;
  };

+struct i915_virtual_gpu {
+   bool active;
+};
+
  struct drm_i915_private {
struct drm_device *dev;
struct kmem_cache *slab;
@@ -1482,6 +1486,8 @@ struct drm_i915_private {

struct intel_uncore uncore;

+   struct i915_virtual_gpu vgpu;
+
struct intel_gmbus gmbus[GMBUS_NUM_PORTS];


@@ -2311,6 +2317,11 @@ extern void intel_uncore_check_errors(struct drm_device 
*dev);
  extern void intel_uncore_fini(struct drm_device *dev);
  extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool 
restore);

+static inline bool intel_vgpu_active(struct drm_device *dev)
+{
+   return to_i915(dev)->vgpu.active;
+}
+
  void
  i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 u32 status_mask);
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
new file mode 100644
index 000..3f6b797
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright(c) 2011-2014 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice 

Re: [Intel-gfx] [PATCH] drm/i915: Use true PPGTT in Gen8 if execlists are enabled

[shuang . he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: 
shuang...@intel.com)
-Summary-
Platform  Delta  drm-intel-nightly  Series Applied
PNV  364/364  364/364
ILK  +1-1  364/366  364/366
SNB  448/450  448/450
IVB  497/498  497/498
BYT  289/289  289/289
HSW  563/564  563/564
BDW  417/417  417/417
-Detailed-
Platform  Testdrm-intel-nightly  Series 
Applied
*ILK  igt_gem_fenced_exec_thrash_no-spare-fences-busy  PASS(2, M26M37)  
DMESG_WARN(1, M37)
 ILK  igt_kms_flip_wf_vblank-ts-check  DMESG_WARN(7, M26)PASS(23, M26M37)   
   PASS(1, M37)
Note: You need to pay more attention to line start with '*'
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Re: [Intel-gfx] [PATCH v6 4/5] drm/i915: Mark shadow batch buffers as purgeable

[Michael H. Nguyen]

On 12/11/2014 05:26 AM, Bloomfield, Jon wrote:

-Original Message-
From: Nguyen, Michael H
Sent: Monday, December 08, 2014 10:34 PM
To: intel-gfx@lists.freedesktop.org
Cc: Bloomfield, Jon; Brad Volkin
Subject: [PATCH v6 4/5] drm/i915: Mark shadow batch buffers as purgeable

From: Brad Volkin 

By adding a new exec_entry flag, we cleanly mark the shadow objects as
purgeable after they are on the active list.

v2:
- Move 'shadow_batch_obj->madv = I915_MADV_WILLNEED' inside _get
   fnc (danvet, from v4 6/7 feedback)

Issue: VIZ-4719
Signed-off-by: Brad Volkin 
---
  drivers/gpu/drm/i915/i915_gem_batch_pool.c |  2 ++
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 11 ++-
  2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_batch_pool.c
b/drivers/gpu/drm/i915/i915_gem_batch_pool.c
index e9349e3..9e0ec4b 100644
--- a/drivers/gpu/drm/i915/i915_gem_batch_pool.c
+++ b/drivers/gpu/drm/i915/i915_gem_batch_pool.c
@@ -128,5 +128,7 @@ i915_gem_batch_pool_get(struct
i915_gem_batch_pool *pool,
list_add_tail(&obj->batch_pool_list, &pool->cache_list);
}

+   obj->madv = I915_MADV_WILLNEED;
+
return obj;
  }
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index fccfff5..2071938 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -37,6 +37,7 @@
  #define  __EXEC_OBJECT_HAS_FENCE (1<<30)  #define
__EXEC_OBJECT_NEEDS_MAP (1<<29)  #define
__EXEC_OBJECT_NEEDS_BIAS (1<<28)
+#define  __EXEC_OBJECT_PURGEABLE (1<<27)

  #define BATCH_OFFSET_BIAS (256*1024)

@@ -226,7 +227,12 @@ i915_gem_execbuffer_unreserve_vma(struct
i915_vma *vma)
if (entry->flags & __EXEC_OBJECT_HAS_PIN)
vma->pin_count--;

-   entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE |
__EXEC_OBJECT_HAS_PIN);
+   if (entry->flags & __EXEC_OBJECT_PURGEABLE)
+   obj->madv = I915_MADV_DONTNEED;
+
+   entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE |
+ __EXEC_OBJECT_HAS_PIN |
+ __EXEC_OBJECT_PURGEABLE);
  }

  static void eb_destroy(struct eb_vmas *eb) @@ -1410,6 +1416,8 @@
i915_gem_do_execbuffer(struct drm_device *dev, void *data,
goto err;
}

+   shadow_batch_obj->madv = I915_MADV_WILLNEED;
+


Hasn't i915_gem_batch_pool_get() has already marked the buffer as WILLNEED ?
Yes, good eyes. It was actually corrected in 5/5 but that doesn't make 
this patch okay. Will fix.


Thanks,
Mike




ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 4096, 0);
if (ret)
goto err;
@@ -1433,6 +1441,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
void *data,

vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
vma->exec_entry = &shadow_exec_entry;
+   vma->exec_entry->flags =
__EXEC_OBJECT_PURGEABLE;
drm_gem_object_reference(&shadow_batch_obj-

base);

list_add_tail(&vma->exec_list, &eb->vmas);

--
1.9.1



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Re: [Intel-gfx] [PATCH v6 5/5] drm/i915: Tidy up execbuffer command parsing code

[Michael H. Nguyen]

On 12/11/2014 05:49 AM, Bloomfield, Jon wrote:




-Original Message-
From: Nguyen, Michael H
Sent: Monday, December 08, 2014 10:34 PM
To: intel-gfx@lists.freedesktop.org
Cc: Bloomfield, Jon; Brad Volkin
Subject: [PATCH v6 5/5] drm/i915: Tidy up execbuffer command parsing code

From: Brad Volkin 

Move it to a separate function since the main do_execbuffer function
already has so much going on.

v2:
- Move pin/unpin calls inside i915_parse_cmds() (Chris W, v4 7/7
   feedback)

Issue: VIZ-4719
Signed-off-by: Brad Volkin 

Conflicts:
drivers/gpu/drm/i915/i915_gem_execbuffer.c
---
  drivers/gpu/drm/i915/i915_cmd_parser.c |   8 ++
  drivers/gpu/drm/i915/i915_gem_execbuffer.c | 126 ---
--
  2 files changed, 77 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 118079d..80b1b28 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -1042,10 +1042,17 @@ int i915_parse_cmds(struct intel_engine_cs
*ring,
struct drm_i915_cmd_descriptor default_desc = { 0 };
bool oacontrol_set = false; /* OACONTROL tracking. See
check_cmd() */

+   ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 4096, 0);
+   if (ret) {
+   DRM_DEBUG_DRIVER("CMD: Failed to pin shadow batch\n");
+   return -1;
+   }
+
batch_base = copy_batch(shadow_batch_obj, batch_obj,
batch_start_offset, batch_len);
if (IS_ERR(batch_base)) {
DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n");
+   i915_gem_object_ggtt_unpin(shadow_batch_obj);
return PTR_ERR(batch_base);
}

@@ -1116,6 +1123,7 @@ int i915_parse_cmds(struct intel_engine_cs *ring,
}

vunmap(batch_base);
+   i915_gem_object_ggtt_unpin(shadow_batch_obj);

return ret;
  }
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 2071938..3d36465 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1069,6 +1069,65 @@ i915_emit_box(struct intel_engine_cs *ring,
return 0;
  }

+static struct drm_i915_gem_object*
+i915_gem_execbuffer_parse(struct intel_engine_cs *ring,
+ struct drm_i915_gem_exec_object2
*shadow_exec_entry,
+ struct eb_vmas *eb,
+ struct drm_i915_gem_object *batch_obj,
+ u32 batch_start_offset,
+ u32 batch_len,
+ bool is_master,
+ u32 *flags)
+{
+   struct drm_i915_private *dev_priv = to_i915(batch_obj->base.dev);
+   struct drm_i915_gem_object *shadow_batch_obj;
+   int ret;
+
+   shadow_batch_obj = i915_gem_batch_pool_get(&dev_priv-

mm.batch_pool,

+  batch_obj->base.size);
+   if (IS_ERR(shadow_batch_obj))
+   return shadow_batch_obj;
+
+   ret = i915_parse_cmds(ring,
+ batch_obj,
+ shadow_batch_obj,
+ batch_start_offset,
+ batch_len,
+ is_master);
+   if (ret) {
+   if (ret == -EACCES)
+   return batch_obj;


Shouldn't this be returning an error code ?
Good question. -EACCESS tells the caller of i915_parse_cmds() of a 
special case. There are some comments in its fnc header and implementation.


-EACCESS indicates that batch_obj contains a chained batch in which case 
we dispatch batch_obj as non-secure. We return batch_obj here b/c the 
logic below doesn't apply. I believe the reason we safely dispatch 
chained batches as non-secure is b/c Brad and others probably determined 
that there weren't any valid use cases where chained batches needed to 
be dispatched as secure. Leaving them non-secure, HW will NOP bad cmds 
and its not necessary for i915 to do parsing.


Thanks,
Mike





+   } else {
+   struct i915_vma *vma;
+
+   memset(shadow_exec_entry, 0,
sizeof(*shadow_exec_entry));
+
+   vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
+   vma->exec_entry = shadow_exec_entry;
+   vma->exec_entry->flags = __EXEC_OBJECT_PURGEABLE;
+   drm_gem_object_reference(&shadow_batch_obj->base);
+   list_add_tail(&vma->exec_list, &eb->vmas);
+
+   shadow_batch_obj->base.pending_read_domains =
+   batch_obj->base.pending_read_domains;
+
+   /*
+* Set the DISPATCH_SECURE bit to remove the
NON_SECURE
+* bit from MI_BATCH_BUFFER_START commands issued in
the
+* dispatch_execbuffer implementations. We specifically
+* don't want that set when the c

Re: [Intel-gfx] [PATCH] drm/i915/skl: Correcting the flushing of pipe

[shuang . he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: 
shuang...@intel.com)
-Summary-
Platform  Delta  drm-intel-nightly  Series Applied
PNV  364/364  364/364
ILK  +1-2  364/366  363/366
SNB  448/450  448/450
IVB  497/498  497/498
BYT  289/289  289/289
HSW  563/564  563/564
BDW  417/417  417/417
-Detailed-
Platform  Testdrm-intel-nightly  Series 
Applied
 ILK  igt_kms_flip_blocking-absolute-wf_vblank-interruptible  DMESG_WARN(1, 
M26)PASS(8, M26)  DMESG_WARN(1, M26)
 ILK  igt_kms_flip_flip-vs-rmfb-interruptible  NSPT(1, M26)PASS(6, M26) 
 NSPT(1, M26)
 ILK  igt_kms_flip_wf_vblank-ts-check  DMESG_WARN(7, M26)PASS(24, M26M37)   
   PASS(1, M26)
Note: You need to pay more attention to line start with '*'
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[Intel-gfx] [PATCH v7 4/5] drm/i915: Mark shadow batch buffers as purgeable

[michael . h . nguyen]

From: Brad Volkin 

By adding a new exec_entry flag, we cleanly mark the shadow objects
as purgeable after they are on the active list.

v2:
- Move 'shadow_batch_obj->madv = I915_MADV_WILLNEED' inside _get
  fnc (danvet, from v4 6/7 feedback)

v3:
- Remove duplicate 'madv = I915_MADV_WILLNEED' (danvet, from v6 4/5)

Issue: VIZ-4719
Signed-off-by: Brad Volkin 
---
 drivers/gpu/drm/i915/i915_gem_batch_pool.c | 2 ++
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 9 -
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_batch_pool.c 
b/drivers/gpu/drm/i915/i915_gem_batch_pool.c
index 6016125..c690170 100644
--- a/drivers/gpu/drm/i915/i915_gem_batch_pool.c
+++ b/drivers/gpu/drm/i915/i915_gem_batch_pool.c
@@ -131,5 +131,7 @@ i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool,
/* Keep list in LRU order */
list_move_tail(&obj->batch_pool_list, &pool->cache_list);
 
+   obj->madv = I915_MADV_WILLNEED;
+
return obj;
 }
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index fccfff5..9af4053 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -37,6 +37,7 @@
 #define  __EXEC_OBJECT_HAS_FENCE (1<<30)
 #define  __EXEC_OBJECT_NEEDS_MAP (1<<29)
 #define  __EXEC_OBJECT_NEEDS_BIAS (1<<28)
+#define  __EXEC_OBJECT_PURGEABLE (1<<27)
 
 #define BATCH_OFFSET_BIAS (256*1024)
 
@@ -226,7 +227,12 @@ i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
if (entry->flags & __EXEC_OBJECT_HAS_PIN)
vma->pin_count--;
 
-   entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
+   if (entry->flags & __EXEC_OBJECT_PURGEABLE)
+   obj->madv = I915_MADV_DONTNEED;
+
+   entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE |
+ __EXEC_OBJECT_HAS_PIN |
+ __EXEC_OBJECT_PURGEABLE);
 }
 
 static void eb_destroy(struct eb_vmas *eb)
@@ -1433,6 +1439,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
 
vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
vma->exec_entry = &shadow_exec_entry;
+   vma->exec_entry->flags = __EXEC_OBJECT_PURGEABLE;
drm_gem_object_reference(&shadow_batch_obj->base);
list_add_tail(&vma->exec_list, &eb->vmas);
 
-- 
1.9.1

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[Intel-gfx] [PATCH v7 3/5] drm/i915: Use batch length instead of object size in command parser

[michael . h . nguyen]

From: Brad Volkin 

Previously we couldn't trust the user-supplied batch length because
it came directly from userspace (i.e. untrusted code). It would have
affected what commands software parsed without regard to what hardware
would actually execute, leaving a potential hole.

With the parser now copying the user supplied batch buffer and writing
MI_NOP commands to any space after the copied region, we can safely use
the batch length input. This should be a performance win as the actual
batch length is frequently much smaller than the allocated object size.

v2: Fix handling of non-zero batch_start_offset

Issue: VIZ-4719
Signed-off-by: Brad Volkin 
---
 drivers/gpu/drm/i915/i915_cmd_parser.c | 48 --
 drivers/gpu/drm/i915/i915_drv.h|  1 +
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |  1 +
 3 files changed, 34 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c 
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 2a4ccac..a698b47 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -850,11 +850,19 @@ finish:
 
 /* Returns a vmap'd pointer to dest_obj, which the caller must unmap */
 static u32 *copy_batch(struct drm_i915_gem_object *dest_obj,
-  struct drm_i915_gem_object *src_obj)
+  struct drm_i915_gem_object *src_obj,
+  u32 batch_start_offset,
+  u32 batch_len)
 {
int ret = 0;
int needs_clflush = 0;
-   u32 *src_addr, *dest_addr = NULL;
+   u32 *src_base, *dest_base = NULL;
+   u32 *src_addr, *dest_addr;
+   u32 offset = batch_start_offset / sizeof(*dest_addr);
+   u32 end = batch_start_offset + batch_len;
+
+   if (end > dest_obj->base.size || end > src_obj->base.size)
+   return ERR_PTR(-E2BIG);
 
ret = i915_gem_obj_prepare_shmem_read(src_obj, &needs_clflush);
if (ret) {
@@ -862,15 +870,17 @@ static u32 *copy_batch(struct drm_i915_gem_object 
*dest_obj,
return ERR_PTR(ret);
}
 
-   src_addr = vmap_batch(src_obj);
-   if (!src_addr) {
+   src_base = vmap_batch(src_obj);
+   if (!src_base) {
DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n");
ret = -ENOMEM;
goto unpin_src;
}
 
+   src_addr = src_base + offset;
+
if (needs_clflush)
-   drm_clflush_virt_range((char *)src_addr, src_obj->base.size);
+   drm_clflush_virt_range((char *)src_addr, batch_len);
 
ret = i915_gem_object_set_to_cpu_domain(dest_obj, true);
if (ret) {
@@ -878,24 +888,27 @@ static u32 *copy_batch(struct drm_i915_gem_object 
*dest_obj,
goto unmap_src;
}
 
-   dest_addr = vmap_batch(dest_obj);
-   if (!dest_addr) {
+   dest_base = vmap_batch(dest_obj);
+   if (!dest_base) {
DRM_DEBUG_DRIVER("CMD: Failed to vmap shadow batch\n");
ret = -ENOMEM;
goto unmap_src;
}
 
-   memcpy(dest_addr, src_addr, src_obj->base.size);
-   if (dest_obj->base.size > src_obj->base.size)
-   memset((u8 *)dest_addr + src_obj->base.size, 0,
-  dest_obj->base.size - src_obj->base.size);
+   dest_addr = dest_base + offset;
+
+   if (batch_start_offset != 0)
+   memset((u8 *)dest_base, 0, batch_start_offset);
+
+   memcpy(dest_addr, src_addr, batch_len);
+   memset((u8 *)dest_addr + batch_len, 0, dest_obj->base.size - end);
 
 unmap_src:
-   vunmap(src_addr);
+   vunmap(src_base);
 unpin_src:
i915_gem_object_unpin_pages(src_obj);
 
-   return ret ? ERR_PTR(ret) : dest_addr;
+   return ret ? ERR_PTR(ret) : dest_base;
 }
 
 /**
@@ -1016,6 +1029,7 @@ static bool check_cmd(const struct intel_engine_cs *ring,
  * @batch_obj: the batch buffer in question
  * @shadow_batch_obj: copy of the batch buffer in question
  * @batch_start_offset: byte offset in the batch at which execution starts
+ * @batch_len: length of the commands in batch_obj
  * @is_master: is the submitting process the drm master?
  *
  * Parses the specified batch buffer looking for privilege violations as
@@ -1028,6 +1042,7 @@ int i915_parse_cmds(struct intel_engine_cs *ring,
struct drm_i915_gem_object *batch_obj,
struct drm_i915_gem_object *shadow_batch_obj,
u32 batch_start_offset,
+   u32 batch_len,
bool is_master)
 {
int ret = 0;
@@ -1035,7 +1050,8 @@ int i915_parse_cmds(struct intel_engine_cs *ring,
struct drm_i915_cmd_descriptor default_desc = { 0 };
bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */
 
-   batch_base = copy_batch(shadow_batch_obj, batch_obj);
+   batch_base = copy_batch(shadow_batch_obj, batch_obj,
+   batch_start_offset, b

[Intel-gfx] [PATCH v7 1/5] drm/i915: Implement a framework for batch buffer pools

[michael . h . nguyen]

From: Brad Volkin 

This adds a small module for managing a pool of batch buffers.
The only current use case is for the command parser, as described
in the kerneldoc in the patch. The code is simple, but separating
it out makes it easier to change the underlying algorithms and to
extend to future use cases should they arise.

The interface is simple: init to create an empty pool, fini to
clean it up, get to obtain a new buffer. Note that all buffers are
expected to be inactive before cleaning up the pool.

Locking is currently based on the caller holding the struct_mutex.
We already do that in the places where we will use the batch pool
for the command parser.

v2:
- s/BUG_ON/WARN_ON/ for locking assertions
- Remove the cap on pool size
- Switch from alloc/free to init/fini

v3:
- Idiomatic looping structure in _fini
- Correct handling of purged objects
- Don't return a buffer that's too much larger than needed

v4:
- Rebased to latest -nightly

v5:
- Remove _put() function and clean up comments to match

v6:
- Move purged check inside the loop (danvet, from v4 1/7 feedback)

v7:
- Use single list instead of two. (Chris W)
- s/active_list/cache_list
- Squashed in debug patches (Chris W)
  drm/i915: Add a batch pool debugfs file

  It provides some useful information about the buffers in
  the global command parser batch pool.

  v2: rebase on global pool instead of per-ring pools
  v3: rebase

  drm/i915: Add batch pool details to i915_gem_objects debugfs

  To better account for the potentially large memory consumption
  of the batch pool.

v8:
- Keep cache in LRU order (danvet, from v6 1/5 feedback)

Issue: VIZ-4719
Signed-off-by: Brad Volkin 
---
 Documentation/DocBook/drm.tmpl |   5 ++
 drivers/gpu/drm/i915/Makefile  |   1 +
 drivers/gpu/drm/i915/i915_debugfs.c|  71 +--
 drivers/gpu/drm/i915/i915_drv.h|  21 +
 drivers/gpu/drm/i915/i915_gem.c|   1 +
 drivers/gpu/drm/i915/i915_gem_batch_pool.c | 135 +
 6 files changed, 225 insertions(+), 9 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_gem_batch_pool.c

diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index 25c23ca..21cbcdb 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -4059,6 +4059,11 @@ int num_ioctls;
 !Idrivers/gpu/drm/i915/i915_cmd_parser.c
   
   
+Batchbuffer Pools
+!Pdrivers/gpu/drm/i915/i915_gem_batch_pool.c batch pool
+!Idrivers/gpu/drm/i915/i915_gem_batch_pool.c
+  
+  
 Logical Rings, Logical Ring Contexts and Execlists
 !Pdrivers/gpu/drm/i915/intel_lrc.c Logical Rings, Logical Ring Contexts and 
Execlists
 !Idrivers/gpu/drm/i915/intel_lrc.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3cf70a6..1849ffa 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -19,6 +19,7 @@ i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o
 
 # GEM code
 i915-y += i915_cmd_parser.o \
+ i915_gem_batch_pool.o \
  i915_gem_context.o \
  i915_gem_render_state.o \
  i915_gem_debug.o \
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 479e0c1..5d96d94 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -359,6 +359,33 @@ static int per_file_stats(int id, void *ptr, void *data)
return 0;
 }
 
+#define print_file_stats(m, name, stats) \
+   seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu 
global, %zu shared, %zu unbound)\n", \
+  name, \
+  stats.count, \
+  stats.total, \
+  stats.active, \
+  stats.inactive, \
+  stats.global, \
+  stats.shared, \
+  stats.unbound)
+
+static void print_batch_pool_stats(struct seq_file *m,
+  struct drm_i915_private *dev_priv)
+{
+   struct drm_i915_gem_object *obj;
+   struct file_stats stats;
+
+   memset(&stats, 0, sizeof(stats));
+
+   list_for_each_entry(obj,
+   &dev_priv->mm.batch_pool.cache_list,
+   batch_pool_list)
+   per_file_stats(0, obj, &stats);
+
+   print_file_stats(m, "batch pool", stats);
+}
+
 #define count_vmas(list, member) do { \
list_for_each_entry(vma, list, member) { \
size += i915_gem_obj_ggtt_size(vma->obj); \
@@ -441,6 +468,9 @@ static int i915_gem_object_info(struct seq_file *m, void* 
data)
   dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 
seq_putc(m, '\n');
+   print_batch_pool_stats(m, dev_priv);
+
+   seq_putc(m, '\n');
list_for_each_entry_reverse(file, &dev->filelist, lhead) {
struct file_stats stats;
struct task_struct *task;
@@ -458,15 +488,7 @@ sta

[Intel-gfx] [PATCH v7 5/5] drm/i915: Tidy up execbuffer command parsing code

[michael . h . nguyen]

From: Brad Volkin 

Move it to a separate function since the main do_execbuffer function
already has so much going on.

v2:
- Move pin/unpin calls inside i915_parse_cmds() (Chris W, v4 7/7
  feedback)

Issue: VIZ-4719
Signed-off-by: Brad Volkin 
---
 drivers/gpu/drm/i915/i915_cmd_parser.c |   8 ++
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 124 -
 2 files changed, 77 insertions(+), 55 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c 
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index a698b47..0d757cd 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -1050,10 +1050,17 @@ int i915_parse_cmds(struct intel_engine_cs *ring,
struct drm_i915_cmd_descriptor default_desc = { 0 };
bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */
 
+   ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 4096, 0);
+   if (ret) {
+   DRM_DEBUG_DRIVER("CMD: Failed to pin shadow batch\n");
+   return -1;
+   }
+
batch_base = copy_batch(shadow_batch_obj, batch_obj,
batch_start_offset, batch_len);
if (IS_ERR(batch_base)) {
DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n");
+   i915_gem_object_ggtt_unpin(shadow_batch_obj);
return PTR_ERR(batch_base);
}
 
@@ -1124,6 +1131,7 @@ int i915_parse_cmds(struct intel_engine_cs *ring,
}
 
vunmap(batch_base);
+   i915_gem_object_ggtt_unpin(shadow_batch_obj);
 
return ret;
 }
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 9af4053..3d36465 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1069,6 +1069,65 @@ i915_emit_box(struct intel_engine_cs *ring,
return 0;
 }
 
+static struct drm_i915_gem_object*
+i915_gem_execbuffer_parse(struct intel_engine_cs *ring,
+ struct drm_i915_gem_exec_object2 *shadow_exec_entry,
+ struct eb_vmas *eb,
+ struct drm_i915_gem_object *batch_obj,
+ u32 batch_start_offset,
+ u32 batch_len,
+ bool is_master,
+ u32 *flags)
+{
+   struct drm_i915_private *dev_priv = to_i915(batch_obj->base.dev);
+   struct drm_i915_gem_object *shadow_batch_obj;
+   int ret;
+
+   shadow_batch_obj = i915_gem_batch_pool_get(&dev_priv->mm.batch_pool,
+  batch_obj->base.size);
+   if (IS_ERR(shadow_batch_obj))
+   return shadow_batch_obj;
+
+   ret = i915_parse_cmds(ring,
+ batch_obj,
+ shadow_batch_obj,
+ batch_start_offset,
+ batch_len,
+ is_master);
+   if (ret) {
+   if (ret == -EACCES)
+   return batch_obj;
+   } else {
+   struct i915_vma *vma;
+
+   memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry));
+
+   vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
+   vma->exec_entry = shadow_exec_entry;
+   vma->exec_entry->flags = __EXEC_OBJECT_PURGEABLE;
+   drm_gem_object_reference(&shadow_batch_obj->base);
+   list_add_tail(&vma->exec_list, &eb->vmas);
+
+   shadow_batch_obj->base.pending_read_domains =
+   batch_obj->base.pending_read_domains;
+
+   /*
+* Set the DISPATCH_SECURE bit to remove the NON_SECURE
+* bit from MI_BATCH_BUFFER_START commands issued in the
+* dispatch_execbuffer implementations. We specifically
+* don't want that set when the command parser is
+* enabled.
+*
+* FIXME: with aliasing ppgtt, buffers that should only
+* be in ggtt still end up in the aliasing ppgtt. remove
+* this check when that is fixed.
+*/
+   if (USES_FULL_PPGTT(dev))
+   *flags |= I915_DISPATCH_SECURE;
+   }
+
+   return ret ? ERR_PTR(ret) : shadow_batch_obj;
+}
 
 int
 i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file,
@@ -1286,7 +1345,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
struct drm_i915_private *dev_priv = dev->dev_private;
struct eb_vmas *eb;
struct drm_i915_gem_object *batch_obj;
-   struct drm_i915_gem_object *shadow_batch_obj = NULL;
struct drm_i915_gem_exec_object2 shadow_exec_entry;
struct intel_engine_cs *ring;
struct intel_context *ctx;
@@ -1406,62 +1464,18 @@ i915_gem_do_execbuffer(struct drm_device *dev, void 
*data,
}
 

[Intel-gfx] [PATCH v7 0/5] Command parser batch buffer copy

[michael . h . nguyen]

From: "Michael H. Nguyen" 

This is v7 in response to 
http://lists.freedesktop.org/archives/intel-gfx/2014-December/057033.html

Minor updates from the last rev
- Keep batch pool in LRU order (Daniel)
- Remove duplicate madv assignments (Daniel)

Brad Volkin (5):
  drm/i915: Implement a framework for batch buffer pools
  drm/i915: Use batch pools with the command parser
  drm/i915: Use batch length instead of object size in command parser
  drm/i915: Mark shadow batch buffers as purgeable
  drm/i915: Tidy up execbuffer command parsing code

 Documentation/DocBook/drm.tmpl |   5 ++
 drivers/gpu/drm/i915/Makefile  |   1 +
 drivers/gpu/drm/i915/i915_cmd_parser.c |  99 +
 drivers/gpu/drm/i915/i915_debugfs.c|  71 +--
 drivers/gpu/drm/i915/i915_dma.c|   1 +
 drivers/gpu/drm/i915/i915_drv.h|  23 +
 drivers/gpu/drm/i915/i915_gem.c|   3 +
 drivers/gpu/drm/i915/i915_gem_batch_pool.c | 137 +
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |  98 +
 9 files changed, 396 insertions(+), 42 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_gem_batch_pool.c

-- 
1.9.1

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[Intel-gfx] [PATCH v7 2/5] drm/i915: Use batch pools with the command parser

[michael . h . nguyen]

From: Brad Volkin 

This patch sets up all of the tracking and copying necessary to
use batch pools with the command parser and dispatches the copied
(shadow) batch to the hardware.

After this patch, the parser is in 'enabling' mode.

Note that performance takes a hit from the copy in some cases
and will likely need some work. At a rough pass, the memcpy
appears to be the bottleneck. Without having done a deeper
analysis, two ideas that come to mind are:
1) Copy sections of the batch at a time, as they are reached
   by parsing. Might improve cache locality.
2) Copy only up to the userspace-supplied batch length and
   memset the rest of the buffer. Reduces the number of reads.

v2:
- Remove setting the capacity of the pool
- One global pool instead of per-ring pools
- Replace batch_obj with shadow_batch_obj and hook into eb->vmas
- Memset any space in the shadow batch beyond what gets copied
- Rebased on execlist prep refactoring

v3:
- Rebase on chained batch handling
- Squash in setting the secure dispatch flag
- Add a note about the interaction w/secure dispatch pinning
- Check for request->batch_obj == NULL in i915_gem_free_request

v4:
- Fix read domains for shadow_batch_obj
- Remove the set_to_gtt_domain call from i915_parse_cmds
- ggtt_pin/unpin in the parser block to simplify error handling
- Check USES_FULL_PPGTT before setting DISPATCH_SECURE flag
- Remove i915_gem_batch_pool_put calls

v5:
- Move 'pending_read_domains |= I915_GEM_DOMAIN_COMMAND' after
  the parser (danvet, from v4 0/7 feedback)

Issue: VIZ-4719
Signed-off-by: Brad Volkin 
---
 drivers/gpu/drm/i915/i915_cmd_parser.c | 79 +++---
 drivers/gpu/drm/i915/i915_dma.c|  1 +
 drivers/gpu/drm/i915/i915_drv.h|  1 +
 drivers/gpu/drm/i915/i915_gem.c|  2 +
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 52 +---
 5 files changed, 112 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c 
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index b882bf2..2a4ccac 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -848,6 +848,56 @@ finish:
return (u32*)addr;
 }
 
+/* Returns a vmap'd pointer to dest_obj, which the caller must unmap */
+static u32 *copy_batch(struct drm_i915_gem_object *dest_obj,
+  struct drm_i915_gem_object *src_obj)
+{
+   int ret = 0;
+   int needs_clflush = 0;
+   u32 *src_addr, *dest_addr = NULL;
+
+   ret = i915_gem_obj_prepare_shmem_read(src_obj, &needs_clflush);
+   if (ret) {
+   DRM_DEBUG_DRIVER("CMD: failed to prep read\n");
+   return ERR_PTR(ret);
+   }
+
+   src_addr = vmap_batch(src_obj);
+   if (!src_addr) {
+   DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n");
+   ret = -ENOMEM;
+   goto unpin_src;
+   }
+
+   if (needs_clflush)
+   drm_clflush_virt_range((char *)src_addr, src_obj->base.size);
+
+   ret = i915_gem_object_set_to_cpu_domain(dest_obj, true);
+   if (ret) {
+   DRM_DEBUG_DRIVER("CMD: Failed to set batch CPU domain\n");
+   goto unmap_src;
+   }
+
+   dest_addr = vmap_batch(dest_obj);
+   if (!dest_addr) {
+   DRM_DEBUG_DRIVER("CMD: Failed to vmap shadow batch\n");
+   ret = -ENOMEM;
+   goto unmap_src;
+   }
+
+   memcpy(dest_addr, src_addr, src_obj->base.size);
+   if (dest_obj->base.size > src_obj->base.size)
+   memset((u8 *)dest_addr + src_obj->base.size, 0,
+  dest_obj->base.size - src_obj->base.size);
+
+unmap_src:
+   vunmap(src_addr);
+unpin_src:
+   i915_gem_object_unpin_pages(src_obj);
+
+   return ret ? ERR_PTR(ret) : dest_addr;
+}
+
 /**
  * i915_needs_cmd_parser() - should a given ring use software command parsing?
  * @ring: the ring in question
@@ -964,6 +1014,7 @@ static bool check_cmd(const struct intel_engine_cs *ring,
  * i915_parse_cmds() - parse a submitted batch buffer for privilege violations
  * @ring: the ring on which the batch is to execute
  * @batch_obj: the batch buffer in question
+ * @shadow_batch_obj: copy of the batch buffer in question
  * @batch_start_offset: byte offset in the batch at which execution starts
  * @is_master: is the submitting process the drm master?
  *
@@ -975,32 +1026,28 @@ static bool check_cmd(const struct intel_engine_cs *ring,
  */
 int i915_parse_cmds(struct intel_engine_cs *ring,
struct drm_i915_gem_object *batch_obj,
+   struct drm_i915_gem_object *shadow_batch_obj,
u32 batch_start_offset,
bool is_master)
 {
int ret = 0;
u32 *cmd, *batch_base, *batch_end;
struct drm_i915_cmd_descriptor default_desc = { 0 };
-   int needs_clflush = 0;
bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */
 
-   ret

[Intel-gfx] [PATCH] drm/i915: Add GPGPU_THREADS_DISPATCHED to the register whitelist

[Jordan Justen]

This will allow us to read the number of dispatched compute threads
for GL_ARB_pipeline_statistics_query.

Signed-off-by: Jordan Justen 
Cc: Ben Widawsky 
---
 drivers/gpu/drm/i915/i915_cmd_parser.c |  4 +++-
 drivers/gpu/drm/i915/i915_reg.h| 23 ---
 2 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c 
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 6e9eac4..82679c9 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -401,6 +401,7 @@ static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] 
= {
 #define REG64(addr) (addr), (addr + sizeof(u32))
 
 static const u32 gen7_render_regs[] = {
+   REG64(GPGPU_THREADS_DISPATCHED),
REG64(HS_INVOCATION_COUNT),
REG64(DS_INVOCATION_COUNT),
REG64(IA_VERTICES_COUNT),
@@ -1076,6 +1077,7 @@ int i915_cmd_parser_get_version(void)
 *hardware parsing enabled (so does not allow new use cases).
 * 2. Allow access to the MI_PREDICATE_SRC0 and
 *MI_PREDICATE_SRC1 registers.
+* 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
 */
-   return 2;
+   return 3;
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 869e5ae..0e6e694 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -460,17 +460,18 @@
  */
 #define BCS_SWCTRL 0x22200
 
-#define HS_INVOCATION_COUNT 0x2300
-#define DS_INVOCATION_COUNT 0x2308
-#define IA_VERTICES_COUNT   0x2310
-#define IA_PRIMITIVES_COUNT 0x2318
-#define VS_INVOCATION_COUNT 0x2320
-#define GS_INVOCATION_COUNT 0x2328
-#define GS_PRIMITIVES_COUNT 0x2330
-#define CL_INVOCATION_COUNT 0x2338
-#define CL_PRIMITIVES_COUNT 0x2340
-#define PS_INVOCATION_COUNT 0x2348
-#define PS_DEPTH_COUNT  0x2350
+#define GPGPU_THREADS_DISPATCHED0x2290
+#define HS_INVOCATION_COUNT 0x2300
+#define DS_INVOCATION_COUNT 0x2308
+#define IA_VERTICES_COUNT   0x2310
+#define IA_PRIMITIVES_COUNT 0x2318
+#define VS_INVOCATION_COUNT 0x2320
+#define GS_INVOCATION_COUNT 0x2328
+#define GS_PRIMITIVES_COUNT 0x2330
+#define CL_INVOCATION_COUNT 0x2338
+#define CL_PRIMITIVES_COUNT 0x2340
+#define PS_INVOCATION_COUNT 0x2348
+#define PS_DEPTH_COUNT  0x2350
 
 /* There are the 4 64-bit counter registers, one for each stream output */
 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
-- 
2.1.3

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Re: [Intel-gfx] [PATCH v2] drm/i915/bdw: Enable execlists by default where supported

[shuang . he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: 
shuang...@intel.com)
-Summary-
Platform  Delta  drm-intel-nightly  Series Applied
PNV  364/364  364/364
ILK  +1 364/366  365/366
SNB  448/450  448/450
IVB  497/498  497/498
BYT  289/289  289/289
HSW -1  563/564  562/564
BDW  417/417  417/417
-Detailed-
Platform  Testdrm-intel-nightly  Series 
Applied
 ILK  igt_kms_flip_wf_vblank-ts-check  DMESG_WARN(7, M26)PASS(25, M26M37)   
   PASS(1, M37)
*HSW  igt_pm_rpm_dpms-mode-unset-non-lpsp  PASS(3, M40)  DMESG_WARN(1, 
M40)
Note: You need to pay more attention to line start with '*'
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Re: [Intel-gfx] [PATCH 5/5] drm/i915/opregion: start using extended didl

[shuang . he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: 
shuang...@intel.com)
-Summary-
Platform  Delta  drm-intel-nightly  Series Applied
PNV  364/364  364/364
ILK  +1-3  364/366  362/366
SNB  448/450  448/450
IVB  497/498  497/498
BYT  289/289  289/289
HSW  563/564  563/564
BDW  417/417  417/417
-Detailed-
Platform  Testdrm-intel-nightly  Series 
Applied
*ILK  igt_kms_setmode_invalid-clone-exclusive-crtc  PASS(6, M26)  
DMESG_WARN(1, M26)
*ILK  igt_kms_flip_plain-flip-fb-recreate-interruptible  DMESG_WARN(1, 
M26)PASS(4, M26)  NSPT(1, M26)
 ILK  igt_kms_flip_rcs-flip-vs-modeset  NSPT(1, M26)PASS(5, M26)  
NSPT(1, M26)
 ILK  igt_kms_flip_wf_vblank-ts-check  DMESG_WARN(7, M26)PASS(26, M26M37)   
   PASS(1, M26)
Note: You need to pay more attention to line start with '*'
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Re: [Intel-gfx] [PATCH] drm/i915: Add GPGPU_THREADS_DISPATCHED to the register whitelist

[Ben Widawsky]

On Thu, Dec 11, 2014 at 01:28:09PM -0800, Jordan Justen wrote:
> This will allow us to read the number of dispatched compute threads
> for GL_ARB_pipeline_statistics_query.
> 
> Signed-off-by: Jordan Justen 
> Cc: Ben Widawsky 
Reviewed-by: Ben Widawsky 

[snip]


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[Intel-gfx] [PATCH] drm/i915: Refactor work that can sleep out of commit (v4)

[Matt Roper]

Once we integrate our work into the atomic pipeline, plane commit
operations will need to happen with interrupts disabled, due to vblank
evasion.  Our commit functions today include sleepable work, so those
operations need to be split out and run either before or after the
atomic register programming.

The solution here calculates which of those operations will need to be
performed during the 'check' phase and sets flags in an intel_crtc
sub-struct.  New intel_begin_crtc_commit() and
intel_finish_crtc_commit() functions are added before and after the
actual register programming; these will eventually be called from the
atomic plane helper's .atomic_begin() and .atomic_end() entrypoints.

v2: Fix broken sprite code split

v3: Make the pre/post commit work crtc-based to match how we eventually
want this to be called from the atomic plane helpers.

v4: Some platforms that haven't had their watermark code reworked were
waiting for vblank, then calling update_sprite_watermarks in their
platform-specific disable code.  These also need to be flagged out
of the critical section.

Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/intel_display.c | 180 ++-
 drivers/gpu/drm/i915/intel_drv.h |  31 ++
 drivers/gpu/drm/i915/intel_sprite.c  |  78 ++-
 3 files changed, 178 insertions(+), 111 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3044af5..5d90114 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11737,7 +11737,11 @@ static int
 intel_check_primary_plane(struct drm_plane *plane,
  struct intel_plane_state *state)
 {
+   struct drm_device *dev = plane->dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_crtc *crtc = state->base.crtc;
+   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+   struct intel_plane *intel_plane = to_intel_plane(plane);
struct drm_framebuffer *fb = state->base.fb;
struct drm_rect *dest = &state->dst;
struct drm_rect *src = &state->src;
@@ -11758,6 +11762,40 @@ intel_check_primary_plane(struct drm_plane *plane,
return -EBUSY;
}
 
+   if (intel_crtc->active) {
+   /*
+* FBC does not work on some platforms for rotated
+* planes, so disable it when rotation is not 0 and
+* update it when rotation is set back to 0.
+*
+* FIXME: This is redundant with the fbc update done in
+* the primary plane enable function except that that
+* one is done too late. We eventually need to unify
+* this.
+*/
+   if (intel_crtc->primary_enabled &&
+   INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
+   dev_priv->fbc.plane == intel_crtc->plane &&
+   intel_plane->rotation != BIT(DRM_ROTATE_0)) {
+   intel_crtc->atomic.disable_fbc = true;
+   }
+
+   if (state->visible) {
+   /*
+* BDW signals flip done immediately if the plane
+* is disabled, even if the plane enable is already
+* armed to occur at the next vblank :(
+*/
+   if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
+   intel_crtc->atomic.wait_vblank = true;
+   }
+
+   intel_crtc->atomic.fb_bits |=
+   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
+
+   intel_crtc->atomic.update_fbc = true;
+   }
+
return 0;
 }
 
@@ -11773,18 +11811,6 @@ intel_commit_primary_plane(struct drm_plane *plane,
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
struct intel_plane *intel_plane = to_intel_plane(plane);
struct drm_rect *src = &state->src;
-   enum pipe pipe = intel_plane->pipe;
-
-   if (!fb) {
-   /*
-* 'prepare' is never called when plane is being disabled, so
-* we need to handle frontbuffer tracking here
-*/
-   mutex_lock(&dev->struct_mutex);
-   i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
- INTEL_FRONTBUFFER_PRIMARY(pipe));
-   mutex_unlock(&dev->struct_mutex);
-   }
 
plane->fb = fb;
crtc->x = src->x1 >> 16;
@@ -11801,26 +11827,7 @@ intel_commit_primary_plane(struct drm_plane *plane,
intel_plane->obj = obj;
 
if (intel_crtc->active) {
-   /*
-* FBC does not work on some platforms for rotated
-* planes, so disable it when rotation is not 0 and
-* update it when rotation is set back to 0.
-*
-  

[Intel-gfx] [PATCH] drm/i915: Prepare for atomic plane helpers (v7)

[Matt Roper]

Add the new driver entrypoints that will be called by the atomic plane
helpers.

This patch does not actually switch over to the new plane helpers yet,
so there should be no functional change here.  Also note that although
plane programming was already split into check/prepare/commit steps,
some of the semantics of those individual functions will need to change
slightly when we do make the jump so that they match the behavior the
plane helpers expect.

v2:
 - Renamed file from intel_atomic.c to intel_atomic_plane.c (Daniel)
 - Fix a copy/paste comment mistake (Bob)

v3:
 - Use prepare/cleanup functions that we've already factored out
 - Use newly refactored pre_commit/commit/post_commit to avoid sleeping
   during vblank evasion

v4:
 - Rebase to latest di-nightly requires adding an 'old_state' parameter
   to atomic_update;

v5:
 - Must have botched a rebase somewhere and lost some work.  Restore
   state 'dirty' flag to let begin/end code know which planes to
   run the pre_commit/post_commit hooks for.  This would have actually
   shown up as broken in the next commit rather than this one.

v6:
 - Squash kerneldoc patch into this one.
 - Previous patches have now already taken care of most of the
   infrastructure that used to be in this patch.  All we're adding here
   now is some thin wrappers.

v7:
 - Check return of intel_plane_duplicate_state() for allocation
   failures.

Signed-off-by: Matt Roper 
---
 Documentation/DocBook/drm.tmpl|   5 +
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/intel_atomic_plane.c | 150 ++
 drivers/gpu/drm/i915/intel_display.c  |  32 ++-
 drivers/gpu/drm/i915/intel_drv.h  |   8 ++
 drivers/gpu/drm/i915/intel_sprite.c   |  12 +++
 6 files changed, 207 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/intel_atomic_plane.c

diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index 25c23ca..7c5207b 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -3932,6 +3932,11 @@ int num_ioctls;
 
   
   
+Atomic Plane Helpers
+!Pdrivers/gpu/drm/i915/intel_atomic_plane.c atomic plane helpers
+!Idrivers/gpu/drm/i915/intel_atomic_plane.c
+  
+  
 Output Probing
 
  This section covers output probing and related infrastructure like the
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3cf70a6..4a6ced7 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -65,6 +65,7 @@ i915-y += dvo_ch7017.o \
  dvo_ns2501.o \
  dvo_sil164.o \
  dvo_tfp410.o \
+ intel_atomic_plane.o \
  intel_crt.o \
  intel_ddi.o \
  intel_dp.o \
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c 
b/drivers/gpu/drm/i915/intel_atomic_plane.c
new file mode 100644
index 000..286fec8
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+ * DOC: atomic plane helper support
+ *
+ * The functions here are used by the atomic plane helper functions to
+ * implement legacy plane updates (i.e., drm_plane->update_plane() and
+ * drm_plane->disable_plane()).  This allows plane updates to use the
+ * atomic state infrastructure and perform plane updates as separate
+ * prepare/check/commit/cleanup steps.
+ */
+
+#include 
+#include 
+#include 
+#include "intel_drv.h"
+
+/**
+ * intel_plane_duplicate_state - duplicate plane state
+ * @plane: drm plane
+ *
+ * Allocates and returns a copy of the plane state (both common and
+ * Intel-specific) for the specified plane.
+ *
+ * Returns: The newly allocated plane state, or NULL or failure.
+ */
+struct drm_plane_state *
+intel_plane_duplicate_state(struct drm_plane *

[Intel-gfx] [PATCH v2] drm/i915/chv: Use timeout mode for RC6 on chv

[deepak . s]

From: Deepak S 

Higher RC6 residency is observed using timeout mode
instead of EI mode. It's Recommended to use TO Method for RC6.

v2: Add comment about timeout threshold. (Tom)

Signed-off-by: Deepak S 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/intel_pm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2316d23..2acb3de 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4689,7 +4689,8 @@ static void cherryview_enable_rps(struct drm_device *dev)
I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
I915_WRITE(GEN6_RC_SLEEP, 0);
 
-   I915_WRITE(GEN6_RC6_THRESHOLD, 5); /* 50/125ms per EI */
+   /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */
+   I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
 
/* allows RC6 residency counter to work */
I915_WRITE(VLV_COUNTER_CONTROL,
@@ -4703,7 +4704,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
/* 3: Enable RC6 */
if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
(pcbr >> VLV_PCBR_ADDR_SHIFT))
-   rc6_mode = GEN6_RC_CTL_EI_MODE(1);
+   rc6_mode = GEN7_RC_CTL_TO_MODE;
 
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
 
-- 
1.9.1

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[Intel-gfx] [QA 12/12 ww50] Testing report for `drm-intel-testing` (was: Updated -next)

[Zheng, Jeff]

Summary
We covered the platform: Braswell, Broadwell, Baytrail, Haswell, Ivybridge, 
Ironlake

In this circle, 3 new bugs are filed:
87253

[BSW drm-intel-fixes]Display is blank after system boots

87223

[BSW] eDP screen is blank when booting with DP display connected

87220

[BDW-H]VGA port unable to work



Test Environment
Kernel version:
drm-intel-testing 2014_12_06


Kernel: (drm-intel-testing) c3e107ab06274aa47f082df40ee4365e480e7b2a

Machine Details:
Platform

Machines

BSW

x-bsw04

BDW

x-bdwh01

BYT

x-bytm01

HSW

x-hsw26

SNB

x-sgb4

ILK

x-e6510



Power saving measurement :

HSWU36

drm-intel-testing-12-06

save consumption

i915.enable_fbc=1

4.12%

i915.enable_fbc=1=-1 (default)disable


i915.disable_power_well=1

0.23%

i915.disable_power_well=0

BDW21

drm-intel-testing-12-06

save consumption

i915.enable_fbc=1

0.71%

i915.enable_fbc=1=-1 (default)disable


i915.disable_power_well=1

0.71%



Bests
Jeff

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Re: [Intel-gfx] [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT

[Singh, Gaurav K]

On 12/10/2014 7:38 PM, Gaurav K Singh wrote:

For CHT changes are required for calculating the correct m,n & p with
minimal error +/- for the required DSI clock, so that the correct dividor
& ctrl values are written in cck regs for DSI. This patch has been tested
on CHT RVP with 1200 x 1920 panel.

Signed-off-by: Gaurav K Singh 
---
  drivers/gpu/drm/i915/intel_dsi_pll.c |   43 ++
  1 file changed, 33 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c 
b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 8957f10..9236b66 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -162,7 +162,8 @@ static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, 
int lane_count)
  
  #endif
  
-static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)

+static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
+   u32 dsi_clk, struct dsi_mnp *dsi_mnp)
  {
u32 m, n, p;
u32 ref_clk;
@@ -173,6 +174,10 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp 
*dsi_mnp)
u32 calc_m;
u32 calc_p;
u32 m_seed;
+   u32 m_start;
+   u32 m_limit;
+   u32 n_limit;
+   u32 p_limit;
  
  	/* dsi_clk is expected in KHZ */

if (dsi_clk < 30 || dsi_clk > 115) {
@@ -180,18 +185,33 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp 
*dsi_mnp)
return -ECHRNG;
}
  
-	ref_clk = 25000;

+   if (IS_CHERRYVIEW(dev_priv->dev)) {
+   ref_clk = 10;
+   m_start = 70;
+   m_limit = 96;
+   n_limit = 4;
+   p_limit = 6;
+   } else if (IS_VALLEYVIEW(dev_priv->dev)) {
+   ref_clk = 25000;
+   m_start = 62;
+   m_limit = 92;
+   n_limit = 1;
+   p_limit = 6;
+   } else {
+   DRM_ERROR("Unsupported device\n");
+   return -ENODEV;
+   }
target_dsi_clk = dsi_clk;
error = 0x;
tmp_error = 0x;
calc_m = 0;
calc_p = 0;
  
-	for (m = 62; m <= 92; m++) {

-   for (p = 2; p <= 6; p++) {
+   for (m = m_start; m <= m_limit; m++) {
+   for (p = 2; p <= p_limit; p++) {
/* Find the optimal m and p divisors
   with minimal error +/- the required clock */
-   calc_dsi_clk = (m * ref_clk) / p;
+   calc_dsi_clk = (m * ref_clk) / (p * n_limit);
if (calc_dsi_clk == target_dsi_clk) {
calc_m = m;
calc_p = p;
@@ -212,11 +232,14 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp 
*dsi_mnp)
}
  
  	m_seed = lfsr_converts[calc_m - 62];

-   n = 1;
+   n = n_limit;
dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
-   dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
-   m_seed << DSI_PLL_M1_DIV_SHIFT;
-
+   if (IS_CHERRYVIEW(dev_priv->dev))
+   dsi_mnp->dsi_pll_div = (n/2) << DSI_PLL_N1_DIV_SHIFT |
+   m_seed << DSI_PLL_M1_DIV_SHIFT;
+   else
+   dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
+   m_seed << DSI_PLL_M1_DIV_SHIFT;
return 0;
  }
  
@@ -235,7 +258,7 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)

dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
intel_dsi->lane_count);
  
-	ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);

+   ret = dsi_calc_mnp(dev_priv, dsi_clk, &dsi_mnp);
if (ret) {
DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
return;

Hi Jani,

Could you please review this patch?

With regards,
Gaurav

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