Re: [Intel-gfx] [i915] WARNING: [...] drivers/gpu/drm/i915/intel_display.c:9948 intel_get_pipe_from_connector
Should be fixed with commit 7c063c725987406d743cc7de7625ff224fab75de Author: Jesse Barnes Date: Tue Nov 26 09:13:41 2013 -0800 drm/i915: take mode config lock around crtc disable at suspend which is currently in drm-intel-fixes. I'll forward it early next week. -Daniel On Sat, Nov 30, 2013 at 9:38 PM, Paul Bolle wrote: > On both v3.13-rc1 and v3.13-rc2 is see this at every boot and during > every suspend and resume cycle: > > <4>[2.682468] WARNING: CPU: 0 PID: 173 at > drivers/gpu/drm/i915/intel_display.c:9948 > intel_get_pipe_from_connector+0x42/0x50 [i915]() > <5>[2.682470] Modules linked in: i915(F+) ata_generic(F) pata_acpi(F) > yenta_socket(F+) i2c_algo_bit(F) drm_kms_helper(F) tg3(F+) ptp(F) pps_core(F) > drm(F) i2c_core(F) video(F) sunrpc(F) > <5>[2.682489] CPU: 0 PID: 173 Comm: systemd-udevd Tainted: GF > 3.13.0-0.rc2.1.local0.fc18.i686 #1 > <5>[2.682492] Hardware name: IBM 2525FAG/2525FAG, BIOS 74ET61WW (2.06 ) > 03/14/2006 > <5>[2.682495] f54739f4 c09b66d2 f5473a24 > c0449b14 c0b541a4 > <5>[2.682502] 00ad f82c9524 26dc f8282692 f8282692 > f555ed80 00061200 > <5>[2.682509] f567c000 f5473a34 c0449b52 0009 f5473a40 > f8282692 f5578800 > <5>[2.682516] Call Trace: > <5>[2.682528] [] dump_stack+0x41/0x52 > <5>[2.682534] [] warn_slowpath_common+0x84/0xa0 > <5>[2.682571] [] ? intel_get_pipe_from_connector+0x42/0x50 > [i915] > <5>[2.682607] [] ? intel_get_pipe_from_connector+0x42/0x50 > [i915] > <5>[2.682612] [] warn_slowpath_null+0x22/0x30 > <5>[2.682648] [] intel_get_pipe_from_connector+0x42/0x50 [i915] > <5>[2.682689] [] intel_panel_disable_backlight+0x21/0x160 > [i915] > <5>[2.682725] [] intel_disable_lvds+0x41/0x160 [i915] > <5>[2.682760] [] i9xx_crtc_disable+0x200/0x2c0 [i915] > <5>[2.682802] [] ? gen4_read32+0x31/0x90 [i915] > <5>[2.682839] [] intel_modeset_setup_hw_state+0x92e/0xb00 > [i915] > <5>[2.682844] [] ? power_down+0x8c/0x8d > <5>[2.682884] [] ? gen4_write64+0xa0/0xa0 [i915] > <5>[2.682920] [] intel_modeset_gem_init+0x20/0x30 [i915] > <5>[2.682950] [] i915_driver_load+0xb53/0xdd0 [i915] > <5>[2.682978] [] ? i915_switcheroo_set_state+0xa0/0xa0 [i915] > <5>[2.683003] [] drm_dev_register+0x8c/0x1a0 [drm] > <5>[2.683043] [] drm_get_pci_dev+0x85/0x130 [drm] > <5>[2.683050] [] ? sysfs_do_create_link_sd.isra.3+0xa8/0x1c0 > <5>[2.683057] [] ? notifier_call_chain+0x43/0x60 > <5>[2.683086] [] i915_pci_probe+0x3a/0x80 [i915] > <5>[2.683093] [] pci_device_probe+0x79/0xc0 > <5>[2.683097] [] ? sysfs_create_link+0x25/0x40 > <5>[2.683104] [] driver_probe_device+0x79/0x360 > <5>[2.683108] [] ? pci_match_device+0x9e/0xb0 > <5>[2.683113] [] __driver_attach+0x91/0xa0 > <5>[2.683117] [] ? driver_probe_device+0x360/0x360 > <5>[2.683121] [] bus_for_each_dev+0x42/0x80 > <5>[2.683125] [] driver_attach+0x1e/0x20 > <5>[2.683130] [] ? driver_probe_device+0x360/0x360 > <5>[2.683134] [] bus_add_driver+0xec/0x210 > <5>[2.683138] [] driver_register+0x59/0xe0 > <5>[2.683142] [] ? 0xf7fb1fff > <5>[2.683147] [] __pci_register_driver+0x33/0x40 > <5>[2.683150] [] ? 0xf7fb1fff > <5>[2.683166] [] drm_pci_init+0xfd/0x110 [drm] > <5>[2.683170] [] ? 0xf7fb1fff > <5>[2.683198] [] i915_init+0x5e/0x60 [i915] > <5>[2.683203] [] do_one_initcall+0xda/0x1a0 > <5>[2.683206] [] ? 0xf7fb1fff > <5>[2.683211] [] ? __add_event_to_tracers+0x21/0x30 > <5>[2.683215] [] ? 0xf7fb1fff > <5>[2.683221] [] ? set_memory_ro+0x37/0x40 > <5>[2.683228] [] load_module+0x1abd/0x2390 > <5>[2.683235] [] SyS_init_module+0xa7/0x110 > <5>[2.683242] [] ? vm_mmap_pgoff+0x8b/0xb0 > <5>[2.683248] [] sysenter_do_call+0x12/0x28 > > Feel free to prod for further details. > > > Paul Bolle > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [Intel gfx][i-g-t PATCH 4/4] tests/gem_media_fill: the assembly code for the shader used in the case
> On Thu, 2013-11-28 at 23:57 -0700, Xiang, Haihao wrote:
> > From: "Xiang, Haihao"
> >
> > The code is for reference only
> >
> > Signed-off-by: Xiang, Haihao
> > ---
> > shaders/media/README |6 ++
> > shaders/media/media_fill.gxa | 30 ++
> > 2 files changed, 36 insertions(+)
> > create mode 100644 shaders/media/README
> > create mode 100644 shaders/media/media_fill.gxa
> >
> > diff --git a/shaders/media/README b/shaders/media/README
> > new file mode 100644
> > index 000..334106c
> > --- /dev/null
> > +++ b/shaders/media/README
> > @@ -0,0 +1,6 @@
> > +These files are here for reference only.
> > +
> > +Commands used to generate the shader on gen8
> > +$> m4 media_fill.gxa > media_fill.gxm
> > +$> intel-gen4asm -g 8 -o media_fill.gxm
> > +
> > diff --git a/shaders/media/media_fill.gxa b/shaders/media/media_fill.gxa
> > new file mode 100644
> > index 000..d2931d4
> > --- /dev/null
> > +++ b/shaders/media/media_fill.gxa
> > @@ -0,0 +1,30 @@
> > +/*
> > + * Registers
> > + * g0 -- header
> > + * g1 -- constant
> > + * g2 -- inline data
> > + * g3 -- reserved
> > + * g4-g12 message payload
> > + */
> > +define(`ORIG', `g2.0<2,2,1>UD')
> > +define(`COLOR', `g1.0')
> > +define(`COLORUB', `COLOR<0,1,0>UB')
> > +define(`COLORUD', `COLOR<0,1,0>UD')
> > +
> > +mov(4) COLOR<1>UB COLORUB {align1};
> > +
> > +/* WRITE */
> > +mov(8) g4.0<1>UD g0.0<8,8,1>UD {align1};
> > +mov(2) g4.0<1>UD ORIG{align1};
> > +mov(1) g4.8<1>UD 0x000f000fUD{align1};
> > +
> > +mov(16) g5.0<1>UD COLORUD {align1 compr};
> > +mov(16) g7.0<1>UD COLORUD {align1 compr};
> > +mov(16) g9.0<1>UD COLORUD {align1 compr};
> > +mov(16) g11.0<1>UD COLORUD {align1 compr};
> > +
> > +send(16) 4 acc0<1>UW null write(0, 0, 10, 0) mlen 9 rlen 0 {align1};
> > +
> > +/* EOT */
> > +mov(8) g4.0<1>UD g0.0<8,8,1>UD {align1};
> > +send(16) 4 acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1
> > EOT};
>
> Based on the spec the send with EOT flag should use the register space
> r112-r127 for . So 4 had better be changed as 127.
Thanks for pointing out the issue, I will fix it in the new version of
patches.
>
> Thanks.
> Yakui
>
>
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[Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm-intel-fixes tree
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in
drivers/gpu/drm/i915/intel_display.c between commit a1216444283e
("drm/i915: use the correct force_wake function at the PC8 code") from
the drm-intel-fixes tree and commit c8d9a5905e45 ("drm/i915: Add power
well arguments to force wake routines") from the drm-intel tree.
I fixed it up (I just used the drm-intel-fixes version) and can carry the
fix as necessary (no action is required).
--
Cheers,
Stephen Rothwells...@canb.auug.org.au
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Re: [Intel-gfx] [Intel gfx][i-g-t PATCH 1/4] tests: add gem_media_fill
On Fri, 2013-11-29 at 09:02 +0100, Daniel Vetter wrote:
> On Fri, Nov 29, 2013 at 02:57:13PM +0800, Xiang, Haihao wrote:
> > From: "Xiang, Haihao"
> >
> > It is to check whether media pipeline on render ring works. Codes
> > are copied and modified from the rendercopy case which uses 3D pipeline.
> > However media pipeline is simpler than 3D pipeline and there is few changes
> > between gen6,gen7 and gen8
> >
> > Signed-off-by: Xiang, Haihao
>
> Really awesome. This should also help in writing crazy multi-ring tests
> which check correctness. I don't have any clue about media stuff, so
> please let someone else from your team quickly review it before you push.
> Otherwise lgtm.
Thanks for your comments. I will fix the issue Yakui pointed out first
then push the code.
> -Daniel
>
> > ---
> > lib/Makefile.sources |2 +
> > lib/media_fill.c |9
> > lib/media_fill.h | 50 ++
> > tests/Makefile.sources |1 +
> > tests/gem_media_fill.c | 132
> >
> > 5 files changed, 194 insertions(+)
> > create mode 100644 lib/media_fill.c
> > create mode 100644 lib/media_fill.h
> > create mode 100644 tests/gem_media_fill.c
> >
> > diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> > index 699621b..cad238a 100644
> > --- a/lib/Makefile.sources
> > +++ b/lib/Makefile.sources
> > @@ -19,6 +19,8 @@ libintel_tools_la_SOURCES = \
> > intel_mmio.c\
> > intel_pci.c \
> > intel_reg.h \
> > + media_fill.c\
> > + media_fill.h\
> > rendercopy_i915.c \
> > rendercopy_i830.c \
> > gen6_render.h \
> > diff --git a/lib/media_fill.c b/lib/media_fill.c
> > new file mode 100644
> > index 000..8ee5db6
> > --- /dev/null
> > +++ b/lib/media_fill.c
> > @@ -0,0 +1,9 @@
> > +#include "i830_reg.h"
> > +#include "media_fill.h"
> > +
> > +media_fillfunc_t get_media_fillfunc(int devid)
> > +{
> > + media_fillfunc_t fill = NULL;
> > +
> > + return fill;
> > +}
> > diff --git a/lib/media_fill.h b/lib/media_fill.h
> > new file mode 100644
> > index 000..2e058cb
> > --- /dev/null
> > +++ b/lib/media_fill.h
> > @@ -0,0 +1,50 @@
> > +#ifndef RENDE_MEDIA_FILL_H
> > +#define RENDE_MEDIA_FILL_H
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include "drm.h"
> > +#include "i915_drm.h"
> > +#include "drmtest.h"
> > +#include "intel_bufmgr.h"
> > +#include "intel_batchbuffer.h"
> > +#include "intel_gpu_tools.h"
> > +
> > +struct scratch_buf {
> > +drm_intel_bo *bo;
> > +uint32_t stride;
> > +uint32_t tiling;
> > +uint32_t *data;
> > +uint32_t *cpu_mapping;
> > +uint32_t size;
> > +unsigned num_tiles;
> > +};
> > +
> > +static inline unsigned buf_width(struct scratch_buf *buf)
> > +{
> > + return buf->stride/sizeof(uint8_t);
> > +}
> > +
> > +static inline unsigned buf_height(struct scratch_buf *buf)
> > +{
> > + return buf->size/buf->stride;
> > +}
> > +
> > +typedef void (*media_fillfunc_t)(struct intel_batchbuffer *batch,
> > + struct scratch_buf *dst,
> > + unsigned x, unsigned y,
> > + unsigned width, unsigned height,
> > + uint8_t color);
> > +
> > +media_fillfunc_t get_media_fillfunc(int devid);
> > +
> > +#endif /* RENDE_MEDIA_FILL_H */
> > diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> > index d201809..0ff0e37 100644
> > --- a/tests/Makefile.sources
> > +++ b/tests/Makefile.sources
> > @@ -87,6 +87,7 @@ TESTS_progs = \
> > gem_largeobject \
> > gem_lut_handle \
> > gem_mmap_offset_exhaustion \
> > + gem_media_fill \
> > gem_pin \
> > gem_pipe_control_store_loop \
> > gem_reg_read \
> > diff --git a/tests/gem_media_fill.c b/tests/gem_media_fill.c
> > new file mode 100644
> > index 000..40b391d
> > --- /dev/null
> > +++ b/tests/gem_media_fill.c
> > @@ -0,0 +1,132 @@
> > +/*
> > + * Copyright © 2013 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the
> > "Software"),
> > + * to deal in the Software without restriction, including without
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including the
> > next
> > + * paragraph) shall be included in all copies or substantial portions of
> > the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
> > OR
> > + * IMPLIE
Re: [Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm-intel-fixes tree
On Mon, 2 Dec 2013 12:04:37 +1100 Stephen Rothwell
wrote:
>
> Today's linux-next merge of the drm-intel tree got a conflict in
> drivers/gpu/drm/i915/intel_display.c between commit a1216444283e
> ("drm/i915: use the correct force_wake function at the PC8 code") from
> the drm-intel-fixes tree and commit c8d9a5905e45 ("drm/i915: Add power
> well arguments to force wake routines") from the drm-intel tree.
>
> I fixed it up (I just used the drm-intel-fixes version) and can carry the
> fix as necessary (no action is required).
Actually, I ended up doing the below.
--
Cheers,
Stephen Rothwells...@canb.auug.org.au
diff --cc drivers/gpu/drm/i915/intel_display.c
index 080f6fd4e839,0332d7ca892d..
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@@ -6402,7 -6583,7 +6583,7 @@@ static void hsw_restore_lcpll(struct dr
/* Make sure we're not on PC8 state before disabling PC8, otherwise
* we'll hang the machine! */
- gen6_gt_force_wake_get(dev_priv);
- dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
++ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
if (val & LCPLL_POWER_DOWN_ALLOW) {
val &= ~LCPLL_POWER_DOWN_ALLOW;
@@@ -6436,7 -6617,7 +6617,7 @@@
DRM_ERROR("Switching back to LCPLL failed\n");
}
- gen6_gt_force_wake_put(dev_priv);
- dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
++ gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
}
void hsw_enable_pc8_work(struct work_struct *__work)
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[Intel-gfx] [Intel gfx][i-g-t PATCH (v2) 1/4] tests: add gem_media_fill
From: "Xiang, Haihao"
It is to check whether media pipeline on render ring works. Codes
are copied and modified from the rendercopy case which uses 3D pipeline.
However media pipeline is simpler than 3D pipeline and there is few changes
between gen6,gen7 and gen8
Signed-off-by: Xiang, Haihao
---
lib/Makefile.sources |2 +
lib/media_fill.c |9
lib/media_fill.h | 50 ++
tests/Makefile.sources |1 +
tests/gem_media_fill.c | 132
5 files changed, 194 insertions(+)
create mode 100644 lib/media_fill.c
create mode 100644 lib/media_fill.h
create mode 100644 tests/gem_media_fill.c
diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 699621b..cad238a 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -19,6 +19,8 @@ libintel_tools_la_SOURCES = \
intel_mmio.c\
intel_pci.c \
intel_reg.h \
+ media_fill.c\
+ media_fill.h\
rendercopy_i915.c \
rendercopy_i830.c \
gen6_render.h \
diff --git a/lib/media_fill.c b/lib/media_fill.c
new file mode 100644
index 000..8ee5db6
--- /dev/null
+++ b/lib/media_fill.c
@@ -0,0 +1,9 @@
+#include "i830_reg.h"
+#include "media_fill.h"
+
+media_fillfunc_t get_media_fillfunc(int devid)
+{
+ media_fillfunc_t fill = NULL;
+
+ return fill;
+}
diff --git a/lib/media_fill.h b/lib/media_fill.h
new file mode 100644
index 000..2e058cb
--- /dev/null
+++ b/lib/media_fill.h
@@ -0,0 +1,50 @@
+#ifndef RENDE_MEDIA_FILL_H
+#define RENDE_MEDIA_FILL_H
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "drm.h"
+#include "i915_drm.h"
+#include "drmtest.h"
+#include "intel_bufmgr.h"
+#include "intel_batchbuffer.h"
+#include "intel_gpu_tools.h"
+
+struct scratch_buf {
+drm_intel_bo *bo;
+uint32_t stride;
+uint32_t tiling;
+uint32_t *data;
+uint32_t *cpu_mapping;
+uint32_t size;
+unsigned num_tiles;
+};
+
+static inline unsigned buf_width(struct scratch_buf *buf)
+{
+ return buf->stride/sizeof(uint8_t);
+}
+
+static inline unsigned buf_height(struct scratch_buf *buf)
+{
+ return buf->size/buf->stride;
+}
+
+typedef void (*media_fillfunc_t)(struct intel_batchbuffer *batch,
+ struct scratch_buf *dst,
+ unsigned x, unsigned y,
+ unsigned width, unsigned height,
+ uint8_t color);
+
+media_fillfunc_t get_media_fillfunc(int devid);
+
+#endif /* RENDE_MEDIA_FILL_H */
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index d201809..0ff0e37 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -87,6 +87,7 @@ TESTS_progs = \
gem_largeobject \
gem_lut_handle \
gem_mmap_offset_exhaustion \
+ gem_media_fill \
gem_pin \
gem_pipe_control_store_loop \
gem_reg_read \
diff --git a/tests/gem_media_fill.c b/tests/gem_media_fill.c
new file mode 100644
index 000..40b391d
--- /dev/null
+++ b/tests/gem_media_fill.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *Damien Lespiau
+ *Xiang, Haihao
+ */
+
+/*
+ * This file is a basic test for the media_fill() function, a very simple
+ * workload for the Media pipeline.
+ */
+
+#include
+#include
+#include
+
+#include "media_fill.h"
+
+#define WIDTH 64
+#define STRIDE (WIDTH)
+#define HEIGHT 64
+#define SIZE (HEIGHT*STRIDE)
+
+#define COLOR_C4 0xc4
+#define COLOR_4C 0x4c
+
+typedef struct {
+ int drm_fd;
+ uint32_t devid;
+ drm_intel_bufmgr *bufmgr;
+ uint8_t linear[WIDTH * HEIGHT];
+} data_t;
+
+sta
[Intel-gfx] [Intel gfx][i-g-t PATCH (v2) 4/4] tests/gem_media_fill: the assembly code for the shader used in the case
From: "Xiang, Haihao"
The code is for reference only
v2: Fixed the source register used for the send with EOT
Fixed the posted destination operand for the send with EOT
Signed-off-by: Xiang, Haihao
---
shaders/media/README |6 ++
shaders/media/media_fill.gxa | 30 ++
2 files changed, 36 insertions(+)
create mode 100644 shaders/media/README
create mode 100644 shaders/media/media_fill.gxa
diff --git a/shaders/media/README b/shaders/media/README
new file mode 100644
index 000..334106c
--- /dev/null
+++ b/shaders/media/README
@@ -0,0 +1,6 @@
+These files are here for reference only.
+
+Commands used to generate the shader on gen8
+$> m4 media_fill.gxa > media_fill.gxm
+$> intel-gen4asm -g 8 -o media_fill.gxm
+
diff --git a/shaders/media/media_fill.gxa b/shaders/media/media_fill.gxa
new file mode 100644
index 000..53e2c9f
--- /dev/null
+++ b/shaders/media/media_fill.gxa
@@ -0,0 +1,30 @@
+/*
+ * Registers
+ * g0 -- header
+ * g1 -- constant
+ * g2 -- inline data
+ * g3 -- reserved
+ * g4-g12 payload for write message
+ */
+define(`ORIG', `g2.0<2,2,1>UD')
+define(`COLOR', `g1.0')
+define(`COLORUB', `COLOR<0,1,0>UB')
+define(`COLORUD', `COLOR<0,1,0>UD')
+
+mov(4) COLOR<1>UB COLORUB {align1};
+
+/* WRITE */
+mov(8) g4.0<1>UD g0.0<8,8,1>UD {align1};
+mov(2) g4.0<1>UD ORIG{align1};
+mov(1) g4.8<1>UD 0x000f000fUD{align1};
+
+mov(16) g5.0<1>UD COLORUD {align1 compr};
+mov(16) g7.0<1>UD COLORUD {align1 compr};
+mov(16) g9.0<1>UD COLORUD {align1 compr};
+mov(16) g11.0<1>UD COLORUD {align1 compr};
+
+send(16) 4 acc0<1>UW null write(0, 0, 10, 0) mlen 9 rlen 0 {align1};
+
+/* EOT */
+mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1};
+send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
--
1.7.9.5
___
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[Intel-gfx] [Intel gfx][i-g-t PATCH (v2) 2/4] tests/gem_media_fill: add support for gen8
From: "Xiang, Haihao" v2: Fixed the source register used for the send with EOT Fixed the posted destination operand for the send with EOT Signed-off-by: Xiang, Haihao --- lib/Makefile.sources |2 + lib/gen8_media.h | 371 + lib/media_fill.c |3 + lib/media_fill.h |7 + lib/media_fill_gen8.c | 366 5 files changed, 749 insertions(+) create mode 100644 lib/gen8_media.h create mode 100644 lib/media_fill_gen8.c diff --git a/lib/Makefile.sources b/lib/Makefile.sources index cad238a..95ccb2f 100644 --- a/lib/Makefile.sources +++ b/lib/Makefile.sources @@ -21,6 +21,8 @@ libintel_tools_la_SOURCES = \ intel_reg.h \ media_fill.c\ media_fill.h\ + media_fill_gen8.c \ + gen8_media.h\ rendercopy_i915.c \ rendercopy_i830.c \ gen6_render.h \ diff --git a/lib/gen8_media.h b/lib/gen8_media.h new file mode 100644 index 000..c61aed2 --- /dev/null +++ b/lib/gen8_media.h @@ -0,0 +1,371 @@ +#ifndef GEN8_MEDIA_H +#define GEN8_MEDIA_H + +#define GEN8_SURFACEFORMAT_R32G32B32A32_FLOAT 0x000 +#define GEN8_SURFACEFORMAT_R32G32B32A32_SINT 0x001 +#define GEN8_SURFACEFORMAT_R32G32B32A32_UINT 0x002 +#define GEN8_SURFACEFORMAT_R32G32B32A32_UNORM 0x003 +#define GEN8_SURFACEFORMAT_R32G32B32A32_SNORM 0x004 +#define GEN8_SURFACEFORMAT_R64G64_FLOAT 0x005 +#define GEN8_SURFACEFORMAT_R32G32B32X32_FLOAT 0x006 +#define GEN8_SURFACEFORMAT_R32G32B32A32_SSCALED 0x007 +#define GEN8_SURFACEFORMAT_R32G32B32A32_USCALED 0x008 +#define GEN8_SURFACEFORMAT_R32G32B32_FLOAT0x040 +#define GEN8_SURFACEFORMAT_R32G32B32_SINT 0x041 +#define GEN8_SURFACEFORMAT_R32G32B32_UINT 0x042 +#define GEN8_SURFACEFORMAT_R32G32B32_UNORM0x043 +#define GEN8_SURFACEFORMAT_R32G32B32_SNORM0x044 +#define GEN8_SURFACEFORMAT_R32G32B32_SSCALED 0x045 +#define GEN8_SURFACEFORMAT_R32G32B32_USCALED 0x046 +#define GEN8_SURFACEFORMAT_R16G16B16A16_UNORM 0x080 +#define GEN8_SURFACEFORMAT_R16G16B16A16_SNORM 0x081 +#define GEN8_SURFACEFORMAT_R16G16B16A16_SINT 0x082 +#define GEN8_SURFACEFORMAT_R16G16B16A16_UINT 0x083 +#define GEN8_SURFACEFORMAT_R16G16B16A16_FLOAT 0x084 +#define GEN8_SURFACEFORMAT_R32G32_FLOAT 0x085 +#define GEN8_SURFACEFORMAT_R32G32_SINT0x086 +#define GEN8_SURFACEFORMAT_R32G32_UINT0x087 +#define GEN8_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS 0x088 +#define GEN8_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT0x089 +#define GEN8_SURFACEFORMAT_L32A32_FLOAT 0x08A +#define GEN8_SURFACEFORMAT_R32G32_UNORM 0x08B +#define GEN8_SURFACEFORMAT_R32G32_SNORM 0x08C +#define GEN8_SURFACEFORMAT_R64_FLOAT 0x08D +#define GEN8_SURFACEFORMAT_R16G16B16X16_UNORM 0x08E +#define GEN8_SURFACEFORMAT_R16G16B16X16_FLOAT 0x08F +#define GEN8_SURFACEFORMAT_A32X32_FLOAT 0x090 +#define GEN8_SURFACEFORMAT_L32X32_FLOAT 0x091 +#define GEN8_SURFACEFORMAT_I32X32_FLOAT 0x092 +#define GEN8_SURFACEFORMAT_R16G16B16A16_SSCALED 0x093 +#define GEN8_SURFACEFORMAT_R16G16B16A16_USCALED 0x094 +#define GEN8_SURFACEFORMAT_R32G32_SSCALED 0x095 +#define GEN8_SURFACEFORMAT_R32G32_USCALED 0x096 +#define GEN8_SURFACEFORMAT_B8G8R8A8_UNORM 0x0C0 +#define GEN8_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB0x0C1 +#define GEN8_SURFACEFORMAT_R10G10B10A2_UNORM 0x0C2 +#define GEN8_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB 0x0C3 +#define GEN8_SURFACEFORMAT_R10G10B10A2_UINT 0x0C4 +#define GEN8_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM 0x0C5 +#define GEN8_SURFACEFORMAT_R8G8B8A8_UNORM 0x0C7 +#define GEN8_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB0x0C8 +#define GEN8_SURFACEFORMAT_R8G8B8A8_SNORM 0x0C9 +#define GEN8_SURFACEFORMAT_R8G8B8A8_SINT 0x0CA +#define GEN8_SURFACEFORMAT_R8G8B8A8_UINT 0x0CB +#define GEN8_SURFACEFORMAT_R16G16_UNORM 0x0CC +#define GEN8_SURFACEFORMAT_R16G16_SNORM 0x0CD +#define GEN8_SURFACEFORMAT_R16G16_SINT0x0CE +#define GEN8_SURFACEFORMAT_R16G16_UINT0x0CF +#define GEN8_SURFACEFORMAT_R16G16_FLOAT 0x0D0 +#define GEN8_SURFACEFORMAT_B10G10R10A2_UNORM 0x0D1 +#define GEN8_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB 0x0D2 +#define GEN8_SURFACEFORMAT_R11G11B10_FLOAT0x0D3 +#define GEN8_SURFACEF
[Intel-gfx] [Intel gfx][i-g-t PATCH (v2) 3/4] tests/gem_media_fill: add support for gen7
From: "Xiang, Haihao" v2: Fixed the source register used for the send with EOT Fixed the posted destination operand for the send with EOT Signed-off-by: Xiang, Haihao --- lib/Makefile.sources |2 + lib/gen7_media.h | 323 + lib/media_fill.c |2 + lib/media_fill.h |7 + lib/media_fill_gen7.c | 351 + 5 files changed, 685 insertions(+) create mode 100644 lib/gen7_media.h create mode 100644 lib/media_fill_gen7.c diff --git a/lib/Makefile.sources b/lib/Makefile.sources index 95ccb2f..fd08c1f 100644 --- a/lib/Makefile.sources +++ b/lib/Makefile.sources @@ -21,7 +21,9 @@ libintel_tools_la_SOURCES = \ intel_reg.h \ media_fill.c\ media_fill.h\ + media_fill_gen7.c \ media_fill_gen8.c \ + gen7_media.h\ gen8_media.h\ rendercopy_i915.c \ rendercopy_i830.c \ diff --git a/lib/gen7_media.h b/lib/gen7_media.h new file mode 100644 index 000..d75ee1b --- /dev/null +++ b/lib/gen7_media.h @@ -0,0 +1,323 @@ +#ifndef GEN7_MEDIA_H +#define GEN7_MEDIA_H + +#define GEN7_SURFACEFORMAT_R32G32B32A32_FLOAT 0x000 +#define GEN7_SURFACEFORMAT_R32G32B32A32_SINT 0x001 +#define GEN7_SURFACEFORMAT_R32G32B32A32_UINT 0x002 +#define GEN7_SURFACEFORMAT_R32G32B32A32_UNORM 0x003 +#define GEN7_SURFACEFORMAT_R32G32B32A32_SNORM 0x004 +#define GEN7_SURFACEFORMAT_R64G64_FLOAT 0x005 +#define GEN7_SURFACEFORMAT_R32G32B32X32_FLOAT 0x006 +#define GEN7_SURFACEFORMAT_R32G32B32A32_SSCALED 0x007 +#define GEN7_SURFACEFORMAT_R32G32B32A32_USCALED 0x008 +#define GEN7_SURFACEFORMAT_R32G32B32_FLOAT0x040 +#define GEN7_SURFACEFORMAT_R32G32B32_SINT 0x041 +#define GEN7_SURFACEFORMAT_R32G32B32_UINT 0x042 +#define GEN7_SURFACEFORMAT_R32G32B32_UNORM0x043 +#define GEN7_SURFACEFORMAT_R32G32B32_SNORM0x044 +#define GEN7_SURFACEFORMAT_R32G32B32_SSCALED 0x045 +#define GEN7_SURFACEFORMAT_R32G32B32_USCALED 0x046 +#define GEN7_SURFACEFORMAT_R16G16B16A16_UNORM 0x080 +#define GEN7_SURFACEFORMAT_R16G16B16A16_SNORM 0x081 +#define GEN7_SURFACEFORMAT_R16G16B16A16_SINT 0x082 +#define GEN7_SURFACEFORMAT_R16G16B16A16_UINT 0x083 +#define GEN7_SURFACEFORMAT_R16G16B16A16_FLOAT 0x084 +#define GEN7_SURFACEFORMAT_R32G32_FLOAT 0x085 +#define GEN7_SURFACEFORMAT_R32G32_SINT0x086 +#define GEN7_SURFACEFORMAT_R32G32_UINT0x087 +#define GEN7_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS 0x088 +#define GEN7_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT0x089 +#define GEN7_SURFACEFORMAT_L32A32_FLOAT 0x08A +#define GEN7_SURFACEFORMAT_R32G32_UNORM 0x08B +#define GEN7_SURFACEFORMAT_R32G32_SNORM 0x08C +#define GEN7_SURFACEFORMAT_R64_FLOAT 0x08D +#define GEN7_SURFACEFORMAT_R16G16B16X16_UNORM 0x08E +#define GEN7_SURFACEFORMAT_R16G16B16X16_FLOAT 0x08F +#define GEN7_SURFACEFORMAT_A32X32_FLOAT 0x090 +#define GEN7_SURFACEFORMAT_L32X32_FLOAT 0x091 +#define GEN7_SURFACEFORMAT_I32X32_FLOAT 0x092 +#define GEN7_SURFACEFORMAT_R16G16B16A16_SSCALED 0x093 +#define GEN7_SURFACEFORMAT_R16G16B16A16_USCALED 0x094 +#define GEN7_SURFACEFORMAT_R32G32_SSCALED 0x095 +#define GEN7_SURFACEFORMAT_R32G32_USCALED 0x096 +#define GEN7_SURFACEFORMAT_B8G8R8A8_UNORM 0x0C0 +#define GEN7_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB0x0C1 +#define GEN7_SURFACEFORMAT_R10G10B10A2_UNORM 0x0C2 +#define GEN7_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB 0x0C3 +#define GEN7_SURFACEFORMAT_R10G10B10A2_UINT 0x0C4 +#define GEN7_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM 0x0C5 +#define GEN7_SURFACEFORMAT_R8G8B8A8_UNORM 0x0C7 +#define GEN7_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB0x0C8 +#define GEN7_SURFACEFORMAT_R8G8B8A8_SNORM 0x0C9 +#define GEN7_SURFACEFORMAT_R8G8B8A8_SINT 0x0CA +#define GEN7_SURFACEFORMAT_R8G8B8A8_UINT 0x0CB +#define GEN7_SURFACEFORMAT_R16G16_UNORM 0x0CC +#define GEN7_SURFACEFORMAT_R16G16_SNORM 0x0CD +#define GEN7_SURFACEFORMAT_R16G16_SINT0x0CE +#define GEN7_SURFACEFORMAT_R16G16_UINT0x0CF +#define GEN7_SURFACEFORMAT_R16G16_FLOAT 0x0D0 +#define GEN7_SURFACEFORMAT_B10G10R10A2_UNORM 0x0D1 +#define GEN7_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB 0x0D2 +#define GEN7_SURFACEFORMAT_R11G11B10_FLOAT
Re: [Intel-gfx] [Intel gfx][i-g-t PATCH (v2) 1/4] tests: add gem_media_fill
On Sun, 2013-12-01 at 22:02 -0700, Xiang, Haihao wrote:
> From: "Xiang, Haihao"
>
> It is to check whether media pipeline on render ring works. Codes
> are copied and modified from the rendercopy case which uses 3D pipeline.
> However media pipeline is simpler than 3D pipeline and there is few changes
> between gen6,gen7 and gen8
The media pipeline is critical to intel-vaapi driver, which is used in
encoding and video post-processing. This patch set can be used to check
whether the media pipeline can work as expected.
>
> Signed-off-by: Xiang, Haihao
Reviewed-by: Zhao Yakui
> ---
> lib/Makefile.sources |2 +
> lib/media_fill.c |9
> lib/media_fill.h | 50 ++
> tests/Makefile.sources |1 +
> tests/gem_media_fill.c | 132
>
> 5 files changed, 194 insertions(+)
> create mode 100644 lib/media_fill.c
> create mode 100644 lib/media_fill.h
> create mode 100644 tests/gem_media_fill.c
>
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index 699621b..cad238a 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -19,6 +19,8 @@ libintel_tools_la_SOURCES = \
> intel_mmio.c\
> intel_pci.c \
> intel_reg.h \
> + media_fill.c\
> + media_fill.h\
> rendercopy_i915.c \
> rendercopy_i830.c \
> gen6_render.h \
> diff --git a/lib/media_fill.c b/lib/media_fill.c
> new file mode 100644
> index 000..8ee5db6
> --- /dev/null
> +++ b/lib/media_fill.c
> @@ -0,0 +1,9 @@
> +#include "i830_reg.h"
> +#include "media_fill.h"
> +
> +media_fillfunc_t get_media_fillfunc(int devid)
> +{
> + media_fillfunc_t fill = NULL;
> +
> + return fill;
> +}
> diff --git a/lib/media_fill.h b/lib/media_fill.h
> new file mode 100644
> index 000..2e058cb
> --- /dev/null
> +++ b/lib/media_fill.h
> @@ -0,0 +1,50 @@
> +#ifndef RENDE_MEDIA_FILL_H
> +#define RENDE_MEDIA_FILL_H
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include "drm.h"
> +#include "i915_drm.h"
> +#include "drmtest.h"
> +#include "intel_bufmgr.h"
> +#include "intel_batchbuffer.h"
> +#include "intel_gpu_tools.h"
> +
> +struct scratch_buf {
> +drm_intel_bo *bo;
> +uint32_t stride;
> +uint32_t tiling;
> +uint32_t *data;
> +uint32_t *cpu_mapping;
> +uint32_t size;
> +unsigned num_tiles;
> +};
> +
> +static inline unsigned buf_width(struct scratch_buf *buf)
> +{
> + return buf->stride/sizeof(uint8_t);
> +}
> +
> +static inline unsigned buf_height(struct scratch_buf *buf)
> +{
> + return buf->size/buf->stride;
> +}
> +
> +typedef void (*media_fillfunc_t)(struct intel_batchbuffer *batch,
> + struct scratch_buf *dst,
> + unsigned x, unsigned y,
> + unsigned width, unsigned height,
> + uint8_t color);
> +
> +media_fillfunc_t get_media_fillfunc(int devid);
> +
> +#endif /* RENDE_MEDIA_FILL_H */
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> index d201809..0ff0e37 100644
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -87,6 +87,7 @@ TESTS_progs = \
> gem_largeobject \
> gem_lut_handle \
> gem_mmap_offset_exhaustion \
> + gem_media_fill \
> gem_pin \
> gem_pipe_control_store_loop \
> gem_reg_read \
> diff --git a/tests/gem_media_fill.c b/tests/gem_media_fill.c
> new file mode 100644
> index 000..40b391d
> --- /dev/null
> +++ b/tests/gem_media_fill.c
> @@ -0,0 +1,132 @@
> +/*
> + * Copyright © 2013 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + *
> + * Authors:
> + *Da
Re: [Intel-gfx] [i915] WARNING: [...] drivers/gpu/drm/i915/intel_display.c:9948 intel_get_pipe_from_connector
On Sun, Dec 1, 2013 at 5:57 PM, Paul Bolle wrote: > On Sun, 2013-12-01 at 10:58 +0100, Daniel Vetter wrote: >> Should be fixed with >> >> commit 7c063c725987406d743cc7de7625ff224fab75de >> Author: Jesse Barnes >> Date: Tue Nov 26 09:13:41 2013 -0800 >> >> drm/i915: take mode config lock around crtc disable at suspend >> >> which is currently in drm-intel-fixes. I'll forward it early next week. > > Thanks! > > The WARNING is now gone during suspend and resume (having tested that > thoroughly - ie, twice). But I still see it at boot. Is there a related > fix for that WARNING during boot? Hm, I've never seen it during boot. Can you please boot with drm.debug=0xe and attach the dmesg with the WARN? Thanks, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave, Just flushing out my pile of bugfixes, most of them for regressions/cc: stable. Nothing really serious going on. For outstanding issues we still have the S4 fun due to the hsw S4 duct-tape pending (seems like I need to switch into angry maintainer mode on that one). And there's the mode merging revert to make my g33 work again still pending for drm core. For that one I don't have any more clue (and it looks like no one else has a good idea either). And apparently the locking WARN fix in here also needs to be replicated for boot, still confirming that one though. Cheers, Daniel The following changes since commit f727b490efd0941a8d720fd07012dcb7f0740f77: drm/i915: Fix gen3 self-refresh watermarks (2013-11-20 15:52:52 +0100) are available in the git repository at: git://people.freedesktop.org/~danvet/drm-intel tags/drm-intel-fixes-2013-12-02 for you to fetch changes up to 993fc6ebaf4af6fdfde08cc8649c386e483a5908: drm/i915: Pin pages whilst allocating for dma-buf vmap() (2013-11-29 15:51:20 +0100) Chris Wilson (3): drm/i915: Prefer setting PTE cache age to 3 drm/i915: Pin relocations for the duration of constructing the execbuffer drm/i915: Pin pages whilst allocating for dma-buf vmap() Jani Nikula (1): drm/i915/ddi: set sink to power down mode on dp disable Jesse Barnes (2): drm/i915: take mode config lock around crtc disable at suspend drm/i915: use crtc_htotal in watermark calculations to match fastboot v2 Paulo Zanoni (1): drm/i915: use the correct force_wake function at the PC8 code Ville Syrjälä (5): drm/i915: Check VBT for eDP ports on VLV drm/i915: Simplify DP vs. eDP detection drm/i915: Fix pipe CSC post offset calculation drm/i915: Make the DERRMR SRM target global GTT drm/i915: MI_PREDICATE_RESULT_2 is HSW only drivers/gpu/drm/i915/i915_drv.c| 2 + drivers/gpu/drm/i915/i915_gem.c| 7 ++-- drivers/gpu/drm/i915/i915_gem_dmabuf.c | 13 --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 60 -- drivers/gpu/drm/i915/i915_gem_gtt.c| 6 ++- drivers/gpu/drm/i915/i915_reg.h| 1 + drivers/gpu/drm/i915/intel_ddi.c | 5 ++- drivers/gpu/drm/i915/intel_display.c | 14 +++ drivers/gpu/drm/i915/intel_dp.c| 34 +++-- drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_pm.c| 15 11 files changed, 82 insertions(+), 77 deletions(-) -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
