Re: [Intel-gfx] [PATCH] drm/i915: cache the EDID for eDP panels

2012-06-15 Thread Jani Nikula 
On Thu, 14 Jun 2012, Jesse Barnes  wrote:
> They aren't going anywhere, and probing on DDC can cause the panel to
> blank briefly, so read them up front and cache them for later queries.
>
> v2: fix potential NULL derefs in intel_dp_get_edid_modes and
> intel_dp_get_edid (Jani)
> copy full EDID length, including extension blocks (Takashi)
> free EDID on teardown (Takashi)
> v3: malloc a new EDID buffer that's big enough for the memcpy (Chris)
> v4: change handling of NULL EDIDs, just preserve the NULL behavior
> across detects and mode list fetches rather than trying to re-fetch
> the EDID (Chris)
> v5: be glad that Chris is around to remind me to hit C-x C-s before
> committing.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=46856
> Signed-off-by: Jesse Barnes 
> ---
>  drivers/gpu/drm/i915/intel_dp.c |   49 
> ++-
>  1 file changed, 43 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 6538c46..69d2f0c 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -32,6 +32,7 @@
>  #include "drm.h"
>  #include "drm_crtc.h"
>  #include "drm_crtc_helper.h"
> +#include "drm_edid.h"
>  #include "intel_drv.h"
>  #include "i915_drm.h"
>  #include "i915_drv.h"
> @@ -67,6 +68,8 @@ struct intel_dp {
>   struct drm_display_mode *panel_fixed_mode;  /* for eDP */
>   struct delayed_work panel_vdd_work;
>   bool want_panel_vdd;
> + struct edid *edid; /* cached EDID for eDP */
> + int edid_mode_count;
>  };
>  
>  /**
> @@ -2121,10 +2124,22 @@ intel_dp_get_edid(struct drm_connector *connector, 
> struct i2c_adapter *adapter)
>  {
>   struct intel_dp *intel_dp = intel_attached_dp(connector);
>   struct edid *edid;
> + int size;
> +
> + if (is_edp(intel_dp)) {
> + if (!intel_dp->edid)
> + return NULL;
> +
> + size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
> + edid = kmalloc(size, GFP_KERNEL);
> + if (!edid)
> + return NULL;
> +
> + memcpy(edid, intel_dp->edid, size);
> + return edid;
> + }
>  
> - ironlake_edp_panel_vdd_on(intel_dp);
>   edid = drm_get_edid(connector, adapter);
> - ironlake_edp_panel_vdd_off(intel_dp, false);
>   return edid;
>  }
>  
> @@ -2134,9 +2149,17 @@ intel_dp_get_edid_modes(struct drm_connector 
> *connector, struct i2c_adapter *ada
>   struct intel_dp *intel_dp = intel_attached_dp(connector);
>   int ret;
>  
> - ironlake_edp_panel_vdd_on(intel_dp);
> + if (is_edp(intel_dp)) {
> + drm_mode_connector_update_edid_property(connector,
> + intel_dp->edid);
> + ret = drm_add_edid_modes(connector, intel_dp->edid);

Hi Jesse, I'm sure you meant to do *something* with that return value. I
presume it should be equal to intel_dp->edid_mode_count, but is it
possible it's not? Is it better to return ret or
intel_dp->edid_mode_count from this function?

BR,
Jani.


> + drm_edid_to_eld(connector,
> + intel_dp->edid);
> + connector->display_info.raw_edid = NULL;
> + return intel_dp->edid_mode_count;
> + }
> +
>   ret = intel_ddc_get_modes(connector, adapter);
> - ironlake_edp_panel_vdd_off(intel_dp, false);
>   return ret;
>  }
>  
> @@ -2326,6 +2349,7 @@ static void intel_dp_encoder_destroy(struct drm_encoder 
> *encoder)
>   i2c_del_adapter(&intel_dp->adapter);
>   drm_encoder_cleanup(encoder);
>   if (is_edp(intel_dp)) {
> + kfree(intel_dp->edid);
>   cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
>   ironlake_panel_vdd_off_sync(intel_dp);
>   }
> @@ -2509,11 +2533,14 @@ intel_dp_init(struct drm_device *dev, int output_reg)
>   break;
>   }
>  
> + intel_dp_i2c_init(intel_dp, intel_connector, name);
> +
>   /* Cache some DPCD data in the eDP case */
>   if (is_edp(intel_dp)) {
>   bool ret;
>   struct edp_power_seqcur, vbt;
>   u32 pp_on, pp_off, pp_div;
> + struct edid *edid;
>  
>   pp_on = I915_READ(PCH_PP_ON_DELAYS);
>   pp_off = I915_READ(PCH_PP_OFF_DELAYS);
> @@ -2581,9 +2608,19 @@ intel_dp_init(struct drm_device *dev, int output_reg)
>   intel_dp_destroy(&intel_connector->base);
>   return;
>   }
> - }
>  
> - intel_dp_i2c_init(intel_dp, intel_connector, name);
> + ironlake_edp_panel_vdd_on(intel_dp);
> + edid = drm_get_edid(connector, &intel_dp->adapter);
> + if (edid) {
> + drm_mode_connector_update_edid_property(connector,
> + edid);
> +

[Intel-gfx] [PATCH] drm/i915: cache the EDID for eDP panels

2012-06-15 Thread Chris Wilson 
They aren't going anywhere, and probing on DDC can cause the panel to
blank briefly, so read them up front and cache them for later queries.

Jesse's patch revamped. Gotta love those display_info.raw_edid = NULL!
---
 drivers/gpu/drm/i915/intel_dp.c|   48 +++-
 drivers/gpu/drm/i915/intel_drv.h   |1 +
 drivers/gpu/drm/i915/intel_modes.c |   24 --
 3 files changed, 54 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index eb57ec7..207e25f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -67,6 +67,7 @@ struct intel_dp {
struct drm_display_mode *panel_fixed_mode;  /* for eDP */
struct delayed_work panel_vdd_work;
bool want_panel_vdd;
+   struct edid *edid; /* cached for eDP */
 };
 
 /**
@@ -2095,26 +2096,50 @@ g4x_dp_detect(struct intel_dp *intel_dp)
 }
 
 static struct edid *
-intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
+_drm_edid_duplicate(struct edid *edid)
+{
+   struct edid *copy;
+   int size;
+
+   if (edid == NULL)
+   return NULL;
+
+   size = EDID_LENGTH * (1 + edid->extensions);
+   *copy = kmalloc(size, GFP_KERNEL);
+   if (copy)
+   memcpy(copy, edid, size);
+
+   return copy;
+}
+
+static struct edid *
+intel_dp_get_edid(struct drm_connector *connector)
 {
struct intel_dp *intel_dp = intel_attached_dp(connector);
-   struct edid *edid;
+   struct edid *edid;
+
+   if (is_edp(intel_dp))
+   return _drm_edid_duplicate(intel_dp->edid);
 
ironlake_edp_panel_vdd_on(intel_dp);
-   edid = drm_get_edid(connector, adapter);
+   edid = drm_get_edid(connector, &intel_dp->adapter);
ironlake_edp_panel_vdd_off(intel_dp, false);
+
return edid;
 }
 
 static int
-intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter 
*adapter)
+intel_dp_get_edid_modes(struct drm_connector *connector)
 {
struct intel_dp *intel_dp = intel_attached_dp(connector);
-   int ret;
+   struct edid *edid;
+   int ret;
+
+   edid = intel_dp_get_edid(intel_dp);
+   ret = intel_connector_attach_edid(connector, edid);
+   connector->display_info.raw_edid = NULL;
+   kfree(edid);
 
-   ironlake_edp_panel_vdd_on(intel_dp);
-   ret = intel_ddc_get_modes(connector, adapter);
-   ironlake_edp_panel_vdd_off(intel_dp, false);
return ret;
 }
 
@@ -2172,7 +2197,7 @@ static int intel_dp_get_modes(struct drm_connector 
*connector)
/* We should parse the EDID data and find out if it has an audio sink
 */
 
-   ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
+   ret = intel_dp_get_edid_modes(connector);
if (ret) {
if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
struct drm_display_mode *newmode;
@@ -2485,6 +2510,8 @@ intel_dp_init(struct drm_device *dev, int output_reg)
break;
}
 
+   intel_dp_i2c_init(intel_dp, intel_connector, name);
+
/* Cache some DPCD data in the eDP case */
if (is_edp(intel_dp)) {
bool ret;
@@ -2543,6 +2570,7 @@ intel_dp_init(struct drm_device *dev, int output_reg)
 
ironlake_edp_panel_vdd_on(intel_dp);
ret = intel_dp_get_dpcd(intel_dp);
+   intel_dp->edid = drm_get_edid(connector, &intel_dp->adapter);
ironlake_edp_panel_vdd_off(intel_dp, false);
 
if (ret) {
@@ -2559,8 +2587,6 @@ intel_dp_init(struct drm_device *dev, int output_reg)
}
}
 
-   intel_dp_i2c_init(intel_dp, intel_connector, name);
-
intel_encoder->hot_plug = intel_dp_hot_plug;
 
if (is_edp(intel_dp)) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3e09188..316413d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -336,6 +336,7 @@ struct intel_fbc_work {
 
 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus);
+int intel_connector_attach_edid(struct drm_connector *connector, struct edid 
*edid);
 
 extern void intel_attach_force_audio_property(struct drm_connector *connector);
 extern void intel_attach_broadcast_rgb_property(struct drm_connector 
*connector);
diff --git a/drivers/gpu/drm/i915/intel_modes.c 
b/drivers/gpu/drm/i915/intel_modes.c
index d67ec3a..089ed8b 100644
--- a/drivers/gpu/drm/i915/intel_modes.c
+++ b/drivers/gpu/drm/i915/intel_modes.c
@@ -60,6 +60,18 @@ bool intel_ddc_probe(struct intel_encoder *intel_encoder, 
int ddc_bus)
msgs, 2) == 2;
 }
 
+int intel_connector_attach_edid(struct drm_connector *connector,
+   struct edid *edi

Re: [Intel-gfx] [PATCH] Revert "drm/i915/dp: Use auxch precharge value of 5 everywhere"

2012-06-15 Thread Daniel Vetter 
On Thu, Jun 14, 2012 at 10:15:00PM +0200, Daniel Vetter wrote:
> This reverts commit 092945e11c5b84f66dd08f0b87fb729715d377bc.
> 
> This commit prevents a DP screen from properly training the link.
> Oddly enough it works, once the machine has been warm-booted with an
> older kernel.
> 
> According to DP docs this _should_ have been the right precharge time.
> Also, the commit that originally introduces this was just general snb
> DP enabling and didn't mention any specific reason for this special
> value. Whatever, trust the reporter that this makes things worse and
> let's just revert it.
> 
> v2: Less spelling fail.
> 
> Cc: Adam Jackson 
> Cc: Jesse Barnes 
> Reported-by: "Wouter M. Koolen" 
> Buglink: https://lkml.org/lkml/2012/6/14/301
> Signed-Off-by: Daniel Vetter 
No one yelled around with a better idea, so I've picked this up for fixes
with cc stable.
-Daniel
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Mobile: +41 (0)79 365 57 48
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[Intel-gfx] Stupid question: Latest GIT repository?

2012-06-15 Thread Johannes Bauer 
Hi list,

sorry for this question, but I'm puzzled and cannot figure out the
correct answer: What is actually the most recently updated GIT
repository? I'd like to try a newer version (had previously issues with
sleeping on Sandy Bridge).

Keith's repository (which is referred to by the website) has on the
drm-intel-fixes branch its latest commit from 2012-03-07.

Eugeni's repository is on the 3.2-stable branch from 2012-02-08, on the
rc6 branch (which is something I'm interested in, especially 1c9b22f81)
from 2012-01-03.

However on the mailing list I frequently see patches -- but I really
have no clue where they go :-/

So again sorry for this stupid question, but could somebody please point
out where the new stuff goes?

Best regards,
Johannes
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Re: [Intel-gfx] [PATCH] drm/i915: cache the EDID for eDP panels

2012-06-15 Thread Jani Nikula 
On Fri, 15 Jun 2012, Chris Wilson  wrote:
> They aren't going anywhere, and probing on DDC can cause the panel to
> blank briefly, so read them up front and cache them for later queries.
>
> Jesse's patch revamped. Gotta love those display_info.raw_edid = NULL!
> ---
>  drivers/gpu/drm/i915/intel_dp.c|   48 
> +++-
>  drivers/gpu/drm/i915/intel_drv.h   |1 +
>  drivers/gpu/drm/i915/intel_modes.c |   24 --
>  3 files changed, 54 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index eb57ec7..207e25f 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -67,6 +67,7 @@ struct intel_dp {
>   struct drm_display_mode *panel_fixed_mode;  /* for eDP */
>   struct delayed_work panel_vdd_work;
>   bool want_panel_vdd;
> + struct edid *edid; /* cached for eDP */
>  };
>  
>  /**
> @@ -2095,26 +2096,50 @@ g4x_dp_detect(struct intel_dp *intel_dp)
>  }
>  
>  static struct edid *
> -intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter 
> *adapter)
> +_drm_edid_duplicate(struct edid *edid)
> +{
> + struct edid *copy;
> + int size;
> +
> + if (edid == NULL)
> + return NULL;
> +
> + size = EDID_LENGTH * (1 + edid->extensions);
> + *copy = kmalloc(size, GFP_KERNEL);

You may want to remove that '*' there...

Jani.

> + if (copy)
> + memcpy(copy, edid, size);
> +
> + return copy;
> +}
> +
> +static struct edid *
> +intel_dp_get_edid(struct drm_connector *connector)
>  {
>   struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct edid *edid;
> + struct edid *edid;
> +
> + if (is_edp(intel_dp))
> + return _drm_edid_duplicate(intel_dp->edid);
>  
>   ironlake_edp_panel_vdd_on(intel_dp);
> - edid = drm_get_edid(connector, adapter);
> + edid = drm_get_edid(connector, &intel_dp->adapter);
>   ironlake_edp_panel_vdd_off(intel_dp, false);
> +
>   return edid;
>  }
>  
>  static int
> -intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter 
> *adapter)
> +intel_dp_get_edid_modes(struct drm_connector *connector)
>  {
>   struct intel_dp *intel_dp = intel_attached_dp(connector);
> - int ret;
> + struct edid *edid;
> + int ret;
> +
> + edid = intel_dp_get_edid(intel_dp);
> + ret = intel_connector_attach_edid(connector, edid);
> + connector->display_info.raw_edid = NULL;
> + kfree(edid);
>  
> - ironlake_edp_panel_vdd_on(intel_dp);
> - ret = intel_ddc_get_modes(connector, adapter);
> - ironlake_edp_panel_vdd_off(intel_dp, false);
>   return ret;
>  }
>  
> @@ -2172,7 +2197,7 @@ static int intel_dp_get_modes(struct drm_connector 
> *connector)
>   /* We should parse the EDID data and find out if it has an audio sink
>*/
>  
> - ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
> + ret = intel_dp_get_edid_modes(connector);
>   if (ret) {
>   if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
>   struct drm_display_mode *newmode;
> @@ -2485,6 +2510,8 @@ intel_dp_init(struct drm_device *dev, int output_reg)
>   break;
>   }
>  
> + intel_dp_i2c_init(intel_dp, intel_connector, name);
> +
>   /* Cache some DPCD data in the eDP case */
>   if (is_edp(intel_dp)) {
>   bool ret;
> @@ -2543,6 +2570,7 @@ intel_dp_init(struct drm_device *dev, int output_reg)
>  
>   ironlake_edp_panel_vdd_on(intel_dp);
>   ret = intel_dp_get_dpcd(intel_dp);
> + intel_dp->edid = drm_get_edid(connector, &intel_dp->adapter);
>   ironlake_edp_panel_vdd_off(intel_dp, false);
>  
>   if (ret) {
> @@ -2559,8 +2587,6 @@ intel_dp_init(struct drm_device *dev, int output_reg)
>   }
>   }
>  
> - intel_dp_i2c_init(intel_dp, intel_connector, name);
> -
>   intel_encoder->hot_plug = intel_dp_hot_plug;
>  
>   if (is_edp(intel_dp)) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index 3e09188..316413d 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -336,6 +336,7 @@ struct intel_fbc_work {
>  
>  int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter 
> *adapter);
>  extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int 
> ddc_bus);
> +int intel_connector_attach_edid(struct drm_connector *connector, struct edid 
> *edid);
>  
>  extern void intel_attach_force_audio_property(struct drm_connector 
> *connector);
>  extern void intel_attach_broadcast_rgb_property(struct drm_connector 
> *connector);
> diff --git a/drivers/gpu/drm/i915/intel_modes.c 
> b/drivers/gpu/drm/i915/intel_modes.c
> index d67ec3a..089ed8b 100644
> --- a/drivers/gpu/drm/i915/intel_modes.c
> +++ b/drivers/gpu/drm/i915/i

Re: [Intel-gfx] [PATCH] drm/i915: cache the EDID for eDP panels

2012-06-15 Thread Chris Wilson 
On Fri, 15 Jun 2012 13:52:04 +0300, Jani Nikula  
wrote:
> On Fri, 15 Jun 2012, Chris Wilson  wrote:
> > They aren't going anywhere, and probing on DDC can cause the panel to
> > blank briefly, so read them up front and cache them for later queries.
> >
> > Jesse's patch revamped. Gotta love those display_info.raw_edid = NULL!
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c|   48 
> > +++-
> >  drivers/gpu/drm/i915/intel_drv.h   |1 +
> >  drivers/gpu/drm/i915/intel_modes.c |   24 --
> >  3 files changed, 54 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index eb57ec7..207e25f 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -67,6 +67,7 @@ struct intel_dp {
> > struct drm_display_mode *panel_fixed_mode;  /* for eDP */
> > struct delayed_work panel_vdd_work;
> > bool want_panel_vdd;
> > +   struct edid *edid; /* cached for eDP */
> >  };
> >  
> >  /**
> > @@ -2095,26 +2096,50 @@ g4x_dp_detect(struct intel_dp *intel_dp)
> >  }
> >  
> >  static struct edid *
> > -intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter 
> > *adapter)
> > +_drm_edid_duplicate(struct edid *edid)
> > +{
> > +   struct edid *copy;
> > +   int size;
> > +
> > +   if (edid == NULL)
> > +   return NULL;
> > +
> > +   size = EDID_LENGTH * (1 + edid->extensions);
> > +   *copy = kmalloc(size, GFP_KERNEL);
> 
> You may want to remove that '*' there...

And free the cached edid upon destroy. :)
Mainly seeing if I could convince Jesse that we could do a nice patch
for -fixes.
-Chris

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Re: [Intel-gfx] Stupid question: Latest GIT repository?

2012-06-15 Thread Daniel Vetter 
On Fri, Jun 15, 2012 at 12:17 PM, Johannes Bauer  wrote:
> Hi list,
>
> sorry for this question, but I'm puzzled and cannot figure out the
> correct answer: What is actually the most recently updated GIT
> repository? I'd like to try a newer version (had previously issues with
> sleeping on Sandy Bridge).
>
> Keith's repository (which is referred to by the website) has on the
> drm-intel-fixes branch its latest commit from 2012-03-07.
>
> Eugeni's repository is on the 3.2-stable branch from 2012-02-08, on the
> rc6 branch (which is something I'm interested in, especially 1c9b22f81)
> from 2012-01-03.
>
> However on the mailing list I frequently see patches -- but I really
> have no clue where they go :-/
>
> So again sorry for this stupid question, but could somebody please point
> out where the new stuff goes?

In my maintainer git repo at:

http://cgit.freedesktop.org/~danvet/drm-intel

Both the MAINTAINERS file in the kernel and our OTC graphics page are
updated, see:

http://intellinuxgraphics.org/download.html

Can you please tell me where Keith's repo is still referred to?

Thanks, Daniel
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[Intel-gfx] [PATCH 0/2] Valleyview PLL fix and cleanup

2012-06-15 Thread Vijay Purushothaman 
Fixed the wrong p2 PLL values and replaced all hardcoded numbers in best PLL
calculation. These two patches should be applied on top of Jesse's Jun 14 
Valleyview patch set.

Tried to refactor the code to avoid so many nested loops but ended up messing 
other VLV code. Any help with code refactoring, most welcome! 

Thanks,
Vijay


Vijay Purushothaman (2):
  drm/i915 : fix incorrect p2 values for Valleyview
  drm/i915: cleanup Valleyview PLL calculation

 drivers/gpu/drm/i915/intel_display.c |   58 ++
 1 files changed, 24 insertions(+), 34 deletions(-)

-- 
1.7.5.4

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[Intel-gfx] [PATCH 1/2] drm/i915 : fix incorrect p2 values for Valleyview

2012-06-15 Thread Vijay Purushothaman 
Signed-off-by: Vijay Purushothaman 
---
 drivers/gpu/drm/i915/intel_display.c |6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 157dcb0a..0707b7a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -374,7 +374,7 @@ static const intel_limit_t intel_limits_vlv_dac = {
.p = { .min = 10, .max = 30 },
.p1 = { .min = 2, .max = 3 },
.p2 = { .dot_limit = 27,
-   .p2_slow = 10, .p2_fast = 5 },
+   .p2_slow = 2, .p2_fast = 20 },
.find_pll = intel_vlv_find_best_pll,
 };
 
@@ -388,7 +388,7 @@ static const intel_limit_t intel_limits_vlv_hdmi = {
.p = { .min = 10, .max = 30 },
.p1 = { .min = 2, .max = 3 },
.p2 = { .dot_limit = 27,
-   .p2_slow = 10, .p2_fast = 5 },
+   .p2_slow = 2, .p2_fast = 20 },
.find_pll = intel_vlv_find_best_pll,
 };
 
@@ -402,7 +402,7 @@ static const intel_limit_t intel_limits_vlv_dp = {
.p = { .min = 10, .max = 30 },
.p1 = { .min = 2, .max = 3 },
.p2 = { .dot_limit = 27,
-   .p2_slow = 10, .p2_fast = 5 },
+   .p2_slow = 2, .p2_fast = 20 },
.find_pll = intel_vlv_find_best_pll,
 };
 
-- 
1.7.5.4

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[Intel-gfx] [PATCH 2/2] drm/i915: cleanup Valleyview PLL calculation

2012-06-15 Thread Vijay Purushothaman 
replaced hardcoded numbers with valid PLL limit values

Signed-off-by: Vijay Purushothaman 
---
 drivers/gpu/drm/i915/intel_display.c |   52 +
 1 files changed, 21 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0707b7a..e2d23a3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -865,69 +865,59 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, 
struct drm_crtc *crtc,
intel_clock_t *best_clock)
 {
u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
-   u32 m, n, fastclk, minvco, maxvco;
+   u32 m, n, fastclk;
u32 updrate, minupdate, fracbits, p;
unsigned long bestppm, ppm, absppm;
-   int dotclk;
+   int dotclk, flag;
 
dotclk = target * 1000;
-
bestppm = 100;
-   ppm = 0;
-   absppm = 0;
-
+   ppm = absppm = 0;
fastclk = dotclk / (2*100);
-   minvco = limit->vco.min;
-   maxvco = limit->vco.max;
updrate = 0;
minupdate = 19200;
fracbits = 1;
-
n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
bestm1 = bestm2 = bestp1 = bestp2 = 0;
 
-   for(n = 1; n <= ((refclk) / minupdate); n++) {
+   /* based on hardware requirement, prefer smaller n to precision */
+   for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
updrate = refclk / n;
-   for (p1 = 3; p1 > 1; p1--) {
-   for (p2 = 21; p2 > 0; p2--) {
+   for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
+   for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
if (p2 > 10)
p2 = p2 - 1;
p = p1 * p2;
-
-   for( m1=2; m1 <= 3; m1++) {
+   /* based on hardware requirement, prefer bigger 
m1,m2 values */
+   for (m1 = limit->m1.min; m1 <= limit->m1.max; 
m1++) {
m2 = (((2*(fastclk * p * n / m1 )) +
   refclk) / (2*refclk));
m = m1 * m2;
vco = updrate * m;
-   if(vco >= minvco && vco < maxvco) {
-   ppm = 100 *((vco / p) -
-   fastclk) /
-   fastclk;
-   absppm = (ppm > 0)? ppm: (-ppm);
-   if (absppm < 100 &&
-   ((p1 * p2) >
-(bestp1 * bestp2))) {
+   if (vco >= limit->vco.min && vco < 
limit->vco.max) {
+   ppm = 100 * ((vco / p) - 
fastclk) / fastclk;
+   absppm = (ppm > 0) ? ppm : 
(-ppm);
+   if (absppm < 100 && ((p1 * p2) 
> (bestp1 * bestp2))) {
bestppm = 0;
-   bestn = n;
-   bestm1 = m1;
-   bestm2 = m2;
-   bestp1 = p1;
-   bestp2 = p2;
+   flag = 1;
}
if (absppm < bestppm - 10) {
bestppm = absppm;
+   flag = 1;
+   }
+   if (flag) {
bestn = n;
bestm1 = m1;
bestm2 = m2;
bestp1 = p1;
bestp2 = p2;
+   flag = 0;
}
}
}
-   } /* Next p2 */
-   } /* Next p1 */
-   }/* Next n */
-
+   }
+   }
+   }
best_clock->n = bestn;
best_clock->m1 = bestm1;
best_clock->m2 = bestm2;
-- 
1.7.

Re: [Intel-gfx] Stupid question: Latest GIT repository?

2012-06-15 Thread Eugeni Dodonov 
On Fri, Jun 15, 2012 at 11:36 AM, Daniel Vetter  wrote:

> Both the MAINTAINERS file in the kernel and our OTC graphics page are
> updated, see:
>
> http://intellinuxgraphics.org/download.html
>
> Can you please tell me where Keith's repo is still referred to?
>

Also, note that by some weird reason intellinuxgraphics.org sometimes lists
its pages as unchanged if you have it in your cache. So if it still shows
Keith's repo there, just reload it with shift-reload :).

-- 
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Re: [Intel-gfx] Stupid question: Latest GIT repository?

2012-06-15 Thread Johannes Bauer 
On 15.06.2012 16:47, Eugeni Dodonov wrote:
> On Fri, Jun 15, 2012 at 11:36 AM, Daniel Vetter  wrote:
> 
>> Both the MAINTAINERS file in the kernel and our OTC graphics page are
>> updated, see:
>>
>> http://intellinuxgraphics.org/download.html
>>
>> Can you please tell me where Keith's repo is still referred to?
> 
> Also, note that by some weird reason intellinuxgraphics.org sometimes lists
> its pages as unchanged if you have it in your cache. So if it still shows
> Keith's repo there, just reload it with shift-reload :).

Aaaah, indeed that was the problem. I'm very sorry for the confusion.
Happily cloning the new repo now, the link now correctly points to
Daniel's repository :-)

Best regards,
Joe


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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Group the GT routines together in both code and vtable

2012-06-15 Thread Eugeni Dodonov 
On 06/13/2012 04:47 PM, Chris Wilson wrote:
> On Wed, 13 Jun 2012 12:07:19 -0700, Ben Widawsky  wrote:
>> On Wed, 13 Jun 2012 18:29:51 +0100
>> Chris Wilson  wrote:
>>
>>> Tidy up the routines for interacting with the GT (in particular the
>>> forcewake dance) which are scattered throughout the code in a single
>>> structure.
>>
>> A few comments inline. First though, the bikeshed:
>>
>> I'd really rather the structure not be named, "gt" unless you have
>> further reaching plans for it. GT is way to generic. Also, I think it
>> makes a lot of sense to move the forcewake dancing into intel_pm.c
> 
> This patch predated the intel_pm split. I toyed with the idea of
> updating it, but preferred to get feedback first. Shall we call it
> grantsdale instead? Or uncore? My opinion is that this more core
> functionality than power-management, but first and foremost it
> should not be scattered across multiple files.

I liked the idea of 'gt' because this is how the docs call it too. And
our power code is hidden all around indeed.

So I'd vote for this patch once it gets updated to intel_pm. I'll even
volunteer myself to adjust the power wells and new force wake stuff to
it when it becomes ready :).

Eugeni
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Re: [Intel-gfx] [PATCH] drm/i915: cache the EDID for eDP panels

2012-06-15 Thread Jesse Barnes 
On Fri, 15 Jun 2012 10:34:22 +0300
Jani Nikula  wrote:

> On Thu, 14 Jun 2012, Jesse Barnes  wrote:
> > They aren't going anywhere, and probing on DDC can cause the panel to
> > blank briefly, so read them up front and cache them for later queries.
> >
> > v2: fix potential NULL derefs in intel_dp_get_edid_modes and
> > intel_dp_get_edid (Jani)
> > copy full EDID length, including extension blocks (Takashi)
> > free EDID on teardown (Takashi)
> > v3: malloc a new EDID buffer that's big enough for the memcpy (Chris)
> > v4: change handling of NULL EDIDs, just preserve the NULL behavior
> > across detects and mode list fetches rather than trying to re-fetch
> > the EDID (Chris)
> > v5: be glad that Chris is around to remind me to hit C-x C-s before
> > committing.
> >
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=46856
> > Signed-off-by: Jesse Barnes 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c |   49 
> > ++-
> >  1 file changed, 43 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 6538c46..69d2f0c 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -32,6 +32,7 @@
> >  #include "drm.h"
> >  #include "drm_crtc.h"
> >  #include "drm_crtc_helper.h"
> > +#include "drm_edid.h"
> >  #include "intel_drv.h"
> >  #include "i915_drm.h"
> >  #include "i915_drv.h"
> > @@ -67,6 +68,8 @@ struct intel_dp {
> > struct drm_display_mode *panel_fixed_mode;  /* for eDP */
> > struct delayed_work panel_vdd_work;
> > bool want_panel_vdd;
> > +   struct edid *edid; /* cached EDID for eDP */
> > +   int edid_mode_count;
> >  };
> >  
> >  /**
> > @@ -2121,10 +2124,22 @@ intel_dp_get_edid(struct drm_connector *connector, 
> > struct i2c_adapter *adapter)
> >  {
> > struct intel_dp *intel_dp = intel_attached_dp(connector);
> > struct edid *edid;
> > +   int size;
> > +
> > +   if (is_edp(intel_dp)) {
> > +   if (!intel_dp->edid)
> > +   return NULL;
> > +
> > +   size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
> > +   edid = kmalloc(size, GFP_KERNEL);
> > +   if (!edid)
> > +   return NULL;
> > +
> > +   memcpy(edid, intel_dp->edid, size);
> > +   return edid;
> > +   }
> >  
> > -   ironlake_edp_panel_vdd_on(intel_dp);
> > edid = drm_get_edid(connector, adapter);
> > -   ironlake_edp_panel_vdd_off(intel_dp, false);
> > return edid;
> >  }
> >  
> > @@ -2134,9 +2149,17 @@ intel_dp_get_edid_modes(struct drm_connector 
> > *connector, struct i2c_adapter *ada
> > struct intel_dp *intel_dp = intel_attached_dp(connector);
> > int ret;
> >  
> > -   ironlake_edp_panel_vdd_on(intel_dp);
> > +   if (is_edp(intel_dp)) {
> > +   drm_mode_connector_update_edid_property(connector,
> > +   intel_dp->edid);
> > +   ret = drm_add_edid_modes(connector, intel_dp->edid);
> 
> Hi Jesse, I'm sure you meant to do *something* with that return value. I
> presume it should be equal to intel_dp->edid_mode_count, but is it
> possible it's not? Is it better to return ret or
> intel_dp->edid_mode_count from this function?
> 

Heh there's always something... but yeah it should be equal to the
mode_count; I should either drop the ret= or use it.  Maybe as a
cleanup on top since I'm tired of respinning this one? :p


-- 
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Re: [Intel-gfx] [PATCH] drm/i915: cache the EDID for eDP panels

2012-06-15 Thread Daniel Vetter 
On Fri, Jun 15, 2012 at 10:31:06AM -0700, Jesse Barnes wrote:
> On Fri, 15 Jun 2012 10:34:22 +0300
> Jani Nikula  wrote:
> > Hi Jesse, I'm sure you meant to do *something* with that return value. I
> > presume it should be equal to intel_dp->edid_mode_count, but is it
> > possible it's not? Is it better to return ret or
> > intel_dp->edid_mode_count from this function?
> > 
> 
> Heh there's always something... but yeah it should be equal to the
> mode_count; I should either drop the ret= or use it.  Maybe as a
> cleanup on top since I'm tired of respinning this one? :p

I guess we can mend that bikeshed when we unify the panel handling some
more between lvds and eDP. Patch merged for -fixes, thanks.
-Daniel
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Mail: dan...@ffwll.ch
Mobile: +41 (0)79 365 57 48
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Implement w/a for sporadic read failures on waking from rc6

2012-06-15 Thread Eugeni Dodonov 
On 06/13/2012 02:29 PM, Chris Wilson wrote:
> As a w/a to prevent reads sporadically returning 0, we need to wait for
> the GT thread to return to TC0 before proceeding to read the registers.
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=50243
> Signed-off-by: Chris Wilson 

Reviewed-by: Eugeni Dodonov 

I think that this patch could solve some of the RC6-related issues which
are still out there. So the ones of you affected by random GPU hangs or
dropped writes, could you please give this patch a try?

Eugeni
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[Intel-gfx] [PATCH 02/14] drm/i915: Enable DP panel power sequencing for ValleyView

2012-06-15 Thread Jesse Barnes 
From: Shobhit Kumar 

VLV supports two dp panels, there are two set of panel power sequence
registers which needed to be programmed based on the configured
pipe. This patch add supports for the same

Acked-by: Acked-by: Ben Widawsky 
Signed-off-by: Beeresh G 
Reviewed-by: Vijay Purushothaman 
Reviewed-by: Jesse Barnes 
Signed-off-by: Jesse Barnes 
---
 drivers/gpu/drm/i915/i915_reg.h |   12 
 drivers/gpu/drm/i915/intel_dp.c |8 +++-
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 281446d..a9e9d92 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3854,6 +3854,18 @@
 
 #define BLC_PWM_PCH_CTL2   0xc8254
 
+#define PIPEA_PP_STATUS 0x61200
+#define PIPEA_PP_CONTROL0x61204
+#define PIPEA_PP_ON_DELAYS  0x61208
+#define PIPEA_PP_OFF_DELAYS 0x6120c
+#define PIPEA_PP_DIVISOR0x61210
+
+#define PIPEB_PP_STATUS 0x61300
+#define PIPEB_PP_CONTROL0x61304
+#define PIPEB_PP_ON_DELAYS  0x61308
+#define PIPEB_PP_OFF_DELAYS 0x6130c
+#define PIPEB_PP_DIVISOR0x61310
+
 #define PCH_PP_STATUS  0xc7200
 #define PCH_PP_CONTROL 0xc7204
 #define  PANEL_UNLOCK_REGS (0xabcd << 16)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6538c46..d59af24 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -342,7 +342,13 @@ static bool ironlake_edp_have_panel_power(struct intel_dp 
*intel_dp)
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
 
-   return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
+   if (IS_VALLEYVIEW(dev)) {
+   if (I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT)
+   return (I915_READ(PIPEB_PP_STATUS) & PP_ON) != 0;
+   else
+   return (I915_READ(PIPEA_PP_STATUS) & PP_ON) != 0;
+   } else
+   return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 }
 
 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
-- 
1.7.9.5

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[Intel-gfx] [PATCH 03/14] drm/i915: add ValleyView specific CRT detect function

2012-06-15 Thread Jesse Barnes 
Might be able to merge this back in at some point, but we're seeing bugs
with ADPA based detection, so keep it separate for now with explicit
hotplug trigger usage.

v2: drop superfluous debug message
v3: comment forced detection, need to debug (Eugeni)

Reviewed-by: Eugeni Dodonov 
Signed-off-by: Jesse Barnes 
---
 drivers/gpu/drm/i915/intel_crt.c |   39 ++
 1 file changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 75a70c4..1333a65 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -230,6 +230,42 @@ static bool intel_ironlake_crt_detect_hotplug(struct 
drm_connector *connector)
return ret;
 }
 
+static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
+{
+   struct drm_device *dev = connector->dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   u32 adpa;
+   bool ret;
+   u32 save_adpa;
+
+   save_adpa = adpa = I915_READ(ADPA);
+   DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
+
+   adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
+
+   I915_WRITE(ADPA, adpa);
+
+   if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
+1000)) {
+   DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
+   I915_WRITE(ADPA, save_adpa);
+   }
+
+   /* Check the status to see if both blue and green are on now */
+   adpa = I915_READ(ADPA);
+   if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
+   ret = true;
+   else
+   ret = false;
+
+   DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
+
+   /* FIXME: debug force function and remove */
+   ret = true;
+
+   return ret;
+}
+
 /**
  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  *
@@ -249,6 +285,9 @@ static bool intel_crt_detect_hotplug(struct drm_connector 
*connector)
if (HAS_PCH_SPLIT(dev))
return intel_ironlake_crt_detect_hotplug(connector);
 
+   if (IS_VALLEYVIEW(dev))
+   return valleyview_crt_detect_hotplug(connector);
+
/*
 * On 4 series desktop, CRT detect sequence need to be done twice
 * to get a reliable result.
-- 
1.7.9.5

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[Intel-gfx] [PATCH 04/14] drm/i915: add HDMI and DP port enumeration on ValleyView

2012-06-15 Thread Jesse Barnes 
ValleyView is similar to IbexPeak here, but with different register
offsets.

v2: use SDVOB instead ov VLV_HDMIB (Daniel)
drop unnecessary eDP check in DP_C init (Daniel)

eDP support will be coming later from Shobit.

Signed-off-by: Jesse Barnes 
---
 drivers/gpu/drm/i915/i915_reg.h  |1 -
 drivers/gpu/drm/i915/intel_display.c |   17 +
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a9e9d92..263b50c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3808,7 +3808,6 @@
 #define  ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
 
 /* or SDVOB */
-#define VLV_HDMIB 0x61140
 #define HDMIB   0xe1140
 #define  PORT_ENABLE(1 << 31)
 #define  TRANSCODER(pipe)   ((pipe) << 30)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index f8ea7bc..e2d23a3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6762,7 +6762,24 @@ static void intel_setup_outputs(struct drm_device *dev)
 
if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
intel_dp_init(dev, PCH_DP_D);
+   } else if (IS_VALLEYVIEW(dev)) {
+   int found;
+
+   if (I915_READ(SDVOB) & PORT_DETECTED) {
+   /* SDVOB multiplex with HDMIB */
+   found = intel_sdvo_init(dev, SDVOB, true);
+   if (!found)
+   intel_hdmi_init(dev, SDVOB);
+   if (!found && (I915_READ(DP_B) & DP_DETECTED))
+   intel_dp_init(dev, DP_B);
+   }
+
+   if (I915_READ(SDVOC) & PORT_DETECTED)
+   intel_hdmi_init(dev, SDVOC);
 
+   /* Shares lanes with HDMI on SDVOC */
+   if (I915_READ(DP_C) & DP_DETECTED)
+   intel_dp_init(dev, DP_C);
} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
bool found = false;
 
-- 
1.7.9.5

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[Intel-gfx] [PATCH 01/14] drm/i915: ValleyView mode setting limits and PLL functions

2012-06-15 Thread Jesse Barnes 
Add some VLV limit structures and update the PLL code.

v2: resolve conflicts, Vijay to re-post with PLL valid checks and fixed limits
v3: re-add dpio write function
v4: squash in Vijay's fixes for the PLL limits and clean up the m/n finder

Signed-off-by: Shobhit Kumar 
Signed-off-by: Vijay Purushothaman 
Signed-off-by: Jesse Barnes 
---
 drivers/gpu/drm/i915/i915_reg.h  |1 +
 drivers/gpu/drm/i915/intel_display.c |  240 +-
 2 files changed, 239 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7dcc04f..281446d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -900,6 +900,7 @@
 #define   DPLL_P2_CLOCK_DIV_MASK   0x0300 /* i915 */
 #define   DPLL_FPA01_P1_POST_DIV_MASK  0x00ff /* i915 */
 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
+#define   DPLL_LOCK_VLV(1<<15)
 #define   DPLL_INTEGRATED_CLOCK_VLV(1<<13)
 
 #define SRX_INDEX  0x3c4
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0161d94..f8ea7bc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -98,6 +98,11 @@ intel_find_pll_ironlake_dp(const intel_limit_t *, struct 
drm_crtc *crtc,
   int target, int refclk, intel_clock_t *match_clock,
   intel_clock_t *best_clock);
 
+static bool
+intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
+   int target, int refclk, intel_clock_t *match_clock,
+   intel_clock_t *best_clock);
+
 static inline u32 /* units of 100MHz */
 intel_fdi_link_freq(struct drm_device *dev)
 {
@@ -359,6 +364,48 @@ static const intel_limit_t 
intel_limits_ironlake_display_port = {
.find_pll = intel_find_pll_ironlake_dp,
 };
 
+static const intel_limit_t intel_limits_vlv_dac = {
+   .dot = { .min = 25000, .max = 27 },
+   .vco = { .min = 400, .max = 600 },
+   .n = { .min = 1, .max = 7 },
+   .m = { .min = 22, .max = 450 }, /* guess */
+   .m1 = { .min = 2, .max = 3 },
+   .m2 = { .min = 11, .max = 156 },
+   .p = { .min = 10, .max = 30 },
+   .p1 = { .min = 2, .max = 3 },
+   .p2 = { .dot_limit = 27,
+   .p2_slow = 2, .p2_fast = 20 },
+   .find_pll = intel_vlv_find_best_pll,
+};
+
+static const intel_limit_t intel_limits_vlv_hdmi = {
+   .dot = { .min = 2, .max = 165000 },
+   .vco = { .min = 5994000, .max = 400 },
+   .n = { .min = 1, .max = 7 },
+   .m = { .min = 60, .max = 300 }, /* guess */
+   .m1 = { .min = 2, .max = 3 },
+   .m2 = { .min = 11, .max = 156 },
+   .p = { .min = 10, .max = 30 },
+   .p1 = { .min = 2, .max = 3 },
+   .p2 = { .dot_limit = 27,
+   .p2_slow = 2, .p2_fast = 20 },
+   .find_pll = intel_vlv_find_best_pll,
+};
+
+static const intel_limit_t intel_limits_vlv_dp = {
+   .dot = { .min = 162000, .max = 27 },
+   .vco = { .min = 5994000, .max = 400 },
+   .n = { .min = 1, .max = 7 },
+   .m = { .min = 60, .max = 300 }, /* guess */
+   .m1 = { .min = 2, .max = 3 },
+   .m2 = { .min = 11, .max = 156 },
+   .p = { .min = 10, .max = 30 },
+   .p1 = { .min = 2, .max = 3 },
+   .p2 = { .dot_limit = 27,
+   .p2_slow = 2, .p2_fast = 20 },
+   .find_pll = intel_vlv_find_best_pll,
+};
+
 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 {
unsigned long flags;
@@ -384,6 +431,28 @@ out_unlock:
return val;
 }
 
+static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
+u32 val)
+{
+   unsigned long flags;
+
+   spin_lock_irqsave(&dev_priv->dpio_lock, flags);
+   if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
+   DRM_ERROR("DPIO idle wait timed out\n");
+   goto out_unlock;
+   }
+
+   I915_WRITE(DPIO_DATA, val);
+   I915_WRITE(DPIO_REG, reg);
+   I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
+  DPIO_BYTE);
+   if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
+   DRM_ERROR("DPIO write wait timed out\n");
+
+out_unlock:
+   spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
+}
+
 static void vlv_init_dpio(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -510,6 +579,13 @@ static const intel_limit_t *intel_limit(struct drm_crtc 
*crtc, int refclk)
limit = &intel_limits_pineview_lvds;
else
limit = &intel_limits_pineview_sdvo;
+   } else if (IS_VALLEYVIEW(dev)) {
+   if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
+   limit = &intel_limits_vlv_dac;
+

[Intel-gfx] [PATCH 05/14] drm/i915: access VLV regs through read/write switch

2012-06-15 Thread Jesse Barnes 
Since the offsets have all moved around.

v2: switch IS_DISPLAYREG and IS_VALLEYVIEW checks around since the latter is
cheaper (Daniel)
bail out early in IS_DISPLAYREG if the reg is in the new range (Daniel)

Signed-off-by: Jesse Barnes 
---
 drivers/gpu/drm/i915/i915_drv.c |   87 ++-
 1 file changed, 85 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 238a521..9e772bd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1144,6 +1144,84 @@ MODULE_LICENSE("GPL and additional rights");
 ((reg) != FORCEWAKE)) && \
(!IS_VALLEYVIEW((dev_priv)->dev))
 
+static bool IS_DISPLAYREG(u32 reg)
+{
+   /*
+* This should make it easier to transition modules over to the
+* new register block scheme, since we can do it incrementally.
+*/
+   if (reg >= 0x18)
+   return false;
+
+   if (reg >= RENDER_RING_BASE &&
+   reg < RENDER_RING_BASE + 0xff)
+   return false;
+   if (reg >= GEN6_BSD_RING_BASE &&
+   reg < GEN6_BSD_RING_BASE + 0xff)
+   return false;
+   if (reg >= BLT_RING_BASE &&
+   reg < BLT_RING_BASE + 0xff)
+   return false;
+
+   if (reg == PGTBL_ER)
+   return false;
+
+   if (reg >= IPEIR_I965 &&
+   reg < HWSTAM)
+   return false;
+
+   if (reg == MI_MODE)
+   return false;
+
+   if (reg == GFX_MODE_GEN7)
+   return false;
+
+   if (reg == RENDER_HWS_PGA_GEN7 ||
+   reg == BSD_HWS_PGA_GEN7 ||
+   reg == BLT_HWS_PGA_GEN7)
+   return false;
+
+   if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
+   reg == GEN6_BSD_RNCID)
+   return false;
+
+   if (reg == GEN6_BLITTER_ECOSKPD)
+   return false;
+
+   if (reg >= 0x4000c &&
+   reg <= 0x4002c)
+   return false;
+
+   if (reg >= 0x4f000 &&
+   reg <= 0x4f08f)
+   return false;
+
+   if (reg >= 0x4f100 &&
+   reg <= 0x4f11f)
+   return false;
+
+   if (reg >= VLV_MASTER_IER &&
+   reg <= GEN6_PMIER)
+   return false;
+
+   if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
+   reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
+   return false;
+
+   if (reg >= VLV_IIR_RW &&
+   reg <= VLV_ISR)
+   return false;
+
+   if (reg == FORCEWAKE_VLV ||
+   reg == FORCEWAKE_ACK_VLV)
+   return false;
+
+   if (reg == GEN6_GDRST)
+   return false;
+
+   return true;
+}
+
 #define __i915_read(x, y) \
 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
u##x val = 0; \
@@ -1156,6 +1234,8 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 
reg) { \
if (dev_priv->forcewake_count == 0) \
dev_priv->display.force_wake_put(dev_priv); \
spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
+   } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
+   val = read##y(dev_priv->regs + reg + 0x18); \
} else { \
val = read##y(dev_priv->regs + reg); \
} \
@@ -1175,8 +1255,11 @@ void i915_write##x(struct drm_i915_private *dev_priv, 
u32 reg, u##x val) { \
trace_i915_reg_rw(true, reg, val, sizeof(val)); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
-   } \
-   write##y(val, dev_priv->regs + reg); \
+   } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
+   write##y(val, dev_priv->regs + reg + 0x18); \
+   } else {\
+   write##y(val, dev_priv->regs + reg);\
+   }   \
if (unlikely(__fifo_ret)) { \
gen6_gt_check_fifodbg(dev_priv); \
} \
-- 
1.7.9.5

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[Intel-gfx] [PATCH 07/14] agp/intel: allow cacheable and GDFT PTEs on ValleyView

2012-06-15 Thread Jesse Barnes 
The PTE format is similar to SNB, but we don't support an MLC and don't
need chipset flushing.

Signed-off-by: Jesse Barnes 
---
 drivers/char/agp/intel-gtt.c |   11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 1237e75..c1e2943 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1182,9 +1182,17 @@ static void gen6_write_entry(dma_addr_t addr, unsigned 
int entry,
 static void valleyview_write_entry(dma_addr_t addr, unsigned int entry,
   unsigned int flags)
 {
+   unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
+   unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
u32 pte_flags;
 
-   pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
+   if (type_mask == AGP_USER_MEMORY)
+   pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
+   else {
+   pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
+   if (gfdt)
+   pte_flags |= GEN6_PTE_GFDT;
+   }
 
/* gen6 has bit11-4 for physical addr bit39-32 */
addr |= (addr >> 28) & 0xff0;
@@ -1379,7 +1387,6 @@ static const struct intel_gtt_driver 
valleyview_gtt_driver = {
.write_entry = valleyview_write_entry,
.dma_mask_size = 40,
.check_flags = gen6_check_flags,
-   .chipset_flush = i9xx_chipset_flush,
 };
 
 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
-- 
1.7.9.5

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[Intel-gfx] [PATCH 09/14] drm/i915: enable display messages to GT on ValleyView

2012-06-15 Thread Jesse Barnes 
Signed-off-by: Jesse Barnes 
---
 drivers/gpu/drm/i915/intel_pm.c |7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d0ce2a5..4fa1a78 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3474,6 +3474,13 @@ static void valleyview_init_clock_gating(struct 
drm_device *dev)
 
I915_WRITE(CACHE_MODE_1,
   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
+
+   /*
+* On ValleyView, the GUnit needs to signal the GT
+* when flip and other events complete.  So enable
+* all the GUnit->GT interrupts here
+*/
+   I915_WRITE(VLV_DPFLIPSTAT, 0x3f7f);
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
-- 
1.7.9.5

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[Intel-gfx] [PATCH 08/14] drm/i915: support page flipping on ValleyView

2012-06-15 Thread Jesse Barnes 
And restructure the IRQ handling a little.  We can use pipestat for most
things, and make sure we don't affect pipe events when enabling and
disabling vblank interupts.

Signed-off-by: Jesse Barnes 
---
 drivers/gpu/drm/i915/i915_irq.c |   62 +--
 1 file changed, 27 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0e87664..453ea7c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -513,15 +513,10 @@ static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
unsigned long irqflags;
int pipe;
u32 pipe_stats[I915_MAX_PIPES];
-   u32 vblank_status;
-   int vblank = 0;
bool blc_event;
 
atomic_inc(&dev_priv->irq_received);
 
-   vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
-   PIPE_VBLANK_INTERRUPT_STATUS;
-
while (true) {
iir = I915_READ(VLV_IIR);
gt_iir = I915_READ(GTIIR);
@@ -551,6 +546,16 @@ static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
}
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 
+   for_each_pipe(pipe) {
+   if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
+   drm_handle_vblank(dev, pipe);
+
+   if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
+   intel_prepare_page_flip(dev, pipe);
+   intel_finish_page_flip(dev, pipe);
+   }
+   }
+
/* Consume port.  Then clear IIR or we'll miss events */
if (iir & I915_DISPLAY_PORT_INTERRUPT) {
u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
@@ -565,19 +570,6 @@ static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
I915_READ(PORT_HOTPLUG_STAT);
}
 
-
-   if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
-   drm_handle_vblank(dev, 0);
-   vblank++;
-   intel_finish_page_flip(dev, 0);
-   }
-
-   if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
-   drm_handle_vblank(dev, 1);
-   vblank++;
-   intel_finish_page_flip(dev, 0);
-   }
-
if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
blc_event = true;
 
@@ -1478,23 +1470,20 @@ static int valleyview_enable_vblank(struct drm_device 
*dev, int pipe)
 {
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
unsigned long irqflags;
-   u32 dpfl, imr;
+   u32 imr;
 
if (!i915_pipe_enabled(dev, pipe))
return -EINVAL;
 
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-   dpfl = I915_READ(VLV_DPFLIPSTAT);
imr = I915_READ(VLV_IMR);
-   if (pipe == 0) {
-   dpfl |= PIPEA_VBLANK_INT_EN;
+   if (pipe == 0)
imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
-   } else {
-   dpfl |= PIPEA_VBLANK_INT_EN;
+   else
imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
-   }
-   I915_WRITE(VLV_DPFLIPSTAT, dpfl);
I915_WRITE(VLV_IMR, imr);
+   i915_enable_pipestat(dev_priv, pipe,
+PIPE_START_VBLANK_INTERRUPT_ENABLE);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 
return 0;
@@ -1544,20 +1533,17 @@ static void valleyview_disable_vblank(struct drm_device 
*dev, int pipe)
 {
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
unsigned long irqflags;
-   u32 dpfl, imr;
+   u32 imr;
 
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-   dpfl = I915_READ(VLV_DPFLIPSTAT);
+   i915_disable_pipestat(dev_priv, pipe,
+ PIPE_START_VBLANK_INTERRUPT_ENABLE);
imr = I915_READ(VLV_IMR);
-   if (pipe == 0) {
-   dpfl &= ~PIPEA_VBLANK_INT_EN;
+   if (pipe == 0)
imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
-   } else {
-   dpfl &= ~PIPEB_VBLANK_INT_EN;
+   else
imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
-   }
I915_WRITE(VLV_IMR, imr);
-   I915_WRITE(VLV_DPFLIPSTAT, dpfl);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 }
 
@@ -1894,10 +1880,13 @@ static int valleyview_irq_postinstall(struct drm_device 
*dev)
u32 render_irqs;
u32 enable_mask;
u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
+   u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
u16 msid;
 
enable_mask = I915_DISPLAY_PORT_INTERRUPT;
-   enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
+   enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+

[Intel-gfx] [PATCH 06/14] drm/i915: VLV VGA port only handles on & off, like PCH VGA

2012-06-15 Thread Jesse Barnes 
Signed-off-by: Jesse Barnes 
---
 drivers/gpu/drm/i915/intel_crt.c |3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 1333a65..ac62f24 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -88,6 +88,9 @@ static void gmch_crt_dpms(struct drm_encoder *encoder, int 
mode)
temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
temp &= ~ADPA_DAC_ENABLE;
 
+   if (IS_VALLEYVIEW(dev) && mode != DRM_MODE_DPMS_ON)
+   mode = DRM_MODE_DPMS_OFF;
+
switch (mode) {
case DRM_MODE_DPMS_ON:
temp |= ADPA_DAC_ENABLE;
-- 
1.7.9.5

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[Intel-gfx] [PATCH 10/14] agp/intel: use correct GTT offset on VLV

2012-06-15 Thread Jesse Barnes 
VLV is a gen7 device, but we don't currently handle that in the switch.
So add it and write the PTEs correctly.

Signed-off-by: Jesse Barnes 
---
 drivers/char/agp/intel-gtt.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index c1e2943..5bbc90d 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1252,6 +1252,7 @@ static int i9xx_setup(void)
switch (INTEL_GTT_GEN) {
case 5:
case 6:
+   case 7:
gtt_offset = MB(2);
break;
case 4:
-- 
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[Intel-gfx] [PATCH 14/14] drm/i915: bind driver to ValleyView chipsets

2012-06-15 Thread Jesse Barnes 
With the code in place, we can bind the driver, should make bisect possible.

Signed-off-by: Jesse Barnes 
---
 drivers/gpu/drm/i915/i915_drv.c |3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9e772bd..ae46c3d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -352,6 +352,9 @@ static const struct pci_device_id pciidlist[] = {   
/* aka */
INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
+   INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
+   INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
+   INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
{0, 0, 0}
 };
 
-- 
1.7.9.5

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[Intel-gfx] [PATCH 11/14] drm/i915: don't enable PPGTT on VLV yet

2012-06-15 Thread Jesse Barnes 
Needs some more work and testing.

Signed-off-by: Jesse Barnes 
---
 drivers/gpu/drm/i915/i915_drv.h |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ccabadd..f44ae6f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1074,7 +1074,7 @@ struct drm_i915_file_private {
 #define HAS_LLC(dev)(INTEL_INFO(dev)->has_llc)
 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
 
-#define HAS_ALIASING_PPGTT(dev)(INTEL_INFO(dev)->gen >=6)
+#define HAS_ALIASING_PPGTT(dev)(INTEL_INFO(dev)->gen >=6 && 
!IS_VALLEYVIEW(dev))
 
 #define HAS_OVERLAY(dev)   (INTEL_INFO(dev)->has_overlay)
 #define OVERLAY_NEEDS_PHYSICAL(dev)
(INTEL_INFO(dev)->overlay_needs_physical)
-- 
1.7.9.5

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[Intel-gfx] [PATCH 13/14] drm/i915: fix initial IRQ masking on VLV

2012-06-15 Thread Jesse Barnes 
We can leave vblank interrupts masked but enabled so we're not dependent
on the first client to toggle the disable timer.  We can also mask all
render based interrupts, since the ring code will handle unmasking them
for us.

Signed-off-by: Jesse Barnes 
---
 drivers/gpu/drm/i915/i915_irq.c |   12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 36732f7..5c6c5e9 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1889,7 +1889,13 @@ static int valleyview_irq_postinstall(struct drm_device 
*dev)
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
 
-   dev_priv->irq_mask = ~enable_mask;
+   /*
+*Leave vblank interrupts masked initially.  enable/disable will
+* toggle them based on usage.
+*/
+   dev_priv->irq_mask = (~enable_mask) |
+   I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
+   I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
 
dev_priv->pipestat[0] = 0;
dev_priv->pipestat[1] = 0;
@@ -1925,11 +1931,11 @@ static int valleyview_irq_postinstall(struct drm_device 
*dev)
GT_SYNC_STATUS |
GT_USER_INTERRUPT;
 
-   dev_priv->gt_irq_mask = ~render_irqs;
+   dev_priv->gt_irq_mask = ~0;
 
I915_WRITE(GTIIR, I915_READ(GTIIR));
I915_WRITE(GTIIR, I915_READ(GTIIR));
-   I915_WRITE(GTIMR, 0);
+   I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
I915_WRITE(GTIER, render_irqs);
POSTING_READ(GTIER);
 
-- 
1.7.9.5

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[Intel-gfx] [PATCH 12/14] drm/i915: don't account for shared interrupts on VLV

2012-06-15 Thread Jesse Barnes 
Only count interrupts we find came from the GPU.

Signed-off-by: Jesse Barnes 
---
 drivers/gpu/drm/i915/i915_irq.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 453ea7c..36732f7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -515,8 +515,6 @@ static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
u32 pipe_stats[I915_MAX_PIPES];
bool blc_event;
 
-   atomic_inc(&dev_priv->irq_received);
-
while (true) {
iir = I915_READ(VLV_IIR);
gt_iir = I915_READ(GTIIR);
@@ -525,6 +523,8 @@ static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
if (gt_iir == 0 && pm_iir == 0 && iir == 0)
goto out;
 
+   atomic_inc(&dev_priv->irq_received);
+
ret = IRQ_HANDLED;
 
snb_gt_irq_handler(dev, dev_priv, gt_iir);
-- 
1.7.9.5

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