[gem5-users] How to obtain real-time cache information in FS simulation
Hello, I plan to enable my program to read hardware information from the underlying layer during full simulation, such as the hit rate of L1 cache, and then schedule based on this information. However, I am not sure how to implement it. My current idea is to add new instructions to Gem5 and implement new system calls, but this step seems particularly complex. Can you provide me with some relevant guidance or similar examples? Of course, if there is a better implementation method, please let me know. Thank you very much___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Transfer cache information to misc register in arm
I am a beginner who has just started to learn Gem5. Recently, I attempted to use the msr instruction to read out the currently allocated entries in L2cache (variable "int allocated" in gem5 stable \ src \ mem \ cache \ queue.hh). I have added a new system register for this purpose (by modifying gem5 stable \ src \ arch \ arm \ regs \ misc.hh and misc.cc), and the mrs instruction can correctly read the value of this register. But what confuses me is how to pass this variable to the MiscRegLUTEntry, or in other words, there is an array called RegVal miscRegs [NUM-MISCREGS] in "gem 5 stable \ src \ arch \ arm \ isa. hh" (which I think is used to store different misc register values). What should I do to pass the allocated variable in src \ mem \ cache \ queue.hh to miscRegs [NUM-MISCREGS] in src \ arch \ arm \ isa. hh?Thank you very much for your help！___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] ARM Full simulation using O3CPU and Kernel panic in simulated kernel
Hi,team.
Recently, I have been trying to conduct a full simulation experiment on ARM and
running some benchmarks on it. Currently, I have encountered two issues.
1.First, I will use the following command line to full simulate
./build/ARM/gem5.opt configs/example/arm/fs_bigLITTLE.py --cache
--bootloader=/home/abc/gem5/fs_images/binaries/boot.arm64
--kernel=/home/abc/gem5/fs_images/binaries/mylinux/vmlinux
--disk=/home/abc/gem5/fs_images/disks/ubuntu-18.04-arm64-docker.img
--cpu-type=exynos --big-cpus=4 --little-cpus=0 --bootscript=bootscript.rcS
And use ./util/term/m5term 3456 on Terminal 2
I can successfully start the full simulation, but I need to make modifications
in gem5-stable\configs\example\arm\fs_bigLITTLE.py lines 93 and 104,such
asdevices.CpuCluster->devices.ArmCpuCluster.I am using gem5 Version 23.0.1.0.
Then I ran my script file on Terminal 2
script:
#!/bin/bash
echo "" > tmpout.txt
for cpu in `seq 0 3`; do
if [ $cpu -ne 0 ]; then
bandwidth -m 4096 -c $cpu -t 100 -a read &
fi
latency -m 96 -c 0 -i 1:
output=`grep average tmpout.txt | awk '{ print $2 }'`
echo $output
done
But after the script finished running, I tried to execute kill
bandwidth,terminal 1 told me:
src/kern/linux/events.cc:64: warn: Kernel panic in simulated kernel
src/kern/linux/events.cc:67: info: Dumping kernel dmesg buffer to
system.workload.dmesg...
src/kern/linux/helpers.cc:113: warn: Malformed dmesg entry:
src/kern/linux/helpers.cc:114: warn: Max length: 14684
src/kern/linux/helpers.cc:115: warn: de.len: 0
src/kern/linux/helpers.cc:116: warn: de.text_len: 0
Exiting @ tick 107002930332000 because Kernel panic in simulated kernel
So my first question is why killing the backend program can cause kernel panic,
and how can I avoid it.
2.I can successfully start full simulation using the following command line
./build/ARM/gem5.opt configs/deprecated/example/fs.py
--bootloader=/home/abc/gem5/fs_images/binaries/boot.arm64
--kernel=/home/abc/gem5/fs_images/binaries/mylinux/vmlinux
--disk=/home/abc/gem5/fs_images/disks/ubuntu-18.04-arm64-docker.img
--num-cpus=4 --caches --l2cache --mem-size=4096MB --l1i_size=32kB
--l1d_size=32kB --l2_size=2MB --l1d_assoc=2 --l2_assoc=16
--cpu-type=TimingSimpleCPU
But using--cpu-type=ArmO3CPU,I have encountered the following information:
1256535500: system.terminal: attach terminal 0 src/mem/cache/mshr.cc:431:
panic: panic condition (pkt->needsWritable() != pkt->isInvalidate()) &&
!pkt->req->isCacheMaintenance() occurred: system.cpu1.dcache.mshr_queue.entry
got snoop WriteReq [80a85804:80a85807] UC where needsWritable, does not match
isInvalidate Memory Usage: 4858020 KBytes Program aborted at tick 88940389500
Thank you in advance.
___
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[gem5-users] About Running Parsec and SPEC2017 Benchmarks in Gem5 ARM FS Simulation
Hello, team! Recently, I have been trying to use the Parsec and spec2017 benchmarks in the tutorial in Gem5 ARM. However, I have seen in the tutorial that building images with specific benchmarks involves trying out specific. json configuration files. Due to my unfamiliarity with these configuration files. So I plan to use other methods to achieve this goal. 1. For the Parsec benchmark, I have seen someone try to cross compile on the x86 platform, and then mount the corresponding image to directly CP the generated executable file into the image. I have tried this method, specifically by https://github.com/arm-university/arm-gem5-rsk Provide. However, some benchmarks may not run successfully. 2. So I plan to try using the method of downloading new applications from the image later, directly moving the Parsec resources into my image, and then using/usr/sbin/chroot mnt/bin/bash to mount the image to the current root directory. I plan to compile it directly in the image because I believe there is already a compilation tool for gcc aarch64 in the disk image, so I don't need to install gcc aarch64 separately, which is more convenient and easier for me to understand. And later on, when conducting the spec2017 benchmark experiment, I also plan to use this method to directly copy CPU2017.ios into the image and compile it (which may involve scaling and other operations) I haven't tried the second method of the above two methods yet, and I'm not sure if it will be successful at the moment. The purpose of this email is to inquire about the team's assessment of the feasibility of the second method and whether there is a better way for me to complete these benchmark tests in the fs simulation of Gem5 ARM. Thank you for your help!___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
