Re: [gem5-users] Latency_input ARM FS
Thank you Ali. Regards, Ali C. 2012/8/25 Ali Saidi > ** > > Hi Ali, > > > > Yes, the hit latency is used for both. I'm going to post a patch soon that > provides a the ability to confider a different latency for the response > path. > > > > Thanks, > > Ali > > > > On 24.08.2012 04:47, Ali chaker wrote: > > Hi, > > > > I'm running bbench in gem5 with this configuration: > > > > Dcache latency: 2.5 ns > > L2 latency: 15.8 ns > > Mem Latency: 100 ns > > > > and I've the following statistics: > > > > *system.l2.overall_avg_mshr_miss_latency::cpu.data 116713.648032* > > *system.l2.overall_avg_miss_latency::cpu.data 136045.358298* > > * > * > > It seems like hit latency is used in access and response. So * > avg_miss_latency*= 15.8**2*+2.5+2(buses latency) +100=136.1? Is it right? > > > > > > Thanks in advance > > > > Regards, > > Ali Chaker > > > > > > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Cycles Statistics ARM FS
Hi, I'm running bbench in gem5 with 2 cores and I've the following statistics: *system.cpu1.numCycles* 5735434319 *system.cpu1.idleCycles* 1841336037 *system.cpu1.quiesceCycles*5027490762 Why the idleCycles + quiesceCycles > numCycles ? Regards, Ali Chaker ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] FS + SMT still not possible?
Hi all, Some time ago, I found out that it is not possible to simulate a core supporting SMT in FS mode using gem5 (m5 at that time). Is this still the case in the current version? If so, is this something that is taken care of? And if not, can someone give a clue how to enable SMT in FS mode, and an estimate how much work/time/experience this requires? Alternatively, has someone been able to run the PARSEC benchmarks in SE mode? If so, how is OS scheduling modeled? Is there also something similar to 'quiesce' in FS mode (i.e., scheduling out threads)? Thanks in advance, Stijn -- dr. ir. Stijn Eyerman Ghent University ELIS department Sint-Pietersnieuwstraat 41 9000 Gent Belgium +32 9 264 3456 http://www.elis.ugent.be/~seyerman ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Implementation of producer consumer problem
On Mon, 27 Aug 2012, vishal rawtiya wrote: Hello! I am sorry for spamming similar mail at both lists. Of course I know about the threads but here at http://gem5.org/Multiprogrammed_workloads I found that SE mode has no thread scheduling. So will it be okay to use pthreads in SE mode to create my application. I can not use FS mode because it invloves Operating System. You can use pthreads in SE mode, but you would need to link your application with m5threads library. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] segmentation fault when creating checkpoints for X86_FS+ruby
Hi Nilay, I used "$scons build/X86/gem5.fast RUBY=True PROTOCOL=MOESI_hammer " to compile gem5 and ran it with "$build/X86/m5.debug -d ruby-output configs/example/ruby_fs.py --kernel=x86_64-vmlinux-2.6.22.9.smp --script=configs/boot/mcf.rcS --cpu-type=detailed --ruby --checkpoint-dir=checkpoint-dir --take-checkpoints 1000,10" I noticed that when I set cpu-type as detailed, it incurred segmentation fault. But if it was timing, it looked fine. But I am still testing it. Can you please tell me if x86+ruby supports detailed cpu-type? I will let you know if I make any progress. Thanks, Yingying On Sat, Aug 25, 2012 at 6:29 PM, Nilay Vaish wrote: > On Fri, 24 Aug 2012, Cookie wrote: > > Hi Nilay, >> >> Thank you for your reply. I did debug it with gdb and it reported the >> assertion "assert(**isDeadlockEventScheduled() == false)" in >> mem/ruby/system/RubyPort.cc was failed. I've no idea how to fix it but >> just >> commented this statement and compiled and ran again. It reported >> segmentation fault again because "build/X86/python/swig/**pyevent.cc:84: >> void >> cleanupCountedDrain(Event*): Assertion `event->getCount() == 0' failed." >> > > I would not be able to debug unless I can reproduce the situation. Just > reading the code did made feel that something is incorrect. > > > >> I also tried to restore the checkpoints (they seemed to be created, at >> least there were checkpoint files in the directory) using the following >> command: build/X86/m5.debug -d ruby-output configs/example/ruby_fs.py >> --kernel=x86_64-vmlinux-2.6.**22.9.smp --script=configs/boot/mcf.rcS >> --cpu-type=detailed --caches --ruby -r 4. >> But it failed and reported as: >> -- >> File "/home/ytian/Documents/Gem5/**configs/common/Simulation.py", line >> 70, >> in setCPUClass >>class TmpClass(AtomicSimpleCPU): pass >> NameError: global name 'AtomicSimpleCPU' is not defined >> >> So I removed the option "--cpu-type" and used >> "--restore-with-cpu=detailed" >> to restore the checkpoint again. It reported as: >> --- >> File "/home/ytian/Documents/Gem5/**configs/common/Simulation.py", line >> 45, >> in setCPUClass >>class TmpClass(TimingSimpleCPU): pass >> NameError: global name 'TimingSimpleCPU' is not defined >> >> >> I think both of the objects are defined. So I wonder if there is something >> wrong with the steps/options which I used to compile/run the gem5 since I >> didn't make any changes to the source code. Could you please help me fix >> this problem? Thank you for your help. >> >> >> > What command and configuration file did you use for compilation? > > -- > Nilay > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Question about running the Gem5
Hi, This is my first time to use the GEM5. I want to run the Aplash-2 Benchmarks on gem5 on Ubuntu in full system mode. I downloaded files from gem5 website and installed on Ubuntu(12.04 Precise). i)Gem5-stable.tar.bz2 ii) M5_system_2.0b3.tar.bz2 Also downloaded and installed required software shown as below: i) Python: 2.4+, it may need to install python-dev ii) Scons: 0.98.1+, you can update it with apt-get (2.0.1) iii) SWIG: 1.3.31+, you can update it with apt-get (1.3.40) To build gem5, I used below command: Ø scons build/ALPHA_FS/gem5.opt (or) Ø scons build/ALPHA_SE/m5.opt but both didnt work. There was an error message that says that cannot find variables files /pgks/gem5/gem5-stable/build/variables/ALPHA_SE or default file(s) / pgks/gem5/gem5-stable/build/variables/ALPHA_SE I was able to build gem5 with ALPHA. (> scons build/ALPHA/gem5.opt) However, if I want to run ALPHA_FS, what are the things I have to do to make it work? What is different between ALPAH and ALPHA_FS ? Does the ALPHA includes both FS and SE mode? Thanks, GL ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] FS + SMT still not possible?
On Mon, 27 Aug 2012, Stijn Eyerman wrote: Hi all, Some time ago, I found out that it is not possible to simulate a core supporting SMT in FS mode using gem5 (m5 at that time). Is this still the case in the current version? If so, is this something that is taken care of? This patch from Andrea Pellegrini supposedly fixes some problems with SMT for x86 architecture, but it is yet to be checked in. http://reviews.gem5.org/r/1281/ Certainly the mainline does not work correctly in SMT mode, and as far as I know, no one is working on it. And if not, can someone give a clue how to enable SMT in FS mode, and an estimate how much work/time/experience this requires? It might be that the above patch fixes everything that needs to be. I suggest that you try out the patch and then raise any issues on the mailing list. Alternatively, has someone been able to run the PARSEC benchmarks in SE mode? If so, how is OS scheduling modeled? Is there also something similar to 'quiesce' in FS mode (i.e., scheduling out threads)? I think there are many users who are running PARSEC benchmarks in SE mode. There is no scheduling in SE mode. My understanding is that you need at least as many hardware contexts as the number of threads the application creates. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] 答复: 答复: ruby request latency and L1 miss rate
Hi Nilay, Thanks for the reply. I double checked ruby.stats file and there are statistics about number of L1, L2 misses. But I went through ruby.stats several times and did not find any number about cache accesses number or cache hit number, so I still cannot get miss rate of the cache. Could you give me some clues? Thanks, Xi -邮件原件- 发件人: Nilay Vaish [mailto:ni...@cs.wisc.edu] 发送时间: Saturday, August 25, 2012 6:19 PM 收件人: Xi Chen 抄送: gem5-users@gem5.org 主题: Re: 答复: [gem5-users] ruby request latency and L1 miss rate On Fri, 24 Aug 2012, Xi Chen wrote: > Hi Nilay, > > Thanks for the explanation. I got the network latency. But I still have > problem of getting L1 miss rate of each core. Could you give me some clues? > Checkout ruby.stats file. -- Nilay ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Are there some benchmarks that can run on gem5 with the X86 ISA in full system mode?
hi all, It seems all the benchmarks provided on the webpage run on gem5 with the ALPHA ISA. Are there some benchmarks targeting x86-linux? We have tried to compile and run SPLASH2 on gem5 with X86 ISA in full system mode, but some benchmarks do not terminate correctly. I downloaded the SPLASH2 for Alpha from the download page of gem5 and found it is patched for Alpha ISA. What should we do if we want to run SPLASH2 on gem5 with x86? Does any one have experience with SPLASH2 for X86-linux? Thanks a lot! Weixing ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Running Android on Gem5 - Creating custom Android image file
Hi, I am trying to run Android on Gem5 for my project and I needed help in getting the system to run. I am running the gem5-stable release and am using the ARM architecture. I have set M5_PATH to point to the gem5-stable/system directory Here are the different approaches I tried: 1. I am trying to create a custom Android image file by following the instructions given on the website. I downloaded the Android source code and patched it with Arm specific files as given in http://www.linux-arm.org/LinuxKernel/LinuxAndroidPlatform for kernel version 2.6.35 I successfully compiled the patched Android ICS source code and created an image file using the gem5 image creation utility and transfered the Android file system on it. I am using the pre-built kernel image given on the site. When I try to run the simulation I get kernel panic message and the system does not boot: VFS: Mounted root (ext2 filesystem) on device 8:1. [2.254005] VFS: Mounted root (ext2 filesystem) on device 8:1. <6>Freeing init memory: 148K [2.254019] Freeing init memory: 148K /bin/sh: earlyprintk: No such file or directory <0>Kernel panic - not syncing: Attempted to kill init! [2.268655] Kernel panic - not syncing: Attempted to kill init! [] (unwind_backtrace+0x0/0xe4) from [] (panic+0x50/0xd0) [2.268666] [] (unwind_backtrace+0x0/0xe4) from [] (panic+0x50/0xd0) [] (panic+0x50/0xd0) from [] (do_exit+0x68/0x620) [2.268679] [] (panic+0x50/0xd0) from [] (do_exit+0x68/0x620) [] (do_exit+0x68/0x620) from [] (do_group_exit+0xa4/0xd4) [2.268691] [] (do_exit+0x68/0x620) from [] (do_group_exit+0xa4/0xd4) [] (do_group_exit+0xa4/0xd4) from [] (sys_exit_group+0x10/0x18) [2.268704] [] (do_group_exit+0xa4/0xd4) from [] (sys_exit_group+0x10/0x18) [] (sys_exit_group+0x10/0x18) from [] (ret_fast_syscall+0x0/0x30) [2.268718] [] (sys_exit_group+0x10/0x18) from [] (ret_fast_syscall+0x0/0x30) Am I missing something in the build process? I compared my init.rc file with the one from the clean ICS image file and there were no differences. 2. I tried to run the simulation using the pre-built images and I was able to boot the Gingerbread bbench, gingerbread clean and Ics bbench images using the pre-compiled kernel image. This does not solve the purpose as I want to use my own Android image file. 3. I downloaded and compiled the armdroid kernel source code and tried to run the simulation. After compilation, I get the file "uImage" in arch/arm/boot folder. I renamed uImage to vmlinux.arm.custom and used it in the simulation. The simulation exits immediately with the message "Could not load kernel file". I have placed the kernel image in gem5-stable/system/binaries. Am I using the correct kernel image file? It would be really helpful if someone could point me in the correct direction so that I can get the system to run. Kindly let me know in case any additional information is required. Thanks and Regards, Abhinav Kannan ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Running Android on Gem5 - Creating custom Android image file
<0>Kernel panic - not syncing: Attempted to kill init! [2.268655] Kernel panic - not syncing: Attempted to kill init! That is you problem. You need to specify init in your boot flags. In configs/common/FSConfig.py it checks if the image name contains "android". If so it adds init to the boot flags: boot_flags += " init/init " Try adding "android" as part of the file name. Or just add " init/init " to be part of the boot flags always. -Tony On Mon, Aug 27, 2012 at 7:43 PM, Abhinav Kannan < abhinavkannan2...@u.northwestern.edu> wrote: > Hi, > > I am trying to run Android on Gem5 for my project and I needed help in > getting the system to run. > > I am running the gem5-stable release and am using the ARM architecture. > I have set M5_PATH to point to the gem5-stable/system directory > > Here are the different approaches I tried: > > 1. I am trying to create a custom Android image file by following the > instructions given on the website. > > I downloaded the Android source code and patched it with Arm specific > files as given in > http://www.linux-arm.org/LinuxKernel/LinuxAndroidPlatform > for kernel version 2.6.35 > > I successfully compiled the patched Android ICS source code and created an > image file using the gem5 image creation utility and transfered the Android > file system on it. I am using the pre-built kernel image given on the site. > > When I try to run the simulation I get kernel panic message and the system > does not boot: > > VFS: Mounted root (ext2 filesystem) on device 8:1. > [2.254005] VFS: Mounted root (ext2 filesystem) on device 8:1. > <6>Freeing init memory: 148K > [2.254019] Freeing init memory: 148K > /bin/sh: earlyprintk: No such file or directory > <0>Kernel panic - not syncing: Attempted to kill init! > [2.268655] Kernel panic - not syncing: Attempted to kill init! > [] (unwind_backtrace+0x0/0xe4) from [] > (panic+0x50/0xd0) > [2.268666] [] (unwind_backtrace+0x0/0xe4) from [] > (panic+0x50/0xd0) > [] (panic+0x50/0xd0) from [] (do_exit+0x68/0x620) > [2.268679] [] (panic+0x50/0xd0) from [] > (do_exit+0x68/0x620) > [] (do_exit+0x68/0x620) from [] > (do_group_exit+0xa4/0xd4) > [2.268691] [] (do_exit+0x68/0x620) from [] > (do_group_exit+0xa4/0xd4) > [] (do_group_exit+0xa4/0xd4) from [] > (sys_exit_group+0x10/0x18) > [2.268704] [] (do_group_exit+0xa4/0xd4) from [] > (sys_exit_group+0x10/0x18) > [] (sys_exit_group+0x10/0x18) from [] > (ret_fast_syscall+0x0/0x30) > [2.268718] [] (sys_exit_group+0x10/0x18) from [] > (ret_fast_syscall+0x0/0x30) > > Am I missing something in the build process? I compared my init.rc file > with the one from the clean ICS image file and there were no differences. > > 2. I tried to run the simulation using the pre-built images and I was able > to boot the Gingerbread bbench, gingerbread clean and Ics bbench images > using the pre-compiled kernel image. > > This does not solve the purpose as I want to use my own Android image file. > > 3. I downloaded and compiled the armdroid kernel source code and tried to > run the simulation. After compilation, I get the file "uImage" in > arch/arm/boot folder. I renamed uImage to vmlinux.arm.custom and used it in > the simulation. The simulation exits immediately with the message "Could > not load kernel file". I have placed the kernel image in > gem5-stable/system/binaries. Am I using the correct kernel image file? > > It would be really helpful if someone could point me in the correct > direction so that I can get the system to run. > Kindly let me know in case any additional information is required. > > Thanks and Regards, > Abhinav Kannan > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] How to define Memory specification in Gem5?
Is there a way to specify a memory subsystem in Gem5? I plan to specify: - # of channel, #Dimm/Channel, #of rank/Dimm, #of bank/Rank - Mega transfers /second, - Precharge time, row access time, column access time Thanks. Vic___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Set total order among multiple logic buses
Hi Tushar, I wonder if all the nodes(controllers) need to have a router before them. This is what I have seen for all the topologies created in GEM5. I have tried topology like the one I attach here. If I run it with ruby_network_tester for simple network with Hammer protocol for 10 sim-cycles. I will have deadlock. But if I run the same for Pt2Pt in GEM5 for example, then there is no deadlock. Do you think because controllers do not know how to handle multiple input links well? or there are some other reasons. Please help me figure it out. Thank you very much! Best, Jinzhu On Thu, Aug 23, 2012 at 10:07 PM, gem5 gem5 wrote: > Thank you very much, Tushar:) > > Best, > > Jinzhu > > > On Wed, Aug 22, 2012 at 12:24 AM, Tushar Krishna wrote: > >> Hi Jinzhu, >> Do the orange routers guarantee that the message is delivered out of all >> output links simultaneously? >> I think something like the following could be the problem: >> Suppose Core B and Core C are sharing a line. >> Core A does a broadcast for GETX. At the orange routers, suppose it >> reaches Core B and Core C, but not Core D since that output link is busy >> and/or no free buffer at Core D. >> Now Core B looks at this message and invalidates its copy. Now it sends >> out a GETX. >> Suppose Core D receives this GETX (via Core B's orange router) before the >> older GETX from Core A (still stuck in Core A's router for some reason). >> This will violate ordering (because other cores saw Core A's broadcast >> before Core B's). >> >> (1) since the orange routers are modeling a "bus", any message being >> broadcast should wait till ALL output links are free and then be sent out >> of all output links simultaneously. >> (2) after that the blue routers should guarantee a FIFO ordering (to >> ensure that messages received from two different "buses" don't get >> reordered) when delivering messages to the core. >> >> I *think* (though you should check) that (2) is guaranteed automatically >> in the code since the input queues are implemented as MessageBuffers which >> order messages according to time of receipt, but I know (1) is not >> guaranteed by default in the simple router. >> See if that solves your issue. >> While a stronger condition of latency between two nodes always being the >> same will definitely solve your problem, I think a weaker condition of >> ensuring that ALL the blue routers receive messages from different buses in >> the same order should be the constraint. >> >> - Tushar >> >> >> On Aug 21, 2012, at 5:30 PM, gem5 gem5 wrote: >> >> Tushar, >> >> All the links used in my topology are single directional. The connection >> is as the attached image. It's Single writer multiple reader and I think >> this topology should be able to guarantee that certain messages only go on >> certain buses. >> >> I am thinking the problem is that the total order is achieved only when >> the latency between any two nodes is always the same, but the throttle link >> creates lots of delays(some messages got sent much later) so latency is not >> always the same.And maybe I should also create one MessageBuffer/queue >> for every bus in the controller instead of just one MessageBuffer for one >> vnet. Then I can read messages from all the messagebuffer round robin. Is >> the simple network modeled cycle accurate? Any suggestions? Thank you very >> much! >> >> Best, >> Jinzhu >> >> On Mon, Aug 20, 2012 at 1:14 AM, Tushar Krishna wrote: >> >>> Hi Jinzhu, >>> While it is true that the a garnet router is more accurate than the >>> PerfectSwitch as it models contention in a detailed manner, I don't think >>> your problem has anything to do with that. >>> I think you should track messages through each router and see why/where >>> 2 messages from the same source get re-ordered. >>> >>> I am wondering if the problem could with the topology itself… >>> Are you modeling multiple buses as multiple links between routers? >>> How does a router guarantee that certain messages only go on certain >>> links (buses), and certain others go on other links? By default both >>> simple/garnet networks try to route using the shortest path, and here all >>> buses will be on the shortest path. >>> >>> - Tushar >>> >>> >>> On Aug 19, 2012, at 11:41 PM, gem5 gem5 wrote: >>> >>> Hi Tushar, >>> >>> I have tried to modify the PerfectSwitch to schedule messages according >>> to a fixed round robin order. And then I also did the same to the throttle >>> link by changing the wakeup order. However, I still cannot see the total >>> order in multiple logic buses. I wonder if that is because the >>> implementation of PerfectSwtich does not reflect the timing characteristic >>> of a real router. It just simply copies everything from the inport to the >>> outport. Although I scheduled according to a predefined order, but actually >>> it's still done right away. Maybe a more detailed model such as Garnet >>> router can solve the problem? I wonder if that's the issue or there is >>> somet
