Re: [PING^1][PATCH] rs6000: Change bitwise xor to inequality operator [PR106907]
Ping! please review. Thanks & Regards Jeevitha On 16/06/23 9:55 am, Peter Bergner wrote: > On 6/12/23 6:18 AM, P Jeevitha wrote: >> Bitwise xor performed on bool >> is similar to checking inequality. So changed to inequality >> operator (!=) instead of bitwise xor (^). > [snip' >> - if (swapped ^ !BYTES_BIG_ENDIAN > [snip] >> + if (swapped != !BYTES_BIG_ENDIAN > > I know Andreas mentioned using "swapped != !BYTES_BIG_ENDIAN" in > the bugzilla, but that's the same as "swapped == BYTES_BIG_ENDIAN", > and it doesn't contain a double-negative and seems a little clearer. > > It's up to Segher though...and if we go with this, then the ChangeLog > entry needs to be updated slightly since we're no longer testing for > inequality. > > Peter >
[PATCH v2] rs6000: Change bitwise xor to an equality operator [PR106907]
Hi All, The following patch has been bootstrapped and regtested on powerpc64le-linux. PR106907 has a few warnings spotted from cppcheck. These warnings are related to the need of precedence clarification. Instead of using xor, it has been changed to equality check, which achieves the same result. Additionally, comment indentation has been fixed. 2023-10-11 Jeevitha Palanisamy gcc/ PR target/106907 * config/rs6000/rs6000.cc (altivec_expand_vec_perm_const): Change bitwise xor to an equality and fix comment indentation. diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 2828f01413c..00191f8656b 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -23624,10 +23624,10 @@ altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1, && GET_MODE (XEXP (op0, 0)) != V8HImode))) continue; - /* For little-endian, the two input operands must be swapped - (or swapped back) to ensure proper right-to-left numbering - from 0 to 2N-1. */ - if (swapped ^ !BYTES_BIG_ENDIAN + /* For little-endian, the two input operands must be swapped +(or swapped back) to ensure proper right-to-left numbering +from 0 to 2N-1. */ + if (swapped == BYTES_BIG_ENDIAN && icode != CODE_FOR_vsx_xxpermdi_v16qi) std::swap (op0, op1); if (imode != V16QImode)
[PATCH V3] rs6000: Don't ICE when compiling the __builtin_vsx_splat_2di built-in [PR113950]
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
When we expand the __builtin_vsx_splat_2di function, we were allowing immediate
value for second operand which causes an unrecognizable insn ICE. Even though
the immediate value was forced into a register, it wasn't correctly assigned
to the second operand. So corrected the assignment of op1 to operands[1].
2024-02-29 Jeevitha Palanisamy
gcc/
PR target/113950
* config/rs6000/vsx.md (vsx_splat_): Corrected assignment to
operand1.
gcc/testsuite/
PR target/113950
* gcc.target/powerpc/pr113950.c: New testcase.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 6111cc90eb7..f135fa079bd 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4666,8 +4666,8 @@
rtx op1 = operands[1];
if (MEM_P (op1))
operands[1] = rs6000_force_indexed_or_indirect_mem (op1);
- else if (!REG_P (op1))
-op1 = force_reg (mode, op1);
+ else
+operands[1] = force_reg (mode, op1);
})
(define_insn "vsx_splat__reg"
diff --git a/gcc/testsuite/gcc.target/powerpc/pr113950.c
b/gcc/testsuite/gcc.target/powerpc/pr113950.c
new file mode 100644
index 000..64566a580d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr113950.c
@@ -0,0 +1,24 @@
+/* PR target/113950 */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O1 -mvsx" } */
+
+/* Verify we do not ICE on the following. */
+
+void abort (void);
+
+int main ()
+{
+ int i;
+ vector signed long long vsll_result, vsll_expected_result;
+ signed long long sll_arg1;
+
+ sll_arg1 = 300;
+ vsll_expected_result = (vector signed long long) {300, 300};
+ vsll_result = __builtin_vsx_splat_2di (sll_arg1);
+
+ for (i = 0; i < 2; i++)
+if (vsll_result[i] != vsll_expected_result[i])
+ abort();
+
+ return 0;
+}
[PING^1][PATCH] rs6000: load high and low part of 128bit vector independently [PR110040]
Ping!
please review.
Thanks & Regards
Jeevitha
On 26/02/24 11:13 am, jeevitha wrote:
> Hi All,
>
> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>
> PR110040 exposes an issue concerning moves from vector registers to GPRs.
> There are two moves, one for upper 64 bits and the other for the lower
> 64 bits. In the problematic test case, we are only interested in storing
> the lower 64 bits. However, the instruction for copying the upper 64 bits
> is still emitted and is dead code. This patch adds a splitter that splits
> apart the two move instructions so that DCE can remove the dead code after
> splitting.
>
> 2024-02-26 Jeevitha Palanisamy
>
> gcc/
> PR target/110040
> * config/rs6000/vsx.md (split pattern for V1TI to DI move): Defined.
>
> gcc/testsuite/
> PR target/110040
> * gcc.target/powerpc/pr110040-1.c: New testcase.
> * gcc.target/powerpc/pr110040-2.c: New testcase.
>
>
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index 6111cc90eb7..78457f8fb14 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -6706,3 +6706,19 @@
>"vmsumcud %0,%1,%2,%3"
>[(set_attr "type" "veccomplex")]
> )
> +
> +(define_split
> + [(set (match_operand:V1TI 0 "int_reg_operand")
> + (match_operand:V1TI 1 "vsx_register_operand"))]
> + "reload_completed
> + && TARGET_DIRECT_MOVE_64BIT"
> + [(pc)]
> +{
> + rtx op0 = gen_rtx_REG (DImode, REGNO (operands[0]));
> + rtx op1 = gen_rtx_REG (V2DImode, REGNO (operands[1]));
> + rtx op2 = gen_rtx_REG (DImode, REGNO (operands[0]) + 1);
> + rtx op3 = gen_rtx_REG (V2DImode, REGNO (operands[1]));
> + emit_insn (gen_vsx_extract_v2di (op0, op1, GEN_INT (0)));
> + emit_insn (gen_vsx_extract_v2di (op2, op3, GEN_INT (1)));
> + DONE;
> +})
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
> b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
> new file mode 100644
> index 000..fb3bd254636
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
> @@ -0,0 +1,14 @@
> +/* PR target/110040 */
> +/* { dg-do compile } */
> +/* { dg-require-effective-target powerpc_p9vector_ok } */
> +/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
> +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
> +
> +#include
> +
> +void
> +foo (signed long *dst, vector signed __int128 src)
> +{
> + *dst = (signed long) src[0];
> +}
> +
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
> b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
> new file mode 100644
> index 000..f3aa22be4e8
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
> @@ -0,0 +1,13 @@
> +/* PR target/110040 */
> +/* { dg-do compile } */
> +/* { dg-require-effective-target power10_ok } */
> +/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
> +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
> +
> +#include
> +
> +void
> +foo (signed int *dst, vector signed __int128 src)
> +{
> + __builtin_vec_xst_trunc (src, 0, dst);
> +}
>
>
[PING^1][PATCH] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]
Ping!
please review.
Thanks & Regards
Jeevitha
On 23/02/24 3:04 pm, jeevitha wrote:
> Hi All,
>
> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>
> PTImode attribute assists in generating even/odd register pairs on 128 bits.
> When the user specifies PTImode as an attribute, it breaks because there is no
> internal type to handle this mode . We have created a tree node with dummy
> type
> to handle PTImode. We are not documenting this dummy type since users are not
> allowed to use this type externally.
>
> 2024-02-23 Jeevitha Palanisamy
>
> gcc/
> PR target/106895
> * config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add fields
> to hold PTImode type.
> * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Add node
> for PTImode type.
>
> gcc/testsuite/
> PR target/106895
> * gcc.target/powerpc/pr106895.c: New testcase.
>
> diff --git a/gcc/config/rs6000/rs6000-builtin.cc
> b/gcc/config/rs6000/rs6000-builtin.cc
> index 6698274031b..f553c72779e 100644
> --- a/gcc/config/rs6000/rs6000-builtin.cc
> +++ b/gcc/config/rs6000/rs6000-builtin.cc
> @@ -756,6 +756,15 @@ rs6000_init_builtins (void)
>else
> ieee128_float_type_node = NULL_TREE;
>
> + /* PTImode to get even/odd register pairs. */
> + intPTI_type_internal_node = make_node(INTEGER_TYPE);
> + TYPE_PRECISION (intPTI_type_internal_node) = GET_MODE_BITSIZE (PTImode);
> + layout_type (intPTI_type_internal_node);
> + SET_TYPE_MODE (intPTI_type_internal_node, PTImode);
> + t = build_qualified_type (intPTI_type_internal_node, TYPE_QUAL_CONST);
> + lang_hooks.types.register_builtin_type (intPTI_type_internal_node,
> + "__dummypti");
> +
>/* Vector pair and vector quad support. */
>vector_pair_type_node = make_node (OPAQUE_TYPE);
>SET_TYPE_MODE (vector_pair_type_node, OOmode);
> diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
> index 2291fe8d3a3..77bb937a28b 100644
> --- a/gcc/config/rs6000/rs6000.h
> +++ b/gcc/config/rs6000/rs6000.h
> @@ -2304,6 +2304,7 @@ enum rs6000_builtin_type_index
>RS6000_BTI_ptr_vector_quad,
>RS6000_BTI_ptr_long_long,
>RS6000_BTI_ptr_long_long_unsigned,
> + RS6000_BTI_PTI,
>RS6000_BTI_MAX
> };
>
> @@ -2348,6 +2349,7 @@ enum rs6000_builtin_type_index
> #define uintDI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_UINTDI])
> #define intTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_INTTI])
> #define uintTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_UINTTI])
> +#define intPTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_PTI])
> #define float_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_float])
> #define double_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_double])
> #define long_double_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_long_double])
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr106895.c
> b/gcc/testsuite/gcc.target/powerpc/pr106895.c
> new file mode 100644
> index 000..56547b7fa9d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr106895.c
> @@ -0,0 +1,15 @@
> +/* PR target/106895 */
> +/* { dg-require-effective-target int128 } */
> +/* { dg-options "-O2" } */
> +
> +/* Verify the following generates even/odd register pairs. */
> +
> +typedef __int128 pti __attribute__((mode(PTI)));
> +
> +void
> +set128 (pti val, pti *mem)
> +{
> +asm("stq %1,%0" : "=m"(*mem) : "r"(val));
> +}
> +
> +/* { dg-final { scan-assembler "stq \[123\]?\[02468\]" } } */
>
[PATCH v2] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
PTImode assists in generating even/odd register pairs on 128 bits. When the
user
specifies PTImode as an attribute, it breaks because there is no internal type
to handle this mode. To address this, we have created a tree node with dummy
type
to handle PTImode. We are not documenting this dummy type since users are not
allowed to use this type externally.
2024-03-21 Jeevitha Palanisamy
gcc/
PR target/110411
* config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add
RS6000_BTI_INTPTI.
* config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Add node
for PTImode type.
gcc/testsuite/
PR target/106895
* gcc.target/powerpc/pr106895.c: New testcase.
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 6698274031b..f553c72779e 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -756,6 +756,15 @@ rs6000_init_builtins (void)
else
ieee128_float_type_node = NULL_TREE;
+ /* PTImode to get even/odd register pairs. */
+ intPTI_type_internal_node = make_node(INTEGER_TYPE);
+ TYPE_PRECISION (intPTI_type_internal_node) = GET_MODE_BITSIZE (PTImode);
+ layout_type (intPTI_type_internal_node);
+ SET_TYPE_MODE (intPTI_type_internal_node, PTImode);
+ t = build_qualified_type (intPTI_type_internal_node, TYPE_QUAL_CONST);
+ lang_hooks.types.register_builtin_type (intPTI_type_internal_node,
+ "__dummypti");
+
/* Vector pair and vector quad support. */
vector_pair_type_node = make_node (OPAQUE_TYPE);
SET_TYPE_MODE (vector_pair_type_node, OOmode);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 68bc45d65ba..b6078077b20 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2302,6 +2302,7 @@ enum rs6000_builtin_type_index
RS6000_BTI_ptr_vector_quad,
RS6000_BTI_ptr_long_long,
RS6000_BTI_ptr_long_long_unsigned,
+ RS6000_BTI_INTPTI,
RS6000_BTI_MAX
};
@@ -2346,6 +2347,7 @@ enum rs6000_builtin_type_index
#define uintDI_type_internal_node
(rs6000_builtin_types[RS6000_BTI_UINTDI])
#define intTI_type_internal_node
(rs6000_builtin_types[RS6000_BTI_INTTI])
#define uintTI_type_internal_node
(rs6000_builtin_types[RS6000_BTI_UINTTI])
+#define intPTI_type_internal_node
(rs6000_builtin_types[RS6000_BTI_INTPTI])
#define float_type_internal_node
(rs6000_builtin_types[RS6000_BTI_float])
#define double_type_internal_node
(rs6000_builtin_types[RS6000_BTI_double])
#define long_double_type_internal_node
(rs6000_builtin_types[RS6000_BTI_long_double])
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106895.c
b/gcc/testsuite/gcc.target/powerpc/pr106895.c
new file mode 100644
index 000..56547b7fa9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr106895.c
@@ -0,0 +1,15 @@
+/* PR target/106895 */
+/* { dg-require-effective-target int128 } */
+/* { dg-options "-O2" } */
+
+/* Verify the following generates even/odd register pairs. */
+
+typedef __int128 pti __attribute__((mode(PTI)));
+
+void
+set128 (pti val, pti *mem)
+{
+asm("stq %1,%0" : "=m"(*mem) : "r"(val));
+}
+
+/* { dg-final { scan-assembler "stq \[123\]?\[02468\]" } } */
[PING^2][PATCH] rs6000: load high and low part of 128bit vector independently [PR110040]
Ping!
please review.
Thanks & Regards
Jeevitha
On 26/02/24 11:13 am, jeevitha wrote:
> Hi All,
>
> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>
> PR110040 exposes an issue concerning moves from vector registers to GPRs.
> There are two moves, one for upper 64 bits and the other for the lower
> 64 bits. In the problematic test case, we are only interested in storing
> the lower 64 bits. However, the instruction for copying the upper 64 bits
> is still emitted and is dead code. This patch adds a splitter that splits
> apart the two move instructions so that DCE can remove the dead code after
> splitting.
>
> 2024-02-26 Jeevitha Palanisamy
>
> gcc/
> PR target/110040
> * config/rs6000/vsx.md (split pattern for V1TI to DI move): Defined.
>
> gcc/testsuite/
> PR target/110040
> * gcc.target/powerpc/pr110040-1.c: New testcase.
> * gcc.target/powerpc/pr110040-2.c: New testcase.
>
>
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index 6111cc90eb7..78457f8fb14 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -6706,3 +6706,19 @@
>"vmsumcud %0,%1,%2,%3"
>[(set_attr "type" "veccomplex")]
> )
> +
> +(define_split
> + [(set (match_operand:V1TI 0 "int_reg_operand")
> + (match_operand:V1TI 1 "vsx_register_operand"))]
> + "reload_completed
> + && TARGET_DIRECT_MOVE_64BIT"
> + [(pc)]
> +{
> + rtx op0 = gen_rtx_REG (DImode, REGNO (operands[0]));
> + rtx op1 = gen_rtx_REG (V2DImode, REGNO (operands[1]));
> + rtx op2 = gen_rtx_REG (DImode, REGNO (operands[0]) + 1);
> + rtx op3 = gen_rtx_REG (V2DImode, REGNO (operands[1]));
> + emit_insn (gen_vsx_extract_v2di (op0, op1, GEN_INT (0)));
> + emit_insn (gen_vsx_extract_v2di (op2, op3, GEN_INT (1)));
> + DONE;
> +})
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
> b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
> new file mode 100644
> index 000..fb3bd254636
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
> @@ -0,0 +1,14 @@
> +/* PR target/110040 */
> +/* { dg-do compile } */
> +/* { dg-require-effective-target powerpc_p9vector_ok } */
> +/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
> +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
> +
> +#include
> +
> +void
> +foo (signed long *dst, vector signed __int128 src)
> +{
> + *dst = (signed long) src[0];
> +}
> +
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
> b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
> new file mode 100644
> index 000..f3aa22be4e8
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
> @@ -0,0 +1,13 @@
> +/* PR target/110040 */
> +/* { dg-do compile } */
> +/* { dg-require-effective-target power10_ok } */
> +/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
> +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
> +
> +#include
> +
> +void
> +foo (signed int *dst, vector signed __int128 src)
> +{
> + __builtin_vec_xst_trunc (src, 0, dst);
> +}
>
>
[PATCH] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
PTImode attribute assists in generating even/odd register pairs on 128 bits.
When the user specifies PTImode as an attribute, it breaks because there is no
internal type to handle this mode . We have created a tree node with dummy type
to handle PTImode. We are not documenting this dummy type since users are not
allowed to use this type externally.
2024-02-23 Jeevitha Palanisamy
gcc/
PR target/106895
* config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add fields
to hold PTImode type.
* config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Add node
for PTImode type.
gcc/testsuite/
PR target/106895
* gcc.target/powerpc/pr106895.c: New testcase.
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 6698274031b..f553c72779e 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -756,6 +756,15 @@ rs6000_init_builtins (void)
else
ieee128_float_type_node = NULL_TREE;
+ /* PTImode to get even/odd register pairs. */
+ intPTI_type_internal_node = make_node(INTEGER_TYPE);
+ TYPE_PRECISION (intPTI_type_internal_node) = GET_MODE_BITSIZE (PTImode);
+ layout_type (intPTI_type_internal_node);
+ SET_TYPE_MODE (intPTI_type_internal_node, PTImode);
+ t = build_qualified_type (intPTI_type_internal_node, TYPE_QUAL_CONST);
+ lang_hooks.types.register_builtin_type (intPTI_type_internal_node,
+ "__dummypti");
+
/* Vector pair and vector quad support. */
vector_pair_type_node = make_node (OPAQUE_TYPE);
SET_TYPE_MODE (vector_pair_type_node, OOmode);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 2291fe8d3a3..77bb937a28b 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2304,6 +2304,7 @@ enum rs6000_builtin_type_index
RS6000_BTI_ptr_vector_quad,
RS6000_BTI_ptr_long_long,
RS6000_BTI_ptr_long_long_unsigned,
+ RS6000_BTI_PTI,
RS6000_BTI_MAX
};
@@ -2348,6 +2349,7 @@ enum rs6000_builtin_type_index
#define uintDI_type_internal_node
(rs6000_builtin_types[RS6000_BTI_UINTDI])
#define intTI_type_internal_node
(rs6000_builtin_types[RS6000_BTI_INTTI])
#define uintTI_type_internal_node
(rs6000_builtin_types[RS6000_BTI_UINTTI])
+#define intPTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_PTI])
#define float_type_internal_node
(rs6000_builtin_types[RS6000_BTI_float])
#define double_type_internal_node
(rs6000_builtin_types[RS6000_BTI_double])
#define long_double_type_internal_node
(rs6000_builtin_types[RS6000_BTI_long_double])
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106895.c
b/gcc/testsuite/gcc.target/powerpc/pr106895.c
new file mode 100644
index 000..56547b7fa9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr106895.c
@@ -0,0 +1,15 @@
+/* PR target/106895 */
+/* { dg-require-effective-target int128 } */
+/* { dg-options "-O2" } */
+
+/* Verify the following generates even/odd register pairs. */
+
+typedef __int128 pti __attribute__((mode(PTI)));
+
+void
+set128 (pti val, pti *mem)
+{
+asm("stq %1,%0" : "=m"(*mem) : "r"(val));
+}
+
+/* { dg-final { scan-assembler "stq \[123\]?\[02468\]" } } */
[PATCH] rs6000: load high and low part of 128bit vector independently [PR110040]
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
PR110040 exposes an issue concerning moves from vector registers to GPRs.
There are two moves, one for upper 64 bits and the other for the lower
64 bits. In the problematic test case, we are only interested in storing
the lower 64 bits. However, the instruction for copying the upper 64 bits
is still emitted and is dead code. This patch adds a splitter that splits
apart the two move instructions so that DCE can remove the dead code after
splitting.
2024-02-26 Jeevitha Palanisamy
gcc/
PR target/110040
* config/rs6000/vsx.md (split pattern for V1TI to DI move): Defined.
gcc/testsuite/
PR target/110040
* gcc.target/powerpc/pr110040-1.c: New testcase.
* gcc.target/powerpc/pr110040-2.c: New testcase.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 6111cc90eb7..78457f8fb14 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -6706,3 +6706,19 @@
"vmsumcud %0,%1,%2,%3"
[(set_attr "type" "veccomplex")]
)
+
+(define_split
+ [(set (match_operand:V1TI 0 "int_reg_operand")
+ (match_operand:V1TI 1 "vsx_register_operand"))]
+ "reload_completed
+ && TARGET_DIRECT_MOVE_64BIT"
+ [(pc)]
+{
+ rtx op0 = gen_rtx_REG (DImode, REGNO (operands[0]));
+ rtx op1 = gen_rtx_REG (V2DImode, REGNO (operands[1]));
+ rtx op2 = gen_rtx_REG (DImode, REGNO (operands[0]) + 1);
+ rtx op3 = gen_rtx_REG (V2DImode, REGNO (operands[1]));
+ emit_insn (gen_vsx_extract_v2di (op0, op1, GEN_INT (0)));
+ emit_insn (gen_vsx_extract_v2di (op2, op3, GEN_INT (1)));
+ DONE;
+})
diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
new file mode 100644
index 000..fb3bd254636
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
@@ -0,0 +1,14 @@
+/* PR target/110040 */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
+/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
+
+#include
+
+void
+foo (signed long *dst, vector signed __int128 src)
+{
+ *dst = (signed long) src[0];
+}
+
diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
new file mode 100644
index 000..f3aa22be4e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
@@ -0,0 +1,13 @@
+/* PR target/110040 */
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
+
+#include
+
+void
+foo (signed int *dst, vector signed __int128 src)
+{
+ __builtin_vec_xst_trunc (src, 0, dst);
+}
[PATCH] rs6000: Don't allow immediate value in the vsx_splat pattern [PR113950]
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
There is no immediate value splatting instruction in powerpc. Currently that
needs to be stored in a register or memory. For addressing this I have updated
the predicate for the second operand in vsx_splat to splat_input_operand,
which will handle the operands appropriately.
2024-02-26 Jeevitha Palanisamy
gcc/
PR target/113950
* config/rs6000/vsx.md (vsx_splat_): Updated the predicates
for second operand.
gcc/testsuite/
PR target/113950
* gcc.target/powerpc/pr113950.c: New testcase.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 6111cc90eb7..e5688ff972a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4660,7 +4660,7 @@
(define_expand "vsx_splat_"
[(set (match_operand:VSX_D 0 "vsx_register_operand")
(vec_duplicate:VSX_D
-(match_operand: 1 "input_operand")))]
+(match_operand: 1 "splat_input_operand")))]
"VECTOR_MEM_VSX_P (mode)"
{
rtx op1 = operands[1];
diff --git a/gcc/testsuite/gcc.target/powerpc/pr113950.c
b/gcc/testsuite/gcc.target/powerpc/pr113950.c
new file mode 100644
index 000..29ded29f683
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr113950.c
@@ -0,0 +1,24 @@
+/* PR target/113950 */
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+/* Verify we do not ICE on the following. */
+
+void abort (void);
+
+int main ()
+{
+ int i;
+ vector signed long long vsll_result, vsll_expected_result;
+ signed long long sll_arg1;
+
+ sll_arg1 = 300;
+ vsll_expected_result = (vector signed long long) {300, 300};
+ vsll_result = __builtin_vsx_splat_2di (sll_arg1);
+
+ for (i = 0; i < 2; i++)
+if (vsll_result[i] != vsll_expected_result[i])
+ abort();
+
+ return 0;
+}
Re: [PATCH] rs6000: Don't allow immediate value in the vsx_splat pattern [PR113950]
On 26/02/24 8:37 pm, Peter Bergner wrote:
> On 2/26/24 4:49 AM, Kewen.Lin wrote:
>> on 2024/2/26 14:18, jeevitha wrote:
>>> Hi All,
>>> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
>>> index 6111cc90eb7..e5688ff972a 100644
>>> --- a/gcc/config/rs6000/vsx.md
>>> +++ b/gcc/config/rs6000/vsx.md
>>> @@ -4660,7 +4660,7 @@
>>> (define_expand "vsx_splat_"
>>>[(set (match_operand:VSX_D 0 "vsx_register_operand")
>>> (vec_duplicate:VSX_D
>>> -(match_operand: 1 "input_operand")))]
>>> +(match_operand: 1 "splat_input_operand")))]
>>>"VECTOR_MEM_VSX_P (mode)"
>>> {
>>>rtx op1 = operands[1];
>>
>> This hunk actually does force_reg already:
>>
>> ...
>> else if (!REG_P (op1))
>> op1 = force_reg (mode, op1);
>>
>> but it's assigning to op1 unexpectedly (an omission IMHO), so just
>> simply fix it with:
>>
>> else if (!REG_P (op1))
>> -op1 = force_reg (mode, op1);
>> +operands[1] = force_reg (mode, op1);
>
> I agree op1 was an oversight and it should be operands[1].
> That said, I think using more precise predicates is a good thing,
> so I think we should use both Jeevitha's predicate change and
> your operands[1] change.
>
> I'll note that Jeevitha originally had the operands[1] change, but I
> didn't look closely enough at the issue or the pattern and mentioned
> that these kinds of bugs can be caused by too loose constraints and
> predicates, which is when she found the updated predicate to use.
> I believe she already even bootstrapped and regtested the operands[1]
> only change. Jeevitha???
>
>
Yes, Peter. I have already bootstrapped and regtested the operands[1] change.
[PATCH V2] rs6000: Don't allow immediate value in the vsx_splat pattern [PR113950]
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
There is no immediate value splatting instruction in Power. Currently, those
values need to be stored in a register or memory. To address this issue, I
have updated the predicate for the second operand in vsx_splat to
splat_input_operand and corrected the assignment of op1 to operands[1].
These changes ensure that operand1 is stored in a register.
2024-02-26 Jeevitha Palanisamy
gcc/
PR target/113950
* config/rs6000/vsx.md (vsx_splat_): Updated the predicates
for second operand and corrected the assignment.
gcc/testsuite/
PR target/113950
* gcc.target/powerpc/pr113950.c: New testcase.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 6111cc90eb7..3e2df247630 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4660,14 +4660,14 @@
(define_expand "vsx_splat_"
[(set (match_operand:VSX_D 0 "vsx_register_operand")
(vec_duplicate:VSX_D
-(match_operand: 1 "input_operand")))]
+(match_operand: 1 "splat_input_operand")))]
"VECTOR_MEM_VSX_P (mode)"
{
rtx op1 = operands[1];
if (MEM_P (op1))
operands[1] = rs6000_force_indexed_or_indirect_mem (op1);
else if (!REG_P (op1))
-op1 = force_reg (mode, op1);
+operands[1] = force_reg (mode, op1);
})
(define_insn "vsx_splat__reg"
diff --git a/gcc/testsuite/gcc.target/powerpc/pr113950.c
b/gcc/testsuite/gcc.target/powerpc/pr113950.c
new file mode 100644
index 000..5c6865a8544
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr113950.c
@@ -0,0 +1,25 @@
+/* PR target/113950 */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O1 -mdejagnu-cpu=power7" } */
+
+/* Verify we do not ICE on the following. */
+
+void abort (void);
+
+int main ()
+{
+ int i;
+ vector signed long long vsll_result, vsll_expected_result;
+ signed long long sll_arg1;
+
+ sll_arg1 = 300;
+ vsll_expected_result = (vector signed long long) {300, 300};
+ vsll_result = __builtin_vsx_splat_2di (sll_arg1);
+
+ for (i = 0; i < 2; i++)
+if (vsll_result[i] != vsll_expected_result[i])
+ abort();
+
+ return 0;
+}
Re: [PATCH] rs6000: Don't allow immediate value in the vsx_splat pattern [PR113950]
On 27/02/24 8:26 am, Kewen.Lin wrote: > on 2024/2/27 10:13, Peter Bergner wrote: >> On 2/26/24 7:55 PM, Kewen.Lin wrote: >>> on 2024/2/26 23:07, Peter Bergner wrote: >> >>> Good point, or maybe just an explicit -mvsx like some existing ones, which >>> can avoid to only test some fixed cpu type. >> >> If a simple "-O1 -vsx" is enough to expose the ICE on an unpacthed >> compiler and a PASS on a patched compiler, then I'm all for it. >> Jeevitha, can you try confirming that? Yes, Peter, I've confirmed that using "-O1 -mvsx" is sufficient to expose the issue on the unpatched compiler and ensure successful compilation on the patched one. > > Jeevitha, can you also check why we have the different behavior on GCC 11 when > you get time? GCC 12 has new built-in framework, so this ICE gets exposed, > but > IMHO it would still be good to double check the previous behavior is due to > some miss support or some other latent bug. Thanks in advance! Sure Kewen, I will have a look. Jeevitha
Re: [PING ^3][PATCH] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]
Ping! Please review On 13/11/23 8:38 pm, jeevitha wrote: > Ping! > > please review. > > Thanks & Regards > Jeevitha > > On 25/08/23 7:49 am, Peter Bergner wrote: >> On 8/24/23 12:35 PM, Michael Meissner wrote: >>> On Thu, Jul 20, 2023 at 10:05:28AM +0530, jeevitha wrote: >>>> gcc/ >>>>PR target/110411 >>>>* config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add fields >>>>to hold PTImode type. >>>>* config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Add node >>>>for PTImode type. >>> >>> It is good as far as it goes, but I suspect we will eventually need to >>> extend >>> it. In particular, the reason people need PTImode is they need the even/odd >>> register layout. What you've done enables users to declare this value. >> >> Sure, it could be extended, but that is not what this patch is about. >> It's purely to allow the kernel team access to the guaranteed even/odd >> register layout for some inline asm code. Any extension would be a >> follow-on patch to this. >> >> >> >> On 8/9/23 3:48 AM, Kewen.Lin wrote: >>> IIUC, this builtin type registering makes this type expose to users, so >>> I wonder if we want to actually expose this type for users' uses. >>> If yes, we need to update the documentation (and not sure if the current >>> name is good enough); Is the current name acceptable if we're not going to document the type? >> >> Segher, Mike, Jeevitha and I talked about the patch and Segher mentioned >> that under some conditions, it's fine to keep the type undocumented. >> Hopefully he'll weigh in on whether this particular patch is one of >> those cases or not. >> >> >> Peter Thanks & Regards Jeevitha
[PING ^1][PATCH] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]
Ping! please review. Thanks & Regards Jeevitha On 25/08/23 7:49 am, Peter Bergner wrote: > On 8/24/23 12:35 PM, Michael Meissner wrote: >> On Thu, Jul 20, 2023 at 10:05:28AM +0530, jeevitha wrote: >>> gcc/ >>> PR target/110411 >>> * config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add fields >>> to hold PTImode type. >>> * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Add node >>> for PTImode type. >> >> It is good as far as it goes, but I suspect we will eventually need to extend >> it. In particular, the reason people need PTImode is they need the even/odd >> register layout. What you've done enables users to declare this value. > > Sure, it could be extended, but that is not what this patch is about. > It's purely to allow the kernel team access to the guaranteed even/odd > register layout for some inline asm code. Any extension would be a > follow-on patch to this. > > > > On 8/9/23 3:48 AM, Kewen.Lin wrote: >> IIUC, this builtin type registering makes this type expose to users, so >> I wonder if we want to actually expose this type for users' uses. >> If yes, we need to update the documentation (and not sure if the current >> name is good enough); otherwise, I wonder if there is some existing >> practice to declare a builtin type with a name which users can't actually >> use and is just for shadowing a mode. > > Segher, Mike, Jeevitha and I talked about the patch and Segher mentioned > that under some conditions, it's fine to keep the type undocumented. > Hopefully he'll weigh in on whether this particular patch is one of > those cases or not. > > > Peter
Re: [PATCH] rs6000: Disable PCREL for unsupported targets [PR111045]
On 11/11/23 5:21 am, Peter Bergner wrote: > Jeevitha, can you test this patch to see whether it fixes the testsuite > issue caused by your earlier patch that was approved, but not yet pushed? > That was the use GPR2 for register allocation, correct? Note, you'll need > to update the patch to replace the rs6000_pcrel_p() usage with just > TARGET_PCREL, since this patch removes rs6000_pcrel_p(). Yeah Peter. This patch fixes the testsuite issue for GPR2 register allocation patch [PR110320].
[PING^4][PATCH v2] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]
Ping!
Please review.
Thanks & Regards
Jeevitha
On 19/06/24 6:12 pm, jeevitha wrote:
> Ping!
>
> Please review. Are there any more changes required?
>
> Thanks & Regards
> Jeevitha
>
> On 21/05/24 10:28 am, jeevitha wrote:
>> Ping!
>>
>> please review.
>>
>> Thanks & Regards
>> Jeevitha
>>
>>
>> On 17/04/24 2:44 pm, jeevitha wrote:
>>> Ping!
>>>
>>> I've incorporated all the suggested changes. Please review.
>>>
>>> Thanks & Regards
>>> Jeevitha
>>>
>>> On 21/03/24 6:21 pm, jeevitha wrote:
>>>> Hi All,
>>>>
>>>> The following patch has been bootstrapped and regtested on
>>>> powerpc64le-linux.
>>>>
>>>> PTImode assists in generating even/odd register pairs on 128 bits. When
>>>> the user
>>>> specifies PTImode as an attribute, it breaks because there is no internal
>>>> type
>>>> to handle this mode. To address this, we have created a tree node with
>>>> dummy type
>>>> to handle PTImode. We are not documenting this dummy type since users are
>>>> not
>>>> allowed to use this type externally.
>>>>
>>>> 2024-03-21 Jeevitha Palanisamy
>>>>
>>>> gcc/
>>>>PR target/110411
>>>>* config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add
>>>>RS6000_BTI_INTPTI.
>>>>* config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Add node
>>>>for PTImode type.
>>>>
>>>> gcc/testsuite/
>>>>PR target/106895
>>>>* gcc.target/powerpc/pr106895.c: New testcase.
>>>>
>>>> diff --git a/gcc/config/rs6000/rs6000-builtin.cc
>>>> b/gcc/config/rs6000/rs6000-builtin.cc
>>>> index 6698274031b..f553c72779e 100644
>>>> --- a/gcc/config/rs6000/rs6000-builtin.cc
>>>> +++ b/gcc/config/rs6000/rs6000-builtin.cc
>>>> @@ -756,6 +756,15 @@ rs6000_init_builtins (void)
>>>>else
>>>> ieee128_float_type_node = NULL_TREE;
>>>>
>>>> + /* PTImode to get even/odd register pairs. */
>>>> + intPTI_type_internal_node = make_node(INTEGER_TYPE);
>>>> + TYPE_PRECISION (intPTI_type_internal_node) = GET_MODE_BITSIZE (PTImode);
>>>> + layout_type (intPTI_type_internal_node);
>>>> + SET_TYPE_MODE (intPTI_type_internal_node, PTImode);
>>>> + t = build_qualified_type (intPTI_type_internal_node, TYPE_QUAL_CONST);
>>>> + lang_hooks.types.register_builtin_type (intPTI_type_internal_node,
>>>> +"__dummypti");
>>>> +
>>>>/* Vector pair and vector quad support. */
>>>>vector_pair_type_node = make_node (OPAQUE_TYPE);
>>>>SET_TYPE_MODE (vector_pair_type_node, OOmode);
>>>> diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
>>>> index 68bc45d65ba..b6078077b20 100644
>>>> --- a/gcc/config/rs6000/rs6000.h
>>>> +++ b/gcc/config/rs6000/rs6000.h
>>>> @@ -2302,6 +2302,7 @@ enum rs6000_builtin_type_index
>>>>RS6000_BTI_ptr_vector_quad,
>>>>RS6000_BTI_ptr_long_long,
>>>>RS6000_BTI_ptr_long_long_unsigned,
>>>> + RS6000_BTI_INTPTI,
>>>>RS6000_BTI_MAX
>>>> };
>>>>
>>>> @@ -2346,6 +2347,7 @@ enum rs6000_builtin_type_index
>>>> #define uintDI_type_internal_node
>>>> (rs6000_builtin_types[RS6000_BTI_UINTDI])
>>>> #define intTI_type_internal_node
>>>> (rs6000_builtin_types[RS6000_BTI_INTTI])
>>>> #define uintTI_type_internal_node
>>>> (rs6000_builtin_types[RS6000_BTI_UINTTI])
>>>> +#define intPTI_type_internal_node
>>>> (rs6000_builtin_types[RS6000_BTI_INTPTI])
>>>> #define float_type_internal_node
>>>> (rs6000_builtin_types[RS6000_BTI_float])
>>>> #define double_type_internal_node
>>>> (rs6000_builtin_types[RS6000_BTI_double])
>>>> #define long_double_type_internal_node
>>>> (rs6000_builtin_types[RS6000_BTI_long_double])
>>>> diff --git a/gcc/testsuite/gcc.target/powerpc/pr106895.c
>>>> b/gcc/testsuite/gcc.target/powerpc/pr106895.c
>>>> new file mode 100644
>>>> index 000..56547b7fa9d
>>>> --- /dev/null
>>>> +++ b/gcc/testsuite/gcc.target/powerpc/pr106895.c
>>>> @@ -0,0 +1,15 @@
>>>> +/* PR target/106895 */
>>>> +/* { dg-require-effective-target int128 } */
>>>> +/* { dg-options "-O2" } */
>>>> +
>>>> +/* Verify the following generates even/odd register pairs. */
>>>> +
>>>> +typedef __int128 pti __attribute__((mode(PTI)));
>>>> +
>>>> +void
>>>> +set128 (pti val, pti *mem)
>>>> +{
>>>> +asm("stq %1,%0" : "=m"(*mem) : "r"(val));
>>>> +}
>>>> +
>>>> +/* { dg-final { scan-assembler "stq \[123\]?\[02468\]" } } */
>>>>
>>>>
[PATCH V2] rs6000: Don't pass -many to the assembler [PR112868]
Hi All,
The following patch has been bootstrapped and regtested with default
configuration
[--enable-checking=yes] and with --enable-checking=release on powerpc64le-linux.
This patch removes passing the -many assembler option for release builds. Now,
GCC no longer passes -many under any conditions to the assembler.
This patch exposes the issue with target_powerpc_ppu_ok, which makes a few
test cases unsupported. Those changes will be in another patch.
2024-07-11 Jeevitha Palanisamy
gcc/
PR target/112868
* config/rs6000/rs6000.h (ASM_OPT_ANY): Removed Define.
(ASM_CPU_SPEC): Remove ASM_OPT_ANY usage.
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 9211f91740a..a5bd8e461a0 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -94,12 +94,6 @@
"%{mdejagnu-*: %
Re: [PING^2][PATCH v2] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]
Ping!
please review.
Thanks & Regards
Jeevitha
On 17/04/24 2:44 pm, jeevitha wrote:
> Ping!
>
> I've incorporated all the suggested changes. Please review.
>
> Thanks & Regards
> Jeevitha
>
> On 21/03/24 6:21 pm, jeevitha wrote:
>> Hi All,
>>
>> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>>
>> PTImode assists in generating even/odd register pairs on 128 bits. When the
>> user
>> specifies PTImode as an attribute, it breaks because there is no internal
>> type
>> to handle this mode. To address this, we have created a tree node with dummy
>> type
>> to handle PTImode. We are not documenting this dummy type since users are not
>> allowed to use this type externally.
>>
>> 2024-03-21 Jeevitha Palanisamy
>>
>> gcc/
>> PR target/110411
>> * config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add
>> RS6000_BTI_INTPTI.
>> * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Add node
>> for PTImode type.
>>
>> gcc/testsuite/
>> PR target/106895
>> * gcc.target/powerpc/pr106895.c: New testcase.
>>
>> diff --git a/gcc/config/rs6000/rs6000-builtin.cc
>> b/gcc/config/rs6000/rs6000-builtin.cc
>> index 6698274031b..f553c72779e 100644
>> --- a/gcc/config/rs6000/rs6000-builtin.cc
>> +++ b/gcc/config/rs6000/rs6000-builtin.cc
>> @@ -756,6 +756,15 @@ rs6000_init_builtins (void)
>>else
>> ieee128_float_type_node = NULL_TREE;
>>
>> + /* PTImode to get even/odd register pairs. */
>> + intPTI_type_internal_node = make_node(INTEGER_TYPE);
>> + TYPE_PRECISION (intPTI_type_internal_node) = GET_MODE_BITSIZE (PTImode);
>> + layout_type (intPTI_type_internal_node);
>> + SET_TYPE_MODE (intPTI_type_internal_node, PTImode);
>> + t = build_qualified_type (intPTI_type_internal_node, TYPE_QUAL_CONST);
>> + lang_hooks.types.register_builtin_type (intPTI_type_internal_node,
>> + "__dummypti");
>> +
>>/* Vector pair and vector quad support. */
>>vector_pair_type_node = make_node (OPAQUE_TYPE);
>>SET_TYPE_MODE (vector_pair_type_node, OOmode);
>> diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
>> index 68bc45d65ba..b6078077b20 100644
>> --- a/gcc/config/rs6000/rs6000.h
>> +++ b/gcc/config/rs6000/rs6000.h
>> @@ -2302,6 +2302,7 @@ enum rs6000_builtin_type_index
>>RS6000_BTI_ptr_vector_quad,
>>RS6000_BTI_ptr_long_long,
>>RS6000_BTI_ptr_long_long_unsigned,
>> + RS6000_BTI_INTPTI,
>>RS6000_BTI_MAX
>> };
>>
>> @@ -2346,6 +2347,7 @@ enum rs6000_builtin_type_index
>> #define uintDI_type_internal_node
>> (rs6000_builtin_types[RS6000_BTI_UINTDI])
>> #define intTI_type_internal_node
>> (rs6000_builtin_types[RS6000_BTI_INTTI])
>> #define uintTI_type_internal_node
>> (rs6000_builtin_types[RS6000_BTI_UINTTI])
>> +#define intPTI_type_internal_node
>> (rs6000_builtin_types[RS6000_BTI_INTPTI])
>> #define float_type_internal_node
>> (rs6000_builtin_types[RS6000_BTI_float])
>> #define double_type_internal_node
>> (rs6000_builtin_types[RS6000_BTI_double])
>> #define long_double_type_internal_node
>> (rs6000_builtin_types[RS6000_BTI_long_double])
>> diff --git a/gcc/testsuite/gcc.target/powerpc/pr106895.c
>> b/gcc/testsuite/gcc.target/powerpc/pr106895.c
>> new file mode 100644
>> index 000..56547b7fa9d
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/powerpc/pr106895.c
>> @@ -0,0 +1,15 @@
>> +/* PR target/106895 */
>> +/* { dg-require-effective-target int128 } */
>> +/* { dg-options "-O2" } */
>> +
>> +/* Verify the following generates even/odd register pairs. */
>> +
>> +typedef __int128 pti __attribute__((mode(PTI)));
>> +
>> +void
>> +set128 (pti val, pti *mem)
>> +{
>> +asm("stq %1,%0" : "=m"(*mem) : "r"(val));
>> +}
>> +
>> +/* { dg-final { scan-assembler "stq \[123\]?\[02468\]" } } */
>>
>>
Re: [PING^4][PATCH] rs6000: load high and low part of 128bit vector independently [PR110040]
Ping!
please review.
Thanks & Regards
Jeevitha
On 17/04/24 2:46 pm, jeevitha wrote:
> Ping!
>
> please review.
>
> Thanks & Regards
> Jeevitha
>
> On 26/03/24 10:23 am, jeevitha wrote:
>> Ping!
>>
>> please review.
>>
>> Thanks & Regards
>> Jeevitha
>>
>>
>> On 26/02/24 11:13 am, jeevitha wrote:
>>> Hi All,
>>>
>>> The following patch has been bootstrapped and regtested on
>>> powerpc64le-linux.
>>>
>>> PR110040 exposes an issue concerning moves from vector registers to GPRs.
>>> There are two moves, one for upper 64 bits and the other for the lower
>>> 64 bits. In the problematic test case, we are only interested in storing
>>> the lower 64 bits. However, the instruction for copying the upper 64 bits
>>> is still emitted and is dead code. This patch adds a splitter that splits
>>> apart the two move instructions so that DCE can remove the dead code after
>>> splitting.
>>>
>>> 2024-02-26 Jeevitha Palanisamy
>>>
>>> gcc/
>>> PR target/110040
>>> * config/rs6000/vsx.md (split pattern for V1TI to DI move): Defined.
>>>
>>> gcc/testsuite/
>>> PR target/110040
>>> * gcc.target/powerpc/pr110040-1.c: New testcase.
>>> * gcc.target/powerpc/pr110040-2.c: New testcase.
>>>
>>>
>>> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
>>> index 6111cc90eb7..78457f8fb14 100644
>>> --- a/gcc/config/rs6000/vsx.md
>>> +++ b/gcc/config/rs6000/vsx.md
>>> @@ -6706,3 +6706,19 @@
>>>"vmsumcud %0,%1,%2,%3"
>>>[(set_attr "type" "veccomplex")]
>>> )
>>> +
>>> +(define_split
>>> + [(set (match_operand:V1TI 0 "int_reg_operand")
>>> + (match_operand:V1TI 1 "vsx_register_operand"))]
>>> + "reload_completed
>>> + && TARGET_DIRECT_MOVE_64BIT"
>>> + [(pc)]
>>> +{
>>> + rtx op0 = gen_rtx_REG (DImode, REGNO (operands[0]));
>>> + rtx op1 = gen_rtx_REG (V2DImode, REGNO (operands[1]));
>>> + rtx op2 = gen_rtx_REG (DImode, REGNO (operands[0]) + 1);
>>> + rtx op3 = gen_rtx_REG (V2DImode, REGNO (operands[1]));
>>> + emit_insn (gen_vsx_extract_v2di (op0, op1, GEN_INT (0)));
>>> + emit_insn (gen_vsx_extract_v2di (op2, op3, GEN_INT (1)));
>>> + DONE;
>>> +})
>>> diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
>>> b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
>>> new file mode 100644
>>> index 000..fb3bd254636
>>> --- /dev/null
>>> +++ b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
>>> @@ -0,0 +1,14 @@
>>> +/* PR target/110040 */
>>> +/* { dg-do compile } */
>>> +/* { dg-require-effective-target powerpc_p9vector_ok } */
>>> +/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
>>> +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
>>> +
>>> +#include
>>> +
>>> +void
>>> +foo (signed long *dst, vector signed __int128 src)
>>> +{
>>> + *dst = (signed long) src[0];
>>> +}
>>> +
>>> diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
>>> b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
>>> new file mode 100644
>>> index 000..f3aa22be4e8
>>> --- /dev/null
>>> +++ b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
>>> @@ -0,0 +1,13 @@
>>> +/* PR target/110040 */
>>> +/* { dg-do compile } */
>>> +/* { dg-require-effective-target power10_ok } */
>>> +/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
>>> +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
>>> +
>>> +#include
>>> +
>>> +void
>>> +foo (signed int *dst, vector signed __int128 src)
>>> +{
>>> + __builtin_vec_xst_trunc (src, 0, dst);
>>> +}
>>>
>>>
[PATCH] rs6000: Don't pass -many to the assembler [PR112868]
Hi All,
The following patch has been bootstrapped and regtested with default
configuration
[--enable-checking=yes] and with --enable-checking=release on powerpc64le-linux.
This patch removes passing the -many assembler option for release builds. Now,
GCC no longer passes -many under any conditions to the assembler.
2024-05-15 Jeevitha Palanisamy
gcc/
PR target/112868
* config/rs6000/rs6000.h (ASM_OPT_ANY): Removed Define.
(ASM_CPU_SPEC): Remove ASM_OPT_ANY usage.
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 2cde2e329b0..1ccaee9d74c 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -94,12 +94,6 @@
"%{mdejagnu-*: %
[PING^5][PATCH v2] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]
Ping * 5.
Segher, I've incorporated all the suggested changes. Are there any more changes
required?
Jeevitha
On 21/03/24 6:21 pm, jeevitha wrote:
> Hi All,
>
> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>
> PTImode assists in generating even/odd register pairs on 128 bits. When the
> user
> specifies PTImode as an attribute, it breaks because there is no internal
> type
> to handle this mode. To address this, we have created a tree node with dummy
> type
> to handle PTImode. We are not documenting this dummy type since users are not
> allowed to use this type externally.
>
> 2024-03-21 Jeevitha Palanisamy
>
> gcc/
> PR target/110411
> * config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add
> RS6000_BTI_INTPTI.
> * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Add node
> for PTImode type.
>
> gcc/testsuite/
> PR target/106895
> * gcc.target/powerpc/pr106895.c: New testcase.
>
> diff --git a/gcc/config/rs6000/rs6000-builtin.cc
> b/gcc/config/rs6000/rs6000-builtin.cc
> index 6698274031b..f553c72779e 100644
> --- a/gcc/config/rs6000/rs6000-builtin.cc
> +++ b/gcc/config/rs6000/rs6000-builtin.cc
> @@ -756,6 +756,15 @@ rs6000_init_builtins (void)
>else
> ieee128_float_type_node = NULL_TREE;
>
> + /* PTImode to get even/odd register pairs. */
> + intPTI_type_internal_node = make_node(INTEGER_TYPE);
> + TYPE_PRECISION (intPTI_type_internal_node) = GET_MODE_BITSIZE (PTImode);
> + layout_type (intPTI_type_internal_node);
> + SET_TYPE_MODE (intPTI_type_internal_node, PTImode);
> + t = build_qualified_type (intPTI_type_internal_node, TYPE_QUAL_CONST);
> + lang_hooks.types.register_builtin_type (intPTI_type_internal_node,
> + "__dummypti");
> +
>/* Vector pair and vector quad support. */
>vector_pair_type_node = make_node (OPAQUE_TYPE);
>SET_TYPE_MODE (vector_pair_type_node, OOmode);
> diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
> index 68bc45d65ba..b6078077b20 100644
> --- a/gcc/config/rs6000/rs6000.h
> +++ b/gcc/config/rs6000/rs6000.h
> @@ -2302,6 +2302,7 @@ enum rs6000_builtin_type_index
>RS6000_BTI_ptr_vector_quad,
>RS6000_BTI_ptr_long_long,
>RS6000_BTI_ptr_long_long_unsigned,
> + RS6000_BTI_INTPTI,
>RS6000_BTI_MAX
> };
>
> @@ -2346,6 +2347,7 @@ enum rs6000_builtin_type_index
> #define uintDI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_UINTDI])
> #define intTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_INTTI])
> #define uintTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_UINTTI])
> +#define intPTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_INTPTI])
> #define float_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_float])
> #define double_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_double])
> #define long_double_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_long_double])
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr106895.c
> b/gcc/testsuite/gcc.target/powerpc/pr106895.c
> new file mode 100644
> index 000..56547b7fa9d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr106895.c
> @@ -0,0 +1,15 @@
> +/* PR target/106895 */
> +/* { dg-require-effective-target int128 } */
> +/* { dg-options "-O2" } */
> +
> +/* Verify the following generates even/odd register pairs. */
> +
> +typedef __int128 pti __attribute__((mode(PTI)));
> +
> +void
> +set128 (pti val, pti *mem)
> +{
> +asm("stq %1,%0" : "=m"(*mem) : "r"(val));
> +}
> +
> +/* { dg-final { scan-assembler "stq \[123\]?\[02468\]" } } */
>
[PATCH V2] rs6000: load high and low part of 128bit vector independently [PR110040]
Hi All,
Updated the patch based on review comments. This patch passed bootstrap
and regression testing on powerpc64le-linux with no regressions.
PR110040 exposes an issue concerning moves from vector registers to GPRs.
There are two moves, one for upper 64 bits and the other for the lower
64 bits. In the problematic test case, we are only interested in storing
the lower 64 bits. However, the instruction for copying the upper 64 bits
is still emitted and is dead code. This patch adds a splitter that splits
apart the two move instructions so that DCE can remove the dead code after
splitting.
2024-06-19 Jeevitha Palanisamy
gcc/
PR target/110040
* config/rs6000/vsx.md (split pattern for V1TI to DI move): Defined.
gcc/testsuite/
PR target/110040
* gcc.target/powerpc/pr110040-1.c: New testcase.
* gcc.target/powerpc/pr110040-2.c: New testcase.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index f135fa079bd..f1979815df6 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -6706,3 +6706,20 @@
"vmsumcud %0,%1,%2,%3"
[(set_attr "type" "veccomplex")]
)
+
+(define_split
+ [(set (match_operand:V1TI 0 "gpc_reg_operand")
+ (match_operand:V1TI 1 "vsx_register_operand"))]
+ "reload_completed
+ && TARGET_DIRECT_MOVE_64BIT
+ && int_reg_operand (operands[0], V1TImode)
+ && vsx_register_operand (operands[1], V1TImode)"
+ [(pc)]
+{
+ rtx src_op = gen_rtx_REG (V2DImode, REGNO (operands[1]));
+ rtx dest_op0 = gen_rtx_REG (DImode, REGNO (operands[0]));
+ rtx dest_op1 = gen_rtx_REG (DImode, REGNO (operands[0]) + 1);
+ emit_insn (gen_vsx_extract_v2di (dest_op0, src_op, const0_rtx));
+ emit_insn (gen_vsx_extract_v2di (dest_op1, src_op, const1_rtx));
+ DONE;
+})
diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
new file mode 100644
index 000..0a521e9e51d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
@@ -0,0 +1,15 @@
+/* PR target/110040 */
+/* { dg-do compile } */
+/* { dg-require-effective-target int128 } */
+/* { dg-require-effective-target powerpc_vsx } */
+/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
+/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
+
+#include
+
+void
+foo (signed long *dst, vector signed __int128 src)
+{
+ *dst = (signed long) src[0];
+}
+
diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
new file mode 100644
index 000..d2ef471d666
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
@@ -0,0 +1,16 @@
+/* PR target/110040 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+/* { dg-require-effective-target int128 } */
+/* { dg-require-effective-target powerpc_vsx } */
+/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
+
+/* Note: __builtin_altivec_tr_stxvrwx requires the -mcpu=power10 option */
+
+#include
+
+void
+foo (signed int *dst, vector signed __int128 src)
+{
+ __builtin_vec_xst_trunc (src, 0, dst);
+}
Re: [PING^3][PATCH v2] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]
Ping!
Please review. Are there any more changes required?
Thanks & Regards
Jeevitha
On 21/05/24 10:28 am, jeevitha wrote:
> Ping!
>
> please review.
>
> Thanks & Regards
> Jeevitha
>
>
> On 17/04/24 2:44 pm, jeevitha wrote:
>> Ping!
>>
>> I've incorporated all the suggested changes. Please review.
>>
>> Thanks & Regards
>> Jeevitha
>>
>> On 21/03/24 6:21 pm, jeevitha wrote:
>>> Hi All,
>>>
>>> The following patch has been bootstrapped and regtested on
>>> powerpc64le-linux.
>>>
>>> PTImode assists in generating even/odd register pairs on 128 bits. When the
>>> user
>>> specifies PTImode as an attribute, it breaks because there is no internal
>>> type
>>> to handle this mode. To address this, we have created a tree node with
>>> dummy type
>>> to handle PTImode. We are not documenting this dummy type since users are
>>> not
>>> allowed to use this type externally.
>>>
>>> 2024-03-21 Jeevitha Palanisamy
>>>
>>> gcc/
>>> PR target/110411
>>> * config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add
>>> RS6000_BTI_INTPTI.
>>> * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Add node
>>> for PTImode type.
>>>
>>> gcc/testsuite/
>>> PR target/106895
>>> * gcc.target/powerpc/pr106895.c: New testcase.
>>>
>>> diff --git a/gcc/config/rs6000/rs6000-builtin.cc
>>> b/gcc/config/rs6000/rs6000-builtin.cc
>>> index 6698274031b..f553c72779e 100644
>>> --- a/gcc/config/rs6000/rs6000-builtin.cc
>>> +++ b/gcc/config/rs6000/rs6000-builtin.cc
>>> @@ -756,6 +756,15 @@ rs6000_init_builtins (void)
>>>else
>>> ieee128_float_type_node = NULL_TREE;
>>>
>>> + /* PTImode to get even/odd register pairs. */
>>> + intPTI_type_internal_node = make_node(INTEGER_TYPE);
>>> + TYPE_PRECISION (intPTI_type_internal_node) = GET_MODE_BITSIZE (PTImode);
>>> + layout_type (intPTI_type_internal_node);
>>> + SET_TYPE_MODE (intPTI_type_internal_node, PTImode);
>>> + t = build_qualified_type (intPTI_type_internal_node, TYPE_QUAL_CONST);
>>> + lang_hooks.types.register_builtin_type (intPTI_type_internal_node,
>>> + "__dummypti");
>>> +
>>>/* Vector pair and vector quad support. */
>>>vector_pair_type_node = make_node (OPAQUE_TYPE);
>>>SET_TYPE_MODE (vector_pair_type_node, OOmode);
>>> diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
>>> index 68bc45d65ba..b6078077b20 100644
>>> --- a/gcc/config/rs6000/rs6000.h
>>> +++ b/gcc/config/rs6000/rs6000.h
>>> @@ -2302,6 +2302,7 @@ enum rs6000_builtin_type_index
>>>RS6000_BTI_ptr_vector_quad,
>>>RS6000_BTI_ptr_long_long,
>>>RS6000_BTI_ptr_long_long_unsigned,
>>> + RS6000_BTI_INTPTI,
>>>RS6000_BTI_MAX
>>> };
>>>
>>> @@ -2346,6 +2347,7 @@ enum rs6000_builtin_type_index
>>> #define uintDI_type_internal_node
>>> (rs6000_builtin_types[RS6000_BTI_UINTDI])
>>> #define intTI_type_internal_node
>>> (rs6000_builtin_types[RS6000_BTI_INTTI])
>>> #define uintTI_type_internal_node
>>> (rs6000_builtin_types[RS6000_BTI_UINTTI])
>>> +#define intPTI_type_internal_node
>>> (rs6000_builtin_types[RS6000_BTI_INTPTI])
>>> #define float_type_internal_node
>>> (rs6000_builtin_types[RS6000_BTI_float])
>>> #define double_type_internal_node
>>> (rs6000_builtin_types[RS6000_BTI_double])
>>> #define long_double_type_internal_node
>>> (rs6000_builtin_types[RS6000_BTI_long_double])
>>> diff --git a/gcc/testsuite/gcc.target/powerpc/pr106895.c
>>> b/gcc/testsuite/gcc.target/powerpc/pr106895.c
>>> new file mode 100644
>>> index 000..56547b7fa9d
>>> --- /dev/null
>>> +++ b/gcc/testsuite/gcc.target/powerpc/pr106895.c
>>> @@ -0,0 +1,15 @@
>>> +/* PR target/106895 */
>>> +/* { dg-require-effective-target int128 } */
>>> +/* { dg-options "-O2" } */
>>> +
>>> +/* Verify the following generates even/odd register pairs. */
>>> +
>>> +typedef __int128 pti __attribute__((mode(PTI)));
>>> +
>>> +void
>>> +set128 (pti val, pti *mem)
>>> +{
>>> +asm("stq %1,%0" : "=m"(*mem) : "r"(val));
>>> +}
>>> +
>>> +/* { dg-final { scan-assembler "stq \[123\]?\[02468\]" } } */
>>>
>>>
Re: [PATCH V3] rs6000: Don't ICE when compiling the __builtin_vsx_splat_2di built-in [PR113950]
Hi, On 18/03/24 7:00 am, Kewen.Lin wrote: >> The bogus vsx_splat_ code goes all the way back to GCC 8, so we >> should backport this fix. Segher and Ke Wen, can we get an approval >> to backport this to all the open release branches (GCC 13, 12, 11)? >> Thanks. > > Sure, okay for backporting this to all active branches, thanks! > I need clarification regarding the backporting of PR113950 to GCC 12. We encountered an issue while resolving merge conflicts in GCC 12. The problem lies in extra deletions in the diff due to cherry-picking. Now, we're unsure about the best approach for handling the backport. To provide context, I have included the relevant diff snippet below, diff --cc gcc/config/rs6000/vsx.md index c45794fb9ed,f135fa079bd..000 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@@ -4562,8 -4666,8 +4562,8 @@@ rtx op1 = operands[1]; if (MEM_P (op1)) operands[1] = rs6000_force_indexed_or_indirect_mem (op1); - else if (!REG_P (op1)) - op1 = force_reg (mode, op1); + else -operands[1] = force_reg (mode, op1); ++operands[1] = force_reg (mode, op1); }) I'm seeking your advice on how to proceed with the backport. Do you think the above change is acceptable, or should we also backport Segher's commit e0e3ce634818b83965b87512938490df4d57f81d, which caused the conflict?. There was no regression with both of these changes. Jeevitha.
[PING^1][PATCH v2] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]
Ping!
I've incorporated all the suggested changes. Please review.
Thanks & Regards
Jeevitha
On 21/03/24 6:21 pm, jeevitha wrote:
> Hi All,
>
> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>
> PTImode assists in generating even/odd register pairs on 128 bits. When the
> user
> specifies PTImode as an attribute, it breaks because there is no internal
> type
> to handle this mode. To address this, we have created a tree node with dummy
> type
> to handle PTImode. We are not documenting this dummy type since users are not
> allowed to use this type externally.
>
> 2024-03-21 Jeevitha Palanisamy
>
> gcc/
> PR target/110411
> * config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add
> RS6000_BTI_INTPTI.
> * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Add node
> for PTImode type.
>
> gcc/testsuite/
> PR target/106895
> * gcc.target/powerpc/pr106895.c: New testcase.
>
> diff --git a/gcc/config/rs6000/rs6000-builtin.cc
> b/gcc/config/rs6000/rs6000-builtin.cc
> index 6698274031b..f553c72779e 100644
> --- a/gcc/config/rs6000/rs6000-builtin.cc
> +++ b/gcc/config/rs6000/rs6000-builtin.cc
> @@ -756,6 +756,15 @@ rs6000_init_builtins (void)
>else
> ieee128_float_type_node = NULL_TREE;
>
> + /* PTImode to get even/odd register pairs. */
> + intPTI_type_internal_node = make_node(INTEGER_TYPE);
> + TYPE_PRECISION (intPTI_type_internal_node) = GET_MODE_BITSIZE (PTImode);
> + layout_type (intPTI_type_internal_node);
> + SET_TYPE_MODE (intPTI_type_internal_node, PTImode);
> + t = build_qualified_type (intPTI_type_internal_node, TYPE_QUAL_CONST);
> + lang_hooks.types.register_builtin_type (intPTI_type_internal_node,
> + "__dummypti");
> +
>/* Vector pair and vector quad support. */
>vector_pair_type_node = make_node (OPAQUE_TYPE);
>SET_TYPE_MODE (vector_pair_type_node, OOmode);
> diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
> index 68bc45d65ba..b6078077b20 100644
> --- a/gcc/config/rs6000/rs6000.h
> +++ b/gcc/config/rs6000/rs6000.h
> @@ -2302,6 +2302,7 @@ enum rs6000_builtin_type_index
>RS6000_BTI_ptr_vector_quad,
>RS6000_BTI_ptr_long_long,
>RS6000_BTI_ptr_long_long_unsigned,
> + RS6000_BTI_INTPTI,
>RS6000_BTI_MAX
> };
>
> @@ -2346,6 +2347,7 @@ enum rs6000_builtin_type_index
> #define uintDI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_UINTDI])
> #define intTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_INTTI])
> #define uintTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_UINTTI])
> +#define intPTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_INTPTI])
> #define float_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_float])
> #define double_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_double])
> #define long_double_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_long_double])
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr106895.c
> b/gcc/testsuite/gcc.target/powerpc/pr106895.c
> new file mode 100644
> index 000..56547b7fa9d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr106895.c
> @@ -0,0 +1,15 @@
> +/* PR target/106895 */
> +/* { dg-require-effective-target int128 } */
> +/* { dg-options "-O2" } */
> +
> +/* Verify the following generates even/odd register pairs. */
> +
> +typedef __int128 pti __attribute__((mode(PTI)));
> +
> +void
> +set128 (pti val, pti *mem)
> +{
> +asm("stq %1,%0" : "=m"(*mem) : "r"(val));
> +}
> +
> +/* { dg-final { scan-assembler "stq \[123\]?\[02468\]" } } */
>
>
[PING^3][PATCH] rs6000: load high and low part of 128bit vector independently [PR110040]
Ping!
please review.
Thanks & Regards
Jeevitha
On 26/03/24 10:23 am, jeevitha wrote:
> Ping!
>
> please review.
>
> Thanks & Regards
> Jeevitha
>
>
> On 26/02/24 11:13 am, jeevitha wrote:
>> Hi All,
>>
>> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>>
>> PR110040 exposes an issue concerning moves from vector registers to GPRs.
>> There are two moves, one for upper 64 bits and the other for the lower
>> 64 bits. In the problematic test case, we are only interested in storing
>> the lower 64 bits. However, the instruction for copying the upper 64 bits
>> is still emitted and is dead code. This patch adds a splitter that splits
>> apart the two move instructions so that DCE can remove the dead code after
>> splitting.
>>
>> 2024-02-26 Jeevitha Palanisamy
>>
>> gcc/
>> PR target/110040
>> * config/rs6000/vsx.md (split pattern for V1TI to DI move): Defined.
>>
>> gcc/testsuite/
>> PR target/110040
>> * gcc.target/powerpc/pr110040-1.c: New testcase.
>> * gcc.target/powerpc/pr110040-2.c: New testcase.
>>
>>
>> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
>> index 6111cc90eb7..78457f8fb14 100644
>> --- a/gcc/config/rs6000/vsx.md
>> +++ b/gcc/config/rs6000/vsx.md
>> @@ -6706,3 +6706,19 @@
>>"vmsumcud %0,%1,%2,%3"
>>[(set_attr "type" "veccomplex")]
>> )
>> +
>> +(define_split
>> + [(set (match_operand:V1TI 0 "int_reg_operand")
>> + (match_operand:V1TI 1 "vsx_register_operand"))]
>> + "reload_completed
>> + && TARGET_DIRECT_MOVE_64BIT"
>> + [(pc)]
>> +{
>> + rtx op0 = gen_rtx_REG (DImode, REGNO (operands[0]));
>> + rtx op1 = gen_rtx_REG (V2DImode, REGNO (operands[1]));
>> + rtx op2 = gen_rtx_REG (DImode, REGNO (operands[0]) + 1);
>> + rtx op3 = gen_rtx_REG (V2DImode, REGNO (operands[1]));
>> + emit_insn (gen_vsx_extract_v2di (op0, op1, GEN_INT (0)));
>> + emit_insn (gen_vsx_extract_v2di (op2, op3, GEN_INT (1)));
>> + DONE;
>> +})
>> diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
>> b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
>> new file mode 100644
>> index 000..fb3bd254636
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/powerpc/pr110040-1.c
>> @@ -0,0 +1,14 @@
>> +/* PR target/110040 */
>> +/* { dg-do compile } */
>> +/* { dg-require-effective-target powerpc_p9vector_ok } */
>> +/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
>> +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
>> +
>> +#include
>> +
>> +void
>> +foo (signed long *dst, vector signed __int128 src)
>> +{
>> + *dst = (signed long) src[0];
>> +}
>> +
>> diff --git a/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
>> b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
>> new file mode 100644
>> index 000..f3aa22be4e8
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/powerpc/pr110040-2.c
>> @@ -0,0 +1,13 @@
>> +/* PR target/110040 */
>> +/* { dg-do compile } */
>> +/* { dg-require-effective-target power10_ok } */
>> +/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
>> +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
>> +
>> +#include
>> +
>> +void
>> +foo (signed int *dst, vector signed __int128 src)
>> +{
>> + __builtin_vec_xst_trunc (src, 0, dst);
>> +}
>>
>>
[PING^6][PATCH v2] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]
Ping * 6
Please review!
On 21/03/24 6:21 pm, jeevitha wrote:
> Hi All,
>
> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>
> PTImode assists in generating even/odd register pairs on 128 bits. When the
> user
> specifies PTImode as an attribute, it breaks because there is no internal
> type
> to handle this mode. To address this, we have created a tree node with dummy
> type
> to handle PTImode. We are not documenting this dummy type since users are not
> allowed to use this type externally.
>
> 2024-03-21 Jeevitha Palanisamy
>
> gcc/
> PR target/110411
> * config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add
> RS6000_BTI_INTPTI.
> * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Add node
> for PTImode type.
>
> gcc/testsuite/
> PR target/106895
> * gcc.target/powerpc/pr106895.c: New testcase.
>
> diff --git a/gcc/config/rs6000/rs6000-builtin.cc
> b/gcc/config/rs6000/rs6000-builtin.cc
> index 6698274031b..f553c72779e 100644
> --- a/gcc/config/rs6000/rs6000-builtin.cc
> +++ b/gcc/config/rs6000/rs6000-builtin.cc
> @@ -756,6 +756,15 @@ rs6000_init_builtins (void)
>else
> ieee128_float_type_node = NULL_TREE;
>
> + /* PTImode to get even/odd register pairs. */
> + intPTI_type_internal_node = make_node(INTEGER_TYPE);
> + TYPE_PRECISION (intPTI_type_internal_node) = GET_MODE_BITSIZE (PTImode);
> + layout_type (intPTI_type_internal_node);
> + SET_TYPE_MODE (intPTI_type_internal_node, PTImode);
> + t = build_qualified_type (intPTI_type_internal_node, TYPE_QUAL_CONST);
> + lang_hooks.types.register_builtin_type (intPTI_type_internal_node,
> + "__dummypti");
> +
>/* Vector pair and vector quad support. */
>vector_pair_type_node = make_node (OPAQUE_TYPE);
>SET_TYPE_MODE (vector_pair_type_node, OOmode);
> diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
> index 68bc45d65ba..b6078077b20 100644
> --- a/gcc/config/rs6000/rs6000.h
> +++ b/gcc/config/rs6000/rs6000.h
> @@ -2302,6 +2302,7 @@ enum rs6000_builtin_type_index
>RS6000_BTI_ptr_vector_quad,
>RS6000_BTI_ptr_long_long,
>RS6000_BTI_ptr_long_long_unsigned,
> + RS6000_BTI_INTPTI,
>RS6000_BTI_MAX
> };
>
> @@ -2346,6 +2347,7 @@ enum rs6000_builtin_type_index
> #define uintDI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_UINTDI])
> #define intTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_INTTI])
> #define uintTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_UINTTI])
> +#define intPTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_INTPTI])
> #define float_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_float])
> #define double_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_double])
> #define long_double_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_long_double])
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr106895.c
> b/gcc/testsuite/gcc.target/powerpc/pr106895.c
> new file mode 100644
> index 000..56547b7fa9d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr106895.c
> @@ -0,0 +1,15 @@
> +/* PR target/106895 */
> +/* { dg-require-effective-target int128 } */
> +/* { dg-options "-O2" } */
> +
> +/* Verify the following generates even/odd register pairs. */
> +
> +typedef __int128 pti __attribute__((mode(PTI)));
> +
> +void
> +set128 (pti val, pti *mem)
> +{
> +asm("stq %1,%0" : "=m"(*mem) : "r"(val));
> +}
> +
> +/* { dg-final { scan-assembler "stq \[123\]?\[02468\]" } } */
>
[PATCH v3] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
PTImode assists in generating even/odd register pairs on 128 bits. When the user
specifies PTImode as an attribute, it breaks because there is no internal type
to handle this mode. To fix this, we have created a intPTI_type_internal_node to
handle PTImode. We are not documenting this __pti_internal type, since users
are not encouraged to use this type externally.
2024-10-14 Jeevitha Palanisamy
gcc/
PR target/106895
* config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add
RS6000_BTI_INTPTI.
* config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Add node for
PTImode type.
gcc/testsuite/
PR target/106895
* gcc.target/powerpc/pr106895.c: New testcase.
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 9bdbae1ecf9..baf17f3b28a 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -756,6 +756,15 @@ rs6000_init_builtins (void)
else
ieee128_float_type_node = NULL_TREE;
+ /* PTImode to get even/odd register pairs. */
+ intPTI_type_internal_node = make_node(INTEGER_TYPE);
+ TYPE_PRECISION (intPTI_type_internal_node) = GET_MODE_BITSIZE (PTImode);
+ layout_type (intPTI_type_internal_node);
+ SET_TYPE_MODE (intPTI_type_internal_node, PTImode);
+ t = build_qualified_type (intPTI_type_internal_node, TYPE_QUAL_CONST);
+ lang_hooks.types.register_builtin_type (intPTI_type_internal_node,
+ "__pti_internal");
+
/* Vector pair and vector quad support. */
vector_pair_type_node = make_node (OPAQUE_TYPE);
SET_TYPE_MODE (vector_pair_type_node, OOmode);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index d460eb06544..1612b3e2fcd 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2288,6 +2288,7 @@ enum rs6000_builtin_type_index
RS6000_BTI_ptr_vector_quad,
RS6000_BTI_ptr_long_long,
RS6000_BTI_ptr_long_long_unsigned,
+ RS6000_BTI_INTPTI,
RS6000_BTI_MAX
};
@@ -2332,6 +2333,7 @@ enum rs6000_builtin_type_index
#define uintDI_type_internal_node
(rs6000_builtin_types[RS6000_BTI_UINTDI])
#define intTI_type_internal_node
(rs6000_builtin_types[RS6000_BTI_INTTI])
#define uintTI_type_internal_node
(rs6000_builtin_types[RS6000_BTI_UINTTI])
+#define intPTI_type_internal_node
(rs6000_builtin_types[RS6000_BTI_INTPTI])
#define float_type_internal_node
(rs6000_builtin_types[RS6000_BTI_float])
#define double_type_internal_node
(rs6000_builtin_types[RS6000_BTI_double])
#define long_double_type_internal_node
(rs6000_builtin_types[RS6000_BTI_long_double])
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106895.c
b/gcc/testsuite/gcc.target/powerpc/pr106895.c
new file mode 100644
index 000..88516c5a426
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr106895.c
@@ -0,0 +1,17 @@
+/* PR target/106895 */
+/* { dg-do assemble } */
+/* { dg-require-effective-target int128 } */
+/* { dg-options "-O2 -save-temps" } */
+
+/* Verify the following generates even/odd register pairs. */
+
+typedef __int128 pti __attribute__((mode(PTI)));
+
+void
+set128 (pti val, pti *mem)
+{
+asm("stq %1,%0" : "=m"(*mem) : "r"(val));
+}
+
+/* { dg-final { scan-assembler {\mstq\M} } } */
+
[PATCH] rs6000: Correct the function code for _AMO_LD_DEC_BOUNDED
Hi All,
Corrected the function code for the Atomic Memory Operation "Fetch and Decrement
Bounded", changing it from 0x1A to 0x1C.
2024-10-14 Jeevitha Palanisamy
gcc/
* config/rs6000/amo.h (enum _AMO_LD): Correct the function code for
_AMO_LD_DEC_BOUNDED.
diff --git a/gcc/config/rs6000/amo.h b/gcc/config/rs6000/amo.h
index 6b9e4e088b9..1303c9d9dab 100644
--- a/gcc/config/rs6000/amo.h
+++ b/gcc/config/rs6000/amo.h
@@ -46,7 +46,7 @@ enum _AMO_LD {
_AMO_LD_CS_NE= 0x10, /* Compare and Swap Not Equal.
*/
_AMO_LD_INC_BOUNDED = 0x18, /* Fetch and Increment Bounded. */
_AMO_LD_INC_EQUAL= 0x19, /* Fetch and Increment Equal. */
- _AMO_LD_DEC_BOUNDED = 0x1A /* Fetch and Decrement Bounded. */
+ _AMO_LD_DEC_BOUNDED = 0x1C /* Fetch and Decrement Bounded. */
};
/* Implementation of the simple LWAT/LDAT operations that take one register and
[PATCH] testsuite: Simplify target test and dg-options for AMO tests
Hi All,
Removed powerpc*-*-* from the target test as it is always true. Simplified
options by removing -mpower9-misc and -mvsx, which are enabled by default with
-mdejagnu-cpu=power9. The has_arch_pwr9 check is also true with
-mdejagnu-cpu=power9, so it has been removed.
2024-10-15 Jeevitha Palanisamy
gcc/testsuite/
* gcc.target/powerpc/amo1.c: Removed powerpc*-*-* from the target and
simplified dg-options.
* gcc.target/powerpc/amo2.c: Simplified dg-options and added powerpc_vsx
target check.
diff --git a/gcc/testsuite/gcc.target/powerpc/amo1.c
b/gcc/testsuite/gcc.target/powerpc/amo1.c
index c5af373b4e9..9a981cd4219 100644
--- a/gcc/testsuite/gcc.target/powerpc/amo1.c
+++ b/gcc/testsuite/gcc.target/powerpc/amo1.c
@@ -1,6 +1,5 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-options "-mvsx -mpower9-misc -O2" } */
-/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 }
} } */
+/* { dg-do compile { target { lp64 } } } */
+/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
/* { dg-require-effective-target powerpc_vsx } */
/* Verify P9 atomic memory operations. */
diff --git a/gcc/testsuite/gcc.target/powerpc/amo2.c
b/gcc/testsuite/gcc.target/powerpc/amo2.c
index 592f0fb3f92..9e4ff0ce064 100644
--- a/gcc/testsuite/gcc.target/powerpc/amo2.c
+++ b/gcc/testsuite/gcc.target/powerpc/amo2.c
@@ -1,6 +1,6 @@
/* { dg-do run { target { powerpc*-*-linux* && { lp64 && p9vector_hw } } } } */
-/* { dg-options "-O2 -mvsx -mpower9-misc" } */
-/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 }
} } */
+/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
+/* { dg-require-effective-target powerpc_vsx } */
#include
#include
[PING^1][PATCH] testsuite: Simplify target test and dg-options for AMO tests
Ping!
please review.
Thanks & Regards
Jeevitha
On 15/10/24 12:49 pm, jeevitha wrote:
> Hi All,
>
> Removed powerpc*-*-* from the target test as it is always true. Simplified
> options by removing -mpower9-misc and -mvsx, which are enabled by default with
> -mdejagnu-cpu=power9. The has_arch_pwr9 check is also true with
> -mdejagnu-cpu=power9, so it has been removed.
>
> 2024-10-15 Jeevitha Palanisamy
>
> gcc/testsuite/
>
> * gcc.target/powerpc/amo1.c: Removed powerpc*-*-* from the target and
> simplified dg-options.
> * gcc.target/powerpc/amo2.c: Simplified dg-options and added powerpc_vsx
> target check.
>
>
> diff --git a/gcc/testsuite/gcc.target/powerpc/amo1.c
> b/gcc/testsuite/gcc.target/powerpc/amo1.c
> index c5af373b4e9..9a981cd4219 100644
> --- a/gcc/testsuite/gcc.target/powerpc/amo1.c
> +++ b/gcc/testsuite/gcc.target/powerpc/amo1.c
> @@ -1,6 +1,5 @@
> -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
> -/* { dg-options "-mvsx -mpower9-misc -O2" } */
> -/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9
> } } } */
> +/* { dg-do compile { target { lp64 } } } */
> +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
> /* { dg-require-effective-target powerpc_vsx } */
>
> /* Verify P9 atomic memory operations. */
> diff --git a/gcc/testsuite/gcc.target/powerpc/amo2.c
> b/gcc/testsuite/gcc.target/powerpc/amo2.c
> index 592f0fb3f92..9e4ff0ce064 100644
> --- a/gcc/testsuite/gcc.target/powerpc/amo2.c
> +++ b/gcc/testsuite/gcc.target/powerpc/amo2.c
> @@ -1,6 +1,6 @@
> /* { dg-do run { target { powerpc*-*-linux* && { lp64 && p9vector_hw } } } }
> */
> -/* { dg-options "-O2 -mvsx -mpower9-misc" } */
> -/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9
> } } } */
> +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
> +/* { dg-require-effective-target powerpc_vsx } */
>
> #include
> #include
>
>
>
[PING^1][PATCH v3] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]
Ping!
please review.
Thanks & Regards
Jeevitha
On 14/10/24 5:16 pm, jeevitha wrote:
> Hi All,
>
> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>
> PTImode assists in generating even/odd register pairs on 128 bits. When the
> user
> specifies PTImode as an attribute, it breaks because there is no internal type
> to handle this mode. To fix this, we have created a intPTI_type_internal_node
> to
> handle PTImode. We are not documenting this __pti_internal type, since users
> are not encouraged to use this type externally.
>
> 2024-10-14 Jeevitha Palanisamy
>
> gcc/
> PR target/106895
> * config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add
> RS6000_BTI_INTPTI.
> * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Add node for
> PTImode type.
>
> gcc/testsuite/
> PR target/106895
> * gcc.target/powerpc/pr106895.c: New testcase.
>
> diff --git a/gcc/config/rs6000/rs6000-builtin.cc
> b/gcc/config/rs6000/rs6000-builtin.cc
> index 9bdbae1ecf9..baf17f3b28a 100644
> --- a/gcc/config/rs6000/rs6000-builtin.cc
> +++ b/gcc/config/rs6000/rs6000-builtin.cc
> @@ -756,6 +756,15 @@ rs6000_init_builtins (void)
>else
> ieee128_float_type_node = NULL_TREE;
>
> + /* PTImode to get even/odd register pairs. */
> + intPTI_type_internal_node = make_node(INTEGER_TYPE);
> + TYPE_PRECISION (intPTI_type_internal_node) = GET_MODE_BITSIZE (PTImode);
> + layout_type (intPTI_type_internal_node);
> + SET_TYPE_MODE (intPTI_type_internal_node, PTImode);
> + t = build_qualified_type (intPTI_type_internal_node, TYPE_QUAL_CONST);
> + lang_hooks.types.register_builtin_type (intPTI_type_internal_node,
> + "__pti_internal");
> +
>/* Vector pair and vector quad support. */
>vector_pair_type_node = make_node (OPAQUE_TYPE);
>SET_TYPE_MODE (vector_pair_type_node, OOmode);
> diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
> index d460eb06544..1612b3e2fcd 100644
> --- a/gcc/config/rs6000/rs6000.h
> +++ b/gcc/config/rs6000/rs6000.h
> @@ -2288,6 +2288,7 @@ enum rs6000_builtin_type_index
>RS6000_BTI_ptr_vector_quad,
>RS6000_BTI_ptr_long_long,
>RS6000_BTI_ptr_long_long_unsigned,
> + RS6000_BTI_INTPTI,
>RS6000_BTI_MAX
> };
>
> @@ -2332,6 +2333,7 @@ enum rs6000_builtin_type_index
> #define uintDI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_UINTDI])
> #define intTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_INTTI])
> #define uintTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_UINTTI])
> +#define intPTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_INTPTI])
> #define float_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_float])
> #define double_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_double])
> #define long_double_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_long_double])
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr106895.c
> b/gcc/testsuite/gcc.target/powerpc/pr106895.c
> new file mode 100644
> index 000..88516c5a426
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr106895.c
> @@ -0,0 +1,17 @@
> +/* PR target/106895 */
> +/* { dg-do assemble } */
> +/* { dg-require-effective-target int128 } */
> +/* { dg-options "-O2 -save-temps" } */
> +
> +/* Verify the following generates even/odd register pairs. */
> +
> +typedef __int128 pti __attribute__((mode(PTI)));
> +
> +void
> +set128 (pti val, pti *mem)
> +{
> +asm("stq %1,%0" : "=m"(*mem) : "r"(val));
> +}
> +
> +/* { dg-final { scan-assembler {\mstq\M} } } */
> +
>
>
>
[PING^7][PATCH v2] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]
Ping * 7
Please review!
On 21/03/24 6:21 pm, jeevitha wrote:
> Hi All,
>
> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>
> PTImode assists in generating even/odd register pairs on 128 bits. When the
> user
> specifies PTImode as an attribute, it breaks because there is no internal
> type
> to handle this mode. To address this, we have created a tree node with dummy
> type
> to handle PTImode. We are not documenting this dummy type since users are not
> allowed to use this type externally.
>
> 2024-03-21 Jeevitha Palanisamy
>
> gcc/
> PR target/110411
> * config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add
> RS6000_BTI_INTPTI.
> * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Add node
> for PTImode type.
>
> gcc/testsuite/
> PR target/106895
> * gcc.target/powerpc/pr106895.c: New testcase.
>
> diff --git a/gcc/config/rs6000/rs6000-builtin.cc
> b/gcc/config/rs6000/rs6000-builtin.cc
> index 6698274031b..f553c72779e 100644
> --- a/gcc/config/rs6000/rs6000-builtin.cc
> +++ b/gcc/config/rs6000/rs6000-builtin.cc
> @@ -756,6 +756,15 @@ rs6000_init_builtins (void)
>else
> ieee128_float_type_node = NULL_TREE;
>
> + /* PTImode to get even/odd register pairs. */
> + intPTI_type_internal_node = make_node(INTEGER_TYPE);
> + TYPE_PRECISION (intPTI_type_internal_node) = GET_MODE_BITSIZE (PTImode);
> + layout_type (intPTI_type_internal_node);
> + SET_TYPE_MODE (intPTI_type_internal_node, PTImode);
> + t = build_qualified_type (intPTI_type_internal_node, TYPE_QUAL_CONST);
> + lang_hooks.types.register_builtin_type (intPTI_type_internal_node,
> + "__dummypti");
> +
>/* Vector pair and vector quad support. */
>vector_pair_type_node = make_node (OPAQUE_TYPE);
>SET_TYPE_MODE (vector_pair_type_node, OOmode);
> diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
> index 68bc45d65ba..b6078077b20 100644
> --- a/gcc/config/rs6000/rs6000.h
> +++ b/gcc/config/rs6000/rs6000.h
> @@ -2302,6 +2302,7 @@ enum rs6000_builtin_type_index
>RS6000_BTI_ptr_vector_quad,
>RS6000_BTI_ptr_long_long,
>RS6000_BTI_ptr_long_long_unsigned,
> + RS6000_BTI_INTPTI,
>RS6000_BTI_MAX
> };
>
> @@ -2346,6 +2347,7 @@ enum rs6000_builtin_type_index
> #define uintDI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_UINTDI])
> #define intTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_INTTI])
> #define uintTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_UINTTI])
> +#define intPTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_INTPTI])
> #define float_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_float])
> #define double_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_double])
> #define long_double_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_long_double])
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr106895.c
> b/gcc/testsuite/gcc.target/powerpc/pr106895.c
> new file mode 100644
> index 000..56547b7fa9d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr106895.c
> @@ -0,0 +1,15 @@
> +/* PR target/106895 */
> +/* { dg-require-effective-target int128 } */
> +/* { dg-options "-O2" } */
> +
> +/* Verify the following generates even/odd register pairs. */
> +
> +typedef __int128 pti __attribute__((mode(PTI)));
> +
> +void
> +set128 (pti val, pti *mem)
> +{
> +asm("stq %1,%0" : "=m"(*mem) : "r"(val));
> +}
> +
> +/* { dg-final { scan-assembler "stq \[123\]?\[02468\]" } } */
>
[PING^2][PATCH] testsuite: Simplify target test and dg-options for AMO tests
Ping!
please review.
Thanks & Regards
Jeevitha
On 15/10/24 12:49 pm, jeevitha wrote:
> Hi All,
>
> Removed powerpc*-*-* from the target test as it is always true. Simplified
> options by removing -mpower9-misc and -mvsx, which are enabled by default with
> -mdejagnu-cpu=power9. The has_arch_pwr9 check is also true with
> -mdejagnu-cpu=power9, so it has been removed.
>
> 2024-10-15 Jeevitha Palanisamy
>
> gcc/testsuite/
>
> * gcc.target/powerpc/amo1.c: Removed powerpc*-*-* from the target and
> simplified dg-options.
> * gcc.target/powerpc/amo2.c: Simplified dg-options and added powerpc_vsx
> target check.
>
>
> diff --git a/gcc/testsuite/gcc.target/powerpc/amo1.c
> b/gcc/testsuite/gcc.target/powerpc/amo1.c
> index c5af373b4e9..9a981cd4219 100644
> --- a/gcc/testsuite/gcc.target/powerpc/amo1.c
> +++ b/gcc/testsuite/gcc.target/powerpc/amo1.c
> @@ -1,6 +1,5 @@
> -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
> -/* { dg-options "-mvsx -mpower9-misc -O2" } */
> -/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9
> } } } */
> +/* { dg-do compile { target { lp64 } } } */
> +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
> /* { dg-require-effective-target powerpc_vsx } */
>
> /* Verify P9 atomic memory operations. */
> diff --git a/gcc/testsuite/gcc.target/powerpc/amo2.c
> b/gcc/testsuite/gcc.target/powerpc/amo2.c
> index 592f0fb3f92..9e4ff0ce064 100644
> --- a/gcc/testsuite/gcc.target/powerpc/amo2.c
> +++ b/gcc/testsuite/gcc.target/powerpc/amo2.c
> @@ -1,6 +1,6 @@
> /* { dg-do run { target { powerpc*-*-linux* && { lp64 && p9vector_hw } } } }
> */
> -/* { dg-options "-O2 -mvsx -mpower9-misc" } */
> -/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9
> } } } */
> +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
> +/* { dg-require-effective-target powerpc_vsx } */
>
> #include
> #include
>
>
>
[PING^3][PATCH v3] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]
Ping!
please review.
Thanks & Regards
Jeevitha
On 14/10/24 5:16 pm, jeevitha wrote:
> Hi All,
>
> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>
> PTImode assists in generating even/odd register pairs on 128 bits. When the
> user
> specifies PTImode as an attribute, it breaks because there is no internal type
> to handle this mode. To fix this, we have created a intPTI_type_internal_node
> to
> handle PTImode. We are not documenting this __pti_internal type, since users
> are not encouraged to use this type externally.
>
> 2024-10-14 Jeevitha Palanisamy
>
> gcc/
> PR target/106895
> * config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add
> RS6000_BTI_INTPTI.
> * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Add node for
> PTImode type.
>
> gcc/testsuite/
> PR target/106895
> * gcc.target/powerpc/pr106895.c: New testcase.
>
> diff --git a/gcc/config/rs6000/rs6000-builtin.cc
> b/gcc/config/rs6000/rs6000-builtin.cc
> index 9bdbae1ecf9..baf17f3b28a 100644
> --- a/gcc/config/rs6000/rs6000-builtin.cc
> +++ b/gcc/config/rs6000/rs6000-builtin.cc
> @@ -756,6 +756,15 @@ rs6000_init_builtins (void)
>else
> ieee128_float_type_node = NULL_TREE;
>
> + /* PTImode to get even/odd register pairs. */
> + intPTI_type_internal_node = make_node(INTEGER_TYPE);
> + TYPE_PRECISION (intPTI_type_internal_node) = GET_MODE_BITSIZE (PTImode);
> + layout_type (intPTI_type_internal_node);
> + SET_TYPE_MODE (intPTI_type_internal_node, PTImode);
> + t = build_qualified_type (intPTI_type_internal_node, TYPE_QUAL_CONST);
> + lang_hooks.types.register_builtin_type (intPTI_type_internal_node,
> + "__pti_internal");
> +
>/* Vector pair and vector quad support. */
>vector_pair_type_node = make_node (OPAQUE_TYPE);
>SET_TYPE_MODE (vector_pair_type_node, OOmode);
> diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
> index d460eb06544..1612b3e2fcd 100644
> --- a/gcc/config/rs6000/rs6000.h
> +++ b/gcc/config/rs6000/rs6000.h
> @@ -2288,6 +2288,7 @@ enum rs6000_builtin_type_index
>RS6000_BTI_ptr_vector_quad,
>RS6000_BTI_ptr_long_long,
>RS6000_BTI_ptr_long_long_unsigned,
> + RS6000_BTI_INTPTI,
>RS6000_BTI_MAX
> };
>
> @@ -2332,6 +2333,7 @@ enum rs6000_builtin_type_index
> #define uintDI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_UINTDI])
> #define intTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_INTTI])
> #define uintTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_UINTTI])
> +#define intPTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_INTPTI])
> #define float_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_float])
> #define double_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_double])
> #define long_double_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_long_double])
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr106895.c
> b/gcc/testsuite/gcc.target/powerpc/pr106895.c
> new file mode 100644
> index 000..88516c5a426
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr106895.c
> @@ -0,0 +1,17 @@
> +/* PR target/106895 */
> +/* { dg-do assemble } */
> +/* { dg-require-effective-target int128 } */
> +/* { dg-options "-O2 -save-temps" } */
> +
> +/* Verify the following generates even/odd register pairs. */
> +
> +typedef __int128 pti __attribute__((mode(PTI)));
> +
> +void
> +set128 (pti val, pti *mem)
> +{
> +asm("stq %1,%0" : "=m"(*mem) : "r"(val));
> +}
> +
> +/* { dg-final { scan-assembler {\mstq\M} } } */
> +
>
>
>
[PING^3][PATCH] testsuite: Simplify target test and dg-options for AMO tests
Ping!
please review.
Thanks & Regards
Jeevitha
On 15/10/24 12:49 pm, jeevitha wrote:
> Hi All,
>
> Removed powerpc*-*-* from the target test as it is always true. Simplified
> options by removing -mpower9-misc and -mvsx, which are enabled by default with
> -mdejagnu-cpu=power9. The has_arch_pwr9 check is also true with
> -mdejagnu-cpu=power9, so it has been removed.
>
> 2024-10-15 Jeevitha Palanisamy
>
> gcc/testsuite/
>
> * gcc.target/powerpc/amo1.c: Removed powerpc*-*-* from the target and
> simplified dg-options.
> * gcc.target/powerpc/amo2.c: Simplified dg-options and added powerpc_vsx
> target check.
>
>
> diff --git a/gcc/testsuite/gcc.target/powerpc/amo1.c
> b/gcc/testsuite/gcc.target/powerpc/amo1.c
> index c5af373b4e9..9a981cd4219 100644
> --- a/gcc/testsuite/gcc.target/powerpc/amo1.c
> +++ b/gcc/testsuite/gcc.target/powerpc/amo1.c
> @@ -1,6 +1,5 @@
> -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
> -/* { dg-options "-mvsx -mpower9-misc -O2" } */
> -/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9
> } } } */
> +/* { dg-do compile { target { lp64 } } } */
> +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
> /* { dg-require-effective-target powerpc_vsx } */
>
> /* Verify P9 atomic memory operations. */
> diff --git a/gcc/testsuite/gcc.target/powerpc/amo2.c
> b/gcc/testsuite/gcc.target/powerpc/amo2.c
> index 592f0fb3f92..9e4ff0ce064 100644
> --- a/gcc/testsuite/gcc.target/powerpc/amo2.c
> +++ b/gcc/testsuite/gcc.target/powerpc/amo2.c
> @@ -1,6 +1,6 @@
> /* { dg-do run { target { powerpc*-*-linux* && { lp64 && p9vector_hw } } } }
> */
> -/* { dg-options "-O2 -mvsx -mpower9-misc" } */
> -/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9
> } } } */
> +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
> +/* { dg-require-effective-target powerpc_vsx } */
>
> #include
> #include
>
>
>
[PING^2][PATCH v3] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]
Ping!
please review.
Thanks & Regards
Jeevitha
On 14/10/24 5:16 pm, jeevitha wrote:
> Hi All,
>
> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>
> PTImode assists in generating even/odd register pairs on 128 bits. When the
> user
> specifies PTImode as an attribute, it breaks because there is no internal type
> to handle this mode. To fix this, we have created a intPTI_type_internal_node
> to
> handle PTImode. We are not documenting this __pti_internal type, since users
> are not encouraged to use this type externally.
>
> 2024-10-14 Jeevitha Palanisamy
>
> gcc/
> PR target/106895
> * config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add
> RS6000_BTI_INTPTI.
> * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Add node for
> PTImode type.
>
> gcc/testsuite/
> PR target/106895
> * gcc.target/powerpc/pr106895.c: New testcase.
>
> diff --git a/gcc/config/rs6000/rs6000-builtin.cc
> b/gcc/config/rs6000/rs6000-builtin.cc
> index 9bdbae1ecf9..baf17f3b28a 100644
> --- a/gcc/config/rs6000/rs6000-builtin.cc
> +++ b/gcc/config/rs6000/rs6000-builtin.cc
> @@ -756,6 +756,15 @@ rs6000_init_builtins (void)
>else
> ieee128_float_type_node = NULL_TREE;
>
> + /* PTImode to get even/odd register pairs. */
> + intPTI_type_internal_node = make_node(INTEGER_TYPE);
> + TYPE_PRECISION (intPTI_type_internal_node) = GET_MODE_BITSIZE (PTImode);
> + layout_type (intPTI_type_internal_node);
> + SET_TYPE_MODE (intPTI_type_internal_node, PTImode);
> + t = build_qualified_type (intPTI_type_internal_node, TYPE_QUAL_CONST);
> + lang_hooks.types.register_builtin_type (intPTI_type_internal_node,
> + "__pti_internal");
> +
>/* Vector pair and vector quad support. */
>vector_pair_type_node = make_node (OPAQUE_TYPE);
>SET_TYPE_MODE (vector_pair_type_node, OOmode);
> diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
> index d460eb06544..1612b3e2fcd 100644
> --- a/gcc/config/rs6000/rs6000.h
> +++ b/gcc/config/rs6000/rs6000.h
> @@ -2288,6 +2288,7 @@ enum rs6000_builtin_type_index
>RS6000_BTI_ptr_vector_quad,
>RS6000_BTI_ptr_long_long,
>RS6000_BTI_ptr_long_long_unsigned,
> + RS6000_BTI_INTPTI,
>RS6000_BTI_MAX
> };
>
> @@ -2332,6 +2333,7 @@ enum rs6000_builtin_type_index
> #define uintDI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_UINTDI])
> #define intTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_INTTI])
> #define uintTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_UINTTI])
> +#define intPTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_INTPTI])
> #define float_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_float])
> #define double_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_double])
> #define long_double_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_long_double])
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr106895.c
> b/gcc/testsuite/gcc.target/powerpc/pr106895.c
> new file mode 100644
> index 000..88516c5a426
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr106895.c
> @@ -0,0 +1,17 @@
> +/* PR target/106895 */
> +/* { dg-do assemble } */
> +/* { dg-require-effective-target int128 } */
> +/* { dg-options "-O2 -save-temps" } */
> +
> +/* Verify the following generates even/odd register pairs. */
> +
> +typedef __int128 pti __attribute__((mode(PTI)));
> +
> +void
> +set128 (pti val, pti *mem)
> +{
> +asm("stq %1,%0" : "=m"(*mem) : "r"(val));
> +}
> +
> +/* { dg-final { scan-assembler {\mstq\M} } } */
> +
>
>
>
[PING^5] [PATCH] testsuite: Simplify target test and dg-options for AMO tests
Ping!
please review.
Thanks & Regards
Jeevitha
On 15/10/24 12:49 pm, jeevitha wrote:
> Hi All,
>
> Removed powerpc*-*-* from the target test as it is always true. Simplified
> options by removing -mpower9-misc and -mvsx, which are enabled by default with
> -mdejagnu-cpu=power9. The has_arch_pwr9 check is also true with
> -mdejagnu-cpu=power9, so it has been removed.
>
> 2024-10-15 Jeevitha Palanisamy
>
> gcc/testsuite/
>
> * gcc.target/powerpc/amo1.c: Removed powerpc*-*-* from the target and
> simplified dg-options.
> * gcc.target/powerpc/amo2.c: Simplified dg-options and added powerpc_vsx
> target check.
>
>
> diff --git a/gcc/testsuite/gcc.target/powerpc/amo1.c
> b/gcc/testsuite/gcc.target/powerpc/amo1.c
> index c5af373b4e9..9a981cd4219 100644
> --- a/gcc/testsuite/gcc.target/powerpc/amo1.c
> +++ b/gcc/testsuite/gcc.target/powerpc/amo1.c
> @@ -1,6 +1,5 @@
> -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
> -/* { dg-options "-mvsx -mpower9-misc -O2" } */
> -/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9
> } } } */
> +/* { dg-do compile { target { lp64 } } } */
> +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
> /* { dg-require-effective-target powerpc_vsx } */
>
> /* Verify P9 atomic memory operations. */
> diff --git a/gcc/testsuite/gcc.target/powerpc/amo2.c
> b/gcc/testsuite/gcc.target/powerpc/amo2.c
> index 592f0fb3f92..9e4ff0ce064 100644
> --- a/gcc/testsuite/gcc.target/powerpc/amo2.c
> +++ b/gcc/testsuite/gcc.target/powerpc/amo2.c
> @@ -1,6 +1,6 @@
> /* { dg-do run { target { powerpc*-*-linux* && { lp64 && p9vector_hw } } } }
> */
> -/* { dg-options "-O2 -mvsx -mpower9-misc" } */
> -/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9
> } } } */
> +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
> +/* { dg-require-effective-target powerpc_vsx } */
>
> #include
> #include
>
>
>
[PATCH] rs6000: Adding missed ISA 3.0 atomic memory operation instructions.
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
Changes to amo.h include the addition of the following load atomic operations:
Compare and Swap Not Equal, Fetch and Increment Bounded, Fetch and Increment
Equal, and Fetch and Decrement Bounded. Additionally, Store Twin is added for
store atomic operations.
2024-01-08 Peter Bergner
gcc/:
* config/rs6000/amo.h: Add missing atomic memory operations.
* doc/extend.texi (PowerPC Atomic Memory Operation Functions):
Document new functions.
gcc/testsuite/:
* gcc.target/powerpc/amo3.c: New test.
* gcc.target/powerpc/amo4.c: Likewise.
* gcc.target/powerpc/amo5.c: Likewise.
* gcc.target/powerpc/amo6.c: Likewise.
* gcc.target/powerpc/amo7.c: Likewise.
Co-authored-by: Jeevitha Palanisamy
diff --git a/gcc/config/rs6000/amo.h b/gcc/config/rs6000/amo.h
index 25ab1c7b4c4..10960208d31 100644
--- a/gcc/config/rs6000/amo.h
+++ b/gcc/config/rs6000/amo.h
@@ -71,6 +71,64 @@ NAME (TYPE *_PTR, TYPE _VALUE)
\
return _RET; \
}
+/* Implementation of the LWAT/LDAT operations that take two input registers
+ and modify one word or double-word of memory and return the value that was
+ previously in the memory location. The destination and two source
+ registers are encoded with only one register number, so we need three
+ consecutive GPR registers and there is no C/C++ type that will give
+ us that, so we have to use register asm variables to achieve that.
+
+ The LWAT/LDAT opcode requires the address to be a single register,
+ and that points to a suitably aligned memory location. Asm volatile
+ is used to prevent the optimizer from moving the operation. */
+
+#define _AMO_LD_CMPSWP(NAME, TYPE, OPCODE, FC) \
+static __inline__ TYPE \
+NAME (TYPE *_PTR, TYPE _COND, TYPE _VALUE) \
+{ \
+ register TYPE _ret asm ("r8"); \
+ register TYPE _cond asm ("r9") = _COND; \
+ register TYPE _value asm ("r10") = _VALUE; \
+ __asm__ __volatile__ (OPCODE " %[ret],%P[addr],%[code]" \
+ : [addr] "+Q" (_PTR[0]), [ret] "=r" (_ret) \
+ : "r" (_cond), "r" (_value), [code] "n" (FC)); \
+ return _ret; \
+}
+
+/* Implementation of the LWAT/LDAT fetch and increment operations.
+
+ The LWAT/LDAT opcode requires the address to be a single register that
+ points to a suitably aligned memory location. Asm volatile is used to
+ prevent the optimizer from moving the operation. */
+
+#define _AMO_LD_INCREMENT(NAME, TYPE, OPCODE, FC) \
+static __inline__ TYPE \
+NAME (TYPE *_PTR) \
+{ \
+ TYPE _RET; \
+ __asm__ volatile (OPCODE " %[ret],%P[addr],%[code]\n"
\
+ : [addr] "+Q" (_PTR[0]), [ret] "=r" (_RET) \
+ : "Q" (*(TYPE (*)[2]) _PTR), [code] "n" (FC)); \
+ return _RET; \
+}
+
+/* Implementation of the LWAT/LDAT fetch and decrement operations.
+
+ The LWAT/LDAT opcode requires the address to be a single register that
+ points to a suitably aligned memory location. Asm volatile is used to
+ prevent the optimizer from moving the operation. */
+
+#define _AMO_LD_DECREMENT(NAME, TYPE, OPCODE, FC) \
+static __inline__ TYPE \
+NAME (TYPE *_PTR) \
+{ \
+ TYPE _RET; \
+ __asm__ volatile (OPCODE " %[ret],%P[addr],%[code]\n"
\
+ : [addr] "+Q" (_PTR[1]), [ret] "=r" (_RET) \
+ : "Q" (*(TYPE (*)[2]) (_PTR)), [code] "n" (FC));\
+ return _RET; \
+}
+
_AMO_LD_SIMPLE (amo_lwat_add, uint32_t, "lwat", _AMO_LD_ADD)
_AMO_LD_SIMPLE (amo_lwat_xor, uint32_t, "lwat", _AMO_LD_XOR)
_AMO_LD_SIMPLE (amo_lwat_ior, uint32_t, "lwat", _AMO_L
[PING^4][PATCH] testsuite: Simplify target test and dg-options for AMO tests
Ping!
please review.
Thanks & Regards
Jeevitha
On 02/12/24 2:04 pm, jeevitha wrote:
> Ping!
>
> please review.
>
> Thanks & Regards
> Jeevitha
>
> On 15/10/24 12:49 pm, jeevitha wrote:
>> Hi All,
>>
>> Removed powerpc*-*-* from the target test as it is always true. Simplified
>> options by removing -mpower9-misc and -mvsx, which are enabled by default
>> with
>> -mdejagnu-cpu=power9. The has_arch_pwr9 check is also true with
>> -mdejagnu-cpu=power9, so it has been removed.
>>
>> 2024-10-15 Jeevitha Palanisamy
>>
>> gcc/testsuite/
>>
>> * gcc.target/powerpc/amo1.c: Removed powerpc*-*-* from the target and
>> simplified dg-options.
>> * gcc.target/powerpc/amo2.c: Simplified dg-options and added powerpc_vsx
>> target check.
>>
>>
>> diff --git a/gcc/testsuite/gcc.target/powerpc/amo1.c
>> b/gcc/testsuite/gcc.target/powerpc/amo1.c
>> index c5af373b4e9..9a981cd4219 100644
>> --- a/gcc/testsuite/gcc.target/powerpc/amo1.c
>> +++ b/gcc/testsuite/gcc.target/powerpc/amo1.c
>> @@ -1,6 +1,5 @@
>> -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
>> -/* { dg-options "-mvsx -mpower9-misc -O2" } */
>> -/* { dg-additional-options "-mdejagnu-cpu=power9" { target { !
>> has_arch_pwr9 } } } */
>> +/* { dg-do compile { target { lp64 } } } */
>> +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
>> /* { dg-require-effective-target powerpc_vsx } */
>>
>> /* Verify P9 atomic memory operations. */
>> diff --git a/gcc/testsuite/gcc.target/powerpc/amo2.c
>> b/gcc/testsuite/gcc.target/powerpc/amo2.c
>> index 592f0fb3f92..9e4ff0ce064 100644
>> --- a/gcc/testsuite/gcc.target/powerpc/amo2.c
>> +++ b/gcc/testsuite/gcc.target/powerpc/amo2.c
>> @@ -1,6 +1,6 @@
>> /* { dg-do run { target { powerpc*-*-linux* && { lp64 && p9vector_hw } } }
>> } */
>> -/* { dg-options "-O2 -mvsx -mpower9-misc" } */
>> -/* { dg-additional-options "-mdejagnu-cpu=power9" { target { !
>> has_arch_pwr9 } } } */
>> +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
>> +/* { dg-require-effective-target powerpc_vsx } */
>>
>> #include
>> #include
>>
>>
>>
>
[PING^1][PATCH v2] rs6000: Adding missed ISA 3.0 atomic memory operation instructions.
Ping!
please review.
Thanks & Regards
Jeevitha
On 20/02/25 7:41 pm, jeevitha wrote:
> Hi All,
>
> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>
> Changes to amo.h include the addition of the following load atomic operations:
> Compare and Swap Not Equal, Fetch and Increment Bounded, Fetch and Increment
> Equal, and Fetch and Decrement Bounded. Additionally, Store Twin is added for
> store atomic operations.
>
> 2025-02-20 Peter Bergner
>
> gcc/:
> * config/rs6000/amo.h: Add missing atomic memory operations.
> * doc/extend.texi (PowerPC Atomic Memory Operation Functions):
> Document new functions.
>
> gcc/testsuite/:
> * gcc.target/powerpc/amo3.c: New test.
> * gcc.target/powerpc/amo4.c: Likewise.
> * gcc.target/powerpc/amo5.c: Likewise.
> * gcc.target/powerpc/amo6.c: Likewise.
> * gcc.target/powerpc/amo7.c: Likewise.
>
> Co-authored-by: Jeevitha Palanisamy
>
>
> diff --git a/gcc/config/rs6000/amo.h b/gcc/config/rs6000/amo.h
> index 25ab1c7b4c4..10960208d31 100644
> --- a/gcc/config/rs6000/amo.h
> +++ b/gcc/config/rs6000/amo.h
> @@ -71,6 +71,64 @@ NAME (TYPE *_PTR, TYPE _VALUE)
> \
>return _RET;
> \
> }
>
> +/* Implementation of the LWAT/LDAT operations that take two input registers
> + and modify one word or double-word of memory and return the value that was
> + previously in the memory location. The destination and two source
> + registers are encoded with only one register number, so we need three
> + consecutive GPR registers and there is no C/C++ type that will give
> + us that, so we have to use register asm variables to achieve that.
> +
> + The LWAT/LDAT opcode requires the address to be a single register,
> + and that points to a suitably aligned memory location. Asm volatile
> + is used to prevent the optimizer from moving the operation. */
> +
> +#define _AMO_LD_CMPSWP(NAME, TYPE, OPCODE, FC)
> \
> +static __inline__ TYPE
> \
> +NAME (TYPE *_PTR, TYPE _COND, TYPE _VALUE) \
> +{\
> + register TYPE _ret asm ("r8"); \
> + register TYPE _cond asm ("r9") = _COND;\
> + register TYPE _value asm ("r10") = _VALUE; \
> + __asm__ __volatile__ (OPCODE " %[ret],%P[addr],%[code]"\
> + : [addr] "+Q" (_PTR[0]), [ret] "=r" (_ret) \
> + : "r" (_cond), "r" (_value), [code] "n" (FC)); \
> + return _ret;
> \
> +}
> +
> +/* Implementation of the LWAT/LDAT fetch and increment operations.
> +
> + The LWAT/LDAT opcode requires the address to be a single register that
> + points to a suitably aligned memory location. Asm volatile is used to
> + prevent the optimizer from moving the operation. */
> +
> +#define _AMO_LD_INCREMENT(NAME, TYPE, OPCODE, FC)\
> +static __inline__ TYPE
> \
> +NAME (TYPE *_PTR)\
> +{\
> + TYPE _RET; \
> + __asm__ volatile (OPCODE " %[ret],%P[addr],%[code]\n"
> \
> + : [addr] "+Q" (_PTR[0]), [ret] "=r" (_RET) \
> + : "Q" (*(TYPE (*)[2]) _PTR), [code] "n" (FC)); \
> + return _RET;
> \
> +}
> +
> +/* Implementation of the LWAT/LDAT fetch and decrement operations.
> +
> + The LWAT/LDAT opcode requires the address to be a single register that
> + points to a suitably aligned memory location. Asm volatile is used to
> + prevent the optimizer from moving the operation. */
> +
> +#define _AMO_LD_DECREMENT(NAME, TYPE, OPCODE, FC)\
> +static __inline__ TYPE
> \
> +NAME (TYPE *_PTR)\
> +{\
> + TYPE _RET; \
> + __asm_
[PATCH v2] rs6000: Adding missed ISA 3.0 atomic memory operation instructions.
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
Changes to amo.h include the addition of the following load atomic operations:
Compare and Swap Not Equal, Fetch and Increment Bounded, Fetch and Increment
Equal, and Fetch and Decrement Bounded. Additionally, Store Twin is added for
store atomic operations.
2025-02-20 Peter Bergner
gcc/:
* config/rs6000/amo.h: Add missing atomic memory operations.
* doc/extend.texi (PowerPC Atomic Memory Operation Functions):
Document new functions.
gcc/testsuite/:
* gcc.target/powerpc/amo3.c: New test.
* gcc.target/powerpc/amo4.c: Likewise.
* gcc.target/powerpc/amo5.c: Likewise.
* gcc.target/powerpc/amo6.c: Likewise.
* gcc.target/powerpc/amo7.c: Likewise.
Co-authored-by: Jeevitha Palanisamy
diff --git a/gcc/config/rs6000/amo.h b/gcc/config/rs6000/amo.h
index 25ab1c7b4c4..10960208d31 100644
--- a/gcc/config/rs6000/amo.h
+++ b/gcc/config/rs6000/amo.h
@@ -71,6 +71,64 @@ NAME (TYPE *_PTR, TYPE _VALUE)
\
return _RET; \
}
+/* Implementation of the LWAT/LDAT operations that take two input registers
+ and modify one word or double-word of memory and return the value that was
+ previously in the memory location. The destination and two source
+ registers are encoded with only one register number, so we need three
+ consecutive GPR registers and there is no C/C++ type that will give
+ us that, so we have to use register asm variables to achieve that.
+
+ The LWAT/LDAT opcode requires the address to be a single register,
+ and that points to a suitably aligned memory location. Asm volatile
+ is used to prevent the optimizer from moving the operation. */
+
+#define _AMO_LD_CMPSWP(NAME, TYPE, OPCODE, FC) \
+static __inline__ TYPE \
+NAME (TYPE *_PTR, TYPE _COND, TYPE _VALUE) \
+{ \
+ register TYPE _ret asm ("r8"); \
+ register TYPE _cond asm ("r9") = _COND; \
+ register TYPE _value asm ("r10") = _VALUE; \
+ __asm__ __volatile__ (OPCODE " %[ret],%P[addr],%[code]" \
+ : [addr] "+Q" (_PTR[0]), [ret] "=r" (_ret) \
+ : "r" (_cond), "r" (_value), [code] "n" (FC)); \
+ return _ret; \
+}
+
+/* Implementation of the LWAT/LDAT fetch and increment operations.
+
+ The LWAT/LDAT opcode requires the address to be a single register that
+ points to a suitably aligned memory location. Asm volatile is used to
+ prevent the optimizer from moving the operation. */
+
+#define _AMO_LD_INCREMENT(NAME, TYPE, OPCODE, FC) \
+static __inline__ TYPE \
+NAME (TYPE *_PTR) \
+{ \
+ TYPE _RET; \
+ __asm__ volatile (OPCODE " %[ret],%P[addr],%[code]\n"
\
+ : [addr] "+Q" (_PTR[0]), [ret] "=r" (_RET) \
+ : "Q" (*(TYPE (*)[2]) _PTR), [code] "n" (FC)); \
+ return _RET; \
+}
+
+/* Implementation of the LWAT/LDAT fetch and decrement operations.
+
+ The LWAT/LDAT opcode requires the address to be a single register that
+ points to a suitably aligned memory location. Asm volatile is used to
+ prevent the optimizer from moving the operation. */
+
+#define _AMO_LD_DECREMENT(NAME, TYPE, OPCODE, FC) \
+static __inline__ TYPE \
+NAME (TYPE *_PTR) \
+{ \
+ TYPE _RET; \
+ __asm__ volatile (OPCODE " %[ret],%P[addr],%[code]\n"
\
+ : [addr] "+Q" (_PTR[1]), [ret] "=r" (_RET) \
+ : "Q" (*(TYPE (*)[2]) (_PTR)), [code] "n" (FC));\
+ return _RET; \
+}
+
_AMO_LD_SIMPLE (amo_lwat_add, uint32_t, "lwat", _AMO_LD_ADD)
_AMO_LD_SIMPLE (amo_lwat_xor, uint32_t, "lwat", _AMO_LD_XOR)
_AMO_LD_SIMPLE (amo_lwat_ior, uint32_t, "lwat", _AMO_L
[PATCH] testsuite: Fix gcc.target/powerpc/vsx-builtin-7.c test [PR119382]
Hi All,
The following patch has been tested on powerpc64le-linux and verified it's
fixed.
The test vsx-builtin-7.c was failing on powerpc64le-linux due to identical
function detection by ICF. This behavior was introduced by commit
r15-7961-gdc47161c1f32c3, which improved alias analysis in
ao_compare::compare_ao_refs, allowing the compiler to recognize and optimize
structurally identical functions.
The option -fno-ipa-icf is required because insert_di_0_v2 and insert_di_0 are
identified as equivalent, causing the compiler to replace insert_di_0_v2 with a
tail call to insert_di_0.
To prevent this optimization from altering the test behavior, explicitly disable
ICF by adding -fno-ipa-icf to the test options.
2025-03-25 Jeevitha Palanisamy
gcc/testsuite/
PR testsuite/119382
* gcc.target/powerpc/vsx-builtin-7.c: Add '-fno-ipa-icf' to dg-options.
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c
b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c
index 5095d5030fd..78e4e23d102 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-options "-O2 -mdejagnu-cpu=power7 -fno-inline-functions" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power7 -fno-inline-functions -fno-ipa-icf"
} */
/* { dg-require-effective-target powerpc_vsx } */
/* Test simple extract/insert/slat operations. Make sure all types are
[PING^2] [PATCH v2] rs6000: Adding missed ISA 3.0 atomic memory operation instructions.
Ping!
please review.
Thanks & Regards
Jeevitha
On 20/02/25 7:41 pm, jeevitha wrote:
> Hi All,
>
> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>
> Changes to amo.h include the addition of the following load atomic operations:
> Compare and Swap Not Equal, Fetch and Increment Bounded, Fetch and Increment
> Equal, and Fetch and Decrement Bounded. Additionally, Store Twin is added for
> store atomic operations.
>
> 2025-02-20 Peter Bergner
>
> gcc/:
> * config/rs6000/amo.h: Add missing atomic memory operations.
> * doc/extend.texi (PowerPC Atomic Memory Operation Functions):
> Document new functions.
>
> gcc/testsuite/:
> * gcc.target/powerpc/amo3.c: New test.
> * gcc.target/powerpc/amo4.c: Likewise.
> * gcc.target/powerpc/amo5.c: Likewise.
> * gcc.target/powerpc/amo6.c: Likewise.
> * gcc.target/powerpc/amo7.c: Likewise.
>
> Co-authored-by: Jeevitha Palanisamy
>
>
> diff --git a/gcc/config/rs6000/amo.h b/gcc/config/rs6000/amo.h
> index 25ab1c7b4c4..10960208d31 100644
> --- a/gcc/config/rs6000/amo.h
> +++ b/gcc/config/rs6000/amo.h
> @@ -71,6 +71,64 @@ NAME (TYPE *_PTR, TYPE _VALUE)
> \
>return _RET;
> \
> }
>
> +/* Implementation of the LWAT/LDAT operations that take two input registers
> + and modify one word or double-word of memory and return the value that was
> + previously in the memory location. The destination and two source
> + registers are encoded with only one register number, so we need three
> + consecutive GPR registers and there is no C/C++ type that will give
> + us that, so we have to use register asm variables to achieve that.
> +
> + The LWAT/LDAT opcode requires the address to be a single register,
> + and that points to a suitably aligned memory location. Asm volatile
> + is used to prevent the optimizer from moving the operation. */
> +
> +#define _AMO_LD_CMPSWP(NAME, TYPE, OPCODE, FC)
> \
> +static __inline__ TYPE
> \
> +NAME (TYPE *_PTR, TYPE _COND, TYPE _VALUE) \
> +{\
> + register TYPE _ret asm ("r8"); \
> + register TYPE _cond asm ("r9") = _COND;\
> + register TYPE _value asm ("r10") = _VALUE; \
> + __asm__ __volatile__ (OPCODE " %[ret],%P[addr],%[code]"\
> + : [addr] "+Q" (_PTR[0]), [ret] "=r" (_ret) \
> + : "r" (_cond), "r" (_value), [code] "n" (FC)); \
> + return _ret;
> \
> +}
> +
> +/* Implementation of the LWAT/LDAT fetch and increment operations.
> +
> + The LWAT/LDAT opcode requires the address to be a single register that
> + points to a suitably aligned memory location. Asm volatile is used to
> + prevent the optimizer from moving the operation. */
> +
> +#define _AMO_LD_INCREMENT(NAME, TYPE, OPCODE, FC)\
> +static __inline__ TYPE
> \
> +NAME (TYPE *_PTR)\
> +{\
> + TYPE _RET; \
> + __asm__ volatile (OPCODE " %[ret],%P[addr],%[code]\n"
> \
> + : [addr] "+Q" (_PTR[0]), [ret] "=r" (_RET) \
> + : "Q" (*(TYPE (*)[2]) _PTR), [code] "n" (FC)); \
> + return _RET;
> \
> +}
> +
> +/* Implementation of the LWAT/LDAT fetch and decrement operations.
> +
> + The LWAT/LDAT opcode requires the address to be a single register that
> + points to a suitably aligned memory location. Asm volatile is used to
> + prevent the optimizer from moving the operation. */
> +
> +#define _AMO_LD_DECREMENT(NAME, TYPE, OPCODE, FC)\
> +static __inline__ TYPE
> \
> +NAME (TYPE *_PTR)\
> +{\
> + TYPE _RET; \
> + __asm_
[PATCH V2] rs6000: Don't allow AltiVec address in movoo & movxo pattern [PR110411]
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
There are no instructions that do traditional AltiVec addresses (i.e.
with the low four bits of the address masked off) for OOmode and XOmode
objects. The solution is to modify the constraints used in the movoo and
movxo pattern to disallow these types of addresses, which assists LRA in
resolving this issue. Furthermore, the mode size 16 check has been
removed in vsx_quad_dform_memory_operand to allow OOmode and
quad_address_p already handles less than size 16.
2023-07-19 Jeevitha Palanisamy
gcc/
PR target/110411
* config/rs6000/mma.md (define_insn_and_split movoo): Disallow
AltiVec address in movoo and movxo pattern.
(define_insn_and_split movxo): Likewise.
*config/rs6000/predicates.md (vsx_quad_dform_memory_operand):Remove
redundant mode size check.
gcc/testsuite/
PR target/110411
* gcc.target/powerpc/pr110411-1.c: New testcase.
* gcc.target/powerpc/pr110411-2.c: New testcase.
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index d36dc13872b..575751d477e 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -293,8 +293,8 @@
})
(define_insn_and_split "*movoo"
- [(set (match_operand:OO 0 "nonimmediate_operand" "=wa,m,wa")
- (match_operand:OO 1 "input_operand" "m,wa,wa"))]
+ [(set (match_operand:OO 0 "nonimmediate_operand" "=wa,ZwO,wa")
+ (match_operand:OO 1 "input_operand" "ZwO,wa,wa"))]
"TARGET_MMA
&& (gpc_reg_operand (operands[0], OOmode)
|| gpc_reg_operand (operands[1], OOmode))"
@@ -340,8 +340,8 @@
})
(define_insn_and_split "*movxo"
- [(set (match_operand:XO 0 "nonimmediate_operand" "=d,m,d")
- (match_operand:XO 1 "input_operand" "m,d,d"))]
+ [(set (match_operand:XO 0 "nonimmediate_operand" "=d,ZwO,d")
+ (match_operand:XO 1 "input_operand" "ZwO,d,d"))]
"TARGET_MMA
&& (gpc_reg_operand (operands[0], XOmode)
|| gpc_reg_operand (operands[1], XOmode))"
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 3552d908e9d..925f69cd3fc 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -924,7 +924,7 @@
(define_predicate "vsx_quad_dform_memory_operand"
(match_code "mem")
{
- if (!TARGET_P9_VECTOR || GET_MODE_SIZE (mode) != 16)
+ if (!TARGET_P9_VECTOR)
return false;
return quad_address_p (XEXP (op, 0), mode, false);
diff --git a/gcc/testsuite/gcc.target/powerpc/pr110411-1.c
b/gcc/testsuite/gcc.target/powerpc/pr110411-1.c
new file mode 100644
index 000..f42e9388d65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110411-1.c
@@ -0,0 +1,22 @@
+/* PR target/110411 */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -mblock-ops-vector-pair" } */
+
+/* Verify we do not ICE on the following. */
+
+#include
+
+struct s {
+ long a;
+ long b;
+ long c;
+ long d: 1;
+};
+unsigned long ptr;
+
+void
+bug (struct s *dst)
+{
+ struct s *src = (struct s *)(ptr & ~0xFUL);
+ memcpy (dst, src, sizeof(struct s));
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/pr110411-2.c
b/gcc/testsuite/gcc.target/powerpc/pr110411-2.c
new file mode 100644
index 000..c2046fb9855
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110411-2.c
@@ -0,0 +1,12 @@
+/* PR target/110411 */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Verify we do not ICE on the following. */
+
+void
+bug (__vector_quad *dst)
+{
+ dst = (__vector_quad *)((unsigned long)dst & ~0xFUL);
+ __builtin_mma_xxsetaccz (dst);
+}
[PATCH] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
When the user specifies PTImode as an attribute, it breaks. Created
a tree node to handle PTImode types. PTImode attribute helps in generating
even/odd register pairs on 128 bits.
2023-07-20 Jeevitha Palanisamy
gcc/
PR target/110411
* config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add fields
to hold PTImode type.
* config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Add node
for PTImode type.
gcc/testsuite/
PR target/106895
* gcc.target/powerpc/pr106895.c: New testcase.
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index a8f291c6a72..ca00c3b0d4c 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -756,6 +756,15 @@ rs6000_init_builtins (void)
else
ieee128_float_type_node = NULL_TREE;
+ /* PTImode to get even/odd register pairs. */
+ intPTI_type_internal_node = make_node(INTEGER_TYPE);
+ TYPE_PRECISION (intPTI_type_internal_node) = GET_MODE_BITSIZE (PTImode);
+ layout_type (intPTI_type_internal_node);
+ SET_TYPE_MODE (intPTI_type_internal_node, PTImode);
+ t = build_qualified_type (intPTI_type_internal_node, TYPE_QUAL_CONST);
+ lang_hooks.types.register_builtin_type (intPTI_type_internal_node,
+ "__int128pti");
+
/* Vector pair and vector quad support. */
vector_pair_type_node = make_node (OPAQUE_TYPE);
SET_TYPE_MODE (vector_pair_type_node, OOmode);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 3503614efbd..0456bf56d17 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2303,6 +2303,7 @@ enum rs6000_builtin_type_index
RS6000_BTI_ptr_vector_quad,
RS6000_BTI_ptr_long_long,
RS6000_BTI_ptr_long_long_unsigned,
+ RS6000_BTI_PTI,
RS6000_BTI_MAX
};
@@ -2347,6 +2348,7 @@ enum rs6000_builtin_type_index
#define uintDI_type_internal_node
(rs6000_builtin_types[RS6000_BTI_UINTDI])
#define intTI_type_internal_node
(rs6000_builtin_types[RS6000_BTI_INTTI])
#define uintTI_type_internal_node
(rs6000_builtin_types[RS6000_BTI_UINTTI])
+#define intPTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_PTI])
#define float_type_internal_node
(rs6000_builtin_types[RS6000_BTI_float])
#define double_type_internal_node
(rs6000_builtin_types[RS6000_BTI_double])
#define long_double_type_internal_node
(rs6000_builtin_types[RS6000_BTI_long_double])
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106895.c
b/gcc/testsuite/gcc.target/powerpc/pr106895.c
new file mode 100644
index 000..04630fe1df5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr106895.c
@@ -0,0 +1,15 @@
+/* PR target/106895 */
+/* { dg-require-effective-target int128 } */
+/* { dg-options "-O2" } */
+
+/* Verify the following generates even/odd register pairs. */
+
+typedef __int128 pti __attribute__((mode(PTI)));
+
+void
+set128 (pti val, pti *mem)
+{
+asm("stq %1,%0" : "=m"(*mem) : "r"(val));
+}
+
+/* { dg-final { scan-assembler "stq 10,0\\(5\\)" } } */
[PING ^1][PATCH] rs6000: Fix issue in specifying PTImode as an attribute [PR106895]
Ping!
please review.
Thanks & Regards
Jeevitha
On 20/07/23 10:05 am, jeevitha wrote:
> Hi All,
>
> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>
> When the user specifies PTImode as an attribute, it breaks. Created
> a tree node to handle PTImode types. PTImode attribute helps in generating
> even/odd register pairs on 128 bits.
>
> 2023-07-20 Jeevitha Palanisamy
>
> gcc/
> PR target/110411
> * config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add fields
> to hold PTImode type.
> * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Add node
> for PTImode type.
>
> gcc/testsuite/
> PR target/106895
> * gcc.target/powerpc/pr106895.c: New testcase.
>
> diff --git a/gcc/config/rs6000/rs6000-builtin.cc
> b/gcc/config/rs6000/rs6000-builtin.cc
> index a8f291c6a72..ca00c3b0d4c 100644
> --- a/gcc/config/rs6000/rs6000-builtin.cc
> +++ b/gcc/config/rs6000/rs6000-builtin.cc
> @@ -756,6 +756,15 @@ rs6000_init_builtins (void)
>else
> ieee128_float_type_node = NULL_TREE;
>
> + /* PTImode to get even/odd register pairs. */
> + intPTI_type_internal_node = make_node(INTEGER_TYPE);
> + TYPE_PRECISION (intPTI_type_internal_node) = GET_MODE_BITSIZE (PTImode);
> + layout_type (intPTI_type_internal_node);
> + SET_TYPE_MODE (intPTI_type_internal_node, PTImode);
> + t = build_qualified_type (intPTI_type_internal_node, TYPE_QUAL_CONST);
> + lang_hooks.types.register_builtin_type (intPTI_type_internal_node,
> + "__int128pti");
> +
>/* Vector pair and vector quad support. */
>vector_pair_type_node = make_node (OPAQUE_TYPE);
>SET_TYPE_MODE (vector_pair_type_node, OOmode);
> diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
> index 3503614efbd..0456bf56d17 100644
> --- a/gcc/config/rs6000/rs6000.h
> +++ b/gcc/config/rs6000/rs6000.h
> @@ -2303,6 +2303,7 @@ enum rs6000_builtin_type_index
>RS6000_BTI_ptr_vector_quad,
>RS6000_BTI_ptr_long_long,
>RS6000_BTI_ptr_long_long_unsigned,
> + RS6000_BTI_PTI,
>RS6000_BTI_MAX
> };
>
> @@ -2347,6 +2348,7 @@ enum rs6000_builtin_type_index
> #define uintDI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_UINTDI])
> #define intTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_INTTI])
> #define uintTI_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_UINTTI])
> +#define intPTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_PTI])
> #define float_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_float])
> #define double_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_double])
> #define long_double_type_internal_node
> (rs6000_builtin_types[RS6000_BTI_long_double])
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr106895.c
> b/gcc/testsuite/gcc.target/powerpc/pr106895.c
> new file mode 100644
> index 000..04630fe1df5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr106895.c
> @@ -0,0 +1,15 @@
> +/* PR target/106895 */
> +/* { dg-require-effective-target int128 } */
> +/* { dg-options "-O2" } */
> +
> +/* Verify the following generates even/odd register pairs. */
> +
> +typedef __int128 pti __attribute__((mode(PTI)));
> +
> +void
> +set128 (pti val, pti *mem)
> +{
> +asm("stq %1,%0" : "=m"(*mem) : "r"(val));
> +}
> +
> +/* { dg-final { scan-assembler "stq 10,0\\(5\\)" } } */
>
>
[PING^1][PATCH V2] rs6000: Don't allow AltiVec address in movoo & movxo pattern [PR110411]
Ping!
please review.
Thanks & Regards
Jeevitha
On 19/07/23 10:16 pm, jeevitha wrote:
> Hi All,
>
> The following patch has been bootstrapped and regtested on powerpc64le-linux.
>
> There are no instructions that do traditional AltiVec addresses (i.e.
> with the low four bits of the address masked off) for OOmode and XOmode
> objects. The solution is to modify the constraints used in the movoo and
> movxo pattern to disallow these types of addresses, which assists LRA in
> resolving this issue. Furthermore, the mode size 16 check has been
> removed in vsx_quad_dform_memory_operand to allow OOmode and
> quad_address_p already handles less than size 16.
>
> 2023-07-19 Jeevitha Palanisamy
>
> gcc/
> PR target/110411
> * config/rs6000/mma.md (define_insn_and_split movoo): Disallow
> AltiVec address in movoo and movxo pattern.
> (define_insn_and_split movxo): Likewise.
> *config/rs6000/predicates.md (vsx_quad_dform_memory_operand):Remove
> redundant mode size check.
>
> gcc/testsuite/
> PR target/110411
> * gcc.target/powerpc/pr110411-1.c: New testcase.
> * gcc.target/powerpc/pr110411-2.c: New testcase.
>
> diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
> index d36dc13872b..575751d477e 100644
> --- a/gcc/config/rs6000/mma.md
> +++ b/gcc/config/rs6000/mma.md
> @@ -293,8 +293,8 @@
> })
>
> (define_insn_and_split "*movoo"
> - [(set (match_operand:OO 0 "nonimmediate_operand" "=wa,m,wa")
> - (match_operand:OO 1 "input_operand" "m,wa,wa"))]
> + [(set (match_operand:OO 0 "nonimmediate_operand" "=wa,ZwO,wa")
> + (match_operand:OO 1 "input_operand" "ZwO,wa,wa"))]
>"TARGET_MMA
> && (gpc_reg_operand (operands[0], OOmode)
> || gpc_reg_operand (operands[1], OOmode))"
> @@ -340,8 +340,8 @@
> })
>
> (define_insn_and_split "*movxo"
> - [(set (match_operand:XO 0 "nonimmediate_operand" "=d,m,d")
> - (match_operand:XO 1 "input_operand" "m,d,d"))]
> + [(set (match_operand:XO 0 "nonimmediate_operand" "=d,ZwO,d")
> + (match_operand:XO 1 "input_operand" "ZwO,d,d"))]
>"TARGET_MMA
> && (gpc_reg_operand (operands[0], XOmode)
> || gpc_reg_operand (operands[1], XOmode))"
> diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
> index 3552d908e9d..925f69cd3fc 100644
> --- a/gcc/config/rs6000/predicates.md
> +++ b/gcc/config/rs6000/predicates.md
> @@ -924,7 +924,7 @@
> (define_predicate "vsx_quad_dform_memory_operand"
>(match_code "mem")
> {
> - if (!TARGET_P9_VECTOR || GET_MODE_SIZE (mode) != 16)
> + if (!TARGET_P9_VECTOR)
> return false;
>
>return quad_address_p (XEXP (op, 0), mode, false);
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr110411-1.c
> b/gcc/testsuite/gcc.target/powerpc/pr110411-1.c
> new file mode 100644
> index 000..f42e9388d65
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr110411-1.c
> @@ -0,0 +1,22 @@
> +/* PR target/110411 */
> +/* { dg-require-effective-target power10_ok } */
> +/* { dg-options "-O2 -mdejagnu-cpu=power10 -mblock-ops-vector-pair" } */
> +
> +/* Verify we do not ICE on the following. */
> +
> +#include
> +
> +struct s {
> + long a;
> + long b;
> + long c;
> + long d: 1;
> +};
> +unsigned long ptr;
> +
> +void
> +bug (struct s *dst)
> +{
> + struct s *src = (struct s *)(ptr & ~0xFUL);
> + memcpy (dst, src, sizeof(struct s));
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr110411-2.c
> b/gcc/testsuite/gcc.target/powerpc/pr110411-2.c
> new file mode 100644
> index 000..c2046fb9855
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr110411-2.c
> @@ -0,0 +1,12 @@
> +/* PR target/110411 */
> +/* { dg-require-effective-target power10_ok } */
> +/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
> +
> +/* Verify we do not ICE on the following. */
> +
> +void
> +bug (__vector_quad *dst)
> +{
> + dst = (__vector_quad *)((unsigned long)dst & ~0xFUL);
> + __builtin_mma_xxsetaccz (dst);
> +}
>
>
>
[PATCH] MAINTAINERS: Add myself to write after approval
2023-05-30 Jeevitha Palanisamy ChangeLog: * MAINTAINERS (Write After Approval): Add myself. diff --git a/MAINTAINERS b/MAINTAINERS index 2dc51154446..4a7c963914b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -584,6 +584,7 @@ Patrick O'Neill Braden Obrzut Andrea Ornstein Maxim Ostapenko +Jeevitha Palanisamy Patrick Palka Srinath Parvathaneni Devang Patel -- 2.39.1
[PATCH] rs6000: Remove duplicate expression [PR106907]
PR106907 has few warnings spotted from cppcheck. In that addressing duplicate expression issue here. Here the same expression is used twice in logical AND(&&) operation which result in same result so removing that. 2023-06-05 Jeevitha Palanisamy gcc/ PR target/106907 * config/rs6000/rs6000.cc (vec_const_128bit_to_bytes): Remove duplicate expression. diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 42f49e4a56b..d197c3f3289 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -28784,7 +28784,6 @@ vec_const_128bit_to_bytes (rtx op, info->all_words_same = (info->words[0] == info->words[1] - && info->words[0] == info->words[1] && info->words[0] == info->words[2] && info->words[0] == info->words[3]);
Re: [PATCH] rs6000: Remove duplicate expression [PR106907]
Thanks for reviewing Segher. Will work on backports as well :). Jeevitha
[PATCH] rs6000: Remove redundant initialization [PR106907]
PR106907 has few warnings spotted from cppcheck. In that addressing
redundant initialization issue. Here the initialized value of 'new_addr'
was overwritten before it was read. Updated the source by removing the
unnecessary initialization of 'new_addr'.
2023-06-07 Jeevitha Palanisamy
gcc/
PR target/106907
* gcc/config/rs6000/rs6000.cc (rs6000_expand_vector_extract): Remove
redundant
initialization of new_addr.
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 42f49e4a56b..d994e004bd3 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7660,12 +7660,11 @@ rs6000_expand_vector_extract (rtx target, rtx vec, rtx
elt)
{
unsigned int ele_size = GET_MODE_SIZE (inner_mode);
rtx num_ele_m1 = GEN_INT (GET_MODE_NUNITS (mode) - 1);
- rtx new_addr = gen_reg_rtx (Pmode);
elt = gen_rtx_AND (Pmode, elt, num_ele_m1);
if (ele_size > 1)
elt = gen_rtx_MULT (Pmode, elt, GEN_INT (ele_size));
- new_addr = gen_rtx_PLUS (Pmode, XEXP (mem, 0), elt);
+ rtx new_addr = gen_rtx_PLUS (Pmode, XEXP (mem, 0), elt);
new_addr = change_address (mem, inner_mode, new_addr);
emit_move_insn (target, new_addr);
}
[PATCH] Add parentheses to clarify precedence between operators [PR106907]
PR106907 has few warnings spotted from cppcheck. Inorder to clarify the order of precedence between operators added parentheses to explicitly group operations based on desired order of evaluation. 2023-06-07 Jeevitha Palanisamy gcc/ PR target/106907 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add parentheses to group the operations. diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc index efb7211d54e..d2b5cb74204 100644 --- a/gcc/config/gcn/gcn.cc +++ b/gcc/config/gcn/gcn.cc @@ -6300,7 +6300,7 @@ gcn_hsa_declare_function_name (FILE *file, const char *name, tree) fprintf (file, "\t .amdhsa_system_vgpr_workitem_id\t%i\n", (cfun->machine->args.requested & (1 << WORK_ITEM_ID_Z_ARG)) ? 2 - : cfun->machine->args.requested & (1 << WORK_ITEM_ID_Y_ARG) + : (cfun->machine->args.requested & (1 << WORK_ITEM_ID_Y_ARG)) ? 1 : 0); fprintf (file, "\t .amdhsa_next_free_vgpr\t%i\n"
[PATCH] rs6000: Change bitwise xor to inequality operator [PR106907]
PR106907 has few warnings spotted from cppcheck. Here we have warnings for precedence clarification since boolean results are used in bitwise operation. Bitwise xor performed on bool is similar to checking inequality. So changed to inequality operator (!=) instead of bitwise xor (^). And fixed comment indentation 2023-06-12 Jeevitha Palanisamy gcc/ PR target/106907 * config/rs6000/rs6000.cc (altivec_expand_vec_perm_const): Change bitwise xor to inequality and fix comment indentation. diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index ea68ca6faef..ea7efda8dcd 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -23396,10 +23396,10 @@ altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1, && GET_MODE (XEXP (op0, 0)) != V8HImode))) continue; - /* For little-endian, the two input operands must be swapped - (or swapped back) to ensure proper right-to-left numbering - from 0 to 2N-1. */ - if (swapped ^ !BYTES_BIG_ENDIAN + /* For little-endian, the two input operands must be swapped +(or swapped back) to ensure proper right-to-left numbering +from 0 to 2N-1. */ + if (swapped != !BYTES_BIG_ENDIAN && icode != CODE_FOR_vsx_xxpermdi_v16qi) std::swap (op0, op1); if (imode != V16QImode)
[PATCH V2] rs6000: Change GPR2 to volatile & non-fixed register for function that does not use TOC [PR110320]
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
Normally, GPR2 is the TOC pointer and is defined as a fixed and non-volatile
register. However, it can be used as volatile for PCREL addressing. Therefore,
modified r2 to be non-fixed in FIXED_REGISTERS and set it to fixed if it is not
PCREL and also when the user explicitly requests TOC or fixed. If the register
r2 is fixed, it is made as non-volatile. Changes in register preservation roles
can be accomplished with the help of available target hooks
(TARGET_CONDITIONAL_REGISTER_USAGE).
2023-07-12 Jeevitha Palanisamy
gcc/
PR target/PR110320
* config/rs6000/rs6000.cc (rs6000_conditional_register_usage): Change
GPR2 to volatile and non-fixed register for PCREL.
gcc/testsuite/
PR target/PR110320
* gcc.target/powerpc/pr110320-1.c: New testcase.
* gcc.target/powerpc/pr110320-2.c: New testcase.
* gcc.target/powerpc/pr110320-3.c: New testcase.
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 44b448d2ba6..9aa04ec5d57 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -10193,9 +10193,13 @@ rs6000_conditional_register_usage (void)
for (i = 32; i < 64; i++)
fixed_regs[i] = call_used_regs[i] = 1;
+ /* For non PC-relative code, GPR2 is unavailable for register allocation. */
+ if (FIXED_R2 && !rs6000_pcrel_p ())
+fixed_regs[2] = 1;
+
/* The TOC register is not killed across calls in a way that is
visible to the compiler. */
- if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
+ if (fixed_regs[2] && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2))
call_used_regs[2] = 0;
if (DEFAULT_ABI == ABI_V4 && flag_pic == 2)
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 3503614efbd..2a24fbdf9fd 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -812,7 +812,7 @@ enum data_align { align_abi, align_opt, align_both };
#define FIXED_REGISTERS \
{/* GPRs */ \
- 0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
+ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
/* FPRs */ \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
diff --git a/gcc/testsuite/gcc.target/powerpc/pr110320-1.c
b/gcc/testsuite/gcc.target/powerpc/pr110320-1.c
new file mode 100644
index 000..a4ad34d9303
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110320-1.c
@@ -0,0 +1,22 @@
+/* PR target/110320 */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -ffixed-r0 -ffixed-r11 -ffixed-r12"
} */
+
+/* Ensure we use r2 as a normal volatile register for the code below.
+ The test case ensures all of the parameter registers r3 - r10 are used
+ and needed after we compute the expression "x + y" which requires a
+ temporary. The -ffixed-r* options disallow using the other volatile
+ registers r0, r11 and r12. That leaves RA to choose from r2 and the more
+ expensive non-volatile registers for the temporary to be assigned to, and
+ RA will always chooses the cheaper volatile r2 register. */
+
+extern long bar (long, long, long, long, long, long, long, long *);
+
+long
+foo (long r3, long r4, long r5, long r6, long r7, long r8, long r9, long *r10)
+{
+ *r10 = r3 + r4;
+ return bar (r3, r4, r5, r6, r7, r8, r9, r10);
+}
+
+/* { dg-final { scan-assembler {\madd 2,3,4\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr110320-2.c
b/gcc/testsuite/gcc.target/powerpc/pr110320-2.c
new file mode 100644
index 000..9d6aefedd2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110320-2.c
@@ -0,0 +1,21 @@
+/* PR target/110320 */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -mno-pcrel -ffixed-r0 -ffixed-r11
-ffixed-r12" } */
+
+/* Ensure we don't use r2 as a normal volatile register for the code below.
+ The test case ensures all of the parameter registers r3 - r10 are used
+ and needed after we compute the expression "x + y" which requires a
+ temporary. The -ffixed-r* options disallow using the other volatile
+ registers r0, r11 and r12. That only leaves RA to choose from the more
+ expensive non-volatile registers for the temporary to be assigned to. */
+
+extern long bar (long, long, long, long, long, long, long, long *);
+
+long
+foo (long r3, long r4, long r5, long r6, long r7, long r8, long r9, long *r10)
+{
+ *r10 = r3 + r4;
+ return bar (r3, r4, r5, r6, r7, r8, r9, r10);
+}
+
+/* { dg-final { scan-assembler-not {\madd 2,3,4\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr110320-3.c
b/gcc/testsuite/gcc.target/powerpc/pr110320-3.c
new file mode 100644
index 0
[PATCH] rs6000: Change GPR2 to volatile & non-fixed register for function that does not use TOC [PR110320]
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
Normally, GPR2 is the TOC pointer and is defined as a fixed and non-volatile
register. However, it can be used as volatile for PCREL addressing. Therefore,
if the code is PCREL and the user is not explicitly requesting TOC addressing,
then the register r2 can be changed to volatile and non-fixed register. Changes
in register preservation roles can be accomplished with the help of available
target hooks (TARGET_CONDITIONAL_REGISTER_USAGE).
2023-06-23 Jeevitha Palanisamy
gcc/
PR target/PR110320
* config/rs6000/rs6000.cc (rs6000_conditional_register_usage): Change
GPR2 to volatile and non-fixed register for pc-relative code.
gcc/testsuite/
PR target/PR110320
* gcc.target/powerpc/pr110320_1.c: New testcase.
* gcc.target/powerpc/pr110320_2.c: New testcase.
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 546c353029b..9e978f85f9d 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -10169,6 +10169,35 @@ rs6000_conditional_register_usage (void)
if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
call_used_regs[2] = 0;
+ /* The TOC register is not needed for functions using the PC-relative ABI
+ extension, so make it available for register allocation as a volatile
+ register. */
+ if (FIXED_R2 && rs6000_pcrel_p ())
+{
+ bool cli_fixedr2 = false;
+
+ /* Verify the user has not explicitly asked for GPR2 to be fixed. */
+ if (common_deferred_options)
+ {
+ unsigned int idx;
+ cl_deferred_option *opt;
+ vec v;
+ v = *((vec *) common_deferred_options);
+ FOR_EACH_VEC_ELT (v, idx, opt)
+ if (opt->opt_index == OPT_ffixed_ && strcmp (opt->arg,"r2") == 0)
+ {
+ cli_fixedr2 = true;
+ break;
+ }
+ }
+
+ /* If GPR2 is not FIXED (eg, not a TOC register), then it is volatile.
*/
+ if (!cli_fixedr2)
+ {
+ fixed_regs[2] = 0;
+ call_used_regs[2] = 1;
+ }
+}
if (DEFAULT_ABI == ABI_V4 && flag_pic == 2)
fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
diff --git a/gcc/testsuite/gcc.target/powerpc/pr110320_1.c
b/gcc/testsuite/gcc.target/powerpc/pr110320_1.c
new file mode 100644
index 000..42143fbf889
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110320_1.c
@@ -0,0 +1,23 @@
+/* PR target/110320 */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -ffixed-r0 -ffixed-r11 -ffixed-r12"
} */
+
+/* Ensure we use r2 as a normal volatile register for the code below.
+ The test case ensures all of the parameter registers r3 - r10 are used
+ and needed after we compute the expression "x + y" which requires a
+ temporary. The -ffixed-r* options disallow using the other volatile
+ registers r0, r11 and r12. That leaves RA to choose from r2 and the more
+ expensive non-volatile registers for the temporary to be assigned to, and
+ RA will always chooses the cheaper volatile r2 register. */
+
+extern long bar (long, long, long, long, long, long, long, long *);
+
+long
+foo (long r3, long r4, long r5, long r6, long r7, long r8, long r9, long *r10)
+{
+ *r10 = r3 + r4;
+ return bar (r3, r4, r5, r6, r7, r8, r9, r10);
+}
+
+/* { dg-final { scan-assembler {\madd 2,3,4\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr110320_2.c
b/gcc/testsuite/gcc.target/powerpc/pr110320_2.c
new file mode 100644
index 000..9d0da5b9695
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110320_2.c
@@ -0,0 +1,22 @@
+/* PR target/110320 */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -mno-pcrel -ffixed-r0 -ffixed-r11
-ffixed-r12" } */
+
+/* Ensure we don't use r2 as a normal volatile register for the code below.
+ The test case ensures all of the parameter registers r3 - r10 are used
+ and needed after we compute the expression "x + y" which requires a
+ temporary. The -ffixed-r* options disallow using the other volatile
+ registers r0, r11 and r12. That only leaves RA to choose from the more
+ expensive non-volatile registers for the temporary to be assigned to. */
+
+extern long bar (long, long, long, long, long, long, long, long *);
+
+long
+foo (long r3, long r4, long r5, long r6, long r7, long r8, long r9, long *r10)
+{
+ *r10 = r3 + r4;
+ return bar (r3, r4, r5, r6, r7, r8, r9, r10);
+}
+
+/* { dg-final { scan-assembler-not {\madd 2,3,4\M} } } */
[PATCH] rs6000: Don't ICE when generating vector pair load/store insns [PR110411]
Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
while generating vector pairs of load & store instruction, the src address
was treated as an altivec type and that type of address is invalid for
lxvp and stxvp insns. The solution for this is to avoid altivec type address
for OOmode and XOmode.
2023-07-05 Jeevitha Palanisamy
gcc/
PR target/110411
* config/rs6000/rs6000.cc (rs6000_legitimate_address_p): Avoid altivec
address for OOmode and XOmde.
gcc/testsuite/
PR target/110411
* gcc.target/powerpc/pr110411.c: New testcase.
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 07c3a3d15ac..b914c65e5c9 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -9894,6 +9894,8 @@ rs6000_legitimate_address_p (machine_mode mode, rtx x,
bool reg_ok_strict)
/* Handle unaligned altivec lvx/stvx type addresses. */
if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
+ && mode != OOmode
+ && mode != XOmode
&& GET_CODE (x) == AND
&& CONST_INT_P (XEXP (x, 1))
&& INTVAL (XEXP (x, 1)) == -16)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr110411.c
b/gcc/testsuite/gcc.target/powerpc/pr110411.c
new file mode 100644
index 000..83ef0638fb2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110411.c
@@ -0,0 +1,21 @@
+/* PR target/110411 */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -S -mblock-ops-vector-pair" } */
+
+/* Verify we do not ICE on the following. */
+
+#include
+
+struct s {
+ long a;
+ long b;
+ long c;
+ long d: 1;
+};
+unsigned long ptr;
+
+void
+foo (struct s *dst)
+{
+ struct s *src = (struct s *)(ptr & ~0xFUL);
+ memcpy (dst, src, sizeof(struct s));
+}
Re: [PATCH] rs6000: Change GPR2 to volatile & non-fixed register for function that does not use TOC [PR110320]
On 07/07/2023 A 12:11 am, Peter Bergner wrote:
> I believe the untested patch below should also work, without having to scan
> the (uncommonly used) options. Jeevitha, can you bootstrap and regtest the
> patch below?
Yeah Peter, Bootstrapped and regtested the below patch on powerpc64le-linux
there was no regression.
> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
> index d197c3f3289..7c356a73ac6 100644
> --- a/gcc/config/rs6000/rs6000.cc
> +++ b/gcc/config/rs6000/rs6000.cc
> @@ -10160,9 +10160,13 @@ rs6000_conditional_register_usage (void)
> for (i = 32; i < 64; i++)
>fixed_regs[i] = call_used_regs[i] = 1;
>
> + /* For non PC-relative code, GPR2 is unavailable for register allocation.
> */
> + if (FIXED_R2 && !rs6000_pcrel_p ())
> +fixed_regs[2] = 1;
> +
>/* The TOC register is not killed across calls in a way that is
> visible to the compiler. */
> - if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
> + if (fixed_regs[2] && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2))
> call_used_regs[2] = 0;
>
>if (DEFAULT_ABI == ABI_V4 && flag_pic == 2)
> diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
> index 3503614efbd..2a24fbdf9fd 100644
> --- a/gcc/config/rs6000/rs6000.h
> +++ b/gcc/config/rs6000/rs6000.h
> @@ -812,7 +812,7 @@ enum data_align { align_abi, align_opt, align_both };
>
> #define FIXED_REGISTERS \
>{/* GPRs */ \
> - 0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
> + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
> /* FPRs */ \
> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
>
>
>
>> Besides, IMHO we need a corresponding test case to cover this -ffixed-r2
>> handling.
>
> Good idea. I think we can duplicate the pr110320_2.c test case, replacing the
> -mno-pcrel option with -ffixed-r2. Jeevitha, can you give that a try?
Yeah, adding the new test cases along with the mentioned changes for the older
ones below,
diff --git a/gcc/testsuite/gcc.target/powerpc/pr110320_1.c
b/gcc/testsuite/gcc.target/powerpc/pr110320_1.c
new file mode 100644
index 000..a4ad34d9303
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110320_1.c
@@ -0,0 +1,22 @@
+/* PR target/110320 */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -ffixed-r0 -ffixed-r11 -ffixed-r12"
} */
+
+/* Ensure we use r2 as a normal volatile register for the code below.
+ The test case ensures all of the parameter registers r3 - r10 are used
+ and needed after we compute the expression "x + y" which requires a
+ temporary. The -ffixed-r* options disallow using the other volatile
+ registers r0, r11 and r12. That leaves RA to choose from r2 and the more
+ expensive non-volatile registers for the temporary to be assigned to, and
+ RA will always chooses the cheaper volatile r2 register. */
+
+extern long bar (long, long, long, long, long, long, long, long *);
+
+long
+foo (long r3, long r4, long r5, long r6, long r7, long r8, long r9, long *r10)
+{
+ *r10 = r3 + r4;
+ return bar (r3, r4, r5, r6, r7, r8, r9, r10);
+}
+
+/* { dg-final { scan-assembler {\madd 2,3,4\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr110320_2.c
b/gcc/testsuite/gcc.target/powerpc/pr110320_2.c
new file mode 100644
index 000..9d6aefedd2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110320_2.c
@@ -0,0 +1,21 @@
+/* PR target/110320 */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -mno-pcrel -ffixed-r0 -ffixed-r11
-ffixed-r12" } */
+
+/* Ensure we don't use r2 as a normal volatile register for the code below.
+ The test case ensures all of the parameter registers r3 - r10 are used
+ and needed after we compute the expression "x + y" which requires a
+ temporary. The -ffixed-r* options disallow using the other volatile
+ registers r0, r11 and r12. That only leaves RA to choose from the more
+ expensive non-volatile registers for the temporary to be assigned to. */
+
+extern long bar (long, long, long, long, long, long, long, long *);
+
+long
+foo (long r3, long r4, long r5, long r6, long r7, long r8, long r9, long *r10)
+{
+ *r10 = r3 + r4;
+ return bar (r3, r4, r5, r6, r7, r8, r9, r10);
+}
+
+/* { dg-final { scan-assembler-not {\madd 2,3,4\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr110320_3.c
b/gcc/testsuite/gcc.target/powerpc/pr110320_3.c
new file mode 100644
index 000..ea6c6188c8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110320_3.c
@@ -0,0 +1,21 @@
+/* PR target/110320 *
