[RFC] RISC-V: Support -mcmodel=large.
This is a RFC patch for large code model implementation. gcc/ChangeLog: * gcc/config/riscv/predicates.md(move_operand): Check SYMBOL_REF and LABEL_REF type. (call_insn_operand): Support for CM_Large. (pcrel_symbol_operand): New. * gcc/config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add builtin_define "__riscv_cmodel_large". * gcc/config/riscv/riscv-opts.h (riscv_code_model): Define CM_LARGE. * gcc/config/riscv/riscv-protos.h (riscv_symbol_type): Define SYMBOL_FORCE_TO_MEM. (riscv_asm_output_pool_epilogue): New. * gcc/config/riscv/riscv.cc (riscv_classify_symbol) Support CM_LARGE model. (riscv_symbol_insns) Add SYMBOL_FORCE_TO_MEM. (riscv_cannot_force_const_mem): Ditto. (riscv_split_symbol): Ditto. (riscv_force_address): Check pseudo reg available before force_reg. (riscv_size_ok_for_small_data_p): Disable in CM_LARGE model. (riscv_can_use_per_function_literal_pools_p): New. (riscv_asm_output_pool_epilogue): New. Hook ASM_OUTPUT_POOL_EPILOGUE. (riscv_output_mi_thunk): Add riscv_in_thunk_func. (riscv_option_override): Support CM_LARGE model. (riscv_function_ok_for_sibcall): Disable sibcalls in CM_LARGE model. * gcc/config/riscv/riscv.h (ASM_OUTPUT_POOL_EPILOGUE): Hookfg * gcc/config/riscv/riscv.md (unspec): Define UNSPEC_FORCE_FOR_MEM. (*large_load_address"): New. * gcc/config/riscv/riscv.opt (code_model): New. gcc/testsuite/ChangeLog: * gcc/testsuite/gcc.target/riscv/large-model.c: New test. 0001-RISC-V-Support-mcmodel-large.patch Description: Binary data
[PATCH] RISC-V:Raname UNSPEC_CLMUL in vector-crypto.md
UNSPEC_CLMUL is defined to define_c_enum in riscv.md, so it shouldn't be redefined to define_int_iterator again. *gcc/ChangeLog:* * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to UNSPEC_CLMUL_VC. 0001-RISC-V-Raname-UNSPEC_CLMUL-in-vector-crypto.md.patch Description: Binary data
Re: [RFC][V2] RISC-V: Support -mcmodel=large.
Hi Jeff, Sorry for this missing. I've removed riscv_asm_output_pool_epilogue because the pool beginning is always aligned from FUNCTION_BOUNDARY. Please find attached. Thank you. Jeff Law 於 2023年12月18日 週一 上午3:15寫道： > > > On 11/10/23 02:10, KuanLin Chen wrote: > > Sorry. It missed a semicolon in the previos patch. Please find the new > > one in the attachment. Thanks. > Thanks. I was going to do some final testing with the plan to integrate > this patch today, but I think there's a piece missing. Specifically I > think it's missing a definition for riscv_asm_output_pool_epilogue. > > Can you please send an updated patch that includes that function? > > Thanks, > Jeff > 0001-RISC-V-Support-mcmodel-large.patch Description: Binary data
[PATCH][V4] RISC-V: Nan-box the result of movhf on soft-fp16
According to spec, fmv.h checks if the input operands are correctly NaN-boxed. If not, the input value is treated as an n-bit canonical NaN. This patch fixs the issue that operands returned by soft-fp16 libgcc (i.e., __truncdfhf2) was not correctly NaN-boxed. *gcc/ChangeLog:* * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh with Nan-boxing value. * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern. *gcc/testsuite/ChangeLog:* * gcc.target/riscv/_Float16-nanboxing.c: New test. 0001-RISC-V-Nan-box-the-result-of-movhf-on-soft-fp16.patch Description: Binary data
[PATCH][V3] RISC-V: Nan-box the result of movhf on soft-fp16
According to spec, fmv.h checks if the input operands are correctly NaN-boxed. If not, the input value is treated as an n-bit canonical NaN. This patch fixs the issue that operands returned by soft-fp16 libgcc (i.e., __truncdfhf2) was not correctly NaN-boxed. *gcc/ChangeLog:* * config/riscv/riscv.cc (riscv_legitimize_move): Expand movhf with Nan-boxing value. * config/riscv/riscv.md (*movhf_softfloat_boxing): New pattern. *gcc/testsuite/ChangeLog:* gcc.target/riscv/_Float16-nanboxing.c: New test. 0001-RISC-V-Nan-box-the-result-of-movhf-on-soft-fp16.patch Description: Binary data
[PATCH] RISC-V: Nan-box the result of movhf on soft-fp16
According to spec, fmv.h checks if the input operands are correctly NaN-boxed. If not, the input value is treated as an n-bit canonical NaN. This patch fixs the issue that operands returned by soft-fp16 libgcc (i.e., __truncdfhf2) was not correctly NaN-boxed. *gcc/ChangeLog:* * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh with Nan-boxing value. * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern. *gcc/testsuite/ChangeLog:* gcc.target/riscv/_Float16-nanboxing.c: New test. 0001-RISC-V-Nan-box-the-result-of-movhf-on-soft-fp16.patch Description: Binary data
[RFC][V2] RISC-V: Support -mcmodel=large.
gcc/ChangeLog:
* gcc/config/riscv/predicates.md(move_operand): Check SYMBOL_REF
and LABEL_REF type.
(call_insn_operand): Support for CM_Large.
(pcrel_symbol_operand): New.
* gcc/config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add builtin_define
"__riscv_cmodel_large".
* gcc/config/riscv/riscv-opts.h (riscv_code_model): Define CM_LARGE.
* gcc/config/riscv/riscv-protos.h (riscv_symbol_type): Define
SYMBOL_FORCE_TO_MEM.
* gcc/config/riscv/riscv.cc (riscv_classify_symbol) Support CM_LARGE model.
(riscv_symbol_insns) Add SYMBOL_FORCE_TO_MEM.
(riscv_cannot_force_const_mem): Ditto.
(riscv_split_symbol): Ditto.
(riscv_force_address): Check pseudo reg available before force_reg.
(riscv_can_use_per_function_literal_pools_p): New.
(riscv_elf_select_rtx_section): Literal pool stays with the function.
(riscv_output_mi_thunk): Add riscv_in_thunk_func.
(riscv_option_override): Support CM_LARGE model.
(riscv_function_ok_for_sibcall): Disable sibcalls in CM_LARGE model.
* gcc/config/riscv/riscv.h (ASM_OUTPUT_POOL_EPILOGUE): Hookfg
* gcc/config/riscv/riscv.md (unspec): Define UNSPEC_FORCE_FOR_MEM.
(*large_load_address"): New.
* gcc/config/riscv/riscv.opt (code_model): New.
gcc/testsuite/ChangeLog:
* gcc/testsuite/gcc.target/riscv/large-model.c: New test.
Hi Jeff,
Thanks for your review.
> return (absolute_symbolic_oeprand (op, mode)> ||
> plt_symbolic_operand (op, mode)
>|| register_operand (op, mode);
Sorry for the unformatted indet. Fixed it at the V2 patch.
>> @@ -1972,7 +1992,19 @@ static rtx
>> riscv_force_address (rtx x, machine_mode mode)
>> {
>> if (!riscv_legitimate_address_p (mode, x, false))
>> -x = force_reg (Pmode, x);
>> +{
>> + if (can_create_pseudo_p ())
>> + return force_reg (Pmode, x);
> Note that $ra is fixed now. So if you need a scratch register, you can
> fall back to $ra.
> More importantly, what are the circumstances where you can be asked to
> force an address after the register allocation/reloading phase is
> complete? Or does it happen within the register allocators (the latter
> would be an indicator we need a secondary reload).
This address forcing is from riscv_output_mi_thunk:
insn = emit_call_insn (gen_sibcall (fnaddr, const0_rtx, callee_cc)).
This hook is called after IRA/LRA so it cannot use pseudo registers.
When compiler tries to expand 'sibcall', it calls
riscv_legitimize_call_address and 'fnaddr'
is not a legal call_insn_operand. Then, the address goes a
long-distance trip to legitimize.
Here is a example that using output thunks
===
class base
{
virtual int foo(int a);
};
class derived : public virtual base
{
virtual int foo(int a);
};
int base::foo(int a) { return a; }
int derived::foo(int a) { return a; }
base* make() { return new derived; }
===
>> riscv_in_small_data_p (const_tree x)
> How does large code model impact our ability to access small data
> through $gp? Aren't they independent?
I thought constant pool entries may be put into the small data section.
But it seems I was wrong. Removed this part at V2 patch.
>> + if ((offset & 3) && riscv_can_use_per_function_literal_pools_p ())
>> +ASM_OUTPUT_ALIGN (f, 2);
>> +}
> So the comment implies you're aligning the section. If that were the
> case, then why doesn't the function alignment come from
> FUNCTION_BOUNDARY when we first start emitting the function?
> Or is it the case that the comment is incorrect and you've actually got
> mixed code/rodata?
I forgot there is an alignment from FUNCTION_BOUNDARY. Removed this
part at V2 patch.
>> +(define_insn "*large_load_address"
>> + [(set (match_operand:DI 0 "register_operand" "=r")
>> +(mem:DI (match_operand 1 "pcrel_symbol_operand" "")))]
>> + "TARGET_64BIT && riscv_cmodel == CM_LARGE"
>> + "ld\t%0,%1"
>> + [(set_attr "type" "load")
>> + (set (attr "length") (const_int 8))])
> So it would seem like you're relying on the assembler to expand the ld?
> Is there any reasonable way to expose this properly to the compiler?
> I'd start by emitting the right instructions in the template. Once
> that's working, then we could look to split the components into distinct
> insns.
> I also worry that we've got a mem->reg move instruction that is not
> implemented in the standard movXX patterns. Traditionally that's been a
> recipe for problems. It was certainly a requirement for reload, but I
> don't know offhand if it's a hard requirement for LRA.
> Can you try to merge that in with the standard movdi pattern?
This is a tricky idea for loading the constant pool anchor.
The idea comes from the pattern '*local_pic_load'.
If removing this rtl pattern, GCC will generate 'lla a5,.LC0 + ld
a0,0(a5)' to get the anchor address.
But with this pattern, GCC can generate 'ld a0,.LC0'.
And the code generation is easier for the linker to relax.
> Overall it looks pretty good. Does Andestech have a copyright
> assignment in place? Or are you contributing under the DCO rule?
As Kito
Re: [RFC][V2] RISC-V: Support -mcmodel=large.
Sorry. It missed a semicolon in the previos patch. Please find the new one in the attachment. Thanks. 0001-RISC-V-Support-mcmodel-large.patch Description: Binary data
[PATCH][V2] RISC-V: Nan-box the result of movhf on soft-fp16
According to spec, fmv.h checks if the input operands are correctly NaN-boxed. If not, the input value is treated as an n-bit canonical NaN. This patch fixs the issue that operands returned by soft-fp16 libgcc (i.e., __truncdfhf2) was not correctly NaN-boxed. *gcc/ChangeLog:* * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh with Nan-boxing value. * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern. *gcc/testsuite/ChangeLog:* gcc.target/riscv/_Float16-nanboxing.c: New test. 0001-RISC-V-Nan-box-the-result-of-movhf-on-soft-fp16.patch Description: Binary data
[PATCH] RISC-V: Remove skip of decl in registered_function.
The GTY skip makes GGC clean the registered functions wrongly in lto. Example: riscv64-unknown-elf-gcc -flto gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c -O2 -march=rv64gcv In file included from bug-3.c:2: internal compiler error: Segmentation fault gcc/ChangeLog: *riscv-vector-builtins.cc (registered_function): Remove skip at decl. 0001-RISC-V-Remove-skip-of-decl-in-registered_function.patch Description: Binary data
[PATCH] RISC-V: Fix rvv builtin function groups registration asynchronously.
In the origin, cc1 registers rvv builtins with turn on all sub vector extensions but lto not. It makes lto use the asynchronous DECL_MD_FUNCTION_CODE from lto-objects. Example: riscv64-unknown-elf-gcc -flto gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c -O2 -march=rv64gcv bug-3.c: In function 'main': bug-3.c:10:3: error: invalid argument to built-in function 10 | __riscv_vse32_v_i32m1 (d, vd, 1); gcc/ChangeLog: * config/riscv/riscv-c.cc (riscv_pragma_intrinsic_flags_pollute): Move to riscv-vector-builtins.cc (riscv_pragma_intrinsic_flags_restore): Ditto (riscv_ext_version_value): Remove flags initialization. * config/riscv/riscv-vector-builtins.cc: (reinit_builtins): Remove handle_pragma_vector in lto_p. (riscv_pragma_intrinsic_flags_pollute): Cut from riscv-c.cc. (riscv_pragma_intrinsic_flags_restore): Ditto. (riscv_vector_push_setting): Backup flags. (riscv_vector_pop_setting): Restore flags. (handle_pragma_vector): Initialize flags for registering builtins. 0002-RISC-V-Fix-rvv-builtin-function-groups-registration-.patch Description: Binary data
[PATCH 2/3] Add one more argument to simulate_builtin_function_decl.
simulate_builtin_function_decl may return decl that be ggc_freed already in pushdecl when duplicate_decls is true. Add a argument CREATE_P for the caller to know if the return decl is usable. gcc/ChangeLog: * langhooks.h (simulate_builtin_function_decl): Add one more argument. * langhooks.cc (simulate_builtin_function_decl): Ditto. * config/aarch64/aarch64-builtins.cc (aarch64_general_simulate_builtin): Add one more argument to fit simulate_builtin_function_decl. (aarch64_init_simd_builtin_functions): Ditto. * config/aarch64/aarch64-sve-builtins.cc (function_builder::add_function): Ditto. * config/arm/arm-mve-builtins.cc (function_builder::add_function): Ditto. * config/riscv/riscv-vector-builtins.cc (function_builder::add_function): Ditto. 0002-Add-one-more-argument-to-simulate_builtin_function_d.patch Description: Binary data
[PATCH v2 1/3] RISC-V: Remove skip of decl in registered_function.
Hi Jeff, I'm really sorry for the regression failure. I missed one patch to fix these issues. Thanks for your review. The GTY skip makes GGC clean the registered functions wrongly in lto. Example: riscv64-unknown-elf-gcc -flto gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c -O2 -march=rv64gcv In file included from bug-10.c:2: internal compiler error: Segmentation fault gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (registered_function): Remove skip at decl. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/bug-10.c: New test. 0001-RISC-V-Remove-skip-of-decl-in-registered_function.patch Description: Binary data
[PATCH 3/3] RISC-V: Fix rvv builtin function groups registration
In the origin, cc1 registers rvv builtins with turn on all sub vector extensions but lto not. It makes lto use the asynchronous DECL_MD_FUNCTION_CODE from lto-objects. Example: riscv64-unknown-elf-gcc -flto gcc/testsuite/gcc.target/riscv/rvv/base/bug-10.c -O2 -march=rv64gcv bug-10.c: In function 'main': bug-10.c:10:3: error: invalid argument to built-in function 10 | __riscv_vse32_v_i32m1 (d, vd, 1); gcc/ChangeLog: * config/riscv/riscv-c.cc (riscv_pragma_intrinsic_flags_pollute): Move to riscv-vector-builtins.cc (riscv_pragma_intrinsic_flags_restore): Ditto (riscv_ext_version_value): Remove flags initialization. * config/riscv/riscv-vector-builtins.cc: (reinit_builtins): Remove handle_pragma_vector in lto_p. (riscv_pragma_intrinsic_flags_pollute): Cut from riscv-c.cc. (riscv_pragma_intrinsic_flags_restore): Ditto. (riscv_vector_push_setting): Backup flags. (riscv_vector_pop_setting): Restore flags. (handle_pragma_vector): Intialize flags for registering builtins. 0003-RISC-V-Fix-rvv-builtin-function-groups-registration-.patch Description: Binary data
Re: [PATCH] RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid
Hi Juzhe,
I think fault_load_def::get_name should remove "instance.pred ==
PRED_TYPE_mu", right?
於 2023年6月2日 週五 上午7:05寫道：
>
> From: Juzhe-Zhong
>
> Base on these:
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/232
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/233
>
> Add _mu C++ overloaded intrinsics for load && viota && vid.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-bases.cc: Add _mu overloaded
> intrinsics.
>
> ---
> gcc/config/riscv/riscv-vector-builtins-bases.cc | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index a8113f6602b..498c6ba042e 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -164,7 +164,7 @@ public:
>{
> if (STORE_P || LST_TYPE == LST_INDEXED)
>return true;
> -return pred != PRED_TYPE_none && pred != PRED_TYPE_mu;
> +return pred != PRED_TYPE_none;
>}
>
>rtx expand (function_expander &e) const override
> @@ -963,7 +963,7 @@ public:
>bool can_be_overloaded_p (enum predication_type_index pred) const override
>{
> return pred == PRED_TYPE_tu || pred == PRED_TYPE_tum
> - || pred == PRED_TYPE_tumu;
> + || pred == PRED_TYPE_tumu || pred == PRED_TYPE_mu;
>}
>
>rtx expand (function_expander &e) const override
> @@ -979,7 +979,7 @@ public:
>bool can_be_overloaded_p (enum predication_type_index pred) const override
>{
> return pred == PRED_TYPE_tu || pred == PRED_TYPE_tum
> - || pred == PRED_TYPE_tumu;
> + || pred == PRED_TYPE_tumu || pred == PRED_TYPE_mu;
>}
>
>rtx expand (function_expander &e) const override
> @@ -1749,7 +1749,7 @@ public:
>
>bool can_be_overloaded_p (enum predication_type_index pred) const override
>{
> -return pred != PRED_TYPE_none && pred != PRED_TYPE_mu;
> +return pred != PRED_TYPE_none;
>}
>
>rtx expand (function_expander &e) const override
> @@ -1794,7 +1794,7 @@ public:
>
>bool can_be_overloaded_p (enum predication_type_index pred) const override
>{
> -return pred != PRED_TYPE_none && pred != PRED_TYPE_mu;
> +return pred != PRED_TYPE_none;
>}
>
>rtx expand (function_expander &e) const override
> --
> 2.36.1
>
