Re: [PATCH] Change AVX512FP16 to AVX512-FP16 in the document.
On Sun, 29 Jan 2023, liuhongt wrote: > The official name is AVX512-FP16. > > Ready to push to trunk. > > gcc/ChangeLog: > > * config/i386/i386.opt: Change AVX512FP16 to AVX512-FP16. > * doc/invoke.texi: Ditto. Ok, thank you. (And okay to backport to older branches as/if you want.) Gerald
Re: [PATCH] Change AVX512FP16 to AVX512-FP16 which is official name.
On Sun, 29 Jan 2023, liuhongt wrote: > Ready to push to trunk. Yes, thank you. Gerald
[PATCH] driver, toplevel: Avoid emitting the version information twice.
Technically, this is seems to be a regression somewhere between 4.2 and
4.6 but, it seems, not enough for anyone to care too much. Tested on
various Darwin versions and x86_64, powerpc64 linux,
OK for trunk {now,stage1}?
thanks, Iain
--- 8< ---
For a regular compile job, with -v we emit the GCC version information
twice - once from main() and once from process_options(). We do not need
to emit the former unless the compiler will exit before calling
process_options(), which is controlled by the 'exit_after_options' flag.
Gating the first output on that flag resolves this.
Signed-off-by: Iain Sandoe
gcc/ChangeLog:
* toplev.cc (toplev::main): Only print the version information from
the toplevel main() if we will exit before processing options.
---
gcc/toplev.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/toplev.cc b/gcc/toplev.cc
index 42937f0ba00..8beaa2ab64d 100644
--- a/gcc/toplev.cc
+++ b/gcc/toplev.cc
@@ -2252,7 +2252,7 @@ toplev::main (int argc, char **argv)
initialize_plugins ();
- if (version_flag)
+ if (version_flag && exit_after_options)
print_version (stderr, "", true);
if (help_flag)
--
2.37.1 (Apple Git-137.1)
[PATCH V2 1/1] [fwprop]: Add the support of forwarding the vec_duplicate rtx
From: Lehua Ding
Hi Richard,
According to your previous comments, I adjusted the code. It will be easier (by
extend `get_inner_reg` function) to support the forwarding of new rtx operators
(e.g. sign-extend) in the future. Please help review this code, thank you so
much.
The current code doesn't take into account the possible increase in register
pressure, I'm going to spend a little more time understanding the
flag_ira_hoist_pressure you mentioned.
For the add of new target hook, I understand that it is still necessary. For
standard operators such as vec_duplicate, it can be processed in fwprop.cc.
However, when I was developing the RISC-V Vector Extension, I hope that the
following insn 9 can be forwarded into insn 10 (when other oeprands of
UNSPEC_RVV are same), so that there is only one instruction insn 11 bellow:
```
(insn 9 5 10 2 (parallel [
(set (reg/v:VNx4SI 134 [ va ])
(unspec:VNx4SI [
(const_int 0 [0])
(vec_duplicate:VNx4SI (subreg/s/u:SI (reg/v:DI 136 [ a
]) 0))
(reg/v:DI 138 [ vl ])
(const_int 9 [0x9])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_RVV))
(clobber (reg:DI 141))
]) "test3.c":5:25 10657 {vmvvnx4si_v_x_internal}
(nil))
(insn 10 9 14 2 (parallel [
(set (reg:VNx4SI 135 [ ])
(unspec:VNx4SI [
(unspec:VNx4SI [
(const_int 0 [0])
(plus:VNx4SI (reg/v:VNx4SI 134 [ va ])
(reg/v:VNx4SI 137 [ vb ]))
(const_int 0 [0])
] UNSPEC_SELECT)
(reg/v:DI 138 [ vl ])
(const_int 9 [0x9])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_RVV))
(clobber (reg:DI 142))
]) "test3.c":6:16 7983 {vaddvnx4si_vv}
(nil))
(insn 11 9 14 2 (parallel [
(set (reg:VNx4SI 135 [ ])
(unspec:VNx4SI [
(unspec:VNx4SI [
(const_int 0 [0])
(plus:VNx4SI
(vec_duplicate:VNx4SI (subreg/s/u:SI
(reg/v:DI 136 [ a ]) 0))
(reg/v:VNx4SI 137 [ vb ]))
(const_int 0 [0])
] UNSPEC_SELECT)
(reg/v:DI 138 [ vl ])
(const_int 9 [0x9])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_RVV))
(clobber (reg:DI 142))
]) "test3.c":6:16 7983 {vaddvnx4si_vv}
(nil))
```
The current very preliminary idea is to return the new src through HOOK `rtx
forward_src (rtx_insn *use_insn, rtx dest, rtx src)`, and return the incoming
src by default (that is, without modification), similar to the following
modification:
```
- rtx src = SET_SRC (def_set);
+ rtx src = targetm.forward_src (use->insn ()->rtl (), dest, SET_SRC
(def_set));
```
Best,
Lehua
gcc/ChangeLog:
* fwprop.cc (get_inner_reg): New utils function
(fwprop_propagation::profitable_p): Allow for more
(src_single_def_p): Add new function for src rtx
(forward_propagate_into): Change to new function call
---
gcc/fwprop.cc | 58 ---
1 file changed, 46 insertions(+), 12 deletions(-)
diff --git a/gcc/fwprop.cc b/gcc/fwprop.cc
index ae342f59407..a24d8724028 100644
--- a/gcc/fwprop.cc
+++ b/gcc/fwprop.cc
@@ -317,6 +317,21 @@ fwprop_propagation::folded_to_constants_p () const
return !(result_flags & UNSIMPLIFIED) && (result_flags & CONSTANT);
}
+/* Return the inner reg if x is wrappered by some specific operation. Like
+ VEC_DUPLICATE. It can be extended to let more specific operation be
+ forwarded. */
+
+rtx
+get_inner_reg (rtx x)
+{
+ switch (GET_CODE (x))
+{
+case VEC_DUPLICATE:
+ return XEXP (x, 0);
+default:
+ return x;
+}
+}
/* Return true if it is worth keeping the result of the propagation,
false if it would increase the complexity of the pattern too much. */
@@ -331,15 +346,17 @@ fwprop_propagation::profitable_p () const
&& (result_flags & PROFITABLE))
return true;
- if (REG_P (to))
+ rtx new_to = get_inner_reg (to);
+
+ if (REG_P (new_to))
return true;
- if (GET_CODE (to) == SUBREG
- && REG_P (SUBREG_REG (to))
- && !paradoxical_subreg_p (to))
+ if (GET_CODE (new_to) == SUBREG
+ && REG_P (SUBREG_REG (new_to))
+ && !paradoxical_subreg_p (new_to))
return true;
- if (CONSTANT_P (to))
+ if (CONSTANT_P (new_to))
return true;
return false;
@@ -353,6 +370,23 @@ reg_single_def_p (rtx x)
[PATCH] RISC-V: Add indexed loads/stores C/C++ intrinsic support
From: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-protos.h (get_vector_mode): New function.
* config/riscv/riscv-v.cc (get_vector_mode): Ditto.
* config/riscv/riscv-vector-builtins-bases.cc (enum lst_type): New enum.
(class loadstore): Adjust for indexed loads/stores support.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: New function declare.
* config/riscv/riscv-vector-builtins-functions.def (vluxei8): Ditto.
(vluxei16): Ditto.
(vluxei32): Ditto.
(vluxei64): Ditto.
(vloxei8): Ditto.
(vloxei16): Ditto.
(vloxei32): Ditto.
(vloxei64): Ditto.
(vsuxei8): Ditto.
(vsuxei16): Ditto.
(vsuxei32): Ditto.
(vsuxei64): Ditto.
(vsoxei8): Ditto.
(vsoxei16): Ditto.
(vsoxei32): Ditto.
(vsoxei64): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct
indexed_loadstore_def): New class.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc (required_extensions_p): Adjust
for indexed loads/stores support.
(check_required_extensions): Ditto.
(rvv_arg_type_info::get_base_vector_type): New function.
(rvv_arg_type_info::get_tree_type): Ditto.
(function_builder::add_unique_function): Adjust for indexed
loads/stores support.
(function_expander::use_exact_insn): New function.
* config/riscv/riscv-vector-builtins.h (enum rvv_base_type): Adjust for
indexed loads/stores support.
(struct rvv_arg_type_info): Ditto.
(function_expander::index_mode): New function.
(function_base::apply_tail_policy_p): Ditto.
(function_base::apply_mask_policy_p): Ditto.
* config/riscv/vector-iterators.md (unspec): New unspec.
* config/riscv/vector.md (unspec): Ditto.
(@pred_indexed_load): New
pattern.
(@pred_indexed_store): Ditto.
(@pred_indexed_load): Ditto.
(@pred_indexed_store): Ditto.
(@pred_indexed_load): Ditto.
(@pred_indexed_store): Ditto.
(@pred_indexed_load): Ditto.
(@pred_indexed_store): Ditto.
(@pred_indexed_load): Ditto.
(@pred_indexed_store): Ditto.
(@pred_indexed_load): Ditto.
(@pred_indexed_store): Ditto.
(@pred_indexed_load): Ditto.
(@pred_indexed_store): Ditto.
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-v.cc | 22 ++
.../riscv/riscv-vector-builtins-bases.cc | 92 +-
.../riscv/riscv-vector-builtins-bases.h | 16 +
.../riscv/riscv-vector-builtins-functions.def | 16 +
.../riscv/riscv-vector-builtins-shapes.cc | 49 +++
.../riscv/riscv-vector-builtins-shapes.h | 1 +
gcc/config/riscv/riscv-vector-builtins.cc | 249 +-
gcc/config/riscv/riscv-vector-builtins.h | 36 ++
gcc/config/riscv/vector-iterators.md | 87 +
gcc/config/riscv/vector.md| 309 +-
11 files changed, 845 insertions(+), 33 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 1facad74b3c..ceae4007fd1 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -172,6 +172,7 @@ enum mask_policy
enum tail_policy get_prefer_tail_policy ();
enum mask_policy get_prefer_mask_policy ();
rtx get_avl_type_rtx (enum avl_type);
+opt_machine_mode get_vector_mode (scalar_mode, poly_uint64);
}
/* We classify builtin types into two classes:
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 47f2cef459b..992b3437926 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -349,4 +349,26 @@ get_avl_type_rtx (enum avl_type type)
return gen_int_mode (type, Pmode);
}
+/* Return the RVV vector mode that has NUNITS elements of mode INNER_MODE.
+ This function is not only used by builtins, but also will be used by
+ auto-vectorization in the future. */
+opt_machine_mode
+get_vector_mode (scalar_mode inner_mode, poly_uint64 nunits)
+{
+ enum mode_class mclass;
+ if (inner_mode == E_BImode)
+mclass = MODE_VECTOR_BOOL;
+ else if (FLOAT_MODE_P (inner_mode))
+mclass = MODE_VECTOR_FLOAT;
+ else
+mclass = MODE_VECTOR_INT;
+ machine_mode mode;
+ FOR_EACH_MODE_IN_CLASS (mode, mclass)
+if (inner_mode == GET_MODE_INNER (mode)
+ && known_eq (nunits, GET_MODE_NUNITS (mode))
+ && riscv_v_ext_vector_mode_p (mode))
+ return mode;
+ return opt_machine_mode ();
+}
+
} // namespace riscv_vector
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index f9a16c68e07..129e89f443e 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -48,6 +48,16 @@ using namespace riscv_vector
[PATCH] RISC-V: Add VSETVL testcases for indexed loads/stores.
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/avl_single-72.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-76.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-77.c: New test.
---
.../riscv/rvv/vsetvl/avl_single-72.c | 27 +++
.../riscv/rvv/vsetvl/avl_single-76.c | 24 +
.../riscv/rvv/vsetvl/avl_single-77.c | 27 +++
3 files changed, 78 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
new file mode 100644
index 000..b1e28abd4fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+ size_t vl = 101;
+ for (size_t i = 0; i < n; i++)
+{
+ vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+ __riscv_vse8_v_i8mf8 (out + i, v, vl);
+
+ vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl);
+ __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl);
+}
+
+ for (size_t i = 0; i < n; i++)
+{
+ vuint8mf8_t index = __riscv_vle8_v_u8mf8 (in + i + 300, vl);
+ vfloat32mf2_t v2 = __riscv_vluxei8_v_f32mf2 (in + i + 200, index, vl);
+ __riscv_vse32_v_f32mf2 (out + i + 200, v2, vl);
+}
+}
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]} 1 { target { no-opts
"-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c
new file mode 100644
index 000..1b6e818d209
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+ size_t vl = 101;
+ for (size_t i = 0; i < n; i++)
+{
+ vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+ __riscv_vse8_v_i8mf8 (out + i, v, vl);
+}
+
+ for (size_t i = 0; i < n; i++)
+{
+ vuint8mf8_t index = __riscv_vle8_v_u8mf8 (in + i + 300, vl);
+ vfloat32mf2_t v = __riscv_vle32_v_f32mf2 (in + i + 600, vl);
+ __riscv_vsoxei8_v_f32mf2 (out + i + 200, index, v, vl);
+}
+}
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c
new file mode 100644
index 000..9fb16052385
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void f (void * restrict in, void * restrict out, int n, int cond)
+{
+ size_t vl = 101;
+ for (size_t i = 0; i < n; i++)
+{
+ vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
+ __riscv_vse8_v_i8mf8 (out + i, v, vl);
+}
+
+ for (size_t i = 0; i < n; i++)
+{
+ vbool64_t mask = __riscv_vlm_v_b64 (in + 1, vl);
+ vuint8mf8_t index = __riscv_vle8_v_u8mf8 (in + i + 300, vl);
+ vfloat32mf2_t v = __riscv_vle32_v_f32mf2 (in + i + 3, vl);
+ vfloat32mf2_t v2 = __riscv_vluxei8_v_f32mf2_tumu (mask, v, in + i + 200,
index, vl);
+ __riscv_vse32_v_f32mf2 (out + i + 200, v2, vl);
+}
+}
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts
"-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
no-opts "-g" no-opts "-funroll-loops" } } } } */
+
--
2.36.3
[PATCH] RISC-V: Add indexed loads/stores constraints testcases
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vlxei-vsxei-constraint-1.c: New test.
---
.../riscv/rvv/base/vlxei-vsxei-constraint-1.c | 121 ++
1 file changed, 121 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/vlxei-vsxei-constraint-1.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlxei-vsxei-constraint-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/vlxei-vsxei-constraint-1.c
new file mode 100644
index 000..56e599391fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlxei-vsxei-constraint-1.c
@@ -0,0 +1,121 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** f1:
+** vsetivli\s+zero,4,e32,mf2,tu,m[au]
+** vlse32\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero
+** vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero
+** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+
+** vsoxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+
+** ret
+*/
+void f1 (void * in, void * in2, void *out)
+{
+ vfloat32mf2_t v = __riscv_vlse32_v_f32mf2 (in, 0, 4);
+ vuint8mf8_t index = __riscv_vlse8_v_u8mf8 (in2, 0, 4);
+ vfloat32mf2_t v2 = __riscv_vluxei8_v_f32mf2_tu (v, in, index, 4);
+ __riscv_vsoxei8_v_f32mf2 (out, index, v2, 4);
+}
+
+/*
+** f2:
+** vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]
+** vlm\.v\s+v[0-9]+,\s*0\([a-x0-9]+\)
+** vsetivli\s+zero,4,e32,mf2,\s*t[au],\s*m[au]
+** vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero
+** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+,v0.t
+** vsoxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+
+** ret
+*/
+void f2 (void * in, void * in2, void *out)
+{
+ vbool64_t mask = *(vbool64_t*)in;
+ asm volatile ("":::"memory");
+ vfloat32mf2_t v = __riscv_vlse32_v_f32mf2 (in, 0, 4);
+ vuint8mf8_t index = __riscv_vlse8_v_u8mf8 (in2, 0, 4);
+ vfloat32mf2_t v2 = __riscv_vluxei8_v_f32mf2_m (mask, in, index, 4);
+ __riscv_vsoxei8_v_f32mf2 (out, index, v2, 4);
+}
+
+/*
+** f3:
+** vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]
+** vlm\.v\s+v[0-9]+,\s*0\([a-x0-9]+\)
+** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*tu,\s*mu
+** vlse32\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero
+** vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero
+** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+,v0.t
+** vsoxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+
+** ret
+*/
+void f3 (void * in, void * in2, void *out)
+{
+ vbool64_t mask = *(vbool64_t*)in;
+ asm volatile ("":::"memory");
+ vfloat32mf2_t v = __riscv_vlse32_v_f32mf2 (in, 0, 4);
+ vuint8mf8_t index = __riscv_vlse8_v_u8mf8 (in2, 0, 4);
+ vfloat32mf2_t v2 = __riscv_vluxei8_v_f32mf2_tumu (mask, v, in, index, 4);
+ __riscv_vsoxei8_v_f32mf2 (out, index, v2, 4);
+}
+
+/*
+** f4:
+** vsetivli\s+zero,4,e8,mf8,tu,\s*m[au]
+** vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),zero
+** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+
+** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+
+** vsoxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+
+** ret
+*/
+void f4 (void * in, void * in2, void *out)
+{
+ vuint8mf8_t index = __riscv_vlse8_v_u8mf8 (in2, 0, 4);
+ vint8mf8_t v = __riscv_vluxei8_v_i8mf8 (in, index, 4);
+ vint8mf8_t v2 = __riscv_vluxei8_v_i8mf8_tu (v, in, index, 4);
+ __riscv_vsoxei8_v_i8mf8 (out, index, v2, 4);
+}
+
+/*
+** f5:
+** vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]
+** vlm\.v\s+v[0-9]+,\s*0\([a-x0-9]+\)
+** vsetivli\s+zero,4,e8,mf8,t[au],m[au]
+** vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),zero
+** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+,v0.t
+** vsoxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+
+** ret
+*/
+void f5 (void * in, void * in2, void *out)
+{
+ vbool64_t mask = *(vbool64_t*)in;
+ asm volatile ("":::"memory");
+ vuint8mf8_t index = __riscv_vlse8_v_u8mf8 (in2, 0, 4);
+ vint8mf8_t v = __riscv_vluxei8_v_i8mf8 (in, index, 4);
+ vint8mf8_t v2 = __riscv_vluxei8_v_i8mf8_m (mask, in, index, 4);
+ __riscv_vsoxei8_v_i8mf8 (out, index, v2, 4);
+}
+
+/*
+** f6:
+** vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]
+** vlm\.v\s+v[0-9]+,\s*0\([a-x0-9]+\)
+** vsetivli\s+zero,4,e8,mf8,tu,mu
+** vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),zero
+** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+
+** vluxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+,v0.t
+** vsoxei8\.v\s+v[0-9]+,\s*\([a-x0-9]+\),\s*v[0-9]+
+** ret
+*/
+void f6 (void * in, void * in2, void *out)
+{
+ vbool64_t mask = *(vbool64_t*)in;
+ asm volatile ("":::"memory");
+ vuint8mf8_t index = __riscv_vlse8_v_u8mf8 (in2, 0, 4);
+ vint8mf8_t v = __riscv_vluxei8_v_i8mf8 (in, index, 4);
+ vint8mf8_t v2 = __riscv_vluxei8_v_i8mf8_tumu (mask, v, in, index, 4);
+ __riscv_vsoxei8_v_i8mf8 (out, index, v2, 4);
+}
--
2.36.3
[PATCH] fortran: Explicitly set name for *LOC default BACK argument [PR108450]
Hello,
this is a fix for a gcc-12 ICE regression.
This ICE rings a bell to me, and I think the change by Tobias which
triggers it only uncovers a bug that can also happen independently in
other cases.
The problem is resolution of maxloc expressions is not idempotent, that
is resolution changes the expression in such a way that it can't be
successfully resolved again.
I have not tried to prevent multiple resolutions, and fixed instead the
way the expression is changed. The patch explains the details.
No regression on x86_64-pc-linux-gnu.
OK for master and 12?From e61e2a51e1859f884125670010337f34265997b8 Mon Sep 17 00:00:00 2001
From: Mikael Morin
Date: Sun, 29 Jan 2023 14:38:08 +0100
Subject: [PATCH] fortran: Set name for *LOC default BACK argument [PR108450]
This change fixes an ICE caused by the double resolution of MINLOC,
MAXLOC and FINDLOC expressions which get a default value for the BACK
argument at resolution time. That argument is added without name,
and argument reordering code is not prepared to handle unnamed arguments
coming after named ones, so the second resolution causes a NULL pointer
dereference.
The problem is fixed by explicitly setting the argument name.
PR fortran/108450
gcc/fortran/ChangeLog:
* check.cc (gfc_check_minloc_maxloc): Explicitly set argument name.
(gfc_check_findloc): Ditto.
gcc/testsuite/ChangeLog:
* gfortran.dg/gomp/minmaxloc_1.f90: New test.
---
gcc/fortran/check.cc | 2 ++
.../gfortran.dg/gomp/minmaxloc_1.f90 | 32 +++
2 files changed, 34 insertions(+)
create mode 100644 gcc/testsuite/gfortran.dg/gomp/minmaxloc_1.f90
diff --git a/gcc/fortran/check.cc b/gcc/fortran/check.cc
index ebcb8f39852..8c1ae8c2f00 100644
--- a/gcc/fortran/check.cc
+++ b/gcc/fortran/check.cc
@@ -3888,6 +3888,7 @@ gfc_check_minloc_maxloc (gfc_actual_arglist *ap)
{
b = gfc_get_logical_expr (gfc_logical_4_kind, NULL, 0);
ap->next->next->next->next->expr = b;
+ ap->next->next->next->next->name = gfc_get_string ("back");
}
if (m == NULL && d != NULL && d->ts.type == BT_LOGICAL
@@ -3969,6 +3970,7 @@ gfc_check_findloc (gfc_actual_arglist *ap)
{
b = gfc_get_logical_expr (gfc_logical_4_kind, NULL, 0);
ap->next->next->next->next->next->expr = b;
+ ap->next->next->next->next->next->name = gfc_get_string ("back");
}
if (m == NULL && d != NULL && d->ts.type == BT_LOGICAL
diff --git a/gcc/testsuite/gfortran.dg/gomp/minmaxloc_1.f90 b/gcc/testsuite/gfortran.dg/gomp/minmaxloc_1.f90
new file mode 100644
index 000..b3691f774de
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/gomp/minmaxloc_1.f90
@@ -0,0 +1,32 @@
+! { dg-do compile }
+!
+! PR fortran/108450
+! This program used to cause an ICE because of the double resolution
+! of the maxloc expression and the addition of a hidden unnamed argument
+! during the first resolution.
+!
+! Original testcase from G. Steinmetz
+
+subroutine s1
+ integer :: a(8) = 0
+ integer :: l
+ integer :: n
+ !$omp atomic
+ n = maxloc(a, mask=l) ! { dg-error ".mask. argument of .maxloc. intrinsic at .1. must be LOGICAL" }
+end
+
+subroutine s2
+ integer :: a(8) = 0
+ integer :: l
+ integer :: n
+ !$omp atomic
+ n = minloc(a, mask=l) ! { dg-error ".mask. argument of .minloc. intrinsic at .1. must be LOGICAL" }
+end
+
+subroutine s3
+ integer :: a(8) = 0
+ integer :: l
+ integer :: n
+ !$omp atomic
+ n = findloc(a, 3, mask=l) ! { dg-error ".mask. argument of .findloc. intrinsic at .1. must be LOGICAL" }
+end
--
2.39.0
Re: [patch, fortran] PR103506 [10/11/12/13 Regression] ICE in gfc_free_namespace, at fortran/symbol.c
Le 29/01/2023 à 05:17, Jerry DeLisle via Fortran a écrit : Attached patch fixes this problem by allowing the namespace pointer to be set correctly regardless of error condition. Regression tested on x86_64_linux_gnu. OK for trunk and backports? Yes, thanks.
Re: [PATCH] fortran: Explicitly set name for *LOC default BACK argument [PR108450]
Hi Mikael, Am 29.01.23 um 17:21 schrieb Mikael Morin: Hello, this is a fix for a gcc-12 ICE regression. This ICE rings a bell to me, and I think the change by Tobias which triggers it only uncovers a bug that can also happen independently in other cases. The problem is resolution of maxloc expressions is not idempotent, that is resolution changes the expression in such a way that it can't be successfully resolved again. I have not tried to prevent multiple resolutions, and fixed instead the way the expression is changed. The patch explains the details. No regression on x86_64-pc-linux-gnu. OK for master and 12? yes, ok for both. Thanks for the patch! Harald
[PATCH] RISC-V: Add vsoxei8 && vsoxei16 C++ API intrinsic testcase
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsoxei16-1.C: New test.
* g++.target/riscv/rvv/base/vsoxei16-2.C: New test.
* g++.target/riscv/rvv/base/vsoxei16-3.C: New test.
* g++.target/riscv/rvv/base/vsoxei8-1.C: New test.
* g++.target/riscv/rvv/base/vsoxei8-2.C: New test.
* g++.target/riscv/rvv/base/vsoxei8-3.C: New test.
---
.../g++.target/riscv/rvv/base/vsoxei16-1.C| 660 +
.../g++.target/riscv/rvv/base/vsoxei16-2.C| 660 +
.../g++.target/riscv/rvv/base/vsoxei16-3.C| 660 +
.../g++.target/riscv/rvv/base/vsoxei8-1.C | 686 ++
.../g++.target/riscv/rvv/base/vsoxei8-2.C | 686 ++
.../g++.target/riscv/rvv/base/vsoxei8-3.C | 686 ++
6 files changed, 4038 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsoxei16-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsoxei16-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsoxei16-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsoxei8-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsoxei8-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsoxei8-3.C
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsoxei16-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vsoxei16-1.C
new file mode 100644
index 000..44737078711
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsoxei16-1.C
@@ -0,0 +1,660 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void test___riscv_vsoxei16(int8_t* base,vuint16mf4_t bindex,vint8mf8_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int8_t* base,vuint16mf2_t bindex,vint8mf4_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int8_t* base,vuint16m1_t bindex,vint8mf2_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int8_t* base,vuint16m2_t bindex,vint8m1_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int8_t* base,vuint16m4_t bindex,vint8m2_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int8_t* base,vuint16m8_t bindex,vint8m4_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int16_t* base,vuint16mf4_t bindex,vint16mf4_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int16_t* base,vuint16mf2_t bindex,vint16mf2_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int16_t* base,vuint16m1_t bindex,vint16m1_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int16_t* base,vuint16m2_t bindex,vint16m2_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int16_t* base,vuint16m4_t bindex,vint16m4_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int16_t* base,vuint16m8_t bindex,vint16m8_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int32_t* base,vuint16mf4_t bindex,vint32mf2_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int32_t* base,vuint16mf2_t bindex,vint32m1_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int32_t* base,vuint16m1_t bindex,vint32m2_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int32_t* base,vuint16m2_t bindex,vint32m4_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int32_t* base,vuint16m4_t bindex,vint32m8_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int64_t* base,vuint16mf4_t bindex,vint64m1_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int64_t* base,vuint16mf2_t bindex,vint64m2_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int64_t* base,vuint16m1_t bindex,vint64m4_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(int64_t* base,vuint16m2_t bindex,vint64m8_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(uint8_t* base,vuint16mf4_t bindex,vuint8mf8_t
value,size_t vl)
+{
+__riscv_vsoxei16(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei16(uint8_t* base,vuint16mf2_t bindex,vuint8mf4_t
v
[PATCH] RISC-V: Add vsoxei32 && vsoxei64 C++ API intrinsic testcase
From: Ju-Zhe Zhong
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsoxei32-1.C: New test.
* g++.target/riscv/rvv/base/vsoxei32-2.C: New test.
* g++.target/riscv/rvv/base/vsoxei32-3.C: New test.
* g++.target/riscv/rvv/base/vsoxei64-1.C: New test.
* g++.target/riscv/rvv/base/vsoxei64-2.C: New test.
* g++.target/riscv/rvv/base/vsoxei64-3.C: New test.
---
.../g++.target/riscv/rvv/base/vsoxei32-1.C| 608 ++
.../g++.target/riscv/rvv/base/vsoxei32-2.C| 608 ++
.../g++.target/riscv/rvv/base/vsoxei32-3.C| 608 ++
.../g++.target/riscv/rvv/base/vsoxei64-1.C| 518 +++
.../g++.target/riscv/rvv/base/vsoxei64-2.C| 518 +++
.../g++.target/riscv/rvv/base/vsoxei64-3.C| 518 +++
6 files changed, 3378 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsoxei32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsoxei32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsoxei32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsoxei64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsoxei64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsoxei64-3.C
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsoxei32-1.C
b/gcc/testsuite/g++.target/riscv/rvv/base/vsoxei32-1.C
new file mode 100644
index 000..3f39f889d1f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsoxei32-1.C
@@ -0,0 +1,608 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void test___riscv_vsoxei32(int8_t* base,vuint32mf2_t bindex,vint8mf8_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(int8_t* base,vuint32m1_t bindex,vint8mf4_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(int8_t* base,vuint32m2_t bindex,vint8mf2_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(int8_t* base,vuint32m4_t bindex,vint8m1_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(int8_t* base,vuint32m8_t bindex,vint8m2_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(int16_t* base,vuint32mf2_t bindex,vint16mf4_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(int16_t* base,vuint32m1_t bindex,vint16mf2_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(int16_t* base,vuint32m2_t bindex,vint16m1_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(int16_t* base,vuint32m4_t bindex,vint16m2_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(int16_t* base,vuint32m8_t bindex,vint16m4_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(int32_t* base,vuint32mf2_t bindex,vint32mf2_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(int32_t* base,vuint32m1_t bindex,vint32m1_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(int32_t* base,vuint32m2_t bindex,vint32m2_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(int32_t* base,vuint32m4_t bindex,vint32m4_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(int32_t* base,vuint32m8_t bindex,vint32m8_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(int64_t* base,vuint32mf2_t bindex,vint64m1_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(int64_t* base,vuint32m1_t bindex,vint64m2_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(int64_t* base,vuint32m2_t bindex,vint64m4_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(int64_t* base,vuint32m4_t bindex,vint64m8_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(uint8_t* base,vuint32mf2_t bindex,vuint8mf8_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(uint8_t* base,vuint32m1_t bindex,vuint8mf4_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(uint8_t* base,vuint32m2_t bindex,vuint8mf2_t
value,size_t vl)
+{
+__riscv_vsoxei32(base,bindex,value,vl);
+}
+
+
+void test___riscv_vsoxei32(uint8_t* base,vuint32m4_t bindex,vuint8m1_t
val
Re: [PATCH 0/6] PowerPC Dense Math prelimary support (-mcpu=future)
On Sat, Jan 28, 2023 at 02:29:04AM -0500, Michael Meissner wrote: > On Fri, Jan 27, 2023 at 01:59:00PM -0600, Segher Boessenkool wrote: > > > There is one bug that I noticed. When you use the full DMR instruction > > > the > > > constant copy propagation patch issues internal errors. I believe this > > > is due > > > to the CCP pass not handling opaque types cleanly enough, and it only > > > shows up > > > in larger types. I would like to get these patches committed, and then > > > work > > > the maintainers of the CCP to fix the problem. > > > > Erm. If the compiler ICEs, we can not include this code. But hopefully > > you mean something else? > > I realize we can't include the code for final release. But as a temporary > measure I was hoping we would put in the code, we could allow somebody more > familar with ccp to debug it. Then if there were changes needed in the > PowerPC > back end, we could make them, once ccp was fixed. > > But that is a moot point, ccp no longer dies with the code, so I have removed > the comment and the no tree ccp option in the next set of patches. Unfortunately, while it worked on my x86 as a cross compiler, when I did the builds for real, it is a problem, so I will need to look into it. -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com
Re: [PATCH] Fix PR 108582: ICE due to PHI-OPT removing a still in use ssa_name.
On Sat, Jan 28, 2023 at 11:25 PM Andrew Pinski via Gcc-patches
wrote:
>
> This patch adds a check in match_simplify_replacement to make sure the
> middlebb
> does not have any phi-nodes as we don't currently move those.
> This was just a thinko from before.
>
> Ok? Bootstrapped and tested on x86_64-linux-gnu with no regressions?
OK.
> PR tree-optimization/108582
>
> gcc/ChangeLog:
>
> * tree-ssa-phiopt.cc (match_simplify_replacement): Add check
> for middlebb to have no phi nodes.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/pr108582-1.c: New test.
> ---
> gcc/testsuite/gcc.dg/pr108582-1.c | 58 +++
> gcc/tree-ssa-phiopt.cc| 5 +++
> 2 files changed, 63 insertions(+)
> create mode 100644 gcc/testsuite/gcc.dg/pr108582-1.c
>
> diff --git a/gcc/testsuite/gcc.dg/pr108582-1.c
> b/gcc/testsuite/gcc.dg/pr108582-1.c
> new file mode 100644
> index 000..88c2de369ad
> --- /dev/null
> +++ b/gcc/testsuite/gcc.dg/pr108582-1.c
> @@ -0,0 +1,58 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O3 -fno-tree-ccp -fno-tree-dce" } */
> +
> +/*
> + PHI-OPT via match_simplify_replacement used to transform:
> + if (_25 != 0)
> +goto ; [25.00%]
> + else
> +goto ; [75.00%]
> +
> + [local count: 11649864]:
> + # iftmp.5_13 = PHI <2(7)>
> + k_22 = k_11 | iftmp.5_13;
> +
> + [local count: 105655256]:
> + # g_9 = PHI <1(2), 0(8), g_8(7)>
> + # k_12 = PHI
> +
> +into:
> +
> + _15 = (int) _25;
> + _28 = -_15;
> + _4 = _13 & _28;
> + _6 = _4 | k_11;
> +
> + [local count: 105655256]:
> + # g_9 = PHI <1(2), g_8(7)>
> + # k_12 = PHI
> +
> +Removing the phi-node/assignment of _13.
> +
> + */
> +
> +int a, c, d, e, f;
> +char b;
> +int main() {
> + int g = 1;
> + char h[1] = {0};
> + while (a) {
> +if (f) {
> + b = 0;
> + if (d)
> +continue;
> +}
> +if (a < 1) {
> + g = 0;
> + goto L;
> +}
> + }
> + while (c) {
> +char *j = h;
> +int k;
> + L:
> +if (e && !g)
> + k |= 2 | (*j < 0);
> + }
> + return 0;
> +}
> diff --git a/gcc/tree-ssa-phiopt.cc b/gcc/tree-ssa-phiopt.cc
> index c3a889dc593..a7ab6ce4ad9 100644
> --- a/gcc/tree-ssa-phiopt.cc
> +++ b/gcc/tree-ssa-phiopt.cc
> @@ -1002,6 +1002,11 @@ match_simplify_replacement (basic_block cond_bb,
> basic_block middle_bb,
>if (!single_pred_p (middle_bb))
> return false;
>
> + /* The middle bb cannot have phi nodes as we don't
> +move those assignments yet. */
> + if (!gimple_seq_empty_p (phi_nodes (middle_bb)))
> + return false;
> +
>stmt_to_move = last_and_only_stmt (middle_bb);
>if (!stmt_to_move)
> return false;
> --
> 2.31.1
>
Re: [PATCH] driver, toplevel: Avoid emitting the version information twice.
On Sun, Jan 29, 2023 at 12:35 PM Iain Sandoe via Gcc-patches
wrote:
>
> Technically, this is seems to be a regression somewhere between 4.2 and
> 4.6 but, it seems, not enough for anyone to care too much. Tested on
> various Darwin versions and x86_64, powerpc64 linux,
> OK for trunk {now,stage1}?
This will elide the earlier printing, right? I see
> ./cc1 -quiet t.c -version -v
GNU C17 (GCC) version 13.0.1 20230130 (experimental) (x86_64-pc-linux-gnu)
compiled by GNU C version 7.5.0, GMP version 6.1.2, MPFR
version 4.0.2-p6, MPC version 1.1.0, isl version isl-0.18-GMP
GGC heuristics: --param ggc-min-expand=30 --param ggc-min-heapsize=4096
ignoring nonexistent directory
"/usr/local/lib64/gcc/x86_64-pc-linux-gnu/13.0.1/include"
ignoring nonexistent directory
"/usr/local/lib64/gcc/x86_64-pc-linux-gnu/13.0.1/include-fixed"
ignoring nonexistent directory "/usr/local/lib64/../x86_64-pc-linux-gnu/include"
#include "..." search starts here:
#include <...> search starts here:
/usr/local/include
/usr/include
End of search list.
GNU C17 (GCC) version 13.0.1 20230130 (experimental) (x86_64-pc-linux-gnu)
compiled by GNU C version 7.5.0, GMP version 6.1.2, MPFR
version 4.0.2-p6, MPC version 1.1.0, isl version isl-0.18-GMP
GGC heuristics: --param ggc-min-expand=30 --param ggc-min-heapsize=4096
Compiler executable checksum: 04b9febc760f5d967341e708a5944221
eliding the 2nd would be prefered so the info comes first?
> thanks, Iain
>
> --- 8< ---
>
> For a regular compile job, with -v we emit the GCC version information
> twice - once from main() and once from process_options(). We do not need
> to emit the former unless the compiler will exit before calling
> process_options(), which is controlled by the 'exit_after_options' flag.
>
> Gating the first output on that flag resolves this.
>
> Signed-off-by: Iain Sandoe
>
> gcc/ChangeLog:
>
> * toplev.cc (toplev::main): Only print the version information from
> the toplevel main() if we will exit before processing options.
> ---
> gcc/toplev.cc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/toplev.cc b/gcc/toplev.cc
> index 42937f0ba00..8beaa2ab64d 100644
> --- a/gcc/toplev.cc
> +++ b/gcc/toplev.cc
> @@ -2252,7 +2252,7 @@ toplev::main (int argc, char **argv)
>
>initialize_plugins ();
>
> - if (version_flag)
> + if (version_flag && exit_after_options)
> print_version (stderr, "", true);
>
>if (help_flag)
> --
> 2.37.1 (Apple Git-137.1)
>
