Re: Adding a new thread model to GCC

[Jonathan Yong via Gcc-patches]

On 10/31/22 15:22, i.nixman--- via Gcc-patches wrote:

On 2022-10-31 09:18, Eric Botcazou wrote:

Hi Eric!

thank you very much for the job!
I will try to build our (MinGW-Builds project) builds using this patch 
and will report back.


@Jonathan

what the next steps to be taken to accept this patch?



I don't see any obvious problems with it, looks OK to me.

[r13-4764 Regression] FAIL: gfortran.dg/pr107397.f90 -O (test for excess errors) on Linux/x86_64

[haochen.jiang via Gcc-patches]

On Linux/x86_64,

09710f9934969dcb07131e1ed78b72e648123a3a is the first bad commit
commit 09710f9934969dcb07131e1ed78b72e648123a3a
Author: Steve Kargl 
Date:   Sat Dec 17 19:15:43 2022 -0800

Add a check for invalid use of BOZ with a derived type.

caused

FAIL: gfortran.dg/pr107397.f90   -O   (test for errors, line 7)
FAIL: gfortran.dg/pr107397.f90   -O  (test for excess errors)

with GCC configured with

../../gcc/configure 
--prefix=/export/users/haochenj/src/gcc-bisect/master/master/r13-4764/usr 
--enable-clocale=gnu --with-system-zlib --with-demangler-in-ld 
--with-fpmath=sse --enable-languages=c,c++,fortran --enable-cet --without-isl 
--enable-libmpx x86_64-linux --disable-bootstrap

To reproduce:

$ cd {build_dir}/gcc && make check 
RUNTESTFLAGS="dg.exp=gfortran.dg/pr107397.f90 --target_board='unix{-m32}'"
$ cd {build_dir}/gcc && make check 
RUNTESTFLAGS="dg.exp=gfortran.dg/pr107397.f90 --target_board='unix{-m32\ 
-march=cascadelake}'"
$ cd {build_dir}/gcc && make check 
RUNTESTFLAGS="dg.exp=gfortran.dg/pr107397.f90 --target_board='unix{-m64}'"
$ cd {build_dir}/gcc && make check 
RUNTESTFLAGS="dg.exp=gfortran.dg/pr107397.f90 --target_board='unix{-m64\ 
-march=cascadelake}'"

(Please do not reply to this email, for question about this report, contact me 
at haochen dot jiang at intel.com)

[PATCH v2 01/11] riscv: attr: Synchronize comments with code

[Christoph Muellner]

From: Christoph Müllner 

The comment above the enumeration of existing attributes got out of
order and a few entries were forgotten.
This patch synchronizes the comments according to the list.
This commit does not include any functional change.

gcc/ChangeLog:

* config/riscv/riscv.md: Sync comments with code.

Signed-off-by: Christoph Müllner 
---
 gcc/config/riscv/riscv.md | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index df57e2b0b4a..a8bb331f25c 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -220,7 +220,6 @@ (define_attr "enabled" "no,yes"
 ;; mfc transfer from coprocessor
 ;; const   load constant
 ;; arith   integer arithmetic instructions
-;; auipc   integer addition to PC
 ;; logical  integer logical instructions
 ;; shift   integer shift instructions
 ;; slt set less than instructions
@@ -236,9 +235,13 @@ (define_attr "enabled" "no,yes"
 ;; fcvtfloating point convert
 ;; fsqrt   floating point square root
 ;; multi   multiword sequence (or user asm statements)
+;; auipc   integer addition to PC
+;; sfb_alu  SFB ALU instruction
 ;; nop no operation
 ;; ghost   an instruction that produces no real code
 ;; bitmanipbit manipulation instructions
+;; rotate   rotation instructions
+;; atomic   atomic instructions
 ;; Classification of RVV instructions which will be added to each RVV .md 
pattern and used by scheduler.
 ;; rdvlenb vector byte length vlenb csrr read
 ;; rdvlvector length vl csrr read
-- 
2.38.1

[PATCH v2 00/11] RISC-V: Add XThead* extension support

[Christoph Muellner]

From: Christoph Müllner 

This series introduces support for the T-Head specific RISC-V ISA extensions
which are available e.g. on the T-Head XuanTie C906.

The ISA spec can be found here:
  https://github.com/T-head-Semi/thead-extension-spec

The series begins with two preparation patches, that do not introduce
any functional changes.  The first patch just fixes the comment order
to the code order.  And the second patch restructures the register
save/restore code in the CFA expansion, which simplifies the
XTheadMemPair patch.

This series adds basic support (i.e. awareness of the extension name and test
macro) for the following XThead* extensions:
* XTheadBa
* XTheadBb
* XTheadBs
* XTheadCmo
* XTheadCondMov
* XTheadFMemIdx
* XTheadFmv
* XTheadInt
* XTheadMac
* XTheadMemIdx
* XTheadMemPair
* XTheadSync

The series includes optimizations for most of these extensions
(the exceptions are XTheadInt and XTheadMemIdx).

The series also introduces support for "-mcpu=thead-c906", which also
enables all available XThead* ISA extensions of the T-Head C906.

All patches have been tested and don't introduce regressions for RV32 or
RV64. Therefore partial inclusion of this series is possible.

Christoph Müllner (10):
  riscv: attr: Synchronize comments with code
  riscv: Restructure callee-saved register save/restore code
  riscv: Add basic XThead* vendor extension support
  riscv: riscv-cores.def: Add T-Head XuanTie C906
  riscv: thead: Add support for the XTheadBa ISA extension
  riscv: thead: Add support for the XTheadBs ISA extension
  riscv: thead: Add support for th XTheadBb ISA extension
  riscv: thead: Add support for XTheadCondMov ISA extensions
  riscv: thead: Add support for XTheadMac ISA extension
  riscv: thead: Add support for XTheadFmv ISA extension

moiz.hussain (1):
  riscv: thead: Add support for XTheadMemPair ISA extension

 gcc/common/config/riscv/riscv-common.cc   |  26 +
 gcc/config/riscv/bitmanip.md  |  52 +-
 gcc/config/riscv/constraints.md   |   8 +
 gcc/config/riscv/iterators.md |   4 +
 gcc/config/riscv/peephole.md  | 298 ++
 gcc/config/riscv/predicates.md|   4 +
 gcc/config/riscv/riscv-cores.def  |   4 +
 gcc/config/riscv/riscv-opts.h |  26 +
 gcc/config/riscv/riscv-protos.h   |  11 +-
 gcc/config/riscv/riscv.cc | 919 --
 gcc/config/riscv/riscv.md |  72 +-
 gcc/config/riscv/riscv.opt|   3 +
 gcc/config/riscv/thead.md | 385 
 .../gcc.target/riscv/mcpu-thead-c906.c|  28 +
 .../gcc.target/riscv/xtheadba-addsl.c |  55 ++
 gcc/testsuite/gcc.target/riscv/xtheadba.c |  14 +
 gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c |  20 +
 .../gcc.target/riscv/xtheadbb-extu-2.c|  22 +
 .../gcc.target/riscv/xtheadbb-extu.c  |  22 +
 gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c |  18 +
 gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c |  45 +
 .../gcc.target/riscv/xtheadbb-srri.c  |  21 +
 gcc/testsuite/gcc.target/riscv/xtheadbb.c |  14 +
 gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c |  13 +
 gcc/testsuite/gcc.target/riscv/xtheadbs.c |  14 +
 gcc/testsuite/gcc.target/riscv/xtheadcmo.c|  14 +
 .../riscv/xtheadcondmov-mveqz-imm-eqz.c   |  38 +
 .../riscv/xtheadcondmov-mveqz-imm-not.c   |  38 +
 .../riscv/xtheadcondmov-mveqz-reg-eqz.c   |  38 +
 .../riscv/xtheadcondmov-mveqz-reg-not.c   |  38 +
 .../riscv/xtheadcondmov-mvnez-imm-cond.c  |  38 +
 .../riscv/xtheadcondmov-mvnez-imm-nez.c   |  38 +
 .../riscv/xtheadcondmov-mvnez-reg-cond.c  |  38 +
 .../riscv/xtheadcondmov-mvnez-reg-nez.c   |  38 +
 .../gcc.target/riscv/xtheadcondmov.c  |  14 +
 .../gcc.target/riscv/xtheadfmemidx.c  |  14 +
 .../gcc.target/riscv/xtheadfmv-fmv.c  |  24 +
 gcc/testsuite/gcc.target/riscv/xtheadfmv.c|  14 +
 gcc/testsuite/gcc.target/riscv/xtheadint.c|  14 +
 .../gcc.target/riscv/xtheadmac-mula-muls.c|  43 +
 gcc/testsuite/gcc.target/riscv/xtheadmac.c|  14 +
 gcc/testsuite/gcc.target/riscv/xtheadmemidx.c |  14 +
 .../gcc.target/riscv/xtheadmempair-1.c|  29 +
 .../gcc.target/riscv/xtheadmempair-10.c   |  36 +
 .../gcc.target/riscv/xtheadmempair-11.c   |  18 +
 .../gcc.target/riscv/xtheadmempair-12.c   |  20 +
 .../gcc.target/riscv/xtheadmempair-13.c   |  23 +
 .../gcc.target/riscv/xtheadmempair-14.c   |  30 +
 .../gcc.target/riscv/xtheadmempair-15.c   |  15 +
 .../gcc.target/riscv/xtheadmempair-16.c   |  18 +
 .../gcc.target/riscv/xtheadmempair-17.c   |  13 +
 .../gcc.target/riscv/xtheadmempair-18.c   |  49 +
 .../gcc.target/riscv/xtheadmempair-19.c   |  86 ++
 .../gcc.target/riscv/xtheadmempair-2.c|  26 +
 .../gcc.target/riscv/xtheadmempair-20.c   |  21 +
 .../gcc.target/riscv/xtheadmempair-3.c|  30 +
 .../gcc.target/riscv/x

[PATCH v2 02/11] riscv: Restructure callee-saved register save/restore code

[Christoph Muellner]

From: Christoph Müllner 

This patch restructures the loop over the GP registers
which saves/restores then as part of the prologue/epilogue.
No functional change is intended by this patch, but it
offers the possibility to use load-pair/store-pair instructions.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_next_saved_reg): New function.
(riscv_is_eh_return_data_register): New function.
(riscv_for_each_saved_reg): Restructure loop.

Signed-off-by: Christoph Müllner 
---
 gcc/config/riscv/riscv.cc | 94 +++
 1 file changed, 66 insertions(+), 28 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6dd2ab2d11e..a8d5e1dac7f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4835,6 +4835,49 @@ riscv_save_restore_reg (machine_mode mode, int regno,
   fn (gen_rtx_REG (mode, regno), mem);
 }
 
+/* Return the next register up from REGNO up to LIMIT for the callee
+   to save or restore.  OFFSET will be adjusted accordingly.
+   If INC is set, then REGNO will be incremented first.  */
+
+static unsigned int
+riscv_next_saved_reg (unsigned int regno, unsigned int limit,
+ HOST_WIDE_INT *offset, bool inc = true)
+{
+  if (inc)
+regno++;
+
+  while (regno <= limit)
+{
+  if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
+   {
+ *offset = *offset - UNITS_PER_WORD;
+ break;
+   }
+
+  regno++;
+}
+  return regno;
+}
+
+/* Return TRUE if provided REGNO is eh return data register.  */
+
+static bool
+riscv_is_eh_return_data_register (unsigned int regno)
+{
+  unsigned int i, regnum;
+
+  if (!crtl->calls_eh_return)
+return false;
+
+  for (i = 0; (regnum = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM; i++)
+if (regno == regnum)
+  {
+   return true;
+  }
+
+  return false;
+}
+
 /* Call FN for each register that is saved by the current function.
SP_OFFSET is the offset of the current stack pointer from the start
of the frame.  */
@@ -4844,36 +4887,31 @@ riscv_for_each_saved_reg (poly_int64 sp_offset, 
riscv_save_restore_fn fn,
  bool epilogue, bool maybe_eh_return)
 {
   HOST_WIDE_INT offset;
+  unsigned int regno;
+  unsigned int start = GP_REG_FIRST;
+  unsigned int limit = GP_REG_LAST;
 
   /* Save the link register and s-registers. */
-  offset = (cfun->machine->frame.gp_sp_offset - sp_offset).to_constant ();
-  for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
-if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
-  {
-   bool handle_reg = !cfun->machine->reg_is_wrapped_separately[regno];
-
-   /* If this is a normal return in a function that calls the eh_return
-  builtin, then do not restore the eh return data registers as that
-  would clobber the return value.  But we do still need to save them
-  in the prologue, and restore them for an exception return, so we
-  need special handling here.  */
-   if (epilogue && !maybe_eh_return && crtl->calls_eh_return)
- {
-   unsigned int i, regnum;
-
-   for (i = 0; (regnum = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM;
-i++)
- if (regno == regnum)
-   {
- handle_reg = FALSE;
- break;
-   }
- }
-
-   if (handle_reg)
- riscv_save_restore_reg (word_mode, regno, offset, fn);
-   offset -= UNITS_PER_WORD;
-  }
+  offset = (cfun->machine->frame.gp_sp_offset - sp_offset).to_constant ()
+  + UNITS_PER_WORD;
+  for (regno = riscv_next_saved_reg (start, limit, &offset, false);
+   regno <= limit;
+   regno = riscv_next_saved_reg (regno, limit, &offset))
+{
+  if (cfun->machine->reg_is_wrapped_separately[regno])
+   continue;
+
+  /* If this is a normal return in a function that calls the eh_return
+builtin, then do not restore the eh return data registers as that
+would clobber the return value.  But we do still need to save them
+in the prologue, and restore them for an exception return, so we
+need special handling here.  */
+  if (epilogue && !maybe_eh_return
+ && riscv_is_eh_return_data_register (regno))
+   continue;
+
+  riscv_save_restore_reg (word_mode, regno, offset, fn);
+}
 
   /* This loop must iterate over the same space as its companion in
  riscv_compute_frame_info.  */
-- 
2.38.1

[PATCH v2 04/11] riscv: riscv-cores.def: Add T-Head XuanTie C906

[Christoph Muellner]

From: Christoph Müllner 

This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906".
The C906 is shipped for quite some time (it is the core of the Allwinner D1).
Note, that the tuning struct for the C906 is already part of GCC (it is
also name "thead-c906").

gcc/ChangeLog:

* config/riscv/riscv-cores.def (RISCV_CORE): Add "thead-c906".

gcc/testsuite/ChangeLog:

* gcc.target/riscv/mcpu-thead-c906.c: New test.

Changes for v2:
- Enable all supported vendor extensions

Signed-off-by: Christoph Müllner 
---
 gcc/config/riscv/riscv-cores.def  |  4 +++
 .../gcc.target/riscv/mcpu-thead-c906.c| 28 +++
 2 files changed, 32 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 31ad34682c5..307381802fa 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -73,4 +73,8 @@ RISCV_CORE("sifive-s76",  "rv64imafdc", "sifive-7-series")
 RISCV_CORE("sifive-u54",  "rv64imafdc", "sifive-5-series")
 RISCV_CORE("sifive-u74",  "rv64imafdc", "sifive-7-series")
 
+RISCV_CORE("thead-c906",  
"rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
+ "xtheadcondmov_xtheadfmemidx_xtheadmac_"
+ "xtheadmemidx_xtheadmempair_xtheadsync",
+ "thead-c906")
 #undef RISCV_CORE
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c 
b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c
new file mode 100644
index 000..a71b43a6167
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=thead-c906" { target { rv64 } } } */
+/* T-Head XuanTie C906 => rv64imafdc */
+
+#if !((__riscv_xlen == 64) \
+  && !defined(__riscv_32e) \
+  && defined(__riscv_mul)  \
+  && defined(__riscv_atomic)   \
+  && (__riscv_flen == 64)  \
+  && defined(__riscv_compressed)   \
+  && defined(__riscv_xtheadba) \
+  && defined(__riscv_xtheadbb) \
+  && defined(__riscv_xtheadbs) \
+  && defined(__riscv_xtheadcmo)\
+  && defined(__riscv_xtheadcondmov)\
+  && defined(__riscv_xtheadfmemidx)\
+  && defined(__riscv_xtheadmac)\
+  && defined(__riscv_xtheadmemidx) \
+  && defined(__riscv_xtheadmempair)\
+  && defined(__riscv_xtheadsync))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+  return 0;
+}
-- 
2.38.1

[PATCH v2 06/11] riscv: thead: Add support for the XTheadBs ISA extension

[Christoph Muellner]

From: Christoph Müllner 

This patch adds support for the XTheadBs ISA extension.
The new INSN pattern is defined in a new file to separate
this vendor extension from the standard extensions.
The cost model adjustment reuses the xbs:bext cost.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_rtx_costs): Add xthead:tst cost.
* config/riscv/thead.md (*th_tst): New INSN.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/xtheadbs-tst.c: New test.

Signed-off-by: Christoph Müllner 
---
 gcc/config/riscv/riscv.cc |  4 ++--
 gcc/config/riscv/thead.md | 11 +++
 gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c | 13 +
 3 files changed, 26 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index a8d5e1dac7f..537515771c6 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2400,8 +2400,8 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
outer_code, int opno ATTRIBUTE_UN
  *total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
  return true;
}
-  /* bext pattern for zbs.  */
-  if (TARGET_ZBS && outer_code == SET
+  /* bit extraction pattern (zbs:bext, xtheadbs:tst).  */
+  if ((TARGET_ZBS || TARGET_XTHEADBS) && outer_code == SET
  && GET_CODE (XEXP (x, 1)) == CONST_INT
  && INTVAL (XEXP (x, 1)) == 1)
{
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 0257cbfad3e..0e23644ef59 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -29,3 +29,14 @@ (define_insn "*th_addsl"
   "th.addsl\t%0,%1,%3,%2"
   [(set_attr "type" "bitmanip")
(set_attr "mode" "")])
+
+;; XTheadBs
+
+(define_insn "*th_tst"
+  [(set (match_operand:X 0 "register_operand" "=r")
+   (zero_extract:X (match_operand:X 1 "register_operand" "r")
+   (const_int 1)
+   (match_operand 2 "immediate_operand" "i")))]
+  "TARGET_XTHEADBS"
+  "th.tst\t%0,%1,%2"
+  [(set_attr "type" "bitmanip")])
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c 
b/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c
new file mode 100644
index 000..674cec09128
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadbs" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadbs" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+long
+foo1 (long i)
+{
+  return 1L & (i >> 20);
+}
+
+/* { dg-final { scan-assembler-times "th.tst\t" 1 } } */
+/* { dg-final { scan-assembler-not "andi" } } */
-- 
2.38.1

[PATCH v2 07/11] riscv: thead: Add support for th XTheadBb ISA extension

[Christoph Muellner]

From: Christoph Müllner 

This patch adds support for the XTheadBb ISA extension.
Thus, there is a functional overlap of the new instructions with
existing Bitmanip instruction, which allows a good amount of code
sharing. However, the vendor extensions are cleanly separated from
the standard extensions (e.g. by using INSN expand pattern that
will re-emit RTL that matches the patterns of either Bitmanip or
XThead INSNs).

gcc/ChangeLog:

* config/riscv/bitmanip.md (clzdi2): New expand.
(clzsi2): New expand.
(ctz2): New expand.
(popcount2): New expand.
(si2): Rename INSN.
(*si2): Hide INSN name.
(di2): Rename INSN.
(*di2): Hide INSN name.
(rotrsi3): Remove INSN.
(rotr3): Add expand.
(*rotrsi3): New INSN.
(rotrdi3): Rename INSN.
(*rotrdi3): Hide INSN name.
(rotrsi3_sext): Rename INSN.
(*rotrsi3_sext): Hide INSN name.
(bswap2): Remove INSN.
(bswapdi2): Add expand.
(bswapsi2): Add expand.
(*bswap2): Hide INSN name.
* config/riscv/riscv.cc (riscv_rtx_costs): Add costs for sign
extraction.
* config/riscv/riscv.md (extv): New expand.
(extzv): New expand.
* config/riscv/thead.md (*th_srrisi3): New INSN.
(*th_srridi3): New INSN.
(*th_ext): New INSN.
(*th_extu): New INSN.
(*th_clz2): New INSN.
(*th_revsi2): New INSN.
(*th_revdi2): New INSN.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/xtheadbb-ext.c: New test.
* gcc.target/riscv/xtheadbb-extu-2.c: New test.
* gcc.target/riscv/xtheadbb-extu.c: New test.
* gcc.target/riscv/xtheadbb-ff1.c: New test.
* gcc.target/riscv/xtheadbb-rev.c: New test.
* gcc.target/riscv/xtheadbb-srri.c: New test.

Changes for v2:
- Merge all XTheadB* support patches
- Remove useless operand sanity checks for extv and extzv
- Prefer c.andi over th.extu if possible
- Add ff1 tests for clz/ctz
- Fix ext/extu test cases
- Enable tests for RV32

Signed-off-by: Christoph Müllner 
---
 gcc/config/riscv/bitmanip.md  | 52 +--
 gcc/config/riscv/riscv.cc |  9 +++
 gcc/config/riscv/riscv.md | 20 ++
 gcc/config/riscv/thead.md | 66 +++
 gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c | 20 ++
 .../gcc.target/riscv/xtheadbb-extu-2.c| 22 +++
 .../gcc.target/riscv/xtheadbb-extu.c  | 22 +++
 gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c | 18 +
 gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c | 45 +
 .../gcc.target/riscv/xtheadbb-srri.c  | 21 ++
 10 files changed, 289 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index d17133d58c1..70e72a35d7d 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -185,6 +185,26 @@ (define_insn "*slliuw"
 
 ;; ZBB extension.
 
+(define_expand "clzdi2"
+  [(set (match_operand:DI 0 "register_operand")
+   (clz:DI (match_operand:DI 1 "register_operand")))]
+  "TARGET_64BIT && (TARGET_ZBB || TARGET_XTHEADBB)")
+
+(define_expand "clzsi2"
+  [(set (match_operand:SI 0 "register_operand")
+   (clz:SI (match_operand:SI 1 "register_operand")))]
+  "TARGET_ZBB || (!TARGET_64BIT && TARGET_XTHEADBB)")
+
+(define_expand "ctz2"
+  [(set (match_operand:GPR 0 "register_operand")
+   (ctz:GPR (match_operand:GPR 1 "register_operand")))]
+  "TARGET_ZBB")
+
+(define_expand "popcount2"
+  [(set (match_operand:GPR 0 "register_operand")
+   (popcount:GPR (match_operand:GPR 1 "register_operand")))]
+  "TARGET_ZBB")
+
 (define_insn "*_not"
   [(set (match_operand:X 0 "register_operand" "=r")
 (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
@@ -216,7 +236,7 @@ (define_insn "*xor_not"
   [(set_attr "type" "bitmanip")
(set_attr "mode" "")])
 
-(define_insn "si2"
+(define_insn "*si2"
   [(set (match_operand:SI 0 "register_operand" "=r")
 (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))]
   "TARGET_ZBB"
@@ -233,7 +253,7 @@ (define_insn "*disi2"
   [(set_attr "type" "bitmanip")
(set_attr "mode" "SI")])
 
-(define_insn "di2"
+(define_insn "*di2"
   [(set (match_operand:DI 0 "register_operand" "=r")
 (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))]
   "TARGET_64BIT && TARGET_ZBB"
@@ -273,7 +293,17 @@ (define_insn "*zero_extendhi2_zbb"
   [(set_attr "type" "bitmanip,load")
(set_attr "mode" "HI")])

[PATCH v2 03/11] riscv: Add basic XThead* vendor extension support

[Christoph Muellner]

From: Christoph Müllner 

This patch add basic support for the following XThead* ISA extensions:

* XTheadBa
* XTheadBb
* XTheadBs
* XTheadCmo
* XTheadCondMov
* XTheadFMemIdx
* XTheadFmv
* XTheadInt
* XTheadMac
* XTheadMemIdx
* XTheadMemPair
* XTheadSync

The extensions are just recognized by the compiler and feature test
macros are generated (which this patch also brings tests for).

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add xthead* extensions.
* config/riscv/riscv-opts.h (MASK_XTHEADBA): New.
(TARGET_XTHEADBA): New.
(MASK_XTHEADBB): New.
(TARGET_XTHEADBB): New.
(MASK_XTHEADBS): New.
(TARGET_XTHEADBS): New.
(MASK_XTHEADCMO): New.
(TARGET_XTHEADCMO): New.
(MASK_XTHEADCONDMOV): New.
(TARGET_XTHEADCONDMOV): New.
(MASK_XTHEADFMEMIDX): New.
(TARGET_XTHEADFMEMIDX): New.
(MASK_XTHEADFMV): New.
(TARGET_XTHEADFMV): New.
(MASK_XTHEADINT): New.
(TARGET_XTHEADINT): New.
(MASK_XTHEADMAC): New.
(TARGET_XTHEADMAC): New.
(MASK_XTHEADMEMIDX): New.
(TARGET_XTHEADMEMIDX): New.
(MASK_XTHEADMEMPAIR): New.
(TARGET_XTHEADMEMPAIR): new.
(MASK_XTHEADSYNC): New.
(TARGET_XTHEADSYNC): New.
* config/riscv/riscv.opt: Add riscv_xthead_subext.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/xtheadba.c: New test.
* gcc.target/riscv/xtheadbb.c: New test.
* gcc.target/riscv/xtheadbs.c: New test.
* gcc.target/riscv/xtheadcmo.c: New test.
* gcc.target/riscv/xtheadcondmov.c: New test.
* gcc.target/riscv/xtheadfmemidx.c: New test.
* gcc.target/riscv/xtheadfmv.c: New test.
* gcc.target/riscv/xtheadint.c: New test.
* gcc.target/riscv/xtheadmac.c: New test.
* gcc.target/riscv/xtheadmemidx.c: New test.
* gcc.target/riscv/xtheadmempair.c: New test.
* gcc.target/riscv/xtheadsync.c: New test.

Signed-off-by: Christoph Müllner 
---
 gcc/common/config/riscv/riscv-common.cc   | 26 +++
 gcc/config/riscv/riscv-opts.h | 26 +++
 gcc/config/riscv/riscv.opt|  3 +++
 gcc/testsuite/gcc.target/riscv/xtheadba.c | 14 ++
 gcc/testsuite/gcc.target/riscv/xtheadbb.c | 14 ++
 gcc/testsuite/gcc.target/riscv/xtheadbs.c | 14 ++
 gcc/testsuite/gcc.target/riscv/xtheadcmo.c| 14 ++
 .../gcc.target/riscv/xtheadcondmov.c  | 14 ++
 .../gcc.target/riscv/xtheadfmemidx.c  | 14 ++
 gcc/testsuite/gcc.target/riscv/xtheadfmv.c| 14 ++
 gcc/testsuite/gcc.target/riscv/xtheadint.c| 14 ++
 gcc/testsuite/gcc.target/riscv/xtheadmac.c| 14 ++
 gcc/testsuite/gcc.target/riscv/xtheadmemidx.c | 14 ++
 .../gcc.target/riscv/xtheadmempair.c  | 13 ++
 gcc/testsuite/gcc.target/riscv/xtheadsync.c   | 14 ++
 15 files changed, 222 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcmo.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadint.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadsync.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 4b7f777c103..84f7de8a16e 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -222,6 +222,19 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
   {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadbs", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadcmo", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadcondmov", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadfmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadfmv", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadint", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadmac", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -1247,6 +1260,19 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
   {"svnapot", &gcc_optio

[PATCH v2 05/11] riscv: thead: Add support for the XTheadBa ISA extension

[Christoph Muellner]

From: Christoph Müllner 

This patch adds support for the XTheadBa ISA extension.
The new INSN pattern is defined in a new file to separate
this vendor extension from the standard extensions.

gcc/ChangeLog:

* config/riscv/riscv.md: Include thead.md
* config/riscv/thead.md: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/xtheadba-addsl.c: New test.

Signed-off-by: Christoph Müllner 
---
 gcc/config/riscv/riscv.md |  1 +
 gcc/config/riscv/thead.md | 31 +++
 .../gcc.target/riscv/xtheadba-addsl.c | 55 +++
 3 files changed, 87 insertions(+)
 create mode 100644 gcc/config/riscv/thead.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index a8bb331f25c..571349b1ca5 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3073,4 +3073,5 @@ (define_insn "riscv_prefetchi_"
 (include "pic.md")
 (include "generic.md")
 (include "sifive-7.md")
+(include "thead.md")
 (include "vector.md")
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
new file mode 100644
index 000..0257cbfad3e
--- /dev/null
+++ b/gcc/config/riscv/thead.md
@@ -0,0 +1,31 @@
+;; Machine description for T-Head vendor extensions
+;; Copyright (C) 2021-2022 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+;; XTheadBa
+
+(define_insn "*th_addsl"
+  [(set (match_operand:X 0 "register_operand" "=r")
+   (plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
+ (match_operand:QI 2 "immediate_operand" "I"))
+   (match_operand:X 3 "register_operand" "r")))]
+  "TARGET_XTHEADBA
+   && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)"
+  "th.addsl\t%0,%1,%3,%2"
+  [(set_attr "type" "bitmanip")
+   (set_attr "mode" "")])
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c 
b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c
new file mode 100644
index 000..5004735a246
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadba" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadba" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+long
+test_1 (long a, long b)
+{
+  /* th.addsl aX, aX, 1  */
+  return a + (b << 1);
+}
+
+int
+foos (short *x, int n)
+{
+  /* th.addsl aX, aX, 1  */
+  return x[n];
+}
+
+long
+test_2 (long a, long b)
+{
+  /* th.addsl aX, aX, 2  */
+  return a + (b << 2);
+}
+
+int
+fooi (int *x, int n)
+{
+  /* th.addsl aX, aX, 2  */
+  return x[n];
+}
+
+long
+test_3 (long a, long b)
+{
+  /* th.addsl aX, aX, 3  */
+  return a + (b << 3);
+}
+
+long
+fool (long *x, int n)
+{
+  /* th.addsl aX, aX, 2 (rv32)  */
+  /* th.addsl aX, aX, 3 (rv64)  */
+  return x[n];
+}
+
+/* { dg-final { scan-assembler-times "th.addsl\[ 
\t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,1" 2 } } */
+
+/* { dg-final { scan-assembler-times "th.addsl\[ 
\t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,2" 3 { target { rv32 } } } } */
+/* { dg-final { scan-assembler-times "th.addsl\[ 
\t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,2" 2 { target { rv64 } } } } */
+
+/* { dg-final { scan-assembler-times "th.addsl\[ 
\t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,3" 1 { target { rv32 } } } } */
+/* { dg-final { scan-assembler-times "th.addsl\[ 
\t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,3" 2 { target { rv64 } } } } */
-- 
2.38.1

[PATCH v2 08/11] riscv: thead: Add support for XTheadCondMov ISA extensions

[Christoph Muellner]

From: Christoph Müllner 

This patch adds support for XTheadCondMov ISA extension.
The extension brings a one-sided conditional move (no else-assignment).
Given that GCC has a great if-conversion pass, we don't need to do much,
besides properly expanding movcc accordingly and adjust the cost
model.

gcc/ChangeLog:

* config/riscv/iterators.md (TARGET_64BIT): Add GPR2 iterator.
* config/riscv/riscv-protos.h (riscv_expand_conditional_move):
Add prototype.
* config/riscv/riscv.cc (riscv_rtx_costs): Add costs for
XTheadCondMov.
(riscv_expand_conditional_move): New function.
(riscv_expand_conditional_move_onesided): New function.
* config/riscv/riscv.md: Add support for XTheadCondMov.
* config/riscv/thead.md (*th_cond_mov): Add
support for XTheadCondMov.
(*th_cond_gpr_mov): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c: New test.
* gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c: New test.
* gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c: New test.
* gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c: New test.
* gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c: New test.
* gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c: New test.
* gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c: New test.
* gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c: New test.

Changes for v2:
- Properly gate expansion constraints to avoid failing INSN lookup
- Restrict subreg comparisons

Signed-off-by: Christoph Müllner 
---
 gcc/config/riscv/iterators.md |   4 +
 gcc/config/riscv/riscv-protos.h   |   2 +-
 gcc/config/riscv/riscv.cc | 100 +++---
 gcc/config/riscv/riscv.md |  17 ++-
 gcc/config/riscv/thead.md |  37 +++
 .../riscv/xtheadcondmov-mveqz-imm-eqz.c   |  38 +++
 .../riscv/xtheadcondmov-mveqz-imm-not.c   |  38 +++
 .../riscv/xtheadcondmov-mveqz-reg-eqz.c   |  38 +++
 .../riscv/xtheadcondmov-mveqz-reg-not.c   |  38 +++
 .../riscv/xtheadcondmov-mvnez-imm-cond.c  |  38 +++
 .../riscv/xtheadcondmov-mvnez-imm-nez.c   |  38 +++
 .../riscv/xtheadcondmov-mvnez-reg-cond.c  |  38 +++
 .../riscv/xtheadcondmov-mvnez-reg-nez.c   |  38 +++
 13 files changed, 440 insertions(+), 24 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c

diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index efdd3ccc9a7..1c5f3dd5681 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -26,6 +26,10 @@
 ;; from the same template.
 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
 
+;; A copy of GPR that can be used when a pattern has two independent
+;; modes.
+(define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
+
 ;; This mode iterator allows :P to be used for patterns that operate on
 ;; pointer-sized quantities.  Exactly one of the two alternatives will match.
 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index e17e003f8e2..7975bc4f438 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -58,8 +58,8 @@ extern const char *riscv_output_return ();
 extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx);
 extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx);
 extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx);
-extern void riscv_expand_conditional_move (rtx, rtx, rtx, rtx_code, rtx, rtx);
 #endif
+extern bool riscv_expand_conditional_move (rtx, rtx, rtx, rtx);
 extern rtx riscv_legitimize_call_address (rtx);
 extern void riscv_set_return_address (rtx, rtx);
 extern bool riscv_expand_block_move (rtx, rtx, rtx);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index b57c1f1d727..21ec7a6225b 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2300,8 +2300,8 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
outer_code, int opno ATTRIBUTE_UN
   return false;
 
 case IF_THEN_ELSE:
-  if (TARGET_SFB_ALU
- && register_operand (XEXP (x, 1), mode)
+  if ((TARGET_SFB_ALU || TARGET_XTHEADCONDMOV)
+ && reg_or_0_operand 

[PATCH v2 09/11] riscv: thead: Add support for XTheadMac ISA extension

[Christoph Muellner]

From: Christoph Müllner 

The XTheadMac ISA extension provides multiply-accumulate/subtract
instructions:
* mula/mulaw/mulah
* muls/mulsw/mulsh

To benefit from middle-end passes, we expand the following named
patterns in riscv.md (as they are not T-Head-specific):
* maddhisi4
* msubhisi4

gcc/ChangeLog:

* config/riscv/riscv.md (maddhisi4): New expand.
(msubhisi4): New expand.
* config/riscv/thead.md (*th_mula): New pattern.
(*th_mulawsi): New pattern.
(*th_mulawsi2): New pattern.
(*th_maddhisi4): New pattern.
(*th_sextw_maddhisi4): New pattern.
(*th_muls): New pattern.
(*th_mulswsi): New pattern.
(*th_mulswsi2): New pattern.
(*th_msubhisi4): New pattern.
(*th_sextw_msubhisi4): New pattern.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/thead-mula-muls.c: New test.

Co-Developed-by: Xianmiao Qu 
Signed-off-by: Xianmiao Qu 
Signed-off-by: Christoph Müllner 

Changed in v2:
- Add missing prefix in on INSN
---
 gcc/config/riscv/riscv.md |  18 +++
 gcc/config/riscv/thead.md | 121 ++
 .../gcc.target/riscv/xtheadmac-mula-muls.c|  43 +++
 3 files changed, 182 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac-mula-muls.c

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 34327bfb01f..20506451e7c 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3086,6 +3086,24 @@ (define_expand "extzv"
 FAIL;
 })
 
+(define_expand "maddhisi4"
+  [(set (match_operand:SI 0 "register_operand")
+   (plus:SI
+ (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand"))
+  (sign_extend:SI (match_operand:HI 2 "register_operand")))
+ (match_operand:SI 3 "register_operand")))]
+  "TARGET_XTHEADMAC"
+)
+
+(define_expand "msubhisi4"
+  [(set (match_operand:SI 0 "register_operand")
+   (minus:SI
+ (match_operand:SI 3 "register_operand")
+ (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand"))
+  (sign_extend:SI (match_operand:HI 2 "register_operand")]
+  "TARGET_XTHEADMAC"
+)
+
 (include "bitmanip.md")
 (include "sync.md")
 (include "peephole.md")
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 9f03d1d43b4..d9cac15cc5f 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -143,3 +143,124 @@ (define_insn "*th_cond_gpr_mov"
th.mveqz\t%0,%z3,%1"
   [(set_attr "type" "condmove")
(set_attr "mode" "")])
+
+;; XTheadMac
+
+(define_insn "*th_mula"
+  [(set (match_operand:X 0 "register_operand" "=r")
+ (plus:X (mult:X (match_operand:X 1 "register_operand" "r")
+ (match_operand:X 2 "register_operand" "r"))
+ (match_operand:X 3 "register_operand" "0")))]
+  "TARGET_XTHEADMAC"
+  "th.mula\\t%0,%1,%2"
+  [(set_attr "type" "imul")
+   (set_attr "mode" "")]
+)
+
+(define_insn "*th_mulawsi"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+   (sign_extend:DI
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r"))
+  (match_operand:SI 3 "register_operand" "0"]
+  "TARGET_XTHEADMAC && TARGET_64BIT"
+  "th.mulaw\\t%0,%1,%2"
+  [(set_attr "type" "imul")
+   (set_attr "mode" "SI")]
+)
+
+(define_insn "*th_mulawsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
+   (match_operand:SI 2 "register_operand" "r"))
+  (match_operand:SI 3 "register_operand" "0")))]
+  "TARGET_XTHEADMAC && TARGET_64BIT"
+  "th.mulaw\\t%0,%1,%2"
+  [(set_attr "type" "imul")
+   (set_attr "mode" "SI")]
+)
+
+(define_insn "*th_maddhisi4"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+ (plus:SI
+   (mult:SI
+ (sign_extend:SI (match_operand:HI 1 "register_operand" " r"))
+ (sign_extend:SI (match_operand:HI 2 "register_operand" " r")))
+   (match_operand:SI 3 "register_operand" " 0")))]
+  "TARGET_XTHEADMAC"
+  "th.mulah\\t%0,%1,%2"
+  [(set_attr "type" "imul")
+   (set_attr "mode" "SI")]
+)
+
+(define_insn "*th_sextw_maddhisi4"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+   (sign_extend:DI
+ (plus:SI
+   (mult:SI
+ (sign_extend:SI (match_operand:HI 1 "register_operand" " r"))
+ (sign_extend:SI (match_operand:HI 2 "register_operand" " r")))
+   (match_operand:SI 3 "register_operand" " 0"]
+  "TARGET_XTHEADMAC && TARGET_64BIT"
+  "th.mulah\\t%0,%1,%2"
+  [(set_attr "type" "imul")
+   (set_attr "mode" "SI")]
+)
+
+(define_insn "*th_muls"
+  [(set (match_operand:X 0 "register_operand" "=r")
+ (minus:X (match_operand:X 3 "register_operand" "0")
+  (mult:X (ma

[PATCH v2 10/11] riscv: thead: Add support for XTheadFmv ISA extension

[Christoph Muellner]

From: Christoph Müllner 

The XTheadFmv ISA extension provides instructions to move
data between 32-bit GP registers and 64-bit FP registers.

gcc/ChangeLog:

* config/riscv/constraints.md (TARGET_XTHEADFMV ? FP_REGS : NO_REGS)
New constraint "th_f_fmv".
(TARGET_XTHEADFMV ? GR_REGS : NO_REGS): New constraint
"th_r_fmv".
* config/riscv/riscv.cc (riscv_split_doubleword_move):
Add split code for XTheadFmv.
(riscv_secondary_memory_needed): XTheadFmv does not need
secondary memory.
* config/riscv/riscv.md: Add new UNSPEC_XTHEADFMV and
UNSPEC_XTHEADFMV_HW. Add support for XTheadFmv to
movdf_hardfloat_rv32.
* config/riscv/thead.md (th_fmv_hw_w_x): New INSN.
(th_fmv_x_w): New INSN.
(th_fmv_x_hw): New INSN.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/xtheadfmv-fmv.c: New test.

Co-Developed-by: Xianmiao Qu 
Signed-off-by: Xianmiao Qu 
Signed-off-by: Christoph Müllner 
---
 gcc/config/riscv/constraints.md   |  8 +
 gcc/config/riscv/riscv.cc | 25 --
 gcc/config/riscv/riscv.md | 11 +--
 gcc/config/riscv/thead.md | 33 +++
 .../gcc.target/riscv/xtheadfmv-fmv.c  | 24 ++
 5 files changed, 95 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 51cffb2bcb6..f3b1af774e1 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -156,3 +156,11 @@ (define_constraint "Wdm"
   "Vector duplicate memory operand"
   (and (match_operand 0 "memory_operand")
(match_code "reg" "0")))
+
+;; Vendor ISA extension constraints.
+
+(define_register_constraint "th_f_fmv" "TARGET_XTHEADFMV ? FP_REGS : NO_REGS"
+  "A floating-point register for XTheadFmv.")
+
+(define_register_constraint "th_r_fmv" "TARGET_XTHEADFMV ? GR_REGS : NO_REGS"
+  "An integer register for XTheadFmv.")
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 21ec7a6225b..fc18ce2c766 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2754,11 +2754,29 @@ riscv_split_64bit_move_p (rtx dest, rtx src)
 void
 riscv_split_doubleword_move (rtx dest, rtx src)
 {
-  rtx low_dest;
+  /* XTheadFmv has instructions for accessing the upper bits of a double.  */
+  if (!TARGET_64BIT && TARGET_XTHEADFMV)
+{
+  if (FP_REG_RTX_P (dest))
+   {
+ rtx low_src = riscv_subword (src, false);
+ rtx high_src = riscv_subword (src, true);
+ emit_insn (gen_th_fmv_hw_w_x (dest, high_src, low_src));
+ return;
+   }
+  if (FP_REG_RTX_P (src))
+   {
+ rtx low_dest = riscv_subword (dest, false);
+ rtx high_dest = riscv_subword (dest, true);
+ emit_insn (gen_th_fmv_x_w (low_dest, src));
+ emit_insn (gen_th_fmv_x_hw (high_dest, src));
+ return;
+   }
+}
 
/* The operation can be split into two normal moves.  Decide in
   which order to do them.  */
-   low_dest = riscv_subword (dest, false);
+   rtx low_dest = riscv_subword (dest, false);
if (REG_P (low_dest) && reg_overlap_mentioned_p (low_dest, src))
  {
riscv_emit_move (riscv_subword (dest, true), riscv_subword (src, true));
@@ -5752,7 +5770,8 @@ riscv_secondary_memory_needed (machine_mode mode, 
reg_class_t class1,
 {
   return (!riscv_v_ext_vector_mode_p (mode)
  && GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD
- && (class1 == FP_REGS) != (class2 == FP_REGS));
+ && (class1 == FP_REGS) != (class2 == FP_REGS)
+ && !TARGET_XTHEADFMV);
 }
 
 /* Implement TARGET_REGISTER_MOVE_COST.  */
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 20506451e7c..ef6ae443059 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -100,6 +100,10 @@ (define_c_enum "unspecv" [
 
   ;; Zihintpause unspec
   UNSPECV_PAUSE
+
+  ;; XTheadFmv unspec
+  UNSPEC_XTHEADFMV
+  UNSPEC_XTHEADFMV_HW
 ])
 
 (define_constants
@@ -1836,16 +1840,17 @@ (define_expand "movdf"
 DONE;
 })
 
+
 ;; In RV32, we lack fmv.x.d and fmv.d.x.  Go through memory instead.
 ;; (However, we can still use fcvt.d.w to zero a floating-point register.)
 (define_insn "*movdf_hardfloat_rv32"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,  *r,*r,*m")
-   (match_operand:DF 1 "move_operand" " f,G,m,f,G,*r*G,*m,*r"))]
+  [(set (match_operand:DF 0 "nonimmediate_operand" 
"=f,f,f,m,m,*th_f_fmv,*th_r_fmv,  *r,*r,*m")
+   (match_operand:DF 1 "move_operand" " 
f,G,m,f,G,*th_r_fmv,*th_f_fmv,*r*G,*m,*r"))]
   "!TARGET_64BIT && TARGET_DOUBLE_FLOAT
&& (register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))"
   { return riscv_output_move (operands[0], operands[1]); }
-  [(set_attr "move_type"

[PATCH v2 11/11] riscv: thead: Add support for XTheadMemPair ISA extension

[Christoph Muellner]

From: "moiz.hussain" 

The XTheadMemPair ISA extension provides load/store pair instructions:
* th.ldd
* th.sdd
* th.lwd
* th.lwud
* th.swd

This patch adds the following unnamed patterns to the peephole.md stage,
which take care of reordering loads/stores appropriately:
* load/store pair patterns for 4 instructions
* load/store pair patterns for 2 instructions

The generation of the load/store-pair instructions (based on ordered
load/store sequences) is inspired by the approaches of other backends.

The CFA expansion (save/restore registers on/from stack) is done quite
late, therefore it needs special-treatment. This patch tries to minimize
the impact for the default case and follows the pattern of other
backends.

gcc/ChangeLog:

* config/riscv/peephole.md: New load/store pair ordering
peephole optimizations.
* config/riscv/predicates.md (reg_or_const_operand): New
predicate.
* config/riscv/riscv-protos.h (riscv_load_store_bonding_p_2instr):
New prototype.
(riscv_load_store_bonding_p_4instr): Likewise.
(riscv_ldrstr_offset_compare): Likewise.
(extract_base_offset_in_addr): Likewise.
(th_riscv_output_mempair_move): Likewise.
(th_riscv_gen_adjusted_mempair): Likewise.
* config/riscv/riscv.cc (extract_base_offset_in_addr): New function.
(riscv_split_plus): Likewise.
(th_riscv_output_mempair_move): Likewise.
(riscv_load_store_bonding_p_4instr): Likewise.
(riscv_load_store_bonding_p_2instr): Likewise.
(riscv_ldrstr_offset_compare): Likewise.
(th_riscv_gen_adjusted_mempair): Likewise.
(riscv_save_reg): Moved before new uses.
(riscv_restore_reg): Moved before new uses.
(riscv_for_each_saved_reg): Adjusted for load/store-pair support
in CFA expansion.
* config/riscv/thead.md (th_mov_mempair_): New INSN.
(th_mov_mempair_di_si_zero_ext): New INSN.
(th_mov_mempair_di_si_sign_ext): New INSN.
(th_mov_mempair_si_si_zero_ext): New INSN.
(th_mov_mempair_si_si_sign_ext): New INSN.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/xtheadmempair-1.c: New test.
* gcc.target/riscv/xtheadmempair-10.c: New test.
* gcc.target/riscv/xtheadmempair-11.c: New test.
* gcc.target/riscv/xtheadmempair-12.c: New test.
* gcc.target/riscv/xtheadmempair-13.c: New test.
* gcc.target/riscv/xtheadmempair-14.c: New test.
* gcc.target/riscv/xtheadmempair-15.c: New test.
* gcc.target/riscv/xtheadmempair-16.c: New test.
* gcc.target/riscv/xtheadmempair-17.c: New test.
* gcc.target/riscv/xtheadmempair-18.c: New test.
* gcc.target/riscv/xtheadmempair-19.c: New test.
* gcc.target/riscv/xtheadmempair-2.c: New test.
* gcc.target/riscv/xtheadmempair-20.c: New test.
* gcc.target/riscv/xtheadmempair-3.c: New test.
* gcc.target/riscv/xtheadmempair-4.c: New test.
* gcc.target/riscv/xtheadmempair-5.c: New test.
* gcc.target/riscv/xtheadmempair-6.c: New test.
* gcc.target/riscv/xtheadmempair-7.c: New test.
* gcc.target/riscv/xtheadmempair-8.c: New test.
* gcc.target/riscv/xtheadmempair-9.c: New test.
* gcc.target/riscv/xtheadmempair-helper.h: New test.

Co-Developed-by: Christoph Müllner 
Signed-off-by: Christoph Müllner 
Signed-off-by: M. Moiz Hussain 
Signed-off-by: Christoph Müllner 
---
 gcc/config/riscv/peephole.md  | 298 
 gcc/config/riscv/predicates.md|   4 +
 gcc/config/riscv/riscv-protos.h   |   9 +
 gcc/config/riscv/riscv.cc | 701 +-
 gcc/config/riscv/thead.md |  86 +++
 .../gcc.target/riscv/xtheadmempair-1.c|  29 +
 .../gcc.target/riscv/xtheadmempair-10.c   |  36 +
 .../gcc.target/riscv/xtheadmempair-11.c   |  18 +
 .../gcc.target/riscv/xtheadmempair-12.c   |  20 +
 .../gcc.target/riscv/xtheadmempair-13.c   |  23 +
 .../gcc.target/riscv/xtheadmempair-14.c   |  30 +
 .../gcc.target/riscv/xtheadmempair-15.c   |  15 +
 .../gcc.target/riscv/xtheadmempair-16.c   |  18 +
 .../gcc.target/riscv/xtheadmempair-17.c   |  13 +
 .../gcc.target/riscv/xtheadmempair-18.c   |  49 ++
 .../gcc.target/riscv/xtheadmempair-19.c   |  86 +++
 .../gcc.target/riscv/xtheadmempair-2.c|  26 +
 .../gcc.target/riscv/xtheadmempair-20.c   |  21 +
 .../gcc.target/riscv/xtheadmempair-3.c|  30 +
 .../gcc.target/riscv/xtheadmempair-4.c|  20 +
 .../gcc.target/riscv/xtheadmempair-5.c|  21 +
 .../gcc.target/riscv/xtheadmempair-6.c|  19 +
 .../gcc.target/riscv/xtheadmempair-7.c|  22 +
 .../gcc.target/riscv/xtheadmempair-8.c|  29 +
 .../gcc.target/riscv/xtheadmempair-9.c|  37 +
 .../gcc.target/riscv/xtheadmempair-helper.h   |  52 ++
 26 files changed, 1680 insertions(+), 32 deletions(-)
 create m

Re: [PATCH v2 01/11] riscv: attr: Synchronize comments with code

[Kito Cheng via Gcc-patches]

LGTM, you can commit this separately if you want :)

On Mon, Dec 19, 2022 at 9:09 AM Christoph Muellner
 wrote:
>
> From: Christoph Müllner 
>
> The comment above the enumeration of existing attributes got out of
> order and a few entries were forgotten.
> This patch synchronizes the comments according to the list.
> This commit does not include any functional change.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Sync comments with code.
>
> Signed-off-by: Christoph Müllner 
> ---
>  gcc/config/riscv/riscv.md | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index df57e2b0b4a..a8bb331f25c 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -220,7 +220,6 @@ (define_attr "enabled" "no,yes"
>  ;; mfc transfer from coprocessor
>  ;; const   load constant
>  ;; arith   integer arithmetic instructions
> -;; auipc   integer addition to PC
>  ;; logical  integer logical instructions
>  ;; shift   integer shift instructions
>  ;; slt set less than instructions
> @@ -236,9 +235,13 @@ (define_attr "enabled" "no,yes"
>  ;; fcvtfloating point convert
>  ;; fsqrt   floating point square root
>  ;; multi   multiword sequence (or user asm statements)
> +;; auipc   integer addition to PC
> +;; sfb_alu  SFB ALU instruction
>  ;; nop no operation
>  ;; ghost   an instruction that produces no real code
>  ;; bitmanipbit manipulation instructions
> +;; rotate   rotation instructions
> +;; atomic   atomic instructions
>  ;; Classification of RVV instructions which will be added to each RVV .md 
> pattern and used by scheduler.
>  ;; rdvlenb vector byte length vlenb csrr read
>  ;; rdvlvector length vl csrr read
> --
> 2.38.1
>

Re: [PATCH] RISC-V: Add testcases for VSETVL PASS

[Kito Cheng via Gcc-patches]

Hi Jeff:

> Ah, I should have looked at those regexps closer.  Understood about the
> checking for hoisting the vsetvl.  Though it makes me wonder if we'd be
> better off dumping information out of the vsetvl pass.


I've discussed adding an extra verify pass and a kind of rating
mechnish to vsetvli pass with Ju-Zhe,
so that we don't need to do such asm scan, which is relatively fragile
to broken.

And we'll implement that in the next few weeks :)

Thanks

[RFC/RFT 0/3] Add compiler support for Control Flow Integrity

[Dan Li via Gcc-patches]

This series of patches is mainly used to support the control flow
integrity protection of the linux kernel [1], which is similar to
-fsanitize=kcfi in clang 16.0 [2,3].

I hope that this feature will also support user-mode CFI in the
future (at least for developers who can recompile the runtime),
so I use -fsanitize=cfi as a compilation option here.

Any suggestion please let me know :).

Thanks, Dan.

[1] 
https://lore.kernel.org/all/20220908215504.3686827-1-samitolva...@google.com/
[2] https://clang.llvm.org/docs/ControlFlowIntegrity.html
[3] https://reviews.llvm.org/D119296

Dan Li (3):
  [PR102768] flag-types.h (enum sanitize_code): Extend sanitize_code to
64 bits to support more features
  [PR102768] Support CFI: Add new pass for Control Flow Integrity
  [PR102768] aarch64: Add support for Control Flow Integrity

Signed-off-by: Dan Li 

---
 gcc/Makefile.in   |   1 +
 gcc/asan.h|   4 +-
 gcc/c-family/c-attribs.cc |  10 +-
 gcc/c-family/c-common.h   |   2 +-
 gcc/c/c-parser.cc |   4 +-
 gcc/cgraphunit.cc |  34 +++
 gcc/common.opt|   4 +-
 gcc/config/aarch64/aarch64.cc | 106 
 gcc/cp/typeck.cc  |   2 +-
 gcc/doc/invoke.texi   |  35 +++
 gcc/doc/passes.texi   |  10 +
 gcc/doc/tm.texi   |  27 +++
 gcc/doc/tm.texi.in|   8 +
 gcc/dwarf2asm.cc  |   2 +-
 gcc/flag-types.h  |  67 ++---
 gcc/opt-suggestions.cc|   2 +-
 gcc/opts.cc   |  26 +-
 gcc/opts.h|   8 +-
 gcc/output.h  |   3 +
 gcc/passes.def|   1 +
 gcc/target.def|  39 +++
 .../aarch64/control_flow_integrity_1.c|  14 ++
 .../aarch64/control_flow_integrity_2.c|  25 ++
 .../aarch64/control_flow_integrity_3.c|  23 ++
 gcc/toplev.cc |   4 +
 gcc/tree-cfg.cc   |   2 +-
 gcc/tree-cfi.cc   | 229 ++
 gcc/tree-pass.h   |   1 +
 gcc/tree.cc   | 144 +++
 gcc/tree.h|   1 +
 gcc/varasm.cc |  29 +++
 31 files changed, 803 insertions(+), 64 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/control_flow_integrity_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/control_flow_integrity_2.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/control_flow_integrity_3.c
 create mode 100644 gcc/tree-cfi.cc

-- 
2.17.1