[PATCH v1 0/2] Optimize immediate load. Add prefetch insns.

[Lulu Cheng]

1. The problem mentioned in the link does not move the four immediate load
   instructions out of the loop. It has been optimized. Now, as in the test 
case,
   four immediate load instructions are generated outside the loop.
   (https://sourceware.org/pipermail/libc-alpha/2022-September/142202.html)

2. Add prefetch insns.

*** BLURB HERE ***

Lulu Cheng (2):
  LoongArch: Optimize immediate load.
  LoongArch: Add prefetch insns.

 gcc/config/loongarch/constraints.md   |   7 +-
 gcc/config/loongarch/loongarch-def.c  |   2 +
 gcc/config/loongarch/loongarch-protos.h   |   1 +
 gcc/config/loongarch/loongarch-tune.h |   1 +
 gcc/config/loongarch/loongarch.cc | 143 ++
 gcc/config/loongarch/loongarch.h  |   6 +
 gcc/config/loongarch/loongarch.md |  49 ++
 gcc/config/loongarch/predicates.md|   8 +
 gcc/testsuite/gcc.target/loongarch/imm-load.c |  25 +++
 9 files changed, 208 insertions(+), 34 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/imm-load.c

-- 
2.31.1

[PATCH v1 2/2] LoongArch: Add prefetch insns.

[Lulu Cheng]

Co-Authored-By: xujiahao 

gcc/ChangeLog:

* config/loongarch/loongarch-def.c: Initial number of parallel prefetch.
* config/loongarch/loongarch-protos.h (loongarch_prefetch_cookie):
Function declaration.
* config/loongarch/loongarch-tune.h (struct loongarch_cache):
Define number of parallel prefetch.
* config/loongarch/loongarch.cc (loongarch_option_override_internal):
Set up parameters to be used in prefetching algorithm.
(loongarch_prefetch_cookie): Select load or store based on the value of 
write.
* config/loongarch/loongarch.md (prefetch): New template.
(*prefetch_indexed_): New template.
---
 gcc/config/loongarch/loongarch-def.c|  2 ++
 gcc/config/loongarch/loongarch-protos.h |  1 +
 gcc/config/loongarch/loongarch-tune.h   |  1 +
 gcc/config/loongarch/loongarch.cc   | 48 +
 gcc/config/loongarch/loongarch.md   | 23 
 5 files changed, 75 insertions(+)

diff --git a/gcc/config/loongarch/loongarch-def.c 
b/gcc/config/loongarch/loongarch-def.c
index cbf995d81b5..80ab10a52a8 100644
--- a/gcc/config/loongarch/loongarch-def.c
+++ b/gcc/config/loongarch/loongarch-def.c
@@ -62,11 +62,13 @@ loongarch_cpu_cache[N_TUNE_TYPES] = {
   .l1d_line_size = 64,
   .l1d_size = 64,
   .l2d_size = 256,
+  .simultaneous_prefetches = 4,
   },
   [CPU_LA464] = {
   .l1d_line_size = 64,
   .l1d_size = 64,
   .l2d_size = 256,
+  .simultaneous_prefetches = 4,
   },
 };
 
diff --git a/gcc/config/loongarch/loongarch-protos.h 
b/gcc/config/loongarch/loongarch-protos.h
index 77b2217247d..489525b520e 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -179,5 +179,6 @@ extern tree loongarch_builtin_decl (unsigned int, bool);
 extern rtx loongarch_expand_builtin (tree, rtx, rtx subtarget ATTRIBUTE_UNUSED,
 machine_mode, int);
 extern tree loongarch_build_builtin_va_list (void);
+extern rtx loongarch_prefetch_cookie (rtx, rtx);
 
 #endif /* ! GCC_LOONGARCH_PROTOS_H */
diff --git a/gcc/config/loongarch/loongarch-tune.h 
b/gcc/config/loongarch/loongarch-tune.h
index 6f3530f5c02..8e3eb29472b 100644
--- a/gcc/config/loongarch/loongarch-tune.h
+++ b/gcc/config/loongarch/loongarch-tune.h
@@ -45,6 +45,7 @@ struct loongarch_cache {
 int l1d_line_size;  /* bytes */
 int l1d_size;   /* KiB */
 int l2d_size;   /* kiB */
+int simultaneous_prefetches; /* number of parallel prefetch */
 };
 
 #endif /* LOONGARCH_TUNE_H */
diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 5e8cd293645..d663afe434d 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -63,6 +63,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "context.h"
 #include "builtins.h"
 #include "rtl-iter.h"
+#include "params.h"
 
 /* This file should be included last.  */
 #include "target-def.h"
@@ -6126,6 +6127,33 @@ loongarch_option_override_internal (struct gcc_options 
*opts)
   if (loongarch_branch_cost == 0)
 loongarch_branch_cost = loongarch_cost->branch_cost;
 
+  /* Set up parameters to be used in prefetching algorithm. */
+  maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
+
loongarch_cpu_cache[LARCH_ACTUAL_TUNE].simultaneous_prefetches,
+opts->x_param_values,
+opts_set->x_param_values);
+
+  maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
+loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l1d_line_size,
+opts->x_param_values,
+opts_set->x_param_values);
+
+  maybe_set_param_value (PARAM_L1_CACHE_SIZE,
+loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l1d_size,
+opts->x_param_values,
+opts_set->x_param_values);
+
+  maybe_set_param_value (PARAM_L2_CACHE_SIZE,
+loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l2d_size,
+opts->x_param_values,
+opts_set->x_param_values);
+
+  /* Enable sw prefetching at -O3 and higher. */
+  if (opts->x_flag_prefetch_loop_arrays < 0
+  && (opts->x_optimize >= 3 || opts->x_flag_profile_use)
+  && !opts->x_optimize_size)
+opts->x_flag_prefetch_loop_arrays = 1;
+
   if (TARGET_DIRECT_EXTERN_ACCESS && flag_shlib)
 error ("%qs cannot be used for compiling a shared library",
   "-mdirect-extern-access");
@@ -6506,6 +6534,26 @@ loongarch_asan_shadow_offset (void)
   return TARGET_64BIT ? (HOST_WIDE_INT_1 << 46) : 0;
 }
 
+/* LoongArch only implements preld hint=0 (prefetch for load) and hint=8
+   (prefetch for store), other hint just scale to hint = 0 and hint = 1. */
+
+rtx
+loongarch_prefetch_cookie (rtx write, rtx locality)
+{
+  if (INTVAL (locality) == 1 && INTVAL (write) == 0)
+return GEN_INT (INTVAL (write)

[PATCH v1 1/2] LoongArch: Optimize immediate load.

[Lulu Cheng]

Fixed an issue where the compiler would not take four 64-bit immediate
load instructions out of the loop.

gcc/ChangeLog:

* config/loongarch/constraints.md (x): New constraint.
* config/loongarch/loongarch.cc (struct loongarch_integer_op):
Define a new member curr_value, that records the value of
the number stored in the destination register immediately
after the current instruction has run.
(loongarch_build_integer): Adds a method to load the immediate
32-bit to 63-bit field.
(loongarch_move_integer): Same as above.
* config/loongarch/loongarch.h (HWIT_UC_0x):
(HI32_OPERAND): NEW macro.
* config/loongarch/loongarch.md (load_hi32):New template.
* config/loongarch/predicates.md (const_hi32_operand): Determines
whether the value is an immediate number that has a value of only
the higher 32 bits.
(hi32_mask_operand): Immediately counts the mask of 32 to 61 bits.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/imm-load.c: New test.
---
 gcc/config/loongarch/constraints.md   |  7 +-
 gcc/config/loongarch/loongarch.cc | 95 ---
 gcc/config/loongarch/loongarch.h  |  6 ++
 gcc/config/loongarch/loongarch.md | 26 +
 gcc/config/loongarch/predicates.md|  8 ++
 gcc/testsuite/gcc.target/loongarch/imm-load.c | 25 +
 6 files changed, 133 insertions(+), 34 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/imm-load.c

diff --git a/gcc/config/loongarch/constraints.md 
b/gcc/config/loongarch/constraints.md
index 43cb7b5f0f5..1dcf09ce5eb 100644
--- a/gcc/config/loongarch/constraints.md
+++ b/gcc/config/loongarch/constraints.md
@@ -46,7 +46,7 @@
 ;; "u" "A signed 52bit constant and low 32-bit is zero (for logic 
instructions)"
 ;; "v" "A signed 64-bit constant and low 44-bit is zero (for logic 
instructions)."
 ;; "w" "Matches any valid memory."
-;; "x" <-unused
+;; "x" "A signed 64-bit constant and low 32-bit is zero (for logic 
instructions)."
 ;; "y" <-unused
 ;; "z" FCC_REGS
 ;; "A" <-unused
@@ -139,6 +139,11 @@ (define_constraint "v"
   (and (match_code "const_int")
(match_test "LU52I_OPERAND (ival)")))
 
+(define_constraint "x"
+  "A signed 64-bit constant and low 32-bit is zero (for logic instructions)."
+  (and (match_code "const_int")
+   (match_test "HI32_OPERAND (ival)")))
+
 (define_register_constraint "z" "FCC_REGS"
   "A floating-point condition code register.")
 
diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index f54c233f90c..5e8cd293645 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -139,6 +139,9 @@ struct loongarch_address_info
METHOD_LU52I:
  Load 52-63 bit of the immediate number.
 
+   METHOD_LD_HI32:
+ Load 32-63 bit of the immediate number.
+
METHOD_INSV:
  immediate like 0xfff0fxxx
*/
@@ -147,13 +150,18 @@ enum loongarch_load_imm_method
   METHOD_NORMAL,
   METHOD_LU32I,
   METHOD_LU52I,
+  METHOD_LD_HI32,
   METHOD_INSV
 };
 
 struct loongarch_integer_op
 {
   enum rtx_code code;
+  /* Current Immediate Count The immediate count of the load instruction.  */
   HOST_WIDE_INT value;
+  /* Represent the result　of the immediate count of the load instruction at
+ each step.  */
+  HOST_WIDE_INT curr_value;
   enum loongarch_load_imm_method method;
 };
 
@@ -1474,24 +1482,27 @@ loongarch_build_integer (struct loongarch_integer_op 
*codes,
 {
   /* The value of the lower 32 bit be loaded with one instruction.
 lu12i.w.  */
-  codes[0].code = UNKNOWN;
-  codes[0].method = METHOD_NORMAL;
-  codes[0].value = low_part;
+  codes[cost].code = UNKNOWN;
+  codes[cost].method = METHOD_NORMAL;
+  codes[cost].value = low_part;
+  codes[cost].curr_value = low_part;
   cost++;
 }
   else
 {
   /* lu12i.w + ior.  */
-  codes[0].code = UNKNOWN;
-  codes[0].method = METHOD_NORMAL;
-  codes[0].value = low_part & ~(IMM_REACH - 1);
+  codes[cost].code = UNKNOWN;
+  codes[cost].method = METHOD_NORMAL;
+  codes[cost].value = low_part & ~(IMM_REACH - 1);
+  codes[cost].curr_value = codes[cost].value;
   cost++;
   HOST_WIDE_INT iorv = low_part & (IMM_REACH - 1);
   if (iorv != 0)
{
- codes[1].code = IOR;
- codes[1].method = METHOD_NORMAL;
- codes[1].value = iorv;
+ codes[cost].code = IOR;
+ codes[cost].method = METHOD_NORMAL;
+ codes[cost].value = iorv;
+ codes[cost].curr_value = low_part;
  cost++;
}
 }
@@ -1514,23 +1525,34 @@ loongarch_build_integer (struct loongarch_integer_op 
*codes,
{
  codes[cost].method = METHOD_LU52I;
  codes[cost].value = value & LU52I_B;
- return cost + 1;
+ codes[cost].curr_value = codes[cost].value | 
(codes[cost

Re: [PATCH v1 2/2] LoongArch: Add prefetch insns.

[Lulu Cheng]

Sorry for the problem in this patch. I will send it again after 
modification.


在 2022/10/29 下午3:05, Lulu Cheng 写道:

Co-Authored-By: xujiahao 

gcc/ChangeLog:

* config/loongarch/loongarch-def.c: Initial number of parallel prefetch.
* config/loongarch/loongarch-protos.h (loongarch_prefetch_cookie):
Function declaration.
* config/loongarch/loongarch-tune.h (struct loongarch_cache):
Define number of parallel prefetch.
* config/loongarch/loongarch.cc (loongarch_option_override_internal):
Set up parameters to be used in prefetching algorithm.
(loongarch_prefetch_cookie): Select load or store based on the value of 
write.
* config/loongarch/loongarch.md (prefetch): New template.
(*prefetch_indexed_): New template.
---
  gcc/config/loongarch/loongarch-def.c|  2 ++
  gcc/config/loongarch/loongarch-protos.h |  1 +
  gcc/config/loongarch/loongarch-tune.h   |  1 +
  gcc/config/loongarch/loongarch.cc   | 48 +
  gcc/config/loongarch/loongarch.md   | 23 
  5 files changed, 75 insertions(+)

diff --git a/gcc/config/loongarch/loongarch-def.c 
b/gcc/config/loongarch/loongarch-def.c
index cbf995d81b5..80ab10a52a8 100644
--- a/gcc/config/loongarch/loongarch-def.c
+++ b/gcc/config/loongarch/loongarch-def.c
@@ -62,11 +62,13 @@ loongarch_cpu_cache[N_TUNE_TYPES] = {
.l1d_line_size = 64,
.l1d_size = 64,
.l2d_size = 256,
+  .simultaneous_prefetches = 4,
},
[CPU_LA464] = {
.l1d_line_size = 64,
.l1d_size = 64,
.l2d_size = 256,
+  .simultaneous_prefetches = 4,
},
  };
  
diff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h

index 77b2217247d..489525b520e 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -179,5 +179,6 @@ extern tree loongarch_builtin_decl (unsigned int, bool);
  extern rtx loongarch_expand_builtin (tree, rtx, rtx subtarget 
ATTRIBUTE_UNUSED,
 machine_mode, int);
  extern tree loongarch_build_builtin_va_list (void);
+extern rtx loongarch_prefetch_cookie (rtx, rtx);
  
  #endif /* ! GCC_LOONGARCH_PROTOS_H */

diff --git a/gcc/config/loongarch/loongarch-tune.h 
b/gcc/config/loongarch/loongarch-tune.h
index 6f3530f5c02..8e3eb29472b 100644
--- a/gcc/config/loongarch/loongarch-tune.h
+++ b/gcc/config/loongarch/loongarch-tune.h
@@ -45,6 +45,7 @@ struct loongarch_cache {
  int l1d_line_size;  /* bytes */
  int l1d_size;   /* KiB */
  int l2d_size;   /* kiB */
+int simultaneous_prefetches; /* number of parallel prefetch */
  };
  
  #endif /* LOONGARCH_TUNE_H */

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 5e8cd293645..d663afe434d 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -63,6 +63,7 @@ along with GCC; see the file COPYING3.  If not see
  #include "context.h"
  #include "builtins.h"
  #include "rtl-iter.h"
+#include "params.h"
  
  /* This file should be included last.  */

  #include "target-def.h"
@@ -6126,6 +6127,33 @@ loongarch_option_override_internal (struct gcc_options 
*opts)
if (loongarch_branch_cost == 0)
  loongarch_branch_cost = loongarch_cost->branch_cost;
  
+  /* Set up parameters to be used in prefetching algorithm. */

+  maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
+
loongarch_cpu_cache[LARCH_ACTUAL_TUNE].simultaneous_prefetches,
+opts->x_param_values,
+opts_set->x_param_values);
+
+  maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
+loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l1d_line_size,
+opts->x_param_values,
+opts_set->x_param_values);
+
+  maybe_set_param_value (PARAM_L1_CACHE_SIZE,
+loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l1d_size,
+opts->x_param_values,
+opts_set->x_param_values);
+
+  maybe_set_param_value (PARAM_L2_CACHE_SIZE,
+loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l2d_size,
+opts->x_param_values,
+opts_set->x_param_values);
+
+  /* Enable sw prefetching at -O3 and higher. */
+  if (opts->x_flag_prefetch_loop_arrays < 0
+  && (opts->x_optimize >= 3 || opts->x_flag_profile_use)
+  && !opts->x_optimize_size)
+opts->x_flag_prefetch_loop_arrays = 1;
+
if (TARGET_DIRECT_EXTERN_ACCESS && flag_shlib)
  error ("%qs cannot be used for compiling a shared library",
   "-mdirect-extern-access");
@@ -6506,6 +6534,26 @@ loongarch_asan_shadow_offset (void)
return TARGET_64BIT ? (HOST_WIDE_INT_1 << 46) : 0;
  }
  
+/* LoongArch only implements preld hint=0 (prefetch for load) and hint=8

+   (prefetch for store), other hint just scale to hint = 0 and 

[committed] d: Make TARGET_D_MINFO_SECTION hooks in elfos.h the language default.

[Iain Buclaw via Gcc-patches]

Hi,

This patch makes the TARGET_D_MINFO_SECTION hooks defined in elfos.h the
langauge default, removing the last of all TARGET_D_* macro definitions
in common target headers.  Now everything is either defined in the D
language front-end, or D-specific target headers.

The target macros TARGET_D_MINFO_START_NAME and TARGET_D_MINFO_END_NAME
have also been renamed to TARGET_D_MINFO_SECTION_START and
TARGET_D_MINFO_SECTION_END respectively to reflect their relation to the
hook TARGET_D_MINFO_SECTION - the documentation of which has been
revised to clarify these changes.

Bootstrapped and regression tested on x86_64-linux-gnu, committed to
mainline.

Regards,
Iain.

---
gcc/ChangeLog:

* config/darwin-d.cc (TARGET_D_MINFO_START_NAME): Rename to ...
(TARGET_D_MINFO_SECTION_START): ...this.
(TARGET_D_MINFO_END_NAME): Rename to ...
(TARGET_D_MINFO_SECTION_END): ... this.
* config/elfos.h (TARGET_D_MINFO_SECTION): Remove.
(TARGET_D_MINFO_START_NAME): Remove.
(TARGET_D_MINFO_END_NAME): Remove.
* config/i386/cygwin-d.cc (TARGET_D_MINFO_SECTION): Remove.
(TARGET_D_MINFO_START_NAME): Remove.
(TARGET_D_MINFO_END_NAME): Remove.
* config/i386/winnt-d.cc (TARGET_D_MINFO_SECTION): Remove.
(TARGET_D_MINFO_START_NAME): Remove.
(TARGET_D_MINFO_END_NAME): Remove.
* doc/tm.texi: Regenerate.
* doc/tm.texi.in (TARGET_D_MINFO_START_NAME): Rename to ...
(TARGET_D_MINFO_SECTION_START): ...this.
(TARGET_D_MINFO_END_NAME): Rename to ...
(TARGET_D_MINFO_SECTION_END): ...this.

gcc/d/ChangeLog:

* d-target.def (d_minfo_section): Expand documentation of hook.
Default initialize to "minfo".
(d_minfo_start_name): Rename to ...
(d_minfo_section_start): ... this.  Default initialize to
"__start_minfo".
(d_minfo_end_name): Rename to ...
(d_minfo_section_end): ... this. Default initialize to "__stop_minfo".
* modules.cc (register_moduleinfo): Use new targetdm hook names.
---
 gcc/config/darwin-d.cc  |  8 
 gcc/config/elfos.h  |  6 --
 gcc/config/i386/cygwin-d.cc | 11 ---
 gcc/config/i386/winnt-d.cc  | 11 ---
 gcc/d/d-target.def  | 23 +--
 gcc/d/modules.cc|  4 ++--
 gcc/doc/tm.texi | 16 ++--
 gcc/doc/tm.texi.in  |  4 ++--
 8 files changed, 31 insertions(+), 52 deletions(-)

diff --git a/gcc/config/darwin-d.cc b/gcc/config/darwin-d.cc
index 2ceebc49851..97304947c0a 100644
--- a/gcc/config/darwin-d.cc
+++ b/gcc/config/darwin-d.cc
@@ -67,10 +67,10 @@ darwin_d_register_target_info (void)
 #undef TARGET_D_MINFO_SECTION
 #define TARGET_D_MINFO_SECTION "__DATA,__minfodata"
 
-#undef TARGET_D_MINFO_START_NAME
-#define TARGET_D_MINFO_START_NAME "*section$start$__DATA$__minfodata"
+#undef TARGET_D_MINFO_SECTION_START
+#define TARGET_D_MINFO_SECTION_START "*section$start$__DATA$__minfodata"
 
-#undef TARGET_D_MINFO_END_NAME
-#define TARGET_D_MINFO_END_NAME "*section$end$__DATA$__minfodata"
+#undef TARGET_D_MINFO_SECTION_END
+#define TARGET_D_MINFO_SECTION_END "*section$end$__DATA$__minfodata"
 
 struct gcc_targetdm targetdm = TARGETDM_INITIALIZER;
diff --git a/gcc/config/elfos.h b/gcc/config/elfos.h
index acb376283cf..f8b3be4358a 100644
--- a/gcc/config/elfos.h
+++ b/gcc/config/elfos.h
@@ -482,9 +482,3 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  
If not, see
 
 #undef TARGET_LIBC_HAS_FUNCTION
 #define TARGET_LIBC_HAS_FUNCTION no_c99_libc_has_function
-
-/* ELF support needed only by D front-end.  */
-
-#define TARGET_D_MINFO_SECTION "minfo"
-#define TARGET_D_MINFO_START_NAME "__start_minfo"
-#define TARGET_D_MINFO_END_NAME "__stop_minfo"
diff --git a/gcc/config/i386/cygwin-d.cc b/gcc/config/i386/cygwin-d.cc
index 619930b4ff4..6d70d499eef 100644
--- a/gcc/config/i386/cygwin-d.cc
+++ b/gcc/config/i386/cygwin-d.cc
@@ -64,17 +64,6 @@ cygwin_d_register_target_info (void)
 #undef TARGET_D_REGISTER_OS_TARGET_INFO
 #define TARGET_D_REGISTER_OS_TARGET_INFO cygwin_d_register_target_info
 
-/* Define TARGET_D_MINFO_SECTION for Cygwin targets.  */
-
-#undef TARGET_D_MINFO_SECTION
-#define TARGET_D_MINFO_SECTION "minfo"
-
-#undef TARGET_D_MINFO_START_NAME
-#define TARGET_D_MINFO_START_NAME "__start_minfo"
-
-#undef TARGET_D_MINFO_END_NAME
-#define TARGET_D_MINFO_END_NAME "__stop_minfo"
-
 /* Define TARGET_D_TEMPLATES_ALWAYS_COMDAT for Cygwin targets.  */
 
 #undef TARGET_D_TEMPLATES_ALWAYS_COMDAT
diff --git a/gcc/config/i386/winnt-d.cc b/gcc/config/i386/winnt-d.cc
index a1fd3fa1fbe..843c7139cb2 100644
--- a/gcc/config/i386/winnt-d.cc
+++ b/gcc/config/i386/winnt-d.cc
@@ -69,17 +69,6 @@ winnt_d_register_target_info (void)
 #undef TARGET_D_REGISTER_OS_TARGET_INFO
 #define TARGET_D_REGISTER_OS_TARGET_INFO winnt_d_register_target_info
 
-/* Define TARGET_D_MINFO_SECTION for Windows targets.  */
-
-#undef TARGET_D_MINFO_SECTION
-#define TARGET

Re: [PATCH] Restore RTL alias analysis for hard frame pointer

[Eric Botcazou via Gcc-patches]

> OK for trunk and 12 after a while of burn-in.

Thanks!

> Oh, do you have a testcase suitable for the testsuite?

I only have an Ada testcase for GDB, let me try to find something more usable.

-- 
Eric Botcazou

[committed] wwwdocs: contribute: Remove

[Gerald Pfeifer]

Google has not been using that forever and there are indications
search engines even use it as one indication for spam sites.

Pushed.
Gerald
---
 htdocs/contribute.html | 2 --
 1 file changed, 2 deletions(-)

diff --git a/htdocs/contribute.html b/htdocs/contribute.html
index 02843580..7c1ae323 100644
--- a/htdocs/contribute.html
+++ b/htdocs/contribute.html
@@ -3,8 +3,6 @@
 
 
 
-
 Contributing to GCC
 https://gcc.gnu.org/gcc.css";>
 
-- 
2.38.0

[PATCH v5] RISC-V: Libitm add RISC-V support.

[Xiongchuan Tan via Gcc-patches]

Reviewed-by: Palmer Dabbelt 
Acked-by: Palmer Dabbelt 

libitm/ChangeLog:

* configure.tgt: Add riscv support.
* config/riscv/asm.h: New file.
* config/riscv/sjlj.S: New file.
* config/riscv/target.h: New file.
---
v2: Change HW_CACHELINE_SIZE to 64 (in accordance with the RVA profiles, see
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc)

v3: Ensure the stack is aligned to 16 bytes; make use of Zihintpause in
cpu_relax()

v4: Add a guard for unsupported RV32E

v5: Fix error message for rv32e and rv64e; add guards for the Q-extension; 
define a macro ADJ_STACK_SIZE to hold the size of the struct gtm_jmpbuf

 libitm/config/riscv/asm.h|  63 +++
 libitm/config/riscv/sjlj.S   | 144 +++
 libitm/config/riscv/target.h |  64 
 libitm/configure.tgt |   2 +
 4 files changed, 273 insertions(+)
 create mode 100644 libitm/config/riscv/asm.h
 create mode 100644 libitm/config/riscv/sjlj.S
 create mode 100644 libitm/config/riscv/target.h

diff --git a/libitm/config/riscv/asm.h b/libitm/config/riscv/asm.h
new file mode 100644
index 000..f0e3bd0
--- /dev/null
+++ b/libitm/config/riscv/asm.h
@@ -0,0 +1,63 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+   Contributed by Xiongchuan Tan .
+
+   This file is part of the GNU Transactional Memory Library (libitm).
+
+   Libitm is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
+   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+   FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+   more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   .  */
+
+#ifndef _RV_ASM_H
+#define _RV_ASM_H
+
+#ifdef __riscv_e
+#  error "rv32e and rv64e unsupported"
+#endif
+
+#if __riscv_xlen == 64
+#  define GPR_L ld
+#  define GPR_S sd
+#  define SZ_GPR 8
+#  define LEN_GPR 14
+#elif __riscv_xlen == 32
+#  define GPR_L lw
+#  define GPR_S sw
+#  define SZ_GPR 4
+#  define LEN_GPR 16 /* Extra padding to align the stack to 16 bytes */
+#else
+#  error Unsupported XLEN (must be 64-bit or 32-bit).
+#endif
+
+#if defined(__riscv_flen) && __riscv_flen == 64
+#  define FPR_L fld
+#  define FPR_S fsd
+#  define SZ_FPR 8
+#elif defined(__riscv_flen) && __riscv_flen == 32
+#  define FPR_L flw
+#  define FPR_S fsw
+#  define SZ_FPR 4
+#elif defined(__riscv_flen)
+#  error Q-extension unsupported
+#else
+#  define SZ_FPR 0
+#endif
+
+/* The size of gtm_jmpbuf */
+#define ADJ_STACK_SIZE (LEN_GPR*SZ_GPR+12*SZ_FPR)
+
+#endif  /* _RV_ASM_H */
diff --git a/libitm/config/riscv/sjlj.S b/libitm/config/riscv/sjlj.S
new file mode 100644
index 000..18521ae
--- /dev/null
+++ b/libitm/config/riscv/sjlj.S
@@ -0,0 +1,144 @@
+/* Copyright (C) 2022 Free Software Foundation, Inc.
+   Contributed by Xiongchuan Tan .
+
+   This file is part of the GNU Transactional Memory Library (libitm).
+
+   Libitm is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
+   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+   FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+   more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   .  */
+
+#include "asmcfi.h"
+#include "asm.h"
+
+   .text
+   .align  2
+   .global _ITM_beginTransaction
+   .type   _ITM_beginTransaction, @function
+
+_ITM_beginTransaction:
+   cfi_startproc
+   mv a1, sp
+   addi sp, sp, -ADJ_STACK_SIZE
+   cfi_adjust_cfa_offset(ADJ_STACK_SIZE)
+
+   /* Return Address */
+   GPR_S ra, 0*SZ_GPR(sp)
+   cfi_rel_offset(ra, 0*SZ_GPR)
+
+   /* Caller's sp */
+   GPR_S a1, 1*SZ_GPR(sp)
+
+ 

Re: [PATCH v4] RISC-V: Libitm add RISC-V support.

[Xiongchuan Tan via Gcc-patches]

On Saturday, 29 October 2022 12:33:50 CST Jeff Law wrote:
> > +#ifdef __riscv_e
> > +#  error "rv32e unsupported"
> > +#endif
> 
> error "rv32e and rv64e unsupported" would probably be a better error 
> here.  But it's probably not a big deal.

Fixed in v5.

> Do you have commit access?  If so, go ahead and commit the change.  Else 
> let me know and I can do it for you.

I don't have commit access, so thank you for doing it for me!

Re: [PATCH] Restore RTL alias analysis for hard frame pointer

[Richard Biener via Gcc-patches]

> Am 29.10.2022 um 10:19 schrieb Eric Botcazou :
> 
> 
>> 
>> OK for trunk and 12 after a while of burn-in.
> 
> Thanks!
> 
>> Oh, do you have a testcase suitable for the testsuite?
> 
> I only have an Ada testcase for GDB, let me try to find something more usable.

Not too bad if it works to scan-assembler for the DWARF?

> -- 
> Eric Botcazou
> 
> 

Repair --disable-sjlj-exceptions

[Eric Botcazou via Gcc-patches]

It was broken by:

2022-08-31  Martin Liska  

* config.build: Remove deprecated ports.
* config.gcc: Likewise.
* config.host: Likewise.
* configure.ac: Likewise.
* configure: Regenerate.
* config/pa/pa-hpux10.h: Removed.
* config/pa/pa-hpux10.opt: Removed.
* config/pa/t-dce-thr: Removed.

Tested by building i686-w64-mingw32 with --disable-sjlj-exceptions, applied on 
the mainline as obvious.


2022-10-29  Eric Botcazou  

* configure.ac (sjlj-exceptions): Restore dropped line.
* configure: Regenerate.

-- 
Eric Botcazoudiff --git a/gcc/configure.ac b/gcc/configure.ac
index eb92a37cd46..4ecccffc324 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -1805,6 +1805,7 @@ AC_SUBST(objext)
 AC_ARG_ENABLE(sjlj-exceptions,
 [AS_HELP_STRING([--enable-sjlj-exceptions],
 [arrange to use setjmp/longjmp exception handling])],
+[force_sjlj_exceptions=yes],
 [case $target in
   lm32*-*-*)
  force_sjlj_exceptions=yes

[committed] wwwdocs: bugs: Switch www.open-std.org to https

[Gerald Pfeifer]

Pushed.

Gerald
---
 htdocs/bugs/index.html | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/htdocs/bugs/index.html b/htdocs/bugs/index.html
index d3a50f2a..aaef8915 100644
--- a/htdocs/bugs/index.html
+++ b/htdocs/bugs/index.html
@@ -650,8 +650,8 @@ the C++ standard: [dcl.init.ref] wwwdocs:/5, bullet 2, 
sub-bullet 1, and
 [class.temporary] wwwdocs:/2.
 
 Starting with GCC 4.3.0, GCC no longer gives an error for this
-case.  This change is based on
-the http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_defects.html#391";>intent
+case.  This change is based on the
+https://www.open-std.org/jtc1/sc22/wg21/docs/cwg_defects.html#391";>intent
 of the C++ language committee.  As of 2010-05-28, the final
 proposed draft of the C++0x standard permits this code without error.
 
-- 
2.38.0

[committed] wwwdocs: readings: Update Go-related links to new site

[Gerald Pfeifer]

Pushed.

Gerald

---
 htdocs/readings.html | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/htdocs/readings.html b/htdocs/readings.html
index f0327e39..01ccd55d 100644
--- a/htdocs/readings.html
+++ b/htdocs/readings.html
@@ -553,9 +553,8 @@ names.
 Go information
 
 
-https://golang.org/";>General Go information
-https://golang.org/ref/spec";>Go language
-specification
+https://go.dev/";>General Go information
+https://go.dev/ref/spec";>Go language specification
 
 
 
-- 
2.38.0

[committed] wwwdocs: frontends: Adjust Sourceforge links to https

[Gerald Pfeifer]

Pushed.

Gerald
---
 htdocs/frontends.html | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/htdocs/frontends.html b/htdocs/frontends.html
index 8f156e96..8e38838a 100644
--- a/htdocs/frontends.html
+++ b/htdocs/frontends.html
@@ -37,7 +37,7 @@ a declarative logic/functional language. The University of 
Melbourne Mercury
 compiler is written in Mercury; originally it compiled via C but now it also
 has a back end that generates assembler directly, using the GCC back end.
 
-http://CobolForGCC.sourceforge.net/";>Cobol For GCC
+https://CobolForGCC.sourceforge.net/";>Cobol For GCC
 (at an early stage of development).
 
 http://www.nongnu.org/gm2/";>GNU Modula-2 implements
@@ -61,7 +61,7 @@ VHDL (IEEE 1076) hardware design language.  GHDL and its 
runtime library
 are written in Ada95 using GNAT and are distributed under the GPL.
 Currently they only support GNU/Linux x86 systems.
 
-http://pl1gcc.sourceforge.net/";>PL/1 for GCC is a
+https://pl1gcc.sourceforge.net/";>PL/1 for GCC is a
 GCC front end for the PL/I language.
 
 https://github.com/Intrepid/GUPC";>GCC Unified Parallel C
-- 
2.38.0

[committed] wwwdocs: gcc-10: Update two developer.arm.com links

[Gerald Pfeifer]

Pushed.

---
 htdocs/gcc-10/changes.html | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html
index 79de28f7..2bad8ea3 100644
--- a/htdocs/gcc-10/changes.html
+++ b/htdocs/gcc-10/changes.html
@@ -850,14 +850,14 @@ typedef svbool_t pred512 
__attribute__((arm_sve_vector_bits(512)));
   with MOVT. For example, -mcpu=cortex-m0
   now supports this option.
   Support for the
-  https://developer.arm.com/architectures/cpu-architecture/m-profile";>
+  https://developer.arm.com/Architectures/M-Profile%20Architecture";>
   Armv8.1-M Mainline Architecture has been added.
   
 Armv8.1-M Mainline can be enabled by using the
   -march=armv8.1-m.main command-line option.
   
   Support for the
-  https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/helium-intrinsics";>
+  https://developer.arm.com/architectures/instruction-sets/intrinsics/";>
   MVE beta ACLE intrinsics has been added. These intrinsics can be
   enabled by including the arm_mve.h header file and passing the
   +mve or +mve.fp option extensions (for
-- 
2.38.0

[committed] wwwdocs: testing: Switch www.netlib.org to https

[Gerald Pfeifer]

Not sure anyone is (still) using these instructions?

Still, as long as we have them, adjust the links.

Pushed.
Gerald

---
 htdocs/testing/testing-lapack.html | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/htdocs/testing/testing-lapack.html 
b/htdocs/testing/testing-lapack.html
index a819b7d5..6416ac3e 100644
--- a/htdocs/testing/testing-lapack.html
+++ b/htdocs/testing/testing-lapack.html
@@ -11,14 +11,14 @@
 LAPACK build and test guide
 
 This page is a guide to building the
-http://www.netlib.org/lapack/index.html";>LAPACK linear
+https://www.netlib.org/lapack/index.html";>LAPACK linear
 algebra package and running its testing and timing programs as part of
 GCC integration testing.
 
 Resource usage
 
 The LAPACK distribution, available from the netlib repository at
-http://www.netlib.org/lapack/lapack.tgz";>lapack.tgz,
+https://www.netlib.org/lapack/lapack.tgz";>lapack.tgz,
 is a 5 MB file.  The uncompressed LAPACK distribution comprises some 35 MB
 of source files.  Building the libraries, test and timing programs adds
 between 80 and 100 MB of objects, libraries and executables to this.
-- 
2.38.0

[committed] wwwdocs: gcc-4.3: Switch www.open-std.org to https

[Gerald Pfeifer]

Pushed.

Gerald
---
 htdocs/gcc-4.3/cxx0x_status.html | 102 +++
 htdocs/gcc-4.3/porting_to.html   |   2 +-
 2 files changed, 52 insertions(+), 52 deletions(-)

diff --git a/htdocs/gcc-4.3/cxx0x_status.html b/htdocs/gcc-4.3/cxx0x_status.html
index d4680370..de1de274 100644
--- a/htdocs/gcc-4.3/cxx0x_status.html
+++ b/htdocs/gcc-4.3/cxx0x_status.html
@@ -18,7 +18,7 @@
 GCC's C++0x mode tracks the C++0x working paper drafts produced by
 the ISO C++ committee, available on the ISO C++ committee's web site
 at http://www.open-std.org/jtc1/sc22/wg21/";>http://www.open-std.org/jtc1/sc22/wg21/.
 Since
+href="https://www.open-std.org/jtc1/sc22/wg21/";>https://www.open-std.org/jtc1/sc22/wg21/.
 Since
 this standard is still being extended and modified, the feature set
 provided by the experimental C++0x mode may vary greatly from one GCC
 version to another. No attempts will be made to preserve backward
@@ -38,189 +38,189 @@ page.
 
 
   Rvalue references
-  http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2006/n2118.html";>N2118
+  https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2006/n2118.html";>N2118
   Yes
 
 
   Rvalue references for *this
-  http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2007/n2439.htm";>N2439
+  https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2007/n2439.htm";>N2439
   No
 
 
   Variadic templates
-  http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2007/n2242.pdf";>N2242
+  https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2007/n2242.pdf";>N2242
   Yes
 
 
   Extending variadic template template 
parameters
-  http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2008/n2555.pdf";>N2555
+  https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2008/n2555.pdf";>N2555
   No
 
 
   Initializer lists
-  http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2008/n2672.htm";>N2672
+  https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2008/n2672.htm";>N2672
   No
 
 
   Static assertions
-  http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2004/n1720.html";>N1720
+  https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2004/n1720.html";>N1720
   Yes
 
 
   auto-typed variables
-  http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2006/n1984.pdf";>N1984
+  https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2006/n1984.pdf";>N1984
   No
 
 
   Multi-declarator auto
-  http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2004/n1737.pdf";>N1737
+  https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2004/n1737.pdf";>N1737
   No
 
 
   Removal of auto as a storage-class 
specifier
-  http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2008/n2546.htm";>N2546
+  https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2008/n2546.htm";>N2546
   No
 
 
   New function declarator syntax
-  http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2008/n2541.htm";>N2541
+  https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2008/n2541.htm";>N2541
   No
 
 
   Lambda expressions and closures
-  http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2008/n2550.pdf";>N2550
+  https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2008/n2550.pdf";>N2550
   No
 
 
   Constness of lambda functions
-  http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2008/n2658.pdf";>N2658
+  https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2008/n2658.pdf";>N2658
   No
 
 
   Declared type of an expression
-  http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2007/n2343.pdf";>N2343
+  https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2007/n2343.pdf";>N2343
   Yes
 
 
   Right angle brackets
-  http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2005/n1757.html";>N1757
+  https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2005/n1757.html";>N1757
   Yes
 
 
   Default template arguments for function templates
-  http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_defects.html#226";>DR226
+  https://www.open-std.org/jtc1/sc22/wg21/docs/cwg_defects.html#226";>DR226
   Yes
 
 
   Solving the SFINAE problem for expressions
-  http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2008/n2634.html";>DR339
+  https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2008/n2634.html";>DR339
   No
 
 
   Template aliases
-  http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2007/n2258.pdf";>N2258
+  https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2007/n2258.pdf";>N2258
   No
 
 
   Extern templates
-  http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2006/n1987.htm";>N1987
+  https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2006/n1987.htm";>N1987
   Yes
 
 
   Null pointer 

[committed] wwwdocs: projects: Remove extra slash at end of

[Gerald Pfeifer]

Pushed.

Gerald

---
 htdocs/projects/cxx0x.html | 2 +-
 htdocs/projects/cxx1y.html | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/htdocs/projects/cxx0x.html b/htdocs/projects/cxx0x.html
index 89112d01..49cfcc98 100644
--- a/htdocs/projects/cxx0x.html
+++ b/htdocs/projects/cxx0x.html
@@ -3,7 +3,7 @@
 
 
 
-
+