[PATCH] [PATCH, v5, 1/1, AARCH64][PR102768] aarch64: Add compiler support for Shadow Call Stack
Shadow Call Stack can be used to protect the return address of a function at runtime, and clang already supports this feature[1]. To enable SCS in user mode, in addition to compiler, other support is also required (as discussed in [2]). This patch only adds basic support for SCS from the compiler side, and provides convenience for users to enable SCS. For linux kernel, only the support of the compiler is required. [1] https://clang.llvm.org/docs/ShadowCallStack.html [2] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102768 Signed-off-by: Dan Li gcc/ChangeLog: * config/aarch64/aarch64.cc (SLOT_REQUIRED): Change wb_candidate[12] to wb_push_candidate[12]. (aarch64_layout_frame): Likewise, and change callee_adjust when scs is enabled. (aarch64_save_callee_saves): Change wb_candidate[12] to wb_push_candidate[12]. (aarch64_restore_callee_saves): Change wb_candidate[12] to wb_pop_candidate[12]. (aarch64_get_separate_components): Change wb_candidate[12] to wb_push_candidate[12]. (aarch64_expand_prologue): Push x30 onto SCS before it's pushed onto stack. (aarch64_expand_epilogue): Pop x30 frome SCS, while preventing it from being popped from the regular stack again. (aarch64_override_options_internal): Add SCS compile option check. (TARGET_HAVE_SHADOW_CALL_STACK): New hook. * config/aarch64/aarch64.h (struct GTY): Add is_scs_enabled, wb_pop_candidate[12], and rename wb_candidate[12] to wb_push_candidate[12]. * config/aarch64/aarch64.md (scs_push): New template. (scs_pop): Likewise. * doc/invoke.texi: Document -fsanitize=shadow-call-stack. * doc/tm.texi: Regenerate. * doc/tm.texi.in: Add hook have_shadow_call_stack. * flag-types.h (enum sanitize_code): Add SANITIZE_SHADOW_CALL_STACK. * opts.cc: Add shadow-call-stack. * target.def: New hook. * toplev.cc (process_options): Add SCS compile option check. gcc/testsuite/ChangeLog: * gcc.target/aarch64/shadow_call_stack_1.c: New test. * gcc.target/aarch64/shadow_call_stack_2.c: New test. * gcc.target/aarch64/shadow_call_stack_3.c: New test. * gcc.target/aarch64/shadow_call_stack_4.c: New test. * gcc.target/aarch64/shadow_call_stack_5.c: New test. * gcc.target/aarch64/shadow_call_stack_6.c: New test. * gcc.target/aarch64/shadow_call_stack_7.c: New test. * gcc.target/aarch64/shadow_call_stack_8.c: New test. --- V5: - Modify part of wb_push_candidates to wb_pop_candidates. - Rebase to the mainline (20220210). V4: - Added wb_[push|pop]_candidates[12] to ensure push/pop can emit different registers. V3: - Change scs_push/pop to standard move patterns. - Optimize scs_pop to avoid pop x30 twice when shadow stack is enabled. gcc/config/aarch64/aarch64.cc | 113 +- gcc/config/aarch64/aarch64.h | 21 +++- gcc/config/aarch64/aarch64.md | 10 ++ gcc/doc/invoke.texi | 30 + gcc/doc/tm.texi | 5 + gcc/doc/tm.texi.in| 2 + gcc/flag-types.h | 2 + gcc/opts.cc | 1 + gcc/target.def| 8 ++ .../gcc.target/aarch64/shadow_call_stack_1.c | 6 + .../gcc.target/aarch64/shadow_call_stack_2.c | 6 + .../gcc.target/aarch64/shadow_call_stack_3.c | 45 +++ .../gcc.target/aarch64/shadow_call_stack_4.c | 20 .../gcc.target/aarch64/shadow_call_stack_5.c | 18 +++ .../gcc.target/aarch64/shadow_call_stack_6.c | 18 +++ .../gcc.target/aarch64/shadow_call_stack_7.c | 18 +++ .../gcc.target/aarch64/shadow_call_stack_8.c | 24 gcc/toplev.cc | 10 ++ 18 files changed, 326 insertions(+), 31 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/shadow_call_stack_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/shadow_call_stack_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/shadow_call_stack_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/shadow_call_stack_4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/shadow_call_stack_5.c create mode 100644 gcc/testsuite/gcc.target/aarch64/shadow_call_stack_6.c create mode 100644 gcc/testsuite/gcc.target/aarch64/shadow_call_stack_7.c create mode 100644 gcc/testsuite/gcc.target/aarch64/shadow_call_stack_8.c diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index e3f18fbe7da..35f6f64f5b2 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -80,6 +80,7 @@ #include "fractional-cost.h" #include "rtlanal.h" #include "tree-dfa.h" +#include "asan.h" /* This file should be included last. */ #include "target-def.h" @@ -7443,8 +7444,8 @@ aarch64_layout_fra
Re: [PATCH] [PATCH,v4,1/1,AARCH64][PR102768] aarch64: Add compiler support for Shadow Call Stack
On 2/11/22 07:35, Richard Sandiford wrote: Dan Li writes: On 2/11/22 01:53, Richard Sandiford wrote: Dan Li writes: On 2/10/22 01:55, Richard Sandiford wrote: And I think maybe we could handle this through three patches: 1.Keep current patch (a V5) unchanged for scs. 2.Add shrink-warpping for X30: logically this might be a separate topic, and I think more testing might be needed here (Well, I'm a little worried about if there might be other effects, since I just read this part of the code roughly yesterday). 3.Add scs push/pop to shrink-wrapping (and maybe we can do the same for the PAC code in pro/epilogue, since it's also the operation of the X30). Yeah, that's fair. (Like I said earlier, I wasn't asking for the shrink-wrapping change. It was just a note in passing. But as you point out, the individual shrink-wrapping support would be even more work than I'd imagined.) Hi, Richard, I have sent out the v5[1] and rebased it to mainline at the same time, please let me know if there is anything else I need to do :) [1].https://gcc.gnu.org/pipermail/gcc-patches/2022-February/590311.html Thanks, Dan
Re: [PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU
On Fri, 11 Feb 2022, Jeff Law wrote: > > If MIPS MCU extension is enable, the IPL section in Cause register > > has been expand to 8bit instead of 6bit. > > > > gcc/ChangeLog: > > > > * config/mips/mips.cc (mips_expand_prologue): > > IPL is 8bit for MCU ASE. > OK But this is still wrong AFAICT. The mask is applied to the CP0 Status register according to the comment, but the layout of the interrupt bit-field is different between the CP0 Status and the CP0 Cause registers, so you can't just extract it from one of the two registers and directly apply to the other. I would like to know how this code has been verified. Maciej
[PATCH] i386: Fix up cvtsd2ss splitter [PR104502]
Hi!
The following testcase ICEs, because AVX512F is enabled, AVX512VL is not,
and the cvtsd2ss insn has %xmm0-15 as output operand and %xmm16-31 as
input operand. For output operand %xmm16+ the splitter just gives up
in such case, but for such input it just emits vmovddup which requires
AVX512VL if either operand is EXT_REX_SSE_REG_P (when it is 128-bit).
The following patch fixes it by treating that case like the pre-SSE3
output != input case - move the input to output and do everything on
the output reg which is known to be < %xmm16.
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2022-02-12 Jakub Jelinek
PR target/104502
* config/i386/i386.md (cvtsd2ss splitter): If operands[1] is xmm16+
and AVX512VL isn't available, move operands[1] to operands[0] first.
* gcc.target/i386/pr104502.c: New test.
--- gcc/config/i386/i386.md.jj 2022-01-18 11:58:59.142988343 +0100
+++ gcc/config/i386/i386.md 2022-02-11 16:19:48.399518508 +0100
@@ -4838,8 +4838,8 @@ (define_split
movddup is available. */
if (REG_P (operands[1]))
{
- if (!TARGET_SSE3
- && REGNO (operands[0]) != REGNO (operands[1]))
+ if ((!TARGET_SSE3 && REGNO (operands[0]) != REGNO (operands[1]))
+ || (EXT_REX_SSE_REG_P (operands[1]) && !TARGET_AVX512VL))
{
rtx tmp = lowpart_subreg (DFmode, operands[0], SFmode);
emit_move_insn (tmp, operands[1]);
--- gcc/testsuite/gcc.target/i386/pr104502.c.jj 2022-02-11 16:28:12.880556460
+0100
+++ gcc/testsuite/gcc.target/i386/pr104502.c2022-02-11 16:29:42.358321630
+0100
@@ -0,0 +1,31 @@
+/* PR target/104502 */
+/* { dg-do compile { target fstack_protector } } */
+/* { dg-options "-O -flive-range-shrinkage -march=barcelona
-fstack-protector-all -mavx512f" } */
+
+typedef char __attribute__((__vector_size__ (8))) U;
+typedef int __attribute__((__vector_size__ (8))) A;
+typedef int __attribute__((__vector_size__ (16))) B;
+typedef int __attribute__((__vector_size__ (32))) C;
+typedef int __attribute__((__vector_size__ (64))) D;
+typedef __float128 __attribute__((__vector_size__ (32))) F;
+
+char s;
+U u;
+A a;
+int i;
+C c;
+double d;
+
+U
+foo (U u0, A a0, B b0, B b1, C c0, C c1, C c2, C c3, A a1, A a2, F f0)
+{
+ C ca = c |= (short) (float) d;
+ C cb = c0 + c1 + c2 + c3 + ca + (C) f0;
+ U ua = s << (u & 4);
+ B ba = ((union {C a; B b;}) cb).b + b0 + b1;
+ U ub = ((union {B a; U b;}) ba).b +
+u0 + u + ua + (U) a + (U) a + (U) a0 + (U) a1 + (U) a2;
+ long long u64_r = i + d;
+ char u8_r = u64_r;
+ return ub + u8_r;
+}
Jakub
[PATCH] asan: Fix up address sanitizer instrumentation of __builtin_alloca* if it can throw [PR104449]
Hi!
With -fstack-check=generic __builtin_alloca* can throw and the asan
instrumentation of this builtin wasn't prepared for that case.
The following patch fixes that by replacing the builtin with the
replacement builtin and emitting any further insns on the fallthru
edge.
I haven't touched the hwasan code which most likely suffers from the
same problem.
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2022-02-12 Jakub Jelinek
PR sanitizer/104449
* asan.cc: Include tree-eh.h.
(handle_builtin_alloca): Handle the case when __builtin_alloca or
__builtin_alloca_with_align can throw.
* gcc.dg/asan/pr104449.c: New test.
* g++.dg/asan/pr104449.C: New test.
--- gcc/asan.cc.jj 2022-01-18 11:58:58.876992143 +0100
+++ gcc/asan.cc 2022-02-11 19:09:39.752065877 +0100
@@ -63,6 +63,7 @@ along with GCC; see the file COPYING3.
#include "fnmatch.h"
#include "tree-inline.h"
#include "tree-ssa.h"
+#include "tree-eh.h"
/* AddressSanitizer finds out-of-bounds and use-after-free bugs
with <2x slowdown on average.
@@ -726,14 +727,24 @@ handle_builtin_alloca (gcall *call, gimp
gassign *g;
gcall *gg;
tree callee = gimple_call_fndecl (call);
+ tree lhs = gimple_call_lhs (call);
tree old_size = gimple_call_arg (call, 0);
- tree ptr_type = gimple_call_lhs (call) ? TREE_TYPE (gimple_call_lhs (call))
-: ptr_type_node;
+ tree ptr_type = lhs ? TREE_TYPE (lhs) : ptr_type_node;
tree partial_size = NULL_TREE;
unsigned int align
= DECL_FUNCTION_CODE (callee) == BUILT_IN_ALLOCA
? 0 : tree_to_uhwi (gimple_call_arg (call, 1));
+ bool throws = false;
+ edge e = NULL;
+ if (stmt_can_throw_internal (cfun, call))
+{
+ if (!lhs)
+ return;
+ throws = true;
+ e = find_fallthru_edge (gsi_bb (*iter)->succs);
+}
+
if (hwasan_sanitize_allocas_p ())
{
gimple_seq stmts = NULL;
@@ -852,29 +863,54 @@ handle_builtin_alloca (gcall *call, gimp
build_int_cst (size_type_node, align));
tree new_alloca_with_rz = make_ssa_name (ptr_type, gg);
gimple_call_set_lhs (gg, new_alloca_with_rz);
- gsi_insert_before (iter, gg, GSI_SAME_STMT);
+ if (throws)
+{
+ gimple_call_set_lhs (call, NULL);
+ gsi_replace (iter, gg, true);
+}
+ else
+gsi_insert_before (iter, gg, GSI_SAME_STMT);
/* new_alloca = new_alloca_with_rz + align. */
g = gimple_build_assign (make_ssa_name (ptr_type), POINTER_PLUS_EXPR,
new_alloca_with_rz,
build_int_cst (size_type_node,
align / BITS_PER_UNIT));
- gsi_insert_before (iter, g, GSI_SAME_STMT);
+ gimple_stmt_iterator gsi = gsi_none ();
+ if (throws)
+{
+ gsi_insert_on_edge_immediate (e, g);
+ gsi = gsi_for_stmt (g);
+}
+ else
+gsi_insert_before (iter, g, GSI_SAME_STMT);
tree new_alloca = gimple_assign_lhs (g);
/* Poison newly created alloca redzones:
__asan_alloca_poison (new_alloca, old_size). */
fn = builtin_decl_implicit (BUILT_IN_ASAN_ALLOCA_POISON);
gg = gimple_build_call (fn, 2, new_alloca, old_size);
- gsi_insert_before (iter, gg, GSI_SAME_STMT);
+ if (throws)
+gsi_insert_after (&gsi, gg, GSI_NEW_STMT);
+ else
+gsi_insert_before (iter, gg, GSI_SAME_STMT);
/* Save new_alloca_with_rz value into last_alloca to use it during
allocas unpoisoning. */
g = gimple_build_assign (last_alloca, new_alloca_with_rz);
- gsi_insert_before (iter, g, GSI_SAME_STMT);
+ if (throws)
+gsi_insert_after (&gsi, g, GSI_NEW_STMT);
+ else
+gsi_insert_before (iter, g, GSI_SAME_STMT);
/* Finally, replace old alloca ptr with NEW_ALLOCA. */
- replace_call_with_value (iter, new_alloca);
+ if (throws)
+{
+ g = gimple_build_assign (lhs, new_alloca);
+ gsi_insert_after (&gsi, g, GSI_NEW_STMT);
+}
+ else
+replace_call_with_value (iter, new_alloca);
}
/* Return the memory references contained in a gimple statement
--- gcc/testsuite/gcc.dg/asan/pr104449.c.jj 2022-02-11 19:23:05.085974426
+0100
+++ gcc/testsuite/gcc.dg/asan/pr104449.c2022-02-11 19:26:20.537282682
+0100
@@ -0,0 +1,12 @@
+/* PR sanitizer/104449 */
+/* { dg-do compile } */
+/* { dg-options "-fexceptions -fsanitize=address -fstack-check=generic" } */
+
+void bar (int *);
+
+void
+foo (void)
+{
+ int a[16];
+ bar (a);
+}
--- gcc/testsuite/g++.dg/asan/pr104449.C.jj 2022-02-11 19:25:22.035088372
+0100
+++ gcc/testsuite/g++.dg/asan/pr104449.C2022-02-11 19:26:08.605447008
+0100
@@ -0,0 +1,16 @@
+// PR sanitizer/104449
+// { dg-do compile }
+// { dg-options "-fexceptions -fsanitize=address -fstack-check=generic" }
+
+void bar (int *);
+struct A { A (); ~A (); };
+
+void
+foo (int n)
+{
+ A b;
+ {
+int a[n];
+bar (a);
+ }
+}
Jakub
Re: [PATCH] i386: Fix up cvtsd2ss splitter [PR104502]
On Sat, Feb 12, 2022 at 10:02 AM Jakub Jelinek wrote:
>
> Hi!
>
> The following testcase ICEs, because AVX512F is enabled, AVX512VL is not,
> and the cvtsd2ss insn has %xmm0-15 as output operand and %xmm16-31 as
> input operand. For output operand %xmm16+ the splitter just gives up
> in such case, but for such input it just emits vmovddup which requires
> AVX512VL if either operand is EXT_REX_SSE_REG_P (when it is 128-bit).
>
> The following patch fixes it by treating that case like the pre-SSE3
> output != input case - move the input to output and do everything on
> the output reg which is known to be < %xmm16.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
>
> 2022-02-12 Jakub Jelinek
>
> PR target/104502
> * config/i386/i386.md (cvtsd2ss splitter): If operands[1] is xmm16+
> and AVX512VL isn't available, move operands[1] to operands[0] first.
>
> * gcc.target/i386/pr104502.c: New test.
OK.
Thanks,
Uros.
>
> --- gcc/config/i386/i386.md.jj 2022-01-18 11:58:59.142988343 +0100
> +++ gcc/config/i386/i386.md 2022-02-11 16:19:48.399518508 +0100
> @@ -4838,8 +4838,8 @@ (define_split
> movddup is available. */
>if (REG_P (operands[1]))
> {
> - if (!TARGET_SSE3
> - && REGNO (operands[0]) != REGNO (operands[1]))
> + if ((!TARGET_SSE3 && REGNO (operands[0]) != REGNO (operands[1]))
> + || (EXT_REX_SSE_REG_P (operands[1]) && !TARGET_AVX512VL))
> {
> rtx tmp = lowpart_subreg (DFmode, operands[0], SFmode);
> emit_move_insn (tmp, operands[1]);
> --- gcc/testsuite/gcc.target/i386/pr104502.c.jj 2022-02-11 16:28:12.880556460
> +0100
> +++ gcc/testsuite/gcc.target/i386/pr104502.c2022-02-11 16:29:42.358321630
> +0100
> @@ -0,0 +1,31 @@
> +/* PR target/104502 */
> +/* { dg-do compile { target fstack_protector } } */
> +/* { dg-options "-O -flive-range-shrinkage -march=barcelona
> -fstack-protector-all -mavx512f" } */
> +
> +typedef char __attribute__((__vector_size__ (8))) U;
> +typedef int __attribute__((__vector_size__ (8))) A;
> +typedef int __attribute__((__vector_size__ (16))) B;
> +typedef int __attribute__((__vector_size__ (32))) C;
> +typedef int __attribute__((__vector_size__ (64))) D;
> +typedef __float128 __attribute__((__vector_size__ (32))) F;
> +
> +char s;
> +U u;
> +A a;
> +int i;
> +C c;
> +double d;
> +
> +U
> +foo (U u0, A a0, B b0, B b1, C c0, C c1, C c2, C c3, A a1, A a2, F f0)
> +{
> + C ca = c |= (short) (float) d;
> + C cb = c0 + c1 + c2 + c3 + ca + (C) f0;
> + U ua = s << (u & 4);
> + B ba = ((union {C a; B b;}) cb).b + b0 + b1;
> + U ub = ((union {B a; U b;}) ba).b +
> +u0 + u + ua + (U) a + (U) a + (U) a0 + (U) a1 + (U) a2;
> + long long u64_r = i + d;
> + char u8_r = u64_r;
> + return ub + u8_r;
> +}
>
> Jakub
>
[PATCH] i386: Skip decimal float vector modes in type_natural_mode [PR79754]
2022-02-12 Uroš Bizjak
gcc/ChangeLog:
PR target/79754
* config/i386/i386.cc (type_natural_mode):
Skip decimal float vector modes.
gcc/testsuite/ChangeLog:
PR target/79754
* gcc.target/i386/pr79754.c: New test.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Pushed to master.
Uros.
diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index 6b97a2b0e50..cf246e74e57 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -1876,10 +1876,14 @@ type_natural_mode (const_tree type, const
CUMULATIVE_ARGS *cum,
{
machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
- /* There are no XFmode vector modes. */
+ /* There are no XFmode vector modes ... */
if (innermode == XFmode)
return mode;
+ /* ... and no decimal float vector modes. */
+ if (DECIMAL_FLOAT_MODE_P (innermode))
+ return mode;
+
if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
mode = MIN_MODE_VECTOR_FLOAT;
else
diff --git a/gcc/testsuite/gcc.target/i386/pr79754.c
b/gcc/testsuite/gcc.target/i386/pr79754.c
new file mode 100644
index 000..27845c9d5b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr79754.c
@@ -0,0 +1,7 @@
+/* PR target/79754 */
+/* { dg-do compile } */
+/* { dg-options "-Wno-psabi" } */
+
+typedef _Decimal32 V __attribute__ ((vector_size(16)));
+
+V fn1 (V a) { return a; }
Re: [PATCH] asan: Fix up address sanitizer instrumentation of __builtin_alloca* if it can throw [PR104449]
> Am 12.02.2022 um 10:08 schrieb Jakub Jelinek via Gcc-patches
> :
>
> Hi!
>
> With -fstack-check=generic __builtin_alloca* can throw and the asan
> instrumentation of this builtin wasn't prepared for that case.
> The following patch fixes that by replacing the builtin with the
> replacement builtin and emitting any further insns on the fallthru
> edge.
>
> I haven't touched the hwasan code which most likely suffers from the
> same problem.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
Ok
Richard
> 2022-02-12 Jakub Jelinek
>
>PR sanitizer/104449
>* asan.cc: Include tree-eh.h.
>(handle_builtin_alloca): Handle the case when __builtin_alloca or
>__builtin_alloca_with_align can throw.
>
>* gcc.dg/asan/pr104449.c: New test.
>* g++.dg/asan/pr104449.C: New test.
>
> --- gcc/asan.cc.jj2022-01-18 11:58:58.876992143 +0100
> +++ gcc/asan.cc2022-02-11 19:09:39.752065877 +0100
> @@ -63,6 +63,7 @@ along with GCC; see the file COPYING3.
> #include "fnmatch.h"
> #include "tree-inline.h"
> #include "tree-ssa.h"
> +#include "tree-eh.h"
>
> /* AddressSanitizer finds out-of-bounds and use-after-free bugs
>with <2x slowdown on average.
> @@ -726,14 +727,24 @@ handle_builtin_alloca (gcall *call, gimp
> gassign *g;
> gcall *gg;
> tree callee = gimple_call_fndecl (call);
> + tree lhs = gimple_call_lhs (call);
> tree old_size = gimple_call_arg (call, 0);
> - tree ptr_type = gimple_call_lhs (call) ? TREE_TYPE (gimple_call_lhs (call))
> - : ptr_type_node;
> + tree ptr_type = lhs ? TREE_TYPE (lhs) : ptr_type_node;
> tree partial_size = NULL_TREE;
> unsigned int align
> = DECL_FUNCTION_CODE (callee) == BUILT_IN_ALLOCA
> ? 0 : tree_to_uhwi (gimple_call_arg (call, 1));
>
> + bool throws = false;
> + edge e = NULL;
> + if (stmt_can_throw_internal (cfun, call))
> +{
> + if (!lhs)
> +return;
> + throws = true;
> + e = find_fallthru_edge (gsi_bb (*iter)->succs);
> +}
> +
> if (hwasan_sanitize_allocas_p ())
> {
> gimple_seq stmts = NULL;
> @@ -852,29 +863,54 @@ handle_builtin_alloca (gcall *call, gimp
> build_int_cst (size_type_node, align));
> tree new_alloca_with_rz = make_ssa_name (ptr_type, gg);
> gimple_call_set_lhs (gg, new_alloca_with_rz);
> - gsi_insert_before (iter, gg, GSI_SAME_STMT);
> + if (throws)
> +{
> + gimple_call_set_lhs (call, NULL);
> + gsi_replace (iter, gg, true);
> +}
> + else
> +gsi_insert_before (iter, gg, GSI_SAME_STMT);
>
> /* new_alloca = new_alloca_with_rz + align. */
> g = gimple_build_assign (make_ssa_name (ptr_type), POINTER_PLUS_EXPR,
> new_alloca_with_rz,
> build_int_cst (size_type_node,
> align / BITS_PER_UNIT));
> - gsi_insert_before (iter, g, GSI_SAME_STMT);
> + gimple_stmt_iterator gsi = gsi_none ();
> + if (throws)
> +{
> + gsi_insert_on_edge_immediate (e, g);
> + gsi = gsi_for_stmt (g);
> +}
> + else
> +gsi_insert_before (iter, g, GSI_SAME_STMT);
> tree new_alloca = gimple_assign_lhs (g);
>
> /* Poison newly created alloca redzones:
> __asan_alloca_poison (new_alloca, old_size). */
> fn = builtin_decl_implicit (BUILT_IN_ASAN_ALLOCA_POISON);
> gg = gimple_build_call (fn, 2, new_alloca, old_size);
> - gsi_insert_before (iter, gg, GSI_SAME_STMT);
> + if (throws)
> +gsi_insert_after (&gsi, gg, GSI_NEW_STMT);
> + else
> +gsi_insert_before (iter, gg, GSI_SAME_STMT);
>
> /* Save new_alloca_with_rz value into last_alloca to use it during
> allocas unpoisoning. */
> g = gimple_build_assign (last_alloca, new_alloca_with_rz);
> - gsi_insert_before (iter, g, GSI_SAME_STMT);
> + if (throws)
> +gsi_insert_after (&gsi, g, GSI_NEW_STMT);
> + else
> +gsi_insert_before (iter, g, GSI_SAME_STMT);
>
> /* Finally, replace old alloca ptr with NEW_ALLOCA. */
> - replace_call_with_value (iter, new_alloca);
> + if (throws)
> +{
> + g = gimple_build_assign (lhs, new_alloca);
> + gsi_insert_after (&gsi, g, GSI_NEW_STMT);
> +}
> + else
> +replace_call_with_value (iter, new_alloca);
> }
>
> /* Return the memory references contained in a gimple statement
> --- gcc/testsuite/gcc.dg/asan/pr104449.c.jj2022-02-11 19:23:05.085974426
> +0100
> +++ gcc/testsuite/gcc.dg/asan/pr104449.c2022-02-11 19:26:20.537282682
> +0100
> @@ -0,0 +1,12 @@
> +/* PR sanitizer/104449 */
> +/* { dg-do compile } */
> +/* { dg-options "-fexceptions -fsanitize=address -fstack-check=generic" } */
> +
> +void bar (int *);
> +
> +void
> +foo (void)
> +{
> + int a[16];
> + bar (a);
> +}
> --- gcc/testsuite/g++.dg/asan/pr104449.C.jj2022-02-11 19:25:22.035088372
> +0100
> +++ gcc/testsuite/g++.dg/asan/pr104449.C2022-02-11 19:26:08.605447008
> +0100
> @@ -0,0 +1,16 @@
> +// PR sanitizer/104449
> +// { dg-do compile }
> +// { dg-options "-fexceptions -fsanitize=address -fstack-check=
Re: [PATCH] x86: Update PR 35513 tests
On Fri, Feb 11, 2022 at 9:43 PM Hongtao Liu wrote:
>
> On Thu, Feb 10, 2022 at 9:58 PM H.J. Lu via Gcc-patches
> wrote:
> >
> > 1. Require linker with GNU_PROPERTY_1_NEEDED support for PR 35513
> > run-time tests.
> > 2. Compile pr35513-8.c to scan assembly code.
> >
> > PR testsuite/104481
> > * g++.target/i386/pr35513-1.C: Require property_1_needed target.
> > * g++.target/i386/pr35513-2.C: Likewise.
> > * gcc.target/i386/pr35513-8.c: Change to compile.
> > * lib/target-supports.exp (check_compile): Support assembly code.
> > (check_effective_target_property_1_needed): New proc.
> This is for testcase fixup, and i think it should be ok.
I am checking it in.
Thanks.
> > ---
> > gcc/testsuite/g++.target/i386/pr35513-1.C | 2 +-
> > gcc/testsuite/g++.target/i386/pr35513-2.C | 2 +-
> > gcc/testsuite/gcc.target/i386/pr35513-8.c | 2 +-
> > gcc/testsuite/lib/target-supports.exp | 37 +++
> > 4 files changed, 40 insertions(+), 3 deletions(-)
> >
> > diff --git a/gcc/testsuite/g++.target/i386/pr35513-1.C
> > b/gcc/testsuite/g++.target/i386/pr35513-1.C
> > index 6f8db37fb7c..daa615662c5 100644
> > --- a/gcc/testsuite/g++.target/i386/pr35513-1.C
> > +++ b/gcc/testsuite/g++.target/i386/pr35513-1.C
> > @@ -1,4 +1,4 @@
> > -// { dg-do run }
> > +// { dg-do run { target property_1_needed } }
> > // { dg-options "-O2 -mno-direct-extern-access" }
> >
> > #include
> > diff --git a/gcc/testsuite/g++.target/i386/pr35513-2.C
> > b/gcc/testsuite/g++.target/i386/pr35513-2.C
> > index 9143ff3f0a5..ecccdaeb666 100644
> > --- a/gcc/testsuite/g++.target/i386/pr35513-2.C
> > +++ b/gcc/testsuite/g++.target/i386/pr35513-2.C
> > @@ -1,4 +1,4 @@
> > -// { dg-do run }
> > +// { dg-do run { target property_1_needed } }
> > // { dg-options "-O2 -mno-direct-extern-access" }
> >
> > class Foo
> > diff --git a/gcc/testsuite/gcc.target/i386/pr35513-8.c
> > b/gcc/testsuite/gcc.target/i386/pr35513-8.c
> > index 7ba67de2156..d51f7efb353 100644
> > --- a/gcc/testsuite/gcc.target/i386/pr35513-8.c
> > +++ b/gcc/testsuite/gcc.target/i386/pr35513-8.c
> > @@ -1,4 +1,4 @@
> > -/* { dg-do assemble { target { *-*-linux* && { ! ia32 } } } } */
> > +/* { dg-do compile { target { *-*-linux* && { ! ia32 } } } } */
> > /* { dg-require-effective-target maybe_x32 } */
> > /* { dg-options "-mx32 -O2 -fno-pic -fexceptions
> > -fasynchronous-unwind-tables -mno-direct-extern-access" } */
> >
> > diff --git a/gcc/testsuite/lib/target-supports.exp
> > b/gcc/testsuite/lib/target-supports.exp
> > index 4463cc8d7ed..0d8a7df5026 100644
> > --- a/gcc/testsuite/lib/target-supports.exp
> > +++ b/gcc/testsuite/lib/target-supports.exp
> > @@ -30,6 +30,7 @@
> > #
> > # Assume by default that CONTENTS is C code.
> > # Otherwise, code should contain:
> > +# "/* Assembly" for assembly code,
> > # "// C++" for c++,
> > # "// D" for D,
> > # "! Fortran" for Fortran code,
> > @@ -57,6 +58,7 @@ proc check_compile {basename type contents args} {
> > set options ""
> > }
> > switch -glob -- $contents {
> > + "*/* Assembly*" { set src ${basename}[pid].S }
> > "*! Fortran*" { set src ${basename}[pid].f90 }
> > "*// C++*" { set src ${basename}[pid].cc }
> > "*// D*" { set src ${basename}[pid].d }
> > @@ -11758,3 +11760,38 @@ proc check_effective_target_pytest3 { } {
> > return 0;
> > }
> > }
> > +
> > +proc check_effective_target_property_1_needed { } {
> > + return [check_no_compiler_messages_nocache property_1_needed executable {
> > +/* Assembly code */
> > +#ifdef __LP64__
> > +# define __PROPERTY_ALIGN 3
> > +#else
> > +# define __PROPERTY_ALIGN 2
> > +#endif
> > +
> > + .section ".note.gnu.property", "a"
> > + .p2align __PROPERTY_ALIGN
> > + .long 1f - 0f /* name length. */
> > + .long 4f - 1f /* data length. */
> > + /* NT_GNU_PROPERTY_TYPE_0. */
> > + .long 5 /* note type. */
> > +0:
> > + .asciz "GNU"/* vendor name. */
> > +1:
> > + .p2align __PROPERTY_ALIGN
> > + /* GNU_PROPERTY_1_NEEDED. */
> > + .long 0xb0008000/* pr_type. */
> > + .long 3f - 2f /* pr_datasz. */
> > +2:
> > + /* GNU_PROPERTY_1_NEEDED_INDIRECT_EXTERN_ACCESS. */
> > + .long 1
> > +3:
> > + .p2align __PROPERTY_ALIGN
> > +4:
> > + .text
> > + .globl main
> > +main:
> > + .byte 0
> > + } ""]
> > +}
> > --
> > 2.34.1
> >
>
>
> --
> BR,
> Hongtao
--
H.J.
[wwwdocs PATCH] gcc-12: Mention -mno-direct-extern-access
--- htdocs/gcc-12/changes.html | 3 +++ 1 file changed, 3 insertions(+) diff --git a/htdocs/gcc-12/changes.html b/htdocs/gcc-12/changes.html index b6341fda..897de8ef 100644 --- a/htdocs/gcc-12/changes.html +++ b/htdocs/gcc-12/changes.html @@ -399,6 +399,9 @@ a work-in-progress. Add CS prefix to call and jmp to indirect thunk with branch target in r8-r15 registers via -mindirect-branch-cs-prefix. + Always use GOT to access external data and function symbols via + -mno-direct-extern-access. + -- 2.34.1
Re: [wwwdocs PATCH] gcc-12: Mention -mno-direct-extern-access
On Sat, 12 Feb 2022, H.J. Lu via Gcc-patches wrote: > + Always use GOT to access external data and function symbols via > + -mno-direct-extern-access. Maybe say "global offset table (GOT)"? And at first I was confused reading this, so I suggest something like "...when the new -mno-direct-extern-access command-line option is specified" or "New command-line option ... that ..." ? Gerald
