[patch,doc] Remove dead/inactive links for GCC binaries
Attached patch cleans up the list of links we provide for GCC binaries: - pware.hvcc.edu is dead, no mirror or newer alternative found - h8300-hms.sourceforge.net is inactive since 2003, carries only gcc 3.2 and 3.3 - sunsite.informatik.rwth-aachen.de only has gcc 3.0.1 - SCO website has gcc 2.95.2 - ftp.thewrittenword.com only offers gcc 4.0.2 Tested with "make pdf info html", OK to commit? FX binaries.ChangeLog Description: Binary data binaries.diff Description: Binary data
Re: Fix PR debug/66728
Hello!
> This is yet another bug caused by rtx having modeless scalar integer
> constants. We need to use context to find the actual mode of a
> CONST_INT or CONST_WIDE_INT.
+++ b/gcc/testsuite/gcc.dg/debug/dwarf2/pr66728.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { x86_64-*-* && lp64 } } } */
Please also add i*86-*-* target with x86_64-*-*. These two should go
together, even when additional lp64 selector is used.
Uros.
Re: Fix PR debug/66728
On Sat, Aug 22, 2015 at 10:02 AM, Uros Bizjak wrote:
> Hello!
>
>> This is yet another bug caused by rtx having modeless scalar integer
>> constants. We need to use context to find the actual mode of a
>> CONST_INT or CONST_WIDE_INT.
>
> +++ b/gcc/testsuite/gcc.dg/debug/dwarf2/pr66728.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile { target { x86_64-*-* && lp64 } } } */
>
> Please also add i*86-*-* target with x86_64-*-*. These two should go
> together, even when additional lp64 selector is used.
Actually, i?86-*-*
Uros.
Re: [PATCHv2/AARCH64] Remove index from AARCH64_EXTRA_TUNING_OPTION
On Thu, Aug 20, 2015 at 12:08 AM, James Greenhalgh
wrote:
> On Wed, Aug 19, 2015 at 05:00:14PM +0100, Andrew Pinski wrote:
>> Just like the patch for AARCH64_FUSION_PAIR, this is a patch for
>> AARCH64_EXTRA_TUNING_OPTION. Note I tested this patch on top of the
>> patch for AARCH64_EXTRA_TUNING_OPTION.
>>
>> Changes in v2:
>> Remove the hack for AARCH64_EXTRA_TUNE_ALL.
>>
>> Remove index from AARCH64_EXTRA_TUNING_OPTION
>>
>> Instead of doing an explict index in aarch64-tuning-flags.def, we
>> should have an enum which does the index instead. This allows
>> you to add/remove them without worrying about the order being
>> correct and having holes or worry about merge conficts.
>>
>> OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions.
>
> -ENOPATCH, but assuming this is along the same lines as the one I just
> acked, I'm happy for you to consider this preapproved (after checking
> the comments below). Please send a copy to the list for the archives.
Attached. Yes I just had forgot to attach it when I sent this one out.
>
>> ChangeLog:
>> * config/aarch64/aarch64-tuning-flags.def: Remove all index to
>> AARCH64_EXTRA_TUNING_OPTION.
>> * config/aarch64/aarch64-protos.h (extra_tuning_flags_index): New enum.
>
> I'm guessing that this has a more aarch64-centric name like
> aarch64_extra_tuning_flags_index ? If not, it probably should have just to
> fit with the naming scheme in the rest of the file.
That was just a copy and paste error into the ChangeLog.
The name in the aarch64-protos.h is aarch64_extra_tuning_flags_index.
>
>> (aarch64_extra_tuning_flags): Base the shifted value on the index instead
>> of the argument to AARCH64_EXTRA_TUNING_OPTION.
>> * config/aarch64/aarch64.c: Remove the last argument to
>> AARCH64_EXTRA_TUNING_OPTION..
>
> Watch out for the extra . on the end of this ChangeLog line..
Got it will fix.
Thanks,
Andrew
>
> Thanks,
> James
>
>>
commit b109e73f5966827d99b9abd8c9c45dc897604ccd
Author: Andrew Pinski
Date: Wed Aug 19 01:15:00 2015 -0700
Remove index from AARCH64_EXTRA_TUNING_OPTION
Instead of doing an explict index in aarch64-tuning-flags.def, we
should have an enum which does the index instead. This allows
you to add/remove them without worrying about the order being
correct and having holes or worry about merge conficts.
OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions.
ChangeLog:
* config/aarch64/aarch64-tuning-flags.def: Remove all index to
AARCH64_EXTRA_TUNING_OPTION.
* config/aarch64/aarch64-protos.h (extra_tuning_flags_index): New enum.
(aarch64_extra_tuning_flags): Base the shifted value on the index instead
of the argument to AARCH64_EXTRA_TUNING_OPTION.
* config/aarch64/aarch64.c: Remove the last argument to
AARCH64_EXTRA_TUNING_OPTION..
diff --git a/gcc/config/aarch64/aarch64-protos.h
b/gcc/config/aarch64/aarch64-protos.h
index 057d4fc..a12dec5 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -222,21 +222,25 @@ enum aarch64_fusion_pairs
};
#undef AARCH64_FUSION_PAIR
-#define AARCH64_EXTRA_TUNING_OPTION(x, name, index) \
- AARCH64_EXTRA_TUNE_##name = (1 << index),
+#define AARCH64_EXTRA_TUNING_OPTION(x, name) \
+ AARCH64_EXTRA_TUNE_##name##_index,
+/* Supported tuning flags indexes. */
+enum aarch64_extra_tuning_flags_index
+{
+#include "aarch64-tuning-flags.def"
+ AARCH64_EXTRA_TUNE_index_END
+};
+#undef AARCH64_EXTRA_TUNING_OPTION
+
+
+#define AARCH64_EXTRA_TUNING_OPTION(x, name) \
+ AARCH64_EXTRA_TUNE_##name = (1u << AARCH64_EXTRA_TUNE_##name##_index),
/* Supported tuning flags. */
enum aarch64_extra_tuning_flags
{
AARCH64_EXTRA_TUNE_NONE = 0,
#include "aarch64-tuning-flags.def"
-
-/* Hacky macro to build the "all" flag mask.
- Expands to 0 | AARCH64_TUNE_index0 | AARCH64_TUNE_index1 , etc. */
-#undef AARCH64_EXTRA_TUNING_OPTION
-#define AARCH64_EXTRA_TUNING_OPTION(x, name, y) \
- | AARCH64_EXTRA_TUNE_##name
- AARCH64_EXTRA_TUNE_ALL = 0
-#include "aarch64-tuning-flags.def"
+ AARCH64_EXTRA_TUNE_ALL = (1u << AARCH64_EXTRA_TUNE_index_END) - 1
};
#undef AARCH64_EXTRA_TUNING_OPTION
diff --git a/gcc/config/aarch64/aarch64-tuning-flags.def
b/gcc/config/aarch64/aarch64-tuning-flags.def
index 01aaca8..628386b 100644
--- a/gcc/config/aarch64/aarch64-tuning-flags.def
+++ b/gcc/config/aarch64/aarch64-tuning-flags.def
@@ -20,15 +20,13 @@
/* Additional control over certain tuning parameters. Before including
this file, define a macro:
- AARCH64_EXTRA_TUNING_OPTION (name, internal_name, index_bit)
+ AARCH64_EXTRA_TUNING_OPTION (name, internal_name)
Where:
NAME is a string giving a friendly name for the tuning flag.
INTERNAL_NAME gives the internal name suitable for appending to
- AARCH64_TUNE_ to give an enum name.
- INDEX_BIT is the bit to set in the bitmask of supported tuning
- flags. */
+ A
Fix PR libgomp/66761 and PR libgomp/67303 (tsan warnings)
The following fixes two warnings reported by tsan when running OMP'ed code. As
suggested by Andrew Pinski in PR67303 for gomp_iter_guided_next, by employing a
relaxed atomic load. The same pattern occurred a couple of more times, so fixed
as well. I used the same approach for the warning in do_spin (PR66761), even
though this is a different context.
Bootstrapped and regtested on x86_64-unknown-linux-gnu for trunk, and manually
verified that the PR is fixed using a tsan compiled libgomp based on gcc-5.1.
OK for trunk ?
This applies without changes to the 5 branch, should I commit there as well ?
libgomp/ChangeLog:
2015-08-22 Joost VandeVondele
PR libgomp/66761
PR libgomp/67303
* iter.c (gomp_iter_dynamic_next): Employ an atomic load.
(gomp_iter_guided_next): Idem.
* iter_ull.c (gomp_iter_ull_dynamic_next): Idem.
(gomp_iter_ull_guided_next): Idem.
* config/linux/wait.h (do_spin): Idem.
Index: libgomp/iter.c
===
--- libgomp/iter.c (revision 227094)
+++ libgomp/iter.c (working copy)
@@ -218,7 +218,7 @@ gomp_iter_dynamic_next (long *pstart, lo
}
}
- start = ws->next;
+ start = __atomic_load_n (&ws->next, MEMMODEL_RELAXED);
while (1)
{
long left = end - start;
@@ -301,7 +301,7 @@ gomp_iter_guided_next (long *pstart, lon
long start, end, nend, incr;
unsigned long chunk_size;
- start = ws->next;
+ start = __atomic_load_n (&ws->next, MEMMODEL_RELAXED);
end = ws->end;
incr = ws->incr;
chunk_size = ws->chunk_size;
Index: libgomp/iter_ull.c
===
--- libgomp/iter_ull.c (revision 227094)
+++ libgomp/iter_ull.c (working copy)
@@ -219,7 +219,7 @@ gomp_iter_ull_dynamic_next (gomp_ull *ps
}
}
- start = ws->next_ull;
+ start = __atomic_load_n (&ws->next_ull, MEMMODEL_RELAXED);
while (1)
{
gomp_ull left = end - start;
@@ -305,7 +305,7 @@ gomp_iter_ull_guided_next (gomp_ull *pst
gomp_ull start, end, nend, incr;
gomp_ull chunk_size;
- start = ws->next_ull;
+ start = __atomic_load_n (&ws->next_ull, MEMMODEL_RELAXED);
end = ws->end_ull;
incr = ws->incr_ull;
chunk_size = ws->chunk_size_ull;
Index: libgomp/config/linux/wait.h
===
--- libgomp/config/linux/wait.h (revision 227094)
+++ libgomp/config/linux/wait.h (working copy)
@@ -49,7 +49,8 @@ static inline int do_spin (int *addr, in
{
unsigned long long i, count = gomp_spin_count_var;
- if (__builtin_expect (gomp_managed_threads > gomp_available_cpus, 0))
+ if (__builtin_expect (__atomic_load_n (&gomp_managed_threads,
+ MEMMODEL_RELAXED) > gomp_available_cpus, 0))
count = gomp_throttled_spin_count_var;
for (i = 0; i < count; i++)
if (__builtin_expect (__atomic_load_n (addr, MEMMODEL_RELAXED) != val, 0))
[gomp4] Calling partitoned routines
I've committed this to gomp4. It gets partitioned routines working by
surrounding the call by fork & join instructions such that the right number of
active threads get to the call.
nathan
2015-08-22 Nathan Sidwell
gcc/
* omp-low.c (build_oacc_routine_dims): Size non-partitioned
levels to 1.
* config/nvptx/nvptx.c (nvptx_expand_call): Move later, emit
forking and joining instructions.
(nvptx_process_pars): Cope with both Worker and Vector being set.
libgomp/
* testsuite/libgomp.oacc-c-c++-common/routine-vec-1.c: New.
* testsuite/libgomp.oacc-c-c++-common/routine-work-1.c: New.
Index: gcc/omp-low.c
===
--- gcc/omp-low.c (revision 227089)
+++ gcc/omp-low.c (working copy)
@@ -9374,7 +9374,10 @@ set_oacc_fn_attrib (tree fn, tree clause
(dynamic). TREE_PURPOSE is set to indicate whether that dimension
can have a loop partitioned on it. non-zero indicates
yes, zero indicates no. By construction once a non-zero has been
-reached, further inner dimensions must also be non-zero. */
+reached, further inner dimensions must also be non-zero. We set
+TREE_VALUE to zero for the dimensions that may be partitioned and
+1 for the other ones -- if a loop is (erroneously) spawned at
+an outer level, we don't want to try and partition it. */
tree
build_oacc_routine_dims (tree clauses)
@@ -9404,7 +9407,7 @@ build_oacc_routine_dims (tree clauses)
for (ix = GOMP_DIM_MAX; ix--;)
dims = tree_cons (build_int_cst (boolean_type_node, ix >= level),
- integer_zero_node, dims);
+ build_int_cst (integer_type_node, ix < level), dims);
return dims;
}
Index: gcc/config/nvptx/nvptx.c
===
--- gcc/config/nvptx/nvptx.c (revision 227089)
+++ gcc/config/nvptx/nvptx.c (working copy)
@@ -840,127 +840,6 @@ nvptx_end_call_args (void)
free_EXPR_LIST_list (&cfun->machine->call_args);
}
-/* Emit the sequence for a call to ADDRESS, setting RETVAL. Keep
- track of whether calls involving static chains or varargs were seen
- in the current function.
- For libcalls, maintain a hash table of decls we have seen, and
- record a function decl for later when encountering a new one. */
-
-void
-nvptx_expand_call (rtx retval, rtx address)
-{
- int nargs = 0;
- rtx callee = XEXP (address, 0);
- rtx pat, t;
- rtvec vec;
- bool external_decl = false;
- rtx varargs = NULL_RTX;
- tree decl_type = NULL_TREE;
- unsigned parallel = 0;
-
- for (t = cfun->machine->call_args; t; t = XEXP (t, 1))
-nargs++;
-
- if (!call_insn_operand (callee, Pmode))
-{
- callee = force_reg (Pmode, callee);
- address = change_address (address, QImode, callee);
-}
-
- if (GET_CODE (callee) == SYMBOL_REF)
-{
- tree decl = SYMBOL_REF_DECL (callee);
- if (decl != NULL_TREE)
- {
- decl_type = TREE_TYPE (decl);
- if (DECL_STATIC_CHAIN (decl))
- cfun->machine->has_call_with_sc = true;
- if (DECL_EXTERNAL (decl))
- external_decl = true;
- tree attr = get_oacc_fn_attrib (decl);
- if (attr)
- {
- tree dims = TREE_VALUE (attr);
-
- for (int ix = 0; ix != GOMP_DIM_MAX; ix++)
- {
- if (TREE_PURPOSE (dims)
- && !integer_zerop (TREE_PURPOSE (dims)))
- {
- parallel = GOMP_DIM_MASK (GOMP_DIM_MAX) - 1;
- if (ix)
- parallel ^= GOMP_DIM_MASK (ix - 1) - 1;
- break;
- }
- dims = TREE_CHAIN (dims);
- }
- }
- }
-}
-
- if (cfun->machine->funtype
- /* It's possible to construct testcases where we call a variable.
- See compile/20020129-1.c. stdarg_p will crash so avoid calling it
- in such a case. */
- && (TREE_CODE (cfun->machine->funtype) == FUNCTION_TYPE
- || TREE_CODE (cfun->machine->funtype) == METHOD_TYPE)
- && stdarg_p (cfun->machine->funtype))
-{
- varargs = gen_reg_rtx (Pmode);
- if (Pmode == DImode)
- emit_move_insn (varargs, stack_pointer_rtx);
- else
- emit_move_insn (varargs, stack_pointer_rtx);
- cfun->machine->has_call_with_varargs = true;
-}
- vec = rtvec_alloc (nargs + 1 + (varargs ? 1 : 0));
- pat = gen_rtx_PARALLEL (VOIDmode, vec);
-
- int vec_pos = 0;
-
- rtx tmp_retval = retval;
- t = gen_rtx_CALL (VOIDmode, address, const0_rtx);
- if (retval != NULL_RTX)
-{
- if (!nvptx_register_operand (retval, GET_MODE (retval)))
- tmp_retval = gen_reg_rtx (GET_MODE (retval));
- t = gen_rtx_SET (tmp_retval, t);
-}
- XVECEXP (pat, 0, vec_pos++) = t;
-
- /* Construct the call insn, including a USE for each argument pseudo
- register. These will be used when printing the insn. */
- for (rtx arg = cfun->machine->call_args; arg; arg = XEXP (arg, 1))
-{
- rtx this_arg = XEXP (arg, 0);
- XVECEXP (pat, 0, vec_pos++) = gen_rtx_USE (VOIDmode, this_arg);
-}
-
- if (varargs)
- XVECEXP (pat, 0, vec_pos++) = gen_rtx_USE (VOIDmode, varargs);
-
- gcc
Re: Elimitate duplication of get_catalogs in different abi
2015-08-21 23:11 GMT+02:00 François Dumont : > I think I found a better way to handle this problem. It is c++locale.cc > that needs to be built with --fimplicit-templates. I even think that the > *_cow.cc file do not need this option but as I don't know what is the > drawback of this option I kept it. I also explicitely used the file name > c++locale.cc even if it is an alias to a configurable source file. I > guess there must be some variable to use no ? > > With this patch there are 6 additional symbols. I guess I need to > declare those in the scripts even if it is for internal library usage, > right ? I would expect that the new Catalog_info definition either has deleted or properly (user-)defined copy constructor and copy assignment operator. - Daniel
[obvious c-family] Fix column location in c_lex_with_flags errors
input_location is not always up-to-date in the preprocessor. Using the
actual token's location is always best. Bootstrapped & regtested on
x86-64-linux-gnu & committed as obvious https://gcc.gnu.org/r227096
Cheers,
Manuel.
Fix column location in c_lex_with_flags errors
gcc/testsuite/ChangeLog:
2015-08-22 Manuel López-Ibáñez
* gcc.dg/cpp/multiline-2.c: Add column numbers.
* gcc.dg/dollar.c: Likewise.
* gcc.dg/pragma-message.c: Likewise.
* g++.dg/cpp1y/digit-sep-neg.C: Likewise.
* c-c++-common/raw-string-14.c: Likewise.
gcc/c-family/ChangeLog:
2015-08-22 Manuel López-Ibáñez
* c-lex.c (c_lex_with_flags): Use explicit locations.
Index: gcc/c-family/c-lex.c
===
--- gcc/c-family/c-lex.c(revision 226953)
+++ gcc/c-family/c-lex.c(working copy)
@@ -521,15 +521,15 @@ c_lex_with_flags (tree *value, location_
case CPP_OTHER:
{
cppchar_t c = tok->val.str.text[0];
if (c == '"' || c == '\'')
- error ("missing terminating %c character", (int) c);
+ error_at (*loc, "missing terminating %c character", (int) c);
else if (ISGRAPH (c))
- error ("stray %qc in program", (int) c);
+ error_at (*loc, "stray %qc in program", (int) c);
else
- error ("stray %<\\%o%> in program", (int) c);
+ error_at (*loc, "stray %<\\%o%> in program", (int) c);
}
goto retry;
case CPP_CHAR_USERDEF:
case CPP_WCHAR_USERDEF:
Index: gcc/testsuite/gcc.dg/cpp/multiline-2.c
===
--- gcc/testsuite/gcc.dg/cpp/multiline-2.c (revision 226953)
+++ gcc/testsuite/gcc.dg/cpp/multiline-2.c (working copy)
@@ -7,8 +7,8 @@
const char *p = "line 1
"
""; /* The compiler front end sees this. */
-/* { dg-error "missing term" "multiline strings" { target *-*-* } 8 } */
+/* { dg-error "17:missing term" "multiline strings" { target *-*-* } 8 } */
/* { dg-error "missing term" "multiline strings" { target *-*-* } 9 } */
Index: gcc/testsuite/gcc.dg/dollar.c
===
--- gcc/testsuite/gcc.dg/dollar.c (revision 226953)
+++ gcc/testsuite/gcc.dg/dollar.c (working copy)
@@ -4,6 +4,6 @@
/* { dg-options -fno-dollars-in-identifiers } */
/* Test that -fno-dollars-in-identifiers is honoured.
Neil Booth, 17 May 2003. */
-int foobar$; /* { dg-error "stray '\\$'" } */
+int foobar$; /* { dg-error "11:stray '\\$'" } */
Index: gcc/testsuite/gcc.dg/pragma-message.c
===
--- gcc/testsuite/gcc.dg/pragma-message.c (revision 226953)
+++ gcc/testsuite/gcc.dg/pragma-message.c (working copy)
@@ -14,17 +14,17 @@
then 'note: #pragma message: ', allowing dg-message to check output.
If unexpected pragma messages are printed (anything not caught by a
matching dg-message), dejagnu will report these as excess errors. */
#pragma message "
-/* { dg-error "missing terminating" "" { target *-*-* } 18 } */
+/* { dg-error "17:missing terminating" "" { target *-*-* } 18 } */
/* { dg-warning "expected a string" "" { target *-*-* } 18 } */
#pragma message "Bad 1
-/* { dg-error "missing terminating" "" { target *-*-* } 21 } */
+/* { dg-error "17:missing terminating" "" { target *-*-* } 21 } */
/* { dg-warning "expected a string" "" { target *-*-* } 21 } */
#pragma message ("Bad 2
-/* { dg-error "missing terminating" "" { target *-*-* } 24 } */
+/* { dg-error "18:missing terminating" "" { target *-*-* } 24 } */
/* { dg-warning "expected a string" "" { target *-*-* } 24 } */
#pragma message ("Bad 3"
/* { dg-warning "malformed '#pragma message" "" { target *-*-* } 27 } */
#pragma message "" junk
Index: gcc/testsuite/g++.dg/cpp1y/digit-sep-neg.C
===
--- gcc/testsuite/g++.dg/cpp1y/digit-sep-neg.C (revision 226953)
+++ gcc/testsuite/g++.dg/cpp1y/digit-sep-neg.C (working copy)
@@ -8,22 +8,22 @@ main()
i = 0X'10; // { dg-error "digit separator after base indicator" }
i = 0x'10; // { dg-error "digit separator after base indicator" }
i = 0004''000'000; // { dg-error "adjacent digit separators" }
i = 0B1'0'0'0'0'0'0'0'0'0'0'0'0'0'0'0'0'0'0'0'0; // OK
i = 0b'0001'''''; // { dg-error "digit separator after
base indicator" }
- i = 0b0001''''''; // { dg-error "missing terminating" }
+ i = 0b0001''''''; // { dg-error "38:missing terminating"
}
unsigned u = 0b0001''''''U; // { dg-error "digit
separator outside digit sequence" }
double d = 0.0;
d = 1'.602'176'565e-19; // { dg-error "digit separator adjacent to decimal
point" }
d = 1.'602'176'565e-19; // { dg-error "digit separator adjacent to decimal
po
Re: [obvious c-family] Fix column location in c_lex_with_flags errors
OK. Jason
Re: [C++ Patch] PR 63693
OK. Jason
[nvptx] markup alloca tests
nvptx cannot support alloca, this marks up the tests that use alloca directly
or indirectly (mainly via VLAs).
I checked x86_64-linux test results are unaffected.
committed to trunk.
nathan
2015-08-22 Nathan Sidwell
* c-c++-common/Wsizeof-pointer-memaccess1.c: Require alloca.
* c-c++-common/Wsizeof-pointer-memaccess2.c: Likewise.
* c-c++-common/Wunused-var-8.c: Likewise.
* c-c++-common/gomp/pr61486-2.c: Likewise.
* c-c++-common/Wunused-var-6.c: Likewise.
* c-c++-common/goacc/reduction-1.c: Likewise.
* c-c++-common/goacc/reduction-2.c: Likewise.
* c-c++-common/goacc/reduction-3.c: Likewise.
* c-c++-common/goacc/reduction-4.c: Likewise.
* gcc.dg/builtins-64.c: Likewise.
* gcc.dg/pr59523.c: Likewise.
* gcc.dg/tree-ssa/20080530.c: Likewise.
* gcc.dg/tree-ssa/pr23848-2.c: Likewise.
* gcc.dg/tree-ssa/pr23848-4.c: Likewise.
* gcc.dg/tree-ssa/pr23848-1.c: Likewise.
* gcc.dg/tree-ssa/pr23848-3.c: Likewise.
* gcc.dg/tree-ssa/20030807-2.c: Likewise.
* gcc.dg/pr59011.c: Likewise.
* gcc.dg/uninit-9.c: Likewise.
* gcc.dg/pr61561.c: Likewise.
* gcc.dg/vla-4.c: Likewise.
* gcc.dg/20101010-1.c: Likewise.
* gcc.dg/pr49120.c: Likewise.
* gcc.dg/20030331-2.c: Likewise.
* gcc.dg/compat/struct-by-value-22_main.c: Likewise.
* gcc.dg/pr25682.c: Likewise.
* gcc.dg/guality/guality.c: Likewise.
* gcc.dg/pr27301.c: Likewise.
* gcc.dg/uninit-9-O0.c: Likewise.
* gcc.dg/fold-alloca-1.c: Likewise.
* gcc.dg/pr41470.c: Likewise.
* gcc.dg/pr51491-2.c: Likewise.
* gcc.dg/winline-7.c: Likewise.
* gcc.dg/vla-2.c: Likewise.
* gcc.dg/pr50764.c: Likewise.
* gcc.dg/c99-vla-1.c: Likewise.
* gcc.dg/pr33238.c: Likewise.
* gcc.dg/c99-const-expr-13.c: Likewise.
* gcc.dg/builtin-return-1.c: Likewise.
* gcc.dg/vla-3.c: Likewise.
* gcc.dg/20020415-1.c: Likewise.
* gcc.dg/Wsizeof-pointer-memaccess1.c: Likewise.
* gcc.dg/shrink-wrap-alloca.c: Likewise.
* gcc.dg/Wstrict-aliasing-bogus-vla-1.c: Likewise.
* gcc.dg/torture/calleesave-sse.c: Likewise.
* gcc.dg/torture/Wsizeof-pointer-memaccess1.c: Likewise.
* gcc.dg/gomp/vla-2.c: Likewise.
* gcc.dg/gomp/vla-3.c: Likewise.
* gcc.dg/gomp/vla-4.c: Likewise.
* gcc.dg/gomp/pr30494.c: Likewise.
* gcc.dg/gomp/vla-5.c: Likewise.
* gcc.dg/pr51990-2.c: Likewise.
* gcc.dg/vla-22.c: Likewise.
Index: gcc/testsuite/c-c++-common/Wsizeof-pointer-memaccess1.c
===
--- gcc/testsuite/c-c++-common/Wsizeof-pointer-memaccess1.c (revision 227083)
+++ gcc/testsuite/c-c++-common/Wsizeof-pointer-memaccess1.c (working copy)
@@ -2,6 +2,7 @@
/* { dg-do compile } */
/* { dg-options "-Wall -Wno-sizeof-array-argument" } */
/* { dg-options "-Wall -Wno-sizeof-array-argument -Wno-c++-compat" { target c } } */
+/* { dg-require-effective-target alloca } */
typedef __SIZE_TYPE__ size_t;
#ifdef __cplusplus
Index: gcc/testsuite/c-c++-common/Wsizeof-pointer-memaccess2.c
===
--- gcc/testsuite/c-c++-common/Wsizeof-pointer-memaccess2.c (revision 227083)
+++ gcc/testsuite/c-c++-common/Wsizeof-pointer-memaccess2.c (working copy)
@@ -2,6 +2,7 @@
/* { dg-do compile } */
/* { dg-options "-Wall -O2 -Wno-sizeof-array-argument" } */
/* { dg-options "-Wall -O2 -Wno-sizeof-array-argument -Wno-c++-compat" {target c} } */
+/* { dg-require-effective-target alloca } */
#define bos(ptr) __builtin_object_size (ptr, 1)
#define bos0(ptr) __builtin_object_size (ptr, 0)
Index: gcc/testsuite/c-c++-common/Wunused-var-8.c
===
--- gcc/testsuite/c-c++-common/Wunused-var-8.c (revision 227083)
+++ gcc/testsuite/c-c++-common/Wunused-var-8.c (working copy)
@@ -1,6 +1,7 @@
/* Origin: PR c++/44108 */
/* { dg-options "-Wunused" } */
/* { dg-do compile } */
+/* { dg-require-effective-target alloca } */
int
foo ()
Index: gcc/testsuite/c-c++-common/gomp/pr61486-2.c
===
--- gcc/testsuite/c-c++-common/gomp/pr61486-2.c (revision 227083)
+++ gcc/testsuite/c-c++-common/gomp/pr61486-2.c (working copy)
@@ -1,6 +1,7 @@
/* PR middle-end/61486 */
/* { dg-do compile } */
/* { dg-options "-fopenmp" } */
+/* { dg-require-effective-target alloca } */
#pragma omp declare target
void dosomething (int *a, int n, int m);
Index: gcc/testsuite/c-c++-common/Wunused-var-6.c
===
--- gcc/testsuite/c-c++-common/Wunused-var-6.c (revision 227083)
+++ gcc/testsuite/c-c++-common/Wunused-var-6.c (working copy)
@@ -1,6 +1,7 @@
/* PR c/43981 */
/* { dg-do compile } */
/* { dg-options "-Wunused" } */
+/* { dg-require-effective-target alloca } */
void g (char *);
Index: gcc/testsuite/c-c++-common/goacc/reduction-1.c
===
--- gcc/testsuite/c-c++-common/goacc/reduction-1.c (revision 227083)
+++ gcc/testsuite/c-c++-common/goacc/reduction-1.c (working cop
Re: [PATCH], PR target/67211, Fix PowerPC 'insn does not satisfy its constraints' error on GCC 5
On Thu, Aug 20, 2015 at 5:15 PM, Michael Meissner wrote: > PR 67211 is an error that shows up on the GCC 5.x branch when the test case is > compiled with -mcpu=power7 -mtune=power8 -O3. In looking at the code, I > noticed > that the code optimized adjancent 64-bit integer/pointers in a structure from > DImode to V2DImode. The compiler optimized these to the vector registers, and > then tried to move a common field used later back to the GPR field. If the cpu > was power8, it would be able to use the direct move instructions, but on > power7 > those instructions don't exist. The current trunk compiler has dialed back on > the optimization, and it no longer tries to optimize adjacent fields in this > particular case to V2DImode, but it is an issue in the GCC 5 branch. > > In debugging the issue, I noticed the -mefficient-unaligned-VSX option was > being set if -mtune=power8 was used, even if the architecture was not a > power8. Efficient unaligned VSX is an architecture feature, and not a tuning > feature. In fixing this to be an architecture feature, it no longer tried to > do > the V2DImode optimization because it didn't have fast unaligned support. > > I have checked this on a big endian power7 and a little endian power8 system, > using the GCC 5.x patches and the patches for the trunk. There were no > regressions in any of the runs. Is it ok to install these patches on both the > GCC 5.x branch and trunk? > > I would like to commit a similar patch for the 4.9 branch as well. Is this ok? > > Note, due to rs6000.opt being slightly different between GCC 5.x and trunk, > there are two different patches, one for GCC 5.x and the other for GCC 6.x > (trunk). > > [gcc] > 2015-08-20 Michael Meissner > > PR target/67211 > * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Set > -mefficient-unaligned-vsx on ISA 2.7. > > * config/rs6000/rs6000.opt (-mefficient-unaligned-vsx): Convert > option to a masked option. > > * config/rs6000/rs6000.c (rs6000_option_override_internal): Rework > logic for -mefficient-unaligned-vsx so that it is set via an arch > ISA option, instead of being set if -mtune=power8 is set. Move > -mefficient-unaligned-vsx and -mallow-movmisalign handling to be > near other default option handling. > > [gcc/testsuite] > 2015-08-20 Michael Meissner > > PR target/67211 > * g++.dg/pr67211.C: New test. Okay everywhere. Thanks, David
Re: [PATCH] config: fix AM_ICONV for in-tree libiconv
On 05/29/2015 10:25 PM, Yaakov Selkowitz wrote: > This is the second in a series of patches to make a build with an > in-tree GNU libiconv work as designed. > > Currently GDB is the only toolchain component which actually uses an > in-tree libiconv. This patch modifies the common AM_ICONV to use an > in-tree libiconv when present and not already provided by libc. (GDB's > workaround uses an in-tree libiconv even when libc provides iconv(3); > I'm not sure when or why that would be desirable.) > > Once these two patches are merged in to each tree, I will follow with > patches to regenerate the various configure scripts and a few other > minor corresponding changes. I noticed that regenerating binutils/configure or gdb/configure undoes the libiconv changes done here: commit 016a3251631341bf4d8fe50966d2b70f8ea69e96 Author: DJ Delorie AuthorDate: Thu Aug 6 18:35:26 2015 -0400 Commit: DJ Delorie CommitDate: Thu Aug 6 23:55:06 2015 -0400 Yaakov Selkowitz: fixes for in-tree libiconv * Makefile.def (libiconv): Define bootstrap=true. Mark pdf/html/info as missing. (configure-gcc): Depend on all-libiconv. (all-gcc): Ditto. (configure-libcpp): Ditto. (all-libcpp): Ditto. (configure-intl): Ditto. (all-intl): Ditto. * Makefile.in: Regenerate. binutils/ * configure: Regenerate. gdb/ * Makefile.in (LIBICONV): Define. (CLIBS): Add LIBICONV. * acinclude.m4: Use config/iconv.m4 instead of custom AM_ICONV. * configure: Regenerate. However, that commit does not include any config/iconv.m4/AM_ICONV change. Looks like you forgot to attach the config/iconv.m4 patch, and then only the regeneration bits were pushed (both binutils-gdb git and gcc svn)? Thanks, Pedro Alves
Re: [ARM] Use vector wide add for mixed-mode adds
This is a modified version of the previous patch that addresses issue
raised by Ramana. The patch now uses vect_select instead of unspec.
I had to fix an unrelated issue to the read_name function in read-md.c.
The fix corrects broken support for mode iterators inside '<>'. Without
this fix support for rtl expression such 'plus:' were broken.
A second unrelated issue to this patch is correcting the documentation
for the standard names for wide add support
This patch is designed to address code that was not being vectorized due
to missing widening patterns in the ARM backend. Code such as:
int t6(int len, void * dummy, short * __restrict x)
{
len = len & ~31;
int result = 0;
__asm volatile ("");
for (int i = 0; i < len; i++)
result += x[i];
return result;
}
Validated on arm-none-eabi, arm-none-linux-gnueabi,
arm-none-linux-gnueabihf, and armeb-none-linux-gnueabihf.
--
2015-08-21 Michael Collison
* config/arm/neon.md (widen_sum): New patterns
where mode is VQI to improve mixed mode vectorization.
* read-md.c (read_name): Allow mode iterators inside '<>' in rtl
expressions.
* doc/md.texi: Rename [su]sum_widen to widen_[su]sum to reflect
correct standard name
* gcc.target/arm/neon-vaddws16.c: New test.
* gcc.target/arm/neon-vaddws32.c: New test.
* gcc.target/arm/neon-vaddwu16.c: New test.
* gcc.target/arm/neon-vaddwu32.c: New test.
* gcc.target/arm/neon-vaddwu8.c: New test.
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 654d9d5..54623fe 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -1174,6 +1174,57 @@
;; Widening operations
+(define_expand "widen_ssum3"
+ [(set (match_operand: 0 "s_register_operand" "")
+(plus: (sign_extend:
(match_operand:VQI 1 "s_register_operand" ""))
+ (match_operand: 2
"s_register_operand" "")))]
+ "TARGET_NEON"
+ {
+int i;
+int half_elem = /2;
+rtvec v1 = rtvec_alloc (half_elem);
+rtvec v2 = rtvec_alloc (half_elem);
+rtx p1, p2;
+
+for (i = 0; i < half_elem; i++)
+ RTVEC_ELT (v1, i) = GEN_INT (i);
+p1 = gen_rtx_PARALLEL (GET_MODE (operands[1]), v1);
+
+for (i = half_elem; i < ; i++)
+ RTVEC_ELT (v2, i - half_elem) = GEN_INT (i);
+p2 = gen_rtx_PARALLEL (GET_MODE (operands[1]), v2);
+
+if (operands[0] != operands[2])
+ emit_move_insn (operands[0], operands[2]);
+
+emit_insn (gen_vec_sel_widen_ssum_lo3 (operands[0],
operands[1], p1, operands[0]));
+emit_insn (gen_vec_sel_widen_ssum_hi3 (operands[0],
operands[1], p2, operands[0]));
+DONE;
+ }
+)
+
+(define_insn "vec_sel_widen_ssum_lo3"
+ [(set (match_operand: 0 "s_register_operand" "=w")
+(plus: (sign_extend: (vec_select:VW
(match_operand:VQI 1 "s_register_operand" "%w")
+ (match_operand:VQI 2 "vect_par_constant_low"
"")))
+(match_operand: 3 "s_register_operand" "0")))]
+ "TARGET_NEON"
+ "vaddw.\t%q0, %q3, %e1"
+ [(set_attr "type" "neon_add_widen")
+ (set_attr "length" "8")]
+)
+
+(define_insn "vec_sel_widen_ssum_hi3"
+ [(set (match_operand: 0 "s_register_operand" "=w")
+(plus: (sign_extend: (vec_select:VW
(match_operand:VQI 1 "s_register_operand" "%w")
+ (match_operand:VQI 2
"vect_par_constant_high" "")))
+(match_operand: 3 "s_register_operand" "0")))]
+ "TARGET_NEON"
+ "vaddw.\t%q0, %q3, %f1"
+ [(set_attr "type" "neon_add_widen")
+ (set_attr "length" "8")]
+)
+
(define_insn "widen_ssum3"
[(set (match_operand: 0 "s_register_operand" "=w")
(plus: (sign_extend:
@@ -1184,6 +1235,57 @@
[(set_attr "type" "neon_add_widen")]
)
+(define_expand "widen_usum3"
+ [(set (match_operand: 0 "s_register_operand" "")
+(plus: (zero_extend:
(match_operand:VQI 1 "s_register_operand" ""))
+ (match_operand: 2
"s_register_operand" "")))]
+ "TARGET_NEON"
+ {
+int i;
+int half_elem = /2;
+rtvec v1 = rtvec_alloc (half_elem);
+rtvec v2 = rtvec_alloc (half_elem);
+rtx p1, p2;
+
+for (i = 0; i < half_elem; i++)
+ RTVEC_ELT (v1, i) = GEN_INT (i);
+p1 = gen_rtx_PARALLEL (GET_MODE (operands[1]), v1);
+
+for (i = half_elem; i < ; i++)
+ RTVEC_ELT (v2, i - half_elem) = GEN_INT (i);
+p2 = gen_rtx_PARALLEL (GET_MODE (operands[1]), v2);
+
+if (operands[0] != operands[2])
+ emit_move_insn (operands[0], operands[2]);
+
+emit_insn (gen_vec_sel_widen_usum_lo3 (operands[0],
operands[1], p1, operands[0]));
+emit_insn (gen_vec_sel_widen_usum_hi3 (operands[0],
operands[1], p2, operands[0]));
+DONE;
+ }
+)
+
+(define_insn "vec_sel_widen_usum_lo3"
+ [(set (match_operand: 0 "s_register_operand" "=w")
+(plus: (zero_extend: (vec_select:VW
(match_operand:VQI 1 "s_register_operand" "%w")
+
Re: [C/C++ PATCH] Fix -Wshift-overflow with sign bit
OK. Jason
