[Bug rtl-optimization/49452] [4.7 regression] comp-goto-2.c regresses in testing

2011-09-19 Thread carrot at gcc dot gnu.org 
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49452

--- Comment #25 from carrot at gcc dot gnu.org 2011-09-20 00:57:44 UTC ---
Author: carrot
Date: Tue Sep 20 00:57:39 2011
New Revision: 178995

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=178995
Log:
PR rtl-optimization/49452
* postreload.c (reload_combine): Invalidate use information when across
volatile insn.


Modified:
trunk/gcc/ChangeLog
trunk/gcc/postreload.c

[Bug target/53447] missed optimization of 64bit ALU operation with small constant

2012-07-01 Thread carrot at gcc dot gnu.org 
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53447

--- Comment #3 from carrot at gcc dot gnu.org 2012-07-01 15:14:56 UTC ---
Author: carrot
Date: Sun Jul  1 15:14:52 2012
New Revision: 189102

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=189102
Log:
PR target/53447
* config/arm/arm-protos.h (const_ok_for_dimode_op): New prototype.
* config/arm/arm.c (const_ok_for_dimode_op): New function.
* config/arm/constraints.md (Dd): New constraint.
* config/arm/predicates.md (arm_adddi_operand): New predicate.
* config/arm/arm.md (adddi3): Extend it to handle constants.
(arm_adddi3): Likewise.
(addsi3_carryin_): Extend it to handle sbc case.
(addsi3_carryin_alt2_): Likewise.
* config/arm/neon.md (adddi3_neon): Extend it to handle constants.

* gcc.target/arm/pr53447-1.c: New testcase.
* gcc.target/arm/pr53447-2.c: New testcase.
* gcc.target/arm/pr53447-3.c: New testcase.
* gcc.target/arm/pr53447-4.c: New testcase.


Added:
trunk/gcc/testsuite/gcc.target/arm/pr53447-1.c
trunk/gcc/testsuite/gcc.target/arm/pr53447-2.c
trunk/gcc/testsuite/gcc.target/arm/pr53447-3.c
trunk/gcc/testsuite/gcc.target/arm/pr53447-4.c
Modified:
trunk/gcc/ChangeLog
trunk/gcc/config/arm/arm-protos.h
trunk/gcc/config/arm/arm.c
trunk/gcc/config/arm/arm.md
trunk/gcc/config/arm/constraints.md
trunk/gcc/config/arm/neon.md
trunk/gcc/config/arm/predicates.md
trunk/gcc/testsuite/ChangeLog

[Bug target/61202] gcc generates invalid sqdmulh instruction

2014-05-21 Thread carrot at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61202

--- Comment #4 from carrot at gcc dot gnu.org ---
Author: carrot
Date: Wed May 21 20:46:46 2014
New Revision: 210728

URL: http://gcc.gnu.org/viewcvs?rev=210728&root=gcc&view=rev
Log:
PR target/61202
* config/aarch64/arm_neon.h (vqdmulh_n_s16): Change the last operand's
constraint.
(vqdmulhq_n_s16): Likewise.

Modified:
branches/gcc-4_9-branch/gcc/ChangeLog
branches/gcc-4_9-branch/gcc/config/aarch64/arm_neon.h

[Bug tree-optimization/63530] GCC generates incorrect aligned store on ARM after the loop is unrolled.

2014-10-22 Thread carrot at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63530

--- Comment #4 from carrot at gcc dot gnu.org ---
Author: carrot
Date: Wed Oct 22 15:56:59 2014
New Revision: 216562

URL: https://gcc.gnu.org/viewcvs?rev=216562&root=gcc&view=rev
Log:
PR tree-optimization/63530
tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref): Set
pointer alignment according to DR_MISALIGNMENT.
gcc.dg/vect/pr63530.c: New testcase.


Added:
trunk/gcc/testsuite/gcc.dg/vect/pr63530.c
Modified:
trunk/gcc/ChangeLog
trunk/gcc/testsuite/ChangeLog
trunk/gcc/tree-vect-data-refs.c

[Bug tree-optimization/63530] GCC generates incorrect aligned store on ARM after the loop is unrolled.

2014-10-27 Thread carrot at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63530

--- Comment #5 from carrot at gcc dot gnu.org ---
Author: carrot
Date: Tue Oct 28 00:20:13 2014
New Revision: 216770

URL: https://gcc.gnu.org/viewcvs?rev=216770&root=gcc&view=rev
Log:
PR tree-optimization/63530
tree-vect-data-refs.c (vect_create_addr_base_for_vector_ref): Set
pointer alignment according to DR_MISALIGNMENT.
gcc.dg/vect/pr63530.c: New test.


Added:
branches/gcc-4_9-branch/gcc/testsuite/gcc.dg/vect/pr63530.c
Modified:
branches/gcc-4_9-branch/gcc/ChangeLog
branches/gcc-4_9-branch/gcc/testsuite/ChangeLog
branches/gcc-4_9-branch/gcc/tree-vect-data-refs.c

[Bug target/62262] aarch64 gcc generates invalid assembler

2014-08-27 Thread carrot at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62262

--- Comment #9 from amker at gcc dot gnu.org ---
(In reply to Andrew Pinski from comment #6)
> (In reply to Carrot from comment #5)
> > Actually the original source code is guarded by assert, and the parameter
> > passed to CLZ can be guaranteed not 0, so "value <<= zeros" is well defined
> > in our original source code.
> 
> The issue is the second CLZ (not the first one).  Though if I read the code
> correctly value<<1 can never be zero but GCC does not optimize away that
> check.

How is that?  Both "value >> bias" and "value << 1" are zero if value == 1 at
the entry, am I misunderstanding?

--- Comment #10 from carrot at gcc dot gnu.org ---
Author: carrot
Date: Wed Aug 27 16:48:09 2014
New Revision: 214578

URL: https://gcc.gnu.org/viewcvs?rev=214578&root=gcc&view=rev
Log:
PR target/62262
* config/aarch64/aarch64.md (*andim_ashift_bfiz): Check the shift
amount before using it.

* gcc.target/aarch64/pr62262.c: New test.


Added:
trunk/gcc/testsuite/gcc.target/aarch64/pr62262.c
Modified:
trunk/gcc/ChangeLog
trunk/gcc/config/aarch64/aarch64.md
trunk/gcc/testsuite/ChangeLog

[Bug target/62262] aarch64 gcc generates invalid assembler

2014-08-27 Thread carrot at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62262

--- Comment #11 from carrot at gcc dot gnu.org ---
Author: carrot
Date: Wed Aug 27 23:00:54 2014
New Revision: 214610

URL: https://gcc.gnu.org/viewcvs?rev=214610&root=gcc&view=rev
Log:
PR target/62262
* config/aarch64/aarch64.md (*andim_ashift_bfiz): Check the shift
amount before using it.

* gcc.target/aarch64/pr62262.c: New test.


Added:
branches/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/pr62262.c
Modified:
branches/gcc-4_9-branch/gcc/ChangeLog
branches/gcc-4_9-branch/gcc/config/aarch64/aarch64.md
branches/gcc-4_9-branch/gcc/testsuite/ChangeLog

[Bug target/62040] internal compiler error: in simplify_const_unary_operation, at simplify-rtx.c:1555

2014-09-04 Thread carrot at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62040

--- Comment #8 from carrot at gcc dot gnu.org ---
Author: carrot
Date: Thu Sep  4 16:06:13 2014
New Revision: 214905

URL: https://gcc.gnu.org/viewcvs?rev=214905&root=gcc&view=rev
Log:
PR target/62040
* config/aarch64/iterators.md (VQ_NO2E, VQ_2E): New iterators.
* config/aarch64/aarch64-simd.md (move_lo_quad_internal_): Split
it into two patterns.
(move_lo_quad_internal_be_): Likewise.

* gcc.target/aarch64/pr62040.c: New test.


Added:
trunk/gcc/testsuite/gcc.target/aarch64/pr62040.c
Modified:
trunk/gcc/ChangeLog
trunk/gcc/config/aarch64/aarch64-simd.md
trunk/gcc/config/aarch64/iterators.md
trunk/gcc/testsuite/ChangeLog

[Bug target/62040] internal compiler error: in simplify_const_unary_operation, at simplify-rtx.c:1555

2014-09-04 Thread carrot at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62040

--- Comment #9 from carrot at gcc dot gnu.org ---
Author: carrot
Date: Thu Sep  4 17:34:12 2014
New Revision: 214913

URL: https://gcc.gnu.org/viewcvs?rev=214913&root=gcc&view=rev
Log:
PR target/62040
* config/aarch64/iterators.md (VQ_NO2E, VQ_2E): New iterators.
* config/aarch64/aarch64-simd.md (move_lo_quad_internal_): Split
it into two patterns.
(move_lo_quad_internal_be_): Likewise.

* gcc.target/aarch64/pr62040.c: New test.


Added:
branches/gcc-4_9-branch/gcc/testsuite/gcc.target/aarch64/pr62040.c
Modified:
branches/gcc-4_9-branch/gcc/ChangeLog
branches/gcc-4_9-branch/gcc/config/aarch64/aarch64-simd.md
branches/gcc-4_9-branch/gcc/config/aarch64/iterators.md
branches/gcc-4_9-branch/gcc/testsuite/ChangeLog

[Bug rtl-optimization/49799] gcc arm generates illegal sbfx instruction

2011-07-28 Thread carrot at gcc dot gnu.org 
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49799

--- Comment #9 from carrot at gcc dot gnu.org 2011-07-29 01:27:32 UTC ---
Author: carrot
Date: Fri Jul 29 01:27:29 2011
New Revision: 176911

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=176911
Log:
PR rtl-optimization/49799

* combine.c (make_compound_operation): Check if the bit field is valid
before change it to bit field extraction.

* gcc.dg/pr49799.c: New test case.


Added:
trunk/gcc/testsuite/gcc.dg/pr49799.c
Modified:
trunk/gcc/ChangeLog
trunk/gcc/combine.c
trunk/gcc/testsuite/ChangeLog

[Bug rtl-optimization/49799] gcc arm generates illegal sbfx instruction

2011-07-29 Thread carrot at gcc dot gnu.org 
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49799

--- Comment #10 from carrot at gcc dot gnu.org 2011-07-29 08:36:11 UTC ---
Author: carrot
Date: Fri Jul 29 08:35:59 2011
New Revision: 176917

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=176917
Log:
PR rtl-optimization/49799

* combine.c (make_compound_operation): Check if the bit field is valid
before change it to bit field extraction.

* gcc.dg/pr49799.c: New test case.


Added:
branches/gcc-4_6-branch/gcc/testsuite/gcc.dg/pr49799.c
  - copied unchanged from r176911, trunk/gcc/testsuite/gcc.dg/pr49799.c
Modified:
branches/gcc-4_6-branch/   (props changed)
branches/gcc-4_6-branch/gcc/ChangeLog
branches/gcc-4_6-branch/gcc/combine.c
branches/gcc-4_6-branch/gcc/testsuite/ChangeLog

Propchange: branches/gcc-4_6-branch/
('svn:mergeinfo' modified)