Reload Pass
Hi All, Does anyone know of any document describing (in details) the reload phase of GCC? I am planning to write a linear scan reload for GCC (one that does not take reg_renumber but takes instruction specific register allocation and move information). Can anyone point me to some existing code/literature for this in GCC? regards, Raj
Re: Reload Pass
Hi, Thanks very much. I still have doubts on your suggestion: AFAIK, the back-end pass consists of (in order) : reg move -> insn sched -> reg class -> local alloc -> global alloc -> reload -> post-reload. There are edges from reg move to reg class and reload back to global alloc. In case I want to implement a linear scan which may split live ranges (pseudos) into live intervals(smaller pseudos) and allocate different registers for each of them. This process would break the whole loop. So, what did you mean by --- "run this pass in between the register allocator and reload, that would probably be doable."? regards, Raj Ian Lance Taylor <[EMAIL PROTECTED]> wrote on 12/21/2006 09:02:04 PM: > Rajkishore Barik <[EMAIL PROTECTED]> writes: > > > Does anyone know of any document describing (in details) the reload phase > > of GCC? > > There isn't one. The closest such document is > http://gcc.gnu.org/wiki/reload > which is accurate despite, or perhaps because of, starting out by > equating reload with Satan. > > > I am planning to write a linear scan reload for GCC (one that does not > > take reg_renumber > > but takes instruction specific register allocation and move information). > > Can anyone point me > > to some existing code/literature for this in GCC? > > There is none. > > If you expect this pass to actually replace reload, then I advise you > to reconsider. That would be a hopeless task. Well, maybe you could > do it if you restrict yourself to a single architecture. > > If you want to run this pass in between the register allocator and > reload, that would probably be doable. Of course, reload will then > muck up your decisions, and the resulting code will sometimes be worse > than what you get today. But it might be an interesting experiment. > > Ian
Spill cost
Hi, Does anyone know how to obtain the overall spill cost for the old reg alloc of GCC (global.c)? I would like to know the spill cost before reload and after the reload (assuming reload changes the allocation). Are there any interface already available? By spill cost I mean: for each reg i, if it is spilled, spill_cost+=REG_N_REFS(i)*REG_FREQ(i); regards, Raj
Error help
Checked out a version of new-regalloc code and patched some of my code. It crashes in the bootstrapping part where "xgcc" runs some of my code on __dtor* modules. Is there a way to avoid this bootstrapping? I do not really care about these errors.
coverage mismatch
Hi, I have been trying to use "-fprofile-generate" and "-fprofile-use" for some small bitwise C benchmarks (developed at MIT). I have a check-out of October 2004 GCC build of 4.0 version. It throws me "coverage mismatch error for "arcs"" saying number of counters is "6" instead of "5". How do I go around fixing these problems? In fact, 8 out of 15 of these benchmarks throw me the same problem. Most of these benchmarks have only one module "main.c". I compile the following way "gcc -O2 -fprofile-generate main.c" "gcc -O2 -fprofile-use main.c" -- here it throws error. Thanks for your help, regards, Raj
combine.c
Can someone tell me why are the "REG_VALUE_PROFILE" notes dropped in "combine.c"? I am using these notes to carry some values to back-end (reg-alloc) and it seems to get lost somewhere. "combine.c" looked to me as the potential place. --Raj
GCC errors
Hi, I am trying to compile MEDIABENCH (@UCLA) using the latest GCC CVS checkout. I get the following errors when I compile with "-O3 -fprofile-generate". I just want to make sure that this is not a silly mistake before I file a bug report. Can someone help? Almost 9 out of 11 benchmarks throw error. Two errors are reported below. For benchmark(epic) * gcc -static -fprofile-generate -O3 -c build_pyr.c build_pyr.c: In function âbuild_levelâ: build_pyr.c:94: error: Abnormal edges for no purpose in bb 162 build_pyr.c:94: internal compiler error: verify_flow_info failed Please submit a full bug report, with preprocessed source if appropriate. See http://gcc.gnu.org/bugs.html> for instructions. make: *** [build_pyr.o] Error 1 For benchmark (g721) * gcc -static -fprofile-generate -o encode encode.c g711.o g72x.o g721.o g723_24.o g723_40.o encode.c: In function âmainâ: encode.c:98: warning: incompatible implicit declaration of built-in function âexitâ encode.c:99: warning: incompatible implicit declaration of built-in function âstrcpyâ encode.c:100: warning: incompatible implicit declaration of built-in function âstrcatâ encode.c:132: error: unrecognizable insn: (insn 738 159 739 74 (set (reg:SI 242) (reg:SI 19 dirflag)) -1 (nil) (nil)) encode.c:132: internal compiler error: in extract_insn, at recog.c:2042 Please submit a full bug report, with preprocessed source if appropriate. See http://gcc.gnu.org/bugs.html> for instructions. make: *** [encode] Error 1 --Raj
RTL code
Can someone tell me if there is a way to generate RTL code which does not include use and def of the same pseudo in the same insn? Of course, I can break every such instruction into two but I am wondering if it is already there or anyone has the code already available. i.e. generate t=p56+p76; p56=t; instead of p56=p56+p76; --R
spill_failure
Hi,
I have been adding some profiling stuff onto the RTL. I get the following
error in reload phase. Can someone tell me how to fix this? I use 8th
April 2005
check out from CVS.
./mul_mdmd_md.c: In function âmul_mdmd_md_l1_arb_allâ:
./mul_mdmd_md.c:343: error: unable to find a register to spill in class
âAD_REGSâ
./mul_mdmd_md.c:343: error: this is the insn:
(insn 529 8 530 0 (parallel [
(set (reg:DI 232)
(sign_extend:DI (reg/v:SI 149 [ M ])))
(clobber (reg:CC 17 flags))
(clobber (scratch:SI))
]) 82 {*extendsidi2_1} (nil)
(expr_list:REG_UNUSED (scratch:SI)
(expr_list:REG_UNUSED (reg:CC 17 flags)
(nil
./mul_mdmd_md.c:343: internal compiler error: in spill_failure, at
reload1.c:1885
regards,
Raj
Re: spill_failure
> Hmm, let me rephrase your question:
> "I did some GCC hacking that I'm not showing, and it doesn't work,
> please help me fix it."
This is not what I meant. I meant if similar problem has been reported by
anyone else before. In any case. This is the piece of code that I add
after every integer "set" instruction returned from "single_set()" module.
// "insn" being the current integer set instruction
// "value" being the "destination" of the set instruction
// GCOV_COUNTER_V_RANGE is a new Value Range Counter added by me
enum machine_mode mode = mode_for_size (GCOV_TYPE_SIZE, MODE_INT, 0);
start_sequence ();
rtx stored_val_ref = rtl_coverage_counter_ref(GCOV_COUNTER_V_RANGE,
0);
rtx stored_val = validize_mem (stored_val_ref);
rtx uval = gen_reg_rtx (mode);
convert_move (uval, copy_rtx (value), 0);
rtx tmp=expand_simple_binop(mode, IOR,copy_rtx(uval),
copy_rtx(stored_val),stored_val,0, OPTAB_WIDEN);
sequence = get_insns ();
end_sequence ();
emit_insn_after(sequence,insn);
Note that I these pieces of code just before register allocation and code
scheduling are done.
> > ./mul_mdmd_md.c: In function âmul_mdmd_md_l1_arb_allâ:
> > ./mul_mdmd_md.c:343: error: unable to find a register to spill in
class
> > âAD_REGSâ
> > ./mul_mdmd_md.c:343: error: this is the insn:
> > (insn 529 8 530 0 (parallel [
> > (set (reg:DI 232)
> > (sign_extend:DI (reg/v:SI 149 [ M ])))
> > (clobber (reg:CC 17 flags))
> > (clobber (scratch:SI))
> > ]) 82 {*extendsidi2_1} (nil)
> > (expr_list:REG_UNUSED (scratch:SI)
> > (expr_list:REG_UNUSED (reg:CC 17 flags)
> > (nil
> > ./mul_mdmd_md.c:343: internal compiler error: in spill_failure, at
> > reload1.c:1885
> What this basically says is that after register allocation some insns
> do not have all their operand constraints satisfied, so reload needs
> to fix up something, but it cannot use the registers it needs.
The same piece of code works fine for me for the whole lot of benchmarks
without having any problem. Its a few which cause this AD_REG spill
problem.
I am wondering why is this happening.
--R
Induction Variable
Hi, Can someone tell me how to obtain the following: 1) Given a rtx, find out if it is an induction variable. 2) For an induction variable, find all the loop nest 3) For each loopnest, find the corresponding upper and lower bounds (compile-time) 4) For an induction variables, find the increment/decrement value I tried using the "iv_analysis_init(loop)", "iv_analyze()" and "iv_iv_analysis_done()". However, since I am calling these functions later in the stage (just before register allocation), they give me ICE. Any clue? Aliasing: 5) Given two mem-rtx "a" and "b" find if they alias to each other. Assume that "a" and "b" represent programmer defined arrays which are never assigned directly. I looked at the code of alias.c, but the interfaces are not clear to me as to how they should be used to get what I want. regards, Raj
-fprofile-arcs
Hi, I am trying to profile the frequency of each basic block of SPEC 2000 benchmarks by compiling them using -fprofile-arcs and opt -O3. After running the benchmark, when I try to read "bb->count" while compiling using "-fbranch-probabilities and -O3", I get "0" values for basic blocks which were known to execute for sure. Any clue as to where I am missing? Is "bb->count" is the right way to get the dynamic frequency in the second pass? regards, Raj
Re: -fprofile-arcs
Hi,
Thanks a lot. Basically, I want to obtain dynamic basic block frequency at
RTL
level just before register allocation. Look at the following piece of
code(a.c):
void foo(int i, int *a, int *p) {
int x1,j;
for(j=0;j<200;j++) {
x1=a[i]+j;
*p=99;
a[i]=x1;
}
}
main() {
int *a,*p,i=0;
int x1,x2,x3,x4;
a=malloc(sizeof(int));
p=malloc(sizeof(int));
a[0]=0;
foo(0,a,p);
printf("\n%d ",*p);
for(i=0;i<1;i++) {
printf(" %d ",a[i]);
}
}
This code was executed using "gcc -O3 -fprofile-arcs --param
max-unroll-times=0 a.c".
"a.out" was then executed (for profiling).
Now I compile using "gcc -O3 -fbranch-probabilities --param
max-unroll-times=0 a.c".
During this phase, I try to obtain dynamic frequencies of the statements
within the "for"
loop in "foo" method at RTL level. The frequencies return "0" using
"bb->count". I
would like this to reflect "200". How to obtain this information?
regards,
Raj
Jan Hubicka <[EMAIL PROTECTED]>
07/18/2005 10:29 AM
To
Rajkishore Barik/India/[EMAIL PROTECTED]
cc
gcc@gcc.gnu.org
Subject
Re: -fprofile-arcs
> Hi,
>
> I am trying to profile the frequency of each basic block of
> SPEC 2000 benchmarks by compiling them using -fprofile-arcs and opt -O3.
> After running the benchmark, when I try to read "bb->count" while
> compiling
> using "-fbranch-probabilities and -O3", I get "0" values for basic
blocks
> which were known to execute for sure. Any clue as to where I am missing?
> Is "bb->count" is the right way to get the dynamic frequency in the
second
> pass?
It is. You would need to provide more information for me to figure out
what is going wrong. Of course the bb->count is initialized only after
profile is read in that at current mainline is pretty late in
compilation queue (after bp RTL pass), but this is going to change
hopefully at monday.
Honza
>
> regards,
> Raj
SPECINT 2000 176.gcc compilation
Hi, I am trying to compile SPECINT 2000 176.gcc benchmark using GCC 4.1 April 24th build on Redhat Linux/i386. I get the following error while compiling "reorg.c": reorg.c: In function âfind_end_labelâ: reorg.c:831: error: invalid lvalue in increment reorg.c: In function âdelete_from_delay_slotâ: reorg.c:1033: error: invalid lvalue in increment reorg.c: In function âmake_return_insnsâ: reorg.c:4157: error: invalid lvalue in increment reorg.c: In function âdbr_scheduleâ: reorg.c:4237: error: invalid lvalue in increment reorg.c:4312: warning: incompatible implicit declaration of built-in function âmemsetâ make: *** [reorg.o] Error 1 Can someone tell me the right set of flags for compiling 176.gcc? I am using "-DUSG -O3" TIA, --R
Loop information
Can someone please help me getting the following information? 1) I would like to obtain the loop bounds (constant case) of all nested loops of a RTL insn. Is there a data structure over which I can iterate to get bounds for each nested loop of a RTL insn? 2) Is there a way of determining sequences as mentioned in the paper "Beyond Induction Variables: Detecting and Classifying Sequences Using a Demand-Driven SSA From" by Gerlek, Stoltz and Wolfe? 3) Can I determine if a pseudo register (RTX) is an induction variable (linear) or not? Which data structure gives me this information? 4) At RTL level, array accesses convert to MEM expressions. I was wondering if I can obtain the source level array name from the MEM expression. If it does not exist already, can I annotate the MEM rtl with the array name while the RTL is being generated? I am performing an analysis at RTL level which needs to know the array that I am accessing and treats them independently. Which module would I have to modify to handle this case? --R
reload problem in GCC 4.1
Hi,
I was trying to feed the "reload" phase with a different hardware
register assignment to pseudo registers (using reg_renumber array)
than the ones produced by local-alloc or global-alloc. However, I get
problems with the following instruction in post-reload.c:391 in
"reload_cse_simplify_operands" function stating that the "insn does
not satisfy constraint".
Can someone please help me if the following instruction has any
specific constraint requirement during register allocation phase?
(insn:HI 100 99 102 8 (parallel [
(set (reg:SI 108)
(div:SI (reg:SI 75 [ prephitmp.6 ])
(reg:SI 74 [ prephitmp.8 ])))
(set (reg:SI 109)
(mod:SI (reg:SI 75 [ prephitmp.6 ])
(reg:SI 74 [ prephitmp.8 ])))
(clobber (reg:CC 17 flags))
]) 196 {*divmodsi4_cltd} (insn_list:REG_DEP_TRUE 99 (nil))
(expr_list:REG_UNUSED (reg:CC 17 flags)
(expr_list:REG_UNUSED (reg:SI 109)
(expr_list:REG_DEAD (reg:SI 74 [ prephitmp.8 ])
(expr_list:REG_DEAD (reg:SI 75 [ prephitmp.6 ])
(expr_list:REG_UNUSED (reg:CC 17 flags)
(expr_list:REG_UNUSED (reg:SI 109)
(nil
regards,
~R
Re: reload problem in GCC 4.1
The architecture for which I generate code is Intel x86.
On 3/6/06, Rajkishore Barik <[EMAIL PROTECTED]> wrote:
> Hi,
>
> I was trying to feed the "reload" phase with a different hardware
> register assignment to pseudo registers (using reg_renumber array)
> than the ones produced by local-alloc or global-alloc. However, I get
> problems with the following instruction in post-reload.c:391 in
> "reload_cse_simplify_operands" function stating that the "insn does
> not satisfy constraint".
> Can someone please help me if the following instruction has any
> specific constraint requirement during register allocation phase?
>
> (insn:HI 100 99 102 8 (parallel [
> (set (reg:SI 108)
> (div:SI (reg:SI 75 [ prephitmp.6 ])
> (reg:SI 74 [ prephitmp.8 ])))
> (set (reg:SI 109)
> (mod:SI (reg:SI 75 [ prephitmp.6 ])
> (reg:SI 74 [ prephitmp.8 ])))
> (clobber (reg:CC 17 flags))
> ]) 196 {*divmodsi4_cltd} (insn_list:REG_DEP_TRUE 99 (nil))
> (expr_list:REG_UNUSED (reg:CC 17 flags)
> (expr_list:REG_UNUSED (reg:SI 109)
> (expr_list:REG_DEAD (reg:SI 74 [ prephitmp.8 ])
> (expr_list:REG_DEAD (reg:SI 75 [ prephitmp.6 ])
> (expr_list:REG_UNUSED (reg:CC 17 flags)
> (expr_list:REG_UNUSED (reg:SI 109)
> (nil
>
> regards,
> ~R
>
GCC 4.1 on AIX 5.3 POWER 5
Hi All, I am trying to complie GCC 4.1 on an AIX 5.3 machine having 2 power5 processors. I get the following error while trying to compile. Can someone help? "cc" is IBM's xlC compiler. cc -c -g-DHAVE_CONFIG_H -I. -I../../gcc-4.1-20060310/fixincludes -I../include -I../../gcc-4.1-20060310/fixincludes/../include ../../gcc-4.1-20060310/fixincludes/fixincl.c cc -c -g-DHAVE_CONFIG_H -I. -I../../gcc-4.1-20060310/fixincludes -I../include -I../../gcc-4.1-20060310/fixincludes/../include ../../gcc-4.1-20060310/fixincludes/fixtests.c cc -c -g-DHAVE_CONFIG_H -I. -I../../gcc-4.1-20060310/fixincludes -I../include -I../../gcc-4.1-20060310/fixincludes/../include ../../gcc-4.1-20060310/fixincludes/fixfixes.c cc -c -g-DHAVE_CONFIG_H -I. -I../../gcc-4.1-20060310/fixincludes -I../include -I../../gcc-4.1-20060310/fixincludes/../include ../../gcc-4.1-20060310/fixincludes/server.c cc -c -g-DHAVE_CONFIG_H -I. -I../../gcc-4.1-20060310/fixincludes -I../include -I../../gcc-4.1-20060310/fixincludes/../include ../../gcc-4.1-20060310/fixincludes/procopen.c cc -c -g-DHAVE_CONFIG_H -I. -I../../gcc-4.1-20060310/fixincludes -I../include -I../../gcc-4.1-20060310/fixincludes/../include ../../gcc-4.1-20060310/fixincludes/fixlib.c cc -c -g-DHAVE_CONFIG_H -I. -I../../gcc-4.1-20060310/fixincludes -I../include -I../../gcc-4.1-20060310/fixincludes/../include ../../gcc-4.1-20060310/fixincludes/fixopts.c cc -g -o fixincl fixincl.o fixtests.o fixfixes.o server.o procopen.o fixlib.o fixopts.o ../libiberty/libiberty.a echo timestamp > full-stamp srcdir="../../gcc-4.1-20060310/fixincludes" /bin/sh ../../gcc-4.1-20060310/fixincludes/mkfixinc.sh powerpc-ibm-aix5.3.0.0 sed -e 's/@gcc_version@//' < > mkheadersT /bin/sh: 0403-057 Syntax error at line 1 : `>' is not expected. make: 1254-004 The error code from the last command is 2. Stop. make: 1254-004 The error code from the last command is 2. Stop. make: 1254-004 The error code from the last command is 2 regards, Raj
replace_rtx
Hi, I am doing some modification to gcc's RTL code. I am trying to split a pseudo (old) into two pseudos (old and new) and rewriting some part of the code to replace the "old" pseudo by the "new" pseudo. I am using the "replace_rtx" function to perform the replacement. However I get "fatal error: internal consistency failure" when I try to execute any program. The specific call that I make is: replace_rtx (insn, old_rtx, new_rtx); I notice that "replace_rtx" actually performs the replacement when I try to print the "insn" before and after the call. However, later on I get the error "internal consistency failure". I would like to know what are the cases in which this error is thrown. Is there any document which I can refer to? regards, Raj
Quick Question
Hi, Is there a way to determine if the given RTX is accessing an array element or not? If yes, how do I determine the static size of that array from the given RTX? Thanks a lot in advance. regards, Raj
