[Freedreno] [v1] drm/msm/dpu: consider vertical front porch in the prefill bw calculation

[Kalyan Thota]

In case of panels with low vertical back porch, the prefill bw
requirement will be high as we will have less time(vbp+pw) to
fetch and fill the hw latency buffers before start of first line
in active period.

For ex:
Say hw_latency_line_buffers = 24, and if blanking vbp+pw = 10
Here we need to fetch 24 lines of data in 10 line times.
This will increase the bw to the ratio of linebuffers to blanking.

DPU hw can also fetch data during vertical front porch provided
interface prefetch is enabled. Use vfp in the prefill calculation
as dpu driver enables prefetch if the blanking is not sufficient
to fill the latency lines.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 7ea90d2..315b999 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -151,7 +151,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane,
u64 plane_bw;
u32 hw_latency_lines;
u64 scale_factor;
-   int vbp, vpw;
+   int vbp, vpw, vfp;
 
pstate = to_dpu_plane_state(plane->state);
mode = &plane->state->crtc->mode;
@@ -164,6 +164,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane,
fps = drm_mode_vrefresh(mode);
vbp = mode->vtotal - mode->vsync_end;
vpw = mode->vsync_end - mode->vsync_start;
+   vfp = mode->vsync_start - mode->vdisplay;
hw_latency_lines =  dpu_kms->catalog->perf.min_prefill_lines;
scale_factor = src_height > dst_height ?
mult_frac(src_height, 1, dst_height) : 1;
@@ -176,7 +177,13 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane,
src_width * hw_latency_lines * fps * fmt->bpp *
scale_factor * mode->vtotal;
 
-   do_div(plane_prefill_bw, (vbp+vpw));
+   if ((vbp+vpw) > hw_latency_lines)
+   do_div(plane_prefill_bw, (vbp+vpw));
+   else if ((vbp+vpw+vfp) < hw_latency_lines)
+   do_div(plane_prefill_bw, (vbp+vpw+vfp));
+   else
+   do_div(plane_prefill_bw, hw_latency_lines);
+
 
pstate->plane_fetch_bw = max(plane_bw, plane_prefill_bw);
 }
-- 
2.7.4

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[Freedreno] [v1] drm/msm/disp/dpu1: turn off vblank irqs aggressively in dpu driver

[Kalyan Thota]

Turn off vblank irqs immediately as soon as drm_vblank_put is
requested so that there are no irqs triggered during idle state.

This will reduce cpu wakeups and help in power saving. The change
also enable driver timestamp for vblanks.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 69 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 15 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h |  6 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  4 ++
 4 files changed, 94 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index d4662e8..a4a5733 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -65,6 +65,73 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
kfree(dpu_crtc);
 }
 
+static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)
+{
+   struct drm_device *dev = crtc->dev;
+   struct drm_encoder *encoder;
+
+   drm_for_each_encoder(encoder, dev)
+   if (encoder->crtc == crtc)
+   return encoder;
+
+   return NULL;
+}
+
+static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc,
+  bool in_vblank_irq,
+  int *vpos, int *hpos,
+  ktime_t *stime, ktime_t *etime,
+  const struct drm_display_mode *mode)
+{
+   unsigned int pipe = crtc->index;
+   struct drm_encoder *encoder;
+   int line, vsw, vbp, vactive_start, vactive_end, vfp_end;
+
+
+   encoder = get_encoder_from_crtc(crtc);
+   if (!encoder) {
+   DRM_ERROR("no encoder found for crtc %d\n", pipe);
+   return false;
+   }
+
+   vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
+   vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
+
+   /*
+* the line counter is 1 at the start of the VSYNC pulse and VTOTAL at
+* the end of VFP. Translate the porch values relative to the line
+* counter positions.
+*/
+
+   vactive_start = vsw + vbp + 1;
+
+   vactive_end = vactive_start + mode->crtc_vdisplay;
+
+   /* last scan line before VSYNC */
+   vfp_end = mode->crtc_vtotal;
+
+   if (stime)
+   *stime = ktime_get();
+
+   line = dpu_encoder_get_linecount(encoder);
+
+   if (line < vactive_start)
+   line -= vactive_start;
+   else if (line > vactive_end)
+   line = line - vfp_end - vactive_start;
+   else
+   line -= vactive_start;
+
+   *vpos = line;
+   *hpos = 0;
+
+   if (etime)
+   *etime = ktime_get();
+
+   return true;
+}
+
+
 static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
struct dpu_plane_state *pstate, struct dpu_format *format)
 {
@@ -1243,6 +1310,7 @@ static const struct drm_crtc_funcs dpu_crtc_funcs = {
.early_unregister = dpu_crtc_early_unregister,
.enable_vblank  = msm_crtc_enable_vblank,
.disable_vblank = msm_crtc_disable_vblank,
+   .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
 };
 
 static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = {
@@ -1251,6 +1319,7 @@ static const struct drm_crtc_helper_funcs 
dpu_crtc_helper_funcs = {
.atomic_check = dpu_crtc_atomic_check,
.atomic_begin = dpu_crtc_atomic_begin,
.atomic_flush = dpu_crtc_atomic_flush,
+   .get_scanout_position = dpu_crtc_get_scanout_position,
 };
 
 /* initialize crtc */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index f7f5c25..6c7c7fd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -425,6 +425,21 @@ int dpu_encoder_helper_unregister_irq(struct 
dpu_encoder_phys *phys_enc,
return 0;
 }
 
+int dpu_encoder_get_linecount(struct drm_encoder *drm_enc)
+{
+   struct dpu_encoder_virt *dpu_enc = NULL;
+   struct dpu_encoder_phys *phys = NULL;
+   int linecount = 0;
+
+   dpu_enc = to_dpu_encoder_virt(drm_enc);
+   phys = dpu_enc ? dpu_enc->cur_master : NULL;
+
+   if (phys && phys->ops.get_line_count)
+   linecount = phys->ops.get_line_count(phys);
+
+   return linecount;
+}
+
 void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc,
  struct dpu_encoder_hw_resources *hw_res)
 {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index b491346..2c4804c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -156,5 +156,11 @@ void dpu_encoder_prepare_commit(struct drm_encoder 
*drm_enc)

[Freedreno] [v2] drm/msm/disp/dpu1: turn off vblank irqs aggressively in dpu driver

[Kalyan Thota]

Set the flag vblank_disable_immediate = true to turn off vblank irqs
immediately as soon as drm_vblank_put is requested so that there are
no irqs triggered during idle state. This will reduce cpu wakeups
and help in power saving.

To enable vblank_disable_immediate flag the underlying KMS driver
needs to support high precision vblank timestamping and also a
reliable way of providing vblank counter which is incrementing
at the leading edge of vblank.

This patch also brings in changes to support vblank_disable_immediate
requirement in dpu driver.

Changes in v1:
 - Specify reason to add vblank timestamp support. (Rob)
 - Add changes to provide vblank counter from dpu driver.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   | 80 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 30 
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h| 11 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |  1 +
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 17 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  5 ++
 6 files changed, 144 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index d4662e8..9a80981 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -65,6 +65,83 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
kfree(dpu_crtc);
 }
 
+static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)
+{
+   struct drm_device *dev = crtc->dev;
+   struct drm_encoder *encoder;
+
+   drm_for_each_encoder(encoder, dev)
+   if (encoder->crtc == crtc)
+   return encoder;
+
+   return NULL;
+}
+
+static u32 dpu_crtc_get_vblank_counter(struct drm_crtc *crtc)
+{
+   struct drm_encoder *encoder;
+
+   encoder = get_encoder_from_crtc(crtc);
+   if (!encoder) {
+   DRM_ERROR("no encoder found for crtc %d\n", crtc->index);
+   return false;
+   }
+
+   return dpu_encoder_get_frame_count(encoder);
+}
+
+static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc,
+  bool in_vblank_irq,
+  int *vpos, int *hpos,
+  ktime_t *stime, ktime_t *etime,
+  const struct drm_display_mode *mode)
+{
+   unsigned int pipe = crtc->index;
+   struct drm_encoder *encoder;
+   int line, vsw, vbp, vactive_start, vactive_end, vfp_end;
+
+   encoder = get_encoder_from_crtc(crtc);
+   if (!encoder) {
+   DRM_ERROR("no encoder found for crtc %d\n", pipe);
+   return false;
+   }
+
+   vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
+   vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
+
+   /*
+* the line counter is 1 at the start of the VSYNC pulse and VTOTAL at
+* the end of VFP. Translate the porch values relative to the line
+* counter positions.
+*/
+
+   vactive_start = vsw + vbp + 1;
+   vactive_end = vactive_start + mode->crtc_vdisplay;
+
+   /* last scan line before VSYNC */
+   vfp_end = mode->crtc_vtotal;
+
+   if (stime)
+   *stime = ktime_get();
+
+   line = dpu_encoder_get_linecount(encoder);
+
+   if (line < vactive_start)
+   line -= vactive_start;
+   else if (line > vactive_end)
+   line = line - vfp_end - vactive_start;
+   else
+   line -= vactive_start;
+
+   *vpos = line;
+   *hpos = 0;
+
+   if (etime)
+   *etime = ktime_get();
+
+   return true;
+}
+
 static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
struct dpu_plane_state *pstate, struct dpu_format *format)
 {
@@ -1243,6 +1320,8 @@ static const struct drm_crtc_funcs dpu_crtc_funcs = {
.early_unregister = dpu_crtc_early_unregister,
.enable_vblank  = msm_crtc_enable_vblank,
.disable_vblank = msm_crtc_disable_vblank,
+   .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
+   .get_vblank_counter = dpu_crtc_get_vblank_counter,
 };
 
 static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = {
@@ -1251,6 +1330,7 @@ static const struct drm_crtc_helper_funcs 
dpu_crtc_helper_funcs = {
.atomic_check = dpu_crtc_atomic_check,
.atomic_begin = dpu_crtc_atomic_begin,
.atomic_flush = dpu_crtc_atomic_flush,
+   .get_scanout_position = dpu_crtc_get_scanout_position,
 };
 
 /* initialize crtc */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index f7f5c25..5cd3f31 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -425,6

[Freedreno] [v3] drm/msm/disp/dpu1: turn off vblank irqs aggressively in dpu

[Kalyan Thota]

From: Kalyan Thota 

Set the flag vblank_disable_immediate = true to turn off vblank irqs
immediately as soon as drm_vblank_put is requested so that there are
no irqs triggered during idle state. This will reduce cpu wakeups
and help in power saving.

To enable vblank_disable_immediate flag the underlying KMS driver
needs to support high precision vblank timestamping and also a
reliable way of providing vblank counter which is incrementing
at the leading edge of vblank.

This patch also brings in changes to support vblank_disable_immediate
requirement in dpu driver.

Changes in v1:
 - Specify reason to add vblank timestamp support. (Rob Clark)
 - Add changes to provide vblank counter from dpu driver.

Changes in v2:
 - Fix warn stack reported by Rob Clark with v2 patch

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 80 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 28 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 11 
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  5 ++
 4 files changed, 123 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index d4662e8..9a80981 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -65,6 +65,83 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
kfree(dpu_crtc);
 }
 
+static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)
+{
+   struct drm_device *dev = crtc->dev;
+   struct drm_encoder *encoder;
+
+   drm_for_each_encoder(encoder, dev)
+   if (encoder->crtc == crtc)
+   return encoder;
+
+   return NULL;
+}
+
+static u32 dpu_crtc_get_vblank_counter(struct drm_crtc *crtc)
+{
+   struct drm_encoder *encoder;
+
+   encoder = get_encoder_from_crtc(crtc);
+   if (!encoder) {
+   DRM_ERROR("no encoder found for crtc %d\n", crtc->index);
+   return false;
+   }
+
+   return dpu_encoder_get_frame_count(encoder);
+}
+
+static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc,
+  bool in_vblank_irq,
+  int *vpos, int *hpos,
+  ktime_t *stime, ktime_t *etime,
+  const struct drm_display_mode *mode)
+{
+   unsigned int pipe = crtc->index;
+   struct drm_encoder *encoder;
+   int line, vsw, vbp, vactive_start, vactive_end, vfp_end;
+
+   encoder = get_encoder_from_crtc(crtc);
+   if (!encoder) {
+   DRM_ERROR("no encoder found for crtc %d\n", pipe);
+   return false;
+   }
+
+   vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
+   vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
+
+   /*
+* the line counter is 1 at the start of the VSYNC pulse and VTOTAL at
+* the end of VFP. Translate the porch values relative to the line
+* counter positions.
+*/
+
+   vactive_start = vsw + vbp + 1;
+   vactive_end = vactive_start + mode->crtc_vdisplay;
+
+   /* last scan line before VSYNC */
+   vfp_end = mode->crtc_vtotal;
+
+   if (stime)
+   *stime = ktime_get();
+
+   line = dpu_encoder_get_linecount(encoder);
+
+   if (line < vactive_start)
+   line -= vactive_start;
+   else if (line > vactive_end)
+   line = line - vfp_end - vactive_start;
+   else
+   line -= vactive_start;
+
+   *vpos = line;
+   *hpos = 0;
+
+   if (etime)
+   *etime = ktime_get();
+
+   return true;
+}
+
 static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
struct dpu_plane_state *pstate, struct dpu_format *format)
 {
@@ -1243,6 +1320,8 @@ static const struct drm_crtc_funcs dpu_crtc_funcs = {
.early_unregister = dpu_crtc_early_unregister,
.enable_vblank  = msm_crtc_enable_vblank,
.disable_vblank = msm_crtc_disable_vblank,
+   .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
+   .get_vblank_counter = dpu_crtc_get_vblank_counter,
 };
 
 static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = {
@@ -1251,6 +1330,7 @@ static const struct drm_crtc_helper_funcs 
dpu_crtc_helper_funcs = {
.atomic_check = dpu_crtc_atomic_check,
.atomic_begin = dpu_crtc_atomic_begin,
.atomic_flush = dpu_crtc_atomic_flush,
+   .get_scanout_position = dpu_crtc_get_scanout_position,
 };
 
 /* initialize crtc */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index f7f5c25..fb6546c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -425,6 +425,32 @@ int dpu_encoder_

[Freedreno] [v3] drm/msm/disp/dpu1: turn off vblank irqs aggressively in dpu

[Kalyan Thota]

Set the flag vblank_disable_immediate = true to turn off vblank irqs
immediately as soon as drm_vblank_put is requested so that there are
no irqs triggered during idle state. This will reduce cpu wakeups
and help in power saving.

To enable vblank_disable_immediate flag the underlying KMS driver
needs to support high precision vblank timestamping and also a
reliable way of providing vblank counter which is incrementing
at the leading edge of vblank.

This patch also brings in changes to support vblank_disable_immediate
requirement in dpu driver.

Changes in v1:
 - Specify reason to add vblank timestamp support. (Rob)
 - Add changes to provide vblank counter from dpu driver.

Changes in v2:
 - fix warn stack reported by Rob with v2 patch

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 80 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 28 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 11 
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  5 ++
 4 files changed, 123 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index d4662e8..9a80981 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -65,6 +65,83 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
kfree(dpu_crtc);
 }
 
+static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)
+{
+   struct drm_device *dev = crtc->dev;
+   struct drm_encoder *encoder;
+
+   drm_for_each_encoder(encoder, dev)
+   if (encoder->crtc == crtc)
+   return encoder;
+
+   return NULL;
+}
+
+static u32 dpu_crtc_get_vblank_counter(struct drm_crtc *crtc)
+{
+   struct drm_encoder *encoder;
+
+   encoder = get_encoder_from_crtc(crtc);
+   if (!encoder) {
+   DRM_ERROR("no encoder found for crtc %d\n", crtc->index);
+   return false;
+   }
+
+   return dpu_encoder_get_frame_count(encoder);
+}
+
+static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc,
+  bool in_vblank_irq,
+  int *vpos, int *hpos,
+  ktime_t *stime, ktime_t *etime,
+  const struct drm_display_mode *mode)
+{
+   unsigned int pipe = crtc->index;
+   struct drm_encoder *encoder;
+   int line, vsw, vbp, vactive_start, vactive_end, vfp_end;
+
+   encoder = get_encoder_from_crtc(crtc);
+   if (!encoder) {
+   DRM_ERROR("no encoder found for crtc %d\n", pipe);
+   return false;
+   }
+
+   vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
+   vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
+
+   /*
+* the line counter is 1 at the start of the VSYNC pulse and VTOTAL at
+* the end of VFP. Translate the porch values relative to the line
+* counter positions.
+*/
+
+   vactive_start = vsw + vbp + 1;
+   vactive_end = vactive_start + mode->crtc_vdisplay;
+
+   /* last scan line before VSYNC */
+   vfp_end = mode->crtc_vtotal;
+
+   if (stime)
+   *stime = ktime_get();
+
+   line = dpu_encoder_get_linecount(encoder);
+
+   if (line < vactive_start)
+   line -= vactive_start;
+   else if (line > vactive_end)
+   line = line - vfp_end - vactive_start;
+   else
+   line -= vactive_start;
+
+   *vpos = line;
+   *hpos = 0;
+
+   if (etime)
+   *etime = ktime_get();
+
+   return true;
+}
+
 static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
struct dpu_plane_state *pstate, struct dpu_format *format)
 {
@@ -1243,6 +1320,8 @@ static const struct drm_crtc_funcs dpu_crtc_funcs = {
.early_unregister = dpu_crtc_early_unregister,
.enable_vblank  = msm_crtc_enable_vblank,
.disable_vblank = msm_crtc_disable_vblank,
+   .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
+   .get_vblank_counter = dpu_crtc_get_vblank_counter,
 };
 
 static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = {
@@ -1251,6 +1330,7 @@ static const struct drm_crtc_helper_funcs 
dpu_crtc_helper_funcs = {
.atomic_check = dpu_crtc_atomic_check,
.atomic_begin = dpu_crtc_atomic_begin,
.atomic_flush = dpu_crtc_atomic_flush,
+   .get_scanout_position = dpu_crtc_get_scanout_position,
 };
 
 /* initialize crtc */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index f7f5c25..fb6546c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -425,6 +425,32 @@ int dpu_encoder_helper_unregister_irq(struct 

[Freedreno] [v4] drm/msm/disp/dpu1: turn off vblank irqs aggressively in dpu driver

[Kalyan Thota]

Set the flag vblank_disable_immediate = true to turn off vblank irqs
immediately as soon as drm_vblank_put is requested so that there are
no irqs triggered during idle state. This will reduce cpu wakeups
and help in power saving.

To enable vblank_disable_immediate flag the underlying KMS driver
needs to support high precision vblank timestamping and also a
reliable way of providing vblank counter which is incrementing
at the leading edge of vblank.

This patch also brings in changes to support vblank_disable_immediate
requirement in dpu driver.

Changes in v1:
 - Specify reason to add vblank timestamp support. (Rob).
 - Add changes to provide vblank counter from dpu driver.

Changes in v2:
 - Fix warn stack reported by Rob Clark with v2 patch.

Changes in v3:
 - Move back to HW frame counter (Rob).

 Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   | 80 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 30 
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h| 11 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |  1 +
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 26 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c|  1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h|  1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  5 ++
 8 files changed, 155 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index d4662e8..9a80981 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -65,6 +65,83 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
kfree(dpu_crtc);
 }
 
+static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)
+{
+   struct drm_device *dev = crtc->dev;
+   struct drm_encoder *encoder;
+
+   drm_for_each_encoder(encoder, dev)
+   if (encoder->crtc == crtc)
+   return encoder;
+
+   return NULL;
+}
+
+static u32 dpu_crtc_get_vblank_counter(struct drm_crtc *crtc)
+{
+   struct drm_encoder *encoder;
+
+   encoder = get_encoder_from_crtc(crtc);
+   if (!encoder) {
+   DRM_ERROR("no encoder found for crtc %d\n", crtc->index);
+   return false;
+   }
+
+   return dpu_encoder_get_frame_count(encoder);
+}
+
+static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc,
+  bool in_vblank_irq,
+  int *vpos, int *hpos,
+  ktime_t *stime, ktime_t *etime,
+  const struct drm_display_mode *mode)
+{
+   unsigned int pipe = crtc->index;
+   struct drm_encoder *encoder;
+   int line, vsw, vbp, vactive_start, vactive_end, vfp_end;
+
+   encoder = get_encoder_from_crtc(crtc);
+   if (!encoder) {
+   DRM_ERROR("no encoder found for crtc %d\n", pipe);
+   return false;
+   }
+
+   vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
+   vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
+
+   /*
+* the line counter is 1 at the start of the VSYNC pulse and VTOTAL at
+* the end of VFP. Translate the porch values relative to the line
+* counter positions.
+*/
+
+   vactive_start = vsw + vbp + 1;
+   vactive_end = vactive_start + mode->crtc_vdisplay;
+
+   /* last scan line before VSYNC */
+   vfp_end = mode->crtc_vtotal;
+
+   if (stime)
+   *stime = ktime_get();
+
+   line = dpu_encoder_get_linecount(encoder);
+
+   if (line < vactive_start)
+   line -= vactive_start;
+   else if (line > vactive_end)
+   line = line - vfp_end - vactive_start;
+   else
+   line -= vactive_start;
+
+   *vpos = line;
+   *hpos = 0;
+
+   if (etime)
+   *etime = ktime_get();
+
+   return true;
+}
+
 static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
struct dpu_plane_state *pstate, struct dpu_format *format)
 {
@@ -1243,6 +1320,8 @@ static const struct drm_crtc_funcs dpu_crtc_funcs = {
.early_unregister = dpu_crtc_early_unregister,
.enable_vblank  = msm_crtc_enable_vblank,
.disable_vblank = msm_crtc_disable_vblank,
+   .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
+   .get_vblank_counter = dpu_crtc_get_vblank_counter,
 };
 
 static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = {
@@ -1251,6 +1330,7 @@ static const struct drm_crtc_helper_funcs 
dpu_crtc_helper_funcs = {
.atomic_check = dpu_crtc_atomic_check,
.atomic_begin = dpu_crtc_atomic_begin,
.atomic_flush = dpu_crtc_atomic_flush,
+   .get_scanout_position = dpu_crtc_get_scanout_position,
 };
 
 /* initialize crtc */
dif

[Freedreno] [v1] drm/msm/disp/dpu1: fix warning reported by kernel bot in dpu driver

[Kalyan Thota]

Fix a warning, pointing to an early deference of a variable before
check. This bug was introduced in the following commit.

commit 4259ff7ae509
("drm/msm/dpu: add support for pcc color block in dpu driver")

Reported-by: kernel test robot 
Reported-by: Dan Carpenter 
Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
index a7a2453..0f9974c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
@@ -26,10 +26,16 @@ static void dpu_setup_dspp_pcc(struct dpu_hw_dspp *ctx,
struct dpu_hw_pcc_cfg *cfg)
 {
 
-   u32 base = ctx->cap->sblk->pcc.base;
+   u32 base;
 
-   if (!ctx || !base) {
-   DRM_ERROR("invalid ctx %pK pcc base 0x%x\n", ctx, base);
+   if (!ctx) {
+   DRM_ERROR("invalid dspp ctx %pK\n", ctx);
+   return;
+   }
+
+   base = ctx->cap->sblk->pcc.base;
+   if (!base) {
+   DRM_ERROR("invalid pcc base 0x%x\n", base);
return;
}
 
-- 
2.7.4

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[Freedreno] [v1] drm/msm/disp/dpu1: fix display underruns during modeset.

[Kalyan Thota]

During crtc disable, display perf structures are reset to 0
which includes state varibles which are immutable. On crtc
enable, we use the same structures and they don't refelect
the actual values

1) Fix is to avoid updating the state structures during disable.
2) Reset the perf structures during atomic check when there is no
modeset enable.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 1 +
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 37c8270..b4cd479 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -382,7 +382,6 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
} else {
DPU_DEBUG("crtc=%d disable\n", crtc->base.id);
memset(old, 0, sizeof(*old));
-   memset(new, 0, sizeof(*new));
update_bus = true;
update_clk = true;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 9a80981..a821e2c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -912,6 +912,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
if (!state->enable || !state->active) {
DPU_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n",
crtc->base.id, state->enable, state->active);
+   memset(&cstate->new_perf, 0, sizeof(cstate->new_perf));
goto end;
}
 
-- 
2.7.4

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[Freedreno] [v1] drm/msm/disp/dpu1: icc path needs to be set before dpu runtime resume

[Kalyan Thota]

From: Kalyan Thota 

DPU runtime resume will request for a min vote on the AXI bus as
it is a necessary step before turning ON the AXI clock.

The change does below
1) Move the icc path set before requesting runtime get_sync.
2) remove the dependency of hw catalog for min ib vote
as it is initialized at a later point.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index ed636f1..cab387f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -44,6 +44,8 @@
 #define DPU_DEBUGFS_DIR "msm_dpu"
 #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask"
 
+#define MIN_IB_BW  4ULL /* Min ib vote 400MB */
+
 static int dpu_kms_hw_init(struct msm_kms *kms);
 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms);
 
@@ -932,6 +934,9 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
DPU_DEBUG("REG_DMA is not defined");
}
 
+   if (of_device_is_compatible(dev->dev->of_node, "qcom,sc7180-mdss"))
+   dpu_kms_parse_data_bus_icc_path(dpu_kms);
+
pm_runtime_get_sync(&dpu_kms->pdev->dev);
 
dpu_kms->core_rev = readl_relaxed(dpu_kms->mmio + 0x0);
@@ -1037,9 +1042,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
 
dpu_vbif_init_memtypes(dpu_kms);
 
-   if (of_device_is_compatible(dev->dev->of_node, "qcom,sc7180-mdss"))
-   dpu_kms_parse_data_bus_icc_path(dpu_kms);
-
pm_runtime_put_sync(&dpu_kms->pdev->dev);
 
return 0;
@@ -1196,10 +1198,10 @@ static int __maybe_unused dpu_runtime_resume(struct 
device *dev)
 
ddev = dpu_kms->dev;
 
+   WARN_ON(!(dpu_kms->num_paths));
/* Min vote of BW is required before turning on AXI clk */
for (i = 0; i < dpu_kms->num_paths; i++)
-   icc_set_bw(dpu_kms->path[i], 0,
-   dpu_kms->catalog->perf.min_dram_ib);
+   icc_set_bw(dpu_kms->path[i], 0, Bps_to_icc(MIN_IB_BW));
 
rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
if (rc) {
-- 
2.7.4

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[Freedreno] [v1] drm/msm/disp/dpu1: fix warn stack reported during dpu resume

[Kalyan Thota]

WARN_ON was introduced by the below commit to catch runtime resumes
that are getting triggered before icc path was set.

"drm/msm/disp/dpu1: icc path needs to be set before dpu runtime resume"

For the targets where the bw scaling is not enabled, this WARN_ON is
a false alarm. Fix the WARN condition appropriately.

Reported-by: Steev Klimaszewski 
Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c  |  8 +---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h  |  9 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 11 ++-
 3 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index cab387f..0071a4d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -294,6 +294,9 @@ static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms 
*dpu_kms)
struct icc_path *path1;
struct drm_device *dev = dpu_kms->dev;
 
+   if (!dpu_supports_bw_scaling(dev))
+   return 0;
+
path0 = of_icc_get(dev->dev, "mdp0-mem");
path1 = of_icc_get(dev->dev, "mdp1-mem");
 
@@ -934,8 +937,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
DPU_DEBUG("REG_DMA is not defined");
}
 
-   if (of_device_is_compatible(dev->dev->of_node, "qcom,sc7180-mdss"))
-   dpu_kms_parse_data_bus_icc_path(dpu_kms);
+   dpu_kms_parse_data_bus_icc_path(dpu_kms);
 
pm_runtime_get_sync(&dpu_kms->pdev->dev);
 
@@ -1198,7 +1200,7 @@ static int __maybe_unused dpu_runtime_resume(struct 
device *dev)
 
ddev = dpu_kms->dev;
 
-   WARN_ON(!(dpu_kms->num_paths));
+   WARN_ON((dpu_supports_bw_scaling(ddev) && !dpu_kms->num_paths));
/* Min vote of BW is required before turning on AXI clk */
for (i = 0; i < dpu_kms->num_paths; i++)
icc_set_bw(dpu_kms->path[i], 0, Bps_to_icc(MIN_IB_BW));
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index d6717d6..f7bcc0a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -154,6 +154,15 @@ struct vsync_info {
 
 #define to_dpu_global_state(x) container_of(x, struct dpu_global_state, base)
 
+/**
+ * dpu_supports_bw_scaling: returns true for drivers that support bw scaling.
+ * @dev: Pointer to drm_device structure
+ */
+static inline int dpu_supports_bw_scaling(struct drm_device *dev)
+{
+   return of_device_is_compatible(dev->dev->of_node, "qcom,sc7180-mdss");
+}
+
 /* Global private object state for tracking resources that are shared across
  * multiple kms objects (planes/crtcs/etc).
  */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
index cd40788..8cd712c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
@@ -41,6 +41,9 @@ static int dpu_mdss_parse_data_bus_icc_path(struct drm_device 
*dev,
struct icc_path *path0 = of_icc_get(dev->dev, "mdp0-mem");
struct icc_path *path1 = of_icc_get(dev->dev, "mdp1-mem");
 
+   if (dpu_supports_bw_scaling(dev))
+   return 0;
+
if (IS_ERR_OR_NULL(path0))
return PTR_ERR_OR_ZERO(path0);
 
@@ -276,11 +279,9 @@ int dpu_mdss_init(struct drm_device *dev)
 
DRM_DEBUG("mapped mdss address space @%pK\n", dpu_mdss->mmio);
 
-   if (!of_device_is_compatible(dev->dev->of_node, "qcom,sc7180-mdss")) {
-   ret = dpu_mdss_parse_data_bus_icc_path(dev, dpu_mdss);
-   if (ret)
-   return ret;
-   }
+   ret = dpu_mdss_parse_data_bus_icc_path(dev, dpu_mdss);
+   if (ret)
+   return ret;
 
mp = &dpu_mdss->mp;
ret = msm_dss_parse_clock(pdev, mp);
-- 
2.7.4

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[Freedreno] [v1] drm/msm/disp/dpu1: program 3d_merge only if block is attached

[Kalyan Thota]

Update the 3d merge as active in the data path only if
the hw block is selected in the configuration.

Reported-by: Stephen Boyd 
Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 8981cfa..92e6f1b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -496,7 +496,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
 
DPU_REG_WRITE(c, CTL_TOP, mode_sel);
DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
-   DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, BIT(cfg->merge_3d - MERGE_3D_0));
+   if (cfg->merge_3d)
+   DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
+ BIT(cfg->merge_3d - MERGE_3D_0));
 }
 
 static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
-- 
2.7.4

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[Freedreno] [RFC] drm/msm/disp/dpu1: add support for inline rotation in dpu driver

[Kalyan Thota]

Add inline rotation support in dpu driver. This change adds
rotation config for SC7280 target.

Change-Id: I15861dc03422274ffd823fc0fc2c1e47909bb22c
Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 47 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 20 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c  | 93 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h  |  2 +
 4 files changed, 128 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index d01c4c9..45e4e56 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -25,6 +25,9 @@
 #define VIG_SM8250_MASK \
(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
 
+#define VIG_SC7280_MASK \
+   (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
+
 #define DMA_SDM845_MASK \
(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
@@ -102,6 +105,8 @@
 #define MAX_DOWNSCALE_RATIO4
 #define SSPP_UNITY_SCALE   1
 
+#define INLINE_ROTATOR_V2  2
+
 #define STRCAT(X, Y) (X Y)
 
 static const uint32_t plane_formats[] = {
@@ -177,6 +182,11 @@ static const uint32_t plane_formats_yuv[] = {
DRM_FORMAT_YVU420,
 };
 
+static const uint32_t rotation_formats[] = {
+   DRM_FORMAT_NV12,
+   /* TODO add formats after validation */
+};
+
 /*
  * DPU sub blocks config
  */
@@ -465,7 +475,16 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
 
 /* SSPP common configuration */
 
-#define _VIG_SBLK(num, sdma_pri, qseed_ver) \
+static const struct dpu_rotation_cfg dpu_rot_cfg = {
+   .version = INLINE_ROTATOR_V2,
+   .rot_maxdwnscale_ratio_num = 1,
+   .rot_maxdwnscale_ratio_dem = 1,
+   .rot_maxheight = 1088,
+   .rot_num_formats = ARRAY_SIZE(rotation_formats),
+   .rot_format_list = rotation_formats,
+};
+
+#define _VIG_SBLK(num, sdma_pri, qseed_ver, rot_cfg) \
{ \
.maxdwnscale = MAX_DOWNSCALE_RATIO, \
.maxupscale = MAX_UPSCALE_RATIO, \
@@ -482,6 +501,7 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
.num_formats = ARRAY_SIZE(plane_formats_yuv), \
.virt_format_list = plane_formats, \
.virt_num_formats = ARRAY_SIZE(plane_formats), \
+   .rotation_cfg = rot_cfg, \
}
 
 #define _DMA_SBLK(num, sdma_pri) \
@@ -498,13 +518,13 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
}
 
 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =
-   _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3);
+   _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3, 0);
 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
-   _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3);
+   _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3, 0);
 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 =
-   _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3);
+   _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3, 0);
 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 =
-   _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3);
+   _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3, 0);
 
 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1);
 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
@@ -543,7 +563,10 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
 };
 
 static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
-   _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4);
+   _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4, 0);
+
+static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
+   _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4, 
&dpu_rot_cfg);
 
 static const struct dpu_sspp_cfg sc7180_sspp[] = {
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
@@ -557,13 +580,13 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
 };
 
 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
-   _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
+   _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE, 
0);
 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
-   _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE);
+   _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE, 
0);
 s

[Freedreno] [RFC] Inline rotation support in dpu driver

[Kalyan Thota]

This change adds support for inline rotation in the dpu driver.
When inline rotation is enabled the VIG pipes will directly fetch the image
from memory in a rotated fashion

Inline rotation has following restrictions 
1) Supported only with compressed formats
2) max pre rotated height is 1088
3) restrictions with downscaling ratio

Queries: 

1) Since inline rotation works for fewer pixel formats with specific modifier, 
how can we provide this information to the compositor so that
chrome compositor can choose between overlaying or falling back to GPU. In the 
patch it fails in the atomic check.

2) If a display composition fails in atomic check due to any of the 
restrictions in overlays
can chrome compositor switch it back to the GPU and re trigger the commit ?

posting it as RFC as validation is not complete, please share early comments on 
this.

Kalyan Thota (1):
  drm/msm/disp/dpu1: add support for inline rotation in dpu driver

 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 47 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 20 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c  | 93 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h  |  2 +
 4 files changed, 128 insertions(+), 34 deletions(-)

-- 
2.7.4

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[Freedreno] [v1] drm/msm/disp/dpu1: add safe lut config in dpu driver

[Kalyan Thota]

Add safe lut configuration for all the targets in dpu
driver as per QOS recommendation.

Issue reported on SC7280:

With wait-for-safe feature in smmu enabled, RT client
buffer levels are checked to be safe before smmu invalidation.
Since display was always set to unsafe it was delaying the
invalidaiton process thus impacting the performance on NRT clients
such as eMMC and NVMe.

Validated this change on SC7280, With this change eMMC performance
has improved significantly.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index d01c4c9..2e482cd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -974,6 +974,7 @@ static const struct dpu_perf_cfg sdm845_perf_data = {
.amortizable_threshold = 25,
.min_prefill_lines = 24,
.danger_lut_tbl = {0xf, 0x, 0x0},
+   .safe_lut_tbl = {0xfff0, 0xf000, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sdm845_qos_linear),
.entries = sdm845_qos_linear
@@ -1001,6 +1002,7 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
.min_dram_ib = 160,
.min_prefill_lines = 24,
.danger_lut_tbl = {0xff, 0x, 0x0},
+   .safe_lut_tbl = {0xfff0, 0xff00, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sc7180_qos_linear),
.entries = sc7180_qos_linear
@@ -1028,6 +1030,7 @@ static const struct dpu_perf_cfg sm8150_perf_data = {
.min_dram_ib = 80,
.min_prefill_lines = 24,
.danger_lut_tbl = {0xf, 0x, 0x0},
+   .safe_lut_tbl = {0xfff8, 0xf000, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sm8150_qos_linear),
.entries = sm8150_qos_linear
@@ -1056,6 +1059,7 @@ static const struct dpu_perf_cfg sm8250_perf_data = {
.min_dram_ib = 80,
.min_prefill_lines = 35,
.danger_lut_tbl = {0xf, 0x, 0x0},
+   .safe_lut_tbl = {0xfff0, 0xff00, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sc7180_qos_linear),
.entries = sc7180_qos_linear
@@ -1084,6 +1088,7 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
.min_dram_ib = 160,
.min_prefill_lines = 24,
.danger_lut_tbl = {0x, 0x, 0x0},
+   .safe_lut_tbl = {0xff00, 0xff00, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
.entries = sc7180_qos_macrotile
-- 
2.7.4

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[Freedreno] [v2] drm/msm/disp/dpu1: add safe lut config in dpu driver

[Kalyan Thota]

Add safe lut configuration for all the targets in dpu
driver as per QOS recommendation.

Issue reported on SC7280:

With wait-for-safe feature in smmu enabled, RT client
buffer levels are checked to be safe before smmu invalidation.
Since display was always set to unsafe it was delaying the
invalidaiton process thus impacting the performance on NRT clients
such as eMMC and NVMe.

Validated this change on SC7280, With this change eMMC performance
has improved significantly.

Changes in v1:
- Add fixes tag (Sai)
- CC stable kernel (Dimtry)

Fixes: cfacf946a464d4(drm/msm/disp/dpu1: add support for display for SC7280 
target)
Signed-off-by: Kalyan Thota 
Tested-by: Sai Prakash Ranjan  (sc7280, 
sc7180)
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index d01c4c9..2e482cd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -974,6 +974,7 @@ static const struct dpu_perf_cfg sdm845_perf_data = {
.amortizable_threshold = 25,
.min_prefill_lines = 24,
.danger_lut_tbl = {0xf, 0x, 0x0},
+   .safe_lut_tbl = {0xfff0, 0xf000, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sdm845_qos_linear),
.entries = sdm845_qos_linear
@@ -1001,6 +1002,7 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
.min_dram_ib = 160,
.min_prefill_lines = 24,
.danger_lut_tbl = {0xff, 0x, 0x0},
+   .safe_lut_tbl = {0xfff0, 0xff00, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sc7180_qos_linear),
.entries = sc7180_qos_linear
@@ -1028,6 +1030,7 @@ static const struct dpu_perf_cfg sm8150_perf_data = {
.min_dram_ib = 80,
.min_prefill_lines = 24,
.danger_lut_tbl = {0xf, 0x, 0x0},
+   .safe_lut_tbl = {0xfff8, 0xf000, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sm8150_qos_linear),
.entries = sm8150_qos_linear
@@ -1056,6 +1059,7 @@ static const struct dpu_perf_cfg sm8250_perf_data = {
.min_dram_ib = 80,
.min_prefill_lines = 35,
.danger_lut_tbl = {0xf, 0x, 0x0},
+   .safe_lut_tbl = {0xfff0, 0xff00, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sc7180_qos_linear),
.entries = sc7180_qos_linear
@@ -1084,6 +1088,7 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
.min_dram_ib = 160,
.min_prefill_lines = 24,
.danger_lut_tbl = {0x, 0x, 0x0},
+   .safe_lut_tbl = {0xff00, 0xff00, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
.entries = sc7180_qos_macrotile
-- 
2.7.4

[Freedreno] [v3] drm/msm/disp/dpu1: add safe lut config in dpu driver

[Kalyan Thota]

Add safe lut configuration for all the targets in dpu
driver as per QOS recommendation.

Issue reported on SC7280:

With wait-for-safe feature in smmu enabled, RT client
buffer levels are checked to be safe before smmu invalidation.
Since display was always set to unsafe it was delaying the
invalidaiton process thus impacting the performance on NRT clients
such as eMMC and NVMe.

Validated this change on SC7280, With this change eMMC performance
has improved significantly.

Changes in v1:
- Add fixes tag (Sai)
- CC stable kernel (Dimtry)

Changes in v2:
- Correct fixes tag with appropriate hash (stephen)

Fixes: 591e34a091d1 (drm/msm/disp/dpu1: add support for display
for SC7280 target)
Signed-off-by: Kalyan Thota 
Tested-by: Sai Prakash Ranjan  (sc7280, 
sc7180)
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index d01c4c9..2e482cd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -974,6 +974,7 @@ static const struct dpu_perf_cfg sdm845_perf_data = {
.amortizable_threshold = 25,
.min_prefill_lines = 24,
.danger_lut_tbl = {0xf, 0x, 0x0},
+   .safe_lut_tbl = {0xfff0, 0xf000, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sdm845_qos_linear),
.entries = sdm845_qos_linear
@@ -1001,6 +1002,7 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
.min_dram_ib = 160,
.min_prefill_lines = 24,
.danger_lut_tbl = {0xff, 0x, 0x0},
+   .safe_lut_tbl = {0xfff0, 0xff00, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sc7180_qos_linear),
.entries = sc7180_qos_linear
@@ -1028,6 +1030,7 @@ static const struct dpu_perf_cfg sm8150_perf_data = {
.min_dram_ib = 80,
.min_prefill_lines = 24,
.danger_lut_tbl = {0xf, 0x, 0x0},
+   .safe_lut_tbl = {0xfff8, 0xf000, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sm8150_qos_linear),
.entries = sm8150_qos_linear
@@ -1056,6 +1059,7 @@ static const struct dpu_perf_cfg sm8250_perf_data = {
.min_dram_ib = 80,
.min_prefill_lines = 35,
.danger_lut_tbl = {0xf, 0x, 0x0},
+   .safe_lut_tbl = {0xfff0, 0xff00, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sc7180_qos_linear),
.entries = sc7180_qos_linear
@@ -1084,6 +1088,7 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
.min_dram_ib = 160,
.min_prefill_lines = 24,
.danger_lut_tbl = {0x, 0x, 0x0},
+   .safe_lut_tbl = {0xff00, 0xff00, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
.entries = sc7180_qos_macrotile
-- 
2.7.4

[Freedreno] [Resend v3] drm/msm/disp/dpu1: add safe lut config in dpu driver

[Kalyan Thota]

Add safe lut configuration for all the targets in dpu
driver as per QOS recommendation.

Issue reported on SC7280:

With wait-for-safe feature in smmu enabled, RT client
buffer levels are checked to be safe before smmu invalidation.
Since display was always set to unsafe it was delaying the
invalidaiton process thus impacting the performance on NRT clients
such as eMMC and NVMe.

Validated this change on SC7280, With this change eMMC performance
has improved significantly.

Changes in v2:
- Add fixes tag (Sai)
- CC stable kernel (Dimtry)

Changes in v3:
- Correct fixes tag with appropriate hash (stephen)
- Resend patch adding reviewed by tag

Fixes: 591e34a091d1 ("drm/msm/disp/dpu1: add support for display for SC7280 
target")
Signed-off-by: Kalyan Thota 
Reviewed-by: Dmitry Baryshkov 
Tested-by: Sai Prakash Ranjan  (sc7280, 
sc7180)
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index d01c4c9..2e482cd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -974,6 +974,7 @@ static const struct dpu_perf_cfg sdm845_perf_data = {
.amortizable_threshold = 25,
.min_prefill_lines = 24,
.danger_lut_tbl = {0xf, 0x, 0x0},
+   .safe_lut_tbl = {0xfff0, 0xf000, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sdm845_qos_linear),
.entries = sdm845_qos_linear
@@ -1001,6 +1002,7 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
.min_dram_ib = 160,
.min_prefill_lines = 24,
.danger_lut_tbl = {0xff, 0x, 0x0},
+   .safe_lut_tbl = {0xfff0, 0xff00, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sc7180_qos_linear),
.entries = sc7180_qos_linear
@@ -1028,6 +1030,7 @@ static const struct dpu_perf_cfg sm8150_perf_data = {
.min_dram_ib = 80,
.min_prefill_lines = 24,
.danger_lut_tbl = {0xf, 0x, 0x0},
+   .safe_lut_tbl = {0xfff8, 0xf000, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sm8150_qos_linear),
.entries = sm8150_qos_linear
@@ -1056,6 +1059,7 @@ static const struct dpu_perf_cfg sm8250_perf_data = {
.min_dram_ib = 80,
.min_prefill_lines = 35,
.danger_lut_tbl = {0xf, 0x, 0x0},
+   .safe_lut_tbl = {0xfff0, 0xff00, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sc7180_qos_linear),
.entries = sc7180_qos_linear
@@ -1084,6 +1088,7 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
.min_dram_ib = 160,
.min_prefill_lines = 24,
.danger_lut_tbl = {0x, 0x, 0x0},
+   .safe_lut_tbl = {0xff00, 0xff00, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
.entries = sc7180_qos_macrotile
-- 
2.7.4

[Freedreno] [Resend v3] drm/msm/disp/dpu1: add safe lut config in dpu driver

[Kalyan Thota]

Add safe lut configuration for all the targets in dpu
driver as per QOS recommendation.

Issue reported on SC7280:

With wait-for-safe feature in smmu enabled, RT client
buffer levels are checked to be safe before smmu invalidation.
Since display was always set to unsafe it was delaying the
invalidaiton process thus impacting the performance on NRT clients
such as eMMC and NVMe.

Validated this change on SC7280, With this change eMMC performance
has improved significantly.

Changes in v2:
- Add fixes tag (Sai)
- CC stable kernel (Dimtry)

Changes in v3:
- Correct fixes tag with appropriate hash (stephen)
- Resend patch adding reviewed by tag
- Resend patch adding correct format for pushing into stable tree (Greg)

Fixes: 591e34a091d1 ("drm/msm/disp/dpu1: add support for display for SC7280 
target")
Cc: sta...@vger.kernel.org
Signed-off-by: Kalyan Thota 
Reviewed-by: Dmitry Baryshkov 
Tested-by: Sai Prakash Ranjan  (sc7280, 
sc7180)
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index d01c4c9..2e482cd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -974,6 +974,7 @@ static const struct dpu_perf_cfg sdm845_perf_data = {
.amortizable_threshold = 25,
.min_prefill_lines = 24,
.danger_lut_tbl = {0xf, 0x, 0x0},
+   .safe_lut_tbl = {0xfff0, 0xf000, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sdm845_qos_linear),
.entries = sdm845_qos_linear
@@ -1001,6 +1002,7 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
.min_dram_ib = 160,
.min_prefill_lines = 24,
.danger_lut_tbl = {0xff, 0x, 0x0},
+   .safe_lut_tbl = {0xfff0, 0xff00, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sc7180_qos_linear),
.entries = sc7180_qos_linear
@@ -1028,6 +1030,7 @@ static const struct dpu_perf_cfg sm8150_perf_data = {
.min_dram_ib = 80,
.min_prefill_lines = 24,
.danger_lut_tbl = {0xf, 0x, 0x0},
+   .safe_lut_tbl = {0xfff8, 0xf000, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sm8150_qos_linear),
.entries = sm8150_qos_linear
@@ -1056,6 +1059,7 @@ static const struct dpu_perf_cfg sm8250_perf_data = {
.min_dram_ib = 80,
.min_prefill_lines = 35,
.danger_lut_tbl = {0xf, 0x, 0x0},
+   .safe_lut_tbl = {0xfff0, 0xff00, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sc7180_qos_linear),
.entries = sc7180_qos_linear
@@ -1084,6 +1088,7 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
.min_dram_ib = 160,
.min_prefill_lines = 24,
.danger_lut_tbl = {0x, 0x, 0x0},
+   .safe_lut_tbl = {0xff00, 0xff00, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
.entries = sc7180_qos_macrotile
-- 
2.7.4

[Freedreno] [v1] drm/msm/disp/dpu1: set default group ID for CTL.

[Kalyan Thota]

From: Kalyan Thota 

New required programming in CTL for SC7280. Group ID informs
HW of which VM owns that CTL. Force this group ID to
default/disabled until virtualization support is enabled in SW.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 5 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 +++
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index ce6f32a..283605c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -45,7 +45,7 @@
(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
 
 #define CTL_SC7280_MASK \
-   (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE))
+   (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | 
BIT(DPU_CTL_VM_CFG))
 
 #define MERGE_3D_SM8150_MASK (0)
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 4ade44b..57b9be1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -179,13 +179,16 @@ enum {
 
 /**
  * CTL sub-blocks
- * @DPU_CTL_SPLIT_DISPLAY   CTL supports video mode split display
+ * @DPU_CTL_SPLIT_DISPLAY, CTL supports video mode split display
+ * @DPU_CTL_FETCH_ACTIVE,  Active CTL for fetch HW (SSPPs).
+ * @DPU_CTL_VM_CFG,CTL supports multiple VMs.
  * @DPU_CTL_MAX
  */
 enum {
DPU_CTL_SPLIT_DISPLAY = 0x1,
DPU_CTL_ACTIVE_CFG,
DPU_CTL_FETCH_ACTIVE,
+   DPU_CTL_VM_CFG,
DPU_CTL_MAX
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 64740ddb..455b06a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -498,6 +498,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
u32 intf_active = 0;
u32 mode_sel = 0;
 
+   if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))
+   mode_sel = 0xf000;
+
if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
mode_sel |= BIT(17);
 
-- 
2.7.4

[Freedreno] [v2] drm/msm/disp/dpu1: set default group ID for CTL.

[Kalyan Thota]

New required programming in CTL for SC7280. Group ID informs
HW of which VM owns that CTL. Force this group ID to
default/disabled until virtualization support is enabled in SW.

Changes in v1:
 - Fix documentation and add descritpion for the change (Stephen)

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 5 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 8 
 3 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index ce6f32a..283605c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -45,7 +45,7 @@
(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
 
 #define CTL_SC7280_MASK \
-   (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE))
+   (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | 
BIT(DPU_CTL_VM_CFG))
 
 #define MERGE_3D_SM8150_MASK (0)
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 4ade44b..31af04a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -179,13 +179,16 @@ enum {
 
 /**
  * CTL sub-blocks
- * @DPU_CTL_SPLIT_DISPLAY   CTL supports video mode split display
+ * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
+ * @DPU_CTL_FETCH_ACTIVE:  Active CTL for fetch HW (SSPPs)
+ * @DPU_CTL_VM_CFG:CTL config to support multiple VMs
  * @DPU_CTL_MAX
  */
 enum {
DPU_CTL_SPLIT_DISPLAY = 0x1,
DPU_CTL_ACTIVE_CFG,
DPU_CTL_FETCH_ACTIVE,
+   DPU_CTL_VM_CFG,
DPU_CTL_MAX
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 64740ddb..02da9ec 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -36,6 +36,7 @@
 #define  MERGE_3D_IDX   23
 #define  INTF_IDX   31
 #define CTL_INVALID_BIT 0x
+#define CTL_DEFAULT_GROUP_ID   0xf
 
 static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19,
CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0,
@@ -498,6 +499,13 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
u32 intf_active = 0;
u32 mode_sel = 0;
 
+   /* CTL_TOP[31:28] carries group_id to collate CTL paths
+* per VM. Explicitly disable it until VM support is
+* added in SW. Power on reset value is not disable.
+*/
+   if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))
+   mode_sel = CTL_DEFAULT_GROUP_ID  << 28;
+
if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
mode_sel |= BIT(17);
 
-- 
2.7.4

[Freedreno] [PATCH v1] msm:disp:dpu1: add support for display for SC7180 target

[Kalyan Thota]

Add display hw catalog changes for SC7180 target.

Changes in v1:

1) Configure register offsets and capabilities for the
display hw blocks.

This patch has dependency on the below series

https://patchwork.kernel.org/patch/11243111/

Signed-off-by: Kalyan Thota 
Signed-off-by: Shubhashree Dhar 
Signed-off-by: Raviteja Tamatam 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 189 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   4 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c  |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|   1 +
 drivers/gpu/drm/msm/msm_drv.c  |   4 +-
 5 files changed, 187 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 357e15b..1d2ea93 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -11,11 +11,17 @@
 #include "dpu_hw_catalog_format.h"
 #include "dpu_kms.h"
 
-#define VIG_SDM845_MASK \
-   (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_SCALER_QSEED3) | BIT(DPU_SSPP_QOS) |\
+#define VIG_MASK \
+   (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_QOS_8LVL) |\
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
 
+#define VIG_SDM845_MASK \
+   (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
+
+#define VIG_SC7180_MASK \
+   (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED4))
+
 #define DMA_SDM845_MASK \
(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
@@ -27,6 +33,9 @@
 #define MIXER_SDM845_MASK \
(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
 
+#define MIXER_SC7180_MASK \
+   (BIT(DPU_DIM_LAYER))
+
 #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER)
 
 #define PINGPONG_SDM845_SPLIT_MASK \
@@ -60,6 +69,16 @@
.has_idle_pc = true,
 };
 
+static const struct dpu_caps sc7180_dpu_caps = {
+   .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+   .max_mixer_blendstages = 0x9,
+   .qseed_type = DPU_SSPP_SCALER_QSEED4,
+   .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
+   .ubwc_version = DPU_HW_UBWC_VER_20,
+   .has_dim_layer = true,
+   .has_idle_pc = true,
+};
+
 static struct dpu_mdp_cfg sdm845_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -85,6 +104,23 @@
},
 };
 
+static struct dpu_mdp_cfg sc7180_mdp[] = {
+   {
+   .name = "top_0", .id = MDP_TOP,
+   .base = 0x0, .len = 0x494,
+   .features = 0,
+   .highest_bank_bit = 0x3,
+   .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+   .reg_off = 0x2AC, .bit_off = 0},
+   .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+   .reg_off = 0x2AC, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+   .reg_off = 0x2B4, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+   .reg_off = 0x2BC, .bit_off = 8},
+   },
+};
+
 /*
  * CTL sub blocks config
  */
@@ -116,6 +152,24 @@
},
 };
 
+static struct dpu_ctl_cfg sc7180_ctl[] = {
+   {
+   .name = "ctl_0", .id = CTL_0,
+   .base = 0x1000, .len = 0xE4,
+   .features = BIT(DPU_CTL_ACTIVE_CFG)
+   },
+   {
+   .name = "ctl_1", .id = CTL_1,
+   .base = 0x1200, .len = 0xE4,
+   .features = BIT(DPU_CTL_ACTIVE_CFG)
+   },
+   {
+   .name = "ctl_2", .id = CTL_2,
+   .base = 0x1400, .len = 0xE4,
+   .features = BIT(DPU_CTL_ACTIVE_CFG)
+   },
+};
+
 /*
  * SSPP sub blocks config
  */
@@ -203,9 +257,23 @@
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
 };
 
+static struct dpu_sspp_cfg sc7180_sspp[] = {
+   SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
+   sdm845_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+   SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
+   sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+   SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_SDM845_MASK,
+   sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
+   SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_SDM845_MASK,
+   sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
+};
+
 /*
  * MIXER sub blocks config
  */
+
+/* SDM845 */
+
 static const struct dpu_lm_sub_blks sdm845_lm_sblk = {
.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.maxblendstages = 11, /* 

[Freedreno] [PATCH v1] msm:disp:dpu1: setup display datapath for SC7180 target

[Kalyan Thota]

SC7180 follows a newer architecture where in some flush controls have been 
re-organized to simplify programming and provide for future expandability. 
Specifically:
1) The TIMING_ bits that control flush of INTF_ have been replaced with a 
common INTF flush bit which flushes the programming in the 
MDP_CTL__INTF_ACTIVE register
2) Individual flush bits for MERGE_3D, DSC and CDWN have been added which flush 
the programming in the MDP_CTL__MERGE_3D_ACTIVE, ... etc respectively
3) PERIPH flush bit has been added to flush DSP packets for DisplayPort

The complete datapath is described using the MDP_CTL__TOP and newly added 
ACTIVE registers to handle other sub blocks
such as interface (INTF) resources, PingPong buffer / Layer Mixer, Display 
Stream Compression (DSC) resources, writeback (WB) and 3D Merge 
selections that are part of the datapath.



Kalyan Thota (1):
  msm:disp:dpu1: setup display datapath for SC7180 target

 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  4 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 21 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 84 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 24 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 28 
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h|  6 ++
 7 files changed, 161 insertions(+), 7 deletions(-)

-- 
1.9.1

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Freedreno@lists.freedesktop.org
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[Freedreno] [PATCH v1] msm:disp:dpu1: setup display datapath for SC7180 target

[Kalyan Thota]

Add changes to setup display datapath on SC7180 target

changes in v1:
1) add changes to support ctl_active on SC7180 target
2) while selecting the number of mixers in the topology
consider the interface width.

This patch has dependency on the below series

https://patchwork.kernel.org/patch/11249423/

Signed-off-by: Kalyan Thota 
Signed-off-by: Shubhashree Dhar 
Signed-off-by: Raviteja Tamatam 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  4 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 21 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 84 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 24 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 28 
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h|  6 ++
 7 files changed, 161 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index d82ea99..96c48a8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -58,7 +58,7 @@
 
 #define IDLE_SHORT_TIMEOUT 1
 
-#define MAX_VDISPLAY_SPLIT 1080
+#define MAX_HDISPLAY_SPLIT 1080
 
 /* timeout in frames waiting for frame done */
 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5
@@ -535,7 +535,7 @@ static struct msm_display_topology dpu_encoder_get_topology(
intf_count++;
 
/* User split topology for width > 1080 */
-   topology.num_lm = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
+   topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
topology.num_enc = 0;
topology.num_intf = intf_count;
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index b9c84fb..8cc8ad12 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -280,6 +280,14 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
&timing_params, fmt);
phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
+
+   /* setup which pp blk will connect to this intf */
+   if (phys_enc->hw_intf->ops.bind_pingpong_blk)
+   phys_enc->hw_intf->ops.bind_pingpong_blk(
+   phys_enc->hw_intf,
+   true,
+   phys_enc->hw_pp->idx);
+
spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
 
programmable_fetch_config(phys_enc, &timing_params);
@@ -435,6 +443,7 @@ static void dpu_encoder_phys_vid_enable(struct 
dpu_encoder_phys *phys_enc)
 {
struct dpu_hw_ctl *ctl;
u32 flush_mask = 0;
+   u32 intf_flush_mask = 0;
 
ctl = phys_enc->hw_ctl;
 
@@ -459,10 +468,18 @@ static void dpu_encoder_phys_vid_enable(struct 
dpu_encoder_phys *phys_enc)
ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->hw_intf->idx);
ctl->ops.update_pending_flush(ctl, flush_mask);
 
+   if (ctl->ops.get_bitmask_active_intf)
+   ctl->ops.get_bitmask_active_intf(ctl, &intf_flush_mask,
+   phys_enc->hw_intf->idx);
+
+   if (ctl->ops.update_pending_intf_flush)
+   ctl->ops.update_pending_intf_flush(ctl, intf_flush_mask);
+
 skip_flush:
DPU_DEBUG_VIDENC(phys_enc,
-"update pending flush ctl %d flush_mask %x\n",
-ctl->idx - CTL_0, flush_mask);
+   "update pending flush ctl %d flush_mask 0%x intf_mask 0x%x\n",
+   ctl->idx - CTL_0, flush_mask, intf_flush_mask);
+
 
/* ctl_flush & timing engine enable will be triggered by framework */
if (phys_enc->enable_state == DPU_ENC_DISABLED)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 1d2ea93..1f2ac6e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -374,6 +374,7 @@
{\
.name = _name, .id = _id, \
.base = _base, .len = 0x280, \
+   .features = BIT(DPU_CTL_ACTIVE_CFG), \
.type = _type, \
.controller_id = _ctrl_id, \
.prog_fetch_lines_worst_case = 24 \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 179e8d5..2ce4b5a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -22,11 +22,15 @@
 #define   CTL_PREPARE   0x0d0
 #define   CTL_SW_RESET  0x030
 #define   CTL_LAYER_EXTN_OFFSET 0x40
+#define

[Freedreno] [PATCH v2] msm:disp:dpu1: add support for display for SC7180 target

[Kalyan Thota]

Add display hw catalog changes for SC7180 target.

Changes in v1:
 - Configure register offsets and capabilities for the
   display hw blocks.

Changes in v2:
 - mdss_irq data type has changed in the dependent
   patch, accomodate the necessary changes.
 - Add co-developed-by tags in the commit msg (Stephen Boyd).

This patch has dependency on the below series

https://patchwork.kernel.org/patch/11251761/

Co-developed-by: Shubhashree Dhar 
Signed-off-by: Shubhashree Dhar 
Co-developed-by: Raviteja Tamatam 
Signed-off-by: Raviteja Tamatam 
Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 189 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   4 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c  |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|   1 +
 drivers/gpu/drm/msm/msm_drv.c  |   4 +-
 5 files changed, 187 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 88f2664..1cf4509 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -11,11 +11,17 @@
 #include "dpu_hw_catalog_format.h"
 #include "dpu_kms.h"
 
-#define VIG_SDM845_MASK \
-   (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_SCALER_QSEED3) | BIT(DPU_SSPP_QOS) |\
+#define VIG_MASK \
+   (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_QOS_8LVL) |\
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
 
+#define VIG_SDM845_MASK \
+   (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
+
+#define VIG_SC7180_MASK \
+   (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED4))
+
 #define DMA_SDM845_MASK \
(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
@@ -27,6 +33,9 @@
 #define MIXER_SDM845_MASK \
(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
 
+#define MIXER_SC7180_MASK \
+   (BIT(DPU_DIM_LAYER))
+
 #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER)
 
 #define PINGPONG_SDM845_SPLIT_MASK \
@@ -60,6 +69,16 @@
.has_idle_pc = true,
 };
 
+static const struct dpu_caps sc7180_dpu_caps = {
+   .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+   .max_mixer_blendstages = 0x9,
+   .qseed_type = DPU_SSPP_SCALER_QSEED4,
+   .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
+   .ubwc_version = DPU_HW_UBWC_VER_20,
+   .has_dim_layer = true,
+   .has_idle_pc = true,
+};
+
 static struct dpu_mdp_cfg sdm845_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -85,6 +104,23 @@
},
 };
 
+static struct dpu_mdp_cfg sc7180_mdp[] = {
+   {
+   .name = "top_0", .id = MDP_TOP,
+   .base = 0x0, .len = 0x494,
+   .features = 0,
+   .highest_bank_bit = 0x3,
+   .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+   .reg_off = 0x2AC, .bit_off = 0},
+   .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+   .reg_off = 0x2AC, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+   .reg_off = 0x2B4, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+   .reg_off = 0x2BC, .bit_off = 8},
+   },
+};
+
 /*
  * CTL sub blocks config
  */
@@ -116,6 +152,24 @@
},
 };
 
+static struct dpu_ctl_cfg sc7180_ctl[] = {
+   {
+   .name = "ctl_0", .id = CTL_0,
+   .base = 0x1000, .len = 0xE4,
+   .features = BIT(DPU_CTL_ACTIVE_CFG)
+   },
+   {
+   .name = "ctl_1", .id = CTL_1,
+   .base = 0x1200, .len = 0xE4,
+   .features = BIT(DPU_CTL_ACTIVE_CFG)
+   },
+   {
+   .name = "ctl_2", .id = CTL_2,
+   .base = 0x1400, .len = 0xE4,
+   .features = BIT(DPU_CTL_ACTIVE_CFG)
+   },
+};
+
 /*
  * SSPP sub blocks config
  */
@@ -203,9 +257,23 @@
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
 };
 
+static struct dpu_sspp_cfg sc7180_sspp[] = {
+   SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
+   sdm845_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+   SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
+   sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+   SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_SDM845_MASK,
+   sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
+   SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_SDM845_MASK,
+   sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
+};
+
 /*
  * MIXE

[Freedreno] [PATCH v2] msm:disp:dpu1: setup display datapath for SC7180 target

[Kalyan Thota]

Add changes to setup display datapath on SC7180 target.

Changes in v1:
 - Add changes to support ctl_active on SC7180 target.
 - While selecting the number of mixers in the topology
   consider the interface width.

Changes in v2:
 - Spawn topology mixer selection into seperate patch (Rob Clark).
 - Add co-developed-by tags in the commit msg (Stephen Boyd).

This patch has dependency on the below series

https://patchwork.kernel.org/patch/11253539/

Co-developed-by: Shubhashree Dhar 
Signed-off-by: Shubhashree Dhar 
Co-developed-by: Raviteja Tamatam 
Signed-off-by: Raviteja Tamatam 
Signed-off-by: Kalyan Thota 
---
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 21 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 84 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 24 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 28 
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h|  6 ++
 6 files changed, 159 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index b9c84fb..8cc8ad12 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -280,6 +280,14 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
&timing_params, fmt);
phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
+
+   /* setup which pp blk will connect to this intf */
+   if (phys_enc->hw_intf->ops.bind_pingpong_blk)
+   phys_enc->hw_intf->ops.bind_pingpong_blk(
+   phys_enc->hw_intf,
+   true,
+   phys_enc->hw_pp->idx);
+
spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
 
programmable_fetch_config(phys_enc, &timing_params);
@@ -435,6 +443,7 @@ static void dpu_encoder_phys_vid_enable(struct 
dpu_encoder_phys *phys_enc)
 {
struct dpu_hw_ctl *ctl;
u32 flush_mask = 0;
+   u32 intf_flush_mask = 0;
 
ctl = phys_enc->hw_ctl;
 
@@ -459,10 +468,18 @@ static void dpu_encoder_phys_vid_enable(struct 
dpu_encoder_phys *phys_enc)
ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->hw_intf->idx);
ctl->ops.update_pending_flush(ctl, flush_mask);
 
+   if (ctl->ops.get_bitmask_active_intf)
+   ctl->ops.get_bitmask_active_intf(ctl, &intf_flush_mask,
+   phys_enc->hw_intf->idx);
+
+   if (ctl->ops.update_pending_intf_flush)
+   ctl->ops.update_pending_intf_flush(ctl, intf_flush_mask);
+
 skip_flush:
DPU_DEBUG_VIDENC(phys_enc,
-"update pending flush ctl %d flush_mask %x\n",
-ctl->idx - CTL_0, flush_mask);
+   "update pending flush ctl %d flush_mask 0%x intf_mask 0x%x\n",
+   ctl->idx - CTL_0, flush_mask, intf_flush_mask);
+
 
/* ctl_flush & timing engine enable will be triggered by framework */
if (phys_enc->enable_state == DPU_ENC_DISABLED)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 1cf4509..0ee2b6c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -374,6 +374,7 @@
{\
.name = _name, .id = _id, \
.base = _base, .len = 0x280, \
+   .features = BIT(DPU_CTL_ACTIVE_CFG), \
.type = _type, \
.controller_id = _ctrl_id, \
.prog_fetch_lines_worst_case = 24 \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 179e8d5..2ce4b5a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -22,11 +22,15 @@
 #define   CTL_PREPARE   0x0d0
 #define   CTL_SW_RESET  0x030
 #define   CTL_LAYER_EXTN_OFFSET 0x40
+#define   CTL_INTF_ACTIVE   0x0F4
+#define   CTL_INTF_FLUSH0x110
+#define   CTL_INTF_MASTER   0x134
 
 #define CTL_MIXER_BORDER_OUTBIT(24)
 #define CTL_FLUSH_MASK_CTL  BIT(17)
 
 #define DPU_REG_RESET_TIMEOUT_US2000
+#define  INTF_IDX   31
 
 static struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl,
struct dpu_mdss_cfg *m,
@@ -100,11 +104,27 @@ static inline void dpu_hw_ctl_update_pending_flush(struct 
dpu_hw_ctl *ctx,
ctx->pending_flush_mask |= flushbits;
 }
 
+static inline void dpu_hw_ctl_update_pending_intf_flush(struct dpu_hw_ctl *ctx,
+   u32 flushbits)
+{
+   ctx

[Freedreno] [PATCH v3] msm:disp:dpu1: add support for display for SC7180 target

[Kalyan Thota]

Add display hw catalog changes for SC7180 target.

Changes in v1:
 - Configure register offsets and capabilities for the
   display hw blocks.

Changes in v2:
 - mdss_irq data type has changed in the dependent
   patch, accommodate the necessary changes.
 - Add co-developed-by tags in the commit msg (Stephen Boyd).

Changes in v3:
 - fix kernel checkpatch errors in v2

This patch has dependency on the below series

https://patchwork.kernel.org/patch/11253647/

Co-developed-by: Shubhashree Dhar 
Signed-off-by: Shubhashree Dhar 
Co-developed-by: Raviteja Tamatam 
Signed-off-by: Raviteja Tamatam 
Signed-off-by: Kalyan Thota 
---
 .../devicetree/bindings/display/msm/dpu.txt|   4 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 189 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   4 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c  |   3 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|   1 +
 drivers/gpu/drm/msm/msm_drv.c  |   4 +-
 6 files changed, 190 insertions(+), 15 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt 
b/Documentation/devicetree/bindings/display/msm/dpu.txt
index a61dd40..512f022 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
@@ -8,7 +8,7 @@ The DPU display controller is found in SDM845 SoC.
 
 MDSS:
 Required properties:
-- compatible: "qcom,sdm845-mdss"
+- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
 - reg: physical base address and length of contoller's registers.
 - reg-names: register region names. The following region is required:
   * "mdss"
@@ -41,7 +41,7 @@ Optional properties:
 
 MDP:
 Required properties:
-- compatible: "qcom,sdm845-dpu"
+- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
 - reg: physical base address and length of controller's registers.
 - reg-names : register region names. The following region is required:
   * "mdp"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 88f2664..1cf4509 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -11,11 +11,17 @@
 #include "dpu_hw_catalog_format.h"
 #include "dpu_kms.h"
 
-#define VIG_SDM845_MASK \
-   (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_SCALER_QSEED3) | BIT(DPU_SSPP_QOS) |\
+#define VIG_MASK \
+   (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_QOS_8LVL) |\
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
 
+#define VIG_SDM845_MASK \
+   (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
+
+#define VIG_SC7180_MASK \
+   (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED4))
+
 #define DMA_SDM845_MASK \
(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
@@ -27,6 +33,9 @@
 #define MIXER_SDM845_MASK \
(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
 
+#define MIXER_SC7180_MASK \
+   (BIT(DPU_DIM_LAYER))
+
 #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER)
 
 #define PINGPONG_SDM845_SPLIT_MASK \
@@ -60,6 +69,16 @@
.has_idle_pc = true,
 };
 
+static const struct dpu_caps sc7180_dpu_caps = {
+   .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+   .max_mixer_blendstages = 0x9,
+   .qseed_type = DPU_SSPP_SCALER_QSEED4,
+   .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
+   .ubwc_version = DPU_HW_UBWC_VER_20,
+   .has_dim_layer = true,
+   .has_idle_pc = true,
+};
+
 static struct dpu_mdp_cfg sdm845_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -85,6 +104,23 @@
},
 };
 
+static struct dpu_mdp_cfg sc7180_mdp[] = {
+   {
+   .name = "top_0", .id = MDP_TOP,
+   .base = 0x0, .len = 0x494,
+   .features = 0,
+   .highest_bank_bit = 0x3,
+   .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+   .reg_off = 0x2AC, .bit_off = 0},
+   .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+   .reg_off = 0x2AC, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+   .reg_off = 0x2B4, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+   .reg_off = 0x2BC, .bit_off = 8},
+   },
+};
+
 /*
  * CTL sub blocks config
  */
@@ -116,6 +152,24 @@
},
 };
 
+static struct dpu_ctl_cfg sc7180_ctl[] = {
+   {
+   .name = "ctl_0", .id = CTL_0,
+   .base = 0x1000, .len = 0xE4,
+   .features = BIT(DPU_CTL_ACTIVE_CFG)
+   },
+   {
+   .name = "ctl_1", .id = CTL_1,
+   .base = 0x1200, .len = 0xE4,
+   .features = BIT(DPU_CTL_

[Freedreno] [PATCH v3] msm:disp:dpu1: setup display datapath for SC7180 target

[Kalyan Thota]

Add changes to setup display datapath on SC7180 target.

Changes in v1:
 - Add changes to support ctl_active on SC7180 target.
 - While selecting the number of mixers in the topology
   consider the interface width.

Changes in v2:
 - Spawn topology mixer selection into separate patch (Rob Clark).
 - Add co-developed-by tags in the commit msg (Stephen Boyd).

Changes in v3:
 - Fix kernel checkpatch errors in v2.

This patch has dependency on the below series

https://patchwork.kernel.org/patch/11253747/

Co-developed-by: Shubhashree Dhar 
Signed-off-by: Shubhashree Dhar 
Co-developed-by: Raviteja Tamatam 
Signed-off-by: Raviteja Tamatam 
Signed-off-by: Kalyan Thota 
---
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 21 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 84 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 24 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 28 
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h|  6 ++
 6 files changed, 159 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index b9c84fb..8cc8ad12 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -280,6 +280,14 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
&timing_params, fmt);
phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
+
+   /* setup which pp blk will connect to this intf */
+   if (phys_enc->hw_intf->ops.bind_pingpong_blk)
+   phys_enc->hw_intf->ops.bind_pingpong_blk(
+   phys_enc->hw_intf,
+   true,
+   phys_enc->hw_pp->idx);
+
spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
 
programmable_fetch_config(phys_enc, &timing_params);
@@ -435,6 +443,7 @@ static void dpu_encoder_phys_vid_enable(struct 
dpu_encoder_phys *phys_enc)
 {
struct dpu_hw_ctl *ctl;
u32 flush_mask = 0;
+   u32 intf_flush_mask = 0;
 
ctl = phys_enc->hw_ctl;
 
@@ -459,10 +468,18 @@ static void dpu_encoder_phys_vid_enable(struct 
dpu_encoder_phys *phys_enc)
ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->hw_intf->idx);
ctl->ops.update_pending_flush(ctl, flush_mask);
 
+   if (ctl->ops.get_bitmask_active_intf)
+   ctl->ops.get_bitmask_active_intf(ctl, &intf_flush_mask,
+   phys_enc->hw_intf->idx);
+
+   if (ctl->ops.update_pending_intf_flush)
+   ctl->ops.update_pending_intf_flush(ctl, intf_flush_mask);
+
 skip_flush:
DPU_DEBUG_VIDENC(phys_enc,
-"update pending flush ctl %d flush_mask %x\n",
-ctl->idx - CTL_0, flush_mask);
+   "update pending flush ctl %d flush_mask 0%x intf_mask 0x%x\n",
+   ctl->idx - CTL_0, flush_mask, intf_flush_mask);
+
 
/* ctl_flush & timing engine enable will be triggered by framework */
if (phys_enc->enable_state == DPU_ENC_DISABLED)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 1cf4509..0ee2b6c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -374,6 +374,7 @@
{\
.name = _name, .id = _id, \
.base = _base, .len = 0x280, \
+   .features = BIT(DPU_CTL_ACTIVE_CFG), \
.type = _type, \
.controller_id = _ctrl_id, \
.prog_fetch_lines_worst_case = 24 \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 179e8d5..2ce4b5a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -22,11 +22,15 @@
 #define   CTL_PREPARE   0x0d0
 #define   CTL_SW_RESET  0x030
 #define   CTL_LAYER_EXTN_OFFSET 0x40
+#define   CTL_INTF_ACTIVE   0x0F4
+#define   CTL_INTF_FLUSH0x110
+#define   CTL_INTF_MASTER   0x134
 
 #define CTL_MIXER_BORDER_OUTBIT(24)
 #define CTL_FLUSH_MASK_CTL  BIT(17)
 
 #define DPU_REG_RESET_TIMEOUT_US2000
+#define  INTF_IDX   31
 
 static struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl,
struct dpu_mdss_cfg *m,
@@ -100,11 +104,27 @@ static inline void dpu_hw_ctl_update_pending_flush(struct 
dpu_hw_ctl *ctx,
ctx->pending_flush_mask |= flushbits;
 }
 
+static inline void dpu_hw_ctl_update_pending_intf_flush(struct dpu_hw_ctl *ctx,

[Freedreno] [PATCH 1/4] dt-bindings: msm:disp: add sc7180 DPU variant

[Kalyan Thota]

Add a compatible string to support sc7180 dpu version.

Signed-off-by: Kalyan Thota 
---
 Documentation/devicetree/bindings/display/msm/dpu.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt 
b/Documentation/devicetree/bindings/display/msm/dpu.txt
index a61dd40..551ae26 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
@@ -8,7 +8,7 @@ The DPU display controller is found in SDM845 SoC.
 
 MDSS:
 Required properties:
-- compatible: "qcom,sdm845-mdss"
+- compatible:  "qcom,sdm845-mdss", "qcom,sc7180-mdss"
 - reg: physical base address and length of contoller's registers.
 - reg-names: register region names. The following region is required:
   * "mdss"
@@ -41,7 +41,7 @@ Optional properties:
 
 MDP:
 Required properties:
-- compatible: "qcom,sdm845-dpu"
+- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
 - reg: physical base address and length of controller's registers.
 - reg-names : register region names. The following region is required:
   * "mdp"
-- 
1.9.1

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[Freedreno] [PATCH 3/4] msm:disp:dpu1: setup display datapath for SC7180 target

[Kalyan Thota]

Add changes to setup display datapath on SC7180 target.

Changes in v1:
 - Add changes to support ctl_active on SC7180 target.
 - While selecting the number of mixers in the topology
   consider the interface width.

Changes in v2:
 - Spawn topology mixer selection into separate patch (Rob Clark).
 - Add co-developed-by tags in the commit msg (Stephen Boyd).

Changes in v3:
 - Fix kernel checkpatch errors in v2.

This patch has dependency on the below series

https://patchwork.kernel.org/patch/11253747/

Co-developed-by: Shubhashree Dhar 
Signed-off-by: Shubhashree Dhar 
Co-developed-by: Raviteja Tamatam 
Signed-off-by: Raviteja Tamatam 
Signed-off-by: Kalyan Thota 
---
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 21 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 84 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 24 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 28 
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h|  6 ++
 6 files changed, 159 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index b9c84fb..8cc8ad12 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -280,6 +280,14 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
&timing_params, fmt);
phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
+
+   /* setup which pp blk will connect to this intf */
+   if (phys_enc->hw_intf->ops.bind_pingpong_blk)
+   phys_enc->hw_intf->ops.bind_pingpong_blk(
+   phys_enc->hw_intf,
+   true,
+   phys_enc->hw_pp->idx);
+
spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
 
programmable_fetch_config(phys_enc, &timing_params);
@@ -435,6 +443,7 @@ static void dpu_encoder_phys_vid_enable(struct 
dpu_encoder_phys *phys_enc)
 {
struct dpu_hw_ctl *ctl;
u32 flush_mask = 0;
+   u32 intf_flush_mask = 0;
 
ctl = phys_enc->hw_ctl;
 
@@ -459,10 +468,18 @@ static void dpu_encoder_phys_vid_enable(struct 
dpu_encoder_phys *phys_enc)
ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->hw_intf->idx);
ctl->ops.update_pending_flush(ctl, flush_mask);
 
+   if (ctl->ops.get_bitmask_active_intf)
+   ctl->ops.get_bitmask_active_intf(ctl, &intf_flush_mask,
+   phys_enc->hw_intf->idx);
+
+   if (ctl->ops.update_pending_intf_flush)
+   ctl->ops.update_pending_intf_flush(ctl, intf_flush_mask);
+
 skip_flush:
DPU_DEBUG_VIDENC(phys_enc,
-"update pending flush ctl %d flush_mask %x\n",
-ctl->idx - CTL_0, flush_mask);
+   "update pending flush ctl %d flush_mask 0%x intf_mask 0x%x\n",
+   ctl->idx - CTL_0, flush_mask, intf_flush_mask);
+
 
/* ctl_flush & timing engine enable will be triggered by framework */
if (phys_enc->enable_state == DPU_ENC_DISABLED)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 1cf4509..0ee2b6c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -374,6 +374,7 @@
{\
.name = _name, .id = _id, \
.base = _base, .len = 0x280, \
+   .features = BIT(DPU_CTL_ACTIVE_CFG), \
.type = _type, \
.controller_id = _ctrl_id, \
.prog_fetch_lines_worst_case = 24 \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 179e8d5..2ce4b5a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -22,11 +22,15 @@
 #define   CTL_PREPARE   0x0d0
 #define   CTL_SW_RESET  0x030
 #define   CTL_LAYER_EXTN_OFFSET 0x40
+#define   CTL_INTF_ACTIVE   0x0F4
+#define   CTL_INTF_FLUSH0x110
+#define   CTL_INTF_MASTER   0x134
 
 #define CTL_MIXER_BORDER_OUTBIT(24)
 #define CTL_FLUSH_MASK_CTL  BIT(17)
 
 #define DPU_REG_RESET_TIMEOUT_US2000
+#define  INTF_IDX   31
 
 static struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl,
struct dpu_mdss_cfg *m,
@@ -100,11 +104,27 @@ static inline void dpu_hw_ctl_update_pending_flush(struct 
dpu_hw_ctl *ctx,
ctx->pending_flush_mask |= flushbits;
 }
 
+static inline void dpu_hw_ctl_update_pending_intf_flush(struct dpu_hw_ctl *ctx,

[Freedreno] [PATCH 2/4] msm:disp:dpu1: add support for display for SC7180 target

[Kalyan Thota]

Add display hw catalog changes for SC7180 target.

Changes in v1:
 - Configure register offsets and capabilities for the
   display hw blocks.

Changes in v2:
 - mdss_irq data type has changed in the dependent
   patch, accommodate the necessary changes.
 - Add co-developed-by tags in the commit msg (Stephen Boyd).

Changes in v3:
 - fix kernel checkpatch errors in v2

Changes in v4:
 - move documentation into seperate patch (Rob Herring).

This patch has dependency on the below series

https://patchwork.kernel.org/patch/11253647/

Co-developed-by: Shubhashree Dhar 
Signed-off-by: Shubhashree Dhar 
Co-developed-by: Raviteja Tamatam 
Signed-off-by: Raviteja Tamatam 
Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 189 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   4 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c  |   3 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|   1 +
 drivers/gpu/drm/msm/msm_drv.c  |   4 +-
 5 files changed, 188 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 88f2664..1cf4509 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -11,11 +11,17 @@
 #include "dpu_hw_catalog_format.h"
 #include "dpu_kms.h"
 
-#define VIG_SDM845_MASK \
-   (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_SCALER_QSEED3) | BIT(DPU_SSPP_QOS) |\
+#define VIG_MASK \
+   (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_QOS_8LVL) |\
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
 
+#define VIG_SDM845_MASK \
+   (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
+
+#define VIG_SC7180_MASK \
+   (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED4))
+
 #define DMA_SDM845_MASK \
(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
@@ -27,6 +33,9 @@
 #define MIXER_SDM845_MASK \
(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
 
+#define MIXER_SC7180_MASK \
+   (BIT(DPU_DIM_LAYER))
+
 #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER)
 
 #define PINGPONG_SDM845_SPLIT_MASK \
@@ -60,6 +69,16 @@
.has_idle_pc = true,
 };
 
+static const struct dpu_caps sc7180_dpu_caps = {
+   .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+   .max_mixer_blendstages = 0x9,
+   .qseed_type = DPU_SSPP_SCALER_QSEED4,
+   .smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
+   .ubwc_version = DPU_HW_UBWC_VER_20,
+   .has_dim_layer = true,
+   .has_idle_pc = true,
+};
+
 static struct dpu_mdp_cfg sdm845_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -85,6 +104,23 @@
},
 };
 
+static struct dpu_mdp_cfg sc7180_mdp[] = {
+   {
+   .name = "top_0", .id = MDP_TOP,
+   .base = 0x0, .len = 0x494,
+   .features = 0,
+   .highest_bank_bit = 0x3,
+   .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+   .reg_off = 0x2AC, .bit_off = 0},
+   .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+   .reg_off = 0x2AC, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+   .reg_off = 0x2B4, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+   .reg_off = 0x2BC, .bit_off = 8},
+   },
+};
+
 /*
  * CTL sub blocks config
  */
@@ -116,6 +152,24 @@
},
 };
 
+static struct dpu_ctl_cfg sc7180_ctl[] = {
+   {
+   .name = "ctl_0", .id = CTL_0,
+   .base = 0x1000, .len = 0xE4,
+   .features = BIT(DPU_CTL_ACTIVE_CFG)
+   },
+   {
+   .name = "ctl_1", .id = CTL_1,
+   .base = 0x1200, .len = 0xE4,
+   .features = BIT(DPU_CTL_ACTIVE_CFG)
+   },
+   {
+   .name = "ctl_2", .id = CTL_2,
+   .base = 0x1400, .len = 0xE4,
+   .features = BIT(DPU_CTL_ACTIVE_CFG)
+   },
+};
+
 /*
  * SSPP sub blocks config
  */
@@ -203,9 +257,23 @@
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
 };
 
+static struct dpu_sspp_cfg sc7180_sspp[] = {
+   SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
+   sdm845_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+   SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
+   sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+   SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_SDM845_MASK,
+   sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
+   SSPP_BLK("sspp_10", SSPP_DMA

[Freedreno] [PATCH 4/4] msm:disp:dpu1: add mixer selection for display topology

[Kalyan Thota]

mixer selection in the display topology is based on multiple
factors
1) mixers available in the hw
2) interfaces to be enabled
3) merge capability

change will pickup mixer as per the topology need.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 21 ++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  2 ++
 3 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index d82ea99..067ef0b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -58,7 +58,7 @@
 
 #define IDLE_SHORT_TIMEOUT 1
 
-#define MAX_VDISPLAY_SPLIT 1080
+#define MAX_HDISPLAY_SPLIT 1080
 
 /* timeout in frames waiting for frame done */
 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5
@@ -534,8 +534,23 @@ static struct msm_display_topology 
dpu_encoder_get_topology(
if (dpu_enc->phys_encs[i])
intf_count++;
 
-   /* User split topology for width > 1080 */
-   topology.num_lm = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
+   /* Datapath topology selection
+*
+* Dual display
+* 2 LM, 2 INTF ( Split display using 2 interfaces)
+*
+* Single display
+* 1 LM, 1 INTF
+* 2 LM, 1 INTF (stream merge to support high resolution interfaces)
+*
+*/
+   if (intf_count == 2)
+   topology.num_lm = 2;
+   else if (!dpu_kms->catalog->caps->has_3d_merge)
+   topology.num_lm = 1;
+   else
+   topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
+
topology.num_enc = 0;
topology.num_intf = intf_count;
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 0ee2b6c..de69f71 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -67,6 +67,7 @@
.has_src_split = true,
.has_dim_layer = true,
.has_idle_pc = true,
+   .has_3d_merge = true,
 };
 
 static const struct dpu_caps sc7180_dpu_caps = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 2607ef3..d0cb41c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -287,6 +287,7 @@ struct dpu_qos_lut_tbl {
  * @has_src_split  source split feature status
  * @has_dim_layer  dim layer feature status
  * @has_idle_pcindicate if idle power collapse feature is supported
+ * @has_3d_merge   indicate if 3D merge is supported
  */
 struct dpu_caps {
u32 max_mixer_width;
@@ -297,6 +298,7 @@ struct dpu_caps {
bool has_src_split;
bool has_dim_layer;
bool has_idle_pc;
+   bool has_3d_merge;
 };
 
 /**
-- 
1.9.1

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[Freedreno] [PATCH 0/4] Add support for SC7180 display

[Kalyan Thota]

SC7180 follows a newer architecture where in some flush controls have been 
re-organized to simplify programming and provide for future expandability.
Specifically:
1) The TIMING_ bits that control flush of INTF_ have been replaced with a 
common INTF flush bit which flushes the programming in the 
MDP_CTL__INTF_ACTIVE register
2) Individual flush bits for MERGE_3D, DSC and CDWN have been added which flush 
the programming in the MDP_CTL__MERGE_3D_ACTIVE, ... etc respectively
3) PERIPH flush bit has been added to flush DSP packets for DisplayPort

The complete datapath is described using the MDP_CTL__TOP and newly added 
ACTIVE registers to handle other sub blocks
such as interface (INTF) resources, PingPong buffer / Layer Mixer, Display 
Stream Compression (DSC) resources, writeback (WB) and 3D Merge
selections that are part of the datapath.

Kalyan Thota (4):
  dt-bindings: msm:disp: add sc7180 DPU variant
  msm:disp:dpu1: add support for display for SC7180 target
  msm:disp:dpu1: setup display datapath for SC7180 target
  msm:disp:dpu1: add mixer selection for display topology

 .../devicetree/bindings/display/msm/dpu.txt|   4 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  21 ++-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  21 ++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 191 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   6 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c |  84 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |  24 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c|  28 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h|   6 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c  |   3 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|   1 +
 drivers/gpu/drm/msm/msm_drv.c  |   4 +-
 12 files changed, 370 insertions(+), 23 deletions(-)

-- 
1.9.1

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[Freedreno] [PATCH] msm:disp:dpu1: add UBWC support for display on SC7180

[Kalyan Thota]

Add UBWC global configuration for display on
SC7180 target.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 58 +++-
 1 file changed, 57 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
index 29705e7..80d3cfc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
@@ -12,6 +12,7 @@
 
 #define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)
 
+#define HW_REV 0x0
 #define HW_INTR_STATUS 0x0010
 
 /* Max BW defined in KBps */
@@ -22,6 +23,17 @@ struct dpu_irq_controller {
struct irq_domain *domain;
 };
 
+struct dpu_hw_cfg {
+   u32 val;
+   u32 offset;
+};
+
+struct dpu_mdss_hw_init_handler {
+   u32 hw_rev;
+   u32 hw_reg_count;
+   struct dpu_hw_cfg* hw_cfg;
+};
+
 struct dpu_mdss {
struct msm_mdss base;
void __iomem *mmio;
@@ -32,6 +44,44 @@ struct dpu_mdss {
u32 num_paths;
 };
 
+static struct dpu_hw_cfg hw_cfg[] = {
+{
+   /* UBWC global settings */
+   .val = 0x1E,
+   .offset = 0x144,
+}
+};
+
+static struct dpu_mdss_hw_init_handler cfg_handler[] = {
+{ .hw_rev = DPU_HW_VER_620,
+  .hw_reg_count = ARRAY_SIZE(hw_cfg),
+  .hw_cfg = hw_cfg
+},
+};
+
+static void dpu_mdss_hw_init(struct dpu_mdss *dpu_mdss, u32 hw_rev)
+{
+   int i;
+   u32 count = 0;
+   struct dpu_hw_cfg *hw_cfg = NULL;
+
+   for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) {
+   if (cfg_handler[i].hw_rev == hw_rev) {
+   hw_cfg = cfg_handler[i].hw_cfg;
+   count = cfg_handler[i].hw_reg_count;
+   break;
+   }
+   }
+
+   for (i = 0; i < count; i++ ) {
+   writel_relaxed(hw_cfg->val,
+   dpu_mdss->mmio + hw_cfg->offset);
+   hw_cfg++;
+   }
+
+return;
+}
+
 static int dpu_mdss_parse_data_bus_icc_path(struct drm_device *dev,
struct dpu_mdss *dpu_mdss)
 {
@@ -174,12 +224,18 @@ static int dpu_mdss_enable(struct msm_mdss *mdss)
struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
struct dss_module_power *mp = &dpu_mdss->mp;
int ret;
+   u32 mdss_rev;
 
dpu_mdss_icc_request_bw(mdss);
 
ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
-   if (ret)
+   if (ret) {
DPU_ERROR("clock enable failed, ret:%d\n", ret);
+   return ret;
+   }
+
+   mdss_rev = readl_relaxed(dpu_mdss->mmio + HW_REV);
+   dpu_mdss_hw_init(dpu_mdss, mdss_rev);
 
return ret;
 }
-- 
1.9.1

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[Freedreno] [PATCH] drm/msm/dpu: ensure device suspend happens during PM sleep

[Kalyan Thota]

"The PM core always increments the runtime usage counter
before calling the ->suspend() callback and decrements it
after calling the ->resume() callback"

DPU and DSI are managed as runtime devices. When
suspend is triggered, PM core adds a refcount on all the
devices and calls device suspend, since usage count is
already incremented, runtime suspend was not getting called
and it kept the clocks on which resulted in target not
entering into XO shutdown.

Add changes to manage runtime devices during pm sleep.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 41 +
 drivers/gpu/drm/msm/dsi/dsi.c   |  7 ++
 drivers/gpu/drm/msm/msm_drv.c   | 14 +++
 drivers/gpu/drm/msm/msm_kms.h   |  2 ++
 4 files changed, 64 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index cb08faf..6e103d5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -26,6 +26,7 @@
 #include "dpu_encoder.h"
 #include "dpu_plane.h"
 #include "dpu_crtc.h"
+#include "dsi.h"
 
 #define CREATE_TRACE_POINTS
 #include "dpu_trace.h"
@@ -250,6 +251,37 @@ static void dpu_kms_disable_commit(struct msm_kms *kms)
pm_runtime_put_sync(&dpu_kms->pdev->dev);
 }
 
+static void _dpu_kms_disable_dpu(struct msm_kms *kms)
+{
+   struct drm_device *dev;
+   struct msm_drm_private *priv;
+   struct dpu_kms *dpu_kms;
+   int i = 0;
+   struct msm_dsi *dsi;
+
+   dpu_kms = to_dpu_kms(kms);
+   dev = dpu_kms->dev;
+   if (!dev) {
+   DPU_ERROR("invalid device\n");
+   return;
+   }
+
+   priv = dev->dev_private;
+   if (!priv) {
+   DPU_ERROR("invalid private data\n");
+   return;
+   }
+
+   dpu_kms_disable_commit(kms);
+
+   for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
+   if (!priv->dsi[i])
+   continue;
+   dsi = priv->dsi[i];
+   pm_runtime_put_sync(&dsi->pdev->dev);
+   }
+}
+
 static ktime_t dpu_kms_vsync_time(struct msm_kms *kms, struct drm_crtc *crtc)
 {
struct drm_encoder *encoder;
@@ -683,6 +715,7 @@ static void dpu_irq_uninstall(struct msm_kms *kms)
 #ifdef CONFIG_DEBUG_FS
.debugfs_init= dpu_kms_debugfs_init,
 #endif
+   .disable_dpu = _dpu_kms_disable_dpu,
 };
 
 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms)
@@ -1053,7 +1086,15 @@ static int __maybe_unused dpu_runtime_resume(struct 
device *dev)
return rc;
 }
 
+
+static int __maybe_unused dpu_pm_suspend_late(struct device *dev)
+{
+   pm_runtime_get_noresume(dev);
+   return 0;
+}
+
 static const struct dev_pm_ops dpu_pm_ops = {
+   SET_LATE_SYSTEM_SLEEP_PM_OPS(dpu_pm_suspend_late, NULL)
SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL)
 };
 
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index 55ea4bc2..3d3740e 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -154,12 +154,19 @@ static int dsi_dev_remove(struct platform_device *pdev)
return 0;
 }
 
+static int __maybe_unused dsi_pm_suspend_late(struct device *dev)
+{
+   pm_runtime_get_noresume(dev);
+   return 0;
+}
+
 static const struct of_device_id dt_match[] = {
{ .compatible = "qcom,mdss-dsi-ctrl" },
{}
 };
 
 static const struct dev_pm_ops dsi_pm_ops = {
+   SET_LATE_SYSTEM_SLEEP_PM_OPS(dsi_pm_suspend_late, NULL)
SET_RUNTIME_PM_OPS(msm_dsi_runtime_suspend, msm_dsi_runtime_resume, 
NULL)
 };
 
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index e4b750b..12ec1c6 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -1038,6 +1038,7 @@ static int msm_pm_suspend(struct device *dev)
 {
struct drm_device *ddev = dev_get_drvdata(dev);
struct msm_drm_private *priv = ddev->dev_private;
+   struct msm_kms *kms = priv->kms;
 
if (WARN_ON(priv->pm_state))
drm_atomic_state_put(priv->pm_state);
@@ -1049,6 +1050,11 @@ static int msm_pm_suspend(struct device *dev)
return ret;
}
 
+   if (kms->funcs->disable_dpu)
+   kms->funcs->disable_dpu(kms);
+
+   pm_runtime_put_sync(dev);
+
return 0;
 }
 
@@ -1067,6 +1073,13 @@ static int msm_pm_resume(struct device *dev)
 
return ret;
 }
+
+static int msm_pm_suspend_late(struct device *dev)
+{
+   pm_runtime_get_noresume(dev);
+   return 0;
+}
+
 #endif
 
 #ifdef CONFIG_PM
@@ -1100,6 +1113,7 @@ static int msm_runtime_resume(struct device *dev)
 #endif
 
 static const struct dev_pm_ops msm_pm_ops = {
+   SET_LATE_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend

[Freedreno] [PATCH] drm/msm/dpu: ensure device suspend happens during PM sleep

[Kalyan Thota]

"The PM core always increments the runtime usage counter
before calling the ->suspend() callback and decrements it
after calling the ->resume() callback"

DPU and DSI are managed as runtime devices. When
suspend is triggered, PM core adds a refcount on all the
devices and calls device suspend, since usage count is
already incremented, runtime suspend was not getting called
and it kept the clocks on which resulted in target not
entering into XO shutdown.

Add changes to manage runtime devices during pm sleep.

Changes in v1:
 - Remove unnecessary checks in the function
 _dpu_kms_disable_dpu (Rob Clark).

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 28 
 drivers/gpu/drm/msm/dsi/dsi.c   |  7 +++
 drivers/gpu/drm/msm/msm_drv.c   | 14 ++
 drivers/gpu/drm/msm/msm_kms.h   |  2 ++
 4 files changed, 51 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index ce19f1d..c3e8287 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -26,6 +26,7 @@
 #include "dpu_encoder.h"
 #include "dpu_plane.h"
 #include "dpu_crtc.h"
+#include "dsi.h"
 
 #define CREATE_TRACE_POINTS
 #include "dpu_trace.h"
@@ -325,6 +326,24 @@ static void dpu_kms_disable_commit(struct msm_kms *kms)
pm_runtime_put_sync(&dpu_kms->pdev->dev);
 }
 
+static void _dpu_kms_disable_dpu(struct msm_kms *kms)
+{
+   struct dpu_kms *dpu_kms = to_dpu_kms(kms);
+   struct drm_device *dev = dpu_kms->dev;
+   struct msm_drm_private *priv = dev->dev_private;
+   struct msm_dsi *dsi;
+   int i;
+
+   dpu_kms_disable_commit(kms);
+
+   for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
+   if (!priv->dsi[i])
+   continue;
+   dsi = priv->dsi[i];
+   pm_runtime_put_sync(&dsi->pdev->dev);
+   }
+}
+
 static ktime_t dpu_kms_vsync_time(struct msm_kms *kms, struct drm_crtc *crtc)
 {
struct drm_encoder *encoder;
@@ -751,6 +770,7 @@ static void dpu_irq_uninstall(struct msm_kms *kms)
 #ifdef CONFIG_DEBUG_FS
.debugfs_init= dpu_kms_debugfs_init,
 #endif
+   .disable_dpu = _dpu_kms_disable_dpu,
 };
 
 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms)
@@ -1121,7 +1141,15 @@ static int __maybe_unused dpu_runtime_resume(struct 
device *dev)
return rc;
 }
 
+
+static int __maybe_unused dpu_pm_suspend_late(struct device *dev)
+{
+   pm_runtime_get_noresume(dev);
+   return 0;
+}
+
 static const struct dev_pm_ops dpu_pm_ops = {
+   SET_LATE_SYSTEM_SLEEP_PM_OPS(dpu_pm_suspend_late, NULL)
SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL)
 };
 
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index 55ea4bc2..3d3740e 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -154,12 +154,19 @@ static int dsi_dev_remove(struct platform_device *pdev)
return 0;
 }
 
+static int __maybe_unused dsi_pm_suspend_late(struct device *dev)
+{
+   pm_runtime_get_noresume(dev);
+   return 0;
+}
+
 static const struct of_device_id dt_match[] = {
{ .compatible = "qcom,mdss-dsi-ctrl" },
{}
 };
 
 static const struct dev_pm_ops dsi_pm_ops = {
+   SET_LATE_SYSTEM_SLEEP_PM_OPS(dsi_pm_suspend_late, NULL)
SET_RUNTIME_PM_OPS(msm_dsi_runtime_suspend, msm_dsi_runtime_resume, 
NULL)
 };
 
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 7d985f8..7451ae0 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -1040,6 +1040,7 @@ static int msm_pm_suspend(struct device *dev)
 {
struct drm_device *ddev = dev_get_drvdata(dev);
struct msm_drm_private *priv = ddev->dev_private;
+   struct msm_kms *kms = priv->kms;
 
if (WARN_ON(priv->pm_state))
drm_atomic_state_put(priv->pm_state);
@@ -1051,6 +1052,11 @@ static int msm_pm_suspend(struct device *dev)
return ret;
}
 
+   if (kms->funcs->disable_dpu)
+   kms->funcs->disable_dpu(kms);
+
+   pm_runtime_put_sync(dev);
+
return 0;
 }
 
@@ -1069,6 +1075,13 @@ static int msm_pm_resume(struct device *dev)
 
return ret;
 }
+
+static int msm_pm_suspend_late(struct device *dev)
+{
+   pm_runtime_get_noresume(dev);
+   return 0;
+}
+
 #endif
 
 #ifdef CONFIG_PM
@@ -1102,6 +1115,7 @@ static int msm_runtime_resume(struct device *dev)
 #endif
 
 static const struct dev_pm_ops msm_pm_ops = {
+   SET_LATE_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend_late, NULL)
SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
 };
diff --git a/drivers/gpu/drm

[Freedreno] [PATCH 1/2] drm/msm/dpu: add support for color processing blocks in dpu driver

[Kalyan Thota]

This change adds support to configure dspp blocks in
the dpu driver.

Macro description of the changes coming in this patch.
1) Add dspp definitions in the hw catalog.
2) Add capability to reserve dspp blocks in the display data path.
3) Attach the reserved block to the encoder.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/Makefile   |  1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h   |  2 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 12 +++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 39 
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 39 
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 26 
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |  3 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c| 82 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h| 69 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|  2 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h|  1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 58 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |  2 +
 drivers/gpu/drm/msm/msm_drv.h  |  1 +
 14 files changed, 322 insertions(+), 15 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
 create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 1579cf0..42f8aae 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -65,6 +65,7 @@ msm-y := \
disp/dpu1/dpu_hw_lm.o \
disp/dpu1/dpu_hw_pingpong.o \
disp/dpu1/dpu_hw_sspp.o \
+   disp/dpu1/dpu_hw_dspp.o \
disp/dpu1/dpu_hw_top.o \
disp/dpu1/dpu_hw_util.o \
disp/dpu1/dpu_hw_vbif.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 5174e86..cec3474 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -73,12 +73,14 @@ struct dpu_crtc_smmu_state_data {
  * struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC
  * @hw_lm: LM HW Driver context
  * @lm_ctl:CTL Path HW driver context
+ * @lm_dspp:   DSPP HW driver context
  * @mixer_op_mode: mixer blending operation mode
  * @flush_mask:mixer flush mask for ctl, mixer and pipe
  */
 struct dpu_crtc_mixer {
struct dpu_hw_mixer *hw_lm;
struct dpu_hw_ctl *lm_ctl;
+   struct dpu_hw_dspp *hw_dspp;
u32 mixer_op_mode;
u32 flush_mask;
 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 42bf5c8..deebbba 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -20,6 +20,7 @@
 #include "dpu_hw_catalog.h"
 #include "dpu_hw_intf.h"
 #include "dpu_hw_ctl.h"
+#include "dpu_hw_dspp.h"
 #include "dpu_formats.h"
 #include "dpu_encoder_phys.h"
 #include "dpu_crtc.h"
@@ -537,6 +538,7 @@ static struct msm_display_topology dpu_encoder_get_topology(
 * 1 LM, 1 INTF
 * 2 LM, 1 INTF (stream merge to support high resolution interfaces)
 *
+* Adding color blocks only to primary interface
 */
if (intf_count == 2)
topology.num_lm = 2;
@@ -545,6 +547,9 @@ static struct msm_display_topology dpu_encoder_get_topology(
else
topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
 
+   if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI)
+   topology.num_dspp = topology.num_lm;
+
topology.num_enc = 0;
topology.num_intf = intf_count;
 
@@ -960,7 +965,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder 
*drm_enc,
struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
-   int num_lm, num_ctl, num_pp;
+   struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
+   int num_lm, num_ctl, num_pp, num_dspp;
int i, j;
 
if (!drm_enc) {
@@ -1009,6 +1015,9 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder 
*drm_enc,
drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
+   num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
+   drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp,
+   ARRAY_SIZE(hw_dspp));
 
for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
@@ -1021,6 +1030,7 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder 

[Freedreno] [PATCH 2/2] drm/msm/dpu: add support for pcc color block in dpu driver

[Kalyan Thota]

This change adds support for color correction sub block
for SC7180 device.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   | 77 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  9 ++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c| 49 +++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h| 33 ++-
 4 files changed, 164 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index bf51341..156a997 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -20,6 +21,7 @@
 #include "dpu_kms.h"
 #include "dpu_hw_lm.h"
 #include "dpu_hw_ctl.h"
+#include "dpu_hw_dspp.h"
 #include "dpu_crtc.h"
 #include "dpu_plane.h"
 #include "dpu_encoder.h"
@@ -40,6 +42,9 @@
 /* timeout in ms waiting for frame done */
 #define DPU_CRTC_FRAME_DONE_TIMEOUT_MS 60
 
+#defineCONVERT_S3_15(val) \
+   (u64)val) & ~BIT_ULL(63)) >> 17) & GENMASK_ULL(17, 0))
+
 static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
 {
struct msm_drm_private *priv = crtc->dev->dev_private;
@@ -422,6 +427,74 @@ static void _dpu_crtc_setup_lm_bounds(struct drm_crtc 
*crtc,
drm_mode_debug_printmodeline(adj_mode);
 }
 
+static void _dpu_crtc_get_pcc_coeff(struct drm_crtc_state *state,
+   struct dpu_hw_pcc_cfg *cfg)
+{
+   struct drm_color_ctm *ctm;
+
+   memset(cfg, 0, sizeof(struct dpu_hw_pcc_cfg));
+
+   ctm = (struct drm_color_ctm *)state->ctm->data;
+
+   if (!ctm)
+   return;
+
+   cfg->r.r = CONVERT_S3_15(ctm->matrix[0]);
+   cfg->g.r = CONVERT_S3_15(ctm->matrix[1]);
+   cfg->b.r = CONVERT_S3_15(ctm->matrix[2]);
+
+   cfg->r.g = CONVERT_S3_15(ctm->matrix[3]);
+   cfg->g.g = CONVERT_S3_15(ctm->matrix[4]);
+   cfg->b.g = CONVERT_S3_15(ctm->matrix[5]);
+
+   cfg->r.b = CONVERT_S3_15(ctm->matrix[6]);
+   cfg->g.b = CONVERT_S3_15(ctm->matrix[7]);
+   cfg->b.b = CONVERT_S3_15(ctm->matrix[8]);
+}
+
+static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc)
+{
+   struct drm_crtc_state *state = crtc->state;
+   struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
+   struct dpu_crtc_mixer *mixer = cstate->mixers;
+   struct dpu_hw_pcc_cfg cfg;
+   struct dpu_hw_ctl *ctl;
+   struct dpu_hw_mixer *lm;
+   struct dpu_hw_dspp *dspp;
+   int i;
+
+
+   if (!state->color_mgmt_changed)
+   return;
+
+   for (i = 0; i < cstate->num_mixers; i++) {
+   ctl = mixer[i].lm_ctl;
+   lm = mixer[i].hw_lm;
+   dspp = mixer[i].hw_dspp;
+
+   if (!dspp || !dspp->ops.setup_pcc)
+   continue;
+
+   if (!state->ctm) {
+   dspp->ops.setup_pcc(dspp, NULL);
+   } else {
+   _dpu_crtc_get_pcc_coeff(state, &cfg);
+   dspp->ops.setup_pcc(dspp, &cfg);
+   }
+
+   mixer[i].flush_mask |= ctl->ops.get_bitmask_dspp(ctl,
+   mixer[i].hw_dspp->idx);
+
+   /* stage config flush mask */
+   ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask);
+
+   DPU_DEBUG("lm %d, ctl %d, flush mask 0x%x\n",
+   mixer[i].hw_lm->idx - DSPP_0,
+   ctl->idx - CTL_0,
+   mixer[i].flush_mask);
+   }
+}
+
 static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
struct drm_crtc_state *old_state)
 {
@@ -475,6 +548,8 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
 
_dpu_crtc_blend_setup(crtc);
 
+   _dpu_crtc_setup_cp_blocks(crtc);
+
/*
 * PP_DONE irq is only used by command mode for now.
 * It is better to request pending before FLUSH and START trigger
@@ -1317,6 +1392,8 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, 
struct drm_plane *plane,
 
drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
 
+   drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
+
/* save user friendly CRTC name for later */
snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 19d065a..731b4fb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -41,7 +41,7 @@
 #define PINGPONG_SDM845_SPLIT_MASK \
(PING

[Freedreno] [PATCH] drm/msm/dpu: ensure device suspend happens during PM sleep

[Kalyan Thota]

"The PM core always increments the runtime usage counter
before calling the ->suspend() callback and decrements it
after calling the ->resume() callback"

DPU and DSI are managed as runtime devices. When
suspend is triggered, PM core adds a refcount on all the
devices and calls device suspend, since usage count is
already incremented, runtime suspend was not getting called
and it kept the clocks on which resulted in target not
entering into XO shutdown.

Add changes to manage runtime devices during pm sleep.

Changes in v1:
 - Remove unnecessary checks in the function
   _dpu_kms_disable_dpu (Rob Clark).

Changes in v2:
 - Avoid using suspend_late to reset the usagecount
   as suspend_late might not be called during suspend
   call failures (Doug).

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 33 +
 drivers/gpu/drm/msm/msm_drv.c   |  4 
 drivers/gpu/drm/msm/msm_kms.h   |  2 ++
 3 files changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index ce19f1d..2343cbd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -26,6 +26,7 @@
 #include "dpu_encoder.h"
 #include "dpu_plane.h"
 #include "dpu_crtc.h"
+#include "dsi.h"
 
 #define CREATE_TRACE_POINTS
 #include "dpu_trace.h"
@@ -325,6 +326,37 @@ static void dpu_kms_disable_commit(struct msm_kms *kms)
pm_runtime_put_sync(&dpu_kms->pdev->dev);
 }
 
+static void _dpu_kms_disable_dpu(struct msm_kms *kms)
+{
+   struct dpu_kms *dpu_kms = to_dpu_kms(kms);
+   struct drm_device *dev = dpu_kms->dev;
+   struct msm_drm_private *priv = dev->dev_private;
+   struct msm_dsi *dsi;
+   int i;
+
+   dpu_kms_disable_commit(kms);
+
+   for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
+   if (!priv->dsi[i])
+   continue;
+   dsi = priv->dsi[i];
+   pm_runtime_put_sync(&dsi->pdev->dev);
+   }
+   pm_runtime_put_sync(dev->dev);
+
+   /* Increment the usagecount without triggering a resume */
+   pm_runtime_get_noresume(dev->dev);
+
+   pm_runtime_get_noresume(&dpu_kms->pdev->dev);
+
+   for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
+   if (!priv->dsi[i])
+   continue;
+   dsi = priv->dsi[i];
+   pm_runtime_get_noresume(&dsi->pdev->dev);
+   }
+}
+
 static ktime_t dpu_kms_vsync_time(struct msm_kms *kms, struct drm_crtc *crtc)
 {
struct drm_encoder *encoder;
@@ -751,6 +783,7 @@ static void dpu_irq_uninstall(struct msm_kms *kms)
 #ifdef CONFIG_DEBUG_FS
.debugfs_init= dpu_kms_debugfs_init,
 #endif
+   .disable_dpu = _dpu_kms_disable_dpu,
 };
 
 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 7d985f8..bb11e00 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -1040,6 +1040,7 @@ static int msm_pm_suspend(struct device *dev)
 {
struct drm_device *ddev = dev_get_drvdata(dev);
struct msm_drm_private *priv = ddev->dev_private;
+   struct msm_kms *kms = priv->kms;
 
if (WARN_ON(priv->pm_state))
drm_atomic_state_put(priv->pm_state);
@@ -1051,6 +1052,9 @@ static int msm_pm_suspend(struct device *dev)
return ret;
}
 
+   if (kms->funcs->disable_dpu)
+   kms->funcs->disable_dpu(kms);
+
return 0;
 }
 
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index 1cbef6b..c73a89b 100644
--- a/drivers/gpu/drm/msm/msm_kms.h
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -126,6 +126,8 @@ struct msm_kms_funcs {
/* debugfs: */
int (*debugfs_init)(struct msm_kms *kms, struct drm_minor *minor);
 #endif
+   void (*disable_dpu)(struct msm_kms *kms);
+
 };
 
 struct msm_kms;
-- 
1.9.1

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[Freedreno] [PATCH] drm/msm/dpu: ensure device suspend happens during PM sleep

[Kalyan Thota]

"The PM core always increments the runtime usage counter
before calling the ->suspend() callback and decrements it
after calling the ->resume() callback"

DPU and DSI are managed as runtime devices. When
suspend is triggered, PM core adds a refcount on all the
devices and calls device suspend, since usage count is
already incremented, runtime suspend was not getting called
and it kept the clocks on which resulted in target not
entering into XO shutdown.

Add changes to force suspend on runtime devices during pm sleep.

Changes in v1:
 - Remove unnecessary checks in the function
_dpu_kms_disable_dpu (Rob Clark).

Changes in v2:
 - Avoid using suspend_late to reset the usagecount
   as suspend_late might not be called during suspend
   call failures (Doug).

Changes in v3:
 - Use force suspend instead of managing device usage_count
   via runtime put and get API's to trigger callbacks (Doug).

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++
 drivers/gpu/drm/msm/dsi/dsi.c   | 2 ++
 drivers/gpu/drm/msm/msm_drv.c   | 4 
 3 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index ce19f1d..b886d9d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1123,6 +1123,8 @@ static int __maybe_unused dpu_runtime_resume(struct 
device *dev)
 
 static const struct dev_pm_ops dpu_pm_ops = {
SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL)
+   SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+   pm_runtime_force_resume)
 };
 
 static const struct of_device_id dpu_dt_match[] = {
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index 55ea4bc2..62704885 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -161,6 +161,8 @@ static int dsi_dev_remove(struct platform_device *pdev)
 
 static const struct dev_pm_ops dsi_pm_ops = {
SET_RUNTIME_PM_OPS(msm_dsi_runtime_suspend, msm_dsi_runtime_resume, 
NULL)
+   SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+   pm_runtime_force_resume)
 };
 
 static struct platform_driver dsi_driver = {
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 7d985f8..2b8c99c 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -1051,6 +1051,8 @@ static int msm_pm_suspend(struct device *dev)
return ret;
}
 
+   pm_runtime_force_suspend(dev);
+
return 0;
 }
 
@@ -1063,6 +1065,8 @@ static int msm_pm_resume(struct device *dev)
if (WARN_ON(!priv->pm_state))
return -ENOENT;
 
+   pm_runtime_force_resume(dev);
+
ret = drm_atomic_helper_resume(ddev, priv->pm_state);
if (!ret)
priv->pm_state = NULL;
-- 
1.9.1

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[Freedreno] [PATCH] drm/msm/dpu: add support for clk and bw scaling for display

[Kalyan Thota]

This change adds support to scale src clk and bandwidth as
per composition requirements.

Interconnect registration for bw has been moved to mdp
device node from mdss to facilitate the scaling.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c  | 106 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |   5 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   4 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  37 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h|   4 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c   |   9 ++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c  |  82 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h  |   4 +
 8 files changed, 228 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 11f2beb..24874f6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -29,6 +29,73 @@ enum dpu_perf_mode {
DPU_PERF_MODE_MAX
 };
 
+/**
+ * @_dpu_core_perf_calc_bw() - to calculate BW per crtc
+ * @kms -  pointer to the dpu_kms
+ * @crtc - pointer to a crtc
+ * Return: returns aggregated BW for all planes in crtc.
+ */
+static u64 _dpu_core_perf_calc_bw(struct dpu_kms *kms,
+   struct drm_crtc *crtc)
+{
+   struct drm_plane *plane;
+   struct dpu_plane_state *pstate;
+   u64 crtc_plane_bw = 0;
+   u32 bw_factor;
+
+   drm_atomic_crtc_for_each_plane(plane, crtc) {
+   pstate = to_dpu_plane_state(plane->state);
+
+   if (!pstate)
+   continue;
+
+   crtc_plane_bw += pstate->plane_fetch_bw;
+   }
+
+   bw_factor = kms->catalog->perf.bw_inefficiency_factor;
+   if (bw_factor)
+   crtc_plane_bw = mult_frac(crtc_plane_bw, bw_factor, 100);
+
+   return crtc_plane_bw;
+}
+
+/**
+ * _dpu_core_perf_calc_clk() - to calculate clock per crtc
+ * @kms -  pointer to the dpu_kms
+ * @crtc - pointer to a crtc
+ * @state - pointer to a crtc state
+ * Return: returns max clk for all planes in crtc.
+ */
+static u64 _dpu_core_perf_calc_clk(struct dpu_kms *kms,
+   struct drm_crtc *crtc, struct drm_crtc_state *state)
+{
+   struct drm_plane *plane;
+   struct dpu_plane_state *pstate;
+   struct drm_display_mode *mode;
+   u64 crtc_clk;
+   u32 clk_factor;
+
+   mode = &state->adjusted_mode;
+
+   crtc_clk = mode->vtotal * mode->hdisplay * drm_mode_vrefresh(mode);
+
+   drm_atomic_crtc_for_each_plane(plane, crtc) {
+   pstate = to_dpu_plane_state(plane->state);
+
+   if (!pstate)
+   continue;
+
+   crtc_clk = max(pstate->plane_clk, crtc_clk);
+   }
+
+   clk_factor = kms->catalog->perf.clk_inefficiency_factor;
+   if (clk_factor)
+   crtc_clk = mult_frac(crtc_clk, clk_factor, 100);
+
+   return crtc_clk;
+}
+
+
 static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
 {
struct msm_drm_private *priv;
@@ -67,12 +134,7 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
dpu_cstate = to_dpu_crtc_state(state);
memset(perf, 0, sizeof(struct dpu_core_perf_params));
 
-   if (!dpu_cstate->bw_control) {
-   perf->bw_ctl = kms->catalog->perf.max_bw_high *
-   1000ULL;
-   perf->max_per_pipe_ib = perf->bw_ctl;
-   perf->core_clk_rate = kms->perf.max_core_clk_rate;
-   } else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
+   if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
perf->bw_ctl = 0;
perf->max_per_pipe_ib = 0;
perf->core_clk_rate = 0;
@@ -80,6 +142,10 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
perf->bw_ctl = kms->perf.fix_core_ab_vote;
perf->max_per_pipe_ib = kms->perf.fix_core_ib_vote;
perf->core_clk_rate = kms->perf.fix_core_clk_rate;
+   } else {
+   perf->bw_ctl = _dpu_core_perf_calc_bw(kms, crtc);
+   perf->max_per_pipe_ib = kms->catalog->perf.min_dram_ib;
+   perf->core_clk_rate = _dpu_core_perf_calc_clk(kms, crtc, state);
}
 
DPU_DEBUG(
@@ -132,11 +198,7 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
DPU_DEBUG("crtc:%d bw:%llu ctrl:%d\n",
tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl,
tmp_cstate->bw_control);
-   /*
-* For bw check only use the bw if the
-* atomic property has been already set
-*/
-   

[Freedreno] [PATCH] drm/msm/dpu: ensure device suspend happens during PM sleep

[Kalyan Thota]

"The PM core always increments the runtime usage counter
before calling the ->suspend() callback and decrements it
after calling the ->resume() callback"

DPU and DSI are managed as runtime devices. When
suspend is triggered, PM core adds a refcount on all the
devices and calls device suspend, since usage count is
already incremented, runtime suspend was not getting called
and it kept the clocks on which resulted in target not
entering into XO shutdown.

Add changes to force suspend on runtime devices during pm sleep.

Changes in v1:
 - Remove unnecessary checks in the function
_dpu_kms_disable_dpu (Rob Clark).

Changes in v2:
 - Avoid using suspend_late to reset the usagecount
   as suspend_late might not be called during suspend
   call failures (Doug).

Changes in v3:
 - Use force suspend instead of managing device usage_count
   via runtime put and get API's to trigger callbacks (Doug).

Changes in v4:
 - Check the return values of pm_runtime_force_suspend and
   pm_runtime_force_resume API's and pass appropriately (Doug).

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  2 ++
 drivers/gpu/drm/msm/dsi/dsi.c   |  2 ++
 drivers/gpu/drm/msm/msm_drv.c   | 14 +-
 3 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index ce19f1d..b886d9d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1123,6 +1123,8 @@ static int __maybe_unused dpu_runtime_resume(struct 
device *dev)
 
 static const struct dev_pm_ops dpu_pm_ops = {
SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL)
+   SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+   pm_runtime_force_resume)
 };
 
 static const struct of_device_id dpu_dt_match[] = {
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index 55ea4bc2..62704885 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -161,6 +161,8 @@ static int dsi_dev_remove(struct platform_device *pdev)
 
 static const struct dev_pm_ops dsi_pm_ops = {
SET_RUNTIME_PM_OPS(msm_dsi_runtime_suspend, msm_dsi_runtime_resume, 
NULL)
+   SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+   pm_runtime_force_resume)
 };
 
 static struct platform_driver dsi_driver = {
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 7d985f8..4b93fc1 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -1040,6 +1040,7 @@ static int msm_pm_suspend(struct device *dev)
 {
struct drm_device *ddev = dev_get_drvdata(dev);
struct msm_drm_private *priv = ddev->dev_private;
+   int ret, rc;
 
if (WARN_ON(priv->pm_state))
drm_atomic_state_put(priv->pm_state);
@@ -1051,7 +1052,14 @@ static int msm_pm_suspend(struct device *dev)
return ret;
}
 
-   return 0;
+   ret = pm_runtime_force_suspend(dev);
+   if (ret) {
+   rc = drm_atomic_helper_resume(ddev, priv->pm_state);
+   if (!rc)
+   priv->pm_state = NULL;
+   }
+
+   return ret;
 }
 
 static int msm_pm_resume(struct device *dev)
@@ -1063,6 +1071,10 @@ static int msm_pm_resume(struct device *dev)
if (WARN_ON(!priv->pm_state))
return -ENOENT;
 
+   ret = pm_runtime_force_resume(dev);
+   if (ret)
+   return ret;
+
ret = drm_atomic_helper_resume(ddev, priv->pm_state);
if (!ret)
priv->pm_state = NULL;
-- 
1.9.1

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[Freedreno] [PATCH] drm/msm/dpu: ensure device suspend happens during PM sleep

[Kalyan Thota]

"The PM core always increments the runtime usage counter
before calling the ->suspend() callback and decrements it
after calling the ->resume() callback"

DPU and DSI are managed as runtime devices. When
suspend is triggered, PM core adds a refcount on all the
devices and calls device suspend, since usage count is
already incremented, runtime suspend was not getting called
and it kept the clocks on which resulted in target not
entering into XO shutdown.

Add changes to force suspend on runtime devices during pm sleep.

Changes in v1:
 - Remove unnecessary checks in the function
_dpu_kms_disable_dpu (Rob Clark).

Changes in v2:
 - Avoid using suspend_late to reset the usagecount
   as suspend_late might not be called during suspend
   call failures (Doug).

Changes in v3:
 - Use force suspend instead of managing device usage_count
   via runtime put and get API's to trigger callbacks (Doug).

Changes in v4:
 - Check the return values of pm_runtime_force_suspend and
   pm_runtime_force_resume API's and pass appropriately (Doug).

Changes in v5:
 - With v4 patch, test cycle has uncovered issues in device resume.

   On bubs: cmd tx failures were seen as SW is sending panel off
   commands when the dsi resources are turned off.

   Upon suspend, DRM driver will issue a NULL composition to the
   dpu, followed by turning off all the HW blocks.

   v5 changes will serialize the NULL commit and resource unwinding
   by handling them under PM prepare and PM complete phases there by
   ensuring that clks are on when panel off commands are being
   processed.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  2 ++
 drivers/gpu/drm/msm/dsi/dsi.c   |  2 ++
 drivers/gpu/drm/msm/msm_drv.c   | 20 
 3 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index ce19f1d..b886d9d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1123,6 +1123,8 @@ static int __maybe_unused dpu_runtime_resume(struct 
device *dev)
 
 static const struct dev_pm_ops dpu_pm_ops = {
SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL)
+   SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+   pm_runtime_force_resume)
 };
 
 static const struct of_device_id dpu_dt_match[] = {
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index 55ea4bc2..62704885 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -161,6 +161,8 @@ static int dsi_dev_remove(struct platform_device *pdev)
 
 static const struct dev_pm_ops dsi_pm_ops = {
SET_RUNTIME_PM_OPS(msm_dsi_runtime_suspend, msm_dsi_runtime_resume, 
NULL)
+   SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+   pm_runtime_force_resume)
 };
 
 static struct platform_driver dsi_driver = {
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 7d985f8..47d492b 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -1036,7 +1036,7 @@ static int msm_ioctl_submitqueue_close(struct drm_device 
*dev, void *data,
 };
 
 #ifdef CONFIG_PM_SLEEP
-static int msm_pm_suspend(struct device *dev)
+static int msm_pm_prepare(struct device *dev)
 {
struct drm_device *ddev = dev_get_drvdata(dev);
struct msm_drm_private *priv = ddev->dev_private;
@@ -1054,18 +1054,28 @@ static int msm_pm_suspend(struct device *dev)
return 0;
 }
 
-static int msm_pm_resume(struct device *dev)
+static void msm_pm_complete(struct device *dev)
 {
struct drm_device *ddev = dev_get_drvdata(dev);
struct msm_drm_private *priv = ddev->dev_private;
int ret;
 
if (WARN_ON(!priv->pm_state))
-   return -ENOENT;
+   return;
 
ret = drm_atomic_helper_resume(ddev, priv->pm_state);
if (!ret)
priv->pm_state = NULL;
+}
+
+static int msm_pm_resume(struct device *dev)
+{
+   int ret;
+
+   /* unwind runtime_disable called by force suspend */
+   pm_runtime_enable(dev);
+
+   ret = pm_runtime_resume(dev);
 
return ret;
 }
@@ -1102,8 +1112,10 @@ static int msm_runtime_resume(struct device *dev)
 #endif
 
 static const struct dev_pm_ops msm_pm_ops = {
-   SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
+   SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, msm_pm_resume)
SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
+   .prepare = msm_pm_prepare,
+   .complete = msm_pm_complete,
 };
 
 /*
-- 
1.9.1

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[Freedreno] [PATCH v6] drm/msm/dpu: ensure device suspend happens during PM sleep

[Kalyan Thota]

"The PM core always increments the runtime usage counter
before calling the ->suspend() callback and decrements it
after calling the ->resume() callback"

DPU and DSI are managed as runtime devices. When
suspend is triggered, PM core adds a refcount on all the
devices and calls device suspend, since usage count is
already incremented, runtime suspend was not getting called
and it kept the clocks on which resulted in target not
entering into XO shutdown.

Add changes to force suspend on runtime devices during pm sleep.

Changes in v1:
 - Remove unnecessary checks in the function
_dpu_kms_disable_dpu (Rob Clark).

Changes in v2:
 - Avoid using suspend_late to reset the usagecount
   as suspend_late might not be called during suspend
   call failures (Doug).

Changes in v3:
 - Use force suspend instead of managing device usage_count
   via runtime put and get API's to trigger callbacks (Doug).

Changes in v4:
 - Check the return values of pm_runtime_force_suspend and
   pm_runtime_force_resume API's and pass appropriately (Doug).

Changes in v5:
 - With v4 patch, test cycle has uncovered issues in device resume.

   On bubs: cmd tx failures were seen as SW is sending panel off
   commands when the dsi resources are turned off.

   Upon suspend, DRM driver will issue a NULL composition to the
   dpu, followed by turning off all the HW blocks.

   v5 changes will serialize the NULL commit and resource unwinding
   by handling them under PM prepare and PM complete phases there by
   ensuring that clks are on when panel off commands are being
   processed.

Changes in v6:
- Use drm_mode_config_helper_suspend/resume() instead of legacy API
  drm_atomic_helper_suspend/resume() (Doug).

  Trigger runtime callbacks from the suspend/resume call to turn
  off the resources.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  2 +
 drivers/gpu/drm/msm/dsi/dsi.c   |  2 +
 drivers/gpu/drm/msm/msm_drv.c   | 67 -
 3 files changed, 37 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index ce19f1d..b886d9d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1123,6 +1123,8 @@ static int __maybe_unused dpu_runtime_resume(struct 
device *dev)
 
 static const struct dev_pm_ops dpu_pm_ops = {
SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL)
+   SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+   pm_runtime_force_resume)
 };
 
 static const struct of_device_id dpu_dt_match[] = {
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index 55ea4bc2..62704885 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -161,6 +161,8 @@ static int dsi_dev_remove(struct platform_device *pdev)
 
 static const struct dev_pm_ops dsi_pm_ops = {
SET_RUNTIME_PM_OPS(msm_dsi_runtime_suspend, msm_dsi_runtime_resume, 
NULL)
+   SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+   pm_runtime_force_resume)
 };
 
 static struct platform_driver dsi_driver = {
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 7d985f8..da42ff7 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -1035,75 +1035,74 @@ static int msm_ioctl_submitqueue_close(struct 
drm_device *dev, void *data,
.patchlevel = MSM_VERSION_PATCHLEVEL,
 };
 
-#ifdef CONFIG_PM_SLEEP
-static int msm_pm_suspend(struct device *dev)
+#ifdef CONFIG_PM
+static int msm_runtime_suspend(struct device *dev)
 {
struct drm_device *ddev = dev_get_drvdata(dev);
struct msm_drm_private *priv = ddev->dev_private;
+   struct msm_mdss *mdss = priv->mdss;
 
-   if (WARN_ON(priv->pm_state))
-   drm_atomic_state_put(priv->pm_state);
+   DBG("");
 
-   priv->pm_state = drm_atomic_helper_suspend(ddev);
-   if (IS_ERR(priv->pm_state)) {
-   int ret = PTR_ERR(priv->pm_state);
-   DRM_ERROR("Failed to suspend dpu, %d\n", ret);
-   return ret;
-   }
+   if (mdss && mdss->funcs)
+   return mdss->funcs->disable(mdss);
 
return 0;
 }
 
-static int msm_pm_resume(struct device *dev)
+static int msm_runtime_resume(struct device *dev)
 {
struct drm_device *ddev = dev_get_drvdata(dev);
struct msm_drm_private *priv = ddev->dev_private;
-   int ret;
+   struct msm_mdss *mdss = priv->mdss;
 
-   if (WARN_ON(!priv->pm_state))
-   return -ENOENT;
+   DBG("");
 
-   ret = drm_atomic_helper_resume(ddev, priv->pm_state);
-   if (!ret)
-   priv->pm_state = NULL;
+   if (mdss && mdss->funcs)
+   return mdss->

[Freedreno] [v8] drm/msm/dpu: ensure device suspend happens during PM sleep

[Kalyan Thota]

"The PM core always increments the runtime usage counter
before calling the ->suspend() callback and decrements it
after calling the ->resume() callback"

DPU and DSI are managed as runtime devices. When
suspend is triggered, PM core adds a refcount on all the
devices and calls device suspend, since usage count is
already incremented, runtime suspend was not getting called
and it kept the clocks on which resulted in target not
entering into XO shutdown.

Add changes to force suspend on runtime devices during pm sleep.

Changes in v1:
 - Remove unnecessary checks in the function
_dpu_kms_disable_dpu (Rob Clark).

Changes in v2:
 - Avoid using suspend_late to reset the usagecount
   as suspend_late might not be called during suspend
   call failures (Doug).

Changes in v3:
 - Use force suspend instead of managing device usage_count
   via runtime put and get API's to trigger callbacks (Doug).

Changes in v4:
 - Check the return values of pm_runtime_force_suspend and
   pm_runtime_force_resume API's and pass appropriately (Doug).

Changes in v5:
 - With v4 patch, test cycle has uncovered issues in device resume.

   On bubs: cmd tx failures were seen as SW is sending panel off
   commands when the dsi resources are turned off.

   Upon suspend, DRM driver will issue a NULL composition to the
   dpu, followed by turning off all the HW blocks.

   v5 changes will serialize the NULL commit and resource unwinding
   by handling them under PM prepare and PM complete phases there by
   ensuring that clks are on when panel off commands are being
   processed.

Changes in v6:
- Use drm_mode_config_helper_suspend/resume() instead of legacy API
  drm_atomic_helper_suspend/resume() (Doug).

  Trigger runtime callbacks from the suspend/resume call to turn
  off the resources.

Changes in v7:
- Add "__maybe_unused" to the functions to avoid compilation
  failures. Cleanup unnecessary configs (Doug).

Signed-off-by: Kalyan Thota 
Reviewed-by: Douglas Anderson 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  2 +
 drivers/gpu/drm/msm/dsi/dsi.c   |  2 +
 drivers/gpu/drm/msm/msm_drv.c   | 67 +++--
 3 files changed, 35 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index a5da7aa..dcf5b9a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1150,6 +1150,8 @@ static int __maybe_unused dpu_runtime_resume(struct 
device *dev)
 
 static const struct dev_pm_ops dpu_pm_ops = {
SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL)
+   SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+   pm_runtime_force_resume)
 };
 
 static const struct of_device_id dpu_dt_match[] = {
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index 55ea4bc2..62704885 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -161,6 +161,8 @@ static int dsi_dev_remove(struct platform_device *pdev)
 
 static const struct dev_pm_ops dsi_pm_ops = {
SET_RUNTIME_PM_OPS(msm_dsi_runtime_suspend, msm_dsi_runtime_resume, 
NULL)
+   SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+   pm_runtime_force_resume)
 };
 
 static struct platform_driver dsi_driver = {
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index f6ce40b..6d294c8 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -1039,75 +1039,70 @@ static int msm_ioctl_submitqueue_close(struct 
drm_device *dev, void *data,
.patchlevel = MSM_VERSION_PATCHLEVEL,
 };
 
-#ifdef CONFIG_PM_SLEEP
-static int msm_pm_suspend(struct device *dev)
+static int __maybe_unused msm_runtime_suspend(struct device *dev)
 {
struct drm_device *ddev = dev_get_drvdata(dev);
struct msm_drm_private *priv = ddev->dev_private;
+   struct msm_mdss *mdss = priv->mdss;
 
-   if (WARN_ON(priv->pm_state))
-   drm_atomic_state_put(priv->pm_state);
+   DBG("");
 
-   priv->pm_state = drm_atomic_helper_suspend(ddev);
-   if (IS_ERR(priv->pm_state)) {
-   int ret = PTR_ERR(priv->pm_state);
-   DRM_ERROR("Failed to suspend dpu, %d\n", ret);
-   return ret;
-   }
+   if (mdss && mdss->funcs)
+   return mdss->funcs->disable(mdss);
 
return 0;
 }
 
-static int msm_pm_resume(struct device *dev)
+static int __maybe_unused msm_runtime_resume(struct device *dev)
 {
struct drm_device *ddev = dev_get_drvdata(dev);
struct msm_drm_private *priv = ddev->dev_private;
-   int ret;
+   struct msm_mdss *mdss = priv->mdss;
 
-   if (WARN_ON(!priv->pm_state))
-   return -ENOENT;
+   DBG("");
 
-   ret = drm_atom

[Freedreno] [v1] drm/msm/dpu: add support for clk and bw scaling for display

[Kalyan Thota]

This change adds support to scale src clk and bandwidth as
per composition requirements.

Interconnect registration for bw has been moved to mdp
device node from mdss to facilitate the scaling.

Changes in v1:
 - Address armv7 compilation issues with the patch (Rob)

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c  | 109 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |   5 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   4 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  37 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h|   4 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c   |   9 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c  |  84 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h  |   4 +
 8 files changed, 233 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 7c230f7..e52bc44 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -29,6 +29,74 @@ enum dpu_perf_mode {
DPU_PERF_MODE_MAX
 };
 
+/**
+ * @_dpu_core_perf_calc_bw() - to calculate BW per crtc
+ * @kms -  pointer to the dpu_kms
+ * @crtc - pointer to a crtc
+ * Return: returns aggregated BW for all planes in crtc.
+ */
+static u64 _dpu_core_perf_calc_bw(struct dpu_kms *kms,
+   struct drm_crtc *crtc)
+{
+   struct drm_plane *plane;
+   struct dpu_plane_state *pstate;
+   u64 crtc_plane_bw = 0;
+   u32 bw_factor;
+
+   drm_atomic_crtc_for_each_plane(plane, crtc) {
+   pstate = to_dpu_plane_state(plane->state);
+   if (!pstate)
+   continue;
+
+   crtc_plane_bw += pstate->plane_fetch_bw;
+   }
+
+   bw_factor = kms->catalog->perf.bw_inefficiency_factor;
+   if (bw_factor) {
+   crtc_plane_bw *= bw_factor;
+   do_div(crtc_plane_bw, 100);
+   }
+
+   return crtc_plane_bw;
+}
+
+/**
+ * _dpu_core_perf_calc_clk() - to calculate clock per crtc
+ * @kms -  pointer to the dpu_kms
+ * @crtc - pointer to a crtc
+ * @state - pointer to a crtc state
+ * Return: returns max clk for all planes in crtc.
+ */
+static u64 _dpu_core_perf_calc_clk(struct dpu_kms *kms,
+   struct drm_crtc *crtc, struct drm_crtc_state *state)
+{
+   struct drm_plane *plane;
+   struct dpu_plane_state *pstate;
+   struct drm_display_mode *mode;
+   u64 crtc_clk;
+   u32 clk_factor;
+
+   mode = &state->adjusted_mode;
+
+   crtc_clk = mode->vtotal * mode->hdisplay * drm_mode_vrefresh(mode);
+
+   drm_atomic_crtc_for_each_plane(plane, crtc) {
+   pstate = to_dpu_plane_state(plane->state);
+   if (!pstate)
+   continue;
+
+   crtc_clk = max(pstate->plane_clk, crtc_clk);
+   }
+
+   clk_factor = kms->catalog->perf.clk_inefficiency_factor;
+   if (clk_factor) {
+   crtc_clk *= clk_factor;
+   do_div(crtc_clk, 100);
+   }
+
+   return crtc_clk;
+}
+
 static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
 {
struct msm_drm_private *priv;
@@ -51,12 +119,7 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
dpu_cstate = to_dpu_crtc_state(state);
memset(perf, 0, sizeof(struct dpu_core_perf_params));
 
-   if (!dpu_cstate->bw_control) {
-   perf->bw_ctl = kms->catalog->perf.max_bw_high *
-   1000ULL;
-   perf->max_per_pipe_ib = perf->bw_ctl;
-   perf->core_clk_rate = kms->perf.max_core_clk_rate;
-   } else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
+   if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
perf->bw_ctl = 0;
perf->max_per_pipe_ib = 0;
perf->core_clk_rate = 0;
@@ -64,6 +127,10 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
perf->bw_ctl = kms->perf.fix_core_ab_vote;
perf->max_per_pipe_ib = kms->perf.fix_core_ib_vote;
perf->core_clk_rate = kms->perf.fix_core_clk_rate;
+   } else {
+   perf->bw_ctl = _dpu_core_perf_calc_bw(kms, crtc);
+   perf->max_per_pipe_ib = kms->catalog->perf.min_dram_ib;
+   perf->core_clk_rate = _dpu_core_perf_calc_clk(kms, crtc, state);
}
 
DPU_DEBUG(
@@ -115,11 +182,7 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
DPU_DEBUG("crtc:%d bw:%llu ctrl:%d\n",
tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl,
tmp_cstate->bw_control);
-   /*
-* For bw check only use the 

[Freedreno] [PATCH] drm/msm/dpu: add support for dither block in display

[Kalyan Thota]

This change enables dither block for primary interface
in display.

Enabled for 6bpc in the current version.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 45 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 66 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 28 +++
 3 files changed, 130 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 63976dc..26e870a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -208,6 +208,42 @@ struct dpu_encoder_virt {
 
 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
 
+static u32 dither_matrix[DITHER_MATRIX_SZ] = {
+   15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
+};
+
+static void _dpu_encoder_setup_dither(struct dpu_encoder_phys *phys)
+{
+   struct dpu_hw_dither_cfg dither_cfg = { 0 };
+   struct drm_display_info *info;
+
+   if (!phys || !phys->connector || !phys->hw_pp ||
+   !phys->hw_pp->ops.setup_dither)
+   return;
+
+   info = &phys->connector->display_info;
+   if (!info)
+   return;
+
+   switch (phys->connector->display_info.bpc) {
+   case 6:
+   dither_cfg.c0_bitdepth = 6;
+   dither_cfg.c1_bitdepth = 6;
+   dither_cfg.c2_bitdepth = 6;
+   dither_cfg.c3_bitdepth = 6;
+   dither_cfg.temporal_en = 0;
+   break;
+   default:
+   phys->hw_pp->ops.setup_dither(phys->hw_pp, NULL);
+   return;
+   }
+
+   memcpy(&dither_cfg.matrix, dither_matrix,
+   sizeof(u32) * DITHER_MATRIX_SZ);
+
+   phys->hw_pp->ops.setup_dither(phys->hw_pp, &dither_cfg);
+}
+
 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
enum dpu_intr_idx intr_idx)
 {
@@ -1082,6 +1118,7 @@ static void _dpu_encoder_virt_enable_helper(struct 
drm_encoder *drm_enc)
struct dpu_encoder_virt *dpu_enc = NULL;
struct msm_drm_private *priv;
struct dpu_kms *dpu_kms;
+   int i;
 
if (!drm_enc || !drm_enc->dev) {
DPU_ERROR("invalid parameters\n");
@@ -1104,6 +1141,14 @@ static void _dpu_encoder_virt_enable_helper(struct 
drm_encoder *drm_enc)
dpu_kms->catalog);
 
_dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
+
+   if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
+   for (i = 0; i < dpu_enc->num_phys_encs; i++) {
+   struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
+
+   _dpu_encoder_setup_dither(phys);
+   }
+   }
 }
 
 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index d110a40..cf7603d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -28,6 +28,16 @@
 #define PP_FBC_BUDGET_CTL   0x038
 #define PP_FBC_LOSSY_MODE   0x03C
 
+#define PP_DITHER_EN   0x000
+#define PP_DITHER_BITDEPTH 0x004
+#define PP_DITHER_MATRIX   0x008
+
+#define DITHER_DEPTH_MAP_INDEX 9
+
+static u32 dither_depth_map[DITHER_DEPTH_MAP_INDEX] = {
+   0, 0, 0, 0, 0, 0, 0, 1, 2
+};
+
 static const struct dpu_pingpong_cfg *_pingpong_offset(enum dpu_pingpong pp,
const struct dpu_mdss_cfg *m,
void __iomem *addr,
@@ -49,6 +59,40 @@ static const struct dpu_pingpong_cfg *_pingpong_offset(enum 
dpu_pingpong pp,
return ERR_PTR(-EINVAL);
 }
 
+static void dpu_hw_pp_setup_dither(struct dpu_hw_pingpong *pp,
+   struct dpu_hw_dither_cfg *cfg)
+{
+   struct dpu_hw_blk_reg_map *c;
+   u32 i, base, data = 0;
+
+   if (!pp)
+   return;
+
+   c = &pp->hw;
+   base = pp->caps->sblk->dither.base;
+   if (!cfg) {
+   DPU_REG_WRITE(c, base + PP_DITHER_EN, 0);
+   return;
+   }
+
+   data = dither_depth_map[cfg->c0_bitdepth] & REG_MASK(2);
+   data |= (dither_depth_map[cfg->c1_bitdepth] & REG_MASK(2)) << 2;
+   data |= (dither_depth_map[cfg->c2_bitdepth] & REG_MASK(2)) << 4;
+   data |= (dither_depth_map[cfg->c3_bitdepth] & REG_MASK(2)) << 6;
+   data |= (cfg->temporal_en) ? (1 << 8) : 0;
+
+   DPU_REG_WRITE(c, base + PP_DITHER_BITDEPTH, data);
+
+   for (i = 0; i < DITHER_MATRIX_SZ - 3; i += 4) {
+   data = (cfg->matrix[i] & REG_MASK(4)) |
+

[Freedreno] [v2] drm/msm/dpu: add support for dither block in display

[Kalyan Thota]

This change enables dither block for primary interface
in display.

Enabled for 6bpc in the current version.

Changes in v1:
 - Remove redundant error checks (Rob).

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 39 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 63 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 28 +++
 3 files changed, 121 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 63976dc..14df5ac 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -208,6 +208,36 @@ struct dpu_encoder_virt {
 
 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
 
+static u32 dither_matrix[DITHER_MATRIX_SZ] = {
+   15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
+};
+
+static void _dpu_encoder_setup_dither(struct dpu_encoder_phys *phys)
+{
+   struct dpu_hw_dither_cfg dither_cfg = { 0 };
+
+   if (!phys->hw_pp || !phys->hw_pp->ops.setup_dither)
+   return;
+
+   switch (phys->connector->display_info.bpc) {
+   case 6:
+   dither_cfg.c0_bitdepth = 6;
+   dither_cfg.c1_bitdepth = 6;
+   dither_cfg.c2_bitdepth = 6;
+   dither_cfg.c3_bitdepth = 6;
+   dither_cfg.temporal_en = 0;
+   break;
+   default:
+   phys->hw_pp->ops.setup_dither(phys->hw_pp, NULL);
+   return;
+   }
+
+   memcpy(&dither_cfg.matrix, dither_matrix,
+   sizeof(u32) * DITHER_MATRIX_SZ);
+
+   phys->hw_pp->ops.setup_dither(phys->hw_pp, &dither_cfg);
+}
+
 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
enum dpu_intr_idx intr_idx)
 {
@@ -1082,6 +1112,7 @@ static void _dpu_encoder_virt_enable_helper(struct 
drm_encoder *drm_enc)
struct dpu_encoder_virt *dpu_enc = NULL;
struct msm_drm_private *priv;
struct dpu_kms *dpu_kms;
+   int i;
 
if (!drm_enc || !drm_enc->dev) {
DPU_ERROR("invalid parameters\n");
@@ -1104,6 +1135,14 @@ static void _dpu_encoder_virt_enable_helper(struct 
drm_encoder *drm_enc)
dpu_kms->catalog);
 
_dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
+
+   if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
+   for (i = 0; i < dpu_enc->num_phys_encs; i++) {
+   struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
+
+   _dpu_encoder_setup_dither(phys);
+   }
+   }
 }
 
 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index d110a40..7411ab6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -28,6 +28,16 @@
 #define PP_FBC_BUDGET_CTL   0x038
 #define PP_FBC_LOSSY_MODE   0x03C
 
+#define PP_DITHER_EN   0x000
+#define PP_DITHER_BITDEPTH 0x004
+#define PP_DITHER_MATRIX   0x008
+
+#define DITHER_DEPTH_MAP_INDEX 9
+
+static u32 dither_depth_map[DITHER_DEPTH_MAP_INDEX] = {
+   0, 0, 0, 0, 0, 0, 0, 1, 2
+};
+
 static const struct dpu_pingpong_cfg *_pingpong_offset(enum dpu_pingpong pp,
const struct dpu_mdss_cfg *m,
void __iomem *addr,
@@ -49,6 +59,37 @@ static const struct dpu_pingpong_cfg *_pingpong_offset(enum 
dpu_pingpong pp,
return ERR_PTR(-EINVAL);
 }
 
+static void dpu_hw_pp_setup_dither(struct dpu_hw_pingpong *pp,
+   struct dpu_hw_dither_cfg *cfg)
+{
+   struct dpu_hw_blk_reg_map *c;
+   u32 i, base, data = 0;
+
+   c = &pp->hw;
+   base = pp->caps->sblk->dither.base;
+   if (!cfg) {
+   DPU_REG_WRITE(c, base + PP_DITHER_EN, 0);
+   return;
+   }
+
+   data = dither_depth_map[cfg->c0_bitdepth] & REG_MASK(2);
+   data |= (dither_depth_map[cfg->c1_bitdepth] & REG_MASK(2)) << 2;
+   data |= (dither_depth_map[cfg->c2_bitdepth] & REG_MASK(2)) << 4;
+   data |= (dither_depth_map[cfg->c3_bitdepth] & REG_MASK(2)) << 6;
+   data |= (cfg->temporal_en) ? (1 << 8) : 0;
+
+   DPU_REG_WRITE(c, base + PP_DITHER_BITDEPTH, data);
+
+   for (i = 0; i < DITHER_MATRIX_SZ - 3; i += 4) {
+   data = (cfg->matrix[i] & REG_MASK(4)) |
+   ((cfg->matrix[i + 1] & REG_MASK(4)) << 4) |
+   ((cfg->matrix[i + 2] & REG_MASK(4)) << 8) |
+   ((cfg-

[Freedreno] [v1] drm/msm/dpu: enumerate second cursor pipe for external interface

[Kalyan Thota]

Setup an RGB HW pipe as cursor which can be used on
secondary interface.

For SC7180 2 HW pipes are enumerated as cursors
1 - primary interface
2 - secondary interface

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 8f2357d..23061fd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -117,10 +117,10 @@
.reg_off = 0x2AC, .bit_off = 0},
.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
.reg_off = 0x2AC, .bit_off = 8},
-   .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
-   .reg_off = 0x2B4, .bit_off = 8},
.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
-   .reg_off = 0x2BC, .bit_off = 8},
+   .reg_off = 0x2B4, .bit_off = 8},
+   .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+   .reg_off = 0x2C4, .bit_off = 8},
},
 };
 
@@ -272,10 +272,10 @@
sc7180_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
-   SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_SDM845_MASK,
-   sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
+   SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_CURSOR_SDM845_MASK,
+   sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_SDM845_MASK,
-   sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
+   sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
 };
 
 /*
-- 
1.9.1

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[Freedreno] [PATCH 2/3] arm64: dts: sc7180: add bus clock to mdp node for sc7180 target

[Kalyan Thota]

From: Krishna Manikandan 

Move the bus clock to mdp device node,in order
to facilitate bus band width scaling on sc7180
target.

The parent device MDSS will not vote for bus bw,
instead the vote will be triggered by mdp device
node. Since a minimum vote is required to turn
on bus clock, move the clock node to mdp device
from where the votes are requested.

This patch has dependency on the below series
https://patchwork.kernel.org/patch/11468783/

Signed-off-by: Krishna Manikandan 
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi 
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 4f2c0d1..31fed6d 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1510,10 +1510,9 @@
power-domains = <&dispcc MDSS_GDSC>;
 
clocks = <&gcc GCC_DISP_AHB_CLK>,
-<&gcc GCC_DISP_HF_AXI_CLK>,
 <&dispcc DISP_CC_MDSS_AHB_CLK>,
 <&dispcc DISP_CC_MDSS_MDP_CLK>;
-   clock-names = "iface", "bus", "ahb", "core";
+   clock-names = "iface", "ahb", "core";
 
assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
assigned-clock-rates = <3>;
@@ -1539,12 +1538,13 @@
  <0 0x0aeb 0 0x2008>;
reg-names = "mdp", "vbif";
 
-   clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+   clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+<&dispcc DISP_CC_MDSS_AHB_CLK>,
 <&dispcc DISP_CC_MDSS_ROT_CLK>,
 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
 <&dispcc DISP_CC_MDSS_MDP_CLK>,
 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
-   clock-names = "iface", "rot", "lut", "core",
+   clock-names = "bus", "iface", "rot", "lut", 
"core",
  "vsync";
assigned-clocks = <&dispcc 
DISP_CC_MDSS_MDP_CLK>,
  <&dispcc 
DISP_CC_MDSS_VSYNC_CLK>;
-- 
1.9.1

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[Freedreno] [PATCH 3/3] drm/msm/dpu: add support for clk and bw scaling for display

[Kalyan Thota]

This change adds support to scale src clk and bandwidth as
per composition requirements.

Interconnect registration for bw has been moved to mdp
device node from mdss to facilitate the scaling.

Changes in v1:
 - Address armv7 compilation issues with the patch (Rob)

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c  | 109 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |   5 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   4 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  37 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h|   4 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c   |   9 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c  |  84 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h  |   4 +
 8 files changed, 233 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 7c230f7..e52bc44 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -29,6 +29,74 @@ enum dpu_perf_mode {
DPU_PERF_MODE_MAX
 };
 
+/**
+ * @_dpu_core_perf_calc_bw() - to calculate BW per crtc
+ * @kms -  pointer to the dpu_kms
+ * @crtc - pointer to a crtc
+ * Return: returns aggregated BW for all planes in crtc.
+ */
+static u64 _dpu_core_perf_calc_bw(struct dpu_kms *kms,
+   struct drm_crtc *crtc)
+{
+   struct drm_plane *plane;
+   struct dpu_plane_state *pstate;
+   u64 crtc_plane_bw = 0;
+   u32 bw_factor;
+
+   drm_atomic_crtc_for_each_plane(plane, crtc) {
+   pstate = to_dpu_plane_state(plane->state);
+   if (!pstate)
+   continue;
+
+   crtc_plane_bw += pstate->plane_fetch_bw;
+   }
+
+   bw_factor = kms->catalog->perf.bw_inefficiency_factor;
+   if (bw_factor) {
+   crtc_plane_bw *= bw_factor;
+   do_div(crtc_plane_bw, 100);
+   }
+
+   return crtc_plane_bw;
+}
+
+/**
+ * _dpu_core_perf_calc_clk() - to calculate clock per crtc
+ * @kms -  pointer to the dpu_kms
+ * @crtc - pointer to a crtc
+ * @state - pointer to a crtc state
+ * Return: returns max clk for all planes in crtc.
+ */
+static u64 _dpu_core_perf_calc_clk(struct dpu_kms *kms,
+   struct drm_crtc *crtc, struct drm_crtc_state *state)
+{
+   struct drm_plane *plane;
+   struct dpu_plane_state *pstate;
+   struct drm_display_mode *mode;
+   u64 crtc_clk;
+   u32 clk_factor;
+
+   mode = &state->adjusted_mode;
+
+   crtc_clk = mode->vtotal * mode->hdisplay * drm_mode_vrefresh(mode);
+
+   drm_atomic_crtc_for_each_plane(plane, crtc) {
+   pstate = to_dpu_plane_state(plane->state);
+   if (!pstate)
+   continue;
+
+   crtc_clk = max(pstate->plane_clk, crtc_clk);
+   }
+
+   clk_factor = kms->catalog->perf.clk_inefficiency_factor;
+   if (clk_factor) {
+   crtc_clk *= clk_factor;
+   do_div(crtc_clk, 100);
+   }
+
+   return crtc_clk;
+}
+
 static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
 {
struct msm_drm_private *priv;
@@ -51,12 +119,7 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
dpu_cstate = to_dpu_crtc_state(state);
memset(perf, 0, sizeof(struct dpu_core_perf_params));
 
-   if (!dpu_cstate->bw_control) {
-   perf->bw_ctl = kms->catalog->perf.max_bw_high *
-   1000ULL;
-   perf->max_per_pipe_ib = perf->bw_ctl;
-   perf->core_clk_rate = kms->perf.max_core_clk_rate;
-   } else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
+   if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) {
perf->bw_ctl = 0;
perf->max_per_pipe_ib = 0;
perf->core_clk_rate = 0;
@@ -64,6 +127,10 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
perf->bw_ctl = kms->perf.fix_core_ab_vote;
perf->max_per_pipe_ib = kms->perf.fix_core_ib_vote;
perf->core_clk_rate = kms->perf.fix_core_clk_rate;
+   } else {
+   perf->bw_ctl = _dpu_core_perf_calc_bw(kms, crtc);
+   perf->max_per_pipe_ib = kms->catalog->perf.min_dram_ib;
+   perf->core_clk_rate = _dpu_core_perf_calc_clk(kms, crtc, state);
}
 
DPU_DEBUG(
@@ -115,11 +182,7 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
DPU_DEBUG("crtc:%d bw:%llu ctrl:%d\n",
tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl,
tmp_cstate->bw_control);
-   /*
-* For bw check only use the 

[Freedreno] [PATCH 1/3] arm64: dts: sc7180: add interconnect bindings for display

[Kalyan Thota]

From: Krishna Manikandan 

This change adds the interconnect bindings to the
MDSS node. This will establish Display to DDR path
for bus bandwidth voting.

Changes in v2:
- Change in commit message(Matthias Kaehlcke)

Changes in v3:
- Updated commit message to include
  reviewer's name in v2

Signed-off-by: Krishna Manikandan 
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi 
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 998f101..4f2c0d1 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1522,6 +1522,9 @@
interrupt-controller;
#interrupt-cells = <1>;
 
+   interconnects = <&mmss_noc MASTER_MDP0 &mc_virt 
SLAVE_EBI1>;
+   interconnect-names = "mdp0-mem";
+
iommus = <&apps_smmu 0x800 0x2>;
 
#address-cells = <2>;
-- 
1.9.1

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[Freedreno] [v1] drm/msm/dpu: Fix scale params in plane validation

[Kalyan Thota]

Plane validation uses an API drm_calc_scale which will
return src/dst value as a scale ratio.

when viewing the range on a scale the values should fall in as

Upscale ratio < Unity scale < Downscale ratio for src/dst formula

Fix the min and max scale ratios to suit the API accordingly.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 6379fe1..e46dcb9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -946,9 +946,9 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
crtc_state = drm_atomic_get_new_crtc_state(state->state,
   state->crtc);
 
-   min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxdwnscale);
+   min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxupscale);
ret = drm_atomic_helper_check_plane_state(state, crtc_state, min_scale,
- pdpu->pipe_sblk->maxupscale << 16,
+ pdpu->pipe_sblk->maxdwnscale << 16,
  true, true);
if (ret) {
DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret);
-- 
1.9.1

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[Freedreno] [v1] drm/msm/dpu: update reservations in commit path

[Kalyan Thota]

DPU resources reserved in the atomic_check path gets unwinded
during modeset operation before commit happens in a non seamless
transition.

Update the reservations in the commit path to avoid resource
failures. Secondly have dummy reservations in atomic_check path
so that we can gracefully fail the composition if resources are
not available.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 15 +++
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 63976dc..c6b8254 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -565,7 +565,7 @@ static int dpu_encoder_virt_atomic_check(
const struct drm_display_mode *mode;
struct drm_display_mode *adj_mode;
struct msm_display_topology topology;
-   struct dpu_global_state *global_state;
+   struct dpu_global_state tmp_resv_state;
int i = 0;
int ret = 0;
 
@@ -582,7 +582,7 @@ static int dpu_encoder_virt_atomic_check(
dpu_kms = to_dpu_kms(priv->kms);
mode = &crtc_state->mode;
adj_mode = &crtc_state->adjusted_mode;
-   global_state = dpu_kms_get_existing_global_state(dpu_kms);
+   memset(&tmp_resv_state, 0, sizeof(tmp_resv_state));
trace_dpu_enc_atomic_check(DRMID(drm_enc));
 
/*
@@ -621,7 +621,7 @@ static int dpu_encoder_virt_atomic_check(
 * info may not be available to complete reservation.
 */
if (drm_atomic_crtc_needs_modeset(crtc_state)) {
-   ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
+   ret = dpu_rm_reserve(&dpu_kms->rm, &tmp_resv_state,
drm_enc, crtc_state, topology);
}
}
@@ -966,7 +966,7 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder 
*drm_enc,
struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
int num_lm, num_ctl, num_pp, num_dspp;
-   int i, j;
+   int i, j, rc;
 
if (!drm_enc) {
DPU_ERROR("invalid encoder\n");
@@ -1006,6 +1006,13 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder 
*drm_enc,
 
topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
 
+   rc = dpu_rm_reserve(&dpu_kms->rm, global_state, drm_enc,
+   drm_crtc->state, topology);
+   if (rc) {
+   DPU_ERROR_ENC(dpu_enc, "Failed to reserve resources\n");
+   return;
+   }
+
/* Query resource that have been reserved in atomic check step. */
num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp,
-- 
1.9.1

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[Freedreno] [v1] drm/msm/dpu: Fix reservation failures in modeset

[Kalyan Thota]

In TEST_ONLY commit, rm global_state will duplicate the
object and request for new reservations, once they pass
then the new state will be swapped with the old and will
be available for the Atomic Commit.

This patch fixes some of missing links in the resource
reservation sequence mentioned above.

1) Creation of a duplicate state in test_only commit (Rob)
2) Allow resource release only during crtc_active false.

For #2
In a modeset operation, swap state happens well before disable.
Hence clearing reservations in disable will cause failures
in modeset enable.

Sequence:
Swap state --> old, new
modeset disables --> virt disable
modeset enable --> virt modeset

Allow reservations to be cleared only when crtc active is false
as in that case there wont be any modeset enable after disable.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 63976dc..b85a576 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -582,7 +582,7 @@ static int dpu_encoder_virt_atomic_check(
dpu_kms = to_dpu_kms(priv->kms);
mode = &crtc_state->mode;
adj_mode = &crtc_state->adjusted_mode;
-   global_state = dpu_kms_get_existing_global_state(dpu_kms);
+   global_state = dpu_kms_get_global_state(crtc_state->state);
trace_dpu_enc_atomic_check(DRMID(drm_enc));
 
/*
@@ -1172,6 +1172,7 @@ static void dpu_encoder_virt_disable(struct drm_encoder 
*drm_enc)
struct msm_drm_private *priv;
struct dpu_kms *dpu_kms;
struct dpu_global_state *global_state;
+   struct drm_crtc_state *crtc_state;
int i = 0;
 
if (!drm_enc) {
@@ -1191,6 +1192,7 @@ static void dpu_encoder_virt_disable(struct drm_encoder 
*drm_enc)
priv = drm_enc->dev->dev_private;
dpu_kms = to_dpu_kms(priv->kms);
global_state = dpu_kms_get_existing_global_state(dpu_kms);
+   crtc_state = drm_enc->crtc->state;
 
trace_dpu_enc_disable(DRMID(drm_enc));
 
@@ -1220,7 +1222,8 @@ static void dpu_encoder_virt_disable(struct drm_encoder 
*drm_enc)
 
DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
 
-   dpu_rm_release(global_state, drm_enc);
+   if (crtc_state->active_changed && !crtc_state->active)
+   dpu_rm_release(global_state, drm_enc);
 
mutex_unlock(&dpu_enc->enc_lock);
 }
-- 
1.9.1

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[Freedreno] [v2] drm/msm/dpu: Fix reservation failures in modeset

[Kalyan Thota]

In TEST_ONLY commit, rm global_state will duplicate the
object and request for new reservations, once they pass
then the new state will be swapped with the old and will
be available for the Atomic Commit.

This patch fixes some of missing links in the resource
reservation sequence mentioned above.

1) Creation of duplicate state in test_only commit (Rob)
2) Allocate and release the resources on every modeset.
3) Avoid allocation only when active is false.

In a modeset operation, swap state happens well before
disable. Hence clearing reservations in disable will
cause failures in modeset enable.

Allow reservations to be cleared/allocated before swap,
such that only newly committed resources are pushed to HW.

Changes in v1:
 - Move the rm release to atomic_check.
 - Ensure resource allocation and free happens when active
   is not changed i.e only when mode is changed.(Rob)

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 17 -
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 63976dc..50a98d1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -582,7 +582,7 @@ static int dpu_encoder_virt_atomic_check(
dpu_kms = to_dpu_kms(priv->kms);
mode = &crtc_state->mode;
adj_mode = &crtc_state->adjusted_mode;
-   global_state = dpu_kms_get_existing_global_state(dpu_kms);
+   global_state = dpu_kms_get_global_state(crtc_state->state);
trace_dpu_enc_atomic_check(DRMID(drm_enc));
 
/*
@@ -617,12 +617,15 @@ static int dpu_encoder_virt_atomic_check(
/* Reserve dynamic resources now. */
if (!ret) {
/*
-* Avoid reserving resources when mode set is pending. Topology
-* info may not be available to complete reservation.
+* Release and Allocate resources on every modeset
+* Dont allocate when active is false.
 */
if (drm_atomic_crtc_needs_modeset(crtc_state)) {
-   ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
-   drm_enc, crtc_state, topology);
+   dpu_rm_release(global_state, drm_enc);
+
+   if (!crtc_state->active_changed || crtc_state->active)
+   ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
+   drm_enc, crtc_state, topology);
}
}
 
@@ -1171,7 +1174,6 @@ static void dpu_encoder_virt_disable(struct drm_encoder 
*drm_enc)
struct dpu_encoder_virt *dpu_enc = NULL;
struct msm_drm_private *priv;
struct dpu_kms *dpu_kms;
-   struct dpu_global_state *global_state;
int i = 0;
 
if (!drm_enc) {
@@ -1190,7 +1192,6 @@ static void dpu_encoder_virt_disable(struct drm_encoder 
*drm_enc)
 
priv = drm_enc->dev->dev_private;
dpu_kms = to_dpu_kms(priv->kms);
-   global_state = dpu_kms_get_existing_global_state(dpu_kms);
 
trace_dpu_enc_disable(DRMID(drm_enc));
 
@@ -1220,8 +1221,6 @@ static void dpu_encoder_virt_disable(struct drm_encoder 
*drm_enc)
 
DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
 
-   dpu_rm_release(global_state, drm_enc);
-
mutex_unlock(&dpu_enc->enc_lock);
 }
 
-- 
1.9.1

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[Freedreno] [v3] drm/msm/dpu: Fix reservation failures in modeset

[Kalyan Thota]

In TEST_ONLY commit, rm global_state will duplicate the
object and request for new reservations, once they pass
then the new state will be swapped with the old and will
be available for the Atomic Commit.

This patch fixes some of missing links in the resource
reservation sequence mentioned above.

1) Creation of duplicate state in test_only commit (Rob)
2) Allocate and release the resources on every modeset.
3) Avoid allocation only when active is false.

In a modeset operation, swap state happens well before
disable. Hence clearing reservations in disable will
cause failures in modeset enable.

Allow reservations to be cleared/allocated before swap,
such that only newly committed resources are pushed to HW.

Changes in v1:
 - Move the rm release to atomic_check.
 - Ensure resource allocation and free happens when active
   is not changed i.e only when mode is changed.(Rob)

Changes in v2:
 - Handle dpu_kms_get_global_state API failure as it may
   return EDEADLK (swboyd).

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 20 +++-
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 63976dc..39e0b32 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -582,7 +582,10 @@ static int dpu_encoder_virt_atomic_check(
dpu_kms = to_dpu_kms(priv->kms);
mode = &crtc_state->mode;
adj_mode = &crtc_state->adjusted_mode;
-   global_state = dpu_kms_get_existing_global_state(dpu_kms);
+   global_state = dpu_kms_get_global_state(crtc_state->state);
+   if (IS_ERR(global_state))
+   return PTR_ERR(global_state);
+
trace_dpu_enc_atomic_check(DRMID(drm_enc));
 
/*
@@ -617,12 +620,15 @@ static int dpu_encoder_virt_atomic_check(
/* Reserve dynamic resources now. */
if (!ret) {
/*
-* Avoid reserving resources when mode set is pending. Topology
-* info may not be available to complete reservation.
+* Release and Allocate resources on every modeset
+* Dont allocate when active is false.
 */
if (drm_atomic_crtc_needs_modeset(crtc_state)) {
-   ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
-   drm_enc, crtc_state, topology);
+   dpu_rm_release(global_state, drm_enc);
+
+   if (!crtc_state->active_changed || crtc_state->active)
+   ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
+   drm_enc, crtc_state, topology);
}
}
 
@@ -1171,7 +1177,6 @@ static void dpu_encoder_virt_disable(struct drm_encoder 
*drm_enc)
struct dpu_encoder_virt *dpu_enc = NULL;
struct msm_drm_private *priv;
struct dpu_kms *dpu_kms;
-   struct dpu_global_state *global_state;
int i = 0;
 
if (!drm_enc) {
@@ -1190,7 +1195,6 @@ static void dpu_encoder_virt_disable(struct drm_encoder 
*drm_enc)
 
priv = drm_enc->dev->dev_private;
dpu_kms = to_dpu_kms(priv->kms);
-   global_state = dpu_kms_get_existing_global_state(dpu_kms);
 
trace_dpu_enc_disable(DRMID(drm_enc));
 
@@ -1220,8 +1224,6 @@ static void dpu_encoder_virt_disable(struct drm_encoder 
*drm_enc)
 
DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
 
-   dpu_rm_release(global_state, drm_enc);
-
mutex_unlock(&dpu_enc->enc_lock);
 }
 
-- 
1.9.1

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[Freedreno] [v1 1/2] drm/msm/disp/dpu1: add dspp support for sc7280

[Kalyan Thota]

Add destination side post processing hw block support in sc7280.

This hwblock enablement is necessary to support color features
like CT Matix (Ex: Night Light feature)

Change-Id: Iba7d5e1693b06cede2891f5b998466070a77c6ef
Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index a4fe77c..021eb2f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -928,7 +928,7 @@ static const struct dpu_lm_cfg sm8150_lm[] = {
 
 static const struct dpu_lm_cfg sc7280_lm[] = {
LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
-   &sc7180_lm_sblk, PINGPONG_0, 0, 0),
+   &sc7180_lm_sblk, PINGPONG_0, 0, DSPP_0),
LM_BLK("lm_2", LM_2, 0x46000, MIXER_SC7180_MASK,
&sc7180_lm_sblk, PINGPONG_2, LM_3, 0),
LM_BLK("lm_3", LM_3, 0x47000, MIXER_SC7180_MASK,
@@ -1792,6 +1792,8 @@ static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
.ctl = sc7280_ctl,
.sspp_count = ARRAY_SIZE(sc7280_sspp),
.sspp = sc7280_sspp,
+   .dspp_count = ARRAY_SIZE(sc7180_dspp),
+   .dspp = sc7180_dspp,
.mixer_count = ARRAY_SIZE(sc7280_lm),
.mixer = sc7280_lm,
.pingpong_count = ARRAY_SIZE(sc7280_pp),
-- 
2.7.4

[Freedreno] [v1 2/2] drm/msm/disp/dpu1: enable crtc color management based on encoder topology

[Kalyan Thota]

Crtc color management needs to be registered only for the crtc which has the
capability to handle it. Since topology decides which encoder will get the
dspp hw block, tie up the crtc and the encoder together 
(encoder->possible_crtcs)

Change-Id: If5a0f33547b6f527ca4b8fbb78424b141dbbd711
Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c|  8 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h|  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 20 
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h |  5 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 22 ++
 5 files changed, 46 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 7763558..2913acb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1511,7 +1511,7 @@ static const struct drm_crtc_helper_funcs 
dpu_crtc_helper_funcs = {
 
 /* initialize crtc */
 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
-   struct drm_plane *cursor)
+   struct drm_plane *cursor, unsigned int enc_mask)
 {
struct drm_crtc *crtc = NULL;
struct dpu_crtc *dpu_crtc = NULL;
@@ -1544,7 +1544,11 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, 
struct drm_plane *plane,
 
drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
 
-   drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
+   /* Register crtc color management if the encoder has dspp, use the
+* crtc to mark it as possible_crtcs for that encoder.
+*/
+   if(BIT(crtc->index) & enc_mask)
+   drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
 
/* save user friendly CRTC name for later */
snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index b8785c3..0a6458e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -269,7 +269,7 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc);
  * @Return: new crtc object or error
  */
 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
-  struct drm_plane *cursor);
+  struct drm_plane *cursor, unsigned int enc_mask);
 
 /**
  * dpu_crtc_register_custom_event - api for enabling/disabling crtc event
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index f2cb497..893ce68 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -13,6 +13,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #include "msm_drv.h"
 #include "dpu_kms.h"
@@ -511,13 +513,18 @@ void dpu_encoder_helper_split_config(
}
 }
 
-static struct msm_display_topology dpu_encoder_get_topology(
-   struct dpu_encoder_virt *dpu_enc,
+struct msm_display_topology dpu_encoder_get_topology(
+   struct drm_encoder *drm_enc,
struct dpu_kms *dpu_kms,
struct drm_display_mode *mode)
 {
struct msm_display_topology topology = {0};
+   struct dpu_encoder_virt *dpu_enc;
+   struct drm_bridge *bridge;
int i, intf_count = 0;
+   bool primary_display = false;
+
+   dpu_enc = to_dpu_encoder_virt(drm_enc);
 
for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
if (dpu_enc->phys_encs[i])
@@ -542,7 +549,12 @@ static struct msm_display_topology 
dpu_encoder_get_topology(
else
topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
 
-   if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
+   drm_for_each_bridge_in_chain(drm_enc, bridge) {
+   if (bridge->type != DRM_MODE_CONNECTOR_DisplayPort)
+   primary_display = true;
+   }
+
+   if (primary_display) {
if (dpu_kms->catalog->dspp &&
(dpu_kms->catalog->dspp_count >= topology.num_lm))
topology.num_dspp = topology.num_lm;
@@ -601,7 +613,7 @@ static int dpu_encoder_virt_atomic_check(
}
}
 
-   topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
+   topology = dpu_encoder_get_topology(drm_enc, dpu_kms, adj_mode);
 
/* Reserve dynamic resources now. */
if (!ret) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 1f39327..c4daf7c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -172,4 +172,9 @@ int dpu_en

Re: [Freedreno] [v1 2/2] drm/msm/disp/dpu1: enable crtc color management based on encoder topology

[Kalyan Thota]

Thanks for the comments, Dmitry. I haven't noticed mode->hdisplay being used. 
My idea was to run thru the topology and tie up the encoders with dspp to the 
CRTCs.
Since mode is available only in the commit, we cannot use the 
dpu_encoder_get_topology during initialization sequence.

The requirement here is that when we initialize the crtc, we need to enable 
drm_crtc_enable_color_mgmt only for the crtcs that support it. As I understand 
from Rob, chrome framework will check for the enablement in order to exercise 
the feature.

Do you have any ideas on how to handle this requirement ? Since we will reserve 
the dspp's only when a commit is issued, I guess it will be too late to enable 
color management by then.

@robdcl...@gmail.com
Is it okay, if we disable color management for all the crtcs during 
initialization and enable it when we have dspps available during modeset. Can 
we framework code query for the property before issuing a commit for the frame 
after modeset ?

Thanks,
Kalyan

> -Original Message-
> From: Dmitry Baryshkov 
> Sent: Tuesday, June 21, 2022 4:43 PM
> To: Kalyan Thota (QUIC) 
> Cc: y...@qualcomm.com; dri-de...@lists.freedesktop.org; linux-arm-
> m...@vger.kernel.org; freedreno@lists.freedesktop.org;
> devicet...@vger.kernel.org; linux-ker...@vger.kernel.org;
> robdcl...@gmail.com; diand...@chromium.org; swb...@chromium.org;
> Vinod Polimera (QUIC) ; Abhinav Kumar (QUIC)
> 
> Subject: Re: [v1 2/2] drm/msm/disp/dpu1: enable crtc color management based
> on encoder topology
> 
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
> 
> Generic comment: y...@qualcomm.com address bounces. Please remove it from
> the cc list. If you need to send a patch for the internal reasons, please use 
> Bcc.
> 
> On Tue, 21 Jun 2022 at 12:06, Kalyan Thota  wrote:
> >
> > Crtc color management needs to be registered only for the crtc which
> > has the capability to handle it. Since topology decides which encoder
> > will get the dspp hw block, tie up the crtc and the encoder together
> > (encoder->possible_crtcs)
> >
> > Change-Id: If5a0f33547b6f527ca4b8fbb78424b141dbbd711
> 
> No change-id's please. This is not the gerrit.
> 
> > Signed-off-by: Kalyan Thota 
> > ---
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c|  8 ++--
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h|  2 +-
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 20 
> > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h |  5 +
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 22 ++
> >  5 files changed, 46 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > index 7763558..2913acb 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > @@ -1511,7 +1511,7 @@ static const struct drm_crtc_helper_funcs
> > dpu_crtc_helper_funcs = {
> >
> >  /* initialize crtc */
> >  struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
> *plane,
> > -   struct drm_plane *cursor)
> > +   struct drm_plane *cursor, unsigned int
> > + enc_mask)
> >  {
> > struct drm_crtc *crtc = NULL;
> > struct dpu_crtc *dpu_crtc = NULL; @@ -1544,7 +1544,11 @@
> > struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct
> > drm_plane *plane,
> >
> > drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
> >
> > -   drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
> > +   /* Register crtc color management if the encoder has dspp, use the
> > +* crtc to mark it as possible_crtcs for that encoder.
> > +*/
> > +   if(BIT(crtc->index) & enc_mask)
> 
> So, we are checking CRTC's index against the encoder's mask? This is
> counterintuitive.
> 
> > +   drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
> >
> > /* save user friendly CRTC name for later */
> > snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u",
> > crtc->base.id); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> > index b8785c3..0a6458e 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> > @@ -269,7 +269,7 @@ void dpu_crtc_complete_commit(struct drm_crtc
> *crtc);
> >   * @Return: new crtc object or error
> >   */
>

[Freedreno] [v1] drm/msm/disp/dpu1: add support for hierarchical flush for dspp in sc7280

[Kalyan Thota]

Flush mechanism for DSPP blocks has changed in sc7280 family, it
allows individual sub blocks to be flushed in coordination with
master flush control.

representation: master_flush && (PCC_flush | IGC_flush .. etc )

This change adds necessary support for the above design.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  4 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  5 +++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  2 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 40 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |  3 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|  7 +
 6 files changed, 59 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 7763558..4eca317 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -703,6 +703,10 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc 
*crtc)
mixer[i].flush_mask |= ctl->ops.get_bitmask_dspp(ctl,
mixer[i].hw_dspp->idx);
 
+   if(ctl->ops.set_dspp_hierarchical_flush)
+   ctl->ops.set_dspp_hierarchical_flush(ctl,
+   mixer[i].hw_dspp->idx, 
DSPP_SUB_PCC);
+
/* stage config flush mask */
ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask);
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 021eb2f..3b27a87 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -58,7 +58,10 @@
(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
 
 #define CTL_SC7280_MASK \
-   (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | 
BIT(DPU_CTL_VM_CFG))
+   (BIT(DPU_CTL_ACTIVE_CFG) | \
+BIT(DPU_CTL_FETCH_ACTIVE) | \
+BIT(DPU_CTL_VM_CFG) | \
+BIT(DPU_CTL_HIERARCHICAL_FLUSH))
 
 #define MERGE_3D_SM8150_MASK (0)
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index b85b24b..7922f6c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -185,6 +185,7 @@ enum {
  * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
  * @DPU_CTL_FETCH_ACTIVE:  Active CTL for fetch HW (SSPPs)
  * @DPU_CTL_VM_CFG:CTL config to support multiple VMs
+ * @DPU_CTL_HIERARCHICAL_FLUSH: CTL config to support hierarchical flush
  * @DPU_CTL_MAX
  */
 enum {
@@ -192,6 +193,7 @@ enum {
DPU_CTL_ACTIVE_CFG,
DPU_CTL_FETCH_ACTIVE,
DPU_CTL_VM_CFG,
+   DPU_CTL_HIERARCHICAL_FLUSH,
DPU_CTL_MAX
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 3584f5e..b34fc30 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -28,6 +28,8 @@
 #define   CTL_INTF_FLUSH0x110
 #define   CTL_INTF_MASTER   0x134
 #define   CTL_FETCH_PIPE_ACTIVE 0x0FC
+#define   CTL_DSPP_0_FLUSH 0x13C
+
 
 #define CTL_MIXER_BORDER_OUTBIT(24)
 #define CTL_FLUSH_MASK_CTL  BIT(17)
@@ -292,6 +294,36 @@ static uint32_t dpu_hw_ctl_get_bitmask_dspp(struct 
dpu_hw_ctl *ctx,
return flushbits;
 }
 
+static uint32_t dpu_hw_ctl_get_bitmask_dspp_v1(struct dpu_hw_ctl *ctx,
+   enum dpu_dspp dspp)
+{
+   return BIT(29);
+}
+
+static void dpu_hw_ctl_set_dspp_hierarchical_flush(struct dpu_hw_ctl *ctx,
+   enum dpu_dspp dspp, enum dpu_dspp_sub_blk dspp_sub_blk)
+{
+   uint32_t flushbits = 0, active = 0;
+
+   switch (dspp_sub_blk) {
+   case DSPP_SUB_IGC:
+   flushbits = BIT(2);
+   break;
+   case DSPP_SUB_PCC:
+   flushbits = BIT(4);
+   break;
+   case DSPP_SUB_GC:
+   flushbits = BIT(5);
+   break;
+   default:
+   return;
+   }
+
+   active = DPU_REG_READ(&ctx->hw, CTL_DSPP_0_FLUSH + ((dspp - 1) * 4));
+
+   DPU_REG_WRITE(&ctx->hw, CTL_DSPP_0_FLUSH + ((dspp - 1) * 4), active | 
flushbits);
+}
+
 static u32 dpu_hw_ctl_poll_reset_status(struct dpu_hw_ctl *ctx, u32 timeout_us)
 {
struct dpu_hw_blk_reg_map *c = &ctx->hw;
@@ -600,7 +632,13 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
ops->setup_blendstage = dpu_hw_ctl_setup_blendstage;
ops->get_bitmask_sspp = dpu_hw_ctl_get_bitmask_sspp;
ops->get_bitmask_mixer = dpu_hw_ctl_get_bitmask_mixer;
-   ops->get_bitmask_dspp = dpu_hw_ctl_get_bitmask_dspp;
+   if (cap & BIT(DPU_CTL_HIERARCHICAL_FLUSH)) {
+   ops->get_bitmask_dspp = dpu_hw_ctl_get

Re: [Freedreno] [v1] drm/msm/disp/dpu1: add support for hierarchical flush for dspp in sc7280

[Kalyan Thota]

>-Original Message-
>From: Dmitry Baryshkov 
>Sent: Thursday, August 4, 2022 9:29 PM
>To: Kalyan Thota (QUIC) 
>Cc: dri-de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
>freedreno@lists.freedesktop.org; devicet...@vger.kernel.org; linux-
>ker...@vger.kernel.org; robdcl...@gmail.com; diand...@chromium.org;
>swb...@chromium.org; Vinod Polimera (QUIC) ;
>Abhinav Kumar (QUIC) 
>Subject: Re: [v1] drm/msm/disp/dpu1: add support for hierarchical flush for 
>dspp
>in sc7280
>
>WARNING: This email originated from outside of Qualcomm. Please be wary of
>any links or attachments, and do not enable macros.
>
>On Thu, 4 Aug 2022 at 13:29, Kalyan Thota  wrote:
>>
>> Flush mechanism for DSPP blocks has changed in sc7280 family, it
>> allows individual sub blocks to be flushed in coordination with master
>> flush control.
>>
>> representation: master_flush && (PCC_flush | IGC_flush .. etc )
>>
>> This change adds necessary support for the above design.
>>
>> Signed-off-by: Kalyan Thota 
>
>I'd like to land at least patches 6-8 from [1] next cycle. They clean up the 
>CTL
>interface. Could you please rebase your patch on top of them?
>

Sure I'll wait for the series to rebase. @Doug can you comment if this is okay 
and this patch is not needed immediately ?

>[1] https://patchwork.freedesktop.org/series/99909/
>
>> ---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  4 +++
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  5 +++-
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  2 ++
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 40
>+-
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |  3 ++
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|  7 +
>>  6 files changed, 59 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> index 7763558..4eca317 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> @@ -703,6 +703,10 @@ static void _dpu_crtc_setup_cp_blocks(struct
>drm_crtc *crtc)
>> mixer[i].flush_mask |= ctl->ops.get_bitmask_dspp(ctl,
>> mixer[i].hw_dspp->idx);
>>
>> +   if(ctl->ops.set_dspp_hierarchical_flush)
>> +   ctl->ops.set_dspp_hierarchical_flush(ctl,
>> +   mixer[i].hw_dspp->idx,
>> + DSPP_SUB_PCC);
>> +
>> /* stage config flush mask */
>> ctl->ops.update_pending_flush(ctl,
>> mixer[i].flush_mask);
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index 021eb2f..3b27a87 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -58,7 +58,10 @@
>> (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
>>
>>  #define CTL_SC7280_MASK \
>> -   (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) |
>BIT(DPU_CTL_VM_CFG))
>> +   (BIT(DPU_CTL_ACTIVE_CFG) | \
>> +BIT(DPU_CTL_FETCH_ACTIVE) | \
>> +BIT(DPU_CTL_VM_CFG) | \
>> +BIT(DPU_CTL_HIERARCHICAL_FLUSH))
>>
>>  #define MERGE_3D_SM8150_MASK (0)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index b85b24b..7922f6c 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -185,6 +185,7 @@ enum {
>>   * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
>>   * @DPU_CTL_FETCH_ACTIVE:  Active CTL for fetch HW (SSPPs)
>>   * @DPU_CTL_VM_CFG:CTL config to support multiple VMs
>> + * @DPU_CTL_HIERARCHICAL_FLUSH: CTL config to support hierarchical
>> + flush
>>   * @DPU_CTL_MAX
>>   */
>>  enum {
>> @@ -192,6 +193,7 @@ enum {
>> DPU_CTL_ACTIVE_CFG,
>> DPU_CTL_FETCH_ACTIVE,
>> DPU_CTL_VM_CFG,
>> +   DPU_CTL_HIERARCHICAL_FLUSH,
>> DPU_CTL_MAX
>>  };
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
>> index 3584f5e..b34fc30 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
>> @@ -28,6 +28,8 @@
>>  #define   CTL_INTF_FLUSH   

Re: [Freedreno] [v1] drm/msm/disp/dpu1: add support for hierarchical flush for dspp in sc7280

[Kalyan Thota]

>-Original Message-
>From: Dmitry Baryshkov 
>Sent: Friday, August 26, 2022 5:02 PM
>To: Kalyan Thota ; Kalyan Thota (QUIC)
>; diand...@chromium.org
>Cc: dri-de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
>freedreno@lists.freedesktop.org; devicet...@vger.kernel.org; linux-
>ker...@vger.kernel.org; robdcl...@gmail.com; swb...@chromium.org; Vinod
>Polimera (QUIC) ; Abhinav Kumar (QUIC)
>
>Subject: Re: [v1] drm/msm/disp/dpu1: add support for hierarchical flush for 
>dspp
>in sc7280
>
>WARNING: This email originated from outside of Qualcomm. Please be wary of
>any links or attachments, and do not enable macros.
>
>On 08/08/2022 13:44, Kalyan Thota wrote:
>>
>>
>>> -Original Message-
>>> From: Dmitry Baryshkov 
>>> Sent: Thursday, August 4, 2022 9:29 PM
>>> To: Kalyan Thota (QUIC) 
>>> Cc: dri-de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
>>> freedreno@lists.freedesktop.org; devicet...@vger.kernel.org; linux-
>>> ker...@vger.kernel.org; robdcl...@gmail.com; diand...@chromium.org;
>>> swb...@chromium.org; Vinod Polimera (QUIC)
>>> ; Abhinav Kumar (QUIC)
>>> 
>>> Subject: Re: [v1] drm/msm/disp/dpu1: add support for hierarchical
>>> flush for dspp in sc7280
>>>
>>> WARNING: This email originated from outside of Qualcomm. Please be
>>> wary of any links or attachments, and do not enable macros.
>>>
>>> On Thu, 4 Aug 2022 at 13:29, Kalyan Thota 
>wrote:
>>>>
>>>> Flush mechanism for DSPP blocks has changed in sc7280 family, it
>>>> allows individual sub blocks to be flushed in coordination with
>>>> master flush control.
>>>>
>>>> representation: master_flush && (PCC_flush | IGC_flush .. etc )
>>>>
>>>> This change adds necessary support for the above design.
>>>>
>>>> Signed-off-by: Kalyan Thota 
>>>
>>> I'd like to land at least patches 6-8 from [1] next cycle. They clean
>>> up the CTL interface. Could you please rebase your patch on top of them?
>>>
>>
>> Sure I'll wait for the series to rebase. @Doug can you comment if this is 
>> okay
>and this patch is not needed immediately ?
>
>The respective patches have been picked up for 6.1 and were pushed to
>https://gitlab.freedesktop.org/lumag/msm.git msm-next-lumag . Could you
>please rebase your patch on top of them?
>
>All other comments also needs addressing.
>
>>
>>> [1] https://patchwork.freedesktop.org/series/99909/
>>>
>>>> ---
>>>>   drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  4 +++
>>>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  5 +++-
>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  2 ++
>>>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 40
>>> +-
>>>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |  3 ++
>>>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|  7 +
>>>>   6 files changed, 59 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>>> index 7763558..4eca317 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>>> @@ -703,6 +703,10 @@ static void _dpu_crtc_setup_cp_blocks(struct
>>> drm_crtc *crtc)
>>>>  mixer[i].flush_mask |= ctl->ops.get_bitmask_dspp(ctl,
>>>>  mixer[i].hw_dspp->idx);
>>>>
>>>> +   if(ctl->ops.set_dspp_hierarchical_flush)
>>>> +   ctl->ops.set_dspp_hierarchical_flush(ctl,
>>>> +
>>>> + mixer[i].hw_dspp->idx, DSPP_SUB_PCC);
>>>> +
>>>>  /* stage config flush mask */
>>>>  ctl->ops.update_pending_flush(ctl,
>>>> mixer[i].flush_mask);
>>>>
>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>> index 021eb2f..3b27a87 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>> @@ -58,7 +58,10 @@
>>>>  (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
>>>>
>>>>   #define CTL_SC7280_MASK \
>>>> -   (BIT(DPU_CT

[Freedreno] [v2] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280

[Kalyan Thota]

Flush mechanism for DSPP blocks has changed in sc7280 family, it
allows individual sub blocks to be flushed in coordination with
master flush control.

Representation: master_flush && (PCC_flush | IGC_flush .. etc )

This change adds necessary support for the above design.

Changes in v1:
- Few nits (Doug, Dmitry)
- Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry)
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  5 +++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  2 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 35 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 10 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|  7 ++
 6 files changed, 56 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 601d687..ab38a52 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -766,7 +766,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc)
 
/* stage config flush mask */
ctl->ops.update_pending_flush_dspp(ctl,
-   mixer[i].hw_dspp->idx);
+   mixer[i].hw_dspp->idx, DPU_DSPP_SUB_PCC);
}
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 27f029f..0eecb2f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -65,7 +65,10 @@
(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
 
 #define CTL_SC7280_MASK \
-   (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | 
BIT(DPU_CTL_VM_CFG))
+   (BIT(DPU_CTL_ACTIVE_CFG) | \
+BIT(DPU_CTL_FETCH_ACTIVE) | \
+BIT(DPU_CTL_VM_CFG) | \
+BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
 
 #define MERGE_3D_SM8150_MASK (0)
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 38aa38a..6a0b784 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -191,6 +191,7 @@ enum {
  * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
  * @DPU_CTL_FETCH_ACTIVE:  Active CTL for fetch HW (SSPPs)
  * @DPU_CTL_VM_CFG:CTL config to support multiple VMs
+ * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush
  * @DPU_CTL_MAX
  */
 enum {
@@ -198,6 +199,7 @@ enum {
DPU_CTL_ACTIVE_CFG,
DPU_CTL_FETCH_ACTIVE,
DPU_CTL_VM_CFG,
+   DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
DPU_CTL_MAX
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index a35ecb6..3b14c30 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -33,6 +33,7 @@
 #define   CTL_INTF_FLUSH0x110
 #define   CTL_INTF_MASTER   0x134
 #define   CTL_FETCH_PIPE_ACTIVE 0x0FC
+#define   CTL_DSPP_n_FLUSH 0x13C
 
 #define CTL_MIXER_BORDER_OUTBIT(24)
 #define CTL_FLUSH_MASK_CTL  BIT(17)
@@ -82,6 +83,31 @@ static int _mixer_stages(const struct dpu_lm_cfg *mixer, int 
count,
return stages;
 }
 
+static u32 _set_dspp_sub_block_flush(struct dpu_hw_ctl *ctx,
+   enum dpu_dspp dspp, enum dpu_dspp_sub_blk dspp_sub_blk)
+{
+   uint32_t flushbits = 0, active;
+
+   switch (dspp_sub_blk) {
+   case DPU_DSPP_SUB_IGC:
+   flushbits = BIT(2);
+   break;
+   case DPU_DSPP_SUB_PCC:
+   flushbits = BIT(4);
+   break;
+   case DPU_DSPP_SUB_GC:
+   flushbits = BIT(5);
+   break;
+   default:
+   return 0;
+   }
+
+   active = DPU_REG_READ(&ctx->hw, CTL_DSPP_n_FLUSH + ((dspp - 1) * 4));
+   DPU_REG_WRITE(&ctx->hw, CTL_DSPP_n_FLUSH + ((dspp - 1) * 4), active | 
flushbits);
+
+   return BIT(29);
+}
+
 static inline u32 dpu_hw_ctl_get_flush_register(struct dpu_hw_ctl *ctx)
 {
struct dpu_hw_blk_reg_map *c = &ctx->hw;
@@ -287,8 +313,15 @@ static void 
dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx,
 }
 
 static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx,
-   enum dpu_dspp dspp)
+   enum dpu_dspp dspp, enum dpu_dspp_sub_blk dspp_sub_blk)
 {
+
+   if ((test_bit(DPU_CTL_DSPP_SUB_BLOCK_FLUSH, &ctx->caps->features))) {
+   ctx->pending_flush_mask |=
+   _set_dspp_sub_block_flush(ctx, dspp, dspp_sub_blk);
+   return;
+   }
+
switch (dspp) {
case DSPP_0:
ctx->pending_flush_mask |= BIT(13);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
index 96c012e..227f1bd 100644
--- a/drivers/gpu/drm/msm/disp/dp

[Freedreno] [v3] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280

[Kalyan Thota]

Flush mechanism for DSPP blocks has changed in sc7280 family, it
allows individual sub blocks to be flushed in coordination with
master flush control.

Representation: master_flush && (PCC_flush | IGC_flush .. etc )

This change adds necessary support for the above design.

Changes in v1:
- Few nits (Doug, Dmitry)
- Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry)

Changes in v2:
- Move the address offset to flush macro (Dmitry)
- Seperate ops for the sub block flush (Dmitry)
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  5 +++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  2 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 35 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 10 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|  7 ++
 6 files changed, 55 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 601d687..ab38a52 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -766,7 +766,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc)
 
/* stage config flush mask */
ctl->ops.update_pending_flush_dspp(ctl,
-   mixer[i].hw_dspp->idx);
+   mixer[i].hw_dspp->idx, DPU_DSPP_SUB_PCC);
}
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 27f029f..0eecb2f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -65,7 +65,10 @@
(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
 
 #define CTL_SC7280_MASK \
-   (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | 
BIT(DPU_CTL_VM_CFG))
+   (BIT(DPU_CTL_ACTIVE_CFG) | \
+BIT(DPU_CTL_FETCH_ACTIVE) | \
+BIT(DPU_CTL_VM_CFG) | \
+BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
 
 #define MERGE_3D_SM8150_MASK (0)
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 38aa38a..6a0b784 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -191,6 +191,7 @@ enum {
  * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
  * @DPU_CTL_FETCH_ACTIVE:  Active CTL for fetch HW (SSPPs)
  * @DPU_CTL_VM_CFG:CTL config to support multiple VMs
+ * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush
  * @DPU_CTL_MAX
  */
 enum {
@@ -198,6 +199,7 @@ enum {
DPU_CTL_ACTIVE_CFG,
DPU_CTL_FETCH_ACTIVE,
DPU_CTL_VM_CFG,
+   DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
DPU_CTL_MAX
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index a35ecb6..31c8c44 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -33,6 +33,7 @@
 #define   CTL_INTF_FLUSH0x110
 #define   CTL_INTF_MASTER   0x134
 #define   CTL_FETCH_PIPE_ACTIVE 0x0FC
+#define   CTL_DSPP_n_FLUSH(n)  ((0x13C) + ((n - 1) * 4))
 
 #define CTL_MIXER_BORDER_OUTBIT(24)
 #define CTL_FLUSH_MASK_CTL  BIT(17)
@@ -287,8 +288,9 @@ static void 
dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx,
 }
 
 static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx,
-   enum dpu_dspp dspp)
+   enum dpu_dspp dspp, enum dpu_dspp_sub_blk dspp_sub_blk)
 {
+
switch (dspp) {
case DSPP_0:
ctx->pending_flush_mask |= BIT(13);
@@ -307,6 +309,31 @@ static void dpu_hw_ctl_update_pending_flush_dspp(struct 
dpu_hw_ctl *ctx,
}
 }
 
+static void dpu_hw_ctl_update_pending_flush_dspp_subblocks(
+   struct dpu_hw_ctl *ctx, enum dpu_dspp dspp, enum dpu_dspp_sub_blk 
dspp_sub_blk)
+{
+   uint32_t flushbits = 0, active;
+
+   switch (dspp_sub_blk) {
+   case DPU_DSPP_SUB_IGC:
+   flushbits = BIT(2);
+   break;
+   case DPU_DSPP_SUB_PCC:
+   flushbits = BIT(4);
+   break;
+   case DPU_DSPP_SUB_GC:
+   flushbits = BIT(5);
+   break;
+   default:
+   return;
+   }
+
+   active = DPU_REG_READ(&ctx->hw, CTL_DSPP_n_FLUSH(dspp));
+   DPU_REG_WRITE(&ctx->hw, CTL_DSPP_n_FLUSH(dspp), active | flushbits);
+
+   ctx->pending_flush_mask |= BIT(29);
+}
+
 static u32 dpu_hw_ctl_poll_reset_status(struct dpu_hw_ctl *ctx, u32 timeout_us)
 {
struct dpu_hw_blk_reg_map *c = &ctx->hw;
@@ -675,7 +702,11 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
ops->setup_blendstage = dpu_hw_ctl_setup_blendstage;
ops->update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp;
ops->update_pending_flus

[Freedreno] [v4] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280

[Kalyan Thota]

Flush mechanism for DSPP blocks has changed in sc7280 family, it
allows individual sub blocks to be flushed in coordination with
master flush control.

Representation: master_flush && (PCC_flush | IGC_flush .. etc )

This change adds necessary support for the above design.

Changes in v1:
- Few nits (Doug, Dmitry)
- Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry)

Changes in v2:
- Move the address offset to flush macro (Dmitry)
- Seperate ops for the sub block flush (Dmitry)

Changes in v3:
- Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry)
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  5 +++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  4 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 35 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 10 ++--
 5 files changed, 50 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 601d687..4170fbe 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -766,7 +766,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc)
 
/* stage config flush mask */
ctl->ops.update_pending_flush_dspp(ctl,
-   mixer[i].hw_dspp->idx);
+   mixer[i].hw_dspp->idx, DPU_DSPP_PCC);
}
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 27f029f..0eecb2f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -65,7 +65,10 @@
(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
 
 #define CTL_SC7280_MASK \
-   (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | 
BIT(DPU_CTL_VM_CFG))
+   (BIT(DPU_CTL_ACTIVE_CFG) | \
+BIT(DPU_CTL_FETCH_ACTIVE) | \
+BIT(DPU_CTL_VM_CFG) | \
+BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
 
 #define MERGE_3D_SM8150_MASK (0)
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 38aa38a..8148e91 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -161,10 +161,12 @@ enum {
  * DSPP sub-blocks
  * @DPU_DSPP_PCC Panel color correction block
  * @DPU_DSPP_GC  Gamma correction block
+ * @DPU_DSPP_IGC Inverse Gamma correction block
  */
 enum {
DPU_DSPP_PCC = 0x1,
DPU_DSPP_GC,
+   DPU_DSPP_IGC,
DPU_DSPP_MAX
 };
 
@@ -191,6 +193,7 @@ enum {
  * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
  * @DPU_CTL_FETCH_ACTIVE:  Active CTL for fetch HW (SSPPs)
  * @DPU_CTL_VM_CFG:CTL config to support multiple VMs
+ * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush
  * @DPU_CTL_MAX
  */
 enum {
@@ -198,6 +201,7 @@ enum {
DPU_CTL_ACTIVE_CFG,
DPU_CTL_FETCH_ACTIVE,
DPU_CTL_VM_CFG,
+   DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
DPU_CTL_MAX
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index a35ecb6..bbda09a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -33,6 +33,7 @@
 #define   CTL_INTF_FLUSH0x110
 #define   CTL_INTF_MASTER   0x134
 #define   CTL_FETCH_PIPE_ACTIVE 0x0FC
+#define   CTL_DSPP_n_FLUSH(n)  ((0x13C) + ((n - 1) * 4))
 
 #define CTL_MIXER_BORDER_OUTBIT(24)
 #define CTL_FLUSH_MASK_CTL  BIT(17)
@@ -287,8 +288,9 @@ static void 
dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx,
 }
 
 static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx,
-   enum dpu_dspp dspp)
+   enum dpu_dspp dspp, u32 dspp_sub_blk)
 {
+
switch (dspp) {
case DSPP_0:
ctx->pending_flush_mask |= BIT(13);
@@ -307,6 +309,31 @@ static void dpu_hw_ctl_update_pending_flush_dspp(struct 
dpu_hw_ctl *ctx,
}
 }
 
+static void dpu_hw_ctl_update_pending_flush_dspp_subblocks(
+   struct dpu_hw_ctl *ctx, enum dpu_dspp dspp, u32 dspp_sub_blk)
+{
+   uint32_t flushbits = 0, active;
+
+   switch (dspp_sub_blk) {
+   case DPU_DSPP_IGC:
+   flushbits = BIT(2);
+   break;
+   case DPU_DSPP_PCC:
+   flushbits = BIT(4);
+   break;
+   case DPU_DSPP_GC:
+   flushbits = BIT(5);
+   break;
+   default:
+   return;
+   }
+
+   active = DPU_REG_READ(&ctx->hw, CTL_DSPP_n_FLUSH(dspp));
+   DPU_REG_WRITE(&ctx->hw, CTL_DSPP_n_FLUSH(dspp), active | flushbits);
+
+   ctx->pending_flush_mask |= BIT(29);
+}
+
 static u32 dpu_hw_ctl_poll_reset_status(struct dpu_hw_ctl *ctx, u32 timeout_us)
 {
 

[Freedreno] [v5] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280

[Kalyan Thota]

Flush mechanism for DSPP blocks has changed in sc7280 family, it
allows individual sub blocks to be flushed in coordination with
master flush control.

Representation: master_flush && (PCC_flush | IGC_flush .. etc )

This change adds necessary support for the above design.

Changes in v1:
- Few nits (Doug, Dmitry)
- Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry)

Changes in v2:
- Move the address offset to flush macro (Dmitry)
- Seperate ops for the sub block flush (Dmitry)

Changes in v3:
- Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry)

Changes in v4:
- Use shorter version for unsigned int (Stephen)

Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  5 +++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  4 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 35 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 10 ++--
 5 files changed, 50 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 601d687..4170fbe 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -766,7 +766,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc)
 
/* stage config flush mask */
ctl->ops.update_pending_flush_dspp(ctl,
-   mixer[i].hw_dspp->idx);
+   mixer[i].hw_dspp->idx, DPU_DSPP_PCC);
}
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 27f029f..0eecb2f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -65,7 +65,10 @@
(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
 
 #define CTL_SC7280_MASK \
-   (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | 
BIT(DPU_CTL_VM_CFG))
+   (BIT(DPU_CTL_ACTIVE_CFG) | \
+BIT(DPU_CTL_FETCH_ACTIVE) | \
+BIT(DPU_CTL_VM_CFG) | \
+BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
 
 #define MERGE_3D_SM8150_MASK (0)
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 38aa38a..8148e91 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -161,10 +161,12 @@ enum {
  * DSPP sub-blocks
  * @DPU_DSPP_PCC Panel color correction block
  * @DPU_DSPP_GC  Gamma correction block
+ * @DPU_DSPP_IGC Inverse Gamma correction block
  */
 enum {
DPU_DSPP_PCC = 0x1,
DPU_DSPP_GC,
+   DPU_DSPP_IGC,
DPU_DSPP_MAX
 };
 
@@ -191,6 +193,7 @@ enum {
  * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
  * @DPU_CTL_FETCH_ACTIVE:  Active CTL for fetch HW (SSPPs)
  * @DPU_CTL_VM_CFG:CTL config to support multiple VMs
+ * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush
  * @DPU_CTL_MAX
  */
 enum {
@@ -198,6 +201,7 @@ enum {
DPU_CTL_ACTIVE_CFG,
DPU_CTL_FETCH_ACTIVE,
DPU_CTL_VM_CFG,
+   DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
DPU_CTL_MAX
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index a35ecb6..f26f484 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -33,6 +33,7 @@
 #define   CTL_INTF_FLUSH0x110
 #define   CTL_INTF_MASTER   0x134
 #define   CTL_FETCH_PIPE_ACTIVE 0x0FC
+#define   CTL_DSPP_n_FLUSH(n)  ((0x13C) + ((n - 1) * 4))
 
 #define CTL_MIXER_BORDER_OUTBIT(24)
 #define CTL_FLUSH_MASK_CTL  BIT(17)
@@ -287,8 +288,9 @@ static void 
dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx,
 }
 
 static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx,
-   enum dpu_dspp dspp)
+   enum dpu_dspp dspp, u32 dspp_sub_blk)
 {
+
switch (dspp) {
case DSPP_0:
ctx->pending_flush_mask |= BIT(13);
@@ -307,6 +309,31 @@ static void dpu_hw_ctl_update_pending_flush_dspp(struct 
dpu_hw_ctl *ctx,
}
 }
 
+static void dpu_hw_ctl_update_pending_flush_dspp_subblocks(
+   struct dpu_hw_ctl *ctx, enum dpu_dspp dspp, u32 dspp_sub_blk)
+{
+   u32 flushbits = 0, active;
+
+   switch (dspp_sub_blk) {
+   case DPU_DSPP_IGC:
+   flushbits = BIT(2);
+   break;
+   case DPU_DSPP_PCC:
+   flushbits = BIT(4);
+   break;
+   case DPU_DSPP_GC:
+   flushbits = BIT(5);
+   break;
+   default:
+   return;
+   }
+
+   active = DPU_REG_READ(&ctx->hw, CTL_DSPP_n_FLUSH(dspp));
+   DPU_REG_WRITE(&ctx->hw, CTL_DSPP_n_FLUSH(dspp), active | flushbits);
+
+   ctx->pending_flush_mask |= BIT(29)

[Freedreno] [Resend v4] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280

[Kalyan Thota]

Flush mechanism for DSPP blocks has changed in sc7280 family, it
allows individual sub blocks to be flushed in coordination with
master flush control.

Representation: master_flush && (PCC_flush | IGC_flush .. etc )

This change adds necessary support for the above design.

Changes in v1:
- Few nits (Doug, Dmitry)
- Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry)

Changes in v2:
- Move the address offset to flush macro (Dmitry)
- Seperate ops for the sub block flush (Dmitry)

Changes in v3:
- Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry)

Changes in v4:
- Use shorter version for unsigned int (Stephen)

Signed-off-by: Kalyan Thota 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  5 +++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  4 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 35 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 10 ++--
 5 files changed, 50 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 601d687..4170fbe 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -766,7 +766,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc)
 
/* stage config flush mask */
ctl->ops.update_pending_flush_dspp(ctl,
-   mixer[i].hw_dspp->idx);
+   mixer[i].hw_dspp->idx, DPU_DSPP_PCC);
}
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 27f029f..0eecb2f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -65,7 +65,10 @@
(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
 
 #define CTL_SC7280_MASK \
-   (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | 
BIT(DPU_CTL_VM_CFG))
+   (BIT(DPU_CTL_ACTIVE_CFG) | \
+BIT(DPU_CTL_FETCH_ACTIVE) | \
+BIT(DPU_CTL_VM_CFG) | \
+BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
 
 #define MERGE_3D_SM8150_MASK (0)
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 38aa38a..8148e91 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -161,10 +161,12 @@ enum {
  * DSPP sub-blocks
  * @DPU_DSPP_PCC Panel color correction block
  * @DPU_DSPP_GC  Gamma correction block
+ * @DPU_DSPP_IGC Inverse Gamma correction block
  */
 enum {
DPU_DSPP_PCC = 0x1,
DPU_DSPP_GC,
+   DPU_DSPP_IGC,
DPU_DSPP_MAX
 };
 
@@ -191,6 +193,7 @@ enum {
  * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
  * @DPU_CTL_FETCH_ACTIVE:  Active CTL for fetch HW (SSPPs)
  * @DPU_CTL_VM_CFG:CTL config to support multiple VMs
+ * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush
  * @DPU_CTL_MAX
  */
 enum {
@@ -198,6 +201,7 @@ enum {
DPU_CTL_ACTIVE_CFG,
DPU_CTL_FETCH_ACTIVE,
DPU_CTL_VM_CFG,
+   DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
DPU_CTL_MAX
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index a35ecb6..f26f484 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -33,6 +33,7 @@
 #define   CTL_INTF_FLUSH0x110
 #define   CTL_INTF_MASTER   0x134
 #define   CTL_FETCH_PIPE_ACTIVE 0x0FC
+#define   CTL_DSPP_n_FLUSH(n)  ((0x13C) + ((n - 1) * 4))
 
 #define CTL_MIXER_BORDER_OUTBIT(24)
 #define CTL_FLUSH_MASK_CTL  BIT(17)
@@ -287,8 +288,9 @@ static void 
dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx,
 }
 
 static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx,
-   enum dpu_dspp dspp)
+   enum dpu_dspp dspp, u32 dspp_sub_blk)
 {
+
switch (dspp) {
case DSPP_0:
ctx->pending_flush_mask |= BIT(13);
@@ -307,6 +309,31 @@ static void dpu_hw_ctl_update_pending_flush_dspp(struct 
dpu_hw_ctl *ctx,
}
 }
 
+static void dpu_hw_ctl_update_pending_flush_dspp_subblocks(
+   struct dpu_hw_ctl *ctx, enum dpu_dspp dspp, u32 dspp_sub_blk)
+{
+   u32 flushbits = 0, active;
+
+   switch (dspp_sub_blk) {
+   case DPU_DSPP_IGC:
+   flushbits = BIT(2);
+   break;
+   case DPU_DSPP_PCC:
+   flushbits = BIT(4);
+   break;
+   case DPU_DSPP_GC:
+   flushbits = BIT(5);
+   break;
+   default:
+   return;
+   }
+
+   active = DPU_REG_READ(&ctx->hw, CTL_DSPP_n_FLUSH(dspp));
+   DPU_REG_WRITE(&ctx->hw, CTL_DSPP_n_FLUSH(dspp), 

Re: [Freedreno] [v5] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280

[Kalyan Thota]

>-Original Message-
>From: Dmitry Baryshkov 
>Sent: Friday, September 30, 2022 1:59 PM
>To: Doug Anderson ; Kalyan Thota (QUIC)
>
>Cc: y...@qualcomm.com; dri-devel ; linux-arm-
>msm ; freedreno
>; open list:OPEN FIRMWARE AND FLATTENED
>DEVICE TREE BINDINGS ; LKML ker...@vger.kernel.org>; Rob Clark ; Stephen Boyd
>; Vinod Polimera (QUIC)
>; Abhinav Kumar (QUIC)
>
>Subject: Re: [v5] drm/msm/disp/dpu1: add support for dspp sub block flush in
>sc7280
>
>WARNING: This email originated from outside of Qualcomm. Please be wary of
>any links or attachments, and do not enable macros.
>
>On 29 September 2022 19:13:20 GMT+03:00, Doug Anderson
> wrote:
>>Hi,
>>
>>On Wed, Sep 14, 2022 at 5:16 AM Kalyan Thota 
>wrote:
>>>
>>> Flush mechanism for DSPP blocks has changed in sc7280 family, it
>>> allows individual sub blocks to be flushed in coordination with
>>> master flush control.
>>>
>>> Representation: master_flush && (PCC_flush | IGC_flush .. etc )
>>>
>>> This change adds necessary support for the above design.
>>>
>>> Changes in v1:
>>> - Few nits (Doug, Dmitry)
>>> - Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry)
>>>
>>> Changes in v2:
>>> - Move the address offset to flush macro (Dmitry)
>>> - Seperate ops for the sub block flush (Dmitry)
>>>
>>> Changes in v3:
>>> - Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry)
>>>
>>> Changes in v4:
>>> - Use shorter version for unsigned int (Stephen)
>>>
>>> Reviewed-by: Dmitry Baryshkov 
>>> ---
>>>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  2 +-
>>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  5 +++-
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  4 +++
>>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 35
>--
>>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 10 ++--
>>>  5 files changed, 50 insertions(+), 6 deletions(-)
>>
>>Breadcrumbs: though this is tagged in the subject as v5 I think the
>>newest version is actually "resend v4" [1] which just fixes the
>>Signed-off-by.
>
>Not to mention that v5 misses the S-o-B tag.
>
>>
>>[1]
>>https://lore.kernel.org/r/1663825463-6715-1-git-send-email-quic_kalyant
>>@quicinc.com
>
Latest one is 
https://lore.kernel.org/r/1663825463-6715-1-git-send-email-quic_kaly...@quicinc.com
 that I last posted.
Don’t recollect on why tag was marked as v5. To avoid confusion, shall I resend 
it again ?
>--
>With best wishes
>Dmitry

[Freedreno] [v6] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280

[Kalyan Thota]

Flush mechanism for DSPP blocks has changed in sc7280 family, it
allows individual sub blocks to be flushed in coordination with
master flush control.

Representation: master_flush && (PCC_flush | IGC_flush .. etc )

This change adds necessary support for the above design.

Changes in v1:
- Few nits (Doug, Dmitry)
- Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry)

Changes in v2:
- Move the address offset to flush macro (Dmitry)
- Seperate ops for the sub block flush (Dmitry)

Changes in v3:
- Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry)

Changes in v4:
- Use shorter version for unsigned int (Stephen)

Changes in v5:
- Spurious patch please ignore.

Changes in v6:
- Add SOB tag (Doug, Dmitry)

Signed-off-by: Kalyan Thota 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  5 +++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  4 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 35 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 10 ++--
 5 files changed, 50 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 601d687..4170fbe 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -766,7 +766,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc)
 
/* stage config flush mask */
ctl->ops.update_pending_flush_dspp(ctl,
-   mixer[i].hw_dspp->idx);
+   mixer[i].hw_dspp->idx, DPU_DSPP_PCC);
}
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 27f029f..0eecb2f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -65,7 +65,10 @@
(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
 
 #define CTL_SC7280_MASK \
-   (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | 
BIT(DPU_CTL_VM_CFG))
+   (BIT(DPU_CTL_ACTIVE_CFG) | \
+BIT(DPU_CTL_FETCH_ACTIVE) | \
+BIT(DPU_CTL_VM_CFG) | \
+BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
 
 #define MERGE_3D_SM8150_MASK (0)
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 38aa38a..8148e91 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -161,10 +161,12 @@ enum {
  * DSPP sub-blocks
  * @DPU_DSPP_PCC Panel color correction block
  * @DPU_DSPP_GC  Gamma correction block
+ * @DPU_DSPP_IGC Inverse Gamma correction block
  */
 enum {
DPU_DSPP_PCC = 0x1,
DPU_DSPP_GC,
+   DPU_DSPP_IGC,
DPU_DSPP_MAX
 };
 
@@ -191,6 +193,7 @@ enum {
  * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
  * @DPU_CTL_FETCH_ACTIVE:  Active CTL for fetch HW (SSPPs)
  * @DPU_CTL_VM_CFG:CTL config to support multiple VMs
+ * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush
  * @DPU_CTL_MAX
  */
 enum {
@@ -198,6 +201,7 @@ enum {
DPU_CTL_ACTIVE_CFG,
DPU_CTL_FETCH_ACTIVE,
DPU_CTL_VM_CFG,
+   DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
DPU_CTL_MAX
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index a35ecb6..f26f484 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -33,6 +33,7 @@
 #define   CTL_INTF_FLUSH0x110
 #define   CTL_INTF_MASTER   0x134
 #define   CTL_FETCH_PIPE_ACTIVE 0x0FC
+#define   CTL_DSPP_n_FLUSH(n)  ((0x13C) + ((n - 1) * 4))
 
 #define CTL_MIXER_BORDER_OUTBIT(24)
 #define CTL_FLUSH_MASK_CTL  BIT(17)
@@ -287,8 +288,9 @@ static void 
dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx,
 }
 
 static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx,
-   enum dpu_dspp dspp)
+   enum dpu_dspp dspp, u32 dspp_sub_blk)
 {
+
switch (dspp) {
case DSPP_0:
ctx->pending_flush_mask |= BIT(13);
@@ -307,6 +309,31 @@ static void dpu_hw_ctl_update_pending_flush_dspp(struct 
dpu_hw_ctl *ctx,
}
 }
 
+static void dpu_hw_ctl_update_pending_flush_dspp_subblocks(
+   struct dpu_hw_ctl *ctx, enum dpu_dspp dspp, u32 dspp_sub_blk)
+{
+   u32 flushbits = 0, active;
+
+   switch (dspp_sub_blk) {
+   case DPU_DSPP_IGC:
+   flushbits = BIT(2);
+   break;
+   case DPU_DSPP_PCC:
+   flushbits = BIT(4);
+   break;
+   case DPU_DSPP_GC:
+   flushbits = BIT(5);
+   break;
+   default:
+   return;
+   }
+
+   active = DPU_REG_READ(&ctx-&g

Re: [Freedreno] [v6] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280

[Kalyan Thota]

>-Original Message-
>From: Dmitry Baryshkov 
>Sent: Tuesday, October 4, 2022 8:03 PM
>To: Kalyan Thota (QUIC) 
>Cc: dri-de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
>freedreno@lists.freedesktop.org; devicet...@vger.kernel.org; linux-
>ker...@vger.kernel.org; robdcl...@gmail.com; diand...@chromium.org;
>swb...@chromium.org; Vinod Polimera (QUIC) ;
>Abhinav Kumar (QUIC) 
>Subject: Re: [v6] drm/msm/disp/dpu1: add support for dspp sub block flush in
>sc7280
>
>WARNING: This email originated from outside of Qualcomm. Please be wary of
>any links or attachments, and do not enable macros.
>
>On Sun, 2 Oct 2022 at 06:15, Kalyan Thota  wrote:
>>
>> Flush mechanism for DSPP blocks has changed in sc7280 family, it
>> allows individual sub blocks to be flushed in coordination with master
>> flush control.
>>
>> Representation: master_flush && (PCC_flush | IGC_flush .. etc )
>>
>> This change adds necessary support for the above design.
>>
>> Changes in v1:
>> - Few nits (Doug, Dmitry)
>> - Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry)
>>
>> Changes in v2:
>> - Move the address offset to flush macro (Dmitry)
>> - Seperate ops for the sub block flush (Dmitry)
>>
>> Changes in v3:
>> - Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry)
>>
>> Changes in v4:
>> - Use shorter version for unsigned int (Stephen)
>>
>> Changes in v5:
>> - Spurious patch please ignore.
>>
>> Changes in v6:
>> - Add SOB tag (Doug, Dmitry)
>>
>> Signed-off-by: Kalyan Thota 
>> Reviewed-by: Dmitry Baryshkov 
>> ---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  2 +-
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  5 +++-
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  4 +++
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 35
>--
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 10 ++--
>>  5 files changed, 50 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> index 601d687..4170fbe 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> @@ -766,7 +766,7 @@ static void _dpu_crtc_setup_cp_blocks(struct
>> drm_crtc *crtc)
>>
>> /* stage config flush mask */
>> ctl->ops.update_pending_flush_dspp(ctl,
>> -   mixer[i].hw_dspp->idx);
>> +   mixer[i].hw_dspp->idx, DPU_DSPP_PCC);
>> }
>>  }
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index 27f029f..0eecb2f 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -65,7 +65,10 @@
>> (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
>>
>>  #define CTL_SC7280_MASK \
>> -   (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) |
>BIT(DPU_CTL_VM_CFG))
>> +   (BIT(DPU_CTL_ACTIVE_CFG) | \
>> +BIT(DPU_CTL_FETCH_ACTIVE) | \
>> +BIT(DPU_CTL_VM_CFG) | \
>> +BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
>>
>>  #define MERGE_3D_SM8150_MASK (0)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index 38aa38a..8148e91 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -161,10 +161,12 @@ enum {
>>   * DSPP sub-blocks
>>   * @DPU_DSPP_PCC Panel color correction block
>>   * @DPU_DSPP_GC  Gamma correction block
>> + * @DPU_DSPP_IGC Inverse Gamma correction block
>>   */
>>  enum {
>> DPU_DSPP_PCC = 0x1,
>> DPU_DSPP_GC,
>> +   DPU_DSPP_IGC,
>> DPU_DSPP_MAX
>>  };
>>
>> @@ -191,6 +193,7 @@ enum {
>>   * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
>>   * @DPU_CTL_FETCH_ACTIVE:  Active CTL for fetch HW (SSPPs)
>>   * @DPU_CTL_VM_CFG:CTL config to support multiple VMs
>> + * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block
>> + flush
>>   * @DPU_CTL_MAX
>>   */
>>  enum {
>> @@ -198,6 +201,7 @@ enum {
>> DPU_CTL_ACTIVE_CFG,
>> DPU_CTL_FETCH_ACTIVE,
>> DPU_CTL_VM_CFG,
>> +  

[Freedreno] [v7] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280

[Kalyan Thota]

Flush mechanism for DSPP blocks has changed in sc7280 family, it
allows individual sub blocks to be flushed in coordination with
master flush control.

Representation: master_flush && (PCC_flush | IGC_flush .. etc )

This change adds necessary support for the above design.

Changes in v1:
- Few nits (Doug, Dmitry)
- Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry)

Changes in v2:
- Move the address offset to flush macro (Dmitry)
- Seperate ops for the sub block flush (Dmitry)

Changes in v3:
- Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry)

Changes in v4:
- Use shorter version for unsigned int (Stephen)

Changes in v5:
- Spurious patch please ignore.

Changes in v6:
- Add SOB tag (Doug, Dmitry)

Changes in v7:
- Cache flush mask per dspp (Dmitry)
- Few nits (Marijn)

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  5 ++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  4 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 46 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |  7 ++--
 5 files changed, 58 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 601d687..4170fbe 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -766,7 +766,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc)
 
/* stage config flush mask */
ctl->ops.update_pending_flush_dspp(ctl,
-   mixer[i].hw_dspp->idx);
+   mixer[i].hw_dspp->idx, DPU_DSPP_PCC);
}
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 27f029f..0eecb2f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -65,7 +65,10 @@
(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
 
 #define CTL_SC7280_MASK \
-   (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | 
BIT(DPU_CTL_VM_CFG))
+   (BIT(DPU_CTL_ACTIVE_CFG) | \
+BIT(DPU_CTL_FETCH_ACTIVE) | \
+BIT(DPU_CTL_VM_CFG) | \
+BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
 
 #define MERGE_3D_SM8150_MASK (0)
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 38aa38a..8148e91 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -161,10 +161,12 @@ enum {
  * DSPP sub-blocks
  * @DPU_DSPP_PCC Panel color correction block
  * @DPU_DSPP_GC  Gamma correction block
+ * @DPU_DSPP_IGC Inverse Gamma correction block
  */
 enum {
DPU_DSPP_PCC = 0x1,
DPU_DSPP_GC,
+   DPU_DSPP_IGC,
DPU_DSPP_MAX
 };
 
@@ -191,6 +193,7 @@ enum {
  * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
  * @DPU_CTL_FETCH_ACTIVE:  Active CTL for fetch HW (SSPPs)
  * @DPU_CTL_VM_CFG:CTL config to support multiple VMs
+ * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush
  * @DPU_CTL_MAX
  */
 enum {
@@ -198,6 +201,7 @@ enum {
DPU_CTL_ACTIVE_CFG,
DPU_CTL_FETCH_ACTIVE,
DPU_CTL_VM_CFG,
+   DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
DPU_CTL_MAX
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index a35ecb6..fbcb7da 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -33,6 +33,7 @@
 #define   CTL_INTF_FLUSH0x110
 #define   CTL_INTF_MASTER   0x134
 #define   CTL_FETCH_PIPE_ACTIVE 0x0FC
+#define   CTL_DSPP_n_FLUSH(n)  ((0x13C) + ((n) * 4))
 
 #define CTL_MIXER_BORDER_OUTBIT(24)
 #define CTL_FLUSH_MASK_CTL  BIT(17)
@@ -110,9 +111,14 @@ static inline void dpu_hw_ctl_trigger_pending(struct 
dpu_hw_ctl *ctx)
 
 static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx)
 {
+   int i;
+
trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask,
 dpu_hw_ctl_get_flush_register(ctx));
ctx->pending_flush_mask = 0x0;
+
+   for(i = 0; i < ARRAY_SIZE(ctx->pending_dspp_flush_mask); i++)
+   ctx->pending_dspp_flush_mask[i] = 0x0;
 }
 
 static inline void dpu_hw_ctl_update_pending_flush(struct dpu_hw_ctl *ctx,
@@ -130,6 +136,8 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl 
*ctx)
 
 static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
 {
+   int i;
+
if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX))
DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,
ctx->pending_merge_3d_flu

[Freedreno] [PATCH] drm/msm/disp/dpu1: register crtc color management to first crtc in the list

[Kalyan Thota]

This patch does the following:

1) Registers crtc color management to the first crtc in the list and
attach to an encoder which is neither pluggable nor virtual
2) Pin 1 crtc to 1 encoder
3) Assign dspp block if crtc supports color processing.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 17 +++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h| 23 
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 42 ++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 16 ++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 14 +++---
 drivers/gpu/drm/msm/dp/dp_display.c |  5 
 drivers/gpu/drm/msm/msm_drv.h   |  7 -
 7 files changed, 109 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 4170fbe..14ff7ca 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -553,6 +554,17 @@ static void _dpu_crtc_complete_flip(struct drm_crtc *crtc)
spin_unlock_irqrestore(&dev->event_lock, flags);
 }
 
+bool dpu_crtc_has_color_enabled(struct drm_crtc *crtc)
+{
+   u32 gamma_id = crtc->dev->mode_config.gamma_lut_property->base.id;
+   u32 degamma_id = crtc->dev->mode_config.degamma_lut_property->base.id;
+   u32 ctm_id = crtc->dev->mode_config.ctm_property->base.id;
+
+   return !!(find_prop_id(&crtc->base, gamma_id) ||
+ find_prop_id(&crtc->base, degamma_id) ||
+ find_prop_id(&crtc->base, ctm_id));
+}
+
 enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc)
 {
struct drm_encoder *encoder;
@@ -1575,6 +1587,8 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, 
struct drm_plane *plane,
 {
struct drm_crtc *crtc = NULL;
struct dpu_crtc *dpu_crtc = NULL;
+   struct msm_drm_private *priv = dev->dev_private;
+   struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
int i;
 
dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL);
@@ -1604,7 +1618,8 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, 
struct drm_plane *plane,
 
drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
 
-   drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
+   if (dpu_kms->catalog->dspp && drm_crtc_index(crtc) == 0)
+   drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
 
/* save user friendly CRTC name for later */
snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 539b68b..164208e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -240,6 +240,29 @@ static inline int dpu_crtc_frame_pending(struct drm_crtc 
*crtc)
 }
 
 /**
+ * find_prop_id - find the property for the drm object
+ * @obj: Pointer to drm object
+ * @prop_id: Property id.
+ */
+static inline struct drm_property *find_prop_id(struct drm_mode_object *obj,
+  uint32_t prop_id)
+{
+   int i;
+
+   for (i = 0; i < obj->properties->count; i++)
+   if (obj->properties->properties[i]->base.id == prop_id)
+   return obj->properties->properties[i];
+
+   return NULL;
+}
+
+/**
+ * dpu_crtc_has_color_enabled - check if the crtc has color management enabled
+ * @crtc: Pointer to drm crtc object
+ */
+bool dpu_crtc_has_color_enabled(struct drm_crtc *crtc);
+
+/**
  * dpu_crtc_vblank - enable or disable vblanks for this crtc
  * @crtc: Pointer to drm crtc object
  * @en: true to enable vblanks, false to disable
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 9c6817b..f09b957 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -545,7 +545,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
 static struct msm_display_topology dpu_encoder_get_topology(
struct dpu_encoder_virt *dpu_enc,
struct dpu_kms *dpu_kms,
-   struct drm_display_mode *mode)
+   struct drm_display_mode *mode,
+   struct drm_crtc *crtc)
 {
struct msm_display_topology topology = {0};
int i, intf_count = 0;
@@ -573,11 +574,9 @@ static struct msm_display_topology 
dpu_encoder_get_topology(
else
topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
 
-   if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
-   if (dpu_kms->catalog->dspp &&
- 

Re: [Freedreno] [v7] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280

[Kalyan Thota]

>-Original Message-
>From: Marijn Suijten 
>Sent: Tuesday, November 1, 2022 5:13 PM
>To: Kalyan Thota (QUIC) 
>Cc: dri-de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
>freedreno@lists.freedesktop.org; devicet...@vger.kernel.org; linux-
>ker...@vger.kernel.org; robdcl...@gmail.com; diand...@chromium.org;
>swb...@chromium.org; Vinod Polimera (QUIC) ;
>dmitry.barysh...@linaro.org; Abhinav Kumar (QUIC)
>
>Subject: Re: [v7] drm/msm/disp/dpu1: add support for dspp sub block flush in
>sc7280
>
>WARNING: This email originated from outside of Qualcomm. Please be wary of
>any links or attachments, and do not enable macros.
>
>On 2022-11-01 03:57:05, Kalyan Thota wrote:
>> Flush mechanism for DSPP blocks has changed in sc7280 family, it
>> allows individual sub blocks to be flushed in coordination with master
>> flush control.
>>
>> Representation: master_flush && (PCC_flush | IGC_flush .. etc )
>>
>> This change adds necessary support for the above design.
>>
>> Changes in v1:
>> - Few nits (Doug, Dmitry)
>> - Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry)
>>
>> Changes in v2:
>> - Move the address offset to flush macro (Dmitry)
>> - Seperate ops for the sub block flush (Dmitry)
>>
>> Changes in v3:
>> - Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry)
>>
>> Changes in v4:
>> - Use shorter version for unsigned int (Stephen)
>>
>> Changes in v5:
>> - Spurious patch please ignore.
>>
>> Changes in v6:
>> - Add SOB tag (Doug, Dmitry)
>>
>> Changes in v7:
>> - Cache flush mask per dspp (Dmitry)
>> - Few nits (Marijn)
>
>Thanks, but it seems like you skipped some of them.  I'll point them out again 
>this
>time, including some new formatting issues.
>
>>
>> Signed-off-by: Kalyan Thota 
>> ---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  2 +-
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  5 ++-
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  4 +++
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 46
>--
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |  7 ++--
>>  5 files changed, 58 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> index 601d687..4170fbe 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> @@ -766,7 +766,7 @@ static void _dpu_crtc_setup_cp_blocks(struct
>> drm_crtc *crtc)
>>
>>   /* stage config flush mask */
>>   ctl->ops.update_pending_flush_dspp(ctl,
>> - mixer[i].hw_dspp->idx);
>> + mixer[i].hw_dspp->idx, DPU_DSPP_PCC);
>>   }
>>  }
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index 27f029f..0eecb2f 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -65,7 +65,10 @@
>>   (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
>>
>>  #define CTL_SC7280_MASK \
>> - (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) |
>BIT(DPU_CTL_VM_CFG))
>> + (BIT(DPU_CTL_ACTIVE_CFG) | \
>> +  BIT(DPU_CTL_FETCH_ACTIVE) | \
>> +  BIT(DPU_CTL_VM_CFG) | \
>> +  BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
>>
>>  #define MERGE_3D_SM8150_MASK (0)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index 38aa38a..8148e91 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -161,10 +161,12 @@ enum {
>>   * DSPP sub-blocks
>>   * @DPU_DSPP_PCC Panel color correction block
>>   * @DPU_DSPP_GC  Gamma correction block
>> + * @DPU_DSPP_IGC Inverse Gamma correction block
>
>Here.
>
>>   */
>>  enum {
>>   DPU_DSPP_PCC = 0x1,
>>   DPU_DSPP_GC,
>> + DPU_DSPP_IGC,
>>   DPU_DSPP_MAX
>>  };
>>
>> @@ -191,6 +193,7 @@ enum {
>>   * @DPU_CTL_SPLIT_DISPLAY:   CTL supports video mode split display
>>   * @DPU_CTL_FETCH_ACTIVE:Active CTL for fetch HW (SSPPs)
>>   * @DPU_CTL_VM_CFG:  CTL config to support multiple VMs
>> + * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block
>> + flush
>
&g

[Freedreno] [v8] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280

[Kalyan Thota]

Flush mechanism for DSPP blocks has changed in sc7280 family, it
allows individual sub blocks to be flushed in coordination with
master flush control.

Representation: master_flush && (PCC_flush | IGC_flush .. etc )

This change adds necessary support for the above design.

Changes in v1:
- Few nits (Doug, Dmitry)
- Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry)

Changes in v2:
- Move the address offset to flush macro (Dmitry)
- Seperate ops for the sub block flush (Dmitry)

Changes in v3:
- Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry)

Changes in v4:
- Use shorter version for unsigned int (Stephen)

Changes in v5:
- Spurious patch please ignore.

Changes in v6:
- Add SOB tag (Doug, Dmitry)

Changes in v7:
- Cache flush mask per dspp (Dmitry)
- Few nits (Marijn)

Changes in v8:
- Few nits (Marijn)

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  5 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 12 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 66 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |  7 ++-
 5 files changed, 72 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 601d687..4170fbe 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -766,7 +766,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc)
 
/* stage config flush mask */
ctl->ops.update_pending_flush_dspp(ctl,
-   mixer[i].hw_dspp->idx);
+   mixer[i].hw_dspp->idx, DPU_DSPP_PCC);
}
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 27f029f..0eecb2f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -65,7 +65,10 @@
(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
 
 #define CTL_SC7280_MASK \
-   (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | 
BIT(DPU_CTL_VM_CFG))
+   (BIT(DPU_CTL_ACTIVE_CFG) | \
+BIT(DPU_CTL_FETCH_ACTIVE) | \
+BIT(DPU_CTL_VM_CFG) | \
+BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
 
 #define MERGE_3D_SM8150_MASK (0)
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 38aa38a..35f4810 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -161,10 +161,12 @@ enum {
  * DSPP sub-blocks
  * @DPU_DSPP_PCC Panel color correction block
  * @DPU_DSPP_GC  Gamma correction block
+ * @DPU_DSPP_IGC Inverse gamma correction block
  */
 enum {
DPU_DSPP_PCC = 0x1,
DPU_DSPP_GC,
+   DPU_DSPP_IGC,
DPU_DSPP_MAX
 };
 
@@ -188,16 +190,18 @@ enum {
 
 /**
  * CTL sub-blocks
- * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
- * @DPU_CTL_FETCH_ACTIVE:  Active CTL for fetch HW (SSPPs)
- * @DPU_CTL_VM_CFG:CTL config to support multiple VMs
- * @DPU_CTL_MAX
+ * @DPU_CTL_SPLIT_DISPLAY CTL supports video mode split display
+ * @DPU_CTL_FETCH_ACTIVE  Active CTL for fetch HW (SSPPs)
+ * @DPU_CTL_VM_CFGCTL config to support multiple VMs
+ * @DPU_CTL_DSPP_BLOCK_FLUSH  CTL config to support dspp sub-block flush
+ * @DPU_CTL_MAX   Maximum value
  */
 enum {
DPU_CTL_SPLIT_DISPLAY = 0x1,
DPU_CTL_ACTIVE_CFG,
DPU_CTL_FETCH_ACTIVE,
DPU_CTL_VM_CFG,
+   DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
DPU_CTL_MAX
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index a35ecb6..29821ea 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -28,22 +28,23 @@
 #define   CTL_INTF_ACTIVE   0x0F4
 #define   CTL_MERGE_3D_FLUSH0x100
 #define   CTL_DSC_ACTIVE0x0E8
-#define   CTL_DSC_FLUSH0x104
+#define   CTL_DSC_FLUSH 0x104
 #define   CTL_WB_FLUSH  0x108
 #define   CTL_INTF_FLUSH0x110
 #define   CTL_INTF_MASTER   0x134
 #define   CTL_FETCH_PIPE_ACTIVE 0x0FC
+#define   CTL_DSPP_n_FLUSH(n)   ((0x13C) + ((n) * 4))
 
-#define CTL_MIXER_BORDER_OUTBIT(24)
-#define CTL_FLUSH_MASK_CTL  BIT(17)
+#define   CTL_MIXER_BORDER_OUT  BIT(24)
+#define   CTL_FLUSH_MASK_CTLBIT(17)
 
-#define DPU_REG_RESET_TIMEOUT_US2000
-#define  MERGE_3D_IDX   23
-#define  DSC_IDX22
-#define  INTF_IDX   31
-#define WB_IDX  16
-#define CTL_INVALID_BIT 0x
-#define CTL_DEFAULT_GROUP_ID   0xf
+#define   DPU_REG_RESET_TIMEOUT_US  

[Freedreno] [PATCH 1/4] drm/msm/disp/dpu1: pin 1 crtc to 1 encoder

[Kalyan Thota]

Pin each crtc with one encoder. This arrangement will
disallow crtc switching between encoders and also will
facilitate to advertise certain features on crtc based
on encoder type.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 7a5fabc..552a89c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -798,19 +798,19 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
max_crtc_count = min(max_crtc_count, primary_planes_idx);
 
/* Create one CRTC per encoder */
+   encoder = list_first_entry(&(dev)->mode_config.encoder_list,
+   struct drm_encoder, head);
for (i = 0; i < max_crtc_count; i++) {
crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]);
-   if (IS_ERR(crtc)) {
+   if (IS_ERR(crtc) || IS_ERR_OR_NULL(encoder)) {
ret = PTR_ERR(crtc);
return ret;
}
priv->crtcs[priv->num_crtcs++] = crtc;
+   encoder->possible_crtcs = 1 << drm_crtc_index(crtc);
+   encoder = list_next_entry(encoder, head);
}
 
-   /* All CRTCs are compatible with all encoders */
-   drm_for_each_encoder(encoder, dev)
-   encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
-
return 0;
 }
 
-- 
2.7.4

[Freedreno] [PATCH 2/4] drm/msm/disp/dpu1: populate disp_info if an interface is external

[Kalyan Thota]

DRM encoder type is same for eDP and DP (DRM_MODE_ENCODER_TMDS)
populate is_external information in the disp_info so as to
differentiate between eDP and DP on the DPU encoder side.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 20 +---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 14 +++---
 drivers/gpu/drm/msm/dp/dp_display.c |  5 +
 drivers/gpu/drm/msm/msm_drv.h   |  7 ++-
 4 files changed, 39 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 9c6817b..5d6ad1f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2412,7 +2412,7 @@ int dpu_encoder_setup(struct drm_device *dev, struct 
drm_encoder *enc,
struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
struct drm_encoder *drm_enc = NULL;
struct dpu_encoder_virt *dpu_enc = NULL;
-   int ret = 0;
+   int ret = 0, intf_i;
 
dpu_enc = to_dpu_encoder_virt(enc);
 
@@ -2424,13 +2424,16 @@ int dpu_encoder_setup(struct drm_device *dev, struct 
drm_encoder *enc,
timer_setup(&dpu_enc->frame_done_timer,
dpu_encoder_frame_done_timeout, 0);
 
+   intf_i = disp_info->h_tile_instance[0];
if (disp_info->intf_type == DRM_MODE_ENCODER_DSI)
timer_setup(&dpu_enc->vsync_event_timer,
dpu_encoder_vsync_event_handler,
0);
-   else if (disp_info->intf_type == DRM_MODE_ENCODER_TMDS)
+   else if (disp_info->intf_type == DRM_MODE_ENCODER_TMDS) {
dpu_enc->wide_bus_en = msm_dp_wide_bus_available(
-   priv->dp[disp_info->h_tile_instance[0]]);
+   priv->dp[intf_i]);
+   disp_info->is_external = msm_dp_is_external(priv->dp[intf_i]);
+   }
 
INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
dpu_encoder_off_work);
@@ -2455,6 +2458,17 @@ int dpu_encoder_setup(struct drm_device *dev, struct 
drm_encoder *enc,
 
 }
 
+bool dpu_encoder_is_external(struct drm_encoder *drm_enc)
+{
+   struct dpu_encoder_virt *dpu_enc;
+
+   if (!drm_enc)
+   return false;
+
+   dpu_enc = to_dpu_encoder_virt(drm_enc);
+   return dpu_enc->disp_info.is_external;
+}
+
 struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
int drm_enc_mode)
 {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 9e7236e..43f0d8b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -25,16 +25,18 @@
  * @num_of_h_tiles: Number of horizontal tiles in case of split interface
  * @h_tile_instance:Controller instance used per tile. Number of elements 
is
  *  based on num_of_h_tiles
- * @is_cmd_modeBoolean to indicate if the CMD mode is requested
+ * @is_cmd_mode:Boolean to indicate if the CMD mode is requested
+ * @is_external:Boolean to indicate if the intf is external
  * @is_te_using_watchdog_timer:  Boolean to indicate watchdog TE is
- *  used instead of panel TE in cmd mode panels
- * @dsc:   DSC configuration data for DSC-enabled displays
+ *  used instead of panel TE in cmd mode panels
+ * @dsc:DSC configuration data for DSC-enabled displays
  */
 struct msm_display_info {
int intf_type;
uint32_t num_of_h_tiles;
uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
bool is_cmd_mode;
+   bool is_external;
bool is_te_using_watchdog_timer;
struct drm_dsc_config *dsc;
 };
@@ -128,6 +130,12 @@ enum dpu_intf_mode dpu_encoder_get_intf_mode(struct 
drm_encoder *encoder);
 void dpu_encoder_virt_runtime_resume(struct drm_encoder *encoder);
 
 /**
+ * dpu_encoder_is_external - find if the encoder is of type external
+ * @drm_enc:Pointer to previously created drm encoder structure
+ */
+bool dpu_encoder_is_external(struct drm_encoder *drm_enc);
+
+/**
  * dpu_encoder_init - initialize virtual encoder object
  * @dev:Pointer to drm device structure
  * @disp_info:  Pointer to display information structure
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c 
b/drivers/gpu/drm/msm/dp/dp_display.c
index bfd0aef..0bbdcca5 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -1509,6 +1509,11 @@ bool msm_dp_wide_bus_available(const struct msm_dp 
*dp_display)
return dp->wide_bus_en;
 }
 
+bool msm_dp_is_external(const struct msm_dp *dp_display)
+{
+   return (dp_display->connector_type == DRM_MODE_CONNECTOR_DisplayPort);
+}
+
 void msm_dp_debugfs_init(struct

[Freedreno] [PATCH 3/4] drm/msm/disp/dpu1: helper function to determine if encoder is virtual

[Kalyan Thota]

Add a helper function to determine if an encoder is of type
virtual.

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h |  6 ++
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 5d6ad1f..4c56a16 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2469,6 +2469,17 @@ bool dpu_encoder_is_external(struct drm_encoder *drm_enc)
return dpu_enc->disp_info.is_external;
 }
 
+bool dpu_encoder_is_virtual(struct drm_encoder *drm_enc)
+{
+   struct dpu_encoder_virt *dpu_enc;
+
+   if (!drm_enc)
+   return false;
+
+   dpu_enc = to_dpu_encoder_virt(drm_enc);
+   return (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_VIRTUAL);
+}
+
 struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
int drm_enc_mode)
 {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 43f0d8b..6ae3c62 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -136,6 +136,12 @@ void dpu_encoder_virt_runtime_resume(struct drm_encoder 
*encoder);
 bool dpu_encoder_is_external(struct drm_encoder *drm_enc);
 
 /**
+ * dpu_encoder_is_virtual - find if the encoder is of type virtual.
+ * @drm_enc:Pointer to previously created drm encoder structure
+ */
+bool dpu_encoder_is_virtual(struct drm_encoder *drm_enc);
+
+/**
  * dpu_encoder_init - initialize virtual encoder object
  * @dev:Pointer to drm device structure
  * @disp_info:  Pointer to display information structure
-- 
2.7.4

[Freedreno] [PATCH 4/4] drm/msm/disp/dpu1: add color management support for the crtc

[Kalyan Thota]

Add color management support for the crtc provided there are
enough dspps that can be allocated from the catalogue

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 15 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h|  6 
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 +++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 53 +
 4 files changed, 77 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 4170fbe..6bd3a64 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -18,9 +18,11 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
+#include "../../../drm_crtc_internal.h"
 
 #include "dpu_kms.h"
 #include "dpu_hw_lm.h"
@@ -553,6 +555,17 @@ static void _dpu_crtc_complete_flip(struct drm_crtc *crtc)
spin_unlock_irqrestore(&dev->event_lock, flags);
 }
 
+bool dpu_crtc_has_color_enabled(struct drm_crtc *crtc)
+{
+   u32 ctm_id = crtc->dev->mode_config.ctm_property->base.id;
+   u32 gamma_id = crtc->dev->mode_config.gamma_lut_property->base.id;
+   u32 degamma_id = crtc->dev->mode_config.degamma_lut_property->base.id;
+
+   return !!(drm_mode_obj_find_prop_id(&crtc->base, ctm_id) ||
+  drm_mode_obj_find_prop_id(&crtc->base, gamma_id) ||
+  drm_mode_obj_find_prop_id(&crtc->base, degamma_id));
+}
+
 enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc)
 {
struct drm_encoder *encoder;
@@ -1604,8 +1617,6 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, 
struct drm_plane *plane,
 
drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
 
-   drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
-
/* save user friendly CRTC name for later */
snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 539b68b..8bac395 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -300,4 +300,10 @@ static inline enum dpu_crtc_client_type 
dpu_crtc_get_client_type(
return crtc && crtc->state ? RT_CLIENT : NRT_CLIENT;
 }
 
+/**
+ * dpu_crtc_has_color_enabled - check if the crtc has color management enabled
+ * @crtc: Pointer to drm crtc object
+ */
+bool dpu_crtc_has_color_enabled(struct drm_crtc *crtc);
+
 #endif /* _DPU_CRTC_H_ */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 4c56a16..ebc3f25 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -545,7 +545,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
 static struct msm_display_topology dpu_encoder_get_topology(
struct dpu_encoder_virt *dpu_enc,
struct dpu_kms *dpu_kms,
-   struct drm_display_mode *mode)
+   struct drm_display_mode *mode,
+   struct drm_crtc *crtc)
 {
struct msm_display_topology topology = {0};
int i, intf_count = 0;
@@ -573,11 +574,9 @@ static struct msm_display_topology 
dpu_encoder_get_topology(
else
topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
 
-   if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
-   if (dpu_kms->catalog->dspp &&
-   (dpu_kms->catalog->dspp_count >= topology.num_lm))
+   if (dpu_crtc_has_color_enabled(crtc) &&
+   (dpu_kms->catalog->dspp_count >= topology.num_lm))
topology.num_dspp = topology.num_lm;
-   }
 
topology.num_enc = 0;
topology.num_intf = intf_count;
@@ -643,7 +642,7 @@ static int dpu_encoder_virt_atomic_check(
}
}
 
-   topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
+   topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, 
crtc_state->crtc);
 
/* Reserve dynamic resources now. */
if (!ret) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 552a89c..47a73fa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -537,6 +538,44 @@ static void dpu_kms_wait_flush(struct msm_kms *kms, 
unsigned crtc_mask)
dpu_kms_wait_for_commit_done(kms, crtc);
 }
 
+/**
+ * _dpu_kms_possible_dspps - Evaluate how many dspps pairs can be facilitated
+ to enable color features for 

Re: [Freedreno] [PATCH 4/4] drm/msm/disp/dpu1: add color management support for the crtc

[Kalyan Thota]

>-Original Message-
>From: Dmitry Baryshkov 
>Sent: Wednesday, November 9, 2022 6:02 PM
>To: Kalyan Thota (QUIC) ; dri-
>de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
>freedreno@lists.freedesktop.org; devicet...@vger.kernel.org
>Cc: linux-ker...@vger.kernel.org; robdcl...@chromium.org;
>diand...@chromium.org; swb...@chromium.org; Vinod Polimera (QUIC)
>; Abhinav Kumar (QUIC)
>
>Subject: Re: [PATCH 4/4] drm/msm/disp/dpu1: add color management support
>for the crtc
>
>WARNING: This email originated from outside of Qualcomm. Please be wary of
>any links or attachments, and do not enable macros.
>
>On 09/11/2022 15:16, Kalyan Thota wrote:
>> Add color management support for the crtc provided there are enough
>> dspps that can be allocated from the catalogue
>>
>> Signed-off-by: Kalyan Thota 
>> ---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 15 ++--
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h|  6 
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 +++---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 53
>+
>>   4 files changed, 77 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> index 4170fbe..6bd3a64 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> @@ -18,9 +18,11 @@
>>   #include 
>>   #include 
>>   #include 
>> +#include 
>>   #include 
>>   #include 
>>   #include 
>> +#include "../../../drm_crtc_internal.h"
>
>If it's internal, it is not supposed to be used by other parties, including 
>the msm
>drm. At least a comment why you are including this file would be helpful.
>
This header file was included to make use of " drm_mode_obj_find_prop_id" 
function from DRM framework.
Should I add a comment near function definition ?
>>
>>   #include "dpu_kms.h"
>>   #include "dpu_hw_lm.h"
>> @@ -553,6 +555,17 @@ static void _dpu_crtc_complete_flip(struct drm_crtc
>*crtc)
>>   spin_unlock_irqrestore(&dev->event_lock, flags);
>>   }
>>
>> +bool dpu_crtc_has_color_enabled(struct drm_crtc *crtc) {
>> + u32 ctm_id = crtc->dev->mode_config.ctm_property->base.id;
>> + u32 gamma_id = crtc->dev->mode_config.gamma_lut_property->base.id;
>> + u32 degamma_id =
>> +crtc->dev->mode_config.degamma_lut_property->base.id;
>> +
>> + return !!(drm_mode_obj_find_prop_id(&crtc->base, ctm_id) ||
>> +drm_mode_obj_find_prop_id(&crtc->base, gamma_id) ||
>> +drm_mode_obj_find_prop_id(&crtc->base, degamma_id));
>> +}
>> +
>>   enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc)
>>   {
>>   struct drm_encoder *encoder;
>> @@ -1604,8 +1617,6 @@ struct drm_crtc *dpu_crtc_init(struct drm_device
>> *dev, struct drm_plane *plane,
>>
>>   drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
>>
>> - drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
>> -
>>   /* save user friendly CRTC name for later */
>>   snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u",
>> crtc->base.id);
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> index 539b68b..8bac395 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> @@ -300,4 +300,10 @@ static inline enum dpu_crtc_client_type
>dpu_crtc_get_client_type(
>>   return crtc && crtc->state ? RT_CLIENT : NRT_CLIENT;
>>   }
>>
>> +/**
>> + * dpu_crtc_has_color_enabled - check if the crtc has color
>> +management enabled
>> + * @crtc: Pointer to drm crtc object
>> + */
>> +bool dpu_crtc_has_color_enabled(struct drm_crtc *crtc);
>> +
>>   #endif /* _DPU_CRTC_H_ */
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> index 4c56a16..ebc3f25 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> @@ -545,7 +545,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder
>*drm_enc)
>>   static struct msm_display_topology dpu_encoder_get_topology(
>>   struct dpu_encoder_virt *dpu_enc,
>>   struct dpu_kms *dpu_kms,
>> - struct d

Re: [Freedreno] [PATCH 4/4] drm/msm/disp/dpu1: add color management support for the crtc

[Kalyan Thota]

>-Original Message-
>From: Dmitry Baryshkov 
>Sent: Wednesday, November 9, 2022 6:02 PM
>To: Kalyan Thota (QUIC) ; dri-
>de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
>freedreno@lists.freedesktop.org; devicet...@vger.kernel.org
>Cc: linux-ker...@vger.kernel.org; robdcl...@chromium.org;
>diand...@chromium.org; swb...@chromium.org; Vinod Polimera (QUIC)
>; Abhinav Kumar (QUIC)
>
>Subject: Re: [PATCH 4/4] drm/msm/disp/dpu1: add color management support
>for the crtc
>
>WARNING: This email originated from outside of Qualcomm. Please be wary of
>any links or attachments, and do not enable macros.
>
>On 09/11/2022 15:16, Kalyan Thota wrote:
>> Add color management support for the crtc provided there are enough
>> dspps that can be allocated from the catalogue
>>
>> Signed-off-by: Kalyan Thota 
>> ---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 15 ++--
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h|  6 
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 +++---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 53
>+
>>   4 files changed, 77 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> index 4170fbe..6bd3a64 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> @@ -18,9 +18,11 @@
>>   #include 
>>   #include 
>>   #include 
>> +#include 
>>   #include 
>>   #include 
>>   #include 
>> +#include "../../../drm_crtc_internal.h"
>
>If it's internal, it is not supposed to be used by other parties, including 
>the msm
>drm. At least a comment why you are including this file would be helpful.
>
>>
>>   #include "dpu_kms.h"
>>   #include "dpu_hw_lm.h"
>> @@ -553,6 +555,17 @@ static void _dpu_crtc_complete_flip(struct drm_crtc
>*crtc)
>>   spin_unlock_irqrestore(&dev->event_lock, flags);
>>   }
>>
>> +bool dpu_crtc_has_color_enabled(struct drm_crtc *crtc) {
>> + u32 ctm_id = crtc->dev->mode_config.ctm_property->base.id;
>> + u32 gamma_id = crtc->dev->mode_config.gamma_lut_property->base.id;
>> + u32 degamma_id =
>> +crtc->dev->mode_config.degamma_lut_property->base.id;
>> +
>> + return !!(drm_mode_obj_find_prop_id(&crtc->base, ctm_id) ||
>> +drm_mode_obj_find_prop_id(&crtc->base, gamma_id) ||
>> +drm_mode_obj_find_prop_id(&crtc->base, degamma_id));
>> +}
>> +
>>   enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc)
>>   {
>>   struct drm_encoder *encoder;
>> @@ -1604,8 +1617,6 @@ struct drm_crtc *dpu_crtc_init(struct drm_device
>> *dev, struct drm_plane *plane,
>>
>>   drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
>>
>> - drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
>> -
>>   /* save user friendly CRTC name for later */
>>   snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u",
>> crtc->base.id);
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> index 539b68b..8bac395 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> @@ -300,4 +300,10 @@ static inline enum dpu_crtc_client_type
>dpu_crtc_get_client_type(
>>   return crtc && crtc->state ? RT_CLIENT : NRT_CLIENT;
>>   }
>>
>> +/**
>> + * dpu_crtc_has_color_enabled - check if the crtc has color
>> +management enabled
>> + * @crtc: Pointer to drm crtc object
>> + */
>> +bool dpu_crtc_has_color_enabled(struct drm_crtc *crtc);
>> +
>>   #endif /* _DPU_CRTC_H_ */
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> index 4c56a16..ebc3f25 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> @@ -545,7 +545,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder
>*drm_enc)
>>   static struct msm_display_topology dpu_encoder_get_topology(
>>   struct dpu_encoder_virt *dpu_enc,
>>   struct dpu_kms *dpu_kms,
>> - struct drm_display_mode *mode)
>> + struct drm_display_mode *mode,
>> + struct drm_crtc *crtc)
&

Re: [Freedreno] [PATCH 4/4] drm/msm/disp/dpu1: add color management support for the crtc

[Kalyan Thota]

>-Original Message-
>From: Kalyan Thota 
>Sent: Wednesday, November 9, 2022 6:53 PM
>To: dmitry.barysh...@linaro.org; Kalyan Thota (QUIC)
>; dri-de...@lists.freedesktop.org; linux-arm-
>m...@vger.kernel.org; freedreno@lists.freedesktop.org;
>devicet...@vger.kernel.org
>Cc: linux-ker...@vger.kernel.org; robdcl...@chromium.org;
>diand...@chromium.org; swb...@chromium.org; Vinod Polimera (QUIC)
>; Abhinav Kumar (QUIC)
>
>Subject: RE: [PATCH 4/4] drm/msm/disp/dpu1: add color management support
>for the crtc
>
>
>
>>-Original Message-
>>From: Dmitry Baryshkov 
>>Sent: Wednesday, November 9, 2022 6:02 PM
>>To: Kalyan Thota (QUIC) ; dri-
>>de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
>>freedreno@lists.freedesktop.org; devicet...@vger.kernel.org
>>Cc: linux-ker...@vger.kernel.org; robdcl...@chromium.org;
>>diand...@chromium.org; swb...@chromium.org; Vinod Polimera (QUIC)
>>; Abhinav Kumar (QUIC)
>>
>>Subject: Re: [PATCH 4/4] drm/msm/disp/dpu1: add color management
>>support for the crtc
>>
>>WARNING: This email originated from outside of Qualcomm. Please be wary
>>of any links or attachments, and do not enable macros.
>>
>>On 09/11/2022 15:16, Kalyan Thota wrote:
>>> Add color management support for the crtc provided there are enough
>>> dspps that can be allocated from the catalogue
>>>
>>> Signed-off-by: Kalyan Thota 
>>> ---
>>>   drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 15 ++--
>>>   drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h|  6 
>>>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 +++---
>>>   drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 53
>>+
>>>   4 files changed, 77 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>> index 4170fbe..6bd3a64 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>> @@ -18,9 +18,11 @@
>>>   #include 
>>>   #include 
>>>   #include 
>>> +#include 
>>>   #include 
>>>   #include 
>>>   #include 
>>> +#include "../../../drm_crtc_internal.h"
>>
>>If it's internal, it is not supposed to be used by other parties,
>>including the msm drm. At least a comment why you are including this file 
>>would
>be helpful.
>>
>>>
>>>   #include "dpu_kms.h"
>>>   #include "dpu_hw_lm.h"
>>> @@ -553,6 +555,17 @@ static void _dpu_crtc_complete_flip(struct
>>> drm_crtc
>>*crtc)
>>>   spin_unlock_irqrestore(&dev->event_lock, flags);
>>>   }
>>>
>>> +bool dpu_crtc_has_color_enabled(struct drm_crtc *crtc) {
>>> + u32 ctm_id = crtc->dev->mode_config.ctm_property->base.id;
>>> + u32 gamma_id = crtc->dev->mode_config.gamma_lut_property->base.id;
>>> + u32 degamma_id =
>>> +crtc->dev->mode_config.degamma_lut_property->base.id;
>>> +
>>> + return !!(drm_mode_obj_find_prop_id(&crtc->base, ctm_id) ||
>>> +drm_mode_obj_find_prop_id(&crtc->base, gamma_id) ||
>>> +drm_mode_obj_find_prop_id(&crtc->base, degamma_id));
>>> +}
>>> +
>>>   enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc)
>>>   {
>>>   struct drm_encoder *encoder;
>>> @@ -1604,8 +1617,6 @@ struct drm_crtc *dpu_crtc_init(struct
>>> drm_device *dev, struct drm_plane *plane,
>>>
>>>   drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
>>>
>>> - drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
>>> -
>>>   /* save user friendly CRTC name for later */
>>>   snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u",
>>> crtc->base.id);
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>>> index 539b68b..8bac395 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>>> @@ -300,4 +300,10 @@ static inline enum dpu_crtc_client_type
>>dpu_crtc_get_client_type(
>>>   return crtc && crtc->state ? RT_CLIENT : NRT_CLIENT;
>>>   }
>>>
>>> +/**
>>> + * dpu_crtc_has_color_enabled - check if the crtc has color
>>> +ma

Re: [Freedreno] [PATCH 4/4] drm/msm/disp/dpu1: add color management support for the crtc

[Kalyan Thota]

>-Original Message-
>From: Dmitry Baryshkov 
>Sent: Wednesday, November 9, 2022 6:02 PM
>To: Kalyan Thota (QUIC) ; dri-
>de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
>freedreno@lists.freedesktop.org; devicet...@vger.kernel.org
>Cc: linux-ker...@vger.kernel.org; robdcl...@chromium.org;
>diand...@chromium.org; swb...@chromium.org; Vinod Polimera (QUIC)
>; Abhinav Kumar (QUIC)
>
>Subject: Re: [PATCH 4/4] drm/msm/disp/dpu1: add color management support
>for the crtc
>
>WARNING: This email originated from outside of Qualcomm. Please be wary of
>any links or attachments, and do not enable macros.
>
>On 09/11/2022 15:16, Kalyan Thota wrote:
>> Add color management support for the crtc provided there are enough
>> dspps that can be allocated from the catalogue
>>
>> Signed-off-by: Kalyan Thota 
>> ---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 15 ++--
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h|  6 
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 +++---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 53
>+
>>   4 files changed, 77 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> index 4170fbe..6bd3a64 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> @@ -18,9 +18,11 @@
>>   #include 
>>   #include 
>>   #include 
>> +#include 
>>   #include 
>>   #include 
>>   #include 
>> +#include "../../../drm_crtc_internal.h"
>
>If it's internal, it is not supposed to be used by other parties, including 
>the msm
>drm. At least a comment why you are including this file would be helpful.
>
>>
>>   #include "dpu_kms.h"
>>   #include "dpu_hw_lm.h"
>> @@ -553,6 +555,17 @@ static void _dpu_crtc_complete_flip(struct drm_crtc
>*crtc)
>>   spin_unlock_irqrestore(&dev->event_lock, flags);
>>   }
>>
>> +bool dpu_crtc_has_color_enabled(struct drm_crtc *crtc) {
>> + u32 ctm_id = crtc->dev->mode_config.ctm_property->base.id;
>> + u32 gamma_id = crtc->dev->mode_config.gamma_lut_property->base.id;
>> + u32 degamma_id =
>> +crtc->dev->mode_config.degamma_lut_property->base.id;
>> +
>> + return !!(drm_mode_obj_find_prop_id(&crtc->base, ctm_id) ||
>> +drm_mode_obj_find_prop_id(&crtc->base, gamma_id) ||
>> +drm_mode_obj_find_prop_id(&crtc->base, degamma_id));
>> +}
>> +
>>   enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc)
>>   {
>>   struct drm_encoder *encoder;
>> @@ -1604,8 +1617,6 @@ struct drm_crtc *dpu_crtc_init(struct drm_device
>> *dev, struct drm_plane *plane,
>>
>>   drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
>>
>> - drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
>> -
>>   /* save user friendly CRTC name for later */
>>   snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u",
>> crtc->base.id);
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> index 539b68b..8bac395 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> @@ -300,4 +300,10 @@ static inline enum dpu_crtc_client_type
>dpu_crtc_get_client_type(
>>   return crtc && crtc->state ? RT_CLIENT : NRT_CLIENT;
>>   }
>>
>> +/**
>> + * dpu_crtc_has_color_enabled - check if the crtc has color
>> +management enabled
>> + * @crtc: Pointer to drm crtc object
>> + */
>> +bool dpu_crtc_has_color_enabled(struct drm_crtc *crtc);
>> +
>>   #endif /* _DPU_CRTC_H_ */
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> index 4c56a16..ebc3f25 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> @@ -545,7 +545,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder
>*drm_enc)
>>   static struct msm_display_topology dpu_encoder_get_topology(
>>   struct dpu_encoder_virt *dpu_enc,
>>   struct dpu_kms *dpu_kms,
>> - struct drm_display_mode *mode)
>> + struct drm_display_mode *mode,
>> + struct drm_crtc *crtc)
>>   {
>>   st

[Freedreno] [v9] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280

[Kalyan Thota]

Flush mechanism for DSPP blocks has changed in sc7280 family, it
allows individual sub blocks to be flushed in coordination with
master flush control.

Representation: master_flush && (PCC_flush | IGC_flush .. etc )

This change adds necessary support for the above design.

Changes in v1:
- Few nits (Doug, Dmitry)
- Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry)

Changes in v2:
- Move the address offset to flush macro (Dmitry)
- Seperate ops for the sub block flush (Dmitry)

Changes in v3:
- Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry)

Changes in v4:
- Use shorter version for unsigned int (Stephen)

Changes in v5:
- Spurious patch please ignore.

Changes in v6:
- Add SOB tag (Doug, Dmitry)

Changes in v7:
- Cache flush mask per dspp (Dmitry)
- Few nits (Marijn)

Changes in v8:
- Few nits (Marijn)

Changes in v9:
- use DSPP enum while accessing flush mask to make it readable (Dmitry)
- Few nits (Dmitry)

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  5 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  4 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 64 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |  5 +-
 5 files changed, 65 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 601d687..4170fbe 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -766,7 +766,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc)
 
/* stage config flush mask */
ctl->ops.update_pending_flush_dspp(ctl,
-   mixer[i].hw_dspp->idx);
+   mixer[i].hw_dspp->idx, DPU_DSPP_PCC);
}
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 27f029f..0eecb2f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -65,7 +65,10 @@
(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
 
 #define CTL_SC7280_MASK \
-   (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | 
BIT(DPU_CTL_VM_CFG))
+   (BIT(DPU_CTL_ACTIVE_CFG) | \
+BIT(DPU_CTL_FETCH_ACTIVE) | \
+BIT(DPU_CTL_VM_CFG) | \
+BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
 
 #define MERGE_3D_SM8150_MASK (0)
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 38aa38a..126ee37 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -161,10 +161,12 @@ enum {
  * DSPP sub-blocks
  * @DPU_DSPP_PCC Panel color correction block
  * @DPU_DSPP_GC  Gamma correction block
+ * @DPU_DSPP_IGC Inverse gamma correction block
  */
 enum {
DPU_DSPP_PCC = 0x1,
DPU_DSPP_GC,
+   DPU_DSPP_IGC,
DPU_DSPP_MAX
 };
 
@@ -191,6 +193,7 @@ enum {
  * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
  * @DPU_CTL_FETCH_ACTIVE:  Active CTL for fetch HW (SSPPs)
  * @DPU_CTL_VM_CFG:CTL config to support multiple VMs
+ * @DPU_CTL_DSPP_BLOCK_FLUSH  CTL config to support dspp sub-block flush
  * @DPU_CTL_MAX
  */
 enum {
@@ -198,6 +201,7 @@ enum {
DPU_CTL_ACTIVE_CFG,
DPU_CTL_FETCH_ACTIVE,
DPU_CTL_VM_CFG,
+   DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
DPU_CTL_MAX
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index a35ecb6..0ee8220 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -28,22 +28,23 @@
 #define   CTL_INTF_ACTIVE   0x0F4
 #define   CTL_MERGE_3D_FLUSH0x100
 #define   CTL_DSC_ACTIVE0x0E8
-#define   CTL_DSC_FLUSH0x104
+#define   CTL_DSC_FLUSH 0x104
 #define   CTL_WB_FLUSH  0x108
 #define   CTL_INTF_FLUSH0x110
 #define   CTL_INTF_MASTER   0x134
 #define   CTL_FETCH_PIPE_ACTIVE 0x0FC
+#define   CTL_DSPP_n_FLUSH(n)   ((0x13C) + ((n) * 4))
 
-#define CTL_MIXER_BORDER_OUTBIT(24)
-#define CTL_FLUSH_MASK_CTL  BIT(17)
+#define   CTL_MIXER_BORDER_OUT  BIT(24)
+#define   CTL_FLUSH_MASK_CTLBIT(17)
 
-#define DPU_REG_RESET_TIMEOUT_US2000
-#define  MERGE_3D_IDX   23
-#define  DSC_IDX22
-#define  INTF_IDX   31
-#define WB_IDX  16
-#define CTL_INVALID_BIT 0x
-#define CTL_DEFAULT_GROUP_ID   0xf
+#define   DPU_REG_RESET_TIMEOUT_US  2000
+#define   MERGE_3D_IDX  23
+#define   DSC_IDX   22
+#define   INTF_IDX  31
+#define   WB_IDX  

[Freedreno] [v1] drm/msm/disp/dpu1: pin 1 crtc to 1 encoder

[Kalyan Thota]

Pin each crtc with one encoder. This arrangement will
disallow crtc switching between encoders and also will
facilitate to advertise certain features on crtc based
on encoder type.

Changes in v1:
- use drm_for_each_encoder macro while iterating through
  encoder list (Dmitry)

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 21 +++--
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 7a5fabc..0d94eec0d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -798,19 +798,20 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
max_crtc_count = min(max_crtc_count, primary_planes_idx);
 
/* Create one CRTC per encoder */
-   for (i = 0; i < max_crtc_count; i++) {
-   crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]);
-   if (IS_ERR(crtc)) {
-   ret = PTR_ERR(crtc);
-   return ret;
+   i = 0;
+   drm_for_each_encoder(encoder, dev) {
+   if (i < max_crtc_count) {
+   crtc = dpu_crtc_init(dev, primary_planes[i], 
cursor_planes[i]);
+   if (IS_ERR(crtc)) {
+   ret = PTR_ERR(crtc);
+   return ret;
+   }
+   priv->crtcs[priv->num_crtcs++] = crtc;
+   encoder->possible_crtcs = 1 << drm_crtc_index(crtc);
}
-   priv->crtcs[priv->num_crtcs++] = crtc;
+   i++;
}
 
-   /* All CRTCs are compatible with all encoders */
-   drm_for_each_encoder(encoder, dev)
-   encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
-
return 0;
 }
 
-- 
2.7.4

[Freedreno] [v1] drm/msm/disp/dpu1: populate disp_info with connector type

[Kalyan Thota]

Populate disp_info with connector type. Since DRM encoder type
for few encoders can be similar (like eDP and DP) this information
will be useful to differentiate interfaces.

Changes in v1:
- add connector type in the disp_info (Dmitry)
- add helper functions to know encoder type
- update commit text reflecting the change

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 44 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 26 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  2 ++
 drivers/gpu/drm/msm/dp/dp_display.c |  5 
 drivers/gpu/drm/msm/msm_drv.h   |  7 -
 5 files changed, 77 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 9c6817b..c9058aa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -217,6 +217,40 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
 };
 
+bool dpu_encoder_is_external(struct drm_encoder *drm_enc)
+{
+   struct dpu_encoder_virt *dpu_enc;
+
+   if (!drm_enc)
+   return false;
+
+   dpu_enc = to_dpu_encoder_virt(drm_enc);
+   return (dpu_enc->disp_info.connector_type ==
+   DRM_MODE_CONNECTOR_DisplayPort);
+}
+
+bool dpu_encoder_is_virtual(struct drm_encoder *drm_enc)
+{
+   struct dpu_encoder_virt *dpu_enc;
+
+   if (!drm_enc)
+   return false;
+
+   dpu_enc = to_dpu_encoder_virt(drm_enc);
+   return (dpu_enc->disp_info.connector_type == 
DRM_MODE_CONNECTOR_WRITEBACK);
+}
+
+bool dpu_encoder_is_primary(struct drm_encoder *drm_enc)
+{
+   struct dpu_encoder_virt *dpu_enc;
+
+   if (!drm_enc)
+   return false;
+
+   dpu_enc = to_dpu_encoder_virt(drm_enc);
+   return((dpu_enc->disp_info.connector_type == DRM_MODE_CONNECTOR_DSI) ||
+   (dpu_enc->disp_info.connector_type == DRM_MODE_CONNECTOR_eDP));
+}
 
 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc)
 {
@@ -2412,7 +2446,7 @@ int dpu_encoder_setup(struct drm_device *dev, struct 
drm_encoder *enc,
struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
struct drm_encoder *drm_enc = NULL;
struct dpu_encoder_virt *dpu_enc = NULL;
-   int ret = 0;
+   int ret = 0, intf_i;
 
dpu_enc = to_dpu_encoder_virt(enc);
 
@@ -2424,13 +2458,17 @@ int dpu_encoder_setup(struct drm_device *dev, struct 
drm_encoder *enc,
timer_setup(&dpu_enc->frame_done_timer,
dpu_encoder_frame_done_timeout, 0);
 
+   intf_i = disp_info->h_tile_instance[0];
if (disp_info->intf_type == DRM_MODE_ENCODER_DSI)
timer_setup(&dpu_enc->vsync_event_timer,
dpu_encoder_vsync_event_handler,
0);
-   else if (disp_info->intf_type == DRM_MODE_ENCODER_TMDS)
+   else if (disp_info->intf_type == DRM_MODE_ENCODER_TMDS) {
dpu_enc->wide_bus_en = msm_dp_wide_bus_available(
-   priv->dp[disp_info->h_tile_instance[0]]);
+   priv->dp[intf_i]);
+   disp_info->connector_type =
+   msm_dp_get_connector_type(priv->dp[intf_i]);
+   }
 
INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
dpu_encoder_off_work);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 9e7236e..d361c5d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -25,16 +25,18 @@
  * @num_of_h_tiles: Number of horizontal tiles in case of split interface
  * @h_tile_instance:Controller instance used per tile. Number of elements 
is
  *  based on num_of_h_tiles
- * @is_cmd_modeBoolean to indicate if the CMD mode is requested
+ * @is_cmd_mode:Boolean to indicate if the CMD mode is requested
+ * @connector_type: DRM_MODE_CONNECTOR_ type
  * @is_te_using_watchdog_timer:  Boolean to indicate watchdog TE is
- *  used instead of panel TE in cmd mode panels
- * @dsc:   DSC configuration data for DSC-enabled displays
+ *  used instead of panel TE in cmd mode panels
+ * @dsc:DSC configuration data for DSC-enabled displays
  */
 struct msm_display_info {
int intf_type;
uint32_t num_of_h_tiles;
uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
bool is_cmd_mode;
+   int connector_type;
bool is_te_using_watchdog_timer;
struct drm_dsc_config *dsc;
 };
@@ -224,4 +226,22 @@ void dpu_encoder_cleanup_wb_job(struct drm_encoder 
*drm_enc,
  */

[Freedreno] [v1] drm/msm/disp/dpu1: add color management support for the crtc

[Kalyan Thota]

Add color management support for the crtc provided there are
enough dspps that can be allocated from the catalogue.

Changes in v1:
- cache color enabled state in the dpu crtc obj (Dmitry)
- simplify dspp allocation while creating crtc (Dmitry)
- register for color when crtc is created (Dmitry)

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c|  5 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h|  6 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |  7 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 53 -
 4 files changed, 64 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 4170fbe..ca4c3b3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1571,7 +1571,7 @@ static const struct drm_crtc_helper_funcs 
dpu_crtc_helper_funcs = {
 
 /* initialize crtc */
 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
-   struct drm_plane *cursor)
+   struct drm_plane *cursor, unsigned long 
features)
 {
struct drm_crtc *crtc = NULL;
struct dpu_crtc *dpu_crtc = NULL;
@@ -1583,6 +1583,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, 
struct drm_plane *plane,
 
crtc = &dpu_crtc->base;
crtc->dev = dev;
+   dpu_crtc->color_enabled = features & BIT(DPU_DSPP_PCC);
 
spin_lock_init(&dpu_crtc->spin_lock);
atomic_set(&dpu_crtc->frame_pending, 0);
@@ -1604,7 +1605,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, 
struct drm_plane *plane,
 
drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
 
-   drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
+   drm_crtc_enable_color_mgmt(crtc, 0, dpu_crtc->color_enabled, 0);
 
/* save user friendly CRTC name for later */
snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 539b68b..342f9ae 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -136,6 +136,7 @@ struct dpu_crtc_frame_event {
  * @enabled   : whether the DPU CRTC is currently enabled. updated in the
  *  commit-thread, not state-swap time which is earlier, so
  *  safe to make decisions on during VBLANK on/off work
+ * @color_enabled : whether crtc supports color management
  * @feature_list  : list of color processing features supported on a crtc
  * @active_list   : list of color processing features are active
  * @dirty_list: list of color processing features are dirty
@@ -164,7 +165,7 @@ struct dpu_crtc {
u64 play_count;
ktime_t vblank_cb_time;
bool enabled;
-
+   bool color_enabled;
struct list_head feature_list;
struct list_head active_list;
struct list_head dirty_list;
@@ -269,10 +270,11 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc);
  * @dev: dpu device
  * @plane: base plane
  * @cursor: cursor plane
+ * @features: color features
  * @Return: new crtc object or error
  */
 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
-  struct drm_plane *cursor);
+  struct drm_plane *cursor, unsigned long 
features);
 
 /**
  * dpu_crtc_register_custom_event - api for enabling/disabling crtc event
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index c9058aa..d72edb8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -579,6 +579,7 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
 static struct msm_display_topology dpu_encoder_get_topology(
struct dpu_encoder_virt *dpu_enc,
struct dpu_kms *dpu_kms,
+   struct dpu_crtc *dpu_crtc,
struct drm_display_mode *mode)
 {
struct msm_display_topology topology = {0};
@@ -607,7 +608,7 @@ static struct msm_display_topology dpu_encoder_get_topology(
else
topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
 
-   if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
+   if (dpu_crtc->color_enabled) {
if (dpu_kms->catalog->dspp &&
(dpu_kms->catalog->dspp_count >= topology.num_lm))
topology.num_dspp = topology.num_lm;
@@ -642,6 +643,7 @@ static int dpu_encoder_virt_atomic_check(
struct drm_display_mode *adj_mode;
struct msm_display_topology topology;
struct dpu_global_state *global_state;
+   struct dpu

Re: [Freedreno] [v1] drm/msm/disp/dpu1: pin 1 crtc to 1 encoder

[Kalyan Thota]

>-Original Message-
>From: Dmitry Baryshkov 
>Sent: Saturday, November 12, 2022 3:51 AM
>To: Kalyan Thota (QUIC) ; dri-
>de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
>freedreno@lists.freedesktop.org; devicet...@vger.kernel.org
>Cc: linux-ker...@vger.kernel.org; robdcl...@chromium.org;
>diand...@chromium.org; swb...@chromium.org; Vinod Polimera (QUIC)
>; Abhinav Kumar (QUIC)
>
>Subject: Re: [v1] drm/msm/disp/dpu1: pin 1 crtc to 1 encoder
>
>WARNING: This email originated from outside of Qualcomm. Please be wary of
>any links or attachments, and do not enable macros.
>
>On 11/11/2022 16:56, Kalyan Thota wrote:
>> Pin each crtc with one encoder. This arrangement will disallow crtc
>> switching between encoders and also will facilitate to advertise
>> certain features on crtc based on encoder type.
>>
>> Changes in v1:
>> - use drm_for_each_encoder macro while iterating through
>>encoder list (Dmitry)
>
>BTW: if these patches form a series, please send them so.
>
>>
>> Signed-off-by: Kalyan Thota 
>> ---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 21 +++--
>>   1 file changed, 11 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> index 7a5fabc..0d94eec0d 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> @@ -798,19 +798,20 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms
>*dpu_kms)
>>   max_crtc_count = min(max_crtc_count, primary_planes_idx);
>>
>>   /* Create one CRTC per encoder */
>> - for (i = 0; i < max_crtc_count; i++) {
>> - crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]);
>> - if (IS_ERR(crtc)) {
>> - ret = PTR_ERR(crtc);
>> - return ret;
>> + i = 0;
>> + drm_for_each_encoder(encoder, dev) {
>> + if (i < max_crtc_count) {
>
>What if max_crtc_counter < num_encoders? I think we should disallow such
>configuration. Can it happen on any of relevant platforms?
>
Yes, we don't need the below checks accounting for crtc as all the platforms in 
the catalog has sufficient resources.

max_crtc_count = min(catalog->mixer_count, num_encoders); 
This check is not needed, as mixer resource allocation will happen at 
later time, even though you have less mixers than encoders, one can turn off
the crtc and get the mixers back to free pool.

max_crtc_count = min(max_crtc_count, primary_planes_idx);
A safety check, but mostly, all the platforms are ensured that at least 
1 primary plane is available per interface.
will add WARN ON additionally

>> + crtc = dpu_crtc_init(dev, primary_planes[i], 
>> cursor_planes[i]);
>> + if (IS_ERR(crtc)) {
>> + ret = PTR_ERR(crtc);
>> + return ret;
>> + }
>> + priv->crtcs[priv->num_crtcs++] = crtc;
>> + encoder->possible_crtcs = 1 <<
>> + drm_crtc_index(crtc);
>>   }
>> - priv->crtcs[priv->num_crtcs++] = crtc;
>> + i++;
>>   }
>>
>> - /* All CRTCs are compatible with all encoders */
>> - drm_for_each_encoder(encoder, dev)
>> - encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
>> -
>>   return 0;
>>   }
>>
>
>--
>With best wishes
>Dmitry

Re: [Freedreno] [v1] drm/msm/disp/dpu1: add color management support for the crtc

[Kalyan Thota]

>-Original Message-
>From: Dmitry Baryshkov 
>Sent: Saturday, November 12, 2022 4:13 AM
>To: Kalyan Thota (QUIC) ; dri-
>de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
>freedreno@lists.freedesktop.org; devicet...@vger.kernel.org
>Cc: linux-ker...@vger.kernel.org; robdcl...@chromium.org;
>diand...@chromium.org; swb...@chromium.org; Vinod Polimera (QUIC)
>; Abhinav Kumar (QUIC)
>
>Subject: Re: [v1] drm/msm/disp/dpu1: add color management support for the
>crtc
>
>WARNING: This email originated from outside of Qualcomm. Please be wary of
>any links or attachments, and do not enable macros.
>
>On 11/11/2022 16:57, Kalyan Thota wrote:
>> Add color management support for the crtc provided there are enough
>> dspps that can be allocated from the catalogue.
>>
>> Changes in v1:
>> - cache color enabled state in the dpu crtc obj (Dmitry)
>> - simplify dspp allocation while creating crtc (Dmitry)
>> - register for color when crtc is created (Dmitry)
>>
>> Signed-off-by: Kalyan Thota 
>> ---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c|  5 +--
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h|  6 ++--
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |  7 ++--
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 53
>-
>>   4 files changed, 64 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> index 4170fbe..ca4c3b3 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> @@ -1571,7 +1571,7 @@ static const struct drm_crtc_helper_funcs
>> dpu_crtc_helper_funcs = {
>>
>>   /* initialize crtc */
>>   struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
>*plane,
>> - struct drm_plane *cursor)
>> + struct drm_plane *cursor, unsigned long
>> + features)
>>   {
>>   struct drm_crtc *crtc = NULL;
>>   struct dpu_crtc *dpu_crtc = NULL; @@ -1583,6 +1583,7 @@ struct
>> drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
>> *plane,
>>
>>   crtc = &dpu_crtc->base;
>>   crtc->dev = dev;
>> + dpu_crtc->color_enabled = features & BIT(DPU_DSPP_PCC);
>>
>>   spin_lock_init(&dpu_crtc->spin_lock);
>>   atomic_set(&dpu_crtc->frame_pending, 0); @@ -1604,7 +1605,7 @@
>> struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct
>> drm_plane *plane,
>>
>>   drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
>>
>> - drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
>> + drm_crtc_enable_color_mgmt(crtc, 0, dpu_crtc->color_enabled, 0);
>>
>>   /* save user friendly CRTC name for later */
>>   snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u",
>> crtc->base.id); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> index 539b68b..342f9ae 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> @@ -136,6 +136,7 @@ struct dpu_crtc_frame_event {
>>* @enabled   : whether the DPU CRTC is currently enabled. updated in 
>> the
>>*  commit-thread, not state-swap time which is earlier, so
>>*  safe to make decisions on during VBLANK on/off work
>> + * @color_enabled : whether crtc supports color management
>>* @feature_list  : list of color processing features supported on a crtc
>>* @active_list   : list of color processing features are active
>>* @dirty_list: list of color processing features are dirty
>> @@ -164,7 +165,7 @@ struct dpu_crtc {
>>   u64 play_count;
>>   ktime_t vblank_cb_time;
>>   bool enabled;
>> -
>> + bool color_enabled;
>>   struct list_head feature_list;
>>   struct list_head active_list;
>>   struct list_head dirty_list;
>> @@ -269,10 +270,11 @@ void dpu_crtc_complete_commit(struct drm_crtc
>*crtc);
>>* @dev: dpu device
>>* @plane: base plane
>>* @cursor: cursor plane
>> + * @features: color features
>>* @Return: new crtc object or error
>>*/
>>   struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane
>*plane,
>> -struct drm_plane *cursor);
>> +struct drm_plane *cursor, unsigned long
>> + features);
&g

[Freedreno] [PATCH v2 0/3] add color management support for the crtc

[Kalyan Thota]

Add color management support for the crtc provided there are
enough dspps that can be allocated from the catalog

Kalyan Thota (3):
  drm/msm/disp/dpu1: pin 1 crtc to 1 encoder
  drm/msm/disp/dpu1: add helper to know if display is pluggable
  drm/msm/disp/dpu1: add color management support for the crtc

 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c|  5 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h|  6 ++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 23 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h |  6 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 75 ++---
 5 files changed, 101 insertions(+), 14 deletions(-)

-- 
2.7.4

[Freedreno] [PATCH v2 1/3] drm/msm/disp/dpu1: pin 1 crtc to 1 encoder

[Kalyan Thota]

Pin each crtc with one encoder. This arrangement will
disallow crtc switching between encoders and also will
facilitate to advertise certain features on crtc based
on encoder type.

Changes in v1:
- use drm_for_each_encoder macro while iterating through
  encoder list (Dmitry)

Changes in v2:
- make sure no encoder miss to have a crtc (Dmitry)
- revisit various factors in deciding the crtc count
  such as num_mixers, num_sspp (Dmitry)

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 17 ++---
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 7a5fabc..4784db8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -763,7 +763,7 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
drm_for_each_encoder(encoder, dev)
num_encoders++;
 
-   max_crtc_count = min(catalog->mixer_count, num_encoders);
+   max_crtc_count = num_encoders;
 
/* Create the planes, keeping track of one primary/cursor per crtc */
for (i = 0; i < catalog->sspp_count; i++) {
@@ -795,22 +795,25 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
primary_planes[primary_planes_idx++] = plane;
}
 
-   max_crtc_count = min(max_crtc_count, primary_planes_idx);
+   /*
+* All the platforms should have at least 1 primary plane for an
+* encoder. The below warn should help in setting up the catalog
+*/
+   WARN_ON(num_encoders > primary_planes_idx);
 
/* Create one CRTC per encoder */
-   for (i = 0; i < max_crtc_count; i++) {
+   i = 0;
+   drm_for_each_encoder(encoder, dev) {
crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]);
if (IS_ERR(crtc)) {
ret = PTR_ERR(crtc);
return ret;
}
priv->crtcs[priv->num_crtcs++] = crtc;
+   encoder->possible_crtcs = 1 << drm_crtc_index(crtc);
+   i++;
}
 
-   /* All CRTCs are compatible with all encoders */
-   drm_for_each_encoder(encoder, dev)
-   encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
-
return 0;
 }
 
-- 
2.7.4

[Freedreno] [PATCH v2 2/3] drm/msm/disp/dpu1: add helper to know if display is pluggable

[Kalyan Thota]

Since DRM encoder type for few encoders can be similar
(like eDP and DP) find out if the interface supports HPD
from encoder bridge to differentiate between builtin
and pluggable displays.

Changes in v1:
- add connector type in the disp_info (Dmitry)
- add helper functions to know encoder type
- update commit text reflecting the change

Changes in v2:
- avoid hardcode of connector type for DSI as it may not be true (Dmitry)
- get the HPD information from encoder bridge

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 16 
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h |  6 ++
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 9c6817b..be93269 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "msm_drv.h"
 #include "dpu_kms.h"
@@ -217,6 +218,21 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
 };
 
+bool dpu_encoder_is_pluggable(struct drm_encoder *encoder)
+{
+   struct drm_bridge *bridge;
+   int ops = 0;
+
+   if (!encoder)
+   return false;
+
+   /* Get last bridge in the chain to determine pluggable state */
+   drm_for_each_bridge_in_chain(encoder, bridge)
+   if (!drm_bridge_get_next_bridge(bridge))
+   ops = bridge->ops;
+
+   return ops & DRM_BRIDGE_OP_HPD;
+}
 
 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc)
 {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 9e7236e..691ab57 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -224,4 +224,10 @@ void dpu_encoder_cleanup_wb_job(struct drm_encoder 
*drm_enc,
  */
 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc);
 
+/**
+ * dpu_encoder_is_pluggable - find if the encoder is of type pluggable
+ * @drm_enc:Pointer to previously created drm encoder structure
+ */
+bool dpu_encoder_is_pluggable(struct drm_encoder *drm_enc);
+
 #endif /* __DPU_ENCODER_H__ */
-- 
2.7.4

[Freedreno] [PATCH v2 3/3] drm/msm/disp/dpu1: add color management support for the crtc

[Kalyan Thota]

Add color management support for the crtc provided there are
enough dspps that can be allocated from the catalog.

Changes in v1:
- cache color enabled state in the dpu crtc obj (Dmitry)
- simplify dspp allocation while creating crtc (Dmitry)
- register for color when crtc is created (Dmitry)

Changes in v2:
- avoid primary encoders in the documentation (Dmitry)

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c|  5 ++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h|  6 ++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |  7 +++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 58 -
 4 files changed, 69 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 4170fbe..ca4c3b3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1571,7 +1571,7 @@ static const struct drm_crtc_helper_funcs 
dpu_crtc_helper_funcs = {
 
 /* initialize crtc */
 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
-   struct drm_plane *cursor)
+   struct drm_plane *cursor, unsigned long 
features)
 {
struct drm_crtc *crtc = NULL;
struct dpu_crtc *dpu_crtc = NULL;
@@ -1583,6 +1583,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, 
struct drm_plane *plane,
 
crtc = &dpu_crtc->base;
crtc->dev = dev;
+   dpu_crtc->color_enabled = features & BIT(DPU_DSPP_PCC);
 
spin_lock_init(&dpu_crtc->spin_lock);
atomic_set(&dpu_crtc->frame_pending, 0);
@@ -1604,7 +1605,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, 
struct drm_plane *plane,
 
drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
 
-   drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
+   drm_crtc_enable_color_mgmt(crtc, 0, dpu_crtc->color_enabled, 0);
 
/* save user friendly CRTC name for later */
snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 539b68b..342f9ae 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -136,6 +136,7 @@ struct dpu_crtc_frame_event {
  * @enabled   : whether the DPU CRTC is currently enabled. updated in the
  *  commit-thread, not state-swap time which is earlier, so
  *  safe to make decisions on during VBLANK on/off work
+ * @color_enabled : whether crtc supports color management
  * @feature_list  : list of color processing features supported on a crtc
  * @active_list   : list of color processing features are active
  * @dirty_list: list of color processing features are dirty
@@ -164,7 +165,7 @@ struct dpu_crtc {
u64 play_count;
ktime_t vblank_cb_time;
bool enabled;
-
+   bool color_enabled;
struct list_head feature_list;
struct list_head active_list;
struct list_head dirty_list;
@@ -269,10 +270,11 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc);
  * @dev: dpu device
  * @plane: base plane
  * @cursor: cursor plane
+ * @features: color features
  * @Return: new crtc object or error
  */
 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
-  struct drm_plane *cursor);
+  struct drm_plane *cursor, unsigned long 
features);
 
 /**
  * dpu_crtc_register_custom_event - api for enabling/disabling crtc event
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index be93269..7f1cfc5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -561,6 +561,7 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
 static struct msm_display_topology dpu_encoder_get_topology(
struct dpu_encoder_virt *dpu_enc,
struct dpu_kms *dpu_kms,
+   struct dpu_crtc *dpu_crtc,
struct drm_display_mode *mode)
 {
struct msm_display_topology topology = {0};
@@ -589,7 +590,7 @@ static struct msm_display_topology dpu_encoder_get_topology(
else
topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
 
-   if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
+   if (dpu_crtc->color_enabled) {
if (dpu_kms->catalog->dspp &&
(dpu_kms->catalog->dspp_count >= topology.num_lm))
topology.num_dspp = topology.num_lm;
@@ -624,6 +625,7 @@ static int dpu_encoder_virt_atomic_check(
struct drm_display_mode *adj_mode;
struct msm_display_topology topology;
st

Re: [Freedreno] [v1] drm/msm/disp/dpu1: add color management support for the crtc

[Kalyan Thota]

>-Original Message-
>From: Dmitry Baryshkov 
>Sent: Wednesday, November 16, 2022 8:37 PM
>To: Kalyan Thota ; Kalyan Thota (QUIC)
>; dri-de...@lists.freedesktop.org; linux-arm-
>m...@vger.kernel.org; freedreno@lists.freedesktop.org;
>devicet...@vger.kernel.org
>Cc: linux-ker...@vger.kernel.org; robdcl...@chromium.org;
>diand...@chromium.org; swb...@chromium.org; Vinod Polimera (QUIC)
>; Abhinav Kumar (QUIC)
>
>Subject: Re: [v1] drm/msm/disp/dpu1: add color management support for the
>crtc
>
>WARNING: This email originated from outside of Qualcomm. Please be wary of
>any links or attachments, and do not enable macros.
>
>On 16/11/2022 17:29, Kalyan Thota wrote:
>>
>>
>>> -Original Message-
>>> From: Dmitry Baryshkov 
>>> Sent: Saturday, November 12, 2022 4:13 AM
>>> To: Kalyan Thota (QUIC) ; dri-
>>> de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
>>> freedreno@lists.freedesktop.org; devicet...@vger.kernel.org
>>> Cc: linux-ker...@vger.kernel.org; robdcl...@chromium.org;
>>> diand...@chromium.org; swb...@chromium.org; Vinod Polimera (QUIC)
>>> ; Abhinav Kumar (QUIC)
>>> 
>>> Subject: Re: [v1] drm/msm/disp/dpu1: add color management support for
>>> the crtc
>>>
>>> WARNING: This email originated from outside of Qualcomm. Please be
>>> wary of any links or attachments, and do not enable macros.
>>>
>>> On 11/11/2022 16:57, Kalyan Thota wrote:
>>>> Add color management support for the crtc provided there are enough
>>>> dspps that can be allocated from the catalogue.
>>>>
>>>> Changes in v1:
>>>> - cache color enabled state in the dpu crtc obj (Dmitry)
>>>> - simplify dspp allocation while creating crtc (Dmitry)
>>>> - register for color when crtc is created (Dmitry)
>>>>
>>>> Signed-off-by: Kalyan Thota 
>>>> ---
>>>>drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c|  5 +--
>>>>drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h|  6 ++--
>>>>drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |  7 ++--
>>>>drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 53
>>> -
>>>>4 files changed, 64 insertions(+), 7 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>>> index 4170fbe..ca4c3b3 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>>>> @@ -1571,7 +1571,7 @@ static const struct drm_crtc_helper_funcs
>>>> dpu_crtc_helper_funcs = {
>>>>
>>>>/* initialize crtc */
>>>>struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct
>>>> drm_plane
>>> *plane,
>>>> - struct drm_plane *cursor)
>>>> + struct drm_plane *cursor, unsigned
>>>> + long
>>>> + features)
>>>>{
>>>>struct drm_crtc *crtc = NULL;
>>>>struct dpu_crtc *dpu_crtc = NULL; @@ -1583,6 +1583,7 @@
>>>> struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct
>>>> drm_plane *plane,
>>>>
>>>>crtc = &dpu_crtc->base;
>>>>crtc->dev = dev;
>>>> + dpu_crtc->color_enabled = features & BIT(DPU_DSPP_PCC);
>>>>
>>>>spin_lock_init(&dpu_crtc->spin_lock);
>>>>atomic_set(&dpu_crtc->frame_pending, 0); @@ -1604,7 +1605,7
>>>> @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct
>>>> drm_plane *plane,
>>>>
>>>>drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
>>>>
>>>> - drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
>>>> + drm_crtc_enable_color_mgmt(crtc, 0, dpu_crtc->color_enabled,
>>>> + 0);
>>>>
>>>>/* save user friendly CRTC name for later */
>>>>snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u",
>>>> crtc->base.id); diff --git
>>>> crtc->a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>>>> index 539b68b..342f9ae 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>>>> @@ -136,6 +136,7 @@ stru

[Freedreno] [PATCH v3 1/3] drm/msm/disp/dpu1: pin 1 crtc to 1 encoder

[Kalyan Thota]

Pin each crtc with one encoder. This arrangement will
disallow crtc switching between encoders and also will
facilitate to advertise certain features on crtc based
on encoder type.

Changes in v1:
- use drm_for_each_encoder macro while iterating through
  encoder list (Dmitry)

Changes in v2:
- make sure no encoder miss to have a crtc (Dmitry)
- revisit various factors in deciding the crtc count
  such as num_mixers, num_sspp (Dmitry)

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 17 ++---
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 7a5fabc..4784db8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -763,7 +763,7 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
drm_for_each_encoder(encoder, dev)
num_encoders++;
 
-   max_crtc_count = min(catalog->mixer_count, num_encoders);
+   max_crtc_count = num_encoders;
 
/* Create the planes, keeping track of one primary/cursor per crtc */
for (i = 0; i < catalog->sspp_count; i++) {
@@ -795,22 +795,25 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
primary_planes[primary_planes_idx++] = plane;
}
 
-   max_crtc_count = min(max_crtc_count, primary_planes_idx);
+   /*
+* All the platforms should have at least 1 primary plane for an
+* encoder. The below warn should help in setting up the catalog
+*/
+   WARN_ON(num_encoders > primary_planes_idx);
 
/* Create one CRTC per encoder */
-   for (i = 0; i < max_crtc_count; i++) {
+   i = 0;
+   drm_for_each_encoder(encoder, dev) {
crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]);
if (IS_ERR(crtc)) {
ret = PTR_ERR(crtc);
return ret;
}
priv->crtcs[priv->num_crtcs++] = crtc;
+   encoder->possible_crtcs = 1 << drm_crtc_index(crtc);
+   i++;
}
 
-   /* All CRTCs are compatible with all encoders */
-   drm_for_each_encoder(encoder, dev)
-   encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
-
return 0;
 }
 
-- 
2.7.4

[Freedreno] [PATCH v3 3/3] drm/msm/disp/dpu1: add color management support for the crtc

[Kalyan Thota]

Add color management support for the crtc provided there are
enough dspps that can be allocated from the catalog.

Changes in v1:
- cache color enabled state in the dpu crtc obj (Dmitry)
- simplify dspp allocation while creating crtc (Dmitry)
- register for color when crtc is created (Dmitry)

Changes in v2:
- avoid primary encoders in the documentation (Dmitry)

Changes in v3:
- add ctm for builtin encoders (Dmitry)

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 5 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h| 6 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 7 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 7 ++-
 4 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 4170fbe..6cacaaf 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1571,7 +1571,7 @@ static const struct drm_crtc_helper_funcs 
dpu_crtc_helper_funcs = {
 
 /* initialize crtc */
 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
-   struct drm_plane *cursor)
+   struct drm_plane *cursor, bool ctm)
 {
struct drm_crtc *crtc = NULL;
struct dpu_crtc *dpu_crtc = NULL;
@@ -1583,6 +1583,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, 
struct drm_plane *plane,
 
crtc = &dpu_crtc->base;
crtc->dev = dev;
+   dpu_crtc->color_enabled = ctm;
 
spin_lock_init(&dpu_crtc->spin_lock);
atomic_set(&dpu_crtc->frame_pending, 0);
@@ -1604,7 +1605,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, 
struct drm_plane *plane,
 
drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
 
-   drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
+   drm_crtc_enable_color_mgmt(crtc, 0, dpu_crtc->color_enabled, 0);
 
/* save user friendly CRTC name for later */
snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 539b68b..1ec9517 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -136,6 +136,7 @@ struct dpu_crtc_frame_event {
  * @enabled   : whether the DPU CRTC is currently enabled. updated in the
  *  commit-thread, not state-swap time which is earlier, so
  *  safe to make decisions on during VBLANK on/off work
+ * @color_enabled : whether crtc supports color management
  * @feature_list  : list of color processing features supported on a crtc
  * @active_list   : list of color processing features are active
  * @dirty_list: list of color processing features are dirty
@@ -164,7 +165,7 @@ struct dpu_crtc {
u64 play_count;
ktime_t vblank_cb_time;
bool enabled;
-
+   bool color_enabled;
struct list_head feature_list;
struct list_head active_list;
struct list_head dirty_list;
@@ -269,10 +270,11 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc);
  * @dev: dpu device
  * @plane: base plane
  * @cursor: cursor plane
+ * @ctm: ctm flag
  * @Return: new crtc object or error
  */
 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
-  struct drm_plane *cursor);
+  struct drm_plane *cursor, bool ctm);
 
 /**
  * dpu_crtc_register_custom_event - api for enabling/disabling crtc event
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 574f2b0..102612c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -572,6 +572,7 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
 static struct msm_display_topology dpu_encoder_get_topology(
struct dpu_encoder_virt *dpu_enc,
struct dpu_kms *dpu_kms,
+   struct dpu_crtc *dpu_crtc,
struct drm_display_mode *mode)
 {
struct msm_display_topology topology = {0};
@@ -600,7 +601,7 @@ static struct msm_display_topology dpu_encoder_get_topology(
else
topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
 
-   if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
+   if (dpu_crtc->color_enabled) {
if (dpu_kms->catalog->dspp &&
(dpu_kms->catalog->dspp_count >= topology.num_lm))
topology.num_dspp = topology.num_lm;
@@ -635,6 +636,7 @@ static int dpu_encoder_virt_atomic_check(
struct drm_display_mode *adj_mode;
struct msm_display_topology topology;
struct dpu_global_state *gl

[Freedreno] [PATCH v3 0/3] add color management support for the crtc

[Kalyan Thota]

Add color management support for the crtc provided there are
enough dspps that can be allocated from the catalog

Kalyan Thota (3):
  drm/msm/disp/dpu1: pin 1 crtc to 1 encoder
  drm/msm/disp/dpu1: add helper to know if display is builtin
  drm/msm/disp/dpu1: add color management support for the crtc

 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c|  5 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h|  6 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 34 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h |  6 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 24 +---
 5 files changed, 61 insertions(+), 14 deletions(-)

-- 
2.7.4

[Freedreno] [PATCH v3 2/3] drm/msm/disp/dpu1: add helper to know if display is builtin

[Kalyan Thota]

Since DRM encoder type for few encoders can be similar
(like eDP and DP) find out if the interface supports HPD
from encoder bridge to differentiate between builtin
and pluggable displays.

Changes in v1:
- add connector type in the disp_info (Dmitry)
- add helper functions to know encoder type
- update commit text reflecting the change

Changes in v2:
- avoid hardcode of connector type for DSI as it may not be true (Dmitry)
- get the HPD information from encoder bridge

Changes in v3:
- use bridge type instead of bridge ops in determining connector (Dmitry)

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 27 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h |  6 ++
 2 files changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 9c6817b..574f2b0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "msm_drv.h"
 #include "dpu_kms.h"
@@ -217,6 +218,32 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
 };
 
+bool dpu_encoder_is_builtin(struct drm_encoder *encoder)
+{
+   struct drm_bridge *bridge;
+   int ops = 0;
+
+   if (!encoder)
+   return false;
+
+   /* Get last bridge in the chain to determine connector type */
+   drm_for_each_bridge_in_chain(encoder, bridge)
+   if (!drm_bridge_get_next_bridge(bridge))
+   ops = bridge->type;
+
+   switch (ops) {
+   case DRM_MODE_CONNECTOR_Unknown:
+   case DRM_MODE_CONNECTOR_LVDS:
+   case DRM_MODE_CONNECTOR_eDP:
+   case DRM_MODE_CONNECTOR_DSI:
+   case DRM_MODE_CONNECTOR_DPI:
+   case DRM_MODE_CONNECTOR_WRITEBACK:
+   case DRM_MODE_CONNECTOR_VIRTUAL:
+   return true;
+   default:
+   return false;
+   }
+}
 
 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc)
 {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 9e7236e..7f3d823 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -224,4 +224,10 @@ void dpu_encoder_cleanup_wb_job(struct drm_encoder 
*drm_enc,
  */
 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc);
 
+/**
+ * dpu_encoder_is_builtin - find if the encoder is of type builtin
+ * @drm_enc:Pointer to previously created drm encoder structure
+ */
+bool dpu_encoder_is_builtin(struct drm_encoder *drm_enc);
+
 #endif /* __DPU_ENCODER_H__ */
-- 
2.7.4

Re: [Freedreno] [PATCH v3 2/3] drm/msm/disp/dpu1: add helper to know if display is builtin

[Kalyan Thota]

>-Original Message-
>From: Dmitry Baryshkov 
>Sent: Friday, November 18, 2022 6:09 PM
>To: Kalyan Thota (QUIC) ; dri-
>de...@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
>freedreno@lists.freedesktop.org; devicet...@vger.kernel.org
>Cc: linux-ker...@vger.kernel.org; robdcl...@chromium.org;
>diand...@chromium.org; swb...@chromium.org; Vinod Polimera (QUIC)
>; Abhinav Kumar (QUIC)
>
>Subject: Re: [PATCH v3 2/3] drm/msm/disp/dpu1: add helper to know if display is
>builtin
>
>WARNING: This email originated from outside of Qualcomm. Please be wary of
>any links or attachments, and do not enable macros.
>
>On 18/11/2022 15:16, Kalyan Thota wrote:
>> Since DRM encoder type for few encoders can be similar (like eDP and
>> DP) find out if the interface supports HPD from encoder bridge to
>> differentiate between builtin and pluggable displays.
>>
>> Changes in v1:
>> - add connector type in the disp_info (Dmitry)
>> - add helper functions to know encoder type
>> - update commit text reflecting the change
>>
>> Changes in v2:
>> - avoid hardcode of connector type for DSI as it may not be true
>> (Dmitry)
>> - get the HPD information from encoder bridge
>>
>> Changes in v3:
>> - use bridge type instead of bridge ops in determining connector
>> (Dmitry)
>>
>> Signed-off-by: Kalyan Thota 
>> ---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 27
>+++
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h |  6 ++
>>   2 files changed, 33 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> index 9c6817b..574f2b0 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> @@ -15,6 +15,7 @@
>>   #include 
>>   #include 
>>   #include 
>> +#include 
>>
>>   #include "msm_drv.h"
>>   #include "dpu_kms.h"
>> @@ -217,6 +218,32 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
>>   15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
>>   };
>>
>> +bool dpu_encoder_is_builtin(struct drm_encoder *encoder) {
>> + struct drm_bridge *bridge;
>> + int ops = 0;
>> +
>> + if (!encoder)
>> + return false;
>> +
>> + /* Get last bridge in the chain to determine connector type */
>> + drm_for_each_bridge_in_chain(encoder, bridge)
>> + if (!drm_bridge_get_next_bridge(bridge))
>> + ops = bridge->type;
>
>Why don't we check the connector type directly? You should not assume that
>connector's type is equal to the latest bridge's type.

if we need to get the type from connector, need to do something as below.
Are you thinking on the same lines ?

"to_drm_bridge_connector" macro needs to be moved to drm_bridge_connector.h

struct drm_bridge_connector *bridge_connector;

drm_connector_list_iter_begin(dev, &conn_iter);
drm_for_each_connector_iter(connector, &conn_iter) {

bridge_connector = to_drm_bridge_connector(connector);
if (bridge_connector->encoder == encoder) {
type = connector->connector_type;
break;
}
}
drm_connector_list_iter_end(&conn_iter);


>> +
>> + switch (ops) {
>> + case DRM_MODE_CONNECTOR_Unknown:
>> + case DRM_MODE_CONNECTOR_LVDS:
>> + case DRM_MODE_CONNECTOR_eDP:
>> + case DRM_MODE_CONNECTOR_DSI:
>> + case DRM_MODE_CONNECTOR_DPI:
>> + case DRM_MODE_CONNECTOR_WRITEBACK:
>> + case DRM_MODE_CONNECTOR_VIRTUAL:
>
>Unknown, WRITEBACK and VIRTUAL are not builtin (for the point of CTM at
>least).
>
>> + return true;
>> + default:
>> + return false;
>> + }
>> +}
>>
>>   bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc)
>>   {
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>> index 9e7236e..7f3d823 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>> @@ -224,4 +224,10 @@ void dpu_encoder_cleanup_wb_job(struct
>drm_encoder *drm_enc,
>>*/
>>   bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc);
>>
>> +/**
>> + * dpu_encoder_is_builtin - find if the encoder is of type builtin
>> + * @drm_enc:Pointer to previously created drm encoder structure
>> + */
>> +bool dpu_encoder_is_builtin(struct drm_encoder *drm_enc);
>> +
>>   #endif /* __DPU_ENCODER_H__ */
>
>--
>With best wishes
>Dmitry

[Freedreno] [PATCH v4 0/3] add color management support for the crtc

[Kalyan Thota]

Add color management support for the crtc provided there are
enough dspps that can be allocated from the catalog

Kalyan Thota (3):
  drm/msm/disp/dpu1: pin 1 crtc to 1 encoder
  drm/msm/disp/dpu1: add helper to know if display is builtin
  drm/msm/disp/dpu1: add color management support for the crtc

 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c|  5 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h|  5 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 33 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h |  6 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 24 ++---
 5 files changed, 60 insertions(+), 13 deletions(-)

-- 
2.7.4

[Freedreno] [PATCH v4 2/3] drm/msm/disp/dpu1: add helper to know if display is builtin

[Kalyan Thota]

Since DRM encoder type for few encoders can be similar
(like eDP and DP), get the connector type for a given
encoder to differentiate between builtin and pluggable
displays.

Changes in v1:
- add connector type in the disp_info (Dmitry)
- add helper functions to know encoder type
- update commit text reflecting the change

Changes in v2:
- avoid hardcode of connector type for DSI as it may not be true (Dmitry)
- get the HPD information from encoder bridge

Changes in v3:
- use connector type instead of bridge ops in determining
connector (Dmitry)

Changes in v4:
- get type from the drm connector rather from bridge connector (Dmitry)

Signed-off-by: Kalyan Thota 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 26 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h |  6 ++
 2 files changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 9c6817b..96db7fb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -217,6 +217,32 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
 };
 
+bool dpu_encoder_is_builtin(struct drm_encoder *encoder)
+{
+   struct drm_connector *connector;
+   struct drm_connector_list_iter conn_iter;
+   struct drm_device *dev = encoder->dev;
+   int type = 0;
+
+   drm_connector_list_iter_begin(dev, &conn_iter);
+   drm_for_each_connector_iter(connector, &conn_iter) {
+   if (drm_connector_has_possible_encoder(connector, encoder)) {
+   type = connector->connector_type;
+   break;
+   }
+   }
+   drm_connector_list_iter_end(&conn_iter);
+
+   switch (type) {
+   case DRM_MODE_CONNECTOR_LVDS:
+   case DRM_MODE_CONNECTOR_eDP:
+   case DRM_MODE_CONNECTOR_DSI:
+   case DRM_MODE_CONNECTOR_DPI:
+   return true;
+   default:
+   return false;
+   }
+}
 
 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc)
 {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 9e7236e..7f3d823 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -224,4 +224,10 @@ void dpu_encoder_cleanup_wb_job(struct drm_encoder 
*drm_enc,
  */
 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc);
 
+/**
+ * dpu_encoder_is_builtin - find if the encoder is of type builtin
+ * @drm_enc:Pointer to previously created drm encoder structure
+ */
+bool dpu_encoder_is_builtin(struct drm_encoder *drm_enc);
+
 #endif /* __DPU_ENCODER_H__ */
-- 
2.7.4