Re: [Freedreno] [PATCHv5 4/6] drm/msm/a6xx: Add support for using system cache(LLC)
Hi Jordan,
On 2020-09-23 20:33, Jordan Crouse wrote:
On Tue, Sep 22, 2020 at 11:48:17AM +0530, Sai Prakash Ranjan wrote:
From: Sharat Masetty
The last level system cache can be partitioned to 32 different
slices of which GPU has two slices preallocated. One slice is
used for caching GPU buffers and the other slice is used for
caching the GPU SMMU pagetables. This talks to the core system
cache driver to acquire the slice handles, configure the SCID's
to those slices and activates and deactivates the slices upon
GPU power collapse and restore.
Some support from the IOMMU driver is also needed to make use
of the system cache to set the right TCR attributes. GPU then
has the ability to override a few cacheability parameters which
it does to override write-allocate to write-no-allocate as the
GPU hardware does not benefit much from it.
DOMAIN_ATTR_SYS_CACHE is another domain level attribute used by the
IOMMU driver to set the right attributes to cache the hardware
pagetables into the system cache.
Signed-off-by: Sharat Masetty
[saiprakash.ranjan: fix to set attr before device attach to iommu and
rebase]
Signed-off-by: Sai Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83
+
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 17 +
3 files changed, 104 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 8915882e..151190ff62f7 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -8,7 +8,9 @@
#include "a6xx_gpu.h"
#include "a6xx_gmu.xml.h"
+#include
#include
+#include
#define GPU_PAS_ID 13
@@ -1022,6 +1024,79 @@ static irqreturn_t a6xx_irq(struct msm_gpu
*gpu)
return IRQ_HANDLED;
}
+static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32
mask, u32 or)
+{
+ return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);
+}
+
+static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32
value)
+{
+ return msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
+}
+
+static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu)
+{
+ llcc_slice_deactivate(a6xx_gpu->llc_slice);
+ llcc_slice_deactivate(a6xx_gpu->htw_llc_slice);
+}
+
+static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
+{
+ u32 cntl1_regval = 0;
+
+ if (IS_ERR(a6xx_gpu->llc_mmio))
+ return;
+
+ if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
+ u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);
+
+ gpu_scid &= 0x1f;
+ cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10)
|
+ (gpu_scid << 15) | (gpu_scid << 20);
+ }
+
+ if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) {
+ u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice);
+
+ gpuhtw_scid &= 0x1f;
+ cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid);
+ }
+
+ if (cntl1_regval) {
+ /*
+* Program the slice IDs for the various GPU blocks and GPU MMU
+* pagetables
+*/
+ a6xx_llc_write(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1,
cntl1_regval);
+
+ /*
+* Program cacheability overrides to not allocate cache lines on
+* a write miss
+*/
+ a6xx_llc_rmw(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF,
0x03);
+ }
+}
This code has been around long enough that it pre-dates a650. On a650
and other
MMU-500 targets the htw_llc is configured by the firmware and the
llc_slice is
configured in a different register.
I don't think we need to pause everything and add support for the
MMU-500 path,
but we do need a way to disallow LLCC on affected targets until such
time that
we can get it fixed up.
Thanks for taking a close look, does something like below look ok or
something
else is needed here?
+ /* Till the time we get in LLCC support for A650 */
+ if (!(info && info->revn == 650))
+ a6xx_llc_slices_init(pdev, a6xx_gpu);
Thanks,
Sai
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Re: [Freedreno] [PATCHv5 5/6] iommu: arm-smmu-impl: Use table to list QCOM implementations
On 2020-09-23 20:54, Robin Murphy wrote:
On 2020-09-22 07:18, Sai Prakash Ranjan wrote:
Use table and of_match_node() to match qcom implementation
instead of multiple of_device_compatible() calls for each
QCOM SMMU implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
index d199b4bff15d..ce78295cfa78 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
@@ -9,6 +9,13 @@
#include "arm-smmu.h"
+static const struct of_device_id __maybe_unused
qcom_smmu_impl_of_match[] = {
+ { .compatible = "qcom,sc7180-smmu-500" },
+ { .compatible = "qcom,sdm845-smmu-500" },
+ { .compatible = "qcom,sm8150-smmu-500" },
+ { .compatible = "qcom,sm8250-smmu-500" },
+ { }
+};
Can you push the table itself into arm-smmu-qcom? That way you'll be
free to add new SoCs willy-nilly without any possibility of
conflicting with anything else.
Bonus points if you can fold in the Adreno variant and keep everything
together ;)
Sure I can get bonus points :)
Thanks,
Sai
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Re: [Freedreno] [PATCHv5 4/6] drm/msm/a6xx: Add support for using system cache(LLC)
On Mon, Sep 28, 2020 at 05:56:55PM +0530, Sai Prakash Ranjan wrote:
> Hi Jordan,
>
> On 2020-09-23 20:33, Jordan Crouse wrote:
> >On Tue, Sep 22, 2020 at 11:48:17AM +0530, Sai Prakash Ranjan wrote:
> >>From: Sharat Masetty
> >>
> >>The last level system cache can be partitioned to 32 different
> >>slices of which GPU has two slices preallocated. One slice is
> >>used for caching GPU buffers and the other slice is used for
> >>caching the GPU SMMU pagetables. This talks to the core system
> >>cache driver to acquire the slice handles, configure the SCID's
> >>to those slices and activates and deactivates the slices upon
> >>GPU power collapse and restore.
> >>
> >>Some support from the IOMMU driver is also needed to make use
> >>of the system cache to set the right TCR attributes. GPU then
> >>has the ability to override a few cacheability parameters which
> >>it does to override write-allocate to write-no-allocate as the
> >>GPU hardware does not benefit much from it.
> >>
> >>DOMAIN_ATTR_SYS_CACHE is another domain level attribute used by the
> >>IOMMU driver to set the right attributes to cache the hardware
> >>pagetables into the system cache.
> >>
> >>Signed-off-by: Sharat Masetty
> >>[saiprakash.ranjan: fix to set attr before device attach to iommu and
> >>rebase]
> >>Signed-off-by: Sai Prakash Ranjan
> >>---
> >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +
> >> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++
> >> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 17 +
> >> 3 files changed, 104 insertions(+)
> >>
> >>diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >>b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >>index 8915882e..151190ff62f7 100644
> >>--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >>+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >>@@ -8,7 +8,9 @@
> >> #include "a6xx_gpu.h"
> >> #include "a6xx_gmu.xml.h"
> >>
> >>+#include
> >> #include
> >>+#include
> >>
> >> #define GPU_PAS_ID 13
> >>
> >>@@ -1022,6 +1024,79 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
> >>return IRQ_HANDLED;
> >> }
> >>
> >>+static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask,
> >>u32 or)
> >>+{
> >>+ return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);
> >>+}
> >>+
> >>+static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32
> >>value)
> >>+{
> >>+ return msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
> >>+}
> >>+
> >>+static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu)
> >>+{
> >>+ llcc_slice_deactivate(a6xx_gpu->llc_slice);
> >>+ llcc_slice_deactivate(a6xx_gpu->htw_llc_slice);
> >>+}
> >>+
> >>+static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
> >>+{
> >>+ u32 cntl1_regval = 0;
> >>+
> >>+ if (IS_ERR(a6xx_gpu->llc_mmio))
> >>+ return;
> >>+
> >>+ if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
> >>+ u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);
> >>+
> >>+ gpu_scid &= 0x1f;
> >>+ cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid <<
> >>10) |
> >>+ (gpu_scid << 15) | (gpu_scid << 20);
> >>+ }
> >>+
> >>+ if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) {
> >>+ u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice);
> >>+
> >>+ gpuhtw_scid &= 0x1f;
> >>+ cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid);
> >>+ }
> >>+
> >>+ if (cntl1_regval) {
> >>+ /*
> >>+* Program the slice IDs for the various GPU blocks and GPU MMU
> >>+* pagetables
> >>+*/
> >>+ a6xx_llc_write(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1,
> >>cntl1_regval);
> >>+
> >>+ /*
> >>+* Program cacheability overrides to not allocate cache lines on
> >>+* a write miss
> >>+*/
> >>+ a6xx_llc_rmw(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0,
> >>0xF,
> >>0x03);
> >>+ }
> >>+}
> >
> >This code has been around long enough that it pre-dates a650. On a650 and
> >other
> >MMU-500 targets the htw_llc is configured by the firmware and the
> >llc_slice is
> >configured in a different register.
> >
> >I don't think we need to pause everything and add support for the MMU-500
> >path,
> >but we do need a way to disallow LLCC on affected targets until such time
> >that
> >we can get it fixed up.
> >
>
> Thanks for taking a close look, does something like below look ok or
> something
> else is needed here?
>
> + /* Till the time we get in LLCC support for A650 */
> + if (!(info && info->revn == 650))
> + a6xx_llc_slices_init(pdev, a6xx_gpu);
It doesn't look like Rob picked this up for 5.10, so we have some time to do it
right. Would you like me to give you an add-on patch for mmu-500 targets?
Jordan
> Thanks,
> Sai
>
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> of Code Aurora Forum, hosted by The Linux Foundation
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Re: [Freedreno] [PATCH 5/7] drm/msm/a5xx: Fix VPC protect value in gpu_write()
On Sat, Sep 26, 2020 at 02:51:44PM +0200, khol...@gmail.com wrote: > From: Konrad Dybcio > > The upstream API for some reason uses logbase2 instead of > just passing the argument as-is, whereas downstream CAF > kernel does the latter. > > Hence, a mistake has been made when porting: > 4 is the value that's supposed to be passed, but > log2(4) = 2. Changing the value to 16 (= 2^4) fixes > the issue. FWIW I think downstream is wrong. Its a lot more intuitive to pass the number of registers that should be protected than to force a human to do math. Jordan > Signed-off-by: Konrad Dybcio > Signed-off-by: AngeloGioacchino Del Regno > --- > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > index 00df5de3c8e3..b2670af638a3 100644 > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > @@ -789,7 +789,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu) > > /* VPC */ > gpu_write(gpu, REG_A5XX_CP_PROTECT(14), ADRENO_PROTECT_RW(0xE68, 8)); > - gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 4)); > + gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 16)); > > /* UCHE */ > gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16)); > -- > 2.28.0 > -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH 1/7] drm/msm/a5xx: Remove overwriting A5XX_PC_DBG_ECO_CNTL register
On Sat, Sep 26, 2020 at 02:51:40PM +0200, khol...@gmail.com wrote: > From: AngeloGioacchino Del Regno > > The PC_DBG_ECO_CNTL register on the Adreno A5xx family gets > programmed to some different values on a per-model basis. > At least, this is what we intend to do here; > > Unfortunately, though, this register is being overwritten with a > static magic number, right after applying the GPU-specific > configuration (including the GPU-specific quirks) and that is > effectively nullifying the efforts. > > Let's remove the redundant and wrong write to the PC_DBG_ECO_CNTL > register in order to retain the wanted configuration for the > target GPU. This was probably inherited from downstream which doesn't mind RMWing the same register multiple times. Reviewed-by: Jordan Crouse > Signed-off-by: AngeloGioacchino Del Regno > --- > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > index 91726da82ed6..6262603e6e2e 100644 > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > @@ -594,8 +594,6 @@ static int a5xx_hw_init(struct msm_gpu *gpu) > if (adreno_gpu->info->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI) > gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8)); > > - gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0xc0200100); > - > /* Enable USE_RETENTION_FLOPS */ > gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x0200); > > -- > 2.28.0 > -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
Re: [Freedreno] [PATCH 2/7] drm/msm/a5xx: Separate A5XX_PC_DBG_ECO_CNTL write from main branch
On Sat, Sep 26, 2020 at 02:51:41PM +0200, khol...@gmail.com wrote:
> From: AngeloGioacchino Del Regno
>
> The "main" if branch where we program the other regsiters for the
Nit - regsiters -> registers
> Adreno 5xx family of GPUs should not contain the PC_DBG_ECO_CNTL
> register programming because this has logical similarity
> differences from all the others.
>
> A later commit will show the entire sense of this.
With that
Reviewed-by: Jordan Crouse
> Signed-off-by: AngeloGioacchino Del Regno
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> index 6262603e6e2e..f98f0844838c 100644
> --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> @@ -577,8 +577,6 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
> gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20);
> gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x4030);
> gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x20100D0A);
> - gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
> - (0x200 << 11 | 0x200 << 22));
> } else {
> gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40);
> if (adreno_is_a530(adreno_gpu))
> @@ -587,9 +585,14 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
> gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400);
> gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x8060);
> gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16);
> + }
> +
> + if (adreno_is_a510(adreno_gpu))
> + gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
> + (0x200 << 11 | 0x200 << 22));
> + else
> gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
> (0x400 << 11 | 0x300 << 22));
> - }
>
> if (adreno_gpu->info->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI)
> gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8));
> --
> 2.28.0
>
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Re: [Freedreno] [PATCH 3/7] drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs
On Sat, Sep 26, 2020 at 02:51:42PM +0200, khol...@gmail.com wrote:
> From: AngeloGioacchino Del Regno
>
> The Adreno 508/509/512 GPUs are stripped versions of the Adreno
> 5xx found in the mid-end SoCs such as SDM630, SDM636, SDM660 and
> SDA variants; these SoCs are usually provided with ZAP firmwares,
> but they have no available GPMU.
Reviewed-by: Jordan Crouse
> Signed-off-by: AngeloGioacchino Del Regno
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 172 ++---
> drivers/gpu/drm/msm/adreno/a5xx_power.c| 4 +-
> drivers/gpu/drm/msm/adreno/adreno_device.c | 60 +++
> drivers/gpu/drm/msm/adreno/adreno_gpu.h| 15 ++
> 4 files changed, 231 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> index f98f0844838c..9bcbf6cd5a28 100644
> --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> @@ -212,7 +212,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct
> msm_gem_submit *submit,
> a5xx_preempt_trigger(gpu);
> }
>
> -static const struct {
> +static const struct adreno_five_hwcg_regs {
> u32 offset;
> u32 value;
> } a5xx_hwcg[] = {
> @@ -308,16 +308,124 @@ static const struct {
> {REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x4000},
> {REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x0200},
> {REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x}
> +}, a50x_hwcg[] = {
> + {REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x0222},
> + {REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x0220},
> + {REG_A5XX_RBBM_CLOCK_HYST_SP0, 0xF3CF},
> + {REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x0080},
> + {REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x0022},
> + {REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST_UCHE, 0x00F4},
> + {REG_A5XX_RBBM_CLOCK_DELAY_UCHE, 0x0002},
> + {REG_A5XX_RBBM_CLOCK_CNTL_RB0, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL2_RB0, 0x0022},
> + {REG_A5XX_RBBM_CLOCK_CNTL_CCU0, 0x0000},
> + {REG_A5XX_RBBM_CLOCK_CNTL_RAC, 0x0552},
> + {REG_A5XX_RBBM_CLOCK_CNTL2_RAC, 0x0050},
> + {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},
> + {REG_A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},
> + {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x0002},
> + {REG_A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},
> + {REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x0422},
> + {REG_A5XX_RBBM_CLOCK_MODE_GPC, 0x0222},
> + {REG_A5XX_RBBM_CLOCK_MODE_VFD, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
> + {REG_A5XX_RBBM_CLOCK_HYST_VFD, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x4000},
> + {REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x0200},
> + {REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x},
> +}, a512_hwcg[] = {
> + {REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x0222},
> + {REG_A5XX_RBBM_CLOCK_CNTL_SP1, 0x0222},
> + {REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x0220},
> + {REG_A5XX_RBBM_CLOCK_CNTL2_SP1, 0x0220},
> + {REG_A5XX_RBBM_CLOCK_HYST_SP0, 0xF3CF},
> + {REG_A5XX_RBBM_CLOCK_HYST_SP1, 0xF3CF},
> + {REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x0080},
> + {REG_A5XX_RBBM_CLOCK_DELAY_SP1, 0x0080},
> + {REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL_TP1, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL2_TP1, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL3_TP1, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST_TP1, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST2_TP1, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST3_TP1, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY_TP1, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY2_TP1, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY3_TP1, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL2_U
Re: [Freedreno] [PATCH 4/7] drm/msm/a5xx: Reset VBIF before PC only on A510 and A530
On Sat, Sep 26, 2020 at 02:51:43PM +0200, khol...@gmail.com wrote:
> From: AngeloGioacchino Del Regno
>
> Resetting the VBIF before power collapse is done to avoid getting
> bogus FIFO entries during the suspend sequence or subsequent resume,
> but this is doable only on Adreno 510 and Adreno 530, as the other
> units will tendentially lock up.
> Especially on Adreno 508, the GPU will show lockups and very bad
> slownesses after processing the first frame.
>
> Avoiding to execute the RBBM SW Reset before suspend will stop the
> lockup issue from happening on at least Adreno 508/509/512.
Reviewed-by: Jordan Crouse
> Signed-off-by: AngeloGioacchino Del Regno
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> index 9bcbf6cd5a28..00df5de3c8e3 100644
> --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> @@ -1306,10 +1306,12 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
>
> /*
>* Reset the VBIF before power collapse to avoid issue with FIFO
> - * entries
> + * entries on Adreno A510 and A530 (the others will tend to lock up)
>*/
> - gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C);
> - gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x);
> + if (adreno_is_a510(adreno_gpu) || adreno_is_a530(adreno_gpu)) {
> + gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C);
> + gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x);
> + }
>
> return msm_gpu_pm_suspend(gpu);
> }
> --
> 2.28.0
>
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Re: [Freedreno] [PATCHv5 4/6] drm/msm/a6xx: Add support for using system cache(LLC)
On 2020-09-28 21:41, Jordan Crouse wrote:
On Mon, Sep 28, 2020 at 05:56:55PM +0530, Sai Prakash Ranjan wrote:
Hi Jordan,
On 2020-09-23 20:33, Jordan Crouse wrote:
>On Tue, Sep 22, 2020 at 11:48:17AM +0530, Sai Prakash Ranjan wrote:
>>From: Sharat Masetty
>>
>>The last level system cache can be partitioned to 32 different
>>slices of which GPU has two slices preallocated. One slice is
>>used for caching GPU buffers and the other slice is used for
>>caching the GPU SMMU pagetables. This talks to the core system
>>cache driver to acquire the slice handles, configure the SCID's
>>to those slices and activates and deactivates the slices upon
>>GPU power collapse and restore.
>>
>>Some support from the IOMMU driver is also needed to make use
>>of the system cache to set the right TCR attributes. GPU then
>>has the ability to override a few cacheability parameters which
>>it does to override write-allocate to write-no-allocate as the
>>GPU hardware does not benefit much from it.
>>
>>DOMAIN_ATTR_SYS_CACHE is another domain level attribute used by the
>>IOMMU driver to set the right attributes to cache the hardware
>>pagetables into the system cache.
>>
>>Signed-off-by: Sharat Masetty
>>[saiprakash.ranjan: fix to set attr before device attach to iommu and
>>rebase]
>>Signed-off-by: Sai Prakash Ranjan
>>---
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++
>> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 17 +
>> 3 files changed, 104 insertions(+)
>>
>>diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>index 8915882e..151190ff62f7 100644
>>--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>@@ -8,7 +8,9 @@
>> #include "a6xx_gpu.h"
>> #include "a6xx_gmu.xml.h"
>>
>>+#include
>> #include
>>+#include
>>
>> #define GPU_PAS_ID 13
>>
>>@@ -1022,6 +1024,79 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
>>return IRQ_HANDLED;
>> }
>>
>>+static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask,
>>u32 or)
>>+{
>>+ return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);
>>+}
>>+
>>+static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32
>>value)
>>+{
>>+ return msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
>>+}
>>+
>>+static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu)
>>+{
>>+ llcc_slice_deactivate(a6xx_gpu->llc_slice);
>>+ llcc_slice_deactivate(a6xx_gpu->htw_llc_slice);
>>+}
>>+
>>+static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
>>+{
>>+ u32 cntl1_regval = 0;
>>+
>>+ if (IS_ERR(a6xx_gpu->llc_mmio))
>>+ return;
>>+
>>+ if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
>>+ u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);
>>+
>>+ gpu_scid &= 0x1f;
>>+ cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid
<< 10) |
>>+ (gpu_scid << 15) | (gpu_scid << 20);
>>+ }
>>+
>>+ if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) {
>>+ u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice);
>>+
>>+ gpuhtw_scid &= 0x1f;
>>+ cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid);
>>+ }
>>+
>>+ if (cntl1_regval) {
>>+ /*
>>+* Program the slice IDs for the various GPU blocks and GPU
MMU
>>+* pagetables
>>+*/
>>+ a6xx_llc_write(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1,
>>cntl1_regval);
>>+
>>+ /*
>>+* Program cacheability overrides to not allocate cache lines
on
>>+* a write miss
>>+*/
>>+ a6xx_llc_rmw(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0,
0xF,
>>0x03);
>>+ }
>>+}
>
>This code has been around long enough that it pre-dates a650. On a650 and
>other
>MMU-500 targets the htw_llc is configured by the firmware and the
>llc_slice is
>configured in a different register.
>
>I don't think we need to pause everything and add support for the MMU-500
>path,
>but we do need a way to disallow LLCC on affected targets until such time
>that
>we can get it fixed up.
>
Thanks for taking a close look, does something like below look ok or
something
else is needed here?
+ /* Till the time we get in LLCC support for A650 */
+ if (!(info && info->revn == 650))
+ a6xx_llc_slices_init(pdev, a6xx_gpu);
It doesn't look like Rob picked this up for 5.10, so we have some time
to do it
right. Would you like me to give you an add-on patch for mmu-500
targets?
Yes that will be great.
Thanks,
Sai
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[Freedreno] [PATCH] drm/msm/dpu: Add newline to printks
Printk messages need newlines. Add it here.
Cc: Abhinav Kumar
Cc: Jeykumar Sankaran
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Stephen Boyd
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index f272a8d0f95b..cbe0461246f8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -906,7 +906,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
}
mode = &state->adjusted_mode;
- DPU_DEBUG("%s: check", dpu_crtc->name);
+ DPU_DEBUG("%s: check\n", dpu_crtc->name);
/* force a full mode set if active state changed */
if (state->active_changed)
@@ -1012,7 +1012,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
}
pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0;
- DPU_DEBUG("%s: zpos %d", dpu_crtc->name, z_pos);
+ DPU_DEBUG("%s: zpos %d\n", dpu_crtc->name, z_pos);
}
for (i = 0; i < multirect_count; i++) {
--
Sent by a computer, using git, on the internet
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Re: [Freedreno] [PATCH] drm/msm/dpu: Add newline to printks
On 2020-09-28 12:16, Stephen Boyd wrote:
Printk messages need newlines. Add it here.
Cc: Abhinav Kumar
Cc: Jeykumar Sankaran
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Stephen Boyd
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index f272a8d0f95b..cbe0461246f8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -906,7 +906,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc
*crtc,
}
mode = &state->adjusted_mode;
- DPU_DEBUG("%s: check", dpu_crtc->name);
+ DPU_DEBUG("%s: check\n", dpu_crtc->name);
/* force a full mode set if active state changed */
if (state->active_changed)
@@ -1012,7 +1012,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc
*crtc,
}
pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0;
- DPU_DEBUG("%s: zpos %d", dpu_crtc->name, z_pos);
+ DPU_DEBUG("%s: zpos %d\n", dpu_crtc->name, z_pos);
}
for (i = 0; i < multirect_count; i++) {
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Re: [Freedreno] [PATCH 5/7] drm/msm/a5xx: Fix VPC protect value in gpu_write()
Il giorno lun 28 set 2020 alle ore 18:16 Jordan Crouse ha scritto: > > On Sat, Sep 26, 2020 at 02:51:44PM +0200, khol...@gmail.com wrote: > > From: Konrad Dybcio > > > > The upstream API for some reason uses logbase2 instead of > > just passing the argument as-is, whereas downstream CAF > > kernel does the latter. > > > > Hence, a mistake has been made when porting: > > 4 is the value that's supposed to be passed, but > > log2(4) = 2. Changing the value to 16 (= 2^4) fixes > > the issue. > > FWIW I think downstream is wrong. Its a lot more intuitive to pass the number > of > registers that should be protected than to force a human to do math. > > Jordan > Uhm, actually, it's upstream the one forcing to do math... :P In any case, downstream you have some calls with an explicit log2 and some others with the "real" number of registers. Hardware magic register layouts, maybe :))) -- Angelo > > Signed-off-by: Konrad Dybcio > > Signed-off-by: AngeloGioacchino Del Regno > > --- > > drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > > b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > > index 00df5de3c8e3..b2670af638a3 100644 > > --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > > +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > > @@ -789,7 +789,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu) > > > > /* VPC */ > > gpu_write(gpu, REG_A5XX_CP_PROTECT(14), ADRENO_PROTECT_RW(0xE68, 8)); > > - gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 4)); > > + gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 16)); > > > > /* UCHE */ > > gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16)); > > -- > > 2.28.0 > > > > -- > The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v2 0/7] Add support for Adreno 508/509/512
From: AngeloGioacchino Del Regno In this patch series, we are adding support for lower end Adreno 5 series GPUs, such as A508, A509 and A512 that we have found in the Qualcomm SDM630, SDM636 and SDM660 SoCs. On a note, adding support for these three units, also adds 99% of the required "things" for another two GPUs, A505 and A506 but, even if adding them requires literally two lines of code, noone of us has got any SoC equipped with these ones hence we wouldn't be able to test. Even though there is basically no reason for them to not work correctly, kernel side, I chose to avoid adding the two "magic" lines. Anyway, this patchset also addresses some issues that we've found in the A5XX part of the Adreno driver, regarding a logic mistake in one of the VPC protect values and a forced overwrite of the register named A5XX_PC_DBG_ECO_CNTL, forcing the setting of vtxFifo and primFifo thresholds that was valid only for higher end GPUs. This patch series has been tested on the following devices: - Sony Xperia XA2 Ultra (SDM630 Nile Discovery) - Sony Xperia 10(SDM630 Ganges Kirin) - Sony Xperia 10 Plus (SDM636 Ganges Mermaid) Changes in v2: - Define REG_A5XX_UCHE_MODE_CNTL and fix open-coded REG_A5XX_VPC_DBG_ECO_CNTL in the all flat shading optimization disablement commit, as requested by Rob Clark. AngeloGioacchino Del Regno (4): drm/msm/a5xx: Remove overwriting A5XX_PC_DBG_ECO_CNTL register drm/msm/a5xx: Separate A5XX_PC_DBG_ECO_CNTL write from main branch drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs drm/msm/a5xx: Reset VBIF before PC only on A510 and A530 Konrad Dybcio (3): drm/msm/a5xx: Fix VPC protect value in gpu_write() drm/msm/a5xx: Disable flat shading optimization drm/msm/a5xx: Disable UCHE global filter drivers/gpu/drm/msm/adreno/a5xx.xml.h | 2 + drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 195 ++--- drivers/gpu/drm/msm/adreno/a5xx_power.c| 4 +- drivers/gpu/drm/msm/adreno/adreno_device.c | 60 +++ drivers/gpu/drm/msm/adreno/adreno_gpu.h| 15 ++ 5 files changed, 249 insertions(+), 27 deletions(-) -- 2.28.0 ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v2 1/7] drm/msm/a5xx: Remove overwriting A5XX_PC_DBG_ECO_CNTL register
From: AngeloGioacchino Del Regno The PC_DBG_ECO_CNTL register on the Adreno A5xx family gets programmed to some different values on a per-model basis. At least, this is what we intend to do here; Unfortunately, though, this register is being overwritten with a static magic number, right after applying the GPU-specific configuration (including the GPU-specific quirks) and that is effectively nullifying the efforts. Let's remove the redundant and wrong write to the PC_DBG_ECO_CNTL register in order to retain the wanted configuration for the target GPU. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 91726da82ed6..6262603e6e2e 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -594,8 +594,6 @@ static int a5xx_hw_init(struct msm_gpu *gpu) if (adreno_gpu->info->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI) gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8)); - gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0xc0200100); - /* Enable USE_RETENTION_FLOPS */ gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x0200); -- 2.28.0 ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v2 6/7] drm/msm/a5xx: Disable flat shading optimization
From: Konrad Dybcio Port over the command from downstream to prevent undefined behaviour. Signed-off-by: Konrad Dybcio Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 448fded571d3..6dac060902a3 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -759,6 +759,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu) adreno_is_a540(adreno_gpu)) gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, bit); + /* Disable All flat shading optimization (ALLFLATOPTDIS) */ + gpu_rmw(gpu, REG_A5XX_VPC_DBG_ECO_CNTL, 0, (1 << 10)); + /* Protect registers from the CP */ gpu_write(gpu, REG_A5XX_CP_PROTECT_CNTL, 0x0007); -- 2.28.0 ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v2 2/7] drm/msm/a5xx: Separate A5XX_PC_DBG_ECO_CNTL write from main branch
From: AngeloGioacchino Del Regno
The "main" if branch where we program the other registers for the
Adreno 5xx family of GPUs should not contain the PC_DBG_ECO_CNTL
register programming because this has logical similarity
differences from all the others.
A later commit will show the entire sense of this.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 6262603e6e2e..f98f0844838c 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -577,8 +577,6 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20);
gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x4030);
gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x20100D0A);
- gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
- (0x200 << 11 | 0x200 << 22));
} else {
gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40);
if (adreno_is_a530(adreno_gpu))
@@ -587,9 +585,14 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400);
gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x8060);
gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16);
+ }
+
+ if (adreno_is_a510(adreno_gpu))
+ gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
+ (0x200 << 11 | 0x200 << 22));
+ else
gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
(0x400 << 11 | 0x300 << 22));
- }
if (adreno_gpu->info->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI)
gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8));
--
2.28.0
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[Freedreno] [PATCH v2 4/7] drm/msm/a5xx: Reset VBIF before PC only on A510 and A530
From: AngeloGioacchino Del Regno
Resetting the VBIF before power collapse is done to avoid getting
bogus FIFO entries during the suspend sequence or subsequent resume,
but this is doable only on Adreno 510 and Adreno 530, as the other
units will tendentially lock up.
Especially on Adreno 508, the GPU will show lockups and very bad
slownesses after processing the first frame.
Avoiding to execute the RBBM SW Reset before suspend will stop the
lockup issue from happening on at least Adreno 508/509/512.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index fd33a34961cc..6163c3b61a69 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -1306,10 +1306,12 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
/*
* Reset the VBIF before power collapse to avoid issue with FIFO
-* entries
+* entries on Adreno A510 and A530 (the others will tend to lock up)
*/
- gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C);
- gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x);
+ if (adreno_is_a510(adreno_gpu) || adreno_is_a530(adreno_gpu)) {
+ gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C);
+ gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x);
+ }
return msm_gpu_pm_suspend(gpu);
}
--
2.28.0
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[Freedreno] [PATCH v2 7/7] drm/msm/a5xx: Disable UCHE global filter
From: Konrad Dybcio Port over the command from downstream to prevent undefined behaviour. Signed-off-by: Konrad Dybcio Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/msm/adreno/a5xx.xml.h | 2 ++ drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx.xml.h b/drivers/gpu/drm/msm/adreno/a5xx.xml.h index 346cc6ff3a36..7b9fcfe95c04 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a5xx.xml.h @@ -2367,6 +2367,8 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) #define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x0e80 +#define REG_A5XX_UCHE_MODE_CNTL 0x0e81 + #define REG_A5XX_UCHE_SVM_CNTL 0x0e82 #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x0e87 diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 6dac060902a3..979397372505 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -722,6 +722,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu) adreno_is_a512(adreno_gpu)) gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9)); + /* Disable UCHE global filter as SP can invalidate/flush independently */ + gpu_write(gpu, REG_A5XX_UCHE_MODE_CNTL, BIT(29)); + /* Enable USE_RETENTION_FLOPS */ gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x0200); -- 2.28.0 ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v2 5/7] drm/msm/a5xx: Fix VPC protect value in gpu_write()
From: Konrad Dybcio The upstream API for some reason uses logbase2 instead of just passing the argument as-is, whereas downstream CAF kernel does the latter. Hence, a mistake has been made when porting: 4 is the value that's supposed to be passed, but log2(4) = 2. Changing the value to 16 (= 2^4) fixes the issue. Signed-off-by: Konrad Dybcio Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 6163c3b61a69..448fded571d3 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -789,7 +789,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu) /* VPC */ gpu_write(gpu, REG_A5XX_CP_PROTECT(14), ADRENO_PROTECT_RW(0xE68, 8)); - gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 4)); + gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 16)); /* UCHE */ gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16)); -- 2.28.0 ___ Freedreno mailing list Freedreno@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/freedreno
[Freedreno] [PATCH v2 3/7] drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs
From: AngeloGioacchino Del Regno
The Adreno 508/509/512 GPUs are stripped versions of the Adreno
5xx found in the mid-end SoCs such as SDM630, SDM636, SDM660 and
SDA variants; these SoCs are usually provided with ZAP firmwares,
but they have no available GPMU.
Signed-off-by: AngeloGioacchino Del Regno
Tested-by: Martin Botka
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 172 ++---
drivers/gpu/drm/msm/adreno/a5xx_power.c| 4 +-
drivers/gpu/drm/msm/adreno/adreno_device.c | 60 +++
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 15 ++
4 files changed, 231 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index f98f0844838c..fd33a34961cc 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -212,7 +212,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct
msm_gem_submit *submit,
a5xx_preempt_trigger(gpu);
}
-static const struct {
+static const struct adreno_five_hwcg_regs {
u32 offset;
u32 value;
} a5xx_hwcg[] = {
@@ -308,16 +308,124 @@ static const struct {
{REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x4000},
{REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x0200},
{REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x}
+}, a50x_hwcg[] = {
+ {REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x0222},
+ {REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x0220},
+ {REG_A5XX_RBBM_CLOCK_HYST_SP0, 0xF3CF},
+ {REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x0080},
+ {REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x},
+ {REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x},
+ {REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x},
+ {REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x},
+ {REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x},
+ {REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x},
+ {REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x},
+ {REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x},
+ {REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x},
+ {REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x},
+ {REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x},
+ {REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x0022},
+ {REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x},
+ {REG_A5XX_RBBM_CLOCK_HYST_UCHE, 0x00F4},
+ {REG_A5XX_RBBM_CLOCK_DELAY_UCHE, 0x0002},
+ {REG_A5XX_RBBM_CLOCK_CNTL_RB0, 0x},
+ {REG_A5XX_RBBM_CLOCK_CNTL2_RB0, 0x0022},
+ {REG_A5XX_RBBM_CLOCK_CNTL_CCU0, 0x0000},
+ {REG_A5XX_RBBM_CLOCK_CNTL_RAC, 0x0552},
+ {REG_A5XX_RBBM_CLOCK_CNTL2_RAC, 0x0050},
+ {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},
+ {REG_A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},
+ {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x0002},
+ {REG_A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},
+ {REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x0422},
+ {REG_A5XX_RBBM_CLOCK_MODE_GPC, 0x0222},
+ {REG_A5XX_RBBM_CLOCK_MODE_VFD, 0x},
+ {REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x},
+ {REG_A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+ {REG_A5XX_RBBM_CLOCK_HYST_VFD, 0x},
+ {REG_A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x},
+ {REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x4000},
+ {REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x0200},
+ {REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x},
+}, a512_hwcg[] = {
+ {REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x0222},
+ {REG_A5XX_RBBM_CLOCK_CNTL_SP1, 0x0222},
+ {REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x0220},
+ {REG_A5XX_RBBM_CLOCK_CNTL2_SP1, 0x0220},
+ {REG_A5XX_RBBM_CLOCK_HYST_SP0, 0xF3CF},
+ {REG_A5XX_RBBM_CLOCK_HYST_SP1, 0xF3CF},
+ {REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x0080},
+ {REG_A5XX_RBBM_CLOCK_DELAY_SP1, 0x0080},
+ {REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x},
+ {REG_A5XX_RBBM_CLOCK_CNTL_TP1, 0x},
+ {REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x},
+ {REG_A5XX_RBBM_CLOCK_CNTL2_TP1, 0x},
+ {REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x},
+ {REG_A5XX_RBBM_CLOCK_CNTL3_TP1, 0x},
+ {REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x},
+ {REG_A5XX_RBBM_CLOCK_HYST_TP1, 0x},
+ {REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x},
+ {REG_A5XX_RBBM_CLOCK_HYST2_TP1, 0x},
+ {REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x},
+ {REG_A5XX_RBBM_CLOCK_HYST3_TP1, 0x},
+ {REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x},
+ {REG_A5XX_RBBM_CLOCK_DELAY_TP1, 0x},
+ {REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x},
+ {REG_A5XX_RBBM_CLOCK_DELAY2_TP1, 0x},
+ {REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x},
+ {REG_A5XX_RBBM_CLOCK_DELAY3_TP1, 0x},
+ {REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x},
+ {REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x},
+ {REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x},
+ {REG_A5XX_RBBM_CLOCK_
Re: [Freedreno] [pull] drm/msm: msm-next for 5.10
Assuming I merged it right, 32-bit builds adds warning In file included from /home/airlied/devel/kernel/dim/src/include/linux/bitops.h:5, from /home/airlied/devel/kernel/dim/src/include/linux/kernel.h:12, from /home/airlied/devel/kernel/dim/src/include/linux/ascii85.h:11, from /home/airlied/devel/kernel/dim/src/drivers/gpu/drm/msm/adreno/adreno_gpu.c:9: /home/airlied/devel/kernel/dim/src/drivers/gpu/drm/msm/adreno/adreno_gpu.c: In function ‘adreno_iommu_create_address_space’: /home/airlied/devel/kernel/dim/src/include/linux/bits.h:36:11: warning: right shift count is negative [-Wshift-count-negative] (~UL(0) >> (BITS_PER_LONG - 1 - (h ^~ /home/airlied/devel/kernel/dim/src/include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’ (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l)) ^ /home/airlied/devel/kernel/dim/src/drivers/gpu/drm/msm/adreno/adreno_gpu.c:212:11: note: in expansion of macro ‘GENMASK’ start & GENMASK(48, 0), size); ^~~ CC [M] drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.o /home/airlied/devel/kernel/dim/src/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c: In function ‘msm_dsi_pll_7nm_init’: /home/airlied/devel/kernel/dim/src/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c:882:19: warning: conversion from ‘long long unsigned int’ to ‘long unsigned int’ changes value from ‘50’ to ‘705032704’ [-Woverflow] pll->max_rate = 50UL; ^~~~ LD [M] drivers/gpu/drm/msm/msm.o Dave. On Mon, 28 Sep 2020 at 03:14, Rob Clark wrote: > > Hi Dave, > > A bit bigger this time around, with the addition of DP support > which has been baking for a while now. Overall: > > * DSI support for sm8150/sm8250 > * Support for per-process GPU pagetables (finally!) for a6xx. > There are still some iommu/arm-smmu changes required to > enable, without which it will fallback to the current single > pgtable state. The first part (ie. what doesn't depend on > drm side patches) is queued up for v5.10[1]. > * DisplayPort support. Userspace DP compliance tool support > is already merged in IGT[2] > * The usual assortment of smaller fixes/cleanups > > > [1] > https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-joerg/arm-smmu/updates > [2] > https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/commit/222051026b978ebbc0dc58db62d7a1f29728f95f > > The following changes since commit f6828e0c4045f03f9cf2df6c2a768102641183f4: > > drm/msm: Disable the RPTR shadow (2020-09-04 12:14:15 -0700) > > are available in the Git repository at: > > https://gitlab.freedesktop.org/drm/msm.git tags/drm-msm-next-2020-09-27 > > for you to fetch changes up to d1ea914925856d397b0b3241428f20b945e31434: > > drm/msm/dp: fix incorrect function prototype of dp_debug_get() > (2020-09-25 20:31:06 -0700) > > > Abhinav Kumar (10): > drm/msm/dp: store dp_display in the driver data > drm/msm/dp: add audio support for Display Port on MSM > drm/msm/dp: add hook_plugged_cb hdmi-codec op for MSM DP driver > drm/msm/dp: signal the hotplug disconnect in the event handler > drm/msm/dp: wait for audio notification before disabling clocks > drm/msm/dp: add debugfs support to DP driver > drm/msm/dp: move debugfs node to /sys/kernel/debug/dri/*/ > drm/msm/dp: add debugfs nodes for video pattern tests > drm/msm/dp: remove mode hard-coding in case of DP CTS > drm/msm/dp: fix incorrect function prototype of dp_debug_get() > > Akhil P Oommen (2): > drm/msm: Fix premature purging of BO > drm/msm: Leave inuse count intact on map failure > > Bernard Zhao (1): > drm/msm/adreno: remove return value of function XX_print > > Chandan Uddaraju (3): > drm: add constant N value in helper file > drm/msm/dp: add displayPort driver support > drm/msm/dp: add support for DP PLL driver > > Georgi Djakov (1): > drm/msm: Remove depends on interconnect > > Jeykumar Sankaran (1): > drm/msm/dpu: add display port support in DPU > > Jonathan Marek (3): > drm/msm/dsi: remove unused clk_pre/clk_post in msm_dsi_dphy_timing > drm/msm/dsi: add DSI config for sm8150 and sm8250 > drm/msm/dsi: add support for 7nm DSI PHY/PLL > > Jordan Crouse (10): > drm/msm: Add a context pointer to the submitqueue > drm/msm: Drop context arg to gpu->submit() > drm/msm: Set the global virtual address range from the IOMMU domain > drm/msm: Add support to create a local pagetable > drm/msm: Add support for private address space instances > drm/msm/a6xx: Add support for per-instance pagetables > drm/msm: Allow a5xx to mark the RPTR shadow as privileged > drm/msm: a6xx: Use WHERE_AM_I for eligible targets > drm/msm: Get rid of the REG_ADRENO offsets > drm/msm: Fix the a650 hw_apriv c
Re: [Freedreno] [PATCH v2] drm/msm/dp: return correct connection status after suspend
Quoting Kuogee Hsieh (2020-09-26 13:34:54)
> At dp_pm_resume, reinitialize both dp host controller and hpd block
dp_pm_resume()
> so that hpd connection can be detected at realtime by reading hpd state
> status register. Also hpd plug interrupt can be generated accordingly.
Can you describe more here? The subject says "return correct connection
status after suspend" so it seems that suspend connection status is
broken. How is it broken? What can be done to see if it is broken? I
think you can suspend, disconnect the DP cable, and then resume and see
that the device is connected still?
What does "hpd plug interrupt can be generated accordingly" mean? Is the
interrupt not being generated?
>
> Changes in v2:
> -- use container_of to cast correct dp_display_private pointer
>at both dp_pm_suspend and dp_pm_resume.
>
> Signed-off-by: Kuogee Hsieh
Any Fixes tag?
> diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c
> b/drivers/gpu/drm/msm/dp/dp_catalog.c
> index b15b4ce4ba35..63c5ada34c21 100644
> --- a/drivers/gpu/drm/msm/dp/dp_catalog.c
> +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
> @@ -572,6 +572,19 @@ void dp_catalog_ctrl_hpd_config(struct dp_catalog
> *dp_catalog)
> dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN);
> }
>
> +u32 dp_catalog_hpd_get_state_status(struct dp_catalog *dp_catalog)
> +{
> + struct dp_catalog_private *catalog = container_of(dp_catalog,
> + struct dp_catalog_private, dp_catalog);
> + u32 status = 0;
We don't need to assign to 0 to reassign immediately after.
> +
> + status = dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS);
> + status >>= DP_DP_HPD_STATE_STATUS_BITS_SHIFT;
> + status &= DP_DP_HPD_STATE_STATUS_BITS_MASK;
> +
> + return status;
> +}
> +
> u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog)
> {
> struct dp_catalog_private *catalog = container_of(dp_catalog,
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[Freedreno] [PATCH] drm/msm: fix 32b build warns
From: Rob Clark
Neither of these code-paths apply to older 32b devices, but it is rude
to introduce warnings.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index fd8f491f2e48..458b5b26d3c2 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -209,7 +209,7 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,
size = iommu->geometry.aperture_end - start + 1;
aspace = msm_gem_address_space_create(mmu, "gpu",
- start & GENMASK(48, 0), size);
+ start & GENMASK_ULL(48, 0), size);
if (IS_ERR(aspace) && !IS_ERR(mmu))
mmu->funcs->destroy(mmu);
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
index 029cc8bf5a04..de0dfb815125 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
@@ -879,7 +879,7 @@ struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct
platform_device *pdev, int id)
pll->max_rate = 35UL;
if (pll->type == MSM_DSI_PHY_7NM_V4_1) {
pll->min_rate = 6UL;
- pll->max_rate = 50UL;
+ pll->max_rate = (unsigned long)50ULL;
/* workaround for max rate overflowing on 32-bit builds: */
pll->max_rate = max(pll->max_rate, 0xUL);
}
--
2.26.2
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Re: [Freedreno] [PATCH] drm/msm: fix 32b build warns
On 2020-09-28 17:19, Rob Clark wrote:
From: Rob Clark
Neither of these code-paths apply to older 32b devices, but it is rude
to introduce warnings.
Signed-off-by: Rob Clark
Reviewed-by: Abhinav Kumar
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index fd8f491f2e48..458b5b26d3c2 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -209,7 +209,7 @@ adreno_iommu_create_address_space(struct msm_gpu
*gpu,
size = iommu->geometry.aperture_end - start + 1;
aspace = msm_gem_address_space_create(mmu, "gpu",
- start & GENMASK(48, 0), size);
+ start & GENMASK_ULL(48, 0), size);
if (IS_ERR(aspace) && !IS_ERR(mmu))
mmu->funcs->destroy(mmu);
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
index 029cc8bf5a04..de0dfb815125 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
@@ -879,7 +879,7 @@ struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct
platform_device *pdev, int id)
pll->max_rate = 35UL;
if (pll->type == MSM_DSI_PHY_7NM_V4_1) {
pll->min_rate = 6UL;
- pll->max_rate = 50UL;
+ pll->max_rate = (unsigned long)50ULL;
/* workaround for max rate overflowing on 32-bit builds: */
pll->max_rate = max(pll->max_rate, 0xUL);
}
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