[PATCH v7 10/13] media: hantro: handle V4L2_PIX_FMT_HEVC_SLICE control
Make sure that V4L2_PIX_FMT_HEVC_SLICE is correctly handle by v4l2 of the driver. Signed-off-by: Benjamin Gaignard --- drivers/staging/media/hantro/hantro_v4l2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c index 77d7fe62ce81..0655324fd0d4 100644 --- a/drivers/staging/media/hantro/hantro_v4l2.c +++ b/drivers/staging/media/hantro/hantro_v4l2.c @@ -392,6 +392,7 @@ hantro_update_requires_request(struct hantro_ctx *ctx, u32 fourcc) case V4L2_PIX_FMT_MPEG2_SLICE: case V4L2_PIX_FMT_VP8_FRAME: case V4L2_PIX_FMT_H264_SLICE: + case V4L2_PIX_FMT_HEVC_SLICE: ctx->fh.m2m_ctx->out_q_ctx.q.requires_requests = true; break; default: -- 2.25.1 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v7 12/13] media: hantro: IMX8M: add variant for G2/HEVC codec
Add variant to IMX8M to enable G2/HEVC codec.
Define the capabilities for the hardware up to 3840x2160.
G2 doesn't have postprocessor, use the same clocks and got it
own interruption.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Philipp Zabel
---
version 7:
- Add Philipp Reviewed-by tag.
version 5:
- remove useless postproc fields for G2
version 2:
- remove useless clocks
drivers/staging/media/hantro/hantro_drv.c | 1 +
drivers/staging/media/hantro/hantro_hw.h| 1 +
drivers/staging/media/hantro/imx8m_vpu_hw.c | 76 -
3 files changed, 76 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/media/hantro/hantro_drv.c
b/drivers/staging/media/hantro/hantro_drv.c
index 33b8bd38eac1..ed380a8bef93 100644
--- a/drivers/staging/media/hantro/hantro_drv.c
+++ b/drivers/staging/media/hantro/hantro_drv.c
@@ -574,6 +574,7 @@ static const struct of_device_id of_hantro_match[] = {
#endif
#ifdef CONFIG_VIDEO_HANTRO_IMX8M
{ .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
+ { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant },
#endif
{ /* sentinel */ }
};
diff --git a/drivers/staging/media/hantro/hantro_hw.h
b/drivers/staging/media/hantro/hantro_hw.h
index 5788188aae50..b4e7490bbe45 100644
--- a/drivers/staging/media/hantro/hantro_hw.h
+++ b/drivers/staging/media/hantro/hantro_hw.h
@@ -193,6 +193,7 @@ extern const struct hantro_variant rk3399_vpu_variant;
extern const struct hantro_variant rk3328_vpu_variant;
extern const struct hantro_variant rk3288_vpu_variant;
extern const struct hantro_variant imx8mq_vpu_variant;
+extern const struct hantro_variant imx8mq_vpu_g2_variant;
extern const struct hantro_postproc_regs hantro_g1_postproc_regs;
diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c
b/drivers/staging/media/hantro/imx8m_vpu_hw.c
index 8d0c3425234b..6de43e0edc36 100644
--- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
@@ -12,6 +12,7 @@
#include "hantro.h"
#include "hantro_jpeg.h"
#include "hantro_g1_regs.h"
+#include "hantro_g2_regs.h"
#define CTRL_SOFT_RESET0x00
#define RESET_G1 BIT(1)
@@ -129,6 +130,26 @@ static const struct hantro_fmt imx8m_vpu_dec_fmts[] = {
},
};
+static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_NV12,
+ .codec_mode = HANTRO_MODE_NONE,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE,
+ .codec_mode = HANTRO_MODE_HEVC_DEC,
+ .max_depth = 2,
+ .frmsize = {
+ .min_width = 48,
+ .max_width = 3840,
+ .step_width = MB_DIM,
+ .min_height = 48,
+ .max_height = 2160,
+ .step_height = MB_DIM,
+ },
+ },
+};
+
static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id)
{
struct hantro_dev *vpu = dev_id;
@@ -147,6 +168,24 @@ static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id)
return IRQ_HANDLED;
}
+static irqreturn_t imx8m_vpu_g2_irq(int irq, void *dev_id)
+{
+ struct hantro_dev *vpu = dev_id;
+ enum vb2_buffer_state state;
+ u32 status;
+
+ status = vdpu_read(vpu, HEVC_REG_INTERRUPT);
+ state = (status & HEVC_REG_INTERRUPT_DEC_RDY_INT) ?
+VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
+
+ vdpu_write(vpu, 0, HEVC_REG_INTERRUPT);
+ vdpu_write(vpu, HEVC_REG_CONFIG_DEC_CLK_GATE_E, HEVC_REG_CONFIG);
+
+ hantro_irq_done(vpu, state);
+
+ return IRQ_HANDLED;
+}
+
static int imx8mq_vpu_hw_init(struct hantro_dev *vpu)
{
struct device_node *np = vpu->dev->of_node;
@@ -176,6 +215,13 @@ static void imx8m_vpu_g1_reset(struct hantro_ctx *ctx)
imx8m_soft_reset(vpu, RESET_G1);
}
+static void imx8m_vpu_g2_reset(struct hantro_ctx *ctx)
+{
+ struct hantro_dev *vpu = ctx->dev;
+
+ imx8m_soft_reset(vpu, RESET_G2);
+}
+
/*
* Supported codec ops.
*/
@@ -201,16 +247,28 @@ static const struct hantro_codec_ops
imx8mq_vpu_codec_ops[] = {
},
};
+static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = {
+ [HANTRO_MODE_HEVC_DEC] = {
+ .run = hantro_g2_hevc_dec_run,
+ .reset = imx8m_vpu_g2_reset,
+ .init = hantro_hevc_dec_init,
+ .exit = hantro_hevc_dec_exit,
+ },
+};
+
/*
* VPU variants.
*/
static const struct hantro_irq imx8mq_irqs[] = {
{ "g1", imx8m_vpu_g1_irq },
- { "g2", NULL /* TODO: imx8m_vpu_g2_irq */ },
};
-static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" };
+static const struct hantro_irq imx8mq_g2_irqs[] = {
+ { "g2", imx8m_vpu_g2_irq },
+};
+
+static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus"};
const struct hantro_variant imx8mq_vpu_variant = {
[PATCH v7 11/13] media: hantro: Introduce G2/HEVC decoder
Implement all the logic to get G2 hardware decoding HEVC frames.
It support up level 5.1 HEVC stream.
It doesn't support yet 10 bits formats or scaling feature.
Add HANTRO HEVC dedicated control to skip some bits at the beginning
of the slice header. That is very specific to this hardware so can't
go into uapi structures. Compute the needed value is complex and require
information from the stream that only the userland knows so let it
provide the correct value to the driver.
Signed-off-by: Benjamin Gaignard
Co-developed-by: Adrian Ratiu
Signed-off-by: Adrian Ratiu
Co-developed-by: Ezequiel Garcia
Signed-off-by: Ezequiel Garcia
---
version 7:
- Improve motion vectors requested memory size computation.
drivers/staging/media/hantro/Makefile | 2 +
drivers/staging/media/hantro/hantro.h | 2 +
drivers/staging/media/hantro/hantro_drv.c | 36 ++
.../staging/media/hantro/hantro_g2_hevc_dec.c | 587 ++
drivers/staging/media/hantro/hantro_g2_regs.h | 198 ++
drivers/staging/media/hantro/hantro_hevc.c| 325 ++
drivers/staging/media/hantro/hantro_hw.h | 49 ++
7 files changed, 1199 insertions(+)
create mode 100644 drivers/staging/media/hantro/hantro_g2_hevc_dec.c
create mode 100644 drivers/staging/media/hantro/hantro_g2_regs.h
create mode 100644 drivers/staging/media/hantro/hantro_hevc.c
diff --git a/drivers/staging/media/hantro/Makefile
b/drivers/staging/media/hantro/Makefile
index 743ce08eb184..0357f1772267 100644
--- a/drivers/staging/media/hantro/Makefile
+++ b/drivers/staging/media/hantro/Makefile
@@ -9,12 +9,14 @@ hantro-vpu-y += \
hantro_h1_jpeg_enc.o \
hantro_g1_h264_dec.o \
hantro_g1_mpeg2_dec.o \
+ hantro_g2_hevc_dec.o \
hantro_g1_vp8_dec.o \
rk3399_vpu_hw_jpeg_enc.o \
rk3399_vpu_hw_mpeg2_dec.o \
rk3399_vpu_hw_vp8_dec.o \
hantro_jpeg.o \
hantro_h264.o \
+ hantro_hevc.o \
hantro_mpeg2.o \
hantro_vp8.o
diff --git a/drivers/staging/media/hantro/hantro.h
b/drivers/staging/media/hantro/hantro.h
index 7a5ad93466c8..6a21d1e95b34 100644
--- a/drivers/staging/media/hantro/hantro.h
+++ b/drivers/staging/media/hantro/hantro.h
@@ -222,6 +222,7 @@ struct hantro_dev {
* @jpeg_enc: JPEG-encoding context.
* @mpeg2_dec: MPEG-2-decoding context.
* @vp8_dec: VP8-decoding context.
+ * @hevc_dec: HEVC-decoding context.
*/
struct hantro_ctx {
struct hantro_dev *dev;
@@ -248,6 +249,7 @@ struct hantro_ctx {
struct hantro_jpeg_enc_hw_ctx jpeg_enc;
struct hantro_mpeg2_dec_hw_ctx mpeg2_dec;
struct hantro_vp8_dec_hw_ctx vp8_dec;
+ struct hantro_hevc_dec_hw_ctx hevc_dec;
};
};
diff --git a/drivers/staging/media/hantro/hantro_drv.c
b/drivers/staging/media/hantro/hantro_drv.c
index d9a3a5ef9330..33b8bd38eac1 100644
--- a/drivers/staging/media/hantro/hantro_drv.c
+++ b/drivers/staging/media/hantro/hantro_drv.c
@@ -281,6 +281,26 @@ static int hantro_jpeg_s_ctrl(struct v4l2_ctrl *ctrl)
return 0;
}
+static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct hantro_ctx *ctx;
+
+ ctx = container_of(ctrl->handler,
+ struct hantro_ctx, ctrl_handler);
+
+ vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
+
+ switch (ctrl->id) {
+ case V4L2_CID_HANTRO_HEVC_SLICE_HEADER_SKIP:
+ ctx->hevc_dec.ctrls.hevc_hdr_skip_length = ctrl->val;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static const struct v4l2_ctrl_ops hantro_ctrl_ops = {
.try_ctrl = hantro_try_ctrl,
};
@@ -289,6 +309,10 @@ static const struct v4l2_ctrl_ops hantro_jpeg_ctrl_ops = {
.s_ctrl = hantro_jpeg_s_ctrl,
};
+static const struct v4l2_ctrl_ops hantro_hevc_ctrl_ops = {
+ .s_ctrl = hantro_hevc_s_ctrl,
+};
+
static const struct hantro_ctrl controls[] = {
{
.codec = HANTRO_JPEG_ENCODER,
@@ -409,6 +433,18 @@ static const struct hantro_ctrl controls[] = {
.cfg = {
.id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS,
},
+ }, {
+ .codec = HANTRO_HEVC_DECODER,
+ .cfg = {
+ .id = V4L2_CID_HANTRO_HEVC_SLICE_HEADER_SKIP,
+ .name = "Hantro HEVC slice header skip bytes",
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .min = 0,
+ .def = 0,
+ .max = 0x7fff,
+ .step = 1,
+ .ops = &hantro_hevc_ctrl_ops,
+ },
},
};
diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c
b/drivers/staging/media/hantro/hantro_g2_
[PATCH v7 13/13] arm64: dts: imx8mq: Add node to G2 hardware
Split VPU node in two: one for G1 and one for G2 since they are
different hardware blocks.
Add syscon for hardware control block.
Remove reg-names property that is useless.
Each VPU node only need one interrupt.
Change G2 assigned clock to match to the specifications.
In the both nodes all the clocks need to assigned to make
sure that control block will be correctly clocked even if
only one device node is enabled.
Signed-off-by: Benjamin Gaignard
---
version 7:
- use nxp,imx8m-vpu-ctrl as phandle syscon property name
version 5:
- use syscon instead of VPU reset
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 43 ++-
1 file changed, 34 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 17c449e12c2e..65158414d255 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1329,15 +1329,16 @@ usb3_phy1: usb-phy@382f0040 {
status = "disabled";
};
- vpu: video-codec@3830 {
+ vpu_ctrl: syscon@3832 {
+ compatible = "nxp,imx8mq-vpu-ctrl", "syscon";
+ reg = <0x3832 0x1>;
+ };
+
+ vpu_g1: video-codec@3830 {
compatible = "nxp,imx8mq-vpu";
- reg = <0x3830 0x1>,
- <0x3831 0x1>,
- <0x3832 0x1>;
- reg-names = "g1", "g2", "ctrl";
- interrupts = ,
-;
- interrupt-names = "g1", "g2";
+ reg = <0x3830 0x1>;
+ interrupts = ;
+ interrupt-names = "g1";
clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
<&clk IMX8MQ_CLK_VPU_G2_ROOT>,
<&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
@@ -1350,9 +1351,33 @@ vpu: video-codec@3830 {
<&clk IMX8MQ_VPU_PLL_OUT>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_VPU_PLL>;
- assigned-clock-rates = <6>, <6>,
+ assigned-clock-rates = <6>, <3>,
+ <8>, <0>;
+ power-domains = <&pgc_vpu>;
+ nxp,imx8m-vpu-ctrl = <&vpu_ctrl>;
+ };
+
+ vpu_g2: video-codec@3831 {
+ compatible = "nxp,imx8mq-vpu-g2";
+ reg = <0x3831 0x1>;
+ interrupts = ;
+ interrupt-names = "g2";
+ clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
+<&clk IMX8MQ_CLK_VPU_G2_ROOT>,
+<&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+ clock-names = "g1", "g2", "bus";
+ assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
+ <&clk IMX8MQ_CLK_VPU_G2>,
+ <&clk IMX8MQ_CLK_VPU_BUS>,
+ <&clk IMX8MQ_VPU_PLL_BYPASS>;
+ assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
+<&clk IMX8MQ_VPU_PLL_OUT>,
+<&clk IMX8MQ_SYS1_PLL_800M>,
+<&clk IMX8MQ_VPU_PLL>;
+ assigned-clock-rates = <6>, <3>,
<8>, <0>;
power-domains = <&pgc_vpu>;
+ nxp,imx8m-vpu-ctrl = <&vpu_ctrl>;
};
pcie0: pcie@3380 {
--
2.25.1
___
devel mailing list
de...@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH v7 01/13] dt-bindings: mfd: Add 'nxp,imx8mq-vpu-ctrl' to syscon list
On Mon, 29 Mar 2021, Benjamin Gaignard wrote: > Add 'nxp,imx8mq-vpu-ctrl' in the list of possible syscon. > It will used to access to the VPU control registers. > > Signed-off-by: Benjamin Gaignard > Acked-by: Rob Herring > --- > version 7: > - Add Rob ack > Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + > 1 file changed, 1 insertion(+) Acked-by: Lee Jones -- Lee Jones [李琼斯] Senior Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH v6 4/5] drm/bridge: anx7625: add HDCP support
On Thu, Mar 25, 2021 at 02:19:23PM -0400, Sean Paul wrote:
> On Fri, Mar 19, 2021 at 2:35 AM Xin Ji wrote:
> >
> > Add HDCP feature, enable HDCP function through chip internal key
> > and downstream's capability.
> >
> > Signed-off-by: Xin Ji
> > ---
> > drivers/gpu/drm/bridge/analogix/anx7625.c | 147 ++
> > drivers/gpu/drm/bridge/analogix/anx7625.h | 36 ++
> > 2 files changed, 183 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c
> > b/drivers/gpu/drm/bridge/analogix/anx7625.c
> > index 8c514b46d361..b424a570effa 100644
> > --- a/drivers/gpu/drm/bridge/analogix/anx7625.c
> > +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
> > @@ -633,6 +633,150 @@ static int anx7625_dpi_config(struct anx7625_data
> > *ctx)
> > return ret;
> > }
> >
> > +static int anx7625_aux_dpcd_read(struct anx7625_data *ctx,
> > +u8 addrh, u8 addrm, u8 addrl,
> > +u8 len, u8 *buf)
> > +{
> > + struct device *dev = &ctx->client->dev;
> > + int ret;
> > + u8 cmd;
> > +
> > + if (len > MAX_DPCD_BUFFER_SIZE) {
> > + DRM_DEV_ERROR(dev, "exceed aux buffer len.\n");
> > + return -E2BIG;
> > + }
> > +
> > + cmd = ((len - 1) << 4) | 0x09;
> > +
> > + /* Set command and length */
> > + ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > + AP_AUX_COMMAND, cmd);
> > +
> > + /* Set aux access address */
> > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > +AP_AUX_ADDR_7_0, addrl);
> > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > +AP_AUX_ADDR_15_8, addrm);
> > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > +AP_AUX_ADDR_19_16, addrh);
> > +
> > + /* Enable aux access */
> > + ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
> > + AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
> > +
> > + if (ret < 0) {
> > + DRM_DEV_ERROR(dev, "cannot access aux related register.\n");
> > + return -EIO;
> > + }
> > +
> > + usleep_range(2000, 2100);
> > +
> > + ret = wait_aux_op_finish(ctx);
> > + if (ret) {
> > + DRM_DEV_ERROR(dev, "aux IO error: wait aux op finish.\n");
> > + return ret;
> > + }
> > +
> > + ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
> > +AP_AUX_BUFF_START, len, buf);
> > + if (ret < 0) {
> > + DRM_DEV_ERROR(dev, "read dpcd register failed\n");
> > + return -EIO;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int anx7625_read_flash_status(struct anx7625_data *ctx)
> > +{
> > + return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL);
> > +}
> > +
> > +static int anx7625_hdcp_key_probe(struct anx7625_data *ctx)
> > +{
> > + int ret, val;
> > + struct device *dev = &ctx->client->dev;
> > + u8 ident[32];
> > +
> > + ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > + FLASH_ADDR_HIGH, 0x91);
> > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > +FLASH_ADDR_LOW, 0xA0);
> > + if (ret < 0) {
> > + DRM_DEV_ERROR(dev, "IO error : set key flash address.\n");
> > + return ret;
> > + }
> > +
> > + ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > + FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8);
> > + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > +FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF);
> > + if (ret < 0) {
> > + DRM_DEV_ERROR(dev, "IO error : set key flash len.\n");
> > + return ret;
> > + }
> > +
> > + ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> > + R_FLASH_RW_CTRL, FLASH_READ);
> > + ret |= readx_poll_timeout(anx7625_read_flash_status,
> > + ctx, val,
> > + ((val & FLASH_DONE) || (val < 0)),
> > + 2000,
> > + 2000 * 150);
> > + if (ret) {
> > + DRM_DEV_ERROR(dev, "flash read access fail!\n");
> > + return -EIO;
> > + }
> > +
> > + ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
> > +FLASH_BUF_BASE_ADDR,
> > +FLASH_BUF_LEN, ident);
> > + if (ret < 0) {
> > + DRM_DEV_ERROR(dev, "read flash data fail!\n");
> > + return -EIO;
> > + }
> > +
> > + if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xF
Re: [PATCH v6 4/5] drm/bridge: anx7625: add HDCP support
On Mon, Mar 29, 2021 at 6:27 AM Xin Ji wrote:
>
> On Thu, Mar 25, 2021 at 02:19:23PM -0400, Sean Paul wrote:
> > On Fri, Mar 19, 2021 at 2:35 AM Xin Ji wrote:
> > >
> > > Add HDCP feature, enable HDCP function through chip internal key
> > > and downstream's capability.
> > >
> > > Signed-off-by: Xin Ji
> > > ---
/snip
> > > static void anx7625_dp_start(struct anx7625_data *ctx)
> > > {
> > > int ret;
> > > @@ -643,6 +787,9 @@ static void anx7625_dp_start(struct anx7625_data *ctx)
> > > return;
> > > }
> > >
> > > + /* HDCP config */
> > > + anx7625_hdcp_setting(ctx);
> >
> > You should really use the "Content Protection" property to
> > enable/disable HDCP instead of force-enabling it at all times.
> >
> > Sean
> Hi Sean, it's hard to implement "Content Protection" property, we have
> implemented HDCP in firmware, it is not compatible with it. We don't
> have interface to get Downstream Cert.
> Thanks,
> Xin
Hi Xin,
I'm sorry, I don't understand what you mean when you say you don't
have an interface to get Downstream Cert.
The Content Protection property is just a means through which
userspace can turn on and turn off HDCP when it needs. As far as I can
tell, your patch turns on HDCP when the display is enabled and leaves
it on until it is disabled. This is undesirable since it forces HDCP
on the user.
Is it impossible to enable/disable HDCP outside of display
enable/disable on your hardware?
Thanks,
Sean
> >
> > > +
> > > if (ctx->pdata.is_dpi)
> > > ret = anx7625_dpi_config(ctx);
> > > else
/snip
___
devel mailing list
de...@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH v7 04/13] media: hevc: Add fields and flags for hevc PPS
On Mon, 2021-03-29 at 08:57 +0200, Benjamin Gaignard wrote:
> Add fields and flags as they are defined in
> 7.4.3.3.1 "General picture parameter set RBSP semantics of the
> H.265 ITU specification.
>
> Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
> ---
> .../userspace-api/media/v4l/ext-ctrls-codec.rst | 14 ++
> include/media/hevc-ctrls.h | 4
> 2 files changed, 18 insertions(+)
>
> diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> index 188aef8e40d0..92314aec655a 100644
> --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
> @@ -2967,6 +2967,12 @@ enum v4l2_mpeg_video_hevc_size_of_length_field -
> * - __u8
> - ``num_extra_slice_header_bits``
> -
> + * - __u8
> + - ``num_ref_idx_l0_default_active_minus1``
> + - Specifies the inferred value of num_ref_idx_l0_active_minus1
> + * - __u8
> + - ``num_ref_idx_l1_default_active_minus1``
> + - Specifies the inferred value of num_ref_idx_l1_active_minus1
> * - __s8
> - ``init_qp_minus26``
> -
> @@ -3077,6 +3083,14 @@ enum v4l2_mpeg_video_hevc_size_of_length_field -
> * - ``V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT``
> - 0x0004
> -
> + * - ``V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT``
> + - 0x0008
> + - Specifies the presence of deblocking filter control syntax elements
> in
> + the PPS
> + * - ``V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING``
> + - 0x0010
> + - Specifies that tile column boundaries and likewise tile row
> boundaries
> + are distributed uniformly across the picture
>
> .. raw:: latex
>
> diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h
> index b4cb2ef02f17..003f819ecb26 100644
> --- a/include/media/hevc-ctrls.h
> +++ b/include/media/hevc-ctrls.h
> @@ -100,10 +100,14 @@ struct v4l2_ctrl_hevc_sps {
> #define V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER (1ULL << 16)
> #define V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT (1ULL << 17)
> #define V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT (1ULL <<
> 18)
> +#define V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT (1ULL << 19)
> +#define V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING (1ULL << 20)
>
> struct v4l2_ctrl_hevc_pps {
> /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */
> __u8num_extra_slice_header_bits;
> + __u8num_ref_idx_l0_default_active_minus1;
> + __u8num_ref_idx_l1_default_active_minus1;
> __s8init_qp_minus26;
> __u8diff_cu_qp_delta_depth;
> __s8pps_cb_qp_offset;
___
devel mailing list
de...@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH v7 06/13] media: hantro: change hantro_codec_ops run prototype to return errors
On Mon, 2021-03-29 at 08:57 +0200, Benjamin Gaignard wrote:
> Change hantro_codec_ops run prototype from 'void' to 'int'.
> This allow to cancel the job if an error occur while configuring
> the hardware.
>
> Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
> ---
> version 5:
> - forward hantro_h264_dec_prepare_run() return value in case
> of error
>
> drivers/staging/media/hantro/hantro_drv.c | 4 +++-
> .../staging/media/hantro/hantro_g1_h264_dec.c | 10 +++---
> .../media/hantro/hantro_g1_mpeg2_dec.c | 4 +++-
> .../staging/media/hantro/hantro_g1_vp8_dec.c | 6 --
> .../staging/media/hantro/hantro_h1_jpeg_enc.c | 4 +++-
> drivers/staging/media/hantro/hantro_hw.h | 19 ++-
> .../media/hantro/rk3399_vpu_hw_jpeg_enc.c | 4 +++-
> .../media/hantro/rk3399_vpu_hw_mpeg2_dec.c | 4 +++-
> .../media/hantro/rk3399_vpu_hw_vp8_dec.c | 6 --
> 9 files changed, 40 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/staging/media/hantro/hantro_drv.c
> b/drivers/staging/media/hantro/hantro_drv.c
> index 595e82a82728..02c5c2f1a88b 100644
> --- a/drivers/staging/media/hantro/hantro_drv.c
> +++ b/drivers/staging/media/hantro/hantro_drv.c
> @@ -161,7 +161,9 @@ static void device_run(void *priv)
>
> v4l2_m2m_buf_copy_metadata(src, dst, true);
>
> - ctx->codec_ops->run(ctx);
> + if (ctx->codec_ops->run(ctx))
> + goto err_cancel_job;
> +
> return;
>
> err_cancel_job:
> diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c
> b/drivers/staging/media/hantro/hantro_g1_h264_dec.c
> index 845bef73d218..5c792b7bcb79 100644
> --- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c
> +++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c
> @@ -273,13 +273,15 @@ static void set_buffers(struct hantro_ctx *ctx)
> vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, G1_REG_ADDR_QTABLE);
> }
>
> -void hantro_g1_h264_dec_run(struct hantro_ctx *ctx)
> +int hantro_g1_h264_dec_run(struct hantro_ctx *ctx)
> {
> struct hantro_dev *vpu = ctx->dev;
> + int ret;
>
> /* Prepare the H264 decoder context. */
> - if (hantro_h264_dec_prepare_run(ctx))
> - return;
> + ret = hantro_h264_dec_prepare_run(ctx);
> + if (ret)
> + return ret;
>
> /* Configure hardware registers. */
> set_params(ctx);
> @@ -301,4 +303,6 @@ void hantro_g1_h264_dec_run(struct hantro_ctx *ctx)
> G1_REG_CONFIG_DEC_CLK_GATE_E,
> G1_REG_CONFIG);
> vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT);
> +
> + return 0;
> }
> diff --git a/drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c
> b/drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c
> index 6386a3989bfe..5e8943d31dc5 100644
> --- a/drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c
> +++ b/drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c
> @@ -155,7 +155,7 @@ hantro_g1_mpeg2_dec_set_buffers(struct hantro_dev *vpu,
> struct hantro_ctx *ctx,
> vdpu_write_relaxed(vpu, backward_addr, G1_REG_REFER3_BASE);
> }
>
> -void hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx)
> +int hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx)
> {
> struct hantro_dev *vpu = ctx->dev;
> struct vb2_v4l2_buffer *src_buf, *dst_buf;
> @@ -248,4 +248,6 @@ void hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx)
>
> reg = G1_REG_DEC_E(1);
> vdpu_write(vpu, reg, G1_SWREG(1));
> +
> + return 0;
> }
> diff --git a/drivers/staging/media/hantro/hantro_g1_vp8_dec.c
> b/drivers/staging/media/hantro/hantro_g1_vp8_dec.c
> index 57002ba70176..96622a7f8279 100644
> --- a/drivers/staging/media/hantro/hantro_g1_vp8_dec.c
> +++ b/drivers/staging/media/hantro/hantro_g1_vp8_dec.c
> @@ -425,7 +425,7 @@ static void cfg_buffers(struct hantro_ctx *ctx,
> vdpu_write_relaxed(vpu, dst_dma, G1_REG_ADDR_DST);
> }
>
> -void hantro_g1_vp8_dec_run(struct hantro_ctx *ctx)
> +int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx)
> {
> const struct v4l2_ctrl_vp8_frame *hdr;
> struct hantro_dev *vpu = ctx->dev;
> @@ -438,7 +438,7 @@ void hantro_g1_vp8_dec_run(struct hantro_ctx *ctx)
>
> hdr = hantro_get_ctrl(ctx, V4L2_CID_STATELESS_VP8_FRAME);
> if (WARN_ON(!hdr))
> - return;
> + return -EINVAL;
>
> /* Reset segment_map buffer in keyframe */
> if (V4L2_VP8_FRAME_IS_KEY_FRAME(hdr) && ctx->vp8_dec.segment_map.cpu)
> @@ -498,4 +498,6 @@ void hantro_g1_vp8_dec_run(struct hantro_ctx *ctx)
> hantro_end_prepare_run(ctx);
>
> vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT);
> +
> + return 0;
> }
> diff --git a/drivers/staging/media/hantro/hantro_h1_jpeg_enc.c
> b/drivers/staging/media/hantro/hantro_h1_jpeg_enc.c
> index b88dc4ed06db..56cf261a8e95 100644
> --- a/drivers/staging/media/hantro/hantro_h1_jpeg_enc.
Re: [PATCH v7 07/13] media: hantro: Define HEVC codec profiles and supported features
On Mon, 2021-03-29 at 08:57 +0200, Benjamin Gaignard wrote:
> Define which HEVC profiles (up to level 5.1) and features
> (no scaling, no 10 bits) are supported by the driver.
>
> Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
> ---
> drivers/staging/media/hantro/hantro.h | 3 ++
> drivers/staging/media/hantro/hantro_drv.c | 58 +++
> 2 files changed, 61 insertions(+)
>
> diff --git a/drivers/staging/media/hantro/hantro.h
> b/drivers/staging/media/hantro/hantro.h
> index 37b9ce04bd4e..edb4561a6887 100644
> --- a/drivers/staging/media/hantro/hantro.h
> +++ b/drivers/staging/media/hantro/hantro.h
> @@ -35,6 +35,7 @@ struct hantro_codec_ops;
> #define HANTRO_MPEG2_DECODER BIT(16)
> #define HANTRO_VP8_DECODER BIT(17)
> #define HANTRO_H264_DECODERBIT(18)
> +#define HANTRO_HEVC_DECODERBIT(19)
> #define HANTRO_DECODERS0x
>
> /**
> @@ -100,6 +101,7 @@ struct hantro_variant {
> * @HANTRO_MODE_H264_DEC: H264 decoder.
> * @HANTRO_MODE_MPEG2_DEC: MPEG-2 decoder.
> * @HANTRO_MODE_VP8_DEC: VP8 decoder.
> + * @HANTRO_MODE_HEVC_DEC: HEVC decoder.
> */
> enum hantro_codec_mode {
> HANTRO_MODE_NONE = -1,
> @@ -107,6 +109,7 @@ enum hantro_codec_mode {
> HANTRO_MODE_H264_DEC,
> HANTRO_MODE_MPEG2_DEC,
> HANTRO_MODE_VP8_DEC,
> + HANTRO_MODE_HEVC_DEC,
> };
>
> /*
> diff --git a/drivers/staging/media/hantro/hantro_drv.c
> b/drivers/staging/media/hantro/hantro_drv.c
> index 02c5c2f1a88b..d9a3a5ef9330 100644
> --- a/drivers/staging/media/hantro/hantro_drv.c
> +++ b/drivers/staging/media/hantro/hantro_drv.c
> @@ -245,6 +245,18 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl)
> if (sps->bit_depth_luma_minus8 != 0)
> /* Only 8-bit is supported */
> return -EINVAL;
> + } else if (ctrl->id == V4L2_CID_MPEG_VIDEO_HEVC_SPS) {
> + const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
> +
> + if (sps->bit_depth_luma_minus8 !=
> sps->bit_depth_chroma_minus8)
> + /* Luma and chroma bit depth mismatch */
> + return -EINVAL;
> + if (sps->bit_depth_luma_minus8 != 0)
> + /* Only 8-bit is supported */
> + return -EINVAL;
> + if (sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED)
> + /* No scaling support */
> + return -EINVAL;
> }
> return 0;
> }
> @@ -351,6 +363,52 @@ static const struct hantro_ctrl controls[] = {
> .def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN,
> }
> }, {
> + .codec = HANTRO_HEVC_DECODER,
> + .cfg = {
> + .id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE,
> + .min = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
> + .max = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
> + .def = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
> + },
> + }, {
> + .codec = HANTRO_HEVC_DECODER,
> + .cfg = {
> + .id = V4L2_CID_MPEG_VIDEO_HEVC_START_CODE,
> + .min = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B,
> + .max = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B,
> + .def = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B,
> + },
> + }, {
> + .codec = HANTRO_HEVC_DECODER,
> + .cfg = {
> + .id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
> + .min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> + .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
> + .def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> + },
> + }, {
> + .codec = HANTRO_HEVC_DECODER,
> + .cfg = {
> + .id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
> + .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
> + .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
> + },
> + }, {
> + .codec = HANTRO_HEVC_DECODER,
> + .cfg = {
> + .id = V4L2_CID_MPEG_VIDEO_HEVC_SPS,
> + .ops = &hantro_ctrl_ops,
> + },
> + }, {
> + .codec = HANTRO_HEVC_DECODER,
> + .cfg = {
> + .id = V4L2_CID_MPEG_VIDEO_HEVC_PPS,
> + },
> + }, {
> + .codec = HANTRO_HEVC_DECODER,
> + .cfg = {
> + .id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS,
> + },
> },
> };
>
___
devel mailing list
de...@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/list
Re: [PATCH v7 08/13] media: hantro: Only use postproc when post processed formats are defined
On Mon, 2021-03-29 at 08:57 +0200, Benjamin Gaignard wrote:
> If the variant doesn't offert postprocessed formats make sure it will
> be ok.
>
> Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
> ---
> drivers/staging/media/hantro/hantro.h | 8 ++--
> drivers/staging/media/hantro/hantro_postproc.c | 14 ++
> drivers/staging/media/hantro/hantro_v4l2.c | 4 +++-
> 3 files changed, 19 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/staging/media/hantro/hantro.h
> b/drivers/staging/media/hantro/hantro.h
> index edb4561a6887..7a5ad93466c8 100644
> --- a/drivers/staging/media/hantro/hantro.h
> +++ b/drivers/staging/media/hantro/hantro.h
> @@ -414,12 +414,8 @@ hantro_get_dst_buf(struct hantro_ctx *ctx)
> return v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
> }
>
> -static inline bool
> -hantro_needs_postproc(const struct hantro_ctx *ctx,
> - const struct hantro_fmt *fmt)
> -{
> - return !ctx->is_encoder && fmt->fourcc != V4L2_PIX_FMT_NV12;
> -}
> +bool hantro_needs_postproc(const struct hantro_ctx *ctx,
> + const struct hantro_fmt *fmt);
>
> static inline dma_addr_t
> hantro_get_dec_buf_addr(struct hantro_ctx *ctx, struct vb2_buffer *vb)
> diff --git a/drivers/staging/media/hantro/hantro_postproc.c
> b/drivers/staging/media/hantro/hantro_postproc.c
> index 6d2a8f2a8f0b..ed8916c950a4 100644
> --- a/drivers/staging/media/hantro/hantro_postproc.c
> +++ b/drivers/staging/media/hantro/hantro_postproc.c
> @@ -50,6 +50,20 @@ const struct hantro_postproc_regs hantro_g1_postproc_regs
> = {
> .display_width = {G1_REG_PP_DISPLAY_WIDTH, 0, 0xfff},
> };
>
> +bool hantro_needs_postproc(const struct hantro_ctx *ctx,
> + const struct hantro_fmt *fmt)
> +{
> + struct hantro_dev *vpu = ctx->dev;
> +
> + if (ctx->is_encoder)
> + return false;
> +
> + if (!vpu->variant->postproc_fmts)
> + return false;
> +
> + return fmt->fourcc != V4L2_PIX_FMT_NV12;
> +}
> +
> void hantro_postproc_enable(struct hantro_ctx *ctx)
> {
> struct hantro_dev *vpu = ctx->dev;
> diff --git a/drivers/staging/media/hantro/hantro_v4l2.c
> b/drivers/staging/media/hantro/hantro_v4l2.c
> index 1bc118e375a1..77d7fe62ce81 100644
> --- a/drivers/staging/media/hantro/hantro_v4l2.c
> +++ b/drivers/staging/media/hantro/hantro_v4l2.c
> @@ -55,7 +55,9 @@ static const struct hantro_fmt *
> hantro_get_postproc_formats(const struct hantro_ctx *ctx,
> unsigned int *num_fmts)
> {
> - if (ctx->is_encoder) {
> + struct hantro_dev *vpu = ctx->dev;
> +
> + if (ctx->is_encoder || !vpu->variant->postproc_fmts) {
> *num_fmts = 0;
> return NULL;
> }
___
devel mailing list
de...@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH v7 10/13] media: hantro: handle V4L2_PIX_FMT_HEVC_SLICE control
On Mon, 2021-03-29 at 08:57 +0200, Benjamin Gaignard wrote: > Make sure that V4L2_PIX_FMT_HEVC_SLICE is correctly handle by v4l2 > of the driver. > > Signed-off-by: Benjamin Gaignard Reviewed-by: Ezequiel Garcia > --- > drivers/staging/media/hantro/hantro_v4l2.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/staging/media/hantro/hantro_v4l2.c > b/drivers/staging/media/hantro/hantro_v4l2.c > index 77d7fe62ce81..0655324fd0d4 100644 > --- a/drivers/staging/media/hantro/hantro_v4l2.c > +++ b/drivers/staging/media/hantro/hantro_v4l2.c > @@ -392,6 +392,7 @@ hantro_update_requires_request(struct hantro_ctx *ctx, > u32 fourcc) > case V4L2_PIX_FMT_MPEG2_SLICE: > case V4L2_PIX_FMT_VP8_FRAME: > case V4L2_PIX_FMT_H264_SLICE: > + case V4L2_PIX_FMT_HEVC_SLICE: > ctx->fh.m2m_ctx->out_q_ctx.q.requires_requests = true; > break; > default: ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH v7 12/13] media: hantro: IMX8M: add variant for G2/HEVC codec
On Mon, 2021-03-29 at 08:57 +0200, Benjamin Gaignard wrote:
> Add variant to IMX8M to enable G2/HEVC codec.
> Define the capabilities for the hardware up to 3840x2160.
> G2 doesn't have postprocessor, use the same clocks and got it
> own interruption.
>
> Signed-off-by: Benjamin Gaignard
> Reviewed-by: Philipp Zabel
Reviewed-by: Ezequiel Garcia
> ---
> version 7:
> - Add Philipp Reviewed-by tag.
>
> version 5:
> - remove useless postproc fields for G2
>
> version 2:
> - remove useless clocks
>
> drivers/staging/media/hantro/hantro_drv.c | 1 +
> drivers/staging/media/hantro/hantro_hw.h | 1 +
> drivers/staging/media/hantro/imx8m_vpu_hw.c | 76 -
> 3 files changed, 76 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/staging/media/hantro/hantro_drv.c
> b/drivers/staging/media/hantro/hantro_drv.c
> index 33b8bd38eac1..ed380a8bef93 100644
> --- a/drivers/staging/media/hantro/hantro_drv.c
> +++ b/drivers/staging/media/hantro/hantro_drv.c
> @@ -574,6 +574,7 @@ static const struct of_device_id of_hantro_match[] = {
> #endif
> #ifdef CONFIG_VIDEO_HANTRO_IMX8M
> { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
> + { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant },
> #endif
> { /* sentinel */ }
> };
> diff --git a/drivers/staging/media/hantro/hantro_hw.h
> b/drivers/staging/media/hantro/hantro_hw.h
> index 5788188aae50..b4e7490bbe45 100644
> --- a/drivers/staging/media/hantro/hantro_hw.h
> +++ b/drivers/staging/media/hantro/hantro_hw.h
> @@ -193,6 +193,7 @@ extern const struct hantro_variant rk3399_vpu_variant;
> extern const struct hantro_variant rk3328_vpu_variant;
> extern const struct hantro_variant rk3288_vpu_variant;
> extern const struct hantro_variant imx8mq_vpu_variant;
> +extern const struct hantro_variant imx8mq_vpu_g2_variant;
>
> extern const struct hantro_postproc_regs hantro_g1_postproc_regs;
>
> diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c
> b/drivers/staging/media/hantro/imx8m_vpu_hw.c
> index 8d0c3425234b..6de43e0edc36 100644
> --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
> +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
> @@ -12,6 +12,7 @@
> #include "hantro.h"
> #include "hantro_jpeg.h"
> #include "hantro_g1_regs.h"
> +#include "hantro_g2_regs.h"
>
> #define CTRL_SOFT_RESET0x00
> #define RESET_G1 BIT(1)
> @@ -129,6 +130,26 @@ static const struct hantro_fmt imx8m_vpu_dec_fmts[] = {
> },
> };
>
> +static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = {
> + {
> + .fourcc = V4L2_PIX_FMT_NV12,
> + .codec_mode = HANTRO_MODE_NONE,
> + },
> + {
> + .fourcc = V4L2_PIX_FMT_HEVC_SLICE,
> + .codec_mode = HANTRO_MODE_HEVC_DEC,
> + .max_depth = 2,
> + .frmsize = {
> + .min_width = 48,
> + .max_width = 3840,
> + .step_width = MB_DIM,
> + .min_height = 48,
> + .max_height = 2160,
> + .step_height = MB_DIM,
> + },
> + },
> +};
> +
> static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id)
> {
> struct hantro_dev *vpu = dev_id;
> @@ -147,6 +168,24 @@ static irqreturn_t imx8m_vpu_g1_irq(int irq, void
> *dev_id)
> return IRQ_HANDLED;
> }
>
> +static irqreturn_t imx8m_vpu_g2_irq(int irq, void *dev_id)
> +{
> + struct hantro_dev *vpu = dev_id;
> + enum vb2_buffer_state state;
> + u32 status;
> +
> + status = vdpu_read(vpu, HEVC_REG_INTERRUPT);
> + state = (status & HEVC_REG_INTERRUPT_DEC_RDY_INT) ?
> + VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
> +
> + vdpu_write(vpu, 0, HEVC_REG_INTERRUPT);
> + vdpu_write(vpu, HEVC_REG_CONFIG_DEC_CLK_GATE_E, HEVC_REG_CONFIG);
> +
> + hantro_irq_done(vpu, state);
> +
> + return IRQ_HANDLED;
> +}
> +
> static int imx8mq_vpu_hw_init(struct hantro_dev *vpu)
> {
> struct device_node *np = vpu->dev->of_node;
> @@ -176,6 +215,13 @@ static void imx8m_vpu_g1_reset(struct hantro_ctx *ctx)
> imx8m_soft_reset(vpu, RESET_G1);
> }
>
> +static void imx8m_vpu_g2_reset(struct hantro_ctx *ctx)
> +{
> + struct hantro_dev *vpu = ctx->dev;
> +
> + imx8m_soft_reset(vpu, RESET_G2);
> +}
> +
> /*
> * Supported codec ops.
> */
> @@ -201,16 +247,28 @@ static const struct hantro_codec_ops
> imx8mq_vpu_codec_ops[] = {
> },
> };
>
> +static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = {
> + [HANTRO_MODE_HEVC_DEC] = {
> + .run = hantro_g2_hevc_dec_run,
> + .reset = imx8m_vpu_g2_reset,
> + .init = hantro_hevc_dec_init,
> + .exit = hantro_hevc_dec_exit,
> + },
> +};
> +
> /*
> * VPU variants.
> */
>
> static const struct hantro_irq imx8mq_irqs[] = {
>
Re: [PATCH v7 05/13] media: hevc: Add decode params control
On Mon, 2021-03-29 at 08:57 +0200, Benjamin Gaignard wrote: > Add decode params control and it associated structure to regroup > all the information that are needed to decode a reference frame as > it is describe in ITU-T Rec. H.265 section "8.3.2 Decoding process > for reference picture set". > > Adapt Cedrus driver to these changes. > > Signed-off-by: Benjamin Gaignard Reviewed-by: Ezequiel Garcia > --- > version 7: > - rebased on top of media_tree/master branch > > version 6: > - fix compilation errors > > .../media/v4l/ext-ctrls-codec.rst | 94 +++ > .../media/v4l/vidioc-queryctrl.rst | 6 ++ > drivers/media/v4l2-core/v4l2-ctrls.c | 26 +++-- > drivers/staging/media/sunxi/cedrus/cedrus.c | 6 ++ > drivers/staging/media/sunxi/cedrus/cedrus.h | 1 + > .../staging/media/sunxi/cedrus/cedrus_dec.c | 2 + > .../staging/media/sunxi/cedrus/cedrus_h265.c | 12 ++- > include/media/hevc-ctrls.h | 29 -- > 8 files changed, 137 insertions(+), 39 deletions(-) > > diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst > b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst > index 92314aec655a..7552869687f7 100644 > --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst > +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst > @@ -3181,9 +3181,6 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - > * - __u8 > - ``pic_struct`` > - > - * - __u8 > - - ``num_active_dpb_entries`` > - - The number of entries in ``dpb``. > * - __u8 > - ``ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` > - The list of L0 reference elements as indices in the DPB. > @@ -3191,22 +3188,8 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - > - ``ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` > - The list of L1 reference elements as indices in the DPB. > * - __u8 > - - ``num_rps_poc_st_curr_before`` > - - The number of reference pictures in the short-term set that come > before > - the current frame. > - * - __u8 > - - ``num_rps_poc_st_curr_after`` > - - The number of reference pictures in the short-term set that come > after > - the current frame. > - * - __u8 > - - ``num_rps_poc_lt_curr`` > - - The number of reference pictures in the long-term set. > - * - __u8 > - - ``padding[7]`` > + - ``padding`` > - Applications and drivers must set this to zero. > - * - struct :c:type:`v4l2_hevc_dpb_entry` > - - ``dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` > - - The decoded picture buffer, for meta-data about reference frames. > * - struct :c:type:`v4l2_hevc_pred_weight_table` > - ``pred_weight_table`` > - The prediction weight coefficients for inter-picture prediction. > @@ -3441,3 +3424,78 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - > so this has to come from client. > This is applicable to H264 and valid Range is from 0 to 63. > Source Rec. ITU-T H.264 (06/2019); G.7.4.1.1, G.8.8.1. > + > +``V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS (struct)`` > + Specifies various decode parameters, especially the references picture > order > + count (POC) for all the lists (short, long, before, current, after) and > the > + number of entries for each of them. > + These parameters are defined according to :ref:`hevc`. > + They are described in section 8.3 "Slice decoding process" of the > + specification. > + > +.. c:type:: v4l2_ctrl_hevc_decode_params > + > +.. cssclass:: longtable > + > +.. flat-table:: struct v4l2_ctrl_hevc_decode_params > + :header-rows: 0 > + :stub-columns: 0 > + :widths: 1 1 2 > + > + * - __s32 > + - ``pic_order_cnt_val`` > + - PicOrderCntVal as described in section 8.3.1 "Decoding process > + for picture order count" of the specification. > + * - __u8 > + - ``num_active_dpb_entries`` > + - The number of entries in ``dpb``. > + * - struct :c:type:`v4l2_hevc_dpb_entry` > + - ``dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` > + - The decoded picture buffer, for meta-data about reference frames. > + * - __u8 > + - ``num_poc_st_curr_before`` > + - The number of reference pictures in the short-term set that come > before > + the current frame. > + * - __u8 > + - ``num_poc_st_curr_after`` > + - The number of reference pictures in the short-term set that come > after > + the current frame. > + * - __u8 > + - ``num_poc_lt_curr`` > + - The number of reference pictures in the long-term set. > + * - __u8 > + - ``poc_st_curr_before[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` > + - PocStCurrBefore as described in section 8.3.2 "Decoding process for > reference > + picture set. > + * - __u8 > + - ``poc_st_curr_after[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` > + - PocStCurrAfter as described in section 8.3.2 "Dec
[syzbot] KMSAN: uninit-value in efuse_one_byte_read
Hello, syzbot found the following issue on: HEAD commit:29ad81a1 arch/x86: add missing include to sparsemem.h git tree: https://github.com/google/kmsan.git master console output: https://syzkaller.appspot.com/x/log.txt?x=12d4e126d0 kernel config: https://syzkaller.appspot.com/x/.config?x=b573c14b733efb1c dashboard link: https://syzkaller.appspot.com/bug?extid=6610740013f861b6e829 compiler: Debian clang version 11.0.1-2 Unfortunately, I don't have any reproducer for this issue yet. IMPORTANT: if you fix the issue, please add the following tag to the commit: Reported-by: syzbot+6610740013f861b6e...@syzkaller.appspotmail.com r8712u: register rtl8712_netdev_ops to netdev_ops usb 2-1: r8712u: USB_SPEED_HIGH with 0 endpoints usb 2-1: r8712u: Boot from EEPROM: Autoload OK = BUG: KMSAN: uninit-value in efuse_one_byte_read+0x206/0x2e0 drivers/staging/rtl8712/rtl8712_efuse.c:76 CPU: 1 PID: 4662 Comm: kworker/1:3 Tainted: GW 5.11.0-rc7-syzkaller #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 Workqueue: usb_hub_wq hub_event Call Trace: __dump_stack lib/dump_stack.c:79 [inline] dump_stack+0x21c/0x280 lib/dump_stack.c:120 kmsan_report+0xfb/0x1e0 mm/kmsan/kmsan_report.c:118 __msan_warning+0x5f/0xa0 mm/kmsan/kmsan_instr.c:197 efuse_one_byte_read+0x206/0x2e0 drivers/staging/rtl8712/rtl8712_efuse.c:76 r8712_efuse_pg_packet_read+0x29c/0xcd0 drivers/staging/rtl8712/rtl8712_efuse.c:245 r871xu_drv_init+0x1cfb/0x2fe0 drivers/staging/rtl8712/usb_intf.c:443 usb_probe_interface+0xfcc/0x1520 drivers/usb/core/driver.c:396 really_probe+0xe15/0x24d0 drivers/base/dd.c:558 driver_probe_device+0x29d/0x3a0 drivers/base/dd.c:740 __device_attach_driver+0x63f/0x830 drivers/base/dd.c:846 bus_for_each_drv+0x2c8/0x3f0 drivers/base/bus.c:431 __device_attach+0x56a/0x890 drivers/base/dd.c:914 device_initial_probe+0x4a/0x60 drivers/base/dd.c:961 bus_probe_device+0x17e/0x3d0 drivers/base/bus.c:491 device_add+0x2c15/0x31d0 drivers/base/core.c:3109 usb_set_configuration+0x3872/0x3eb0 drivers/usb/core/message.c:2164 usb_generic_driver_probe+0x138/0x300 drivers/usb/core/generic.c:238 usb_probe_device+0x317/0x570 drivers/usb/core/driver.c:293 really_probe+0xe15/0x24d0 drivers/base/dd.c:558 driver_probe_device+0x29d/0x3a0 drivers/base/dd.c:740 __device_attach_driver+0x63f/0x830 drivers/base/dd.c:846 bus_for_each_drv+0x2c8/0x3f0 drivers/base/bus.c:431 __device_attach+0x56a/0x890 drivers/base/dd.c:914 device_initial_probe+0x4a/0x60 drivers/base/dd.c:961 bus_probe_device+0x17e/0x3d0 drivers/base/bus.c:491 device_add+0x2c15/0x31d0 drivers/base/core.c:3109 usb_new_device+0x1bd4/0x2a30 drivers/usb/core/hub.c:2555 hub_port_connect drivers/usb/core/hub.c:5223 [inline] hub_port_connect_change drivers/usb/core/hub.c:5363 [inline] port_event drivers/usb/core/hub.c:5509 [inline] hub_event+0x5b99/0x8870 drivers/usb/core/hub.c:5591 process_one_work+0x1219/0x1fe0 kernel/workqueue.c:2275 worker_thread+0x10ec/0x2340 kernel/workqueue.c:2421 kthread+0x521/0x560 kernel/kthread.c:292 ret_from_fork+0x1f/0x30 arch/x86/entry/entry_64.S:296 Local variable data@usb_read8 created at: usb_read8+0x5d/0x130 drivers/staging/rtl8712/usb_ops.c:33 usb_read8+0x5d/0x130 drivers/staging/rtl8712/usb_ops.c:33 = = BUG: KMSAN: uninit-value in r8712_efuse_pg_packet_read+0x77c/0xcd0 drivers/staging/rtl8712/rtl8712_efuse.c:246 CPU: 1 PID: 4662 Comm: kworker/1:3 Tainted: GB W 5.11.0-rc7-syzkaller #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 Workqueue: usb_hub_wq hub_event Call Trace: __dump_stack lib/dump_stack.c:79 [inline] dump_stack+0x21c/0x280 lib/dump_stack.c:120 kmsan_report+0xfb/0x1e0 mm/kmsan/kmsan_report.c:118 __msan_warning+0x5f/0xa0 mm/kmsan/kmsan_instr.c:197 r8712_efuse_pg_packet_read+0x77c/0xcd0 drivers/staging/rtl8712/rtl8712_efuse.c:246 r871xu_drv_init+0x1cfb/0x2fe0 drivers/staging/rtl8712/usb_intf.c:443 usb_probe_interface+0xfcc/0x1520 drivers/usb/core/driver.c:396 really_probe+0xe15/0x24d0 drivers/base/dd.c:558 driver_probe_device+0x29d/0x3a0 drivers/base/dd.c:740 __device_attach_driver+0x63f/0x830 drivers/base/dd.c:846 bus_for_each_drv+0x2c8/0x3f0 drivers/base/bus.c:431 __device_attach+0x56a/0x890 drivers/base/dd.c:914 device_initial_probe+0x4a/0x60 drivers/base/dd.c:961 bus_probe_device+0x17e/0x3d0 drivers/base/bus.c:491 device_add+0x2c15/0x31d0 drivers/base/core.c:3109 usb_set_configuration+0x3872/0x3eb0 drivers/usb/core/message.c:2164 usb_generic_driver_probe+0x138/0x300 drivers/usb/core/generic.c:238 usb_probe_device+0x317/0x570 drivers/usb/core/driver.c:293 really_probe+0xe15/0x24d0 drivers/base/dd.c:558 driver_probe_device+0x29d/0x3a0 drivers/base/dd.c:740 __device_attach_driver+0x63f/0x830 drivers/base/dd
