[PATCH 1/2] staging: rtl8188eu: rename ODM_PhyStatusQuery()
Rename ODM_PhyStatusQuery() to odm_phy_status_query() to avoid camel
case.
Signed-off-by: Michael Straube
---
drivers/staging/rtl8188eu/hal/odm_hwconfig.c | 6 +++---
drivers/staging/rtl8188eu/hal/rtl8188e_rxdesc.c | 4 ++--
drivers/staging/rtl8188eu/include/odm_hwconfig.h | 8
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/staging/rtl8188eu/hal/odm_hwconfig.c
b/drivers/staging/rtl8188eu/hal/odm_hwconfig.c
index 65a346ae3cb0..c5af0c559cba 100644
--- a/drivers/staging/rtl8188eu/hal/odm_hwconfig.c
+++ b/drivers/staging/rtl8188eu/hal/odm_hwconfig.c
@@ -385,9 +385,9 @@ static void odm_Process_RSSIForDM(struct odm_dm_struct
*dm_odm,
}
/* Endianness before calling this API */
-void ODM_PhyStatusQuery(struct odm_dm_struct *dm_odm,
- struct odm_phy_status_info *pPhyInfo,
- u8 *pPhyStatus, struct odm_per_pkt_info *pPktinfo)
+void odm_phy_status_query(struct odm_dm_struct *dm_odm,
+ struct odm_phy_status_info *pPhyInfo,
+ u8 *pPhyStatus, struct odm_per_pkt_info *pPktinfo)
{
odm_RxPhyStatus92CSeries_Parsing(dm_odm, pPhyInfo, pPhyStatus,
pPktinfo);
diff --git a/drivers/staging/rtl8188eu/hal/rtl8188e_rxdesc.c
b/drivers/staging/rtl8188eu/hal/rtl8188e_rxdesc.c
index 7d0135fde795..0d06cb54b1ad 100644
--- a/drivers/staging/rtl8188eu/hal/rtl8188e_rxdesc.c
+++ b/drivers/staging/rtl8188eu/hal/rtl8188e_rxdesc.c
@@ -171,8 +171,8 @@ void update_recvframe_phyinfo_88e(struct recv_frame
*precvframe,
pkt_info.StationID = psta->mac_id;
pkt_info.Rate = pattrib->mcs_rate;
- ODM_PhyStatusQuery(&padapter->HalData->odmpriv, pPHYInfo,
- (u8 *)pphy_status, &(pkt_info));
+ odm_phy_status_query(&padapter->HalData->odmpriv, pPHYInfo,
+(u8 *)pphy_status, &(pkt_info));
precvframe->psta = NULL;
if (pkt_info.bPacketMatchBSSID &&
diff --git a/drivers/staging/rtl8188eu/include/odm_hwconfig.h
b/drivers/staging/rtl8188eu/include/odm_hwconfig.h
index 2cd8a47a3673..dc86e4058eff 100644
--- a/drivers/staging/rtl8188eu/include/odm_hwconfig.h
+++ b/drivers/staging/rtl8188eu/include/odm_hwconfig.h
@@ -93,9 +93,9 @@ struct phy_status_rpt {
#endif
};
-void ODM_PhyStatusQuery(struct odm_dm_struct *pDM_Odm,
- struct odm_phy_status_info *pPhyInfo,
- u8 *pPhyStatus,
- struct odm_per_pkt_info *pPktinfo);
+void odm_phy_status_query(struct odm_dm_struct *pDM_Odm,
+ struct odm_phy_status_info *pPhyInfo,
+ u8 *pPhyStatus,
+ struct odm_per_pkt_info *pPktinfo);
#endif
--
2.30.1
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[PATCH 2/2] staging: rtl8188eu: rename parameters of odm_phy_status_query()
Rename parameters of odm_phy_status_query() to avoid camel case.
pDM_Odm -> dm_odm
pPhyInfo -> phy_info
pPhyStatus -> phy_status
pPktinfo -> pkt_info
Signed-off-by: Michael Straube
---
drivers/staging/rtl8188eu/hal/odm_hwconfig.c | 9 -
drivers/staging/rtl8188eu/include/odm_hwconfig.h | 8
2 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/staging/rtl8188eu/hal/odm_hwconfig.c
b/drivers/staging/rtl8188eu/hal/odm_hwconfig.c
index c5af0c559cba..684b6cec0f09 100644
--- a/drivers/staging/rtl8188eu/hal/odm_hwconfig.c
+++ b/drivers/staging/rtl8188eu/hal/odm_hwconfig.c
@@ -386,13 +386,12 @@ static void odm_Process_RSSIForDM(struct odm_dm_struct
*dm_odm,
/* Endianness before calling this API */
void odm_phy_status_query(struct odm_dm_struct *dm_odm,
- struct odm_phy_status_info *pPhyInfo,
- u8 *pPhyStatus, struct odm_per_pkt_info *pPktinfo)
+ struct odm_phy_status_info *phy_info,
+ u8 *phy_status, struct odm_per_pkt_info *pkt_info)
{
- odm_RxPhyStatus92CSeries_Parsing(dm_odm, pPhyInfo, pPhyStatus,
-pPktinfo);
+ odm_RxPhyStatus92CSeries_Parsing(dm_odm, phy_info, phy_status,
pkt_info);
if (dm_odm->RSSI_test)
;/* Select the packets to do RSSI checking for antenna
switching. */
else
- odm_Process_RSSIForDM(dm_odm, pPhyInfo, pPktinfo);
+ odm_Process_RSSIForDM(dm_odm, phy_info, pkt_info);
}
diff --git a/drivers/staging/rtl8188eu/include/odm_hwconfig.h
b/drivers/staging/rtl8188eu/include/odm_hwconfig.h
index dc86e4058eff..4f4d3cfb6c77 100644
--- a/drivers/staging/rtl8188eu/include/odm_hwconfig.h
+++ b/drivers/staging/rtl8188eu/include/odm_hwconfig.h
@@ -93,9 +93,9 @@ struct phy_status_rpt {
#endif
};
-void odm_phy_status_query(struct odm_dm_struct *pDM_Odm,
- struct odm_phy_status_info *pPhyInfo,
- u8 *pPhyStatus,
- struct odm_per_pkt_info *pPktinfo);
+void odm_phy_status_query(struct odm_dm_struct *dm_odm,
+ struct odm_phy_status_info *phy_info,
+ u8 *phy_status,
+ struct odm_per_pkt_info *pkt_info);
#endif
--
2.30.1
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Re: [PATCH] Staging: android: ashmem: fixed a struct without const
On Sat, Mar 06, 2021 at 12:38:17PM +0600, nabil5352 wrote:
> Fixed a struct without const
>
> Signed-off-by: nabil5352
> ---
> drivers/staging/android/ashmem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/staging/android/ashmem.c
> b/drivers/staging/android/ashmem.c
> index d66a64e42273..7854fd410efa 100644
> --- a/drivers/staging/android/ashmem.c
> +++ b/drivers/staging/android/ashmem.c
> @@ -376,7 +376,7 @@ ashmem_vmfile_get_unmapped_area(struct file *file,
> unsigned long addr,
>
> static int ashmem_mmap(struct file *file, struct vm_area_struct *vma)
> {
> - static struct file_operations vmfile_fops;
> + static const struct file_operations vmfile_fops;
> struct ashmem_area *asma = file->private_data;
> int ret = 0;
>
It's a bit rude to submit patches that you have not at the very least,
tried to build before sending it out to us, right?
Please always do so.
greg k-h
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Re: [PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation
Hi again,
On Sat, Mar 6, 2021 at 8:12 AM Sergio Paracuellos
wrote:
>
> Hi Rob,
>
> On Fri, Mar 5, 2021 at 11:47 PM Rob Herring wrote:
> [snip]
> > > +
> > > + ralink,sysctl:
> > > +$ref: /schemas/types.yaml#/definitions/phandle
> > > +description:
> > > + phandle of syscon used to control system registers
> > > +
> > > + ralink,memctl:
> > > +$ref: /schemas/types.yaml#/definitions/phandle
> > > +description:
> > > + phandle of syscon used to control memory registers
> >
> > I assume one of these phandles are the main registers for the clocks?
> > Make this a child node and drop that phandle.
>
> The 'ralink,sysctl' phandle is to read bootstrap register to be able
> to derive xtal and a clk gate register for the peripherals.
> The 'ralink,memctl' phandle is to read the cpu clock frequency from
> the memory controller.
>
> So there is not "main registers". I already put this as a child node
> in v4 and I was told to get rid of child nodes. I need this as a
> regmap to other DT node registers (sysctl, and memctl) to be able to
> use the driver without specific architecture operations and properly
> enable for COMPILE_TEST without dirty Makefile arch flags. Both sysctl
> and memctl has no other child nodes, and I think that's why I was told
> to avoid child nodes at the end. I explained here [0] current sysctl
> and memctl in the mt7621 device tree and my view of the need for this
> two syscons:
>
> [0]: https://lkml.org/lkml/2021/1/2/9
>
> So to avoid to send again "a previous version" on this patch, please
> guide me in the correct thing to do. Stephen, Rob, I will be really
> happy with your help :)
Since there are no other child nodes for this sysc, should merge clock
properties
with this node in the following way a valid approach:
sysc: sysc@0 {
compatible = "mediatek,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
#clock-cells = <1>;
ralink,memctl = <&memc>;
clock-output-names = "xtal", "cpu", "bus",
"50m", "125m", "150m",
"250m", "270m";
};
Consumer clock:
node: node@0 {
...
clocks = <&sysc MT7621_CLK_WHATEVER>;
...
};
If that is the case... and since 'sysc' is used as system control
registers for all the rest of the world, where should be the yaml file
with bindings placed?
Thanks in advance again for your help.
Best regards,
Sergio Paracuellos
>
> Best regards,
> Sergio Paracuellos
> >
> > > +
> > > + clock-output-names:
> > > +maxItems: 8
> > > +
> > > +required:
> > > + - compatible
> > > + - '#clock-cells'
> > > + - ralink,sysctl
> > > + - ralink,memctl
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > + - |
> > > +#include
> > > +
> > > +pll {
> > > + compatible = "mediatek,mt7621-clk";
> > > + #clock-cells = <1>;
> > > + ralink,sysctl = <&sysc>;
> > > + ralink,memctl = <&memc>;
> > > + clock-output-names = "xtal", "cpu", "bus",
> > > + "50m", "125m", "150m",
> > > + "250m", "270m";
> > > +};
> > > --
> > > 2.25.1
> > >
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[PATCH] media:atomisp: remove duplicate include in sh_css
From: Zhang Yunkai 'ia_css_isys.h' included in 'sh_css.c' is duplicated. It is also included in the 30th line. Signed-off-by: Zhang Yunkai --- drivers/staging/media/atomisp/pci/sh_css.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/staging/media/atomisp/pci/sh_css.c b/drivers/staging/media/atomisp/pci/sh_css.c index ddee04c8248d..afddc54094e9 100644 --- a/drivers/staging/media/atomisp/pci/sh_css.c +++ b/drivers/staging/media/atomisp/pci/sh_css.c @@ -49,9 +49,6 @@ #include "ia_css_pipe_util.h" #include "ia_css_pipe_binarydesc.h" #include "ia_css_pipe_stagedesc.h" -#ifndef ISP2401 -#include "ia_css_isys.h" -#endif #include "tag.h" #include "assert_support.h" -- 2.25.1 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH] staging: vc04_services: vchiq_arm: fix error return code of vchiq_release_internal() and vchiq_use_internal()
When arm_state is NULL, no error return code of vchiq_release_internal()
and vchiq_use_internal() is assigned.
To fix this bug, ret is assigned with VCHIQ_ERROR.
Reported-by: TOTE Robot
Signed-off-by: Jia-Ju Bai
---
.../staging/vc04_services/interface/vchiq_arm/vchiq_arm.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
index 59e45dc03a97..8b2b4771f420 100644
--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c
@@ -2332,8 +2332,10 @@ vchiq_use_internal(struct vchiq_state *state, struct
vchiq_service *service,
int *entity_uc;
int local_uc;
- if (!arm_state)
+ if (!arm_state) {
+ ret = VCHIQ_ERROR;
goto out;
+ }
vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
@@ -2389,8 +2391,10 @@ vchiq_release_internal(struct vchiq_state *state, struct
vchiq_service *service)
char entity[16];
int *entity_uc;
- if (!arm_state)
+ if (!arm_state) {
+ ret = VCHIQ_ERROR;
goto out;
+ }
vchiq_log_trace(vchiq_susp_log_level, "%s", __func__);
--
2.17.1
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[PATCH] staging: ralink-gdma: Check return code of device_reset
The device_reset() function is marked as "__must_check", thus the static analysis tool "sparse" complains that in ralink-gdma its return value is ignored. Log a warning in case it returns an error. Signed-off-by: Giovanni Gherdovich --- drivers/staging/ralink-gdma/ralink-gdma.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/staging/ralink-gdma/ralink-gdma.c b/drivers/staging/ralink-gdma/ralink-gdma.c index 655df317d0ee..3c26b665ee7c 100644 --- a/drivers/staging/ralink-gdma/ralink-gdma.c +++ b/drivers/staging/ralink-gdma/ralink-gdma.c @@ -833,7 +833,9 @@ static int gdma_dma_probe(struct platform_device *pdev) return ret; } - device_reset(&pdev->dev); + ret = device_reset(&pdev->dev); + if (ret) + dev_err(&pdev->dev, "failed to reset: %d\n", ret); dd = &dma_dev->ddev; dma_cap_set(DMA_MEMCPY, dd->cap_mask); -- 2.26.2 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH] staging: wimax: fix style check warnings
On Fri, Mar 05, 2021 at 08:55:09PM +0100, gabriele.mod...@gmail.com wrote:
> From: Gabriele Modena
>
> Fix style warnings reported by checkpatch.pl on op-rfkill.c
> by moving */ on a separate line in a block comment,
> adding a missing blank line after declarations,
> and reformatting a quoted string split across lines.
>
> Signed-off-by: Gabriele Modena
> ---
> drivers/staging/wimax/op-rfkill.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/staging/wimax/op-rfkill.c
> b/drivers/staging/wimax/op-rfkill.c
> index 78b294481a59..52612ed09183 100644
> --- a/drivers/staging/wimax/op-rfkill.c
> +++ b/drivers/staging/wimax/op-rfkill.c
> @@ -294,7 +294,8 @@ int wimax_rfkill(struct wimax_dev *wimax_dev, enum
> wimax_rf_state state)
> /* While initializing, < 1.4.3 wimax-tools versions use
>* this call to check if the device is a valid WiMAX
>* device; so we allow it to proceed always,
> - * considering the radios are all off. */
> + * considering the radios are all off.
> + */
> if (result == -ENOMEDIUM && state == WIMAX_RF_QUERY)
> result = WIMAX_RF_OFF << 1 | WIMAX_RF_OFF;
> goto error_not_ready;
> @@ -378,6 +379,7 @@ int wimax_rfkill_add(struct wimax_dev *wimax_dev)
> void wimax_rfkill_rm(struct wimax_dev *wimax_dev)
> {
> struct device *dev = wimax_dev_to_dev(wimax_dev);
> +
> d_fnstart(3, dev, "(wimax_dev %p)\n", wimax_dev);
> rfkill_unregister(wimax_dev->rfkill);
> rfkill_destroy(wimax_dev->rfkill);
> @@ -415,8 +417,7 @@ int wimax_gnl_doit_rfkill(struct sk_buff *skb, struct
> genl_info *info)
> dev = wimax_dev_to_dev(wimax_dev);
> result = -EINVAL;
> if (info->attrs[WIMAX_GNL_RFKILL_STATE] == NULL) {
> - dev_err(dev, "WIMAX_GNL_RFKILL: can't find RFKILL_STATE "
> - "attribute\n");
> + dev_err(dev, "WIMAX_GNL_RFKILL: can't find RFKILL_STATE
> attribute\n");
> goto error_no_pid;
> }
> new_state = nla_get_u32(info->attrs[WIMAX_GNL_RFKILL_STATE]);
> --
> 2.11.0
>
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Hi,
This is the friendly patch-bot of Greg Kroah-Hartman. You have sent him
a patch that has triggered this response. He used to manually respond
to these common problems, but in order to save his sanity (he kept
writing the same thing over and over, yet to different people), I was
created. Hopefully you will not take offence and will fix the problem
in your patch and resubmit it so that it can be accepted into the Linux
kernel tree.
You are receiving this message because of the following common error(s)
as indicated below:
- Your patch did many different things all at once, making it difficult
to review. All Linux kernel patches need to only do one thing at a
time. If you need to do multiple things (such as clean up all coding
style issues in a file/driver), do it in a sequence of patches, each
one doing only one thing. This will make it easier to review the
patches to ensure that they are correct, and to help alleviate any
merge issues that larger patches can cause.
If you wish to discuss this problem further, or you have questions about
how to resolve this issue, please feel free to respond to this email and
Greg will reply once he has dug out from the pending patches received
from other developers.
thanks,
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Re: [PATCH v10 8/9] dt-bindings: add documentation of xilinx clocking wizard
On Wed, Feb 24, 2021 at 06:40:40PM +0530, Shubhrajyoti Datta wrote:
> Add the devicetree binding for the xilinx clocking wizard.
>
> Signed-off-by: Shubhrajyoti Datta
> ---
> v6:
> Fix a yaml warning
> v7:
> Add vendor prefix speed-grade
> v8:
> Fix the warnings
> v10:
> Add nr-outputs
>
> .../bindings/clock/xlnx,clocking-wizard.yaml | 72
> ++
> 1 file changed, 72 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
> b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
> new file mode 100644
> index 000..280eb09
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
> @@ -0,0 +1,72 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#";
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#";
> +
> +title: Xilinx clocking wizard
> +
> +maintainers:
> + - Shubhrajyoti Datta
> +
> +description:
> + The clocking wizard is a soft ip clocking block of Xilinx versal. It
> + reads required input clock frequencies from the devicetree and acts as
> clock
> + clock output.
> +
> +properties:
> + compatible:
> +const: xlnx,clocking-wizard
Not very specific. Only 1 version of this h/w?
> +
> + reg:
> +maxItems: 1
> +
> + "#clock-cells":
> +const: 1
> +
> + clocks:
> +items:
> + - description: clock input
> + - description: axi clock
> +
> + clock-names:
> +items:
> + - const: clk_in1
> + - const: s_axi_aclk
> +
> +
> + xlnx,speed-grade:
> +$ref: /schemas/types.yaml#/definitions/uint32
> +enum: [1, 2, 3]
> +description:
> + Speed grade of the device. Higher the speed grade faster is the FPGA
> device.
How does one decide what value?
> +
> + nr-outputs:
xlnx,nr-outputs
> +$ref: /schemas/types.yaml#/definitions/uint32
> +enum: [1, 2, 3, 4, 5, 6, 7, 8]
minimum: 1
maximum: 8
> +description:
> + Number of outputs.
> +
> +required:
> + - compatible
> + - reg
> + - "#clock-cells"
> + - clocks
> + - clock-names
> + - xlnx,speed-grade
> + - nr-outputs
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +wizard@b000 {
clock-controller@...
> +compatible = "xlnx,clocking-wizard";
> +reg = <0xb000 0x1>;
> +#clock-cells = <1>;
> +xlnx,speed-grade = <1>;
> +nr-outputs = <6>;
> +clock-names = "clk_in1", "s_axi_aclk";
> +clocks = <&clkc 15>, <&clkc 15>;
> +};
> +...
> --
> 2.1.1
>
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Re: [PATCH] Staging: android: ashmem: fixed a struct without const
Hi nabil5352,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on staging/staging-testing]
url:
https://github.com/0day-ci/linux/commits/nabil5352/Staging-android-ashmem-fixed-a-struct-without-const/20210307-103559
base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git
4e1c5d4c35d8d5a5f861019f1392ebaa0abb490b
config: x86_64-randconfig-m001-20210307 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
#
https://github.com/0day-ci/linux/commit/4847faabe2fac6d0cf216c0d7ad02e0a263945b4
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
nabil5352/Staging-android-ashmem-fixed-a-struct-without-const/20210307-103559
git checkout 4847faabe2fac6d0cf216c0d7ad02e0a263945b4
# save the attached .config to linux build tree
make W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
drivers/staging/android/ashmem.c: In function 'ashmem_mmap':
>> drivers/staging/android/ashmem.c:430:16: error: assignment of read-only
>> variable 'vmfile_fops'
430 |vmfile_fops = *vmfile->f_op;
|^
>> drivers/staging/android/ashmem.c:431:21: error: assignment of member 'mmap'
>> in read-only object
431 |vmfile_fops.mmap = ashmem_vmfile_mmap;
| ^
>> drivers/staging/android/ashmem.c:432:34: error: assignment of member
>> 'get_unmapped_area' in read-only object
432 |vmfile_fops.get_unmapped_area =
| ^
vim +/vmfile_fops +430 drivers/staging/android/ashmem.c
6d67b0290b4b84 Suren Baghdasaryan 2020-01-27 376
11980c2ac4ccfa Robert Love2011-12-20 377 static int
ashmem_mmap(struct file *file, struct vm_area_struct *vma)
11980c2ac4ccfa Robert Love2011-12-20 378 {
4847faabe2fac6 nabil5352 2021-03-06 379 static const struct
file_operations vmfile_fops;
11980c2ac4ccfa Robert Love2011-12-20 380 struct ashmem_area
*asma = file->private_data;
11980c2ac4ccfa Robert Love2011-12-20 381 int ret = 0;
11980c2ac4ccfa Robert Love2011-12-20 382
11980c2ac4ccfa Robert Love2011-12-20 383
mutex_lock(&ashmem_mutex);
11980c2ac4ccfa Robert Love2011-12-20 384
11980c2ac4ccfa Robert Love2011-12-20 385 /* user needs to
SET_SIZE before mapping */
59848d6aded59a Alistair Strachan 2018-06-19 386 if (!asma->size) {
11980c2ac4ccfa Robert Love2011-12-20 387 ret = -EINVAL;
11980c2ac4ccfa Robert Love2011-12-20 388 goto out;
11980c2ac4ccfa Robert Love2011-12-20 389 }
11980c2ac4ccfa Robert Love2011-12-20 390
8632c614565d0c Alistair Strachan 2018-06-19 391 /* requested mapping
size larger than object size */
8632c614565d0c Alistair Strachan 2018-06-19 392 if (vma->vm_end -
vma->vm_start > PAGE_ALIGN(asma->size)) {
11980c2ac4ccfa Robert Love2011-12-20 393 ret = -EINVAL;
11980c2ac4ccfa Robert Love2011-12-20 394 goto out;
11980c2ac4ccfa Robert Love2011-12-20 395 }
11980c2ac4ccfa Robert Love2011-12-20 396
11980c2ac4ccfa Robert Love2011-12-20 397 /* requested protection
bits must match our allowed protection mask */
59848d6aded59a Alistair Strachan 2018-06-19 398 if ((vma->vm_flags &
~calc_vm_prot_bits(asma->prot_mask, 0)) &
59848d6aded59a Alistair Strachan 2018-06-19 399
calc_vm_prot_bits(PROT_MASK, 0)) {
11980c2ac4ccfa Robert Love2011-12-20 400 ret = -EPERM;
11980c2ac4ccfa Robert Love2011-12-20 401 goto out;
11980c2ac4ccfa Robert Love2011-12-20 402 }
56f76fc68492af Arve Hjønnevåg 2011-12-20 403 vma->vm_flags &=
~calc_vm_may_flags(~asma->prot_mask);
11980c2ac4ccfa Robert Love2011-12-20 404
11980c2ac4ccfa Robert Love2011-12-20 405 if (!asma->file) {
11980c2ac4ccfa Robert Love2011-12-20 406 char *name =
ASHMEM_NAME_DEF;
11980c2ac4ccfa Robert Love2011-12-20 407 struct file
*vmfile;
3e338d3c95c735 Suren Baghdasaryan 2020-07-30 408 struct inode
*inode;
11980c2ac4ccfa Robert Love2011-12-20 409
11980c2ac4ccfa Robert Love2011-12-20 410 if
(asma->name[ASHMEM_NAME_PREFIX_LEN] != '\0')
11980c2ac4ccfa Robert Love2011-12-20 411 name =
asma->name;
11980c2ac4ccfa Robert Love2011-12-20 412
11980c2ac4ccfa Robert Love2011-12-20 413 /* ... and
allocate the backing shmem file */
11980c2ac4ccfa Robert Love2011-12-20 414 vmfile =
shmem_file_setup(name, asma->size, vma->vm_flags);
7f44cb0ba88b40
Re: [PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation
Hi,
On Sat, Mar 6, 2021 at 10:54 AM Sergio Paracuellos
wrote:
>
> Hi again,
>
> On Sat, Mar 6, 2021 at 8:12 AM Sergio Paracuellos
> wrote:
> >
> > Hi Rob,
> >
> > On Fri, Mar 5, 2021 at 11:47 PM Rob Herring wrote:
> > [snip]
> > > > +
> > > > + ralink,sysctl:
> > > > +$ref: /schemas/types.yaml#/definitions/phandle
> > > > +description:
> > > > + phandle of syscon used to control system registers
> > > > +
> > > > + ralink,memctl:
> > > > +$ref: /schemas/types.yaml#/definitions/phandle
> > > > +description:
> > > > + phandle of syscon used to control memory registers
> > >
> > > I assume one of these phandles are the main registers for the clocks?
> > > Make this a child node and drop that phandle.
> >
> > The 'ralink,sysctl' phandle is to read bootstrap register to be able
> > to derive xtal and a clk gate register for the peripherals.
> > The 'ralink,memctl' phandle is to read the cpu clock frequency from
> > the memory controller.
> >
> > So there is not "main registers". I already put this as a child node
> > in v4 and I was told to get rid of child nodes. I need this as a
> > regmap to other DT node registers (sysctl, and memctl) to be able to
> > use the driver without specific architecture operations and properly
> > enable for COMPILE_TEST without dirty Makefile arch flags. Both sysctl
> > and memctl has no other child nodes, and I think that's why I was told
> > to avoid child nodes at the end. I explained here [0] current sysctl
> > and memctl in the mt7621 device tree and my view of the need for this
> > two syscons:
> >
> > [0]: https://lkml.org/lkml/2021/1/2/9
> >
> > So to avoid to send again "a previous version" on this patch, please
> > guide me in the correct thing to do. Stephen, Rob, I will be really
> > happy with your help :)
>
> Since there are no other child nodes for this sysc, should merge clock
> properties
> with this node in the following way a valid approach:
>
> sysc: sysc@0 {
> compatible = "mediatek,mt7621-sysc", "syscon";
> reg = <0x0 0x100>;
> #clock-cells = <1>;
> ralink,memctl = <&memc>;
> clock-output-names = "xtal", "cpu", "bus",
> "50m", "125m", "150m",
> "250m", "270m";
> };
>
> Consumer clock:
>
> node: node@0 {
> ...
> clocks = <&sysc MT7621_CLK_WHATEVER>;
> ...
> };
I have been reviewing bindings review comments along the time and I
was already suggested to do this I am saying here (see [0]) but my
mind seems that filtered it for any reason I don't really understand.
Maybe I should sleep a bit more :).
I will send v10 with these changes that hopefully will be the correct ones.
Thanks and sorry for bothering you with already suggested things.
Best regards,
Sergio Paracuellos
[0]: https://lkml.org/lkml/2020/12/31/206
>
> If that is the case... and since 'sysc' is used as system control
> registers for all the rest of the world, where should be the yaml file
> with bindings placed?
>
> Thanks in advance again for your help.
>
> Best regards,
> Sergio Paracuellos
>
> >
> > Best regards,
> > Sergio Paracuellos
> > >
> > > > +
> > > > + clock-output-names:
> > > > +maxItems: 8
> > > > +
> > > > +required:
> > > > + - compatible
> > > > + - '#clock-cells'
> > > > + - ralink,sysctl
> > > > + - ralink,memctl
> > > > +
> > > > +additionalProperties: false
> > > > +
> > > > +examples:
> > > > + - |
> > > > +#include
> > > > +
> > > > +pll {
> > > > + compatible = "mediatek,mt7621-clk";
> > > > + #clock-cells = <1>;
> > > > + ralink,sysctl = <&sysc>;
> > > > + ralink,memctl = <&memc>;
> > > > + clock-output-names = "xtal", "cpu", "bus",
> > > > + "50m", "125m", "150m",
> > > > + "250m", "270m";
> > > > +};
> > > > --
> > > > 2.25.1
> > > >
___
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[PATCH v10 2/6] dt: bindings: add mt7621-sysc device tree binding documentation
Adds device tree binding documentation for clocks in the
MT7621 SOC.
Signed-off-by: Sergio Paracuellos
---
.../bindings/clock/mediatek,mt7621-sysc.yaml | 68 +++
1 file changed, 68 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
new file mode 100644
index ..ef2d71b23ba0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MT7621 Clock Device Tree Bindings
+
+maintainers:
+ - Sergio Paracuellos
+
+description: |
+ The MT7621 has a PLL controller from where the cpu clock is provided
+ as well as derived clocks for the bus and the peripherals. It also
+ can gate SoC device clocks.
+
+ Each clock is assigned an identifier and client nodes use this identifier
+ to specify the clock which they consume.
+
+ All these identifiers could be found in:
+ [1]: .
+
+ The clocks are provided inside a system controller node.
+
+properties:
+ compatible:
+items:
+ - const: mediatek,mt7621-sysc
+ - const: syscon
+
+ reg:
+maxItems: 1
+
+ "#clock-cells":
+description:
+ The first cell indicates the clock number, see [1] for available
+ clocks.
+const: 1
+
+ ralink,memctl:
+$ref: /schemas/types.yaml#/definitions/phandle
+description:
+ phandle of syscon used to control memory registers
+
+ clock-output-names:
+maxItems: 8
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - ralink,memctl
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+sysc: sysc@0 {
+ compatible = "mediatek,mt7621-sysc", "syscon";
+ reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ ralink,memctl = <&memc>;
+ clock-output-names = "xtal", "cpu", "bus",
+ "50m", "125m", "150m",
+ "250m", "270m";
+};
--
2.25.1
___
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[PATCH v10 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621
This patchset ports CPU clock detection for MT7621 from OpenWrt and adds a complete clock plan for the mt7621 SOC. The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers used for CPU and some sort of BUS (AHB?). * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for all or some ip cores. Registers needed for this driver to work are in two already mapped areas in its platform's device tree. These are 'sysc' and 'memc' nodes. Most of other drivers just make use of platform operations defined in 'asm/mach-ralink/ralink_regs.h' but this can be avoided declaring this two nodes to be accesible through syscon. Main registers for the clocks are in the sysc control node so this node is merged with clock properties and will also be the clock provider for the SoC. No documentation about a probably existent set of dividers for each ip core is included in the datasheets. So we cannot make anything better, AFAICT. Looking into driver code, and some openWRT patched there are another frequences which are used in some drivers (uart, sd...). According to all of this information the clock plan for this SoC is set as follows: - Main top clock "xtal" from where all the rest of the world is derived. - CPU clock "cpu" derived from "xtal" frequencies and a bunch of register reads and predividers. - BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz. - Fixed clocks from "xtal": * "50m": 50 MHz. * "125m": 125 MHz. * "150m": 150 MHz. * "250m": 250 MHz. * "270m": 270 MHz. We also have a buch of gate clocks with their parents: - "hsdma": "150m" - "fe": "250m" - "sp_divtx": "270m" - "timer": "50m" - "pcm": "270m" - "pio": "50m" - "gdma": "bus" - "nand": "125m" - "i2c": "50m" - "i2s": "270m" - "spi": "bus" - "uart1": "50m" - "uart2": "50m" - "uart3": "50m" - "eth": "50m" - "pcie0": "125m" - "pcie1": "125m" - "pcie2": "125m" - "crypto": "250m" - "shxc": "50m" There was a previous attempt of doing this here[0] but the author (Chuanhong Guo) did not wanted to make assumptions of a clock plan for the platform that time. It seems that now he has a better idea of how the clocks are dispossed for this SoC so he share code[1] where some frequencies and clock parents for the gates are coded from a real mediatek private clock plan. I do really want this to be upstreamed so according to the comments in previous attempt[0] from Oleksij Rempel and the frequencies in code[1] I have tried to do this by myself. All of this patches have been tested in a GNUBee PC1 resulting in a working platform. Changes in v10: - Merge clock properties into 'sysc' system control node making this node a clock provider. - Update driver to use 'mediatek,mt7621-sysc' as compatible string. - Update documentation bindings and its related filename to 'mediatek,mt7621-sysc.yaml'. - Make use of 'linux/bitfields.h' header to avoid some preprocesor shift definitions and just use bit masks decreasing a bit LOC. Changes in v9: - Set two missing ret values to its related PTR_ERR in function 'mt7621_clk_probe' (also related with [3]). - Select MFC_SYSCON in Kconfig. Changes in v8: - Fix kernel test robot complain about the use of 'ret' variable initialized: see [3] Changes in v7: - Make use of CLK_OF_DECLARE_DRIVER instead of CLK_OF_DECLARE and register there only the top clocks that are needed in 'of_clk_init'. The rest of the clocks (fixed and gates) are now registered using a platform driver. Because we have avoid architecture dependent stuff now this has sense because we can enable this driver for COMPILE_TEST. - Convert fixed clocks and gates related function to receive a 'struct device' pointer instead of 'struct device_node' one. - Make use of dev_ APIS in stuff related with platform driver instead of use device_node related stuff. - Add new static global 'mt7621_clk_early' to store pointers to clk_hw registered at 'of_clk_init' stage. Make use of this in platform device probe function to properly copy this into the new required 'clk_data' to provide a properly hierarchy clock structure. - Rename 'mt7621_register_top_clocks' function into a more accurate name now which is 'mt7621_register_early_clocks'. - Enable driver for COMPILE_TEST. Changes in v6: - Rewrite bindings to properly access the registers needed for the driver making use of syscon for two different areas: 'sysc' and 'memc'. With this changes architecture dependent include 'asm/mach-ralink/ralink_regs.h' is not needed anymore because we access this two syscons using a phandle through kernel's regmap APIs. Explanation of this two areas is in [2]. - Add new 'mt7621_clk_priv' struct to store there pointers to regmap handlers to be able to use regmap operations
[PATCH v10 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks
Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h diff --git a/include/dt-bindings/clock/mt7621-clk.h b/include/dt-bindings/clock/mt7621-clk.h new file mode 100644 index ..1422badcf9de --- /dev/null +++ b/include/dt-bindings/clock/mt7621-clk.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Author: Sergio Paracuellos + */ + +#ifndef _DT_BINDINGS_CLK_MT7621_H +#define _DT_BINDINGS_CLK_MT7621_H + +#define MT7621_CLK_XTAL0 +#define MT7621_CLK_CPU 1 +#define MT7621_CLK_BUS 2 +#define MT7621_CLK_50M 3 +#define MT7621_CLK_125M4 +#define MT7621_CLK_150M5 +#define MT7621_CLK_250M6 +#define MT7621_CLK_270M7 + +#define MT7621_CLK_HSDMA 8 +#define MT7621_CLK_FE 9 +#define MT7621_CLK_SP_DIVTX10 +#define MT7621_CLK_TIMER 11 +#define MT7621_CLK_PCM 12 +#define MT7621_CLK_PIO 13 +#define MT7621_CLK_GDMA14 +#define MT7621_CLK_NAND15 +#define MT7621_CLK_I2C 16 +#define MT7621_CLK_I2S 17 +#define MT7621_CLK_SPI 18 +#define MT7621_CLK_UART1 19 +#define MT7621_CLK_UART2 20 +#define MT7621_CLK_UART3 21 +#define MT7621_CLK_ETH 22 +#define MT7621_CLK_PCIE0 23 +#define MT7621_CLK_PCIE1 24 +#define MT7621_CLK_PCIE2 25 +#define MT7621_CLK_CRYPTO 26 +#define MT7621_CLK_SHXC27 + +#define MT7621_CLK_MAX 28 + +#endif /* _DT_BINDINGS_CLK_MT7621_H */ -- 2.25.1 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v10 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'
Clocks for SoC mt7621 have been properly integrated so there is
no need to declare fixed clocks at all in the device tree. Remove
all of them, add new device tree nodes for mt7621-clk and update
the rest of the nodes to use them.
Acked-by: Greg Kroah-Hartman
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-dts/gbpc1.dts | 11
drivers/staging/mt7621-dts/mt7621.dtsi | 74 --
2 files changed, 33 insertions(+), 52 deletions(-)
diff --git a/drivers/staging/mt7621-dts/gbpc1.dts
b/drivers/staging/mt7621-dts/gbpc1.dts
index a7c0d3115d72..7716d0efe524 100644
--- a/drivers/staging/mt7621-dts/gbpc1.dts
+++ b/drivers/staging/mt7621-dts/gbpc1.dts
@@ -100,17 +100,6 @@ partition@5 {
};
};
-&sysclock {
- compatible = "fixed-clock";
- /* This is normally 1/4 of cpuclock */
- clock-frequency = <22500>;
-};
-
-&cpuclock {
- compatible = "fixed-clock";
- clock-frequency = <9>;
-};
-
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 16fc94f65486..b68183e7e6ad 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -1,5 +1,6 @@
#include
#include
+#include
/ {
#address-cells = <1>;
@@ -27,27 +28,6 @@ aliases {
serial0 = &uartlite;
};
- cpuclock: cpuclock@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
-
- /* FIXME: there should be way to detect this */
- clock-frequency = <88000>;
- };
-
- sysclock: sysclock@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
-
- /* This is normally 1/4 of cpuclock */
- clock-frequency = <22000>;
- };
-
- mmc_clock: mmc_clock@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <4800>;
- };
mmc_fixed_3v3: fixedregulator@0 {
compatible = "regulator-fixed";
@@ -76,8 +56,13 @@ palmbus: palmbus@1E00 {
#size-cells = <1>;
sysc: sysc@0 {
- compatible = "mtk,mt7621-sysc";
+ compatible = "mtk,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ ralink,memctl = <&memc>;
+ clock-output-names = "xtal", "cpu", "bus",
+"50m", "125m", "150m",
+"250m", "270m";
};
wdt: wdt@100 {
@@ -101,8 +86,8 @@ i2c: i2c@900 {
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
- clocks = <&sysclock>;
-
+ clocks = <&sysc MT7621_CLK_I2C>;
+ clock-names = "i2c";
resets = <&rstctrl 16>;
reset-names = "i2c";
@@ -119,8 +104,8 @@ i2s: i2s@a00 {
compatible = "mediatek,mt7621-i2s";
reg = <0xa00 0x100>;
- clocks = <&sysclock>;
-
+ clocks = <&sysc MT7621_CLK_I2S>;
+ clock-names = "i2s";
resets = <&rstctrl 17>;
reset-names = "i2s";
@@ -138,7 +123,7 @@ i2s: i2s@a00 {
};
memc: memc@5000 {
- compatible = "mtk,mt7621-memc";
+ compatible = "mtk,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
@@ -156,8 +141,8 @@ uartlite: uartlite@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
- clocks = <&sysclock>;
- clock-frequency = <5000>;
+ clocks = <&sysc MT7621_CLK_UART1>;
+ clock-names = "uart1";
interrupt-parent = <&gic>;
interrupts = ;
@@ -173,7 +158,8 @@ spi0: spi@b00 {
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
- clocks = <&sysclock>;
+ clocks = <&sysc MT7621_CLK_SPI>;
+ clock-names = "spi";
resets = <&rstctrl 18>;
reset-names = "spi";
@@ -189,6 +175,8 @@ gdma: gdma@2800 {
compatible = "ralink,rt3883-gdma";
reg = <0x2800 0x800>;
+ clocks = <&sysc MT7621_CLK_GDMA>;
+ clock-names = "gdma
[PATCH v10 3/6] clk: ralink: add clock driver for mt7621 SoC
The documentation for this SOC only talks about two
registers regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about
boostrapped refclock. PLL and dividers used for CPU and some
sort of BUS.
* SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable
clocks for all or some ip cores.
Looking into driver code, and some openWRT patched there are
another frequencies which are used in some drivers (uart, sd...).
According to all of this information the clock plan for this
SoC is set as follows:
- Main top clock "xtal" from where all the rest of the world is
derived.
- CPU clock "cpu" derived from "xtal" frequencies and a bunch of
register reads and predividers.
- BUS clock "bus" derived from "cpu" and with (cpu / 4) MHz.
- Fixed clocks from "xtal":
* "50m": 50 MHz.
* "125m": 125 MHz.
* "150m": 150 MHz.
* "250m": 250 MHz.
* "270m": 270 MHz.
We also have a buch of gate clocks with their parents:
* "hsdma": "150m"
* "fe": "250m"
* "sp_divtx": "270m"
* "timer": "50m"
* "pcm": "270m"
* "pio": "50m"
* "gdma": "bus"
* "nand": "125m"
* "i2c": "50m"
* "i2s": "270m"
* "spi": "bus"
* "uart1": "50m"
* "uart2": "50m"
* "uart3": "50m"
* "eth": "50m"
* "pcie0": "125m"
* "pcie1": "125m"
* "pcie2": "125m"
* "crypto": "250m"
* "shxc": "50m"
With this information the clk driver will provide clock and gates
functionality from a a set of hardcoded clocks allowing to define
a nice device tree without fixed clocks.
Signed-off-by: Sergio Paracuellos
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile| 1 +
drivers/clk/ralink/Kconfig | 15 +
drivers/clk/ralink/Makefile | 2 +
drivers/clk/ralink/clk-mt7621.c | 528
5 files changed, 547 insertions(+)
create mode 100644 drivers/clk/ralink/Kconfig
create mode 100644 drivers/clk/ralink/Makefile
create mode 100644 drivers/clk/ralink/clk-mt7621.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 7c5dc348c16f..70b23da997bf 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -382,6 +382,7 @@ source "drivers/clk/mediatek/Kconfig"
source "drivers/clk/meson/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/qcom/Kconfig"
+source "drivers/clk/ralink/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/rockchip/Kconfig"
source "drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5325847469e9..1b35ad852721 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/
obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
obj-$(CONFIG_COMMON_CLK_PXA) += pxa/
obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
+obj-y += ralink/
obj-y += renesas/
obj-$(CONFIG_ARCH_ROCKCHIP)+= rockchip/
obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig
new file mode 100644
index ..3e3f5cb9ad88
--- /dev/null
+++ b/drivers/clk/ralink/Kconfig
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# MediaTek Mt7621 Clock Driver
+#
+menu "Clock driver for Mediatek mt7621 SoC"
+ depends on SOC_MT7621 || COMPILE_TEST
+
+config CLK_MT7621
+ bool "Clock driver for MediaTek MT7621"
+ depends on SOC_MT7621 || COMPILE_TEST
+ default SOC_MT7621
+ select MFD_SYSCON
+ help
+ This driver supports MediaTek MT7621 basic clocks.
+endmenu
diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
new file mode 100644
index ..cf6f9216379d
--- /dev/null
+++ b/drivers/clk/ralink/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c
new file mode 100644
index ..6aea5accd51c
--- /dev/null
+++ b/drivers/clk/ralink/clk-mt7621.c
@@ -0,0 +1,528 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Mediatek MT7621 Clock Driver
+ * Author: Sergio Paracuellos
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Configuration registers */
+#define SYSC_REG_SYSTEM_CONFIG0 0x10
+#define SYSC_REG_SYSTEM_CONFIG1 0x14
+#define SYSC_REG_CLKCFG0 0x2c
+#define SYSC_REG_CLKCFG1 0x30
+#define SYSC_REG_CUR_CLK_STS 0x44
+#define MEMC_REG_CPU_PLL 0x648
+
+#define XTAL_MODE_SEL_MASK GENMASK(8, 6)
+#define CPU_CLK_SEL_MASK GENMASK(31, 30)
+#define CUR_CPU_FDIV_MASK GENMASK(12, 8)
+#define CUR_CPU_FFRAC_MASK GENMASK(4, 0)
+#define CPU_PLL_PREDIV_MASKGENMASK(13, 12)
+#define CPU_PLL_FBDIV_MASK GENMASK(10, 4)
+
+struct mt7621_clk_priv {
+ struct regmap *sysc;
+ struc
[PATCH v10 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'
Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml'
contains 'mediatek' as a valid vendor string. Some nodes in the device
tree are using an invalid vendor string vfor 'mtk' instead. Fix all of
them in dts file. Update also ralink mt7621 related code to properly
match new strings. Even there are used in the device tree there are
some strings that are not referred anywhere but have been also updated
with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand',
'mtk,mt7621-mc', and 'mtk,mt7621-cpc'.
Acked-by: Greg Kroah-Hartman
Signed-off-by: Sergio Paracuellos
---
arch/mips/ralink/mt7621.c | 6 +++---
drivers/staging/mt7621-dts/mt7621.dtsi | 12 ++--
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
index ca0ac607b0f3..5d74fc1c96ac 100644
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -112,8 +112,8 @@ phys_addr_t mips_cpc_default_phys_base(void)
void __init ralink_of_remap(void)
{
- rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
- rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
+ rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
+ rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
if (!rt_sysc_membase || !rt_memc_membase)
panic("Failed to remap core resources");
@@ -181,7 +181,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
name = "MT7621";
- soc_info->compatible = "mtk,mt7621-soc";
+ soc_info->compatible = "mediatek,mt7621-soc";
} else {
panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
}
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi
b/drivers/staging/mt7621-dts/mt7621.dtsi
index b68183e7e6ad..f0c9ae757bcd 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -56,7 +56,7 @@ palmbus: palmbus@1E00 {
#size-cells = <1>;
sysc: sysc@0 {
- compatible = "mtk,mt7621-sysc", "syscon";
+ compatible = "mediatek,mt7621-sysc", "syscon";
reg = <0x0 0x100>;
#clock-cells = <1>;
ralink,memctl = <&memc>;
@@ -66,7 +66,7 @@ sysc: sysc@0 {
};
wdt: wdt@100 {
- compatible = "mtk,mt7621-wdt";
+ compatible = "mediatek,mt7621-wdt";
reg = <0x100 0x100>;
};
@@ -123,17 +123,17 @@ i2s: i2s@a00 {
};
memc: memc@5000 {
- compatible = "mtk,mt7621-memc", "syscon";
+ compatible = "mediatek,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
cpc: cpc@1fbf {
-compatible = "mtk,mt7621-cpc";
+compatible = "mediatek,mt7621-cpc";
reg = <0x1fbf 0x8000>;
};
mc: mc@1fbf8000 {
- compatible = "mtk,mt7621-mc";
+ compatible = "mediatek,mt7621-mc";
reg = <0x1fbf8000 0x8000>;
};
@@ -361,7 +361,7 @@ timer {
nand: nand@1e003000 {
status = "disabled";
- compatible = "mtk,mt7621-nand";
+ compatible = "mediatek,mt7621-nand";
bank-width = <2>;
reg = <0x1e003000 0x800
0x1e003800 0x800>;
--
2.25.1
___
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[PATCH v10 6/6] MAINTAINERS: add MT7621 CLOCK maintainer
Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..be5ada6b4309 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L: linux-wirel...@vger.kernel.org S: Maintained F: drivers/net/wireless/mediatek/mt7601u/ +MEDIATEK MT7621 CLOCK DRIVER +M: Sergio Paracuellos +S: Maintained +F: Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml +F: drivers/clk/ralink/clk-mt7621.c + MEDIATEK MT7621/28/88 I2C DRIVER M: Stefan Roese L: linux-...@vger.kernel.org -- 2.25.1 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
