Re: [PATCH] staging: comedi: drivers: adl_pci9118: Fixes format of line 1283.
On Fri, Aug 24, 2018 at 11:06:56PM +0200, Sven Luthi wrote:
> Checkpatch repored "Lines should not end with a '('" for line 1283.
>
> Moved opening parenthesis of function on line 1283 onto next line.
>
> Signed-off-by: Sven Luthi
> ---
> drivers/staging/comedi/drivers/adl_pci9118.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/staging/comedi/drivers/adl_pci9118.c
> b/drivers/staging/comedi/drivers/adl_pci9118.c
> index 2528ca0ede6d..07431dc9cde9 100644
> --- a/drivers/staging/comedi/drivers/adl_pci9118.c
> +++ b/drivers/staging/comedi/drivers/adl_pci9118.c
> @@ -1280,8 +1280,8 @@ static int pci9118_ai_cmdtest(struct comedi_device *dev,
> } else {
> arg = cmd->convert_arg * cmd->chanlist_len;
> }
> - err |= comedi_check_trigger_arg_min(
> - &cmd->scan_begin_arg, arg);
> + err |= comedi_check_trigger_arg_min
> +(&cmd->scan_begin_arg, arg);
The original is fine. It's probably better than the new version.
Checkpatch.pl is just a hint, not a command.
regards,
dan carpenter
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Re: [PATCH] staging: comedi: cb_pcidas64 fixed '(' coding style issue
On Sat, Aug 25, 2018 at 02:07:01AM +0300, GuyLuz wrote:
> From: Guy Luz
>
> Fixed a Lines should not end with a '(' issue.
>
> Signed-off-by: Guy Luz
> ---
> drivers/staging/comedi/drivers/cb_pcidas64.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c
> b/drivers/staging/comedi/drivers/cb_pcidas64.c
> index 63992c0babf7..a85334f53ff9 100644
> --- a/drivers/staging/comedi/drivers/cb_pcidas64.c
> +++ b/drivers/staging/comedi/drivers/cb_pcidas64.c
> @@ -2173,10 +2173,9 @@ static int ai_cmdtest(struct comedi_device *dev,
> struct comedi_subdevice *s,
>* allows
>*/
> if (cmd->scan_begin_src == TRIG_TIMER) {
> - err |= comedi_check_trigger_arg_min(
> - &cmd->scan_begin_arg,
> - cmd->convert_arg *
> - cmd->chanlist_len);
> + err |= comedi_check_trigger_arg_min
> + (&cmd->scan_begin_arg, cmd->convert_arg *
> + cmd->chanlist_len);
The original is better than the new version. Please leave it as is.
regards,
dan carpenter
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TRADING ACCOUNT
Dear sir , I KELLY ALAN purchasing and sales manager of CFM INTERNATIONAL .Our Company specialised in Supplying computer hardware and Electronic .We want to extend our supplier list because of concurrency in prices on the international market. We are seeking a supplier with whom we can to have partnered long-term in order to have competitive prices . we are interested to buy the products you sell and want to place an order with you in big quantities. Can you give us payment facilities ( 14 , 30 or 60 days payment terms ) ? What is the procedure for our account opening and credit line application ? Cordially KELLY ALAN CFM INTERNATIONAL 2 BOULEVARD DU GAL MARTIAL VALIN 75015 PARIS REG N° 302 527 700 VAT N° FR90 302527700 TEL +33171025367 FAX +33177759149 https://www.cfmaeroengines.com ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
TRADING ACCOUNT
Dear sir , I KELLY ALAN purchasing and sales manager of CFM INTERNATIONAL .Our Company specialised in Supplying computer hardware and Electronic .We want to extend our supplier list because of concurrency in prices on the international market. We are seeking a supplier with whom we can to have partnered long-term in order to have competitive prices . we are interested to buy the products you sell and want to place an order with you in big quantities. Can you give us payment facilities ( 14 , 30 or 60 days payment terms ) ? What is the procedure for our account opening and credit line application ? Cordially KELLY ALAN CFM INTERNATIONAL 2 BOULEVARD DU GAL MARTIAL VALIN 75015 PARIS REG N° 302 527 700 VAT N° FR90 302527700 TEL +33171025367 FAX +33177759149 https://www.cfmaeroengines.com ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v3 02/20] staging: mt7621-pci: replace return value if devm_pci_alloc_host_bridge call fails
Driver probe function calls 'devm_pci_alloc_host_bridge'. If this call fails it is returning -ENODEV. Return -ENOMEM instead which is more accurate for this. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index f1161b3..7e6f053 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -523,7 +523,7 @@ static int mt7621_pci_probe(struct platform_device *pdev) bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); if (!bridge) - return -ENODEV; + return -ENOMEM; pcie = pci_host_bridge_priv(bridge); pcie->dev = dev; -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v3 05/20] staging: mt7621-pci: remove [ASSERT|DEASSERT]_SYSRST_PCIE macros
Driver is using reset_control kernel API's to manage this so this
two macros are not needed anymore. Remove them.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 15 ---
1 file changed, 15 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index da6a137..a6df661 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -94,21 +94,6 @@
#define RALINK_PCI_MM_MAP_BASE 0x6000
#define RALINK_PCI_IO_MAP_BASE 0x1e16
-#define ASSERT_SYSRST_PCIE(val)\
- do {\
- if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101) \
- rt_sysc_m32(0, val, RALINK_RSTCTRL);\
- else\
- rt_sysc_m32(val, 0, RALINK_RSTCTRL);\
- } while (0)
-#define DEASSERT_SYSRST_PCIE(val) \
- do {\
- if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101) \
- rt_sysc_m32(val, 0, RALINK_RSTCTRL);\
- else\
- rt_sysc_m32(0, val, RALINK_RSTCTRL);\
- } while (0)
-
#define RALINK_CLKCFG1 0x30
#define RALINK_RSTCTRL 0x34
#define RALINK_GPIOMODE0x60
--
2.7.4
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[PATCH v3 03/20] staging: mt7621-pci: add two helpers for read and write pcie register ports
mt7621-pcie_port data structure has filed 'base' as the base address for
read and write related port registers. Create two inline functions
'pcie_port_read' and 'pcie_port_write' to make this task easier and
code more readable.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 7e6f053..06395d1 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -175,6 +175,17 @@ static inline void pcie_write(struct mt7621_pcie *pcie,
u32 val, u32 reg)
writel(val, pcie->base + reg);
}
+static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
+{
+ return readl(port->base + reg);
+}
+
+static inline void pcie_port_write(struct mt7621_pcie_port *port,
+ u32 val, u32 reg)
+{
+ writel(val, port->base + reg);
+}
+
static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
unsigned int func, unsigned int where)
{
--
2.7.4
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[PATCH v3 00/20] staging: mt7621-pci: Parse ports info from DT and other minor cleanups
This patch series parse remaining port info from device tree storing it in mt7621_pcie_port struct created for this. Also minor cleanups are performed here: - Remove not used macros. - Use kernel reset_control functions. - Remove unused code. Changes in v3: - 'mt7621_pcie_enable_port' now returns an error instead of void to avoid a layering violation. - Delete 'mt7621_pcie_port_free' function and just delete port from the list in probe function. - Use parent node to get base address registers for each port. Changes in v2: - Rewrite phy part of the driver - fix some checkpatch complains - make use of sysctl from DT Hope this helps. Best regards, Sergio Paracuellos Sergio Paracuellos (20): staging: mt7621-pci: parse and init port data from device tree staging: mt7621-pci: replace return value if devm_pci_alloc_host_bridge call fails staging: mt7621-pci: add two helpers for read and write pcie register ports staging: mt7621-pci: factor out 'mt7621_pcie_enable_port' function staging: mt7621-pci: remove [ASSERT|DEASSERT]_SYSRST_PCIE macros staging: mt7621-pci: remove GPL2+ text from license header staging: mt7621-pci: remove two commented code lines staging: mt7621-pci: remove reset related unused macros staging: mt7621-pci: reagroup reset related macros all together staging: mt7621-pci: make some function static staging: mt7621-pci: show N_FTS status using a loop staging: mt7621-pci: rewrite pcie phy related functions staging: mt7621-pci: factor out 'mt7621_enable_phy' function staging: mt7621-pci: debug port N_FTS inside 'mt7621_pcie_enable_port' staging: mt7621-pci: rename 'mt7621_pcie_enable_port' into 'mt7621_pcie_init_port' staging: mt7621-dts: add sysctl registers base address to pcie staging: mt7621-pci: remap and use sysctl from device tree staging: mt7621-pci: use a trailing */ on a separate line staging: mt7621-pci: use dev_* functions instead of printk staging: mt7621-pci: do not initialise statics to 0 drivers/staging/mt7621-dts/mt7621.dtsi | 4 +- drivers/staging/mt7621-pci/pci-mt7621.c | 597 2 files changed, 379 insertions(+), 222 deletions(-) -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v3 06/20] staging: mt7621-pci: remove GPL2+ text from license header
This file has a valid SPDX license line added so reamining GPL2+ boilerplate text is not needed at all. Remove it. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 31 +++ 1 file changed, 3 insertions(+), 28 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index a6df661..eecad11 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -1,33 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ -/** - * - * BRIEF MODULE DESCRIPTION +/* + * BRIEF MODULE DESCRIPTION * PCI init for Ralink RT2880 solution * - * Copyright 2007 Ralink Inc. (bruce_ch...@ralinktech.com.tw) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BELIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * Copyright 2007 Ralink Inc. (bruce_ch...@ralinktech.com.tw) * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * - ** * May 2007 Bruce Chang * Initial Release * @@ -36,8 +13,6 @@ * * May 2011 Bruce Chang * support RT6855/MT7620 PCIe - * - ** */ #include -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v3 08/20] staging: mt7621-pci: remove reset related unused macros
There are three macros which are not being used at all. Remove them. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 61da75d..11c2287 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -76,10 +76,6 @@ #define RALINK_PCIE_CLK_GEN1 0x80 //RALINK_RSTCTRL bit #define RALINK_PCIE_RSTBIT(23) -#define RALINK_PCI_RST BIT(24) -//RALINK_CLKCFG1 bit -#define RALINK_PCI_CLK_EN BIT(19) -#define RALINK_PCIE_CLK_EN BIT(21) #define MEMORY_BASE 0x0 static int pcie_link_status = 0; -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v3 01/20] staging: mt7621-pci: parse and init port data from device tree
Add initialization of each PCIe port reading and initializing
data using device tree.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 75 +++--
1 file changed, 71 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index a49e279..f1161b3 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -126,16 +126,20 @@ static int pcie_link_status = 0;
/**
* struct mt7621_pcie_port - PCIe port information
- * @base: IO mapped register base
+ * @base: I/O mapped register base
* @list: port list
* @pcie: pointer to PCIe host info
- * @reset: pointer to port reset control
+ * @pcie_rst: pointer to port reset control
+ * @pcie_clk: PCIe clock
+ * @slot: port slot
*/
struct mt7621_pcie_port {
void __iomem *base;
struct list_head list;
struct mt7621_pcie *pcie;
- struct reset_control *reset;
+ struct reset_control *pcie_rst;
+ struct clk *pcie_clk;
+ u32 slot;
};
/**
@@ -382,10 +386,57 @@ static int mt7621_pci_parse_request_of_pci_ranges(struct
mt7621_pcie *pcie)
return 0;
}
+static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
+ struct device_node *node,
+ int slot)
+{
+ struct mt7621_pcie_port *port;
+ struct device *dev = pcie->dev;
+ struct device_node *pnode = dev->of_node;
+ struct resource regs;
+ char name[6];
+ int err;
+
+ port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
+ if (!port)
+ return -ENOMEM;
+
+ err = of_address_to_resource(pnode, slot + 1, ®s);
+ if (err) {
+ dev_err(dev, "missing \"reg\" property\n");
+ return err;
+ }
+
+ port->base = devm_ioremap_resource(dev, ®s);
+ if (IS_ERR(port->base))
+ return PTR_ERR(port->base);
+
+ snprintf(name, sizeof(name), "pcie%d", slot);
+ port->pcie_clk = devm_clk_get(dev, name);
+ if (IS_ERR(port->pcie_clk)) {
+ dev_err(dev, "failed to get pcie%d clock\n", slot);
+ return PTR_ERR(port->pcie_clk);
+ }
+
+ port->pcie_rst = devm_reset_control_get_exclusive(dev, name);
+ if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
+ dev_err(dev, "failed to get pcie%d reset control\n", slot);
+ return PTR_ERR(port->pcie_rst);
+ }
+
+ port->slot = slot;
+ port->pcie = pcie;
+
+ INIT_LIST_HEAD(&port->list);
+ list_add_tail(&port->list, &pcie->ports);
+
+ return 0;
+}
+
static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
{
struct device *dev = pcie->dev;
- struct device_node *node = dev->of_node;
+ struct device_node *node = dev->of_node, *child;
struct resource regs;
const char *type;
int err;
@@ -406,6 +457,22 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
if (IS_ERR(pcie->base))
return PTR_ERR(pcie->base);
+ for_each_available_child_of_node(node, child) {
+ int slot;
+
+ err = of_pci_get_devfn(child);
+ if (err < 0) {
+ dev_err(dev, "failed to parse devfn: %d\n", err);
+ return err;
+ }
+
+ slot = PCI_SLOT(err);
+
+ err = mt7621_pcie_parse_port(pcie, child, slot);
+ if (err)
+ return err;
+ }
+
return 0;
}
--
2.7.4
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[PATCH v3 04/20] staging: mt7621-pci: factor out 'mt7621_pcie_enable_port' function
Driver probe function is a mess and shall be refactored a lot. At first
make use of assert and deassert control factoring out a new function
called 'mt7621_pcie_enable_port'.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 88 +++--
1 file changed, 41 insertions(+), 47 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 06395d1..da6a137 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -487,6 +487,39 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
return 0;
}
+static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
+{
+ struct mt7621_pcie *pcie = port->pcie;
+ struct device *dev = pcie->dev;
+ u32 slot = port->slot;
+ u32 val = 0;
+ int err;
+
+ err = clk_prepare_enable(port->pcie_clk);
+ if (err) {
+ dev_err(dev, "failed to enable pcie%d clock\n", slot);
+ return err;
+ }
+
+ reset_control_assert(port->pcie_rst);
+ reset_control_deassert(port->pcie_rst);
+
+ if ((pcie_port_read(port, RALINK_PCI_STATUS) & 0x1) == 0) {
+ dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", slot);
+ reset_control_assert(port->pcie_rst);
+ rt_sysc_m32(BIT(24 + slot), 0, RALINK_CLKCFG1);
+ pcie_link_status &= ~(1 << slot);
+ } else {
+ pcie_link_status |= BIT(slot);
+ val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+ /* enable pcie interrupt */
+ val |= BIT(20 + slot);
+ pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
+ }
+
+ return 0;
+}
+
static int mt7621_pcie_request_resources(struct mt7621_pcie *pcie,
struct list_head *res)
{
@@ -525,6 +558,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct mt7621_pcie *pcie;
struct pci_host_bridge *bridge;
+ struct mt7621_pcie_port *port, *tmp;
int err;
u32 val = 0;
LIST_HEAD(res);
@@ -553,12 +587,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
ioport_resource.start = 0;
ioport_resource.end = ~0UL; /* no limit */
- val = RALINK_PCIE0_RST;
- val |= RALINK_PCIE1_RST;
- val |= RALINK_PCIE2_RST;
-
- ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST |
RALINK_PCIE2_RST);
-
*(unsigned int *)(0xbe60) &= ~(0x3<<10 | 0x3<<3);
*(unsigned int *)(0xbe60) |= 0x1<<10 | 0x1<<3;
mdelay(100);
@@ -568,11 +596,13 @@ static int mt7621_pci_probe(struct platform_device *pdev)
mdelay(100);
- val = RALINK_PCIE0_RST;
- val |= RALINK_PCIE1_RST;
- val |= RALINK_PCIE2_RST;
-
- DEASSERT_SYSRST_PCIE(val);
+ list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
+ err = mt7621_pcie_enable_port(port);
+ if (err) {
+ dev_err(dev, "enabling port %d failed\n", port->slot);
+ list_del(&port->list);
+ }
+ }
if ((*(unsigned int *)(0xbe0c)&0x) == 0x0101) // MT7621 E2
bypass_pipe_rst(pcie);
@@ -601,42 +631,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;
// set DATA
mdelay(1000);
- if ((pcie_read(pcie, RT6855_PCIE0_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
- printk("PCIE0 no card, disable it(RST&CLK)\n");
- ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
- rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
- pcie_link_status &= ~(1<<0);
- } else {
- pcie_link_status |= 1<<0;
- val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
- val |= (1<<20); // enable pcie1 interrupt
- pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
- }
-
- if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
- printk("PCIE1 no card, disable it(RST&CLK)\n");
- ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
- rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1);
- pcie_link_status &= ~(1<<1);
- } else {
- pcie_link_status |= 1<<1;
- val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
- val |= (1<<21); // enable pcie1 interrupt
- pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
- }
-
- if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
- printk("PCIE2 no card, disable it(RST&CLK)\n");
- ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
- rt_sysc_m32(RALINK_PCIE2_CLK_EN, 0, RALINK_CLKCFG1);
-
[PATCH v3 07/20] staging: mt7621-pci: remove two commented code lines
This two lines whch are commented are not needed at all. Remove them. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index eecad11..61da75d 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -639,11 +639,6 @@ pcie(2/1/0) link statuspcie2_num pcie1_num pcie0_num break; } -/* - ioport_resource.start = mt7621_res_pci_io1.start; - ioport_resource.end = mt7621_res_pci_io1.end; -*/ - pcie_write(pcie, 0x, RALINK_PCI_MEMBASE); pcie_write(pcie, RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE); -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v3 10/20] staging: mt7621-pci: make some function static
There are some functions in driver code that can be declared
'static'. Just do it.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 9c5a8db..ac30175 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -186,7 +186,7 @@ write_config(struct mt7621_pcie *pcie, unsigned int dev,
u32 reg, u32 val)
pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
}
-void
+static void
set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
int start_b, int bits, int val)
{
@@ -197,7 +197,7 @@ set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
pcie_write(pcie, reg, offset);
}
-void
+static void
bypass_pipe_rst(struct mt7621_pcie *pcie)
{
/* PCIe Port 0 */
@@ -211,7 +211,7 @@ bypass_pipe_rst(struct mt7621_pcie *pcie)
set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1,
0x01);// rg_pe1_pipe_cmd_frc[4]
}
-void
+static void
set_phy_for_ssc(struct mt7621_pcie *pcie)
{
unsigned long reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
--
2.7.4
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[PATCH v3 09/20] staging: mt7621-pci: reagroup reset related macros all together
Reset bits related macros are in different parts. Reagroup all of them together to improve readability. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 11c2287..9c5a8db 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -45,6 +45,9 @@ #define RALINK_PCI_CONFIG_DATA 0x24 #define RALINK_PCI_MEMBASE 0x28 #define RALINK_PCI_IOBASE 0x2C + +/* RALINK_RSTCTRL bits */ +#define RALINK_PCIE_RSTBIT(23) #define RALINK_PCIE0_RST BIT(24) #define RALINK_PCIE1_RST BIT(25) #define RALINK_PCIE2_RST BIT(26) @@ -74,8 +77,6 @@ #define RALINK_GPIOMODE0x60 #define RALINK_PCIE_CLK_GEN0x7c #define RALINK_PCIE_CLK_GEN1 0x80 -//RALINK_RSTCTRL bit -#define RALINK_PCIE_RSTBIT(23) #define MEMORY_BASE 0x0 static int pcie_link_status = 0; -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v3 13/20] staging: mt7621-pci: factor out 'mt7621_enable_phy' function
Factor out a new function 'mt7621_enable_phy' for enabling the
pcie phy for each port and call it from 'mt7621_pcie_enable_port'.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 11ec464..4636e7e 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -388,6 +388,14 @@ set_phy_for_ssc(struct mt7621_pcie_port *port)
pcie_write(pcie, val, offset);
}
+static void mt7621_enable_phy(struct mt7621_pcie_port *port)
+{
+ /* MT7621 E2 */
+ if ((*(unsigned int *)(0xbe0c)&0x) == 0x0101)
+ bypass_pipe_rst(port);
+ set_phy_for_ssc(port);
+}
+
static void setup_cm_memory_region(struct resource *mem_resource)
{
resource_size_t mask;
@@ -573,6 +581,8 @@ static int mt7621_pcie_enable_port(struct mt7621_pcie_port
*port)
pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
}
+ mt7621_enable_phy(port);
+
return 0;
}
@@ -660,9 +670,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
dev_err(dev, "enabling port %d failed\n", slot);
list_del(&port->list);
} else {
- if ((*(unsigned int *)(0xbe0c)&0x) == 0x0101)
// MT7621 E2
- bypass_pipe_rst(port);
- set_phy_for_ssc(port);
val = read_config(pcie, slot, 0x70c);
dev_info(dev, "Port %d N_FTS = %x\n", (unsigned
int)val, slot);
}
--
2.7.4
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[PATCH v3 16/20] staging: mt7621-dts: add sysctl registers base address to pcie
Add missing system control registers address in pcie node of the device tree. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts/mt7621.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 2e837e6..6b4bc43 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -397,8 +397,8 @@ reg = <0x1e14 0x100 /* host-pci bridge registers */ 0x1e142000 0x100/* pcie port 0 RC control registers */ 0x1e143000 0x100/* pcie port 1 RC control registers */ - 0x1e144000 0x100>; /* pcie port 2 RC control registers */ - + 0x1e144000 0x100/* pcie port 2 RC control registers */ + 0x1e00 0x100>; /* sysctl */ #address-cells = <3>; #size-cells = <2>; -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v3 11/20] staging: mt7621-pci: show N_FTS status using a loop
There are some printk's which can be replaced properly
using dev_* kernel functions. Use dev_info to show
N_FTS status for each port using a loop instead of duplicating
lines of code.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index ac30175..ae34392 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -565,14 +565,11 @@ static int mt7621_pci_probe(struct platform_device *pdev)
bypass_pipe_rst(pcie);
set_phy_for_ssc(pcie);
- val = read_config(pcie, 0, 0x70c);
- printk("Port 0 N_FTS = %x\n", (unsigned int)val);
-
- val = read_config(pcie, 1, 0x70c);
- printk("Port 1 N_FTS = %x\n", (unsigned int)val);
-
- val = read_config(pcie, 2, 0x70c);
- printk("Port 2 N_FTS = %x\n", (unsigned int)val);
+ list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
+ u32 slot = port->slot;
+ val = read_config(pcie, slot, 0x70c);
+ dev_info(dev, "Port %d N_FTS = %x\n", (unsigned int)val, slot);
+ }
rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
--
2.7.4
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[PATCH v3 15/20] staging: mt7621-pci: rename 'mt7621_pcie_enable_port' into 'mt7621_pcie_init_port'
Rename function 'mt7621_pcie_enable_port' with a name which is better
for what the function is really doing calling it 'mt7621_pcie_init_port'.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 9e009c8..dee6ae8 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -551,7 +551,7 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
return 0;
}
-static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
+static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
{
struct mt7621_pcie *pcie = port->pcie;
struct device *dev = pcie->dev;
@@ -668,7 +668,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
u32 slot = port->slot;
- err = mt7621_pcie_enable_port(port);
+ err = mt7621_pcie_init_port(port);
if (err) {
dev_err(dev, "enabling port %d failed\n", slot);
list_del(&port->list);
--
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[PATCH v3 19/20] staging: mt7621-pci: use dev_* functions instead of printk
checkpatch script is complaining about the use of printk instead
of use more proper dev_* kernel functions. Replace all of them
removing warnings.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index f3d6401..77a03d4 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -406,8 +406,10 @@ static void mt7621_enable_phy(struct mt7621_pcie_port
*port)
set_phy_for_ssc(port);
}
-static void setup_cm_memory_region(struct resource *mem_resource)
+static void setup_cm_memory_region(struct mt7621_pcie *pcie)
{
+ struct resource *mem_resource = &pcie->mem;
+ struct device *dev = pcie->dev;
resource_size_t mask;
if (mips_cps_numiocu(0)) {
@@ -420,7 +422,7 @@ static void setup_cm_memory_region(struct resource
*mem_resource)
write_gcr_reg1_base(mem_resource->start);
write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
- printk("PCI coherence region base: 0x%08llx, mask/settings:
0x%08llx\n",
+ dev_info(dev, "PCI coherence region base: 0x%08llx,
mask/settings: 0x%08llx\n",
(unsigned long long)read_gcr_reg1_base(),
(unsigned long long)read_gcr_reg1_mask());
}
@@ -779,7 +781,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
RT6855_PCIE0_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
pcie_write(pcie, 0x06040001,
RT6855_PCIE0_OFFSET + RALINK_PCI_CLASS);
- printk("PCIE0 enabled\n");
+ dev_info(dev, "PCIE0 enabled\n");
}
//PCIe1
@@ -791,7 +793,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
RT6855_PCIE1_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
pcie_write(pcie, 0x06040001,
RT6855_PCIE1_OFFSET + RALINK_PCI_CLASS);
- printk("PCIE1 enabled\n");
+ dev_info(dev, "PCIE1 enabled\n");
}
//PCIe2
@@ -803,7 +805,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
RT6855_PCIE2_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
pcie_write(pcie, 0x06040001,
RT6855_PCIE2_OFFSET + RALINK_PCI_CLASS);
- printk("PCIE2 enabled\n");
+ dev_info(dev, "PCIE2 enabled\n");
}
switch (pcie_link_status) {
@@ -838,7 +840,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
return err;
}
- setup_cm_memory_region(&pcie->mem);
+ setup_cm_memory_region(pcie);
err = mt7621_pcie_request_resources(pcie, &res);
if (err) {
--
2.7.4
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[PATCH v3 20/20] staging: mt7621-pci: do not initialise statics to 0
Static variables are initialised to 0 by GCC and checkpatch script also complains about that. Make it happy. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 77a03d4..7b9f5e3 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -148,7 +148,7 @@ #define RG_PE1_FRC_MSTCKDIVBIT(5) -static int pcie_link_status = 0; +static int pcie_link_status; /** * struct mt7621_pcie_port - PCIe port information -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v3 18/20] staging: mt7621-pci: use a trailing */ on a separate line
Chackpatch script is compalining about one comment which
is not following the kernel style. Fix it.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index d5ceccc..f3d6401 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -411,9 +411,11 @@ static void setup_cm_memory_region(struct resource
*mem_resource)
resource_size_t mask;
if (mips_cps_numiocu(0)) {
- /* FIXME: hardware doesn't accept mask values with 1s after
+ /*
+* FIXME: hardware doesn't accept mask values with 1s after
* 0s (e.g. 0xffef), so it would be great to warn if that's
-* about to happen */
+* about to happen
+*/
mask = ~(mem_resource->end - mem_resource->start);
write_gcr_reg1_base(mem_resource->start);
--
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[PATCH v3 14/20] staging: mt7621-pci: debug port N_FTS inside 'mt7621_pcie_enable_port'
Move debug for the port N_FTS from driver probe function to the more
appropiate one 'mt7621_pcie_enable_port'.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 4636e7e..9e009c8 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -583,6 +583,9 @@ static int mt7621_pcie_enable_port(struct mt7621_pcie_port
*port)
mt7621_enable_phy(port);
+ val = read_config(pcie, slot, 0x70c);
+ dev_info(dev, "Port %d N_FTS = %x\n", (unsigned int)val, slot);
+
return 0;
}
@@ -669,9 +672,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
if (err) {
dev_err(dev, "enabling port %d failed\n", slot);
list_del(&port->list);
- } else {
- val = read_config(pcie, slot, 0x70c);
- dev_info(dev, "Port %d N_FTS = %x\n", (unsigned
int)val, slot);
}
}
--
2.7.4
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[PATCH v3 12/20] staging: mt7621-pci: rewrite pcie phy related functions
Function 'bypass_pipe_rst' and 'set_phy_for_ssc' can be
written in a cleaner way. Instead of use comments to see which
bits are the ones which are being enabled add new macros with
that information using BIT and GENMASK kernel macros. Avoid the
use of set_pcie_phy which is kind of dark and use new macros also
resetting and adding bits using bitwise operators directly in the
code. Now these function are offset-based on the port to use them
cleaner in driver probe functio and improving readability.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 295 +---
1 file changed, 196 insertions(+), 99 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index ae34392..11ec464 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -66,9 +66,6 @@
#define RALINK_PCI_SUBID 0x0038
#define RALINK_PCI_STATUS 0x0050
-#define RALINK_PCIEPHY_P0P1_CTL_OFFSET 0x9000
-#define RALINK_PCIEPHY_P2_CTL_OFFSET 0xA000
-
#define RALINK_PCI_MM_MAP_BASE 0x6000
#define RALINK_PCI_IO_MAP_BASE 0x1e16
@@ -79,6 +76,72 @@
#define RALINK_PCIE_CLK_GEN1 0x80
#define MEMORY_BASE 0x0
+
+/* pcie phy related macros */
+#define RALINK_PCIEPHY_P0P1_CTL_OFFSET 0x9000
+#define RALINK_PCIEPHY_P2_CTL_OFFSET 0xA000
+
+#define RG_P0_TO_P1_WIDTH 0x100
+
+#define RG_PE1_PIPE_REG0x02c
+#define RG_PE1_PIPE_RSTBIT(12)
+#define RG_PE1_PIPE_CMD_FRCBIT(4)
+
+#define RG_PE1_H_LCDDS_REG 0x49c
+#define RG_PE1_H_LCDDS_PCW GENMASK(30, 0)
+#define RG_PE1_H_LCDDS_PCW_VAL(x) ((0x7fff & (x)) << 0)
+
+#define RG_PE1_FRC_H_XTAL_REG 0x400
+#define RG_PE1_FRC_H_XTAL_TYPE BIT(8)
+#define RG_PE1_H_XTAL_TYPE GENMASK(10, 9)
+#define RG_PE1_H_XTAL_TYPE_VAL(x) ((0x3 & (x)) << 9)
+
+#define RG_PE1_FRC_PHY_REG 0x000
+#define RG_PE1_FRC_PHY_EN BIT(4)
+#define RG_PE1_PHY_EN BIT(5)
+
+#define RG_PE1_H_PLL_REG 0x490
+#define RG_PE1_H_PLL_BCGENMASK(23, 22)
+#define RG_PE1_H_PLL_BC_VAL(x) ((0x3 & (x)) << 22)
+#define RG_PE1_H_PLL_BPGENMASK(21, 18)
+#define RG_PE1_H_PLL_BP_VAL(x) ((0xf & (x)) << 18)
+#define RG_PE1_H_PLL_IRGENMASK(15, 12)
+#define RG_PE1_H_PLL_IR_VAL(x) ((0xf & (x)) << 12)
+#define RG_PE1_H_PLL_ICGENMASK(11, 8)
+#define RG_PE1_H_PLL_IC_VAL(x) ((0xf & (x)) << 8)
+#define RG_PE1_H_PLL_PREDIV GENMASK(7, 6)
+#define RG_PE1_H_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6)
+#define RG_PE1_PLL_DIVEN GENMASK(3, 1)
+#define RG_PE1_PLL_DIVEN_VAL(x)((0x7 & (x)) << 1)
+
+#define RG_PE1_H_PLL_FBKSEL_REG0x4bc
+#define RG_PE1_H_PLL_FBKSEL GENMASK(5, 4)
+#define RG_PE1_H_PLL_FBKSEL_VAL(x) ((0x3 & (x)) << 4)
+
+#defineRG_PE1_H_LCDDS_SSC_PRD_REG 0x4a4
+#define RG_PE1_H_LCDDS_SSC_PRD GENMASK(15, 0)
+#define RG_PE1_H_LCDDS_SSC_PRD_VAL(x) ((0x & (x)) << 0)
+
+#define RG_PE1_H_LCDDS_SSC_DELTA_REG 0x4a8
+#define RG_PE1_H_LCDDS_SSC_DELTAGENMASK(11, 0)
+#define RG_PE1_H_LCDDS_SSC_DELTA_VAL(x) ((0xfff & (x)) << 0)
+#define RG_PE1_H_LCDDS_SSC_DELTA1 GENMASK(27, 16)
+#define RG_PE1_H_LCDDS_SSC_DELTA1_VAL(x) ((0xff & (x)) << 16)
+
+#define RG_PE1_LCDDS_CLK_PH_INV_REG0x4a0
+#define RG_PE1_LCDDS_CLK_PH_INVBIT(5)
+
+#define RG_PE1_H_PLL_BR_REG0x4ac
+#define RG_PE1_H_PLL_BRGENMASK(18, 16)
+#define RG_PE1_H_PLL_BR_VAL(x) ((0x7 & (x)) << 16)
+
+#defineRG_PE1_MSTCKDIV_REG 0x414
+#define RG_PE1_MSTCKDIVGENMASK(7, 6)
+#define RG_PE1_MSTCKDIV_VAL(x) ((0x3 & (x)) << 6)
+
+#define RG_PE1_FRC_MSTCKDIVBIT(5)
+
+
static int pcie_link_status = 0;
/**
@@ -86,6 +149,7 @@ static int pcie_link_status = 0;
* @base: I/O mapped register base
* @list: port list
* @pcie: pointer to PCIe host info
+ * @phy_reg_offset: offset to related phy registers
* @pcie_rst: pointer to port reset control
* @pcie_clk: PCIe clock
* @slot: port slot
@@ -94,6 +158,7 @@ struct mt7621_pcie_port {
void __iomem *base;
struct list_head list;
struct mt7621_pcie *pcie;
+ u32 phy_reg_offset;
struct reset_control *pcie_rst;
struct clk *pcie_clk;
u32 slot;
@@ -187,109 +252,140 @@ write_config(struct mt7621_pcie *pcie, unsigned int
dev, u32 reg, u32 val)
}
static void
-set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
-int start_b, int bits, int val)
+bypass_pipe_rst(struct mt7621_pcie_port *port)
{
+ struct mt7621_pcie *pcie = port->pcie;
+ u32 phy_offset = por
[PATCH v3 17/20] staging: mt7621-pci: remap and use sysctl from device tree
There are some pointer read and writes which can be replaced
properly using sysctl registers readed from device tree. Remap
sysctl registers and replace in proper places.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 38 -
1 file changed, 33 insertions(+), 5 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index dee6ae8..d5ceccc 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -37,6 +37,12 @@
* devices.
*/
+/* sysctl */
+#define MT7621_CHIP_REV_ID 0x0c
+#define MT7621_GPIO_MODE 0x60
+#define CHIP_REV_MT7621_E2 0x0101
+
+/* pcie */
#define RALINK_PCIE0_CLK_ENBIT(24)
#define RALINK_PCIE1_CLK_ENBIT(25)
#define RALINK_PCIE2_CLK_ENBIT(26)
@@ -167,6 +173,7 @@ struct mt7621_pcie_port {
/**
* struct mt7621_pcie - PCIe host information
* @base: IO Mapped Register Base
+ * @sysctl: system control mapped register base
* @io: IO resource
* @mem: non-prefetchable memory resource
* @busn: bus range
@@ -176,6 +183,7 @@ struct mt7621_pcie_port {
*/
struct mt7621_pcie {
void __iomem *base;
+ void __iomem *sysctl;
struct device *dev;
struct resource io;
struct resource mem;
@@ -390,8 +398,10 @@ set_phy_for_ssc(struct mt7621_pcie_port *port)
static void mt7621_enable_phy(struct mt7621_pcie_port *port)
{
- /* MT7621 E2 */
- if ((*(unsigned int *)(0xbe0c)&0x) == 0x0101)
+ struct mt7621_pcie *pcie = port->pcie;
+ u32 chip_rev_id = ioread32(pcie->sysctl + MT7621_CHIP_REV_ID);
+
+ if ((chip_rev_id & 0x) == CHIP_REV_MT7621_E2)
bypass_pipe_rst(port);
set_phy_for_ssc(port);
}
@@ -532,6 +542,16 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
if (IS_ERR(pcie->base))
return PTR_ERR(pcie->base);
+ err = of_address_to_resource(node, 4, ®s);
+ if (err) {
+ dev_err(dev, "missing \"reg\" property\n");
+ return err;
+ }
+
+ pcie->sysctl = devm_ioremap_resource(dev, ®s);
+ if (IS_ERR(pcie->sysctl))
+ return PTR_ERR(pcie->sysctl);
+
for_each_available_child_of_node(node, child) {
int slot;
@@ -622,6 +642,16 @@ static int mt7621_pcie_register_host(struct
pci_host_bridge *host,
return pci_host_probe(host);
}
+static void mt7621_set_gpio_mode(struct mt7621_pcie *pcie)
+{
+ u32 reg = ioread32(pcie->sysctl + MT7621_GPIO_MODE);
+
+ reg &= ~(0x3<<10 | 0x3<<3);
+ reg |= (BIT(10) | BIT(3));
+ iowrite32(reg, pcie->sysctl + MT7621_GPIO_MODE);
+ mdelay(100);
+}
+
static int mt7621_pci_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -656,9 +686,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
ioport_resource.start = 0;
ioport_resource.end = ~0UL; /* no limit */
- *(unsigned int *)(0xbe60) &= ~(0x3<<10 | 0x3<<3);
- *(unsigned int *)(0xbe60) |= 0x1<<10 | 0x1<<3;
- mdelay(100);
+ mt7621_set_gpio_mode(pcie);
*(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use
GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
mdelay(100);
*(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7);
// clear DATA
--
2.7.4
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