Re: [PATCH 05/23] staging: wilc1000: rename goto to avoid leading '_' in label name
Fantastic. Thanks! regards, dan carpenter ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [RFC PATCH v5] Xilinx AXI-Stream FIFO v4.1 IP core
The README is empty... It should say what changes are needed to get this out of staging. regards, dan carpenter ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH 1/2] staging: erofs: add the missing break in z_erofs_map_blocks_iter
On Wed, Aug 01, 2018 at 02:38:30PM +0800, Gao Xiang wrote:
> diff --git a/drivers/staging/erofs/unzip_vle.c
> b/drivers/staging/erofs/unzip_vle.c
> index bd2d7a8..6d3ab31 100644
> --- a/drivers/staging/erofs/unzip_vle.c
> +++ b/drivers/staging/erofs/unzip_vle.c
> @@ -1596,10 +1596,10 @@ int z_erofs_map_blocks_iter(struct inode *inode,
> cluster_type = vle_cluster_type(di);
>
> switch (cluster_type) {
> - case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN:
> + case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN:/* fallthrough */
This fallthrough comment is in the wrong place. It should be at the end
where the break would have been. Like this:
switch (cluster_type) {
case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN:
frob();
frob();
frob();
/* fallthrough */
case Z_EROFS_VLE_CLUSTER_TYPE_HEAD:
frob();
regards,
dan carpenter
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Re: [PATCH 1/2] staging: erofs: add the missing break in z_erofs_map_blocks_iter
Hi Dan,
On 2018/8/1 17:02, Dan Carpenter wrote:
> On Wed, Aug 01, 2018 at 02:38:30PM +0800, Gao Xiang wrote:
>> diff --git a/drivers/staging/erofs/unzip_vle.c
>> b/drivers/staging/erofs/unzip_vle.c
>> index bd2d7a8..6d3ab31 100644
>> --- a/drivers/staging/erofs/unzip_vle.c
>> +++ b/drivers/staging/erofs/unzip_vle.c
>> @@ -1596,10 +1596,10 @@ int z_erofs_map_blocks_iter(struct inode *inode,
>> cluster_type = vle_cluster_type(di);
>>
>> switch (cluster_type) {
>> -case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN:
>> +case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN:/* fallthrough */
> This fallthrough comment is in the wrong place. It should be at the end
> where the break would have been. Like this:
>
> switch (cluster_type) {
> case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN:
> frob();
> frob();
> frob();
> /* fallthrough */
> case Z_EROFS_VLE_CLUSTER_TYPE_HEAD:
> frob();
>
I am sorry.. I will send a new patch.
Thanks for your reply...
Thanks,
Gao Xiang
> regards,
> dan carpenter
>
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Re: [PATCH char-misc 1/1] Drivers: hv: vmbus: Make synic_initialized flag per-cpu
"Michael Kelley (EOSG)" writes:
> From: Vitaly Kuznetsov Sent: Tuesday, July 31, 2018
> 4:20 AM
>>
>> Alternatively, we can get rid of synic_initialized flag altogether:
>> hv_synic_init() never fails in the first place but we can always
>> implement something like:
>>
>> int hv_synic_is_initialized(void) {
>> union hv_synic_scontrol sctrl;
>>
>> hv_get_synic_state(sctrl.as_uint64);
>>
>> return sctrl.enable;
>> }
>>
>> as it doesn't seem that we need to check synic state on _other_ CPUs.
>>
>
> I was trying to decide if there are any arguments in favor of one
> approach vs. the other: a per-cpu flag in memory or checking
> the synic_control "enable" bit. Seems like a wash to me, in which
> case I have a slight preference for the per-cpu flag in memory vs.
> creating another function to return sctrl.enable. But I'm completely
> open to reasons why checking sctrl.enable is better.
Just a few thoughts: reading MSR is definitely slower but we avoid
'shadowing' the state, the reading is always correct. In case there's a
chance the SynIC will get disabled from host side we can only find this
out by doing MSR read. This is a purely theoretical possibility, I
believe, we can go ahead with this patch.
--
Vitaly
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[PATCH RESEND 1/2] staging: erofs: add the missing break in z_erofs_map_blocks_iter
This patch adds a missing break after adding the default case.
Reviewed-by: Chao Yu
Signed-off-by: Gao Xiang
---
As pointed out by Dan Carpenter:
- fix the wrong place of fallthrough comments
drivers/staging/erofs/unzip_vle.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/staging/erofs/unzip_vle.c
b/drivers/staging/erofs/unzip_vle.c
index bd2d7a8..1030ca5 100644
--- a/drivers/staging/erofs/unzip_vle.c
+++ b/drivers/staging/erofs/unzip_vle.c
@@ -1599,6 +1599,7 @@ int z_erofs_map_blocks_iter(struct inode *inode,
case Z_EROFS_VLE_CLUSTER_TYPE_PLAIN:
if (ofs_rem >= logical_cluster_ofs)
map->m_flags ^= EROFS_MAP_ZIPPED;
+ /* fallthrough */
case Z_EROFS_VLE_CLUSTER_TYPE_HEAD:
if (ofs_rem == logical_cluster_ofs) {
pcn = le32_to_cpu(di->di_u.blkaddr);
@@ -1619,11 +1620,13 @@ int z_erofs_map_blocks_iter(struct inode *inode,
goto unmap_out;
}
end = (lcn-- * clustersize) | logical_cluster_ofs;
+ /* fallthrough */
case Z_EROFS_VLE_CLUSTER_TYPE_NONHEAD:
/* get the correspoinding first chunk */
ofs = vle_get_logical_extent_head(inode, mpage_ret,
&kaddr, lcn, &pcn, &map->m_flags);
mpage = *mpage_ret;
+ break;
default:
errln("unknown cluster type %u at offset %llu of nid %llu",
cluster_type, ofs, EROFS_V(inode)->nid);
--
1.9.1
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[PATCH] staging: mt29f_spinand: fix memory leak while programming pages
In spinand_program_page(), it uses devm_kzalloc() to allocate memory to wbuf dynamically if internal ECC is on, but it doesn't free memory allocated to wbuf at the end of this function. This leads to a memory leak issue when internal ECC is on. Signed-off-by: Jheng-Jhong Wu --- drivers/staging/mt29f_spinand/mt29f_spinand.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/staging/mt29f_spinand/mt29f_spinand.c b/drivers/staging/mt29f_spinand/mt29f_spinand.c index e389009..cf51ca8 100644 --- a/drivers/staging/mt29f_spinand/mt29f_spinand.c +++ b/drivers/staging/mt29f_spinand/mt29f_spinand.c @@ -553,6 +553,8 @@ static int spinand_program_page(struct spi_device *spi_nand, } enable_hw_ecc = 0; } + + devm_kfree(&spi_nand->dev, wbuf); #endif return 0; -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH 0/2] staging: wilc1000: fix endianness issues identified by sparse
This patch series has changes to fix the sparse warnings & use correct byte-order conversion. It also includes changes to use correct datatype for 'wid' in cfg struct. Ajay Singh (2): staging: wilc1000: use 'u16' data type for config id parameter staging: wilc1000: fix endianness warnings reported by sparse drivers/staging/wilc1000/linux_mon.c | 1 + drivers/staging/wilc1000/wilc_sdio.c | 4 ++-- drivers/staging/wilc1000/wilc_spi.c | 8 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c | 6 -- drivers/staging/wilc1000/wilc_wlan.c | 12 ++-- drivers/staging/wilc1000/wilc_wlan_cfg.c | 21 ++--- drivers/staging/wilc1000/wilc_wlan_cfg.h | 4 ++-- 7 files changed, 29 insertions(+), 27 deletions(-) -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH 1/2] staging: wilc1000: use 'u16' data type for config id parameter
Cleanup patch to use the correct data type 'u16' for keeping the WID
value in 'wilc_cfg_word' & 'wilc_cfg_str' structure.
Signed-off-by: Ajay Singh
---
drivers/staging/wilc1000/wilc_wlan_cfg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/wilc1000/wilc_wlan_cfg.h
b/drivers/staging/wilc1000/wilc_wlan_cfg.h
index 08092a5..2aa7a9b 100644
--- a/drivers/staging/wilc1000/wilc_wlan_cfg.h
+++ b/drivers/staging/wilc1000/wilc_wlan_cfg.h
@@ -22,12 +22,12 @@ struct wilc_cfg_hword {
};
struct wilc_cfg_word {
- u32 id;
+ u16 id;
u32 val;
};
struct wilc_cfg_str {
- u32 id;
+ u16 id;
u8 *str;
};
--
2.7.4
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[PATCH 2/2] staging: wilc1000: fix endianness warnings reported by sparse
This patch fixes the sparse warnings by making use of le32_to_cpus() &
cpu_to_le32s() conversion API's.
Remove the unnecessary byte-order conversion in
wilc_wlan_parse_response_frame() as the data is copied using individual
byte operation.
Also added the byte-order conversion for 'header' in
wilc_wfi_monitor_rx() & wilc_wfi_p2p_rx() as received in LE byte-order.
The link [1] contains the details of discussion related to this patch.
[1]. https://patchwork.kernel.org/patch/10436791/
Signed-off-by: Ajay Singh
---
drivers/staging/wilc1000/linux_mon.c | 1 +
drivers/staging/wilc1000/wilc_sdio.c | 4 ++--
drivers/staging/wilc1000/wilc_spi.c | 8
drivers/staging/wilc1000/wilc_wfi_cfgoperations.c | 6 --
drivers/staging/wilc1000/wilc_wlan.c | 12 ++--
drivers/staging/wilc1000/wilc_wlan_cfg.c | 21 ++---
6 files changed, 27 insertions(+), 25 deletions(-)
diff --git a/drivers/staging/wilc1000/linux_mon.c
b/drivers/staging/wilc1000/linux_mon.c
index 14405bf..020383c 100644
--- a/drivers/staging/wilc1000/linux_mon.c
+++ b/drivers/staging/wilc1000/linux_mon.c
@@ -39,6 +39,7 @@ void wilc_wfi_monitor_rx(u8 *buff, u32 size)
/* Get WILC header */
memcpy(&header, (buff - HOST_HDR_OFFSET), HOST_HDR_OFFSET);
+ le32_to_cpus(&header);
/*
* The packet offset field contain info about what type of management
* the frame we are dealing with and ack status
diff --git a/drivers/staging/wilc1000/wilc_sdio.c
b/drivers/staging/wilc1000/wilc_sdio.c
index 8a47147..459eb11 100644
--- a/drivers/staging/wilc1000/wilc_sdio.c
+++ b/drivers/staging/wilc1000/wilc_sdio.c
@@ -384,7 +384,7 @@ static int sdio_write_reg(struct wilc *wilc, u32 addr, u32
data)
struct sdio_func *func = dev_to_sdio_func(wilc->dev);
int ret;
- data = cpu_to_le32(data);
+ cpu_to_le32s(&data);
if (addr >= 0xf0 && addr <= 0xff) {
struct sdio_cmd52 cmd;
@@ -563,7 +563,7 @@ static int sdio_read_reg(struct wilc *wilc, u32 addr, u32
*data)
}
}
- *data = cpu_to_le32(*data);
+ le32_to_cpus(*data);
return 1;
diff --git a/drivers/staging/wilc1000/wilc_spi.c
b/drivers/staging/wilc1000/wilc_spi.c
index fa9371b..bb2c738 100644
--- a/drivers/staging/wilc1000/wilc_spi.c
+++ b/drivers/staging/wilc1000/wilc_spi.c
@@ -678,7 +678,7 @@ static int spi_internal_write(struct wilc *wilc, u32 adr,
u32 dat)
struct spi_device *spi = to_spi_device(wilc->dev);
int result;
- dat = cpu_to_le32(dat);
+ cpu_to_le32s(&dat);
result = spi_cmd_complete(wilc, CMD_INTERNAL_WRITE, adr, (u8 *)&dat, 4,
0);
if (result != N_OK)
@@ -699,7 +699,7 @@ static int spi_internal_read(struct wilc *wilc, u32 adr,
u32 *data)
return 0;
}
- *data = cpu_to_le32(*data);
+ le32_to_cpus(*data);
return 1;
}
@@ -717,7 +717,7 @@ static int wilc_spi_write_reg(struct wilc *wilc, u32 addr,
u32 data)
u8 cmd = CMD_SINGLE_WRITE;
u8 clockless = 0;
- data = cpu_to_le32(data);
+ cpu_to_le32s(&data);
if (addr < 0x30) {
/* Clockless register */
cmd = CMD_INTERNAL_WRITE;
@@ -779,7 +779,7 @@ static int wilc_spi_read_reg(struct wilc *wilc, u32 addr,
u32 *data)
return 0;
}
- *data = cpu_to_le32(*data);
+ le32_to_cpus(*data);
return 1;
}
diff --git a/drivers/staging/wilc1000/wilc_wfi_cfgoperations.c
b/drivers/staging/wilc1000/wilc_wfi_cfgoperations.c
index 42c0128..c6f2cf6 100644
--- a/drivers/staging/wilc1000/wilc_wfi_cfgoperations.c
+++ b/drivers/staging/wilc1000/wilc_wfi_cfgoperations.c
@@ -1363,9 +1363,10 @@ void wilc_wfi_p2p_rx(struct net_device *dev, u8 *buff,
u32 size)
struct host_if_drv *wfi_drv = priv->hif_drv;
u32 header, pkt_offset;
s32 freq;
+ __le16 fc;
memcpy(&header, (buff - HOST_HDR_OFFSET), HOST_HDR_OFFSET);
-
+ le32_to_cpus(&header);
pkt_offset = GET_PKT_OFFSET(header);
if (pkt_offset & IS_MANAGMEMENT_CALLBACK) {
@@ -1382,7 +1383,8 @@ void wilc_wfi_p2p_rx(struct net_device *dev, u8 *buff,
u32 size)
freq = ieee80211_channel_to_frequency(curr_channel, NL80211_BAND_2GHZ);
- if (!ieee80211_is_action(buff[FRAME_TYPE_ID])) {
+ fc = ((struct ieee80211_hdr *)buff)->frame_control;
+ if (!ieee80211_is_action(fc)) {
cfg80211_rx_mgmt(priv->wdev, freq, 0, buff, size, 0);
return;
}
diff --git a/drivers/staging/wilc1000/wilc_wlan.c
b/drivers/staging/wilc1000/wilc_wlan.c
index ea2e77f..cde5ce1 100644
--- a/drivers/staging/wilc1000/wilc_wlan.c
+++ b/drivers/staging/wilc1000/wilc_wlan.c
@@ -541,7 +541,7 @@ int wilc_wlan_handle_txq(struct net_device *dev, u32
*txq_count)
vmm_tabl
Re: [PATCH RESEND 1/2] staging: erofs: add the missing break in z_erofs_map_blocks_iter
On Wed, Aug 01, 2018 at 05:36:54PM +0800, Gao Xiang wrote: > This patch adds a missing break after adding the default case. > > Reviewed-by: Chao Yu > Signed-off-by: Gao Xiang > --- > As pointed out by Dan Carpenter: > - fix the wrong place of fallthrough comments Thanks. Looks good. Next time use [PATCH v2] instead of RESEND. The word RESEND basically means you are resending a patch exactly the same as it was before. You would only need to do that if we accidentally deleted your first patch or whatever... regards, dan carpenter ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH] staging: mt29f_spinand: fix memory leak while programming pages
devm_ resources are freed automatically when the device is removed. The name devm_ stands for "device" and "managed". regards, dan carpenter ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v5] staging: rts5208: add error handling into rtsx_probe
If rtsx_probe() fails to allocate dev->chip, then release_everything()
will crash on uninitialized dev->cmnd_ready complete.
Patch adds an error handling into rtsx_probe.
Found by Linux Driver Verification project (linuxtesting.org).
Signed-off-by: Anton Vasilyev
---
v5: fix mistype and remove superfluous pointers zeroing
v4: rename labels baced on Dan Carpenter's recommendation
v3: fix subject and commit message
v2: Add error handling into rtsx_probe based on Dan Carpenter's comment.
I do not have corresponding hardware, so patch was tested by compilation only.
I faced with inaccuracy at rtsx_remove() and original rtsx_probe():
there is quiesce_and_remove_host() call with scsi_remove_host() inside,
whereas release_everything() calls scsi_host_put() after this
scsi_remove_host() call. This is strange for me.
Also I do not know is it require to check result value of
rtsx_init_chip() call on rtsx_probe().
---
drivers/staging/rts5208/rtsx.c | 32 ++--
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/staging/rts5208/rtsx.c b/drivers/staging/rts5208/rtsx.c
index 70e0b8623110..6a5c670634b1 100644
--- a/drivers/staging/rts5208/rtsx.c
+++ b/drivers/staging/rts5208/rtsx.c
@@ -879,7 +879,7 @@ static int rtsx_probe(struct pci_dev *pci,
if (!dev->remap_addr) {
dev_err(&pci->dev, "ioremap error\n");
err = -ENXIO;
- goto errout;
+ goto err_chip_free;
}
/*
@@ -894,7 +894,7 @@ static int rtsx_probe(struct pci_dev *pci,
if (!dev->rtsx_resv_buf) {
dev_err(&pci->dev, "alloc dma buffer fail\n");
err = -ENXIO;
- goto errout;
+ goto err_addr_unmap;
}
dev->chip->host_cmds_ptr = dev->rtsx_resv_buf;
dev->chip->host_cmds_addr = dev->rtsx_resv_buf_addr;
@@ -915,7 +915,7 @@ static int rtsx_probe(struct pci_dev *pci,
if (rtsx_acquire_irq(dev) < 0) {
err = -EBUSY;
- goto errout;
+ goto err_disable_msi;
}
pci_set_master(pci);
@@ -935,14 +935,14 @@ static int rtsx_probe(struct pci_dev *pci,
if (IS_ERR(th)) {
dev_err(&pci->dev, "Unable to start control thread\n");
err = PTR_ERR(th);
- goto errout;
+ goto err_rtsx_release;
}
dev->ctl_thread = th;
err = scsi_add_host(host, &pci->dev);
if (err) {
dev_err(&pci->dev, "Unable to add the scsi host\n");
- goto errout;
+ goto err_complete_control_thread;
}
/* Start up the thread for delayed SCSI-device scanning */
@@ -950,18 +950,16 @@ static int rtsx_probe(struct pci_dev *pci,
if (IS_ERR(th)) {
dev_err(&pci->dev, "Unable to start the device-scanning
thread\n");
complete(&dev->scanning_done);
- quiesce_and_remove_host(dev);
err = PTR_ERR(th);
- goto errout;
+ goto err_stop_host;
}
/* Start up the thread for polling thread */
th = kthread_run(rtsx_polling_thread, dev, "rtsx-polling");
if (IS_ERR(th)) {
dev_err(&pci->dev, "Unable to start the device-polling
thread\n");
- quiesce_and_remove_host(dev);
err = PTR_ERR(th);
- goto errout;
+ goto err_stop_host;
}
dev->polling_thread = th;
@@ -970,9 +968,23 @@ static int rtsx_probe(struct pci_dev *pci,
return 0;
/* We come here if there are any problems */
+err_stop_host:
+ quiesce_and_remove_host(dev);
+err_complete_control_thread:
+ complete(&dev->cmnd_ready);
+ wait_for_completion(&dev->control_exit);
+err_rtsx_release:
+ free_irq(dev->irq, (void *)dev);
+ rtsx_release_chip(dev->chip);
+err_disable_msi:
+ if (dev->chip->msi_en)
+ pci_disable_msi(dev->pci);
+err_addr_unmap:
+ iounmap(dev->remap_addr);
+err_chip_free:
+ kfree(dev->chip);
errout:
dev_err(&pci->dev, "%s failed\n", __func__);
- release_everything(dev);
return err;
}
--
2.18.0
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Re: [PATCH] staging:mt29f_spinand: MT29F2G failing as only 16-bit arguments and variables used for addressing.
On Wed, Aug 01, 2018 at 11:24:19AM +0800, Jheng-Jhong Wu wrote:
> For NAND flash chips with more than 1Gbit (e.g. MT29F2G) more than 16 bits
> are necessary to address the correct page. The driver sets the address for
> more than 16 bits, but it uses 16-bit arguments and variables (these are
> page_id, block_id, row) to do address operations. Obviously, these
> arguments and variables cannot deal with more than 16-bit address.
>
> Signed-off-by: Jheng-Jhong Wu
This seems reasonable... It would be needed to make commit 6efb21d6d0e7
("staging:mt29f_spinand: MT29F2G failing as only 16 bits used for
addressing.") work. It also fixes a static checker warning.
My only concern is that the mtd/nand code seems to use -1 as a magical
page_id. For example:
2069 /**
2070 * nand_exit_status_op - Exit a STATUS operation
2071 * @chip: The NAND chip
2072 *
2073 * This function sends a READ0 command to cancel the effect of the
STATUS
2074 * command to avoid reading only the status until a new read command is
sent.
2075 *
2076 * This function does not select/unselect the CS line.
2077 *
2078 * Returns 0 on success, a negative error code otherwise.
2079 */
2080 int nand_exit_status_op(struct nand_chip *chip)
2081 {
2082 struct mtd_info *mtd = nand_to_mtd(chip);
2083
2084 if (chip->exec_op) {
2085 struct nand_op_instr instrs[] = {
2086 NAND_OP_CMD(NAND_CMD_READ0, 0),
2087 };
2088 struct nand_operation op = NAND_OPERATION(instrs);
2089
2090 return nand_exec_op(chip, &op);
2091 }
2092
2093 chip->cmdfunc(mtd, NAND_CMD_READ0, -1, -1);
^^ ^^
2094
2095 return 0;
2096 }
2097 EXPORT_SYMBOL_GPL(nand_exit_status_op);
I'm not sure if this affect spinand_read_page() etc.
regards,
dan carpenter
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Re: [PATCH RESEND 1/2] staging: erofs: add the missing break in z_erofs_map_blocks_iter
Hi Dan, On 2018/8/1 19:36, Dan Carpenter wrote: > On Wed, Aug 01, 2018 at 05:36:54PM +0800, Gao Xiang wrote: >> This patch adds a missing break after adding the default case. >> >> Reviewed-by: Chao Yu >> Signed-off-by: Gao Xiang >> --- >> As pointed out by Dan Carpenter: >> - fix the wrong place of fallthrough comments > Thanks. Looks good. Next time use [PATCH v2] instead of RESEND. The > word RESEND basically means you are resending a patch exactly the same > as it was before. You would only need to do that if we accidentally > deleted your first patch or whatever... > > regards, > dan carpenter > > OK, it should not be titled RESEND, and I will take care the next time. Thanks for taking the time to review :) Thanks, Gao Xiang ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH v5] staging: rts5208: add error handling into rtsx_probe
On Wed, Aug 1, 2018 at 2:55 PM, Anton Vasilyev wrote: > If rtsx_probe() fails to allocate dev->chip, then release_everything() > will crash on uninitialized dev->cmnd_ready complete. > > Patch adds an error handling into rtsx_probe. > Found by Linux Driver Verification project (linuxtesting.org). Have you based your change on staging-next? Seems not. You need to rebase and resend. -- With Best Regards, Andy Shevchenko ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH] staging:mt29f_spinand: MT29F2G failing as only 16-bit arguments and variables used for addressing.
Hi Dan,
Dan Carpenter wrote on Wed, 1 Aug 2018
15:05:51 +0300:
> On Wed, Aug 01, 2018 at 11:24:19AM +0800, Jheng-Jhong Wu wrote:
> > For NAND flash chips with more than 1Gbit (e.g. MT29F2G) more than 16 bits
> > are necessary to address the correct page. The driver sets the address for
> > more than 16 bits, but it uses 16-bit arguments and variables (these are
> > page_id, block_id, row) to do address operations. Obviously, these
> > arguments and variables cannot deal with more than 16-bit address.
> >
> > Signed-off-by: Jheng-Jhong Wu
>
> This seems reasonable... It would be needed to make commit 6efb21d6d0e7
> ("staging:mt29f_spinand: MT29F2G failing as only 16 bits used for
> addressing.") work. It also fixes a static checker warning.
>
> My only concern is that the mtd/nand code seems to use -1 as a magical
> page_id. For example:
I guess you missed Boris' comment: this driver is very likely to be
removed. A SPI-NAND framework has been added. It does not use the raw
NAND framework anymore, which was wrong anyway.
Thanks,
Miquèl
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Re: [PATCH] staging:mt29f_spinand: MT29F2G failing as only 16-bit arguments and variables used for addressing.
On Wed, Aug 01, 2018 at 03:55:30PM +0200, Miquel Raynal wrote:
> Hi Dan,
>
> Dan Carpenter wrote on Wed, 1 Aug 2018
> 15:05:51 +0300:
>
> > On Wed, Aug 01, 2018 at 11:24:19AM +0800, Jheng-Jhong Wu wrote:
> > > For NAND flash chips with more than 1Gbit (e.g. MT29F2G) more than 16 bits
> > > are necessary to address the correct page. The driver sets the address for
> > > more than 16 bits, but it uses 16-bit arguments and variables (these are
> > > page_id, block_id, row) to do address operations. Obviously, these
> > > arguments and variables cannot deal with more than 16-bit address.
> > >
> > > Signed-off-by: Jheng-Jhong Wu
> >
> > This seems reasonable... It would be needed to make commit 6efb21d6d0e7
> > ("staging:mt29f_spinand: MT29F2G failing as only 16 bits used for
> > addressing.") work. It also fixes a static checker warning.
> >
> > My only concern is that the mtd/nand code seems to use -1 as a magical
> > page_id. For example:
>
> I guess you missed Boris' comment: this driver is very likely to be
> removed. A SPI-NAND framework has been added. It does not use the raw
> NAND framework anymore, which was wrong anyway.
>
We should probably revert commit 6efb21d6d0e7 ("staging:mt29f_spinand:
MT29F2G failing as only 16 bits used for addressing.") in that case if
all it does is add static checker warnings...
regards,
dan carpenter
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Re: [PATCH v5] staging: rts5208: add error handling into rtsx_probe
I found that staging-next already contains my patch v3, committed by Greg Kroah-Hartman. Do I need to send a new patch with a label renaming based on Dan Carpenter comments? -- Anton Vasilyev Linux Verification Center, ISPRAS web: http://linuxtesting.org e-mail: vasil...@ispras.ru On 01.08.2018 15:18, Andy Shevchenko wrote: On Wed, Aug 1, 2018 at 2:55 PM, Anton Vasilyev wrote: If rtsx_probe() fails to allocate dev->chip, then release_everything() will crash on uninitialized dev->cmnd_ready complete. Patch adds an error handling into rtsx_probe. Found by Linux Driver Verification project (linuxtesting.org). Have you based your change on staging-next? Seems not. You need to rebase and resend. ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH v5] staging: rts5208: add error handling into rtsx_probe
On Wed, Aug 01, 2018 at 05:08:48PM +0300, Anton Vasilyev wrote: > I found that staging-next already contains my patch v3, committed by Greg > Kroah-Hartman. > > Do I need to send a new patch with a label renaming based on Dan Carpenter > comments? I had to look to see what I had said earlier... The naming isn't really a problem but we should call scsi_host_put(host); if the "dev->chip = kzalloc(sizeof(*dev->chip), GFP_KERNEL);" allocation fails. regards, dan capenter ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH v5] staging: rts5208: add error handling into rtsx_probe
On Wed, Aug 1, 2018 at 5:08 PM, Anton Vasilyev wrote: > I found that staging-next already contains my patch v3, committed by Greg > Kroah-Hartman. > > Do I need to send a new patch Yes. Based on staging-next. > with a label renaming based on Dan Carpenter > comments? Dan is talking for himself :-) -- With Best Regards, Andy Shevchenko ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [RFC PATCH v5] Xilinx AXI-Stream FIFO v4.1 IP core
On Wed, Aug 01, 2018 at 11:52:39AM +0300, Dan Carpenter wrote: > The README is empty... It should say what changes are needed to get > this out of staging. > > regards, > dan carpenter > Right :) It's ready as far as I'm concerned. Best, Jacob ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH 2/4] staging: fsl-dpaa2/eth: Remove dead code
File net.h contains unused defines, so remove them. Signed-off-by: Ioana Radulescu --- drivers/staging/fsl-dpaa2/ethernet/net.h | 85 1 file changed, 85 deletions(-) diff --git a/drivers/staging/fsl-dpaa2/ethernet/net.h b/drivers/staging/fsl-dpaa2/ethernet/net.h index ddea940..2461d6e 100644 --- a/drivers/staging/fsl-dpaa2/ethernet/net.h +++ b/drivers/staging/fsl-dpaa2/ethernet/net.h @@ -4,8 +4,6 @@ #ifndef __FSL_NET_H #define __FSL_NET_H -#define LAST_HDR_INDEX 0x - /* Protocol fields */ /* Ethernet fields */ @@ -17,8 +15,6 @@ #define NH_FLD_ETH_PADDING(NH_FLD_ETH_DA << 5) #define NH_FLD_ETH_ALL_FIELDS ((NH_FLD_ETH_DA << 6) - 1) -#define NH_FLD_ETH_ADDR_SIZE 6 - /* VLAN fields */ #define NH_FLD_VLAN_VPRI (1) #define NH_FLD_VLAN_CFI (NH_FLD_VLAN_VPRI << 1) @@ -42,8 +38,6 @@ #define NH_FLD_IP_ID (NH_FLD_IP_VER << 8) #define NH_FLD_IP_ALL_FIELDS ((NH_FLD_IP_VER << 9) - 1) -#define NH_FLD_IP_PROTO_SIZE 1 - /* IPV4 fields */ #define NH_FLD_IPV4_VER (1) #define NH_FLD_IPV4_HDR_LEN (NH_FLD_IPV4_VER << 1) @@ -62,9 +56,6 @@ #define NH_FLD_IPV4_OPTS_COUNT(NH_FLD_IPV4_VER << 14) #define NH_FLD_IPV4_ALL_FIELDS((NH_FLD_IPV4_VER << 15) - 1) -#define NH_FLD_IPV4_ADDR_SIZE 4 -#define NH_FLD_IPV4_PROTO_SIZE1 - /* IPV6 fields */ #define NH_FLD_IPV6_VER (1) #define NH_FLD_IPV6_TC(NH_FLD_IPV6_VER << 1) @@ -76,9 +67,6 @@ #define NH_FLD_IPV6_ID (NH_FLD_IPV6_VER << 7) #define NH_FLD_IPV6_ALL_FIELDS((NH_FLD_IPV6_VER << 8) - 1) -#define NH_FLD_IPV6_ADDR_SIZE 16 -#define NH_FLD_IPV6_NEXT_HDR_SIZE 1 - /* ICMP fields */ #define NH_FLD_ICMP_TYPE (1) #define NH_FLD_ICMP_CODE (NH_FLD_ICMP_TYPE << 1) @@ -87,9 +75,6 @@ #define NH_FLD_ICMP_SQ_NUM(NH_FLD_ICMP_TYPE << 4) #define NH_FLD_ICMP_ALL_FIELDS((NH_FLD_ICMP_TYPE << 5) - 1) -#define NH_FLD_ICMP_CODE_SIZE 1 -#define NH_FLD_ICMP_TYPE_SIZE 1 - /* IGMP fields */ #define NH_FLD_IGMP_VERSION (1) #define NH_FLD_IGMP_TYPE (NH_FLD_IGMP_VERSION << 1) @@ -111,8 +96,6 @@ #define NH_FLD_TCP_OPTS_COUNT (NH_FLD_TCP_PORT_SRC << 10) #define NH_FLD_TCP_ALL_FIELDS ((NH_FLD_TCP_PORT_SRC << 11) - 1) -#define NH_FLD_TCP_PORT_SIZE 2 - /* UDP fields */ #define NH_FLD_UDP_PORT_SRC (1) #define NH_FLD_UDP_PORT_DST (NH_FLD_UDP_PORT_SRC << 1) @@ -120,16 +103,12 @@ #define NH_FLD_UDP_CKSUM (NH_FLD_UDP_PORT_SRC << 3) #define NH_FLD_UDP_ALL_FIELDS ((NH_FLD_UDP_PORT_SRC << 4) - 1) -#define NH_FLD_UDP_PORT_SIZE 2 - /* UDP-lite fields */ #define NH_FLD_UDP_LITE_PORT_SRC (1) #define NH_FLD_UDP_LITE_PORT_DST (NH_FLD_UDP_LITE_PORT_SRC << 1) #define NH_FLD_UDP_LITE_ALL_FIELDS \ ((NH_FLD_UDP_LITE_PORT_SRC << 2) - 1) -#define NH_FLD_UDP_LITE_PORT_SIZE 2 - /* UDP-encap-ESP fields */ #define NH_FLD_UDP_ENC_ESP_PORT_SRC (1) #define NH_FLD_UDP_ENC_ESP_PORT_DST (NH_FLD_UDP_ENC_ESP_PORT_SRC << 1) @@ -140,9 +119,6 @@ #define NH_FLD_UDP_ENC_ESP_ALL_FIELDS \ ((NH_FLD_UDP_ENC_ESP_PORT_SRC << 6) - 1) -#define NH_FLD_UDP_ENC_ESP_PORT_SIZE2 -#define NH_FLD_UDP_ENC_ESP_SPI_SIZE 4 - /* SCTP fields */ #define NH_FLD_SCTP_PORT_SRC (1) #define NH_FLD_SCTP_PORT_DST (NH_FLD_SCTP_PORT_SRC << 1) @@ -150,15 +126,11 @@ #define NH_FLD_SCTP_CKSUM (NH_FLD_SCTP_PORT_SRC << 3) #define NH_FLD_SCTP_ALL_FIELDS((NH_FLD_SCTP_PORT_SRC << 4) - 1) -#define NH_FLD_SCTP_PORT_SIZE 2 - /* DCCP fields */ #define NH_FLD_DCCP_PORT_SRC (1) #define NH_FLD_DCCP_PORT_DST (NH_FLD_DCCP_PORT_SRC << 1) #define NH_FLD_DCCP_ALL_FIELDS((NH_FLD_DCCP_PORT_SRC << 2) - 1) -#define NH_FLD_DCCP_PORT_SIZE 2 - /* IPHC fields */ #define NH_FLD_IPHC_CID (1) #define NH_FLD_IPHC_CID_TYPE (NH_FLD_IPHC_CID << 1) @@ -324,7 +296,6 @@ #define NH_FLD_IPSEC_ESP_SEQUENCE_NUM (NH_FLD_IPSEC_ESP_SPI << 1) #define NH_FLD_IPSEC_ESP_ALL_FIELDS ((NH_FLD_IPSEC_ESP_SPI << 2) - 1) -#define NH_FLD_IPSEC_ESP_SPI_SIZE 4 /* MPLS fields */ #define NH_FLD_MPLS_LABEL_STACK (1) @@ -338,54 +309,6 @@ /* GTP fields */ #define NH_FLD_GTP_TEID (1) -/* Protocol options */ - -/* Ethernet options */ -#def
[PATCH 4/4] staging: fsl-dpaa2/eth: Merge header files
File net.h contains definitions that are exclusively used by
the key generator/classification API. Merge its contents with
dpkg.h in order to reduce the number of private headers.
Signed-off-by: Ioana Radulescu
---
drivers/staging/fsl-dpaa2/ethernet/dpkg.h | 350 -
drivers/staging/fsl-dpaa2/ethernet/net.h | 357 --
2 files changed, 349 insertions(+), 358 deletions(-)
delete mode 100644 drivers/staging/fsl-dpaa2/ethernet/net.h
diff --git a/drivers/staging/fsl-dpaa2/ethernet/dpkg.h
b/drivers/staging/fsl-dpaa2/ethernet/dpkg.h
index 099ff02..6de613b1 100644
--- a/drivers/staging/fsl-dpaa2/ethernet/dpkg.h
+++ b/drivers/staging/fsl-dpaa2/ethernet/dpkg.h
@@ -5,7 +5,6 @@
#define __FSL_DPKG_H_
#include
-#include "net.h"
/* Data Path Key Generator API
* Contains initialization APIs and runtime APIs for the Key Generator
@@ -58,6 +57,355 @@ struct dpkg_mask {
u8 offset;
};
+/* Protocol fields */
+
+/* Ethernet fields */
+#define NH_FLD_ETH_DA BIT(0)
+#define NH_FLD_ETH_SA BIT(1)
+#define NH_FLD_ETH_LENGTH BIT(2)
+#define NH_FLD_ETH_TYPEBIT(3)
+#define NH_FLD_ETH_FINAL_CKSUM BIT(4)
+#define NH_FLD_ETH_PADDING BIT(5)
+#define NH_FLD_ETH_ALL_FIELDS (BIT(6) - 1)
+
+/* VLAN fields */
+#define NH_FLD_VLAN_VPRI BIT(0)
+#define NH_FLD_VLAN_CFIBIT(1)
+#define NH_FLD_VLAN_VIDBIT(2)
+#define NH_FLD_VLAN_LENGTH BIT(3)
+#define NH_FLD_VLAN_TYPE BIT(4)
+#define NH_FLD_VLAN_ALL_FIELDS (BIT(5) - 1)
+
+#define NH_FLD_VLAN_TCI(NH_FLD_VLAN_VPRI | \
+NH_FLD_VLAN_CFI | \
+NH_FLD_VLAN_VID)
+
+/* IP (generic) fields */
+#define NH_FLD_IP_VER BIT(0)
+#define NH_FLD_IP_DSCP BIT(2)
+#define NH_FLD_IP_ECN BIT(3)
+#define NH_FLD_IP_PROTOBIT(4)
+#define NH_FLD_IP_SRC BIT(5)
+#define NH_FLD_IP_DST BIT(6)
+#define NH_FLD_IP_TOS_TC BIT(7)
+#define NH_FLD_IP_ID BIT(8)
+#define NH_FLD_IP_ALL_FIELDS (BIT(9) - 1)
+
+/* IPV4 fields */
+#define NH_FLD_IPV4_VERBIT(0)
+#define NH_FLD_IPV4_HDR_LENBIT(1)
+#define NH_FLD_IPV4_TOSBIT(2)
+#define NH_FLD_IPV4_TOTAL_LEN BIT(3)
+#define NH_FLD_IPV4_ID BIT(4)
+#define NH_FLD_IPV4_FLAG_D BIT(5)
+#define NH_FLD_IPV4_FLAG_M BIT(6)
+#define NH_FLD_IPV4_OFFSET BIT(7)
+#define NH_FLD_IPV4_TTLBIT(8)
+#define NH_FLD_IPV4_PROTO BIT(9)
+#define NH_FLD_IPV4_CKSUM BIT(10)
+#define NH_FLD_IPV4_SRC_IP BIT(11)
+#define NH_FLD_IPV4_DST_IP BIT(12)
+#define NH_FLD_IPV4_OPTS BIT(13)
+#define NH_FLD_IPV4_OPTS_COUNT BIT(14)
+#define NH_FLD_IPV4_ALL_FIELDS (BIT(15) - 1)
+
+/* IPV6 fields */
+#define NH_FLD_IPV6_VERBIT(0)
+#define NH_FLD_IPV6_TC BIT(1)
+#define NH_FLD_IPV6_SRC_IP BIT(2)
+#define NH_FLD_IPV6_DST_IP BIT(3)
+#define NH_FLD_IPV6_NEXT_HDR BIT(4)
+#define NH_FLD_IPV6_FL BIT(5)
+#define NH_FLD_IPV6_HOP_LIMIT BIT(6)
+#define NH_FLD_IPV6_ID BIT(7)
+#define NH_FLD_IPV6_ALL_FIELDS (BIT(8) - 1)
+
+/* ICMP fields */
+#define NH_FLD_ICMP_TYPE BIT(0)
+#define NH_FLD_ICMP_CODE BIT(1)
+#define NH_FLD_ICMP_CKSUM BIT(2)
+#define NH_FLD_ICMP_ID BIT(3)
+#define NH_FLD_ICMP_SQ_NUM BIT(4)
+#define NH_FLD_ICMP_ALL_FIELDS (BIT(5) - 1)
+
+/* IGMP fields */
+#define NH_FLD_IGMP_VERSIONBIT(0)
+#define NH_FLD_IGMP_TYPE BIT(1)
+#define NH_FLD_IGMP_CKSUM BIT(2)
+#define NH_FLD_IGMP_DATA BIT(3)
+#define NH_FLD_IGMP_ALL_FIELDS (BIT(4) - 1)
+
+/* TCP fields */
+#define NH_FLD_TCP_PORT_SRCBIT(0)
+#define NH_FLD_TCP_PORT_DSTBIT(1)
+#define NH_FLD_TCP_SEQ BIT(2)
+#define NH_FLD_TCP_ACK BIT(3)
+#define NH_FLD_TCP_OFFSET BIT(4)
+#define NH_FLD_TCP_FLAGS
[PATCH 3/4] staging: fsl-dpaa2/eth: Use BIT() macro
File net.h has several bitmask defines that could be implemented more clearly using the BIT() macro. Signed-off-by: Ioana Radulescu --- drivers/staging/fsl-dpaa2/ethernet/net.h | 448 +++ 1 file changed, 219 insertions(+), 229 deletions(-) diff --git a/drivers/staging/fsl-dpaa2/ethernet/net.h b/drivers/staging/fsl-dpaa2/ethernet/net.h index 2461d6e..81f5a91 100644 --- a/drivers/staging/fsl-dpaa2/ethernet/net.h +++ b/drivers/staging/fsl-dpaa2/ethernet/net.h @@ -7,307 +7,297 @@ /* Protocol fields */ /* Ethernet fields */ -#define NH_FLD_ETH_DA (1) -#define NH_FLD_ETH_SA (NH_FLD_ETH_DA << 1) -#define NH_FLD_ETH_LENGTH (NH_FLD_ETH_DA << 2) -#define NH_FLD_ETH_TYPE (NH_FLD_ETH_DA << 3) -#define NH_FLD_ETH_FINAL_CKSUM(NH_FLD_ETH_DA << 4) -#define NH_FLD_ETH_PADDING(NH_FLD_ETH_DA << 5) -#define NH_FLD_ETH_ALL_FIELDS ((NH_FLD_ETH_DA << 6) - 1) +#define NH_FLD_ETH_DA BIT(0) +#define NH_FLD_ETH_SA BIT(1) +#define NH_FLD_ETH_LENGTH BIT(2) +#define NH_FLD_ETH_TYPEBIT(3) +#define NH_FLD_ETH_FINAL_CKSUM BIT(4) +#define NH_FLD_ETH_PADDING BIT(5) +#define NH_FLD_ETH_ALL_FIELDS (BIT(6) - 1) /* VLAN fields */ -#define NH_FLD_VLAN_VPRI (1) -#define NH_FLD_VLAN_CFI (NH_FLD_VLAN_VPRI << 1) -#define NH_FLD_VLAN_VID (NH_FLD_VLAN_VPRI << 2) -#define NH_FLD_VLAN_LENGTH(NH_FLD_VLAN_VPRI << 3) -#define NH_FLD_VLAN_TYPE (NH_FLD_VLAN_VPRI << 4) -#define NH_FLD_VLAN_ALL_FIELDS((NH_FLD_VLAN_VPRI << 5) - 1) +#define NH_FLD_VLAN_VPRI BIT(0) +#define NH_FLD_VLAN_CFIBIT(1) +#define NH_FLD_VLAN_VIDBIT(2) +#define NH_FLD_VLAN_LENGTH BIT(3) +#define NH_FLD_VLAN_TYPE BIT(4) +#define NH_FLD_VLAN_ALL_FIELDS (BIT(5) - 1) -#define NH_FLD_VLAN_TCI (NH_FLD_VLAN_VPRI | \ - NH_FLD_VLAN_CFI | \ - NH_FLD_VLAN_VID) +#define NH_FLD_VLAN_TCI(NH_FLD_VLAN_VPRI | \ +NH_FLD_VLAN_CFI | \ +NH_FLD_VLAN_VID) /* IP (generic) fields */ -#define NH_FLD_IP_VER (1) -#define NH_FLD_IP_DSCP(NH_FLD_IP_VER << 2) -#define NH_FLD_IP_ECN (NH_FLD_IP_VER << 3) -#define NH_FLD_IP_PROTO (NH_FLD_IP_VER << 4) -#define NH_FLD_IP_SRC (NH_FLD_IP_VER << 5) -#define NH_FLD_IP_DST (NH_FLD_IP_VER << 6) -#define NH_FLD_IP_TOS_TC (NH_FLD_IP_VER << 7) -#define NH_FLD_IP_ID (NH_FLD_IP_VER << 8) -#define NH_FLD_IP_ALL_FIELDS ((NH_FLD_IP_VER << 9) - 1) +#define NH_FLD_IP_VER BIT(0) +#define NH_FLD_IP_DSCP BIT(2) +#define NH_FLD_IP_ECN BIT(3) +#define NH_FLD_IP_PROTOBIT(4) +#define NH_FLD_IP_SRC BIT(5) +#define NH_FLD_IP_DST BIT(6) +#define NH_FLD_IP_TOS_TC BIT(7) +#define NH_FLD_IP_ID BIT(8) +#define NH_FLD_IP_ALL_FIELDS (BIT(9) - 1) /* IPV4 fields */ -#define NH_FLD_IPV4_VER (1) -#define NH_FLD_IPV4_HDR_LEN (NH_FLD_IPV4_VER << 1) -#define NH_FLD_IPV4_TOS (NH_FLD_IPV4_VER << 2) -#define NH_FLD_IPV4_TOTAL_LEN (NH_FLD_IPV4_VER << 3) -#define NH_FLD_IPV4_ID(NH_FLD_IPV4_VER << 4) -#define NH_FLD_IPV4_FLAG_D(NH_FLD_IPV4_VER << 5) -#define NH_FLD_IPV4_FLAG_M(NH_FLD_IPV4_VER << 6) -#define NH_FLD_IPV4_OFFSET(NH_FLD_IPV4_VER << 7) -#define NH_FLD_IPV4_TTL (NH_FLD_IPV4_VER << 8) -#define NH_FLD_IPV4_PROTO (NH_FLD_IPV4_VER << 9) -#define NH_FLD_IPV4_CKSUM (NH_FLD_IPV4_VER << 10) -#define NH_FLD_IPV4_SRC_IP(NH_FLD_IPV4_VER << 11) -#define NH_FLD_IPV4_DST_IP(NH_FLD_IPV4_VER << 12) -#define NH_FLD_IPV4_OPTS (NH_FLD_IPV4_VER << 13) -#define NH_FLD_IPV4_OPTS_COUNT(NH_FLD_IPV4_VER << 14) -#define NH_FLD_IPV4_ALL_FIELDS((NH_FLD_IPV4_VER << 15) - 1) +#define NH_FLD_IPV4_VERBIT(0) +#define NH_FLD_IPV4_HDR_LEN
[PATCH 1/4] staging: fsl-dpaa2/eth: Cleanup comments
Comments in file net.h are too fancy for their own good, so convert them to the regular format. Signed-off-by: Ioana Radulescu --- drivers/staging/fsl-dpaa2/ethernet/net.h | 76 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/drivers/staging/fsl-dpaa2/ethernet/net.h b/drivers/staging/fsl-dpaa2/ethernet/net.h index 75a2d3a..ddea940 100644 --- a/drivers/staging/fsl-dpaa2/ethernet/net.h +++ b/drivers/staging/fsl-dpaa2/ethernet/net.h @@ -6,11 +6,9 @@ #define LAST_HDR_INDEX 0x -/*/ -/*Protocol fields*/ -/*/ +/* Protocol fields */ -/* Ethernet fields */ +/* Ethernet fields */ #define NH_FLD_ETH_DA (1) #define NH_FLD_ETH_SA (NH_FLD_ETH_DA << 1) #define NH_FLD_ETH_LENGTH (NH_FLD_ETH_DA << 2) @@ -21,7 +19,7 @@ #define NH_FLD_ETH_ADDR_SIZE 6 -/*** VLAN fields ***/ +/* VLAN fields */ #define NH_FLD_VLAN_VPRI (1) #define NH_FLD_VLAN_CFI (NH_FLD_VLAN_VPRI << 1) #define NH_FLD_VLAN_VID (NH_FLD_VLAN_VPRI << 2) @@ -33,7 +31,7 @@ NH_FLD_VLAN_CFI | \ NH_FLD_VLAN_VID) -/ IP (generic) fields **/ +/* IP (generic) fields */ #define NH_FLD_IP_VER (1) #define NH_FLD_IP_DSCP(NH_FLD_IP_VER << 2) #define NH_FLD_IP_ECN (NH_FLD_IP_VER << 3) @@ -46,7 +44,7 @@ #define NH_FLD_IP_PROTO_SIZE 1 -/* IPV4 fields */ +/* IPV4 fields */ #define NH_FLD_IPV4_VER (1) #define NH_FLD_IPV4_HDR_LEN (NH_FLD_IPV4_VER << 1) #define NH_FLD_IPV4_TOS (NH_FLD_IPV4_VER << 2) @@ -67,7 +65,7 @@ #define NH_FLD_IPV4_ADDR_SIZE 4 #define NH_FLD_IPV4_PROTO_SIZE1 -/* IPV6 fields */ +/* IPV6 fields */ #define NH_FLD_IPV6_VER (1) #define NH_FLD_IPV6_TC(NH_FLD_IPV6_VER << 1) #define NH_FLD_IPV6_SRC_IP(NH_FLD_IPV6_VER << 2) @@ -81,7 +79,7 @@ #define NH_FLD_IPV6_ADDR_SIZE 16 #define NH_FLD_IPV6_NEXT_HDR_SIZE 1 -/* ICMP fields */ +/* ICMP fields */ #define NH_FLD_ICMP_TYPE (1) #define NH_FLD_ICMP_CODE (NH_FLD_ICMP_TYPE << 1) #define NH_FLD_ICMP_CKSUM (NH_FLD_ICMP_TYPE << 2) @@ -92,14 +90,14 @@ #define NH_FLD_ICMP_CODE_SIZE 1 #define NH_FLD_ICMP_TYPE_SIZE 1 -/* IGMP fields */ +/* IGMP fields */ #define NH_FLD_IGMP_VERSION (1) #define NH_FLD_IGMP_TYPE (NH_FLD_IGMP_VERSION << 1) #define NH_FLD_IGMP_CKSUM (NH_FLD_IGMP_VERSION << 2) #define NH_FLD_IGMP_DATA (NH_FLD_IGMP_VERSION << 3) #define NH_FLD_IGMP_ALL_FIELDS((NH_FLD_IGMP_VERSION << 4) - 1) -/* TCP fields **/ +/* TCP fields */ #define NH_FLD_TCP_PORT_SRC (1) #define NH_FLD_TCP_PORT_DST (NH_FLD_TCP_PORT_SRC << 1) #define NH_FLD_TCP_SEQ(NH_FLD_TCP_PORT_SRC << 2) @@ -115,7 +113,7 @@ #define NH_FLD_TCP_PORT_SIZE 2 -/* UDP fields **/ +/* UDP fields */ #define NH_FLD_UDP_PORT_SRC (1) #define NH_FLD_UDP_PORT_DST (NH_FLD_UDP_PORT_SRC << 1) #define NH_FLD_UDP_LEN(NH_FLD_UDP_PORT_SRC << 2) @@ -124,7 +122,7 @@ #define NH_FLD_UDP_PORT_SIZE 2 -/*** UDP-lite fields ***/ +/* UDP-lite fields */ #define NH_FLD_UDP_LITE_PORT_SRC (1) #define NH_FLD_UDP_LITE_PORT_DST (NH_FLD_UDP_LITE_PORT_SRC << 1) #define NH_FLD_UDP_LITE_ALL_FIELDS \ @@ -132,7 +130,7 @@ #define NH_FLD_UDP_LITE_PORT_SIZE 2 -/*** UDP-encap-ESP fields **/ +/* UDP-encap-ESP fields */ #define NH_FLD_UDP_ENC_ESP_PORT_SRC (1) #define NH_FLD_UDP_ENC_ESP_PORT_DST (NH_FLD_UDP_ENC_ESP_PORT_SRC << 1) #def
[PATCH 0/4] staging: fsl-dpaa2/eth: Private header cleanup
Private header file net.h receives a cleanup and the remaining code is then merged into dpkg.h This patchset depends on: staging: fsl-dpaa2/eth: add SPDX license identifiers (https://lore.kernel.org/patchwork/patch/969402/) Ioana Radulescu (4): staging: fsl-dpaa2/eth: Cleanup comments staging: fsl-dpaa2/eth: Remove dead code staging: fsl-dpaa2/eth: Use BIT() macro staging: fsl-dpaa2/eth: Merge header files drivers/staging/fsl-dpaa2/ethernet/dpkg.h | 350 ++- drivers/staging/fsl-dpaa2/ethernet/net.h | 452 -- 2 files changed, 349 insertions(+), 453 deletions(-) delete mode 100644 drivers/staging/fsl-dpaa2/ethernet/net.h -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v8 01/15] staging: mt7621-pci: use generic kernel pci subsystem read and write
map_bus callback is called before every .read/.write operation.
Implement it and change custom read write operations for the
pci subsystem generics. Make the probe function to don't use
legacy stuff and request bus resources directly. Get pci register
base and ranges from device tree.
The driver is not using PCI_LEGACY code anymore and shall use the
PCI_DRIVERS_GENERIC option to correct compile it. Add also new
Kconfig file for this controller setting there its correct dependencies.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/Kconfig | 2 +
drivers/staging/mt7621-pci/Kconfig | 7 +
drivers/staging/mt7621-pci/pci-mt7621.c | 235 +---
3 files changed, 227 insertions(+), 17 deletions(-)
create mode 100644 drivers/staging/mt7621-pci/Kconfig
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index 2bce647..732b631 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -110,6 +110,8 @@ source "drivers/staging/vboxvideo/Kconfig"
source "drivers/staging/pi433/Kconfig"
+source "drivers/staging/mt7621-pci/Kconfig"
+
source "drivers/staging/mt7621-pinctrl/Kconfig"
source "drivers/staging/mt7621-spi/Kconfig"
diff --git a/drivers/staging/mt7621-pci/Kconfig
b/drivers/staging/mt7621-pci/Kconfig
new file mode 100644
index 000..d335338
--- /dev/null
+++ b/drivers/staging/mt7621-pci/Kconfig
@@ -0,0 +1,7 @@
+config PCI_MT7621
+ tristate "MediaTek MT7621 PCI Controller"
+ depends on RALINK
+ select PCI_DRIVERS_GENERIC
+ help
+ This selects a driver for the MediaTek MT7621 PCI Controller.
+
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 650e49b..0d70a4c 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -53,11 +53,16 @@
#include
#include
#include
+#include
+#include
+#include
#include
#include
#include
+#include "../../pci/pci.h"
+
/*
* These functions and structures provide the BIOS scan and mapping of the PCI
* devices.
@@ -178,6 +183,45 @@ static int pcie_link_status = 0;
#define PCI_ACCESS_WRITE_2 4
#define PCI_ACCESS_WRITE_4 5
+/**
+ * struct mt7621_pcie_port - PCIe port information
+ * @base: IO mapped register base
+ * @list: port list
+ * @pcie: pointer to PCIe host info
+ * @reset: pointer to port reset control
+ */
+struct mt7621_pcie_port {
+ void __iomem *base;
+ struct list_head list;
+ struct mt7621_pcie *pcie;
+ struct reset_control *reset;
+};
+
+/**
+ * struct mt7621_pcie - PCIe host information
+ * @base: IO Mapped Register Base
+ * @dev: Pointer to PCIe device
+ * @io: IO resource
+ * @pio: PIO resource
+ * @mem: non-prefetchable memory resource
+ * @busn: bus range
+ * @offset: IO / Memory offset
+ * @ports: pointer to PCIe port information
+ */
+struct mt7621_pcie {
+ void __iomem *base;
+ struct device *dev;
+ struct resource io;
+ struct resource pio;
+ struct resource mem;
+ struct resource busn;
+ struct {
+ resource_size_t mem;
+ resource_size_t io;
+ } offset;
+ struct list_head ports;
+};
+
static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
unsigned int func, unsigned int where)
{
@@ -297,17 +341,22 @@ pci_config_write(struct pci_bus *bus, unsigned int devfn,
int where, int size, u
}
}
-struct pci_ops mt7621_pci_ops = {
- .read = pci_config_read,
- .write = pci_config_write,
-};
+static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
+unsigned int devfn, int where)
+{
+ struct mt7621_pcie *pcie = bus->sysdata;
+ u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+PCI_FUNC(devfn), where);
+
+ writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
+
+ return pcie->base + RALINK_PCI_CONFIG_DATA_VIRTUAL_REG + (where & 3);
+}
-static struct resource mt7621_res_pci_mem1;
-static struct resource mt7621_res_pci_io1;
-static struct pci_controller mt7621_controller = {
- .pci_ops= &mt7621_pci_ops,
- .mem_resource = &mt7621_res_pci_mem1,
- .io_resource= &mt7621_res_pci_io1,
+struct pci_ops mt7621_pci_ops = {
+ .map_bus= mt7621_pcie_map_bus,
+ .read = pci_generic_config_read,
+ .write = pci_generic_config_write,
};
static void
@@ -463,9 +512,10 @@ set_phy_for_ssc(void)
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1,
0x00); // rg_pe1_frc_phy_en//Force Port 0 disable control
}
-void setup_cm_memory_region(struct resource *mem_resource)
+static void setup_cm_memory_region(struct resource *mem_resource)
{
resource_size_t mask;
+
if (mips_cps_numiocu(0)) {
[PATCH v8 02/15] staging: mt7621-pci: remove dead code derived to not use custom reads and writes
Driver is using now pci subsystem generics reads and writes and requesting
bus resources without using legacy code functions. Because of this there is
a lot of dead code that can be removed.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 128
1 file changed, 128 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 0d70a4c..807bca7 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -123,15 +123,6 @@
*(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
#define MV_READ(ofs, data) \
*(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
-#define MV_WRITE_16(ofs, data) \
- *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
-#define MV_READ_16(ofs, data) \
- *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
-
-#define MV_WRITE_8(ofs, data) \
- *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
-#define MV_READ_8(ofs, data) \
- *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
#define RALINK_PCI_MM_MAP_BASE 0x6000
#define RALINK_PCI_IO_MAP_BASE 0x1e16
@@ -176,13 +167,6 @@
#define MEMORY_BASE 0x0
static int pcie_link_status = 0;
-#define PCI_ACCESS_READ_1 0
-#define PCI_ACCESS_READ_2 1
-#define PCI_ACCESS_READ_4 2
-#define PCI_ACCESS_WRITE_1 3
-#define PCI_ACCESS_WRITE_2 4
-#define PCI_ACCESS_WRITE_4 5
-
/**
* struct mt7621_pcie_port - PCIe port information
* @base: IO mapped register base
@@ -229,118 +213,6 @@ static inline u32 mt7621_pci_get_cfgaddr(unsigned int
bus, unsigned int slot,
(func << 8) | (where & 0xfc) | 0x8000;
}
-static int config_access(unsigned char access_type, struct pci_bus *bus,
- unsigned int devfn, unsigned int where, u32 *data)
-{
- unsigned int slot = PCI_SLOT(devfn);
- u8 func = PCI_FUNC(devfn);
- u32 address_reg, data_reg;
- unsigned int address;
-
- address_reg = RALINK_PCI_CONFIG_ADDR;
- data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
-
- address = mt7621_pci_get_cfgaddr(bus->number, slot, func, where);
-
- MV_WRITE(address_reg, address);
-
- switch (access_type) {
- case PCI_ACCESS_WRITE_1:
- MV_WRITE_8(data_reg+(where&0x3), *data);
- break;
- case PCI_ACCESS_WRITE_2:
- MV_WRITE_16(data_reg+(where&0x3), *data);
- break;
- case PCI_ACCESS_WRITE_4:
- MV_WRITE(data_reg, *data);
- break;
- case PCI_ACCESS_READ_1:
- MV_READ_8(data_reg+(where&0x3), data);
- break;
- case PCI_ACCESS_READ_2:
- MV_READ_16(data_reg+(where&0x3), data);
- break;
- case PCI_ACCESS_READ_4:
- MV_READ(data_reg, data);
- break;
- default:
- printk("no specify access type\n");
- break;
- }
- return 0;
-}
-
-static int
-read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 *val)
-{
- return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned
int)where, (u32 *)val);
-}
-
-static int
-read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 *val)
-{
- return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned
int)where, (u32 *)val);
-}
-
-static int
-read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 *val)
-{
- return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned
int)where, (u32 *)val);
-}
-
-static int
-write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
-{
- if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where,
(u32 *)&val))
- return -1;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
-{
- if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
- return -1;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
-{
- if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
- return -1;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size,
u32 *val)
-{
- switch (size) {
- case 1:
- return read_config_byte(bus, devfn, where, (u8 *) val);
- case 2:
- return read_config_word(bus, devfn, where, (u16 *) val);
- default:
- return read_config_dword(bus, devfn, where, val);
- }
-}
-
-static int
-pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size,
u32 val)
-{
- switch (size) {
- case 1:
- return write_con
[PATCH v8 03/15] staging: mt7621-pci: add pcie_write and pcie_read helpers
Introdice this functions to make easier to write/read to/from
an offset relative to base address
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 807bca7..cd25850 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -206,6 +206,16 @@ struct mt7621_pcie {
struct list_head ports;
};
+static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
+{
+ return readl(pcie->base + reg);
+}
+
+static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
+{
+ writel(val, pcie->base + reg);
+}
+
static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
unsigned int func, unsigned int where)
{
--
2.7.4
___
devel mailing list
de...@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v8 06/15] staging: mt7621-pci: simplify write_config function
write_config function is always called with bus and func
being 0. Avoid those params and just use 0 inside the
function. Review parameter types changing for more proper
ones.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 927e707..ccfbf06 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -251,11 +251,9 @@ read_config(struct mt7621_pcie *pcie, unsigned int dev,
u32 reg)
}
static void
-write_config(struct mt7621_pcie *pcie,
-unsigned long bus, unsigned long dev,
-unsigned long func, unsigned long reg, unsigned long val)
+write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val)
{
- u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+ u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
@@ -270,7 +268,7 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
int irq;
if (dev->bus->number == 0) {
- write_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
+ write_config(pcie, slot, PCI_BASE_ADDRESS_0, MEMORY_BASE);
val = read_config(pcie, slot, PCI_BASE_ADDRESS_0);
printk("BAR0 at slot %d = %x\n", slot, val);
}
@@ -706,27 +704,27 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
switch (pcie_link_status) {
case 7:
val = read_config(pcie, 2, 0x4);
- write_config(pcie, 0, 2, 0, 0x4, val|0x4);
+ write_config(pcie, 2, 0x4, val|0x4);
val = read_config(pcie, 2, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
- write_config(pcie, 0, 2, 0, 0x70c, val);
+ write_config(pcie, 2, 0x70c, val);
case 3:
case 5:
case 6:
val = read_config(pcie, 1, 0x4);
- write_config(pcie, 0, 1, 0, 0x4, val|0x4);
+ write_config(pcie, 1, 0x4, val|0x4);
val = read_config(pcie, 1, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
- write_config(pcie, 0, 1, 0, 0x70c, val);
+ write_config(pcie, 1, 0x70c, val);
default:
val = read_config(pcie, 0, 0x4);
- write_config(pcie, 0, 0, 0, 0x4, val|0x4); //bus master enable
+ write_config(pcie, 0, 0x4, val|0x4); //bus master enable
val = read_config(pcie, 0, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
- write_config(pcie, 0, 0, 0, 0x70c, val);
+ write_config(pcie, 0, 0x70c, val);
}
err = mt7621_pci_parse_request_of_pci_ranges(pcie);
--
2.7.4
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[PATCH v8 04/15] staging: mt7621-pci: use pcie_[read|write] in [write|read]_config
Instead of custom macros use pcie_read and pcie_write functions.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 67 -
1 file changed, 32 insertions(+), 35 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index cd25850..ee15f35 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -242,41 +242,38 @@ struct pci_ops mt7621_pci_ops = {
};
static void
-read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned
long reg, unsigned long *val)
+read_config(struct mt7621_pcie *pcie,
+ unsigned long bus, unsigned long dev,
+ unsigned long func, unsigned long reg, unsigned long *val)
{
- u32 address_reg, data_reg, address;
-
- address_reg = RALINK_PCI_CONFIG_ADDR;
- data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
- address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
- MV_WRITE(address_reg, address);
- MV_READ(data_reg, val);
- return;
+ u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+
+ pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
+ *val = pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
}
static void
-write_config(unsigned long bus, unsigned long dev, unsigned long func,
unsigned long reg, unsigned long val)
+write_config(struct mt7621_pcie *pcie,
+unsigned long bus, unsigned long dev,
+unsigned long func, unsigned long reg, unsigned long val)
{
- u32 address_reg, data_reg, address;
-
- address_reg = RALINK_PCI_CONFIG_ADDR;
- data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
- address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
- MV_WRITE(address_reg, address);
- MV_WRITE(data_reg, val);
- return;
+ u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+
+ pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
+ pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
}
int
pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
+ struct mt7621_pcie *pcie = dev->bus->sysdata;
u16 cmd;
u32 val;
int irq;
if (dev->bus->number == 0) {
- write_config(0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
- read_config(0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long
*)&val);
+ write_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
+ read_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned
long *)&val);
printk("BAR0 at slot %d = %x\n", slot, val);
}
@@ -583,13 +580,13 @@ static int mt7621_pci_probe(struct platform_device *pdev)
bypass_pipe_rst();
set_phy_for_ssc();
- read_config(0, 0, 0, 0x70c, &val);
+ read_config(pcie, 0, 0, 0, 0x70c, &val);
printk("Port 0 N_FTS = %x\n", (unsigned int)val);
- read_config(0, 1, 0, 0x70c, &val);
+ read_config(pcie, 0, 1, 0, 0x70c, &val);
printk("Port 1 N_FTS = %x\n", (unsigned int)val);
- read_config(0, 2, 0, 0x70c, &val);
+ read_config(pcie, 0, 2, 0, 0x70c, &val);
printk("Port 2 N_FTS = %x\n", (unsigned int)val);
rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
@@ -710,28 +707,28 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
switch (pcie_link_status) {
case 7:
- read_config(0, 2, 0, 0x4, &val);
- write_config(0, 2, 0, 0x4, val|0x4);
- read_config(0, 2, 0, 0x70c, &val);
+ read_config(pcie, 0, 2, 0, 0x4, &val);
+ write_config(pcie, 0, 2, 0, 0x4, val|0x4);
+ read_config(pcie, 0, 2, 0, 0x70c, &val);
val &= ~(0xff)<<8;
val |= 0x50<<8;
- write_config(0, 2, 0, 0x70c, val);
+ write_config(pcie, 0, 2, 0, 0x70c, val);
case 3:
case 5:
case 6:
- read_config(0, 1, 0, 0x4, &val);
- write_config(0, 1, 0, 0x4, val|0x4);
- read_config(0, 1, 0, 0x70c, &val);
+ read_config(pcie, 0, 1, 0, 0x4, &val);
+ write_config(pcie, 0, 1, 0, 0x4, val|0x4);
+ read_config(pcie, 0, 1, 0, 0x70c, &val);
val &= ~(0xff)<<8;
val |= 0x50<<8;
- write_config(0, 1, 0, 0x70c, val);
+ write_config(pcie, 0, 1, 0, 0x70c, val);
default:
- read_config(0, 0, 0, 0x4, &val);
- write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
- read_config(0, 0, 0, 0x70c, &val);
+ read_config(pcie, 0, 0, 0, 0x4, &val);
+ write_config(pcie, 0, 0, 0, 0x4, val|0x4); //bus master enable
+ read_config(pcie, 0, 0, 0, 0x70c, &val);
val &= ~(0xff)<<8;
val |= 0x5
[PATCH v8 05/15] staging: mt7621-pci: simplify read_config function
read_config function is always called with bus and func
being 0. Avoid those params and just use 0 inside the
function. Return readed value instead pass a reference
parameter.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 32 +++-
1 file changed, 15 insertions(+), 17 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index ee15f35..927e707 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -241,15 +241,13 @@ struct pci_ops mt7621_pci_ops = {
.write = pci_generic_config_write,
};
-static void
-read_config(struct mt7621_pcie *pcie,
- unsigned long bus, unsigned long dev,
- unsigned long func, unsigned long reg, unsigned long *val)
+static u32
+read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
{
- u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+ u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
- *val = pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
+ return pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
}
static void
@@ -273,7 +271,7 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
if (dev->bus->number == 0) {
write_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
- read_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned
long *)&val);
+ val = read_config(pcie, slot, PCI_BASE_ADDRESS_0);
printk("BAR0 at slot %d = %x\n", slot, val);
}
@@ -529,7 +527,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
struct mt7621_pcie *pcie;
struct pci_host_bridge *bridge;
int err;
- unsigned long val = 0;
+ u32 val = 0;
if (!dev->of_node)
return -ENODEV;
@@ -580,13 +578,13 @@ static int mt7621_pci_probe(struct platform_device *pdev)
bypass_pipe_rst();
set_phy_for_ssc();
- read_config(pcie, 0, 0, 0, 0x70c, &val);
+ val = read_config(pcie, 0, 0x70c);
printk("Port 0 N_FTS = %x\n", (unsigned int)val);
- read_config(pcie, 0, 1, 0, 0x70c, &val);
+ val = read_config(pcie, 1, 0x70c);
printk("Port 1 N_FTS = %x\n", (unsigned int)val);
- read_config(pcie, 0, 2, 0, 0x70c, &val);
+ val = read_config(pcie, 2, 0x70c);
printk("Port 2 N_FTS = %x\n", (unsigned int)val);
rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
@@ -707,25 +705,25 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
switch (pcie_link_status) {
case 7:
- read_config(pcie, 0, 2, 0, 0x4, &val);
+ val = read_config(pcie, 2, 0x4);
write_config(pcie, 0, 2, 0, 0x4, val|0x4);
- read_config(pcie, 0, 2, 0, 0x70c, &val);
+ val = read_config(pcie, 2, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
write_config(pcie, 0, 2, 0, 0x70c, val);
case 3:
case 5:
case 6:
- read_config(pcie, 0, 1, 0, 0x4, &val);
+ val = read_config(pcie, 1, 0x4);
write_config(pcie, 0, 1, 0, 0x4, val|0x4);
- read_config(pcie, 0, 1, 0, 0x70c, &val);
+ val = read_config(pcie, 1, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
write_config(pcie, 0, 1, 0, 0x70c, val);
default:
- read_config(pcie, 0, 0, 0, 0x4, &val);
+ val = read_config(pcie, 0, 0x4);
write_config(pcie, 0, 0, 0, 0x4, val|0x4); //bus master enable
- read_config(pcie, 0, 0, 0, 0x70c, &val);
+ val = read_config(pcie, 0, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
write_config(pcie, 0, 0, 0, 0x70c, val);
--
2.7.4
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[PATCH v8 00/15] staging: mt7621-pci: avoid custom pci config read and writes
This patch series include an attempt to avoid the use of custom read and writes in driver code and use PCI subsystem common ones. In order to do this 'map_bus' callback is implemented and also data structures for driver are included. The regs base address ranges and data is being readed from device tree and the driver gets clean a lot of code. This patchet also removes all legacy PCI code using now PCI_DRIVERS_GENERIC kernel api. Changes in v8: - PATCH 1: don't check 'of_pci_range_to_resource' return value which is not being checked for the legacy code. - PATCH 1: call 'mt7621_pci_parse_request_of_pci_ranges' 'and setup_cm_memory_region' after the port initialization code. - PATCH 1: make use of 'pci_host_probe' to avoid code duplication in function 'mt7621_pcie_register_host'. - PATCH 1: set resource limits with no limit for the end in 'ioport_resource' and 'iomem_resource'. It seems mips needs this to work properly. - Other patches rebased and adapted to this changes. Changes in v7: - PATCH 1: Store resources in mt7621_pci data structure. - PATCH 1: Change completely function mt7621_pci_parse_request_of_pci_ranges to parse resources from ranges manually instead of use the function devm_of_pci_get_host_bridge_resources. This is closer to the mips pci legacy code. - PATCH 1: Create 'mt7621_pcie_request_resources' function to request resources parsed from ranges property in the DT. Use pci_add_resource_offset and set them manually like the mips pci-legacy code do. - PATCH 1: don't delete function setup_cm_memory_region and call it with memory resource. - Other patches rebased and adapted to this changes. Changes in v6: - Reorder patches to be each patch correct in itself. - PATCH 1 adds also Kconfig to do the step from legacy to generic code - PATCH 1 remaps io space using devm_pci_remap_iospace for io resource in a new function called 'mt7621_pci_parse_request_of_pci_ranges'. - Other patches rebased and adapted with this changes. Changes in v5: - Include driver Kconfig file to add compilation depends of PCI_DRIVERS_GENERIC. The new added configuration option is CONFIG_PCI_MT7621. - Add list_splice_init(&res, &bridge->windows); in PATCH 1 to set windows from resources obtanined from devm_request_pci_bus_resources. - Move devm_of_pci_get_host_bridge_resources and devm_request_pci_bus_resources after the ports initialization legacy code. - Add pcie ports 1 and 2 RC registers to device tree. There was only being included port RC register for port 0. - Review includes and order them alphabetically. Changes in v4: - Rebased onto staging-next. Changes in v3: - Include new patches to delete all RALINK_BASE definition dependant code and be able to avoid use of pci_legacy code. - use devm_of_pci_get_host_bridge_resources, devm_request_pci_bus_resources and pci_scan_root_bus_bridge and pci_bus_add_devices Changes in v2: - squash PATCH 1 and PATCH 2 of previous series in only PATCH 1 - Change name for host structure. - Create a new port structure (platform has 3 pcie controllers) - Replace the use of pci_generic_config_[read|write]32 in favour of pci_generic_config_[read|write] and change map_bus implemen- tation for hopefully the right one. Best regards, Sergio Paracuellos Sergio Paracuellos (15): staging: mt7621-pci: use generic kernel pci subsystem read and write staging: mt7621-pci: remove dead code derived to not use custom reads and writes staging: mt7621-pci: add pcie_write and pcie_read helpers staging: mt7621-pci: use pcie_[read|write] in [write|read]_config staging: mt7621-pci: simplify read_config function staging: mt7621-pci: simplify write_config function staging: mt7621-pci: remove unused macros staging: mt7621-pci: avoid register duplication per controller using pcie_[read|write] staging: mt7621-pci: review includes putting them in alphabethic order staging: mt7621-pci: use pcie_[read|write] in RALINK_PCI_PCICFG_ADDR and RALINK_PCI_PCIMSK_ADDR staging: mt7621-pci: remove RALINK_PCI_BASE from remaining definitions staging: mt7621-pci: use BIT macro in preprocessor definitions staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG definition staging: mt7621-pci: remove remaining pci_legacy dependant code staging: mt7621-dts: add pcie controller port registers drivers/staging/Kconfig | 2 + drivers/staging/mt7621-dts/mt7621.dtsi | 6 +- drivers/staging/mt7621-pci/Kconfig | 7 + drivers/staging/mt7621-pci/pci-mt7621.c | 766 +--- 4 files changed, 412 insertions(+), 369 deletions(-) create mode 100644 drivers/staging/mt7621-pci/Kconfig -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://dri
[PATCH v8 15/15] staging: mt7621-dts: add pcie controller port registers
The pcie node of the device tree only contains registers
for the host-bridge and pcie port 0. Add the pcie port 1
and pcie port 2 also.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-dts/mt7621.dtsi | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 4610403..2e837e6 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -394,8 +394,10 @@
pcie: pcie@1e14 {
compatible = "mediatek,mt7621-pci";
- reg = <0x1e14 0x100
- 0x1e142000 0x100>;
+ reg = <0x1e14 0x100 /* host-pci bridge registers */
+ 0x1e142000 0x100/* pcie port 0 RC control registers
*/
+ 0x1e143000 0x100/* pcie port 1 RC control registers
*/
+ 0x1e144000 0x100>; /* pcie port 2 RC control registers
*/
#address-cells = <3>;
#size-cells = <2>;
--
2.7.4
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[PATCH v8 10/15] staging: mt7621-pci: use pcie_[read|write] in RALINK_PCI_PCICFG_ADDR and RALINK_PCI_PCIMSK_ADDR
RALINK_PCI_PCICFG_ADDR and RALINK_PCI_PCIMSK_ADDR are defined to be directly
referenced for read and write. Use pcie_read and pcie_write instead changing
its definition to a simple relative offset to pcie base address.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 54 +
1 file changed, 34 insertions(+), 20 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 1344291..0d4c07f 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -74,8 +74,8 @@
#define RALINK_PCIE1_RST (1<<25)
#define RALINK_PCIE2_RST (1<<26)
-#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE +
0x)
-#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE +
0x000C)
+#define RALINK_PCI_PCICFG_ADDR 0x
+#define RALINK_PCI_PCIMSK_ADDR 0x000C
#define RALINK_PCI_BASE0xBE14
#define RT6855_PCIE0_OFFSET0x2000
@@ -564,7 +564,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
pcie_link_status &= ~(1<<0);
} else {
pcie_link_status |= 1<<0;
- RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
+ val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+ val |= (1<<20); // enable pcie1 interrupt
+ pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
}
if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
@@ -574,7 +576,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
pcie_link_status &= ~(1<<1);
} else {
pcie_link_status |= 1<<1;
- RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
+ val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+ val |= (1<<21); // enable pcie1 interrupt
+ pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
}
if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
@@ -584,7 +588,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
pcie_link_status &= ~(1<<2);
} else {
pcie_link_status |= 1<<2;
- RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
+ val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+ val |= (1<<22); // enable pcie2 interrupt
+ pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
}
if (pcie_link_status == 0)
@@ -603,27 +609,35 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
*/
switch (pcie_link_status) {
case 2:
- RALINK_PCI_PCICFG_ADDR &= ~0x00ff;
- RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;//port0
- RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;//port1
+ val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+ val &= ~0x00ff;
+ val |= 0x1 << 16; // port 0
+ val |= 0x0 << 20; // port 1
+ pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
break;
case 4:
- RALINK_PCI_PCICFG_ADDR &= ~0x0fff;
- RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;//port0
- RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;//port1
- RALINK_PCI_PCICFG_ADDR |= 0x0 << 24;//port2
+ val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+ val &= ~0x0fff;
+ val |= 0x1 << 16; //port0
+ val |= 0x2 << 20; //port1
+ val |= 0x0 << 24; //port2
+ pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
break;
case 5:
- RALINK_PCI_PCICFG_ADDR &= ~0x0fff;
- RALINK_PCI_PCICFG_ADDR |= 0x0 << 16;//port0
- RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;//port1
- RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;//port2
+ val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+ val &= ~0x0fff;
+ val |= 0x0 << 16; //port0
+ val |= 0x2 << 20; //port1
+ val |= 0x1 << 24; //port2
+ pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
break;
case 6:
- RALINK_PCI_PCICFG_ADDR &= ~0x0fff;
- RALINK_PCI_PCICFG_ADDR |= 0x2 << 16;//port0
- RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;//port1
- RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;//port2
+ val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+ val &= ~0x0fff;
+ val |= 0x2 << 16; //port0
+ val |= 0x0 << 20; //port1
+ val |= 0x1 << 24; //port2
+ pcie_write(pcie, val, RAL
[PATCH v8 12/15] staging: mt7621-pci: use BIT macro in preprocessor definitions
Some preprocessor definitions are using a custom implementation of BIT macro. Just use linux kernel BIT macro instead. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 38f7574..371408d 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -62,17 +62,17 @@ * devices. */ -#define RALINK_PCIE0_CLK_EN(1<<24) -#define RALINK_PCIE1_CLK_EN(1<<25) -#define RALINK_PCIE2_CLK_EN(1<<26) +#define RALINK_PCIE0_CLK_ENBIT(24) +#define RALINK_PCIE1_CLK_ENBIT(25) +#define RALINK_PCIE2_CLK_ENBIT(26) #define RALINK_PCI_CONFIG_ADDR 0x20 #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24 #define RALINK_PCI_MEMBASE 0x28 #define RALINK_PCI_IOBASE 0x2C -#define RALINK_PCIE0_RST (1<<24) -#define RALINK_PCIE1_RST (1<<25) -#define RALINK_PCIE2_RST (1<<26) +#define RALINK_PCIE0_RST BIT(24) +#define RALINK_PCIE1_RST BIT(25) +#define RALINK_PCIE2_RST BIT(26) #define RALINK_PCI_PCICFG_ADDR 0x #define RALINK_PCI_PCIMSK_ADDR 0x000C @@ -115,11 +115,11 @@ #define RALINK_PCIE_CLK_GEN0x7c #define RALINK_PCIE_CLK_GEN1 0x80 //RALINK_RSTCTRL bit -#define RALINK_PCIE_RST(1<<23) -#define RALINK_PCI_RST (1<<24) +#define RALINK_PCIE_RSTBIT(23) +#define RALINK_PCI_RST BIT(24) //RALINK_CLKCFG1 bit -#define RALINK_PCI_CLK_EN (1<<19) -#define RALINK_PCIE_CLK_EN (1<<21) +#define RALINK_PCI_CLK_EN BIT(19) +#define RALINK_PCIE_CLK_EN BIT(21) #define MEMORY_BASE 0x0 static int pcie_link_status = 0; -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v8 13/15] staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG definition
RALINK_PCI_CONFIG_DATA_VIRTUAL_REG is a very long name. Make it a bit
shorter renaming it to RALINK_PCI_CONFIG_DATA.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 371408d..39816a2 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -67,7 +67,7 @@
#define RALINK_PCIE2_CLK_ENBIT(26)
#define RALINK_PCI_CONFIG_ADDR 0x20
-#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
+#define RALINK_PCI_CONFIG_DATA 0x24
#define RALINK_PCI_MEMBASE 0x28
#define RALINK_PCI_IOBASE 0x2C
#define RALINK_PCIE0_RST BIT(24)
@@ -189,7 +189,7 @@ static void __iomem *mt7621_pcie_map_bus(struct pci_bus
*bus,
writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
- return pcie->base + RALINK_PCI_CONFIG_DATA_VIRTUAL_REG + (where & 3);
+ return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
}
struct pci_ops mt7621_pci_ops = {
@@ -204,7 +204,7 @@ read_config(struct mt7621_pcie *pcie, unsigned int dev, u32
reg)
u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
- return pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
+ return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
}
static void
@@ -213,7 +213,7 @@ write_config(struct mt7621_pcie *pcie, unsigned int dev,
u32 reg, u32 val)
u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
- pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
+ pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
}
int
--
2.7.4
___
devel mailing list
de...@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v8 14/15] staging: mt7621-pci: remove remaining pci_legacy dependant code
pcibios_* remaining code is not neccessary at all. We can use
map_irq set to of_irq_parse_and_map_pci driver 'probe' function.
Remove this code.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 33 +
1 file changed, 1 insertion(+), 32 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 39816a2..0cfb3ca 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -216,32 +216,6 @@ write_config(struct mt7621_pcie *pcie, unsigned int dev,
u32 reg, u32 val)
pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
}
-int
-pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- struct mt7621_pcie *pcie = dev->bus->sysdata;
- u16 cmd;
- u32 val;
- int irq;
-
- if (dev->bus->number == 0) {
- write_config(pcie, slot, PCI_BASE_ADDRESS_0, MEMORY_BASE);
- val = read_config(pcie, slot, PCI_BASE_ADDRESS_0);
- printk("BAR0 at slot %d = %x\n", slot, val);
- }
-
- pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure
cache line size 0x14
- pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure
latency timer 0x10
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
- pci_write_config_word(dev, PCI_COMMAND, cmd);
-
- irq = of_irq_parse_and_map_pci(dev, slot, pin);
-
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
- return irq;
-}
-
void
set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
int start_b, int bits, int val)
@@ -473,7 +447,7 @@ static int mt7621_pcie_register_host(struct pci_host_bridge
*host)
host->busnr = pcie->busn.start;
host->dev.parent = pcie->dev;
host->ops = &mt7621_pci_ops;
- host->map_irq = pcibios_map_irq;
+ host->map_irq = of_irq_parse_and_map_pci;
host->swizzle_irq = pci_common_swizzle;
host->sysdata = pcie;
@@ -735,11 +709,6 @@ pcie(2/1/0) link statuspcie2_num pcie1_num
pcie0_num
return 0;
}
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
-
static const struct of_device_id mt7621_pci_ids[] = {
{ .compatible = "mediatek,mt7621-pci" },
{},
--
2.7.4
___
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[PATCH v8 11/15] staging: mt7621-pci: remove RALINK_PCI_BASE from remaining definitions
RALINK_PCI_BASE has no sense and this driver has base address readed
and mapped from device tree. Remove remaining uses of it and
change code to use pcie_read and pcie_write functions in places
where this was being used.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 131
1 file changed, 67 insertions(+), 64 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 0d4c07f..38f7574 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -76,7 +76,6 @@
#define RALINK_PCI_PCICFG_ADDR 0x
#define RALINK_PCI_PCIMSK_ADDR 0x000C
-#define RALINK_PCI_BASE0xBE14
#define RT6855_PCIE0_OFFSET0x2000
#define RT6855_PCIE1_OFFSET0x3000
@@ -89,8 +88,8 @@
#define RALINK_PCI_SUBID 0x0038
#define RALINK_PCI_STATUS 0x0050
-#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
-#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
+#define RALINK_PCIEPHY_P0P1_CTL_OFFSET 0x9000
+#define RALINK_PCIEPHY_P2_CTL_OFFSET 0xA000
#define RALINK_PCI_MM_MAP_BASE 0x6000
#define RALINK_PCI_IO_MAP_BASE 0x1e16
@@ -244,105 +243,109 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8
pin)
}
void
-set_pcie_phy(u32 *addr, int start_b, int bits, int val)
+set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
+int start_b, int bits, int val)
{
- *(unsigned int *)(addr) &= ~(((1<> 6) & 0x7;
/* Set PCIe Port0 & Port1 PHY to disable SSC */
/* Debug Xtal Type */
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1,
0x01); // rg_pe1_frc_h_xtal_type
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2,
0x00); // rg_pe1_h_xtal_type
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1,
0x01); // rg_pe1_frc_phy_en//Force Port 0 enable control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1,
0x01); // rg_pe1_frc_phy_en//Force Port 1 enable control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1,
0x00); // rg_pe1_phy_en//Port 0 disable
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1,
0x00); // rg_pe1_phy_en//Port 1 disable
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1,
0x01); // rg_pe1_frc_h_xtal_type
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2,
0x00); // rg_pe1_h_xtal_type
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1,
0x01); // rg_pe1_frc_phy_en//Force Port 0 enable control
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1,
0x01); // rg_pe1_frc_phy_en//Force Port 1 enable control
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1,
0x00); // rg_pe1_phy_en//Port 0 disable
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1,
0x00); // rg_pe1_phy_en//Port 1 disable
if (reg <= 5 && reg >= 3) { // 40MHz Xtal
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),
6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),
6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
printk("* Xtal 40MHz *\n");
} else {// 25MHz | 20MHz Xtal
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),
6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),
6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
if (reg >= 6) {
printk("* Xtal 25MHz *\n");
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x49c), 0, 31, 0x1800); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO
PCW (for host mode)
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x4a4), 0, 16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither
period control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x4a8), 0, 12, 0x4a);// RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither
amplitude control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x4a8), 16, 12, 0x4a);// RG_PE1_H_LCDDS_SSC_DELTA1//DDS SSC dither
amplitude control for initial
+
[PATCH v8 07/15] staging: mt7621-pci: remove unused macros
There some macros that are not being used. Remove them. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 24 +--- 1 file changed, 1 insertion(+), 23 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index ccfbf06..7b39fc3 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -84,7 +84,6 @@ #define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C) #define RALINK_PCI_BASE0xBE14 -#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000) #define RT6855_PCIE0_OFFSET0x2000 #define RT6855_PCIE1_OFFSET0x3000 #define RT6855_PCIE2_OFFSET0x4000 @@ -95,8 +94,6 @@ #define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034) #define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038) #define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050) -#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060) -#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064) #define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010) #define RALINK_PCI1_IMBASEBAR0_ADDR*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018) @@ -104,8 +101,6 @@ #define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034) #define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038) #define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050) -#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060) -#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064) #define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010) #define RALINK_PCI2_IMBASEBAR0_ADDR*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018) @@ -113,17 +108,10 @@ #define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034) #define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038) #define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050) -#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060) -#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064) #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000) #define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000) -#define MV_WRITE(ofs, data)\ - *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data) -#define MV_READ(ofs, data) \ - *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs))) - #define RALINK_PCI_MM_MAP_BASE 0x6000 #define RALINK_PCI_IO_MAP_BASE 0x1e16 @@ -141,28 +129,18 @@ else\ rt_sysc_m32(0, val, RALINK_RSTCTRL);\ } while (0) + #define RALINK_CLKCFG1 0x30 #define RALINK_RSTCTRL 0x34 #define RALINK_GPIOMODE0x60 #define RALINK_PCIE_CLK_GEN0x7c #define RALINK_PCIE_CLK_GEN1 0x80 -#define PPLL_CFG1 0x9c -#define PPLL_DRV 0xa0 -/* SYSC_REG_SYSTEM_CONFIG1 bits */ -#define RALINK_PCI_HOST_MODE_EN(1<<7) -#define RALINK_PCIE_RC_MODE_EN (1<<8) //RALINK_RSTCTRL bit #define RALINK_PCIE_RST(1<<23) #define RALINK_PCI_RST (1<<24) //RALINK_CLKCFG1 bit #define RALINK_PCI_CLK_EN (1<<19) #define RALINK_PCIE_CLK_EN (1<<21) -//RALINK_GPIOMODE bit -#define PCI_SLOTx2 (1<<11) -#define PCI_SLOTx1 (2<<11) -//MTK PCIE PLL bit -#define PDRV_SW_SET(1<<31) -#define LC_CKDRVPD_(1<<19) #define MEMORY_BASE 0x0 static int pcie_link_status = 0; -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v8 08/15] staging: mt7621-pci: avoid register duplication per controller using pcie_[read|write]
Use pcie_[read|write] fucntions to read and write controller registers.
Define those only by offset and pass controller offset + register offset
relative to base address to functions.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 70 -
1 file changed, 34 insertions(+), 36 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 7b39fc3..e9f6b23 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -74,8 +74,8 @@
#define RALINK_PCI_CONFIG_ADDR 0x20
#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
-#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE +
0x0028)
-#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE +
0x002C)
+#define RALINK_PCI_MEMBASE 0x28
+#define RALINK_PCI_IOBASE 0x2C
#define RALINK_PCIE0_RST (1<<24)
#define RALINK_PCIE1_RST (1<<25)
#define RALINK_PCIE2_RST (1<<26)
@@ -88,26 +88,12 @@
#define RT6855_PCIE1_OFFSET0x3000
#define RT6855_PCIE2_OFFSET0x4000
-#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE0_OFFSET + 0x0010)
-#define RALINK_PCI0_IMBASEBAR0_ADDR*(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE0_OFFSET + 0x0018)
-#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE0_OFFSET + 0x0030)
-#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE0_OFFSET + 0x0034)
-#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE0_OFFSET + 0x0038)
-#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE0_OFFSET + 0x0050)
-
-#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE1_OFFSET + 0x0010)
-#define RALINK_PCI1_IMBASEBAR0_ADDR*(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE1_OFFSET + 0x0018)
-#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE1_OFFSET + 0x0030)
-#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE1_OFFSET + 0x0034)
-#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE1_OFFSET + 0x0038)
-#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE1_OFFSET + 0x0050)
-
-#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE2_OFFSET + 0x0010)
-#define RALINK_PCI2_IMBASEBAR0_ADDR*(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE2_OFFSET + 0x0018)
-#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE2_OFFSET + 0x0030)
-#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE2_OFFSET + 0x0034)
-#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE2_OFFSET + 0x0038)
-#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE2_OFFSET + 0x0050)
+#define RALINK_PCI_BAR0SETUP_ADDR 0x0010
+#define RALINK_PCI_IMBASEBAR0_ADDR 0x0018
+#define RALINK_PCI_ID 0x0030
+#define RALINK_PCI_CLASS 0x0034
+#define RALINK_PCI_SUBID 0x0038
+#define RALINK_PCI_STATUS 0x0050
#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
@@ -577,7 +563,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;
// set DATA
mdelay(1000);
- if ((RALINK_PCI0_STATUS & 0x1) == 0) {
+ if ((pcie_read(pcie, RT6855_PCIE0_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
printk("PCIE0 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
@@ -587,7 +573,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
}
- if ((RALINK_PCI1_STATUS & 0x1) == 0) {
+ if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
printk("PCIE1 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1);
@@ -597,7 +583,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
}
- if ((RALINK_PCI2_STATUS & 0x1) == 0) {
+ if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
printk("PCIE2 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
rt_
[PATCH v8 09/15] staging: mt7621-pci: review includes putting them in alphabethic order
There are some includes that are being used that are not really needed to correct driver compilation. Remove them and reorder the rest alphabetically. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 22 -- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index e9f6b23..1344291 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -40,26 +40,20 @@ ** */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include +#include #include +#include #include -#include -#include #include #include +#include +#include +#include #include - -#include +#include #include +#include #include "../../pci/pci.h" -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH v7 00/15] staging: mt7621-pci: avoid custom pci config read and writes
On Wed, Aug 1, 2018 at 6:37 AM, Sergio Paracuellos
wrote:
> On Wed, Aug 01, 2018 at 07:56:38AM +1000, NeilBrown wrote:
>> On Tue, Jul 31 2018, Sergio Paracuellos wrote:
>>
>> > This patch series include an attempt to avoid the use of custom
>> > read and writes in driver code and use PCI subsystem common ones.
>> >
>> > In order to do this 'map_bus' callback is implemented and also
>> > data structures for driver are included. The regs base address
>> > ranges and data is being readed from device tree and the driver
>> > gets clean a lot of code.
>> >
>> > This patchet also removes all legacy PCI code using now PCI_DRIVERS_GENERIC
>> > kernel api.
>> >
>> > Changes in v7:
>> > - PATCH 1: Store resources in mt7621_pci data structure.
>> > - PATCH 1: Change completely function
>> > mt7621_pci_parse_request_of_pci_ranges
>> > to parse resources from ranges manually instead of use the function
>> > devm_of_pci_get_host_bridge_resources. This is closer to the mips
>> > pci legacy
>> > code.
>> > - PATCH 1: Create 'mt7621_pcie_request_resources' function to request
>> > resources
>> > parsed from ranges property in the DT. Use pci_add_resource_offset
>> > and set them
>> > manually like the mips pci-legacy code do.
>> > - PATCH 1: don't delete function setup_cm_memory_region and call it
>> > with memory
>> > resource.
>> > - Other patches rebased and adapted to this changes.
>> >
>>
>> No good, sorry.
>>
>> mt7621_pci_parse_request_of_pci_ranges()
>> calls of_pci_range_to_resource() which, for IO resources,
>> calls
>> port = pci_address_to_pio(range->cpu_addr);
>> ->cpu_addr is 1e16
>> and pci_address_to_pci sees that this is larger that IO_SPACE_LIMIT
>> (0x) and returns -1.
>> So the pci probe failed.
>>
>> Maybe mips should have a arch-specific pci_address_to_pio, which does
>> the setp_cm_memory_region() thing just a random guess really.
>>
>> Though if I hack pci_address_to_pio() to succeed, I get:
>>
>> [1.99] mt7621-pci 1e14.pcie: resource collision: [io
>> 0x1e16-0x1e16] conflicts with PCI IO [io 0x-0x]
>>
>> which looks a little weird ... why do those conflict? Maybe because
>> everything has to fit into "PCI IO"..
>> I'm getting lost...
>
> Mmmm, So that seems to be the reason about why the result of
> of_pci_range_to_resource is
> not checked in the legacy code:
>
> See arch/mips/pci/pci-legacy.c +137 (pci_load_of_ranges function). We can try
> if no checking
> it change the things and call in the same places the legacy code does change
> things. Just apply this (diff is against PATCH 1):
>
> diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
> b/drivers/staging/mt7621-pci/pci-mt7621.c
> index 4e8958b..a7f31cd 100644
> --- a/drivers/staging/mt7621-pci/pci-mt7621.c
> +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
> @@ -545,9 +545,7 @@ static int mt7621_pci_parse_request_of_pci_ranges(struct
> mt7621_pcie *pcie)
> }
>
> for_each_of_pci_range(&parser, &range) {
> - err = of_pci_range_to_resource(&range, node, &res);
> - if (err < 0)
> - return err;
> + of_pci_range_to_resource(&range, node, &res);
>
> switch (res.flags & IORESOURCE_TYPE_BITS) {
> case IORESOURCE_IO:
> @@ -569,7 +567,6 @@ static int mt7621_pci_parse_request_of_pci_ranges(struct
> mt7621_pcie *pcie)
>
> memcpy(&pcie->mem, &res, sizeof(res));
> pcie->mem.name = "non-prefetchable";
> - setup_cm_memory_region(&pcie->mem);
> break;
> }
> }
> @@ -610,9 +607,6 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
> if (IS_ERR(pcie->base))
> return PTR_ERR(pcie->base);
>
> - err = mt7621_pci_parse_request_of_pci_ranges(pcie);
> - if (err)
> - return err;
>
> return 0;
> }
> @@ -876,6 +870,12 @@ pcie(2/1/0) link statuspcie2_num pcie1_num
> pcie0_num
> write_config(0, 0, 0, 0x70c, val);
> }
>
> + err = mt7621_pci_parse_request_of_pci_ranges(pcie);
> + if (err)
> + return err;
> +
> + setup_cm_memory_region(&pcie->mem);
> +
> err = mt7621_pcie_request_resources(pcie);
> if (err) {
> dev_err(dev, "Error requesting resources\n");
>
>>
>> Thanks,
>> NeilBrown
>
v8 sent already including this changes and setting resources limits also.
Best regards,
Sergio Paracuellos
> If this does not work I get completely lost :-(.
>
> Thanks for your time and effort in this.
>
> Best regards,
> Sergio Paracuellos
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Re: [PATCH] staging: gasket: sysfs: fix potential null dereference
On Tue, Jul 31, 2018 at 06:23:20PM +0300, Ivan Bornyakov wrote:
> Add handling of possible allocation failure.
>
> Reported by smatch:
>
> drivers/staging/gasket/gasket_sysfs.c:105 put_mapping() error: potential
> null dereference 'files_to_remove'. (kcalloc returns null)
>
> Signed-off-by: Ivan Bornyakov
> ---
> drivers/staging/gasket/gasket_sysfs.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/staging/gasket/gasket_sysfs.c
> b/drivers/staging/gasket/gasket_sysfs.c
> index ef4eca02afa6..682e5c21f203 100644
> --- a/drivers/staging/gasket/gasket_sysfs.c
> +++ b/drivers/staging/gasket/gasket_sysfs.c
> @@ -101,6 +101,12 @@ static void put_mapping(struct gasket_sysfs_mapping
> *mapping)
> files_to_remove = kcalloc(num_files_to_remove,
> sizeof(*files_to_remove),
> GFP_KERNEL);
> + if (!files_to_remove) {
> + pr_err("%s: can't allocate memory\n", __func__);
kcalloc failing will print something, no need to do it again here.
thanks,
greg k-h
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[PATCH v2] staging: gasket: sysfs: fix potential null dereference
Add handling of possible allocation failure.
Reported by smatch:
drivers/staging/gasket/gasket_sysfs.c:105 put_mapping() error: potential null
dereference 'files_to_remove'. (kcalloc returns null)
Signed-off-by: Ivan Bornyakov
---
drivers/staging/gasket/gasket_sysfs.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/staging/gasket/gasket_sysfs.c
b/drivers/staging/gasket/gasket_sysfs.c
index a4bfca43cd03..56d62aea5111 100644
--- a/drivers/staging/gasket/gasket_sysfs.c
+++ b/drivers/staging/gasket/gasket_sysfs.c
@@ -101,6 +101,11 @@ static void put_mapping(struct gasket_sysfs_mapping
*mapping)
files_to_remove = kcalloc(num_files_to_remove,
sizeof(*files_to_remove),
GFP_KERNEL);
+ if (!files_to_remove) {
+ mutex_unlock(&mapping->mutex);
+ return;
+ }
+
for (i = 0; i < num_files_to_remove; i++)
files_to_remove[i] = mapping->attributes[i].attr;
--
2.16.4
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[PATCH] staging: rtl8188eu: use is_multicast_ether_addr
Use is_multicast_ether_addr instead of custom IS_MCAST. The variable for the result of IS_MCAST was only used in the if conditional. So remove the extra variable and move the call to is_multicast_ether_addr into the conditional. Signed-off-by: Michael Straube --- drivers/staging/rtl8188eu/core/rtw_mlme.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/rtl8188eu/core/rtw_mlme.c b/drivers/staging/rtl8188eu/core/rtw_mlme.c index 80f55937e3be..eca06f05c0c4 100644 --- a/drivers/staging/rtl8188eu/core/rtw_mlme.c +++ b/drivers/staging/rtl8188eu/core/rtw_mlme.c @@ -2022,9 +2022,9 @@ void rtw_issue_addbareq_cmd(struct adapter *padapter, struct xmit_frame *pxmitfr struct sta_info *psta = NULL; struct ht_priv *phtpriv; struct pkt_attrib *pattrib = &pxmitframe->attrib; - s32 bmcst = IS_MCAST(pattrib->ra); - if (bmcst || (padapter->mlmepriv.LinkDetectInfo.NumTxOkInPeriod < 100)) + if (is_multicast_ether_addr(pattrib->ra) || + padapter->mlmepriv.LinkDetectInfo.NumTxOkInPeriod < 100) return; priority = pattrib->priority; -- 2.18.0 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v3 06/14] gpu: ipu-v3: Add planar support to interlaced scan
To support interlaced scan with planar formats, cpmem SLUV must
be programmed with the correct chroma line stride. For full and
partial planar 4:2:2 (YUV422P, NV16), chroma line stride must
be doubled. For full and partial planar 4:2:0 (YUV420, YVU420, NV12),
chroma line stride must _not_ be doubled, since a single chroma line
is shared by two luma lines.
Signed-off-by: Steve Longerbeam
---
drivers/gpu/ipu-v3/ipu-cpmem.c | 26 --
drivers/staging/media/imx/imx-ic-prpencvf.c | 3 ++-
drivers/staging/media/imx/imx-media-csi.c | 3 ++-
include/video/imx-ipu-v3.h | 3 ++-
4 files changed, 30 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/ipu-v3/ipu-cpmem.c b/drivers/gpu/ipu-v3/ipu-cpmem.c
index 8cd9e37..eae0f63 100644
--- a/drivers/gpu/ipu-v3/ipu-cpmem.c
+++ b/drivers/gpu/ipu-v3/ipu-cpmem.c
@@ -267,9 +267,10 @@ void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32
u_off, u32 v_off)
}
EXPORT_SYMBOL_GPL(ipu_cpmem_set_uv_offset);
-void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride)
+void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride,
+ u32 pixelformat)
{
- u32 ilo, sly;
+ u32 ilo, sly, sluv;
if (stride < 0) {
stride = -stride;
@@ -280,9 +281,30 @@ void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch,
int stride)
sly = (stride * 2) - 1;
+ switch (pixelformat) {
+ case V4L2_PIX_FMT_YUV420:
+ case V4L2_PIX_FMT_YVU420:
+ sluv = stride / 2 - 1;
+ break;
+ case V4L2_PIX_FMT_NV12:
+ sluv = stride - 1;
+ break;
+ case V4L2_PIX_FMT_YUV422P:
+ sluv = stride - 1;
+ break;
+ case V4L2_PIX_FMT_NV16:
+ sluv = stride * 2 - 1;
+ break;
+ default:
+ sluv = 0;
+ break;
+ }
+
ipu_ch_param_write_field(ch, IPU_FIELD_SO, 1);
ipu_ch_param_write_field(ch, IPU_FIELD_ILO, ilo);
ipu_ch_param_write_field(ch, IPU_FIELD_SLY, sly);
+ if (sluv)
+ ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, sluv);
};
EXPORT_SYMBOL_GPL(ipu_cpmem_interlaced_scan);
diff --git a/drivers/staging/media/imx/imx-ic-prpencvf.c
b/drivers/staging/media/imx/imx-ic-prpencvf.c
index 28f41ca..af72248 100644
--- a/drivers/staging/media/imx/imx-ic-prpencvf.c
+++ b/drivers/staging/media/imx/imx-ic-prpencvf.c
@@ -412,7 +412,8 @@ static int prp_setup_channel(struct prp_priv *priv,
if (image.pix.field == V4L2_FIELD_NONE &&
V4L2_FIELD_HAS_BOTH(infmt->field) &&
channel == priv->out_ch)
- ipu_cpmem_interlaced_scan(channel, image.pix.bytesperline);
+ ipu_cpmem_interlaced_scan(channel, image.pix.bytesperline,
+ image.pix.pixelformat);
ret = ipu_ic_task_idma_init(priv->ic, channel,
image.pix.width, image.pix.height,
diff --git a/drivers/staging/media/imx/imx-media-csi.c
b/drivers/staging/media/imx/imx-media-csi.c
index 2fdd21d..1c468ec 100644
--- a/drivers/staging/media/imx/imx-media-csi.c
+++ b/drivers/staging/media/imx/imx-media-csi.c
@@ -509,7 +509,8 @@ static int csi_idmac_setup_channel(struct csi_priv *priv)
if (image.pix.field == V4L2_FIELD_NONE &&
V4L2_FIELD_HAS_BOTH(infmt->field))
ipu_cpmem_interlaced_scan(priv->idmac_ch,
- image.pix.bytesperline);
+ image.pix.bytesperline,
+ image.pix.pixelformat);
ipu_idmac_set_double_buffer(priv->idmac_ch, true);
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index f44a351..e888c66 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -255,7 +255,8 @@ void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int
stride);
void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t
buf);
void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
-void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
+void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride,
+ u32 pixelformat);
void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch);
void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
--
2.7.4
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[PATCH v3 09/14] media: imx: interweave and odd-chroma-row skip are incompatible
If IDMAC interweaving is enabled in a write channel, the channel must
write the odd chroma rows for 4:2:0 formats. Skipping writing the odd
chroma rows produces corrupted captured 4:2:0 images when interweave
is enabled.
Reported-by: Krzysztof Hałasa
Signed-off-by: Steve Longerbeam
---
drivers/staging/media/imx/imx-ic-prpencvf.c | 9 +++--
drivers/staging/media/imx/imx-media-csi.c | 8 ++--
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/media/imx/imx-ic-prpencvf.c
b/drivers/staging/media/imx/imx-ic-prpencvf.c
index 1a03d4c..cf76b04 100644
--- a/drivers/staging/media/imx/imx-ic-prpencvf.c
+++ b/drivers/staging/media/imx/imx-ic-prpencvf.c
@@ -391,12 +391,17 @@ static int prp_setup_channel(struct prp_priv *priv,
image.phys0 = addr0;
image.phys1 = addr1;
- if (channel == priv->out_ch || channel == priv->rot_out_ch) {
+ /*
+* Skip writing U and V components to odd rows in the output
+* channels for planar 4:2:0 (but not when enabling IDMAC
+* interweaving, they are incompatible).
+*/
+ if (!interweave && (channel == priv->out_ch ||
+ channel == priv->rot_out_ch)) {
switch (image.pix.pixelformat) {
case V4L2_PIX_FMT_YUV420:
case V4L2_PIX_FMT_YVU420:
case V4L2_PIX_FMT_NV12:
- /* Skip writing U and V components to odd rows */
ipu_cpmem_skip_odd_chroma_rows(channel);
break;
}
diff --git a/drivers/staging/media/imx/imx-media-csi.c
b/drivers/staging/media/imx/imx-media-csi.c
index 3a09a9b..1155d50d 100644
--- a/drivers/staging/media/imx/imx-media-csi.c
+++ b/drivers/staging/media/imx/imx-media-csi.c
@@ -454,8 +454,12 @@ static int csi_idmac_setup_channel(struct csi_priv *priv)
((image.pix.width & 0x1f) ?
((image.pix.width & 0xf) ? 8 : 16) : 32) : 64;
passthrough_bits = 16;
- /* Skip writing U and V components to odd rows */
- ipu_cpmem_skip_odd_chroma_rows(priv->idmac_ch);
+ /*
+* Skip writing U and V components to odd rows (but not
+* when enabling IDMAC interweaving, they are incompatible).
+*/
+ if (!interweave)
+ ipu_cpmem_skip_odd_chroma_rows(priv->idmac_ch);
break;
case V4L2_PIX_FMT_YUYV:
case V4L2_PIX_FMT_UYVY:
--
2.7.4
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[PATCH v3 07/14] media: imx: Fix field negotiation
IDMAC interlaced scan, a.k.a. interweave, should be enabled in the
IDMAC output channels only if the IDMAC output pad field type is
'seq-bt' or 'seq-tb', and field type at the capture interface is
'interlaced*'.
V4L2_FIELD_HAS_BOTH() macro should not be used on the input to determine
enabling interlaced/interweave scan. That macro includes the 'interlaced'
field types, and in those cases the data is already interweaved with
top/bottom field lines.
The CSI will capture whole frames when the source specifies alternate
field mode. So the CSI also enables interweave for alternate input
field type and the field type at capture interface is interlaced.
Fix the logic for setting field type in try_fmt in CSI entity.
The behavior should be:
- No restrictions on field type at sink pad.
- At the output pads, allow sequential fields in TB order, if the sink pad
field type is sequential or alternate. Otherwise passthrough the field
type from sink to source pad.
Move this logic to new function csi_try_field().
These changes result in the following allowed field transformations
from CSI sink -> source pads (all other field types at sink are passed
through to source):
seq-tb -> seq-tb
seq-bt -> seq-tb
alternate -> seq-tb
In a future patch, the CSI sink -> source will allow:
seq-tb -> seq-bt
seq-bt -> seq-bt
alternate -> seq-bt
This will require supporting interweave with top/bottom line swapping.
Until then seq-bt is not allowed at the CSI source pad because there is
no way to swap top/bottom lines when interweaving to INTERLACED_BT --
note that despite the name, INTERLACED_BT is top-bottom order in memory.
The BT in this case refers to field dominance: the bottom lines are
older in time than the top lines.
The capture interface device allows selecting IDMAC interweave by
choosing INTERLACED_TB if the CSI/PRPENCVF source pad is seq-tb and
INTERLACED_BT if the source pad is seq-bt (for future support of seq-bt).
Signed-off-by: Steve Longerbeam
---
drivers/staging/media/imx/imx-ic-prpencvf.c | 21 ++---
drivers/staging/media/imx/imx-media-capture.c | 14 ++
drivers/staging/media/imx/imx-media-csi.c | 64 ---
3 files changed, 76 insertions(+), 23 deletions(-)
diff --git a/drivers/staging/media/imx/imx-ic-prpencvf.c
b/drivers/staging/media/imx/imx-ic-prpencvf.c
index af72248..1a03d4c 100644
--- a/drivers/staging/media/imx/imx-ic-prpencvf.c
+++ b/drivers/staging/media/imx/imx-ic-prpencvf.c
@@ -354,12 +354,13 @@ static int prp_setup_channel(struct prp_priv *priv,
{
struct imx_media_video_dev *vdev = priv->vdev;
const struct imx_media_pixfmt *outcc;
- struct v4l2_mbus_framefmt *infmt;
+ struct v4l2_mbus_framefmt *outfmt;
unsigned int burst_size;
struct ipu_image image;
+ bool interweave;
int ret;
- infmt = &priv->format_mbus[PRPENCVF_SINK_PAD];
+ outfmt = &priv->format_mbus[PRPENCVF_SRC_PAD];
outcc = vdev->cc;
ipu_cpmem_zero(channel);
@@ -369,6 +370,15 @@ static int prp_setup_channel(struct prp_priv *priv,
image.rect.width = image.pix.width;
image.rect.height = image.pix.height;
+ /*
+* If the field type at capture interface is interlaced, and
+* the output IDMAC pad is sequential, enable interweave at
+* the IDMAC output channel.
+*/
+ interweave = V4L2_FIELD_IS_INTERLACED(image.pix.field) &&
+ V4L2_FIELD_IS_SEQUENTIAL(outfmt->field) &&
+ channel == priv->out_ch;
+
if (rot_swap_width_height) {
swap(image.pix.width, image.pix.height);
swap(image.rect.width, image.rect.height);
@@ -409,9 +419,7 @@ static int prp_setup_channel(struct prp_priv *priv,
if (rot_mode)
ipu_cpmem_set_rotation(channel, rot_mode);
- if (image.pix.field == V4L2_FIELD_NONE &&
- V4L2_FIELD_HAS_BOTH(infmt->field) &&
- channel == priv->out_ch)
+ if (interweave)
ipu_cpmem_interlaced_scan(channel, image.pix.bytesperline,
image.pix.pixelformat);
@@ -839,8 +847,7 @@ static void prp_try_fmt(struct prp_priv *priv,
infmt = __prp_get_fmt(priv, cfg, PRPENCVF_SINK_PAD, sdformat->which);
if (sdformat->pad == PRPENCVF_SRC_PAD) {
- if (sdformat->format.field != V4L2_FIELD_NONE)
- sdformat->format.field = infmt->field;
+ sdformat->format.field = infmt->field;
prp_bound_align_output(&sdformat->format, infmt,
priv->rot_mode);
diff --git a/drivers/staging/media/imx/imx-media-capture.c
b/drivers/staging/media/imx/imx-media-capture.c
index 256039c..5d3dc92 100644
--- a/drivers/staging/media/imx/imx-media-capture.c
+++ b/drivers/staging/media/imx/imx-media-capture.c
@@ -239,6 +239,20 @@ static int capture_try_fmt_vid_cap(struct file *file, void
*fh,
[PATCH v3 12/14] media: imx-csi: Move crop/compose reset after filling default mbus fields
If caller passes un-initialized field type V4L2_FIELD_ANY to CSI
sink pad, the reset CSI crop window would not be correct, because
the crop window depends on a valid input field type. To fix move
the reset of crop and compose windows to after the call to
imx_media_fill_default_mbus_fields().
Signed-off-by: Steve Longerbeam
---
drivers/staging/media/imx/imx-media-csi.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/staging/media/imx/imx-media-csi.c
b/drivers/staging/media/imx/imx-media-csi.c
index 139c694..6f24b3b 100644
--- a/drivers/staging/media/imx/imx-media-csi.c
+++ b/drivers/staging/media/imx/imx-media-csi.c
@@ -1402,19 +1402,6 @@ static void csi_try_fmt(struct csi_priv *priv,
W_ALIGN, &sdformat->format.height,
MIN_H, MAX_H, H_ALIGN, S_ALIGN);
- /* Reset crop and compose rectangles */
- crop->left = 0;
- crop->top = 0;
- crop->width = sdformat->format.width;
- crop->height = sdformat->format.height;
- if (sdformat->format.field == V4L2_FIELD_ALTERNATE)
- crop->height *= 2;
- csi_try_crop(priv, crop, cfg, &sdformat->format, upstream_ep);
- compose->left = 0;
- compose->top = 0;
- compose->width = crop->width;
- compose->height = crop->height;
-
*cc = imx_media_find_mbus_format(sdformat->format.code,
CS_SEL_ANY, true);
if (!*cc) {
@@ -1430,6 +1417,20 @@ static void csi_try_fmt(struct csi_priv *priv,
imx_media_fill_default_mbus_fields(
&sdformat->format, infmt,
priv->active_output_pad == CSI_SRC_PAD_DIRECT);
+
+ /* Reset crop and compose rectangles */
+ crop->left = 0;
+ crop->top = 0;
+ crop->width = sdformat->format.width;
+ crop->height = sdformat->format.height;
+ if (sdformat->format.field == V4L2_FIELD_ALTERNATE)
+ crop->height *= 2;
+ csi_try_crop(priv, crop, cfg, &sdformat->format, upstream_ep);
+ compose->left = 0;
+ compose->top = 0;
+ compose->width = crop->width;
+ compose->height = crop->height;
+
break;
}
}
--
2.7.4
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[PATCH v3 03/14] gpu: ipu-csi: Swap fields according to input/output field types
The function ipu_csi_init_interface() was inverting the F-bit for
NTSC case, in the CCIR_CODE_1/2 registers. The result being that
for NTSC bottom-top field order, the CSI would swap fields and
capture in top-bottom order.
Instead, base field swap on the field order of the input to the CSI,
and the field order of the requested output. If the input/output
fields are sequential but different, swap fields, otherwise do
not swap. This requires passing both the input and output mbus
frame formats to ipu_csi_init_interface().
Move this code to a new private function ipu_csi_set_bt_interlaced_codes()
that programs the CCIR_CODE_1/2 registers for interlaced BT.656 (and
possibly interlaced BT.1120 in the future).
When detecting input video standard from the input frame width/height,
make sure to double height if input field type is alternate, since
in that case input height only includes lines for one field.
Signed-off-by: Steve Longerbeam
---
drivers/gpu/ipu-v3/ipu-csi.c | 133 +-
drivers/staging/media/imx/imx-media-csi.c | 13 +--
include/video/imx-ipu-v3.h| 3 +-
3 files changed, 98 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/ipu-v3/ipu-csi.c b/drivers/gpu/ipu-v3/ipu-csi.c
index 5450a2d..7a845c9 100644
--- a/drivers/gpu/ipu-v3/ipu-csi.c
+++ b/drivers/gpu/ipu-v3/ipu-csi.c
@@ -315,6 +315,15 @@ static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config
*cfg, u32 mbus_code)
return 0;
}
+/* translate alternate field mode based on given standard */
+static inline enum v4l2_field
+ipu_csi_translate_field(enum v4l2_field field, v4l2_std_id std)
+{
+ return (field != V4L2_FIELD_ALTERNATE) ? field :
+ ((std & V4L2_STD_525_60) ?
+V4L2_FIELD_SEQ_BT : V4L2_FIELD_SEQ_TB);
+}
+
/*
* Fill a CSI bus config struct from mbus_config and mbus_framefmt.
*/
@@ -358,19 +367,73 @@ static void fill_csi_bus_cfg(struct ipu_csi_bus_config
*csicfg,
}
}
+static int ipu_csi_set_bt_interlaced_codes(struct ipu_csi *csi,
+ struct v4l2_mbus_framefmt *infmt,
+ struct v4l2_mbus_framefmt *outfmt,
+ v4l2_std_id std)
+{
+ enum v4l2_field infield, outfield;
+ bool swap_fields;
+
+ /* get translated field type of input and output */
+ infield = ipu_csi_translate_field(infmt->field, std);
+ outfield = ipu_csi_translate_field(outfmt->field, std);
+
+ /*
+* Write the H-V-F codes the CSI will match against the
+* incoming data for start/end of active and blanking
+* field intervals. If input and output field types are
+* sequential but not the same (one is SEQ_BT and the other
+* is SEQ_TB), swap the F-bit so that the CSI will capture
+* field 1 lines before field 0 lines.
+*/
+ swap_fields = (V4L2_FIELD_IS_SEQUENTIAL(infield) &&
+ V4L2_FIELD_IS_SEQUENTIAL(outfield) &&
+ infield != outfield);
+
+ if (!swap_fields) {
+ /*
+* Field0BlankEnd = 110, Field0BlankStart = 010
+* Field0ActiveEnd = 100, Field0ActiveStart = 000
+* Field1BlankEnd = 111, Field1BlankStart = 011
+* Field1ActiveEnd = 101, Field1ActiveStart = 001
+*/
+ ipu_csi_write(csi, 0x40596 | CSI_CCIR_ERR_DET_EN,
+ CSI_CCIR_CODE_1);
+ ipu_csi_write(csi, 0xD07DF, CSI_CCIR_CODE_2);
+ } else {
+ dev_dbg(csi->ipu->dev, "capture field swap\n");
+
+ /* same as above but with F-bit inverted */
+ ipu_csi_write(csi, 0xD07DF | CSI_CCIR_ERR_DET_EN,
+ CSI_CCIR_CODE_1);
+ ipu_csi_write(csi, 0x40596, CSI_CCIR_CODE_2);
+ }
+
+ ipu_csi_write(csi, 0xFF, CSI_CCIR_CODE_3);
+
+ return 0;
+}
+
+
int ipu_csi_init_interface(struct ipu_csi *csi,
struct v4l2_mbus_config *mbus_cfg,
- struct v4l2_mbus_framefmt *mbus_fmt)
+ struct v4l2_mbus_framefmt *infmt,
+ struct v4l2_mbus_framefmt *outfmt)
{
struct ipu_csi_bus_config cfg;
unsigned long flags;
u32 width, height, data = 0;
+ v4l2_std_id std;
+ int ret = 0;
- fill_csi_bus_cfg(&cfg, mbus_cfg, mbus_fmt);
+ fill_csi_bus_cfg(&cfg, mbus_cfg, infmt);
/* set default sensor frame width and height */
- width = mbus_fmt->width;
- height = mbus_fmt->height;
+ width = infmt->width;
+ height = infmt->height;
+ if (infmt->field == V4L2_FIELD_ALTERNATE)
+ height *= 2;
/* Set the CSI_SENS_CONF register remaining fields */
data |= cfg.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT |
@@ -397,42 +460,33 @@ int ipu
[PATCH v3 11/14] media: imx: vdic: rely on VDIC for correct field order
prepare_vdi_in_buffers() was setting up the dma pointers as if the
VDIC is always programmed to receive the fields in bottom-top order,
i.e. as if ipu_vdi_set_field_order() only programs BT order in the VDIC.
But that's not true, ipu_vdi_set_field_order() is working correctly.
So fix prepare_vdi_in_buffers() to give the VDIC the fields in whatever
order they were received by the video source, and rely on the VDIC to
sort out which is top and which is bottom.
Signed-off-by: Steve Longerbeam
---
drivers/staging/media/imx/imx-media-vdic.c | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/drivers/staging/media/imx/imx-media-vdic.c
b/drivers/staging/media/imx/imx-media-vdic.c
index 482250d..4a89071 100644
--- a/drivers/staging/media/imx/imx-media-vdic.c
+++ b/drivers/staging/media/imx/imx-media-vdic.c
@@ -219,26 +219,18 @@ static void __maybe_unused prepare_vdi_in_buffers(struct
vdic_priv *priv,
switch (priv->fieldtype) {
case V4L2_FIELD_SEQ_TB:
- prev_phys = vb2_dma_contig_plane_dma_addr(prev_vb, 0);
- curr_phys = vb2_dma_contig_plane_dma_addr(curr_vb, 0) + fs;
- next_phys = vb2_dma_contig_plane_dma_addr(curr_vb, 0);
- break;
case V4L2_FIELD_SEQ_BT:
prev_phys = vb2_dma_contig_plane_dma_addr(prev_vb, 0) + fs;
curr_phys = vb2_dma_contig_plane_dma_addr(curr_vb, 0);
next_phys = vb2_dma_contig_plane_dma_addr(curr_vb, 0) + fs;
break;
+ case V4L2_FIELD_INTERLACED_TB:
case V4L2_FIELD_INTERLACED_BT:
+ case V4L2_FIELD_INTERLACED:
prev_phys = vb2_dma_contig_plane_dma_addr(prev_vb, 0) + is;
curr_phys = vb2_dma_contig_plane_dma_addr(curr_vb, 0);
next_phys = vb2_dma_contig_plane_dma_addr(curr_vb, 0) + is;
break;
- default:
- /* assume V4L2_FIELD_INTERLACED_TB */
- prev_phys = vb2_dma_contig_plane_dma_addr(prev_vb, 0);
- curr_phys = vb2_dma_contig_plane_dma_addr(curr_vb, 0) + is;
- next_phys = vb2_dma_contig_plane_dma_addr(curr_vb, 0);
- break;
}
ipu_cpmem_set_buffer(priv->vdi_in_ch_p, 0, prev_phys);
--
2.7.4
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[PATCH v3 08/14] media: imx-csi: Double crop height for alternate fields at sink
If the incoming sink field type is alternate, the reset crop height
and crop height bounds must be set to twice the incoming height,
because in alternate field mode, upstream will report only the
lines for a single field, and the CSI captures the whole frame.
Signed-off-by: Steve Longerbeam
---
drivers/staging/media/imx/imx-media-csi.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/staging/media/imx/imx-media-csi.c
b/drivers/staging/media/imx/imx-media-csi.c
index 8be1033..3a09a9b 100644
--- a/drivers/staging/media/imx/imx-media-csi.c
+++ b/drivers/staging/media/imx/imx-media-csi.c
@@ -1135,6 +1135,8 @@ static void csi_try_crop(struct csi_priv *priv,
struct v4l2_mbus_framefmt *infmt,
struct v4l2_fwnode_endpoint *upstream_ep)
{
+ u32 in_height;
+
crop->width = min_t(__u32, infmt->width, crop->width);
if (crop->left + crop->width > infmt->width)
crop->left = infmt->width - crop->width;
@@ -1142,6 +1144,10 @@ static void csi_try_crop(struct csi_priv *priv,
crop->left &= ~0x3;
crop->width &= ~0x7;
+ in_height = infmt->height;
+ if (infmt->field == V4L2_FIELD_ALTERNATE)
+ in_height *= 2;
+
/*
* FIXME: not sure why yet, but on interlaced bt.656,
* changing the vertical cropping causes loss of vertical
@@ -1151,12 +1157,12 @@ static void csi_try_crop(struct csi_priv *priv,
if (upstream_ep->bus_type == V4L2_MBUS_BT656 &&
(V4L2_FIELD_HAS_BOTH(infmt->field) ||
infmt->field == V4L2_FIELD_ALTERNATE)) {
- crop->height = infmt->height;
- crop->top = (infmt->height == 480) ? 2 : 0;
+ crop->height = in_height;
+ crop->top = (in_height == 480) ? 2 : 0;
} else {
- crop->height = min_t(__u32, infmt->height, crop->height);
- if (crop->top + crop->height > infmt->height)
- crop->top = infmt->height - crop->height;
+ crop->height = min_t(__u32, in_height, crop->height);
+ if (crop->top + crop->height > in_height)
+ crop->top = in_height - crop->height;
}
}
@@ -1396,6 +1402,8 @@ static void csi_try_fmt(struct csi_priv *priv,
crop->top = 0;
crop->width = sdformat->format.width;
crop->height = sdformat->format.height;
+ if (sdformat->format.field == V4L2_FIELD_ALTERNATE)
+ crop->height *= 2;
csi_try_crop(priv, crop, cfg, &sdformat->format, upstream_ep);
compose->left = 0;
compose->top = 0;
@@ -1523,6 +1531,8 @@ static int csi_get_selection(struct v4l2_subdev *sd,
sel->r.top = 0;
sel->r.width = infmt->width;
sel->r.height = infmt->height;
+ if (infmt->field == V4L2_FIELD_ALTERNATE)
+ sel->r.height *= 2;
break;
case V4L2_SEL_TGT_CROP:
sel->r = *crop;
--
2.7.4
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[PATCH v3 13/14] media: imx: Allow interweave with top/bottom lines swapped
Allow sequential->interlaced interweaving but with top/bottom
lines swapped to the output buffer.
This can be accomplished by adding one line length to IDMAC output
channel address, with a negative line length for the interlace offset.
This is to allow the seq-bt -> interlaced-bt transformation, where
bottom lines are still dominant (older in time) but with top lines
first in the interweaved output buffer.
With this support, the CSI can now allow seq-bt at its source pads,
e.g. the following transformations are allowed in CSI from sink to
source:
seq-tb -> seq-bt
seq-bt -> seq-bt
alternate -> seq-bt
Suggested-by: Philipp Zabel
Signed-off-by: Steve Longerbeam
---
drivers/staging/media/imx/imx-ic-prpencvf.c | 17 ++-
drivers/staging/media/imx/imx-media-csi.c | 46 +++--
2 files changed, 53 insertions(+), 10 deletions(-)
diff --git a/drivers/staging/media/imx/imx-ic-prpencvf.c
b/drivers/staging/media/imx/imx-ic-prpencvf.c
index cf76b04..1499b0c 100644
--- a/drivers/staging/media/imx/imx-ic-prpencvf.c
+++ b/drivers/staging/media/imx/imx-ic-prpencvf.c
@@ -106,6 +106,8 @@ struct prp_priv {
u32 frame_sequence; /* frame sequence counter */
bool last_eof; /* waiting for last EOF at stream off */
bool nfb4eof;/* NFB4EOF encountered during streaming */
+ u32 interweave_offset; /* interweave line offset to swap
+ top/bottom lines */
struct completion last_eof_comp;
};
@@ -235,6 +237,9 @@ static void prp_vb2_buf_done(struct prp_priv *priv, struct
ipuv3_channel *ch)
if (ipu_idmac_buffer_is_ready(ch, priv->ipu_buf_num))
ipu_idmac_clear_buffer(ch, priv->ipu_buf_num);
+ if (ch == priv->out_ch)
+ phys += priv->interweave_offset;
+
ipu_cpmem_set_buffer(ch, priv->ipu_buf_num, phys);
}
@@ -388,6 +393,13 @@ static int prp_setup_channel(struct prp_priv *priv,
(image.pix.width * outcc->bpp) >> 3;
}
+ priv->interweave_offset = 0;
+
+ if (interweave && image.pix.field == V4L2_FIELD_INTERLACED_BT) {
+ image.rect.top = 1;
+ priv->interweave_offset = image.pix.bytesperline;
+ }
+
image.phys0 = addr0;
image.phys1 = addr1;
@@ -425,7 +437,10 @@ static int prp_setup_channel(struct prp_priv *priv,
ipu_cpmem_set_rotation(channel, rot_mode);
if (interweave)
- ipu_cpmem_interlaced_scan(channel, image.pix.bytesperline,
+ ipu_cpmem_interlaced_scan(channel,
+ priv->interweave_offset ?
+ -image.pix.bytesperline :
+ image.pix.bytesperline,
image.pix.pixelformat);
ret = ipu_ic_task_idma_init(priv->ic, channel,
diff --git a/drivers/staging/media/imx/imx-media-csi.c
b/drivers/staging/media/imx/imx-media-csi.c
index 6f24b3b..a5f88ae 100644
--- a/drivers/staging/media/imx/imx-media-csi.c
+++ b/drivers/staging/media/imx/imx-media-csi.c
@@ -114,6 +114,8 @@ struct csi_priv {
u32 frame_sequence; /* frame sequence counter */
bool last_eof; /* waiting for last EOF at stream off */
bool nfb4eof;/* NFB4EOF encountered during streaming */
+ u32 interweave_offset; /* interweave line offset to swap
+ top/bottom lines */
struct completion last_eof_comp;
};
@@ -283,7 +285,8 @@ static void csi_vb2_buf_done(struct csi_priv *priv)
if (ipu_idmac_buffer_is_ready(priv->idmac_ch, priv->ipu_buf_num))
ipu_idmac_clear_buffer(priv->idmac_ch, priv->ipu_buf_num);
- ipu_cpmem_set_buffer(priv->idmac_ch, priv->ipu_buf_num, phys);
+ ipu_cpmem_set_buffer(priv->idmac_ch, priv->ipu_buf_num,
+phys + priv->interweave_offset);
}
static irqreturn_t csi_idmac_eof_interrupt(int irq, void *dev_id)
@@ -393,10 +396,10 @@ static void csi_idmac_unsetup_vb2_buf(struct csi_priv
*priv,
static int csi_idmac_setup_channel(struct csi_priv *priv)
{
struct imx_media_video_dev *vdev = priv->vdev;
+ bool passthrough, interweave, interweave_swap;
const struct imx_media_pixfmt *incc;
struct v4l2_mbus_framefmt *infmt;
struct v4l2_mbus_framefmt *outfmt;
- bool passthrough, interweave;
struct ipu_image image;
u32 passthrough_bits;
u32 passthrough_cycles;
@@ -430,6 +433,8 @@ static int csi_idmac_setup_channel(struct csi_priv *priv)
*/
interweave = V4L2_FIELD_IS_INTERLACED(image.pix.field) &&
V4L2_FIELD_IS_SEQUENTIAL(outfmt->field);
+ interweave_swap = interweave &&
+ image.pix.field == V4L2_FIELD_INTERLACED_BT;
switch (image.pix.pixelformat) {
case V4L2_PIX_FMT_SBGGR8:
@@ -483,15 +488,25 @@ static int csi_idmac_setup_channel(struc
[PATCH v3 10/14] media: imx-csi: Allow skipping odd chroma rows for YVU420
Skip writing U/V components to odd rows for YVU420 in addition to YUV420 and NV12. Signed-off-by: Steve Longerbeam Reviewed-by: Philipp Zabel --- drivers/staging/media/imx/imx-media-csi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/staging/media/imx/imx-media-csi.c b/drivers/staging/media/imx/imx-media-csi.c index 1155d50d..139c694 100644 --- a/drivers/staging/media/imx/imx-media-csi.c +++ b/drivers/staging/media/imx/imx-media-csi.c @@ -449,6 +449,7 @@ static int csi_idmac_setup_channel(struct csi_priv *priv) passthrough_bits = 16; break; case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_YVU420: case V4L2_PIX_FMT_NV12: burst_size = (image.pix.width & 0x3f) ? ((image.pix.width & 0x1f) ? -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH v8 00/15] staging: mt7621-pci: avoid custom pci config read and writes
On Wed, Aug 01 2018, Sergio Paracuellos wrote:
> This patch series include an attempt to avoid the use of custom
> read and writes in driver code and use PCI subsystem common ones.
>
> In order to do this 'map_bus' callback is implemented and also
> data structures for driver are included. The regs base address
> ranges and data is being readed from device tree and the driver
> gets clean a lot of code.
>
> This patchet also removes all legacy PCI code using now PCI_DRIVERS_GENERIC
> kernel api.
>
> Changes in v8:
> - PATCH 1: don't check 'of_pci_range_to_resource' return value which is
> not
> being checked for the legacy code.
> - PATCH 1: call 'mt7621_pci_parse_request_of_pci_ranges' 'and
> setup_cm_memory_region'
> after the port initialization code.
> - PATCH 1: make use of 'pci_host_probe' to avoid code duplication in
> function
> 'mt7621_pcie_register_host'.
> - PATCH 1: set resource limits with no limit for the end in
> 'ioport_resource' and
> 'iomem_resource'. It seems mips needs this to work properly.
> - Other patches rebased and adapted to this changes.
See boot log below. Doesn't hang, but doesn't work.
I'll try to schedule some time to see if I can work out what is
happening.
Thanks,
NeilBrown
Starting kernel ...
[0.00] Linux version 4.18.0-rc7+ (neilb@noble) (gcc version 7.2.0
(GCC)) #273 SMP Thu Aug 2 08:02:45 AEST 2018
[0.00] SoC Type: MediaTek MT7621 ver:1 eco:3
[0.00] bootconsole [early0] enabled
[0.00] CPU0 revision is: 0001992f (MIPS 1004Kc)
[0.00] MIPS: machine is GB-PC1
[0.00] Determined physical RAM map:
[0.00] memory: 1c00 @ (usable)
[0.00] memory: 0400 @ 2000 (usable)
[0.00] Initrd not found or empty - disabling initrd
[0.00] VPE topology {2,2} total 4
[0.00] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[0.00] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32
bytes
[0.00] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[0.00] Zone ranges:
[0.00] Normal [mem 0x-0x1fff]
[0.00] HighMem [mem 0x2000-0x23ff]
[0.00] Movable zone start for each node
[0.00] Early memory node ranges
[0.00] node 0: [mem 0x-0x1bff]
[0.00] node 0: [mem 0x2000-0x23ff]
[0.00] Initmem setup node 0 [mem 0x-0x23ff]
[0.00] random: get_random_bytes called from start_kernel+0xb4/0x4ec
with crng_init=0
[0.00] percpu: Embedded 15 pages/cpu @(ptrval) s30480 r8192 d22768
u61440
[0.00] Built 1 zonelists, mobility grouping on. Total pages: 130048
[0.00] Kernel command line: console=ttyS0,57600
[0.00] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[0.00] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[0.00] Writing ErrCtl register=000108a2
[0.00] Readback ErrCtl register=000108a2
[0.00] Memory: 504788K/524288K available (6135K kernel code, 228K
rwdata, 1052K rodata, 6524K init, 241K bss, 19500K reserved, 0K cma-reserved,
65536K highmem)
[0.00] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[0.00] Hierarchical RCU implementation.
[0.00] NR_IRQS: 256
[0.00] clocksource: GIC: mask: 0x max_cycles:
0xcf914c9718, max_idle_ns: 440795231327 ns
[0.00] sched_clock: 32 bits at 100 Hz, resolution 1000ns, wraps
every 2147483647500ns
[0.01] Calibrating delay loop... 597.60 BogoMIPS (lpj=2988032)
[0.07] pid_max: default: 32768 minimum: 301
[0.08] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[0.09] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[0.10] Hierarchical SRCU implementation.
[0.11] smp: Bringing up secondary CPUs ...
[0.12] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[0.12] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32
bytes
[0.12] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[0.12] CPU1 revision is: 0001992f (MIPS 1004Kc)
[0.18] Synchronize counters for CPU 1: done.
[0.22] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[0.22] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32
bytes
[0.22] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[0.22] CPU2 revision is: 0001992f (MIPS 1004Kc)
[0.28] Synchronize counters for CPU 2: done.
[0.32] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[0.32] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32
bytes
[0.32] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[0.32] CPU3 revision
[PATCH char-misc 1/1] Drivers: hv: vmbus: Cleanup synic memory free path
From: Michael Kelley clk_evt memory is not being freed when the synic is shutdown or when there is an allocation error. Add the appropriate kfree() call, along with a comment to clarify how the memory gets freed after an allocation error. Make the free path consistent by removing checks for NULL since kfree() and free_page() already do the check. Signed-off-by: Michael Kelley Reported-by: Dan Carpenter --- drivers/hv/hv.c | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/hv/hv.c b/drivers/hv/hv.c index 8d4fe0e..1fb9a6b 100644 --- a/drivers/hv/hv.c +++ b/drivers/hv/hv.c @@ -240,6 +240,10 @@ int hv_synic_alloc(void) return 0; err: + /* +* Any memory allocations that succeeded will be freed when +* the caller cleans up by calling hv_synic_free() +*/ return -ENOMEM; } @@ -252,12 +256,10 @@ void hv_synic_free(void) struct hv_per_cpu_context *hv_cpu = per_cpu_ptr(hv_context.cpu_context, cpu); - if (hv_cpu->synic_event_page) - free_page((unsigned long)hv_cpu->synic_event_page); - if (hv_cpu->synic_message_page) - free_page((unsigned long)hv_cpu->synic_message_page); - if (hv_cpu->post_msg_page) - free_page((unsigned long)hv_cpu->post_msg_page); + kfree(hv_cpu->clk_evt); + free_page((unsigned long)hv_cpu->synic_event_page); + free_page((unsigned long)hv_cpu->synic_message_page); + free_page((unsigned long)hv_cpu->post_msg_page); } kfree(hv_context.hv_numa_map); -- 1.8.3.1 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH 0/3] Drivers: hv: vmbus: Miscellaneous fixes
From: "K. Y. Srinivasan" Miscellaneous fixes. Dexuan Cui (1): Drivers: hv: vmbus: Reset the channel callback in vmbus_onoffer_rescind() Michael Kelley (2): Drivers: hv: vmbus: Remove use of slow_virt_to_phys() Drivers: hv: vmbus: Cleanup synic memory free path drivers/hv/channel.c | 67 +-- drivers/hv/channel_mgmt.c | 6 drivers/hv/hv.c | 14 include/linux/hyperv.h| 2 ++ 4 files changed, 60 insertions(+), 29 deletions(-) -- 2.17.1 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH 3/3] Drivers: hv: vmbus: Cleanup synic memory free path
From: Michael Kelley clk_evt memory is not being freed when the synic is shutdown or when there is an allocation error. Add the appropriate kfree() call, along with a comment to clarify how the memory gets freed after an allocation error. Make the free path consistent by removing checks for NULL since kfree() and free_page() already do the check. Signed-off-by: Michael Kelley Reported-by: Dan Carpenter Signed-off-by: K. Y. Srinivasan --- drivers/hv/hv.c | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/hv/hv.c b/drivers/hv/hv.c index 312fe5ed7c40..748a1c4172a6 100644 --- a/drivers/hv/hv.c +++ b/drivers/hv/hv.c @@ -242,6 +242,10 @@ int hv_synic_alloc(void) return 0; err: + /* +* Any memory allocations that succeeded will be freed when +* the caller cleans up by calling hv_synic_free() +*/ return -ENOMEM; } @@ -254,12 +258,10 @@ void hv_synic_free(void) struct hv_per_cpu_context *hv_cpu = per_cpu_ptr(hv_context.cpu_context, cpu); - if (hv_cpu->synic_event_page) - free_page((unsigned long)hv_cpu->synic_event_page); - if (hv_cpu->synic_message_page) - free_page((unsigned long)hv_cpu->synic_message_page); - if (hv_cpu->post_msg_page) - free_page((unsigned long)hv_cpu->post_msg_page); + kfree(hv_cpu->clk_evt); + free_page((unsigned long)hv_cpu->synic_event_page); + free_page((unsigned long)hv_cpu->synic_message_page); + free_page((unsigned long)hv_cpu->post_msg_page); } kfree(hv_context.hv_numa_map); -- 2.17.1 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH 2/3] Drivers: hv: vmbus: Remove use of slow_virt_to_phys()
From: Michael Kelley
slow_virt_to_phys() is only implemented for arch/x86.
Remove its use in arch independent Hyper-V drivers, and
replace with test for vmalloc() address followed by
appropriate v-to-p function. This follows the typical
pattern of other drivers and avoids the need to implement
slow_virt_to_phys() for Hyper-V on ARM64.
Signed-off-by: Michael Kelley
Signed-off-by: K. Y. Srinivasan
---
drivers/hv/channel.c | 27 ---
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/hv/channel.c b/drivers/hv/channel.c
index c3949220b770..741857d80da1 100644
--- a/drivers/hv/channel.c
+++ b/drivers/hv/channel.c
@@ -29,12 +29,26 @@
#include
#include
#include
+#include
#include "hyperv_vmbus.h"
#define NUM_PAGES_SPANNED(addr, len) \
((PAGE_ALIGN(addr + len) >> PAGE_SHIFT) - (addr >> PAGE_SHIFT))
+static unsigned long virt_to_hvpfn(void *addr)
+{
+ unsigned long paddr;
+
+ if (is_vmalloc_addr(addr))
+ paddr = page_to_phys(vmalloc_to_page(addr)) +
+offset_in_page(addr);
+ else
+ paddr = __pa(addr);
+
+ return paddr >> PAGE_SHIFT;
+}
+
/*
* vmbus_setevent- Trigger an event notification on the specified
* channel.
@@ -298,8 +312,8 @@ static int create_gpadl_header(void *kbuffer, u32 size,
gpadl_header->range[0].byte_offset = 0;
gpadl_header->range[0].byte_count = size;
for (i = 0; i < pfncount; i++)
- gpadl_header->range[0].pfn_array[i] = slow_virt_to_phys(
- kbuffer + PAGE_SIZE * i) >> PAGE_SHIFT;
+ gpadl_header->range[0].pfn_array[i] = virt_to_hvpfn(
+ kbuffer + PAGE_SIZE * i);
*msginfo = msgheader;
pfnsum = pfncount;
@@ -350,9 +364,8 @@ static int create_gpadl_header(void *kbuffer, u32 size,
* so the hypervisor guarantees that this is ok.
*/
for (i = 0; i < pfncurr; i++)
- gpadl_body->pfn[i] = slow_virt_to_phys(
- kbuffer + PAGE_SIZE * (pfnsum + i)) >>
- PAGE_SHIFT;
+ gpadl_body->pfn[i] = virt_to_hvpfn(
+ kbuffer + PAGE_SIZE * (pfnsum + i));
/* add to msg header */
list_add_tail(&msgbody->msglistentry,
@@ -380,8 +393,8 @@ static int create_gpadl_header(void *kbuffer, u32 size,
gpadl_header->range[0].byte_offset = 0;
gpadl_header->range[0].byte_count = size;
for (i = 0; i < pagecount; i++)
- gpadl_header->range[0].pfn_array[i] = slow_virt_to_phys(
- kbuffer + PAGE_SIZE * i) >> PAGE_SHIFT;
+ gpadl_header->range[0].pfn_array[i] = virt_to_hvpfn(
+ kbuffer + PAGE_SIZE * i);
*msginfo = msgheader;
}
--
2.17.1
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[PATCH 1/3] Drivers: hv: vmbus: Reset the channel callback in vmbus_onoffer_rescind()
From: Dexuan Cui
Before setting channel->rescind in vmbus_rescind_cleanup(), we should make
sure the channel callback won't run any more, otherwise a high-level
driver like pci_hyperv, which may be infinitely waiting for the host VSP's
response and notices the channel has been rescinded, can't safely give
up: e.g., in hv_pci_protocol_negotiation() -> wait_for_response(), it's
unsafe to exit from wait_for_response() and proceed with the on-stack
variable "comp_pkt" popped. The issue was originally spotted by
Michael Kelley .
In vmbus_close_internal(), the patch also minimizes the range protected by
disabling/enabling channel->callback_event: we don't really need that for
the whole function.
Signed-off-by: Dexuan Cui
Reviewed-by: Michael Kelley
Cc: sta...@vger.kernel.org
Cc: K. Y. Srinivasan
Cc: Stephen Hemminger
Cc: Michael Kelley
Signed-off-by: K. Y. Srinivasan
---
drivers/hv/channel.c | 40 +++
drivers/hv/channel_mgmt.c | 6 ++
include/linux/hyperv.h| 2 ++
3 files changed, 32 insertions(+), 16 deletions(-)
diff --git a/drivers/hv/channel.c b/drivers/hv/channel.c
index ba0a092ae085..c3949220b770 100644
--- a/drivers/hv/channel.c
+++ b/drivers/hv/channel.c
@@ -558,11 +558,8 @@ static void reset_channel_cb(void *arg)
channel->onchannel_callback = NULL;
}
-static int vmbus_close_internal(struct vmbus_channel *channel)
+void vmbus_reset_channel_cb(struct vmbus_channel *channel)
{
- struct vmbus_channel_close_channel *msg;
- int ret;
-
/*
* vmbus_on_event(), running in the per-channel tasklet, can race
* with vmbus_close_internal() in the case of SMP guest, e.g., when
@@ -572,6 +569,29 @@ static int vmbus_close_internal(struct vmbus_channel
*channel)
*/
tasklet_disable(&channel->callback_event);
+ channel->sc_creation_callback = NULL;
+
+ /* Stop the callback asap */
+ if (channel->target_cpu != get_cpu()) {
+ put_cpu();
+ smp_call_function_single(channel->target_cpu, reset_channel_cb,
+channel, true);
+ } else {
+ reset_channel_cb(channel);
+ put_cpu();
+ }
+
+ /* Re-enable tasklet for use on re-open */
+ tasklet_enable(&channel->callback_event);
+}
+
+static int vmbus_close_internal(struct vmbus_channel *channel)
+{
+ struct vmbus_channel_close_channel *msg;
+ int ret;
+
+ vmbus_reset_channel_cb(channel);
+
/*
* In case a device driver's probe() fails (e.g.,
* util_probe() -> vmbus_open() returns -ENOMEM) and the device is
@@ -585,16 +605,6 @@ static int vmbus_close_internal(struct vmbus_channel
*channel)
}
channel->state = CHANNEL_OPEN_STATE;
- channel->sc_creation_callback = NULL;
- /* Stop callback and cancel the timer asap */
- if (channel->target_cpu != get_cpu()) {
- put_cpu();
- smp_call_function_single(channel->target_cpu, reset_channel_cb,
-channel, true);
- } else {
- reset_channel_cb(channel);
- put_cpu();
- }
/* Send a closing message */
@@ -639,8 +649,6 @@ static int vmbus_close_internal(struct vmbus_channel
*channel)
get_order(channel->ringbuffer_pagecount * PAGE_SIZE));
out:
- /* re-enable tasklet for use on re-open */
- tasklet_enable(&channel->callback_event);
return ret;
}
diff --git a/drivers/hv/channel_mgmt.c b/drivers/hv/channel_mgmt.c
index f3b551a50653..0f0e091c117c 100644
--- a/drivers/hv/channel_mgmt.c
+++ b/drivers/hv/channel_mgmt.c
@@ -892,6 +892,12 @@ static void vmbus_onoffer_rescind(struct
vmbus_channel_message_header *hdr)
return;
}
+ /*
+* Before setting channel->rescind in vmbus_rescind_cleanup(), we
+* should make sure the channel callback is not running any more.
+*/
+ vmbus_reset_channel_cb(channel);
+
/*
* Now wait for offer handling to complete.
*/
diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h
index 2330f08062c7..efda23cf32c7 100644
--- a/include/linux/hyperv.h
+++ b/include/linux/hyperv.h
@@ -1061,6 +1061,8 @@ extern int vmbus_establish_gpadl(struct vmbus_channel
*channel,
extern int vmbus_teardown_gpadl(struct vmbus_channel *channel,
u32 gpadl_handle);
+void vmbus_reset_channel_cb(struct vmbus_channel *channel);
+
extern int vmbus_recvpacket(struct vmbus_channel *channel,
void *buffer,
u32 bufferlen,
--
2.17.1
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Re: [PATCH] staging: mt29f_spinand: fix memory leak while programming pages
Dear Dan, I know what you wrote, but before the spinand device is removed and freed memory automatically, programming pages may do many many times. Assume we erase and rewrite a large part of the flash, then spinand_program_page() might exhaust memory if memory is not large enough. In fact, OOM indeed occured when I tested programming multi-pages by mtd_debug tool. If OOM was not caused by devm_kzalloc() in spinand_program_page(), what may exhaust memory? Best Regards, ─ Jheng-Jhong Wu (Victor Wu) E-mail: goodwater...@gmail.com ─ ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH v8 00/15] staging: mt7621-pci: avoid custom pci config read and writes
On Thu, Aug 02, 2018 at 08:09:48AM +1000, NeilBrown wrote:
> On Wed, Aug 01 2018, Sergio Paracuellos wrote:
>
> > This patch series include an attempt to avoid the use of custom
> > read and writes in driver code and use PCI subsystem common ones.
> >
> > In order to do this 'map_bus' callback is implemented and also
> > data structures for driver are included. The regs base address
> > ranges and data is being readed from device tree and the driver
> > gets clean a lot of code.
> >
> > This patchet also removes all legacy PCI code using now PCI_DRIVERS_GENERIC
> > kernel api.
> >
> > Changes in v8:
> > - PATCH 1: don't check 'of_pci_range_to_resource' return value which is
> > not
> > being checked for the legacy code.
> > - PATCH 1: call 'mt7621_pci_parse_request_of_pci_ranges' 'and
> > setup_cm_memory_region'
> > after the port initialization code.
> > - PATCH 1: make use of 'pci_host_probe' to avoid code duplication in
> > function
> > 'mt7621_pcie_register_host'.
> > - PATCH 1: set resource limits with no limit for the end in
> > 'ioport_resource' and
> > 'iomem_resource'. It seems mips needs this to work properly.
> > - Other patches rebased and adapted to this changes.
>
> See boot log below. Doesn't hang, but doesn't work.
> I'll try to schedule some time to see if I can work out what is
> happening.
Thanks for this. So the problem here is that PCI_IOBASE is not defined for mips.
I have reviewed al pci drivers included in mips/pci an no one is using actual
code
but legacy one. Also all of them are changing the 'ioport_resource' end limit
to 0x
(as I did in this series) to pass some checks along the code and that it just
works because
the legacy code does not check of_pci_range_to_resource and is using 'ioremap'
at itself.
I have found a very interesting mail thread about this in the linux-mips
mailing list:
https://www.linux-mips.org/archives/linux-mips/2015-12/msg00442.html
So I don't know what should be a good solution. Maybe we should define
PCI_IOBASE properly
in the driver or just call to ioremap with the cpu_adress just changing the
upper limit for
ioport_resource... What do you think? Anyway I am going to send v9 with the
code I think we
should start. It is just getting good things from v6 and this last v8 reducing
code and getting
better code.
>
> Thanks,
> NeilBrown
Best regards,
Sergio Paracuellos
>
>
>
> Starting kernel ...
>
> [0.00] Linux version 4.18.0-rc7+ (neilb@noble) (gcc version 7.2.0
> (GCC)) #273 SMP Thu Aug 2 08:02:45 AEST 2018
> [0.00] SoC Type: MediaTek MT7621 ver:1 eco:3
> [0.00] bootconsole [early0] enabled
> [0.00] CPU0 revision is: 0001992f (MIPS 1004Kc)
> [0.00] MIPS: machine is GB-PC1
> [0.00] Determined physical RAM map:
> [0.00] memory: 1c00 @ (usable)
> [0.00] memory: 0400 @ 2000 (usable)
> [0.00] Initrd not found or empty - disabling initrd
> [0.00] VPE topology {2,2} total 4
> [0.00] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [0.00] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32
> bytes
> [0.00] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [0.00] Zone ranges:
> [0.00] Normal [mem 0x-0x1fff]
> [0.00] HighMem [mem 0x2000-0x23ff]
> [0.00] Movable zone start for each node
> [0.00] Early memory node ranges
> [0.00] node 0: [mem 0x-0x1bff]
> [0.00] node 0: [mem 0x2000-0x23ff]
> [0.00] Initmem setup node 0 [mem
> 0x-0x23ff]
> [0.00] random: get_random_bytes called from start_kernel+0xb4/0x4ec
> with crng_init=0
> [0.00] percpu: Embedded 15 pages/cpu @(ptrval) s30480 r8192 d22768
> u61440
> [0.00] Built 1 zonelists, mobility grouping on. Total pages: 130048
> [0.00] Kernel command line: console=ttyS0,57600
> [0.00] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
> [0.00] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
> [0.00] Writing ErrCtl register=000108a2
> [0.00] Readback ErrCtl register=000108a2
> [0.00] Memory: 504788K/524288K available (6135K kernel code, 228K
> rwdata, 1052K rodata, 6524K init, 241K bss, 19500K reserved, 0K cma-reserved,
> 65536K highmem)
> [0.00] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
> [0.00] Hierarchical RCU implementation.
> [0.00] NR_IRQS: 256
> [0.00] clocksource: GIC: mask: 0x max_cycles:
> 0xcf914c9718, max_idle_ns: 440795231327 ns
> [0.00] sched_clock: 32 bits at 100 Hz, resolution 1000ns, wraps
> every 2147483647500ns
> [0.01] Calibrating delay loop... 597.60 BogoMIPS (l
Re: [PATCH] staging: mt29f_spinand: fix memory leak while programming pages
On Thu, Aug 02, 2018 at 11:42:30AM +0800, Jheng-Jhong Wu wrote: > Dear Dan, > > I know what you wrote, but before the spinand device is removed and > freed memory automatically, programming pages may do many many times. > Assume we erase and rewrite a large part of the flash, then > spinand_program_page() might exhaust memory if memory is not large > enough. > In fact, OOM indeed occured when I tested programming multi-pages by > mtd_debug tool. > If OOM was not caused by devm_kzalloc() in spinand_program_page(), > what may exhaust memory? > Ok. That makes sense. I didn't look at it in context. You should say that sort of thing in your changelog. Looking at it now, the devm_ model isn't right for this function so we should change it to use normal kzalloc(). We should fix all the error paths as well. It looks like if this function starts returning errors, we are probably toasted, but it's still good practice to avoid slow leaks. regards, dan carpenter ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v9 00/15] staging: mt7621-pci: avoid custom pci config read and writes
This patch series include an attempt to avoid the use of custom read and writes in driver code and use PCI subsystem common ones. In order to do this 'map_bus' callback is implemented and also data structures for driver are included. The regs base address ranges and data is being readed from device tree and the driver gets clean a lot of code. This patchet also removes all legacy PCI code using now PCI_DRIVERS_GENERIC kernel api. Changes in v9: - PATCH 1: Use 'res' as resources list and void store resources in the pcie data struct. - PATCH 1: Rewrite 'mt7621_pci_parse_request_of_pci_ranges' to use 'devm_of_pci_get_host_bridge_resources' and use 'remap' directly with the returned 'iobase' address instead of 'devm_pci_remap_iospace' which get into a WARN_ONCE statement because 'PCI_IOBASE' is not defined for mips. - Other patches rebased and adapted to this changes. Changes in v8: - PATCH 1: don't check 'of_pci_range_to_resource' return value which is not being checked for the legacy code. - PATCH 1: call 'mt7621_pci_parse_request_of_pci_ranges' 'and setup_cm_memory_region' after the port initialization code. - PATCH 1: make use of 'pci_host_probe' to avoid code duplication in function 'mt7621_pcie_register_host'. - PATCH 1: set resource limits with no limit for the end in 'ioport_resource' and 'iomem_resource'. It seems mips needs this to work properly. - Other patches rebased and adapted to this changes. Changes in v7: - PATCH 1: Store resources in mt7621_pci data structure. - PATCH 1: Change completely function mt7621_pci_parse_request_of_pci_ranges to parse resources from ranges manually instead of use the function devm_of_pci_get_host_bridge_resources. This is closer to the mips pci legacy code. - PATCH 1: Create 'mt7621_pcie_request_resources' function to request resources parsed from ranges property in the DT. Use pci_add_resource_offset and set them manually like the mips pci-legacy code do. - PATCH 1: don't delete function setup_cm_memory_region and call it with memory resource. - Other patches rebased and adapted to this changes. Changes in v6: - Reorder patches to be each patch correct in itself. - PATCH 1 adds also Kconfig to do the step from legacy to generic code - PATCH 1 remaps io space using devm_pci_remap_iospace for io resource in a new function called 'mt7621_pci_parse_request_of_pci_ranges'. - Other patches rebased and adapted with this changes. Changes in v5: - Include driver Kconfig file to add compilation depends of PCI_DRIVERS_GENERIC. The new added configuration option is CONFIG_PCI_MT7621. - Add list_splice_init(&res, &bridge->windows); in PATCH 1 to set windows from resources obtanined from devm_request_pci_bus_resources. - Move devm_of_pci_get_host_bridge_resources and devm_request_pci_bus_resources after the ports initialization legacy code. - Add pcie ports 1 and 2 RC registers to device tree. There was only being included port RC register for port 0. - Review includes and order them alphabetically. Changes in v4: - Rebased onto staging-next. Changes in v3: - Include new patches to delete all RALINK_BASE definition dependant code and be able to avoid use of pci_legacy code. - use devm_of_pci_get_host_bridge_resources, devm_request_pci_bus_resources and pci_scan_root_bus_bridge and pci_bus_add_devices Changes in v2: - squash PATCH 1 and PATCH 2 of previous series in only PATCH 1 - Change name for host structure. - Create a new port structure (platform has 3 pcie controllers) - Replace the use of pci_generic_config_[read|write]32 in favour of pci_generic_config_[read|write] and change map_bus implemen- tation for hopefully the right one. Best regards, Sergio Paracuellos Sergio Paracuellos (15): staging: mt7621-pci: use generic kernel pci subsystem read and write staging: mt7621-pci: remove dead code derived to not use custom reads and writes staging: mt7621-pci: add pcie_write and pcie_read helpers staging: mt7621-pci: use pcie_[read|write] in [write|read]_config staging: mt7621-pci: simplify read_config function staging: mt7621-pci: simplify write_config function staging: mt7621-pci: remove unused macros staging: mt7621-pci: avoid register duplication per controller using pcie_[read|write] staging: mt7621-pci: review includes putting them in alphabethic order staging: mt7621-pci: use pcie_[read|write] in RALINK_PCI_PCICFG_ADDR and RALINK_PCI_PCIMSK_ADDR staging: mt7621-pci: remove RALINK_PCI_BASE from remaining definitions staging: mt7621-pci: use BIT macro in preprocessor definitions staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG definition staging: mt7621-pci: remove remaining pci_legacy dependant code staging: mt7621-dts: add p
[PATCH v9 07/15] staging: mt7621-pci: remove unused macros
There some macros that are not being used. Remove them. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 24 +--- 1 file changed, 1 insertion(+), 23 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index aa95457..65c573c 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -84,7 +84,6 @@ #define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C) #define RALINK_PCI_BASE0xBE14 -#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000) #define RT6855_PCIE0_OFFSET0x2000 #define RT6855_PCIE1_OFFSET0x3000 #define RT6855_PCIE2_OFFSET0x4000 @@ -95,8 +94,6 @@ #define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034) #define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038) #define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050) -#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060) -#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064) #define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010) #define RALINK_PCI1_IMBASEBAR0_ADDR*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018) @@ -104,8 +101,6 @@ #define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034) #define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038) #define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050) -#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060) -#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064) #define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010) #define RALINK_PCI2_IMBASEBAR0_ADDR*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018) @@ -113,17 +108,10 @@ #define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034) #define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038) #define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050) -#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060) -#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064) #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000) #define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000) -#define MV_WRITE(ofs, data)\ - *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data) -#define MV_READ(ofs, data) \ - *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs))) - #define RALINK_PCI_MM_MAP_BASE 0x6000 #define RALINK_PCI_IO_MAP_BASE 0x1e16 @@ -141,28 +129,18 @@ else\ rt_sysc_m32(0, val, RALINK_RSTCTRL);\ } while (0) + #define RALINK_CLKCFG1 0x30 #define RALINK_RSTCTRL 0x34 #define RALINK_GPIOMODE0x60 #define RALINK_PCIE_CLK_GEN0x7c #define RALINK_PCIE_CLK_GEN1 0x80 -#define PPLL_CFG1 0x9c -#define PPLL_DRV 0xa0 -/* SYSC_REG_SYSTEM_CONFIG1 bits */ -#define RALINK_PCI_HOST_MODE_EN(1<<7) -#define RALINK_PCIE_RC_MODE_EN (1<<8) //RALINK_RSTCTRL bit #define RALINK_PCIE_RST(1<<23) #define RALINK_PCI_RST (1<<24) //RALINK_CLKCFG1 bit #define RALINK_PCI_CLK_EN (1<<19) #define RALINK_PCIE_CLK_EN (1<<21) -//RALINK_GPIOMODE bit -#define PCI_SLOTx2 (1<<11) -#define PCI_SLOTx1 (2<<11) -//MTK PCIE PLL bit -#define PDRV_SW_SET(1<<31) -#define LC_CKDRVPD_(1<<19) #define MEMORY_BASE 0x0 static int pcie_link_status = 0; -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v9 06/15] staging: mt7621-pci: simplify write_config function
write_config function is always called with bus and func
being 0. Avoid those params and just use 0 inside the
function. Review parameter types changing for more proper
ones.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index c724165..aa95457 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -238,11 +238,9 @@ read_config(struct mt7621_pcie *pcie, unsigned int dev,
u32 reg)
}
static void
-write_config(struct mt7621_pcie *pcie,
-unsigned long bus, unsigned long dev,
-unsigned long func, unsigned long reg, unsigned long val)
+write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val)
{
- u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+ u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
@@ -257,7 +255,7 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
int irq;
if (dev->bus->number == 0) {
- write_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
+ write_config(pcie, slot, PCI_BASE_ADDRESS_0, MEMORY_BASE);
val = read_config(pcie, slot, PCI_BASE_ADDRESS_0);
printk("BAR0 at slot %d = %x\n", slot, val);
}
@@ -672,27 +670,27 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
switch (pcie_link_status) {
case 7:
val = read_config(pcie, 2, 0x4);
- write_config(pcie, 0, 2, 0, 0x4, val|0x4);
+ write_config(pcie, 2, 0x4, val|0x4);
val = read_config(pcie, 2, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
- write_config(pcie, 0, 2, 0, 0x70c, val);
+ write_config(pcie, 2, 0x70c, val);
case 3:
case 5:
case 6:
val = read_config(pcie, 1, 0x4);
- write_config(pcie, 0, 1, 0, 0x4, val|0x4);
+ write_config(pcie, 1, 0x4, val|0x4);
val = read_config(pcie, 1, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
- write_config(pcie, 0, 1, 0, 0x70c, val);
+ write_config(pcie, 1, 0x70c, val);
default:
val = read_config(pcie, 0, 0x4);
- write_config(pcie, 0, 0, 0, 0x4, val|0x4); //bus master enable
+ write_config(pcie, 0, 0x4, val|0x4); //bus master enable
val = read_config(pcie, 0, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
- write_config(pcie, 0, 0, 0, 0x70c, val);
+ write_config(pcie, 0, 0x70c, val);
}
err = mt7621_pci_parse_request_of_pci_ranges(pcie, &res);
--
2.7.4
___
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[PATCH v9 03/15] staging: mt7621-pci: add pcie_write and pcie_read helpers
Introdice this functions to make easier to write/read to/from
an offset relative to base address
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index a82fd01..c170cd5 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -193,6 +193,16 @@ struct mt7621_pcie {
struct list_head ports;
};
+static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
+{
+ return readl(pcie->base + reg);
+}
+
+static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
+{
+ writel(val, pcie->base + reg);
+}
+
static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
unsigned int func, unsigned int where)
{
--
2.7.4
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[PATCH v9 10/15] staging: mt7621-pci: use pcie_[read|write] in RALINK_PCI_PCICFG_ADDR and RALINK_PCI_PCIMSK_ADDR
RALINK_PCI_PCICFG_ADDR and RALINK_PCI_PCIMSK_ADDR are defined to be directly
referenced for read and write. Use pcie_read and pcie_write instead changing
its definition to a simple relative offset to pcie base address.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 54 +
1 file changed, 34 insertions(+), 20 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 4dcb881..696d967 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -74,8 +74,8 @@
#define RALINK_PCIE1_RST (1<<25)
#define RALINK_PCIE2_RST (1<<26)
-#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE +
0x)
-#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE +
0x000C)
+#define RALINK_PCI_PCICFG_ADDR 0x
+#define RALINK_PCI_PCIMSK_ADDR 0x000C
#define RALINK_PCI_BASE0xBE14
#define RT6855_PCIE0_OFFSET0x2000
@@ -530,7 +530,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
pcie_link_status &= ~(1<<0);
} else {
pcie_link_status |= 1<<0;
- RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
+ val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+ val |= (1<<20); // enable pcie1 interrupt
+ pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
}
if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
@@ -540,7 +542,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
pcie_link_status &= ~(1<<1);
} else {
pcie_link_status |= 1<<1;
- RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
+ val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+ val |= (1<<21); // enable pcie1 interrupt
+ pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
}
if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
@@ -550,7 +554,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
pcie_link_status &= ~(1<<2);
} else {
pcie_link_status |= 1<<2;
- RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
+ val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+ val |= (1<<22); // enable pcie2 interrupt
+ pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
}
if (pcie_link_status == 0)
@@ -569,27 +575,35 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
*/
switch (pcie_link_status) {
case 2:
- RALINK_PCI_PCICFG_ADDR &= ~0x00ff;
- RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;//port0
- RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;//port1
+ val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+ val &= ~0x00ff;
+ val |= 0x1 << 16; // port 0
+ val |= 0x0 << 20; // port 1
+ pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
break;
case 4:
- RALINK_PCI_PCICFG_ADDR &= ~0x0fff;
- RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;//port0
- RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;//port1
- RALINK_PCI_PCICFG_ADDR |= 0x0 << 24;//port2
+ val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+ val &= ~0x0fff;
+ val |= 0x1 << 16; //port0
+ val |= 0x2 << 20; //port1
+ val |= 0x0 << 24; //port2
+ pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
break;
case 5:
- RALINK_PCI_PCICFG_ADDR &= ~0x0fff;
- RALINK_PCI_PCICFG_ADDR |= 0x0 << 16;//port0
- RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;//port1
- RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;//port2
+ val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+ val &= ~0x0fff;
+ val |= 0x0 << 16; //port0
+ val |= 0x2 << 20; //port1
+ val |= 0x1 << 24; //port2
+ pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
break;
case 6:
- RALINK_PCI_PCICFG_ADDR &= ~0x0fff;
- RALINK_PCI_PCICFG_ADDR |= 0x2 << 16;//port0
- RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;//port1
- RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;//port2
+ val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+ val &= ~0x0fff;
+ val |= 0x2 << 16; //port0
+ val |= 0x0 << 20; //port1
+ val |= 0x1 << 24; //port2
+ pcie_write(pcie, val, RAL
[PATCH v9 02/15] staging: mt7621-pci: remove dead code derived to not use custom reads and writes
Driver is using now pci subsystem generics reads and writes and requesting
bus resources without using legacy code functions. Because of this there is
a lot of dead code that can be removed.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 128
1 file changed, 128 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index fb2618a..a82fd01 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -123,15 +123,6 @@
*(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
#define MV_READ(ofs, data) \
*(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
-#define MV_WRITE_16(ofs, data) \
- *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
-#define MV_READ_16(ofs, data) \
- *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
-
-#define MV_WRITE_8(ofs, data) \
- *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
-#define MV_READ_8(ofs, data) \
- *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
#define RALINK_PCI_MM_MAP_BASE 0x6000
#define RALINK_PCI_IO_MAP_BASE 0x1e16
@@ -176,13 +167,6 @@
#define MEMORY_BASE 0x0
static int pcie_link_status = 0;
-#define PCI_ACCESS_READ_1 0
-#define PCI_ACCESS_READ_2 1
-#define PCI_ACCESS_READ_4 2
-#define PCI_ACCESS_WRITE_1 3
-#define PCI_ACCESS_WRITE_2 4
-#define PCI_ACCESS_WRITE_4 5
-
/**
* struct mt7621_pcie_port - PCIe port information
* @base: IO mapped register base
@@ -216,118 +200,6 @@ static inline u32 mt7621_pci_get_cfgaddr(unsigned int
bus, unsigned int slot,
(func << 8) | (where & 0xfc) | 0x8000;
}
-static int config_access(unsigned char access_type, struct pci_bus *bus,
- unsigned int devfn, unsigned int where, u32 *data)
-{
- unsigned int slot = PCI_SLOT(devfn);
- u8 func = PCI_FUNC(devfn);
- u32 address_reg, data_reg;
- unsigned int address;
-
- address_reg = RALINK_PCI_CONFIG_ADDR;
- data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
-
- address = mt7621_pci_get_cfgaddr(bus->number, slot, func, where);
-
- MV_WRITE(address_reg, address);
-
- switch (access_type) {
- case PCI_ACCESS_WRITE_1:
- MV_WRITE_8(data_reg+(where&0x3), *data);
- break;
- case PCI_ACCESS_WRITE_2:
- MV_WRITE_16(data_reg+(where&0x3), *data);
- break;
- case PCI_ACCESS_WRITE_4:
- MV_WRITE(data_reg, *data);
- break;
- case PCI_ACCESS_READ_1:
- MV_READ_8(data_reg+(where&0x3), data);
- break;
- case PCI_ACCESS_READ_2:
- MV_READ_16(data_reg+(where&0x3), data);
- break;
- case PCI_ACCESS_READ_4:
- MV_READ(data_reg, data);
- break;
- default:
- printk("no specify access type\n");
- break;
- }
- return 0;
-}
-
-static int
-read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 *val)
-{
- return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned
int)where, (u32 *)val);
-}
-
-static int
-read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 *val)
-{
- return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned
int)where, (u32 *)val);
-}
-
-static int
-read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 *val)
-{
- return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned
int)where, (u32 *)val);
-}
-
-static int
-write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
-{
- if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where,
(u32 *)&val))
- return -1;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
-{
- if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
- return -1;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
-{
- if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
- return -1;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size,
u32 *val)
-{
- switch (size) {
- case 1:
- return read_config_byte(bus, devfn, where, (u8 *) val);
- case 2:
- return read_config_word(bus, devfn, where, (u16 *) val);
- default:
- return read_config_dword(bus, devfn, where, val);
- }
-}
-
-static int
-pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size,
u32 val)
-{
- switch (size) {
- case 1:
- return write_con
[PATCH v9 04/15] staging: mt7621-pci: use pcie_[read|write] in [write|read]_config
Instead of custom macros use pcie_read and pcie_write functions.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 67 -
1 file changed, 32 insertions(+), 35 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index c170cd5..d5b939d 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -229,41 +229,38 @@ struct pci_ops mt7621_pci_ops = {
};
static void
-read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned
long reg, unsigned long *val)
+read_config(struct mt7621_pcie *pcie,
+ unsigned long bus, unsigned long dev,
+ unsigned long func, unsigned long reg, unsigned long *val)
{
- u32 address_reg, data_reg, address;
-
- address_reg = RALINK_PCI_CONFIG_ADDR;
- data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
- address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
- MV_WRITE(address_reg, address);
- MV_READ(data_reg, val);
- return;
+ u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+
+ pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
+ *val = pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
}
static void
-write_config(unsigned long bus, unsigned long dev, unsigned long func,
unsigned long reg, unsigned long val)
+write_config(struct mt7621_pcie *pcie,
+unsigned long bus, unsigned long dev,
+unsigned long func, unsigned long reg, unsigned long val)
{
- u32 address_reg, data_reg, address;
-
- address_reg = RALINK_PCI_CONFIG_ADDR;
- data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
- address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
- MV_WRITE(address_reg, address);
- MV_WRITE(data_reg, val);
- return;
+ u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+
+ pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
+ pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
}
int
pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
+ struct mt7621_pcie *pcie = dev->bus->sysdata;
u16 cmd;
u32 val;
int irq;
if (dev->bus->number == 0) {
- write_config(0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
- read_config(0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long
*)&val);
+ write_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
+ read_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned
long *)&val);
printk("BAR0 at slot %d = %x\n", slot, val);
}
@@ -549,13 +546,13 @@ static int mt7621_pci_probe(struct platform_device *pdev)
bypass_pipe_rst();
set_phy_for_ssc();
- read_config(0, 0, 0, 0x70c, &val);
+ read_config(pcie, 0, 0, 0, 0x70c, &val);
printk("Port 0 N_FTS = %x\n", (unsigned int)val);
- read_config(0, 1, 0, 0x70c, &val);
+ read_config(pcie, 0, 1, 0, 0x70c, &val);
printk("Port 1 N_FTS = %x\n", (unsigned int)val);
- read_config(0, 2, 0, 0x70c, &val);
+ read_config(pcie, 0, 2, 0, 0x70c, &val);
printk("Port 2 N_FTS = %x\n", (unsigned int)val);
rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
@@ -676,28 +673,28 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
switch (pcie_link_status) {
case 7:
- read_config(0, 2, 0, 0x4, &val);
- write_config(0, 2, 0, 0x4, val|0x4);
- read_config(0, 2, 0, 0x70c, &val);
+ read_config(pcie, 0, 2, 0, 0x4, &val);
+ write_config(pcie, 0, 2, 0, 0x4, val|0x4);
+ read_config(pcie, 0, 2, 0, 0x70c, &val);
val &= ~(0xff)<<8;
val |= 0x50<<8;
- write_config(0, 2, 0, 0x70c, val);
+ write_config(pcie, 0, 2, 0, 0x70c, val);
case 3:
case 5:
case 6:
- read_config(0, 1, 0, 0x4, &val);
- write_config(0, 1, 0, 0x4, val|0x4);
- read_config(0, 1, 0, 0x70c, &val);
+ read_config(pcie, 0, 1, 0, 0x4, &val);
+ write_config(pcie, 0, 1, 0, 0x4, val|0x4);
+ read_config(pcie, 0, 1, 0, 0x70c, &val);
val &= ~(0xff)<<8;
val |= 0x50<<8;
- write_config(0, 1, 0, 0x70c, val);
+ write_config(pcie, 0, 1, 0, 0x70c, val);
default:
- read_config(0, 0, 0, 0x4, &val);
- write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
- read_config(0, 0, 0, 0x70c, &val);
+ read_config(pcie, 0, 0, 0, 0x4, &val);
+ write_config(pcie, 0, 0, 0, 0x4, val|0x4); //bus master enable
+ read_config(pcie, 0, 0, 0, 0x70c, &val);
val &= ~(0xff)<<8;
val |= 0x5
[PATCH v9 09/15] staging: mt7621-pci: review includes putting them in alphabethic order
There are some includes that are being used that are not really needed to correct driver compilation. Remove them and reorder the rest alphabetically. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 22 -- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 2533dfc..4dcb881 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -40,26 +40,20 @@ ** */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include +#include #include +#include #include -#include -#include #include #include +#include +#include +#include #include - -#include +#include #include +#include #include "../../pci/pci.h" -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v9 01/15] staging: mt7621-pci: use generic kernel pci subsystem read and write
map_bus callback is called before every .read/.write operation.
Implement it and change custom read write operations for the
pci subsystem generics. Make the probe function to don't use
legacy stuff and request bus resources directly. Get pci register
base and ranges from device tree.
The driver is not using PCI_LEGACY code anymore and shall use the
PCI_DRIVERS_GENERIC option to correct compile it. Add also new
Kconfig file for this controller setting there its correct dependencies.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/Kconfig | 2 +
drivers/staging/mt7621-pci/Kconfig | 7 ++
drivers/staging/mt7621-pci/pci-mt7621.c | 195 +---
3 files changed, 187 insertions(+), 17 deletions(-)
create mode 100644 drivers/staging/mt7621-pci/Kconfig
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index 2bce647..732b631 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -110,6 +110,8 @@ source "drivers/staging/vboxvideo/Kconfig"
source "drivers/staging/pi433/Kconfig"
+source "drivers/staging/mt7621-pci/Kconfig"
+
source "drivers/staging/mt7621-pinctrl/Kconfig"
source "drivers/staging/mt7621-spi/Kconfig"
diff --git a/drivers/staging/mt7621-pci/Kconfig
b/drivers/staging/mt7621-pci/Kconfig
new file mode 100644
index 000..d335338
--- /dev/null
+++ b/drivers/staging/mt7621-pci/Kconfig
@@ -0,0 +1,7 @@
+config PCI_MT7621
+ tristate "MediaTek MT7621 PCI Controller"
+ depends on RALINK
+ select PCI_DRIVERS_GENERIC
+ help
+ This selects a driver for the MediaTek MT7621 PCI Controller.
+
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 650e49b..fb2618a 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -53,11 +53,16 @@
#include
#include
#include
+#include
+#include
+#include
#include
#include
#include
+#include "../../pci/pci.h"
+
/*
* These functions and structures provide the BIOS scan and mapping of the PCI
* devices.
@@ -178,6 +183,32 @@ static int pcie_link_status = 0;
#define PCI_ACCESS_WRITE_2 4
#define PCI_ACCESS_WRITE_4 5
+/**
+ * struct mt7621_pcie_port - PCIe port information
+ * @base: IO mapped register base
+ * @list: port list
+ * @pcie: pointer to PCIe host info
+ * @reset: pointer to port reset control
+ */
+struct mt7621_pcie_port {
+ void __iomem *base;
+ struct list_head list;
+ struct mt7621_pcie *pcie;
+ struct reset_control *reset;
+};
+
+/**
+ * struct mt7621_pcie - PCIe host information
+ * @base: IO Mapped Register Base
+ * @dev: Pointer to PCIe device
+ * @ports: pointer to PCIe port information
+ */
+struct mt7621_pcie {
+ void __iomem *base;
+ struct device *dev;
+ struct list_head ports;
+};
+
static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
unsigned int func, unsigned int where)
{
@@ -297,17 +328,22 @@ pci_config_write(struct pci_bus *bus, unsigned int devfn,
int where, int size, u
}
}
-struct pci_ops mt7621_pci_ops = {
- .read = pci_config_read,
- .write = pci_config_write,
-};
+static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
+unsigned int devfn, int where)
+{
+ struct mt7621_pcie *pcie = bus->sysdata;
+ u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+PCI_FUNC(devfn), where);
+
+ writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
+
+ return pcie->base + RALINK_PCI_CONFIG_DATA_VIRTUAL_REG + (where & 3);
+}
-static struct resource mt7621_res_pci_mem1;
-static struct resource mt7621_res_pci_io1;
-static struct pci_controller mt7621_controller = {
- .pci_ops= &mt7621_pci_ops,
- .mem_resource = &mt7621_res_pci_mem1,
- .io_resource= &mt7621_res_pci_io1,
+struct pci_ops mt7621_pci_ops = {
+ .map_bus= mt7621_pcie_map_bus,
+ .read = pci_generic_config_read,
+ .write = pci_generic_config_write,
};
static void
@@ -463,9 +499,10 @@ set_phy_for_ssc(void)
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1,
0x00); // rg_pe1_frc_phy_en//Force Port 0 disable control
}
-void setup_cm_memory_region(struct resource *mem_resource)
+static void setup_cm_memory_region(struct resource *mem_resource)
{
resource_size_t mask;
+
if (mips_cps_numiocu(0)) {
/* FIXME: hardware doesn't accept mask values with 1s after
* 0s (e.g. 0xffef), so it would be great to warn if that's
@@ -480,14 +517,130 @@ void setup_cm_memory_region(struct resource
*mem_resource)
}
}
+static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie,
+
[PATCH v9 11/15] staging: mt7621-pci: remove RALINK_PCI_BASE from remaining definitions
RALINK_PCI_BASE has no sense and this driver has base address readed
and mapped from device tree. Remove remaining uses of it and
change code to use pcie_read and pcie_write functions in places
where this was being used.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 131
1 file changed, 67 insertions(+), 64 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 696d967..288f83a 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -76,7 +76,6 @@
#define RALINK_PCI_PCICFG_ADDR 0x
#define RALINK_PCI_PCIMSK_ADDR 0x000C
-#define RALINK_PCI_BASE0xBE14
#define RT6855_PCIE0_OFFSET0x2000
#define RT6855_PCIE1_OFFSET0x3000
@@ -89,8 +88,8 @@
#define RALINK_PCI_SUBID 0x0038
#define RALINK_PCI_STATUS 0x0050
-#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
-#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
+#define RALINK_PCIEPHY_P0P1_CTL_OFFSET 0x9000
+#define RALINK_PCIEPHY_P2_CTL_OFFSET 0xA000
#define RALINK_PCI_MM_MAP_BASE 0x6000
#define RALINK_PCI_IO_MAP_BASE 0x1e16
@@ -231,105 +230,109 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8
pin)
}
void
-set_pcie_phy(u32 *addr, int start_b, int bits, int val)
+set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
+int start_b, int bits, int val)
{
- *(unsigned int *)(addr) &= ~(((1<> 6) & 0x7;
/* Set PCIe Port0 & Port1 PHY to disable SSC */
/* Debug Xtal Type */
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1,
0x01); // rg_pe1_frc_h_xtal_type
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2,
0x00); // rg_pe1_h_xtal_type
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1,
0x01); // rg_pe1_frc_phy_en//Force Port 0 enable control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1,
0x01); // rg_pe1_frc_phy_en//Force Port 1 enable control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1,
0x00); // rg_pe1_phy_en//Port 0 disable
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1,
0x00); // rg_pe1_phy_en//Port 1 disable
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1,
0x01); // rg_pe1_frc_h_xtal_type
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2,
0x00); // rg_pe1_h_xtal_type
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1,
0x01); // rg_pe1_frc_phy_en//Force Port 0 enable control
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1,
0x01); // rg_pe1_frc_phy_en//Force Port 1 enable control
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1,
0x00); // rg_pe1_phy_en//Port 0 disable
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1,
0x00); // rg_pe1_phy_en//Port 1 disable
if (reg <= 5 && reg >= 3) { // 40MHz Xtal
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),
6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),
6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
printk("* Xtal 40MHz *\n");
} else {// 25MHz | 20MHz Xtal
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),
6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
+ set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),
6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
if (reg >= 6) {
printk("* Xtal 25MHz *\n");
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x49c), 0, 31, 0x1800); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO
PCW (for host mode)
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x4a4), 0, 16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither
period control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x4a8), 0, 12, 0x4a);// RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither
amplitude control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x4a8), 16, 12, 0x4a);// RG_PE1_H_LCDDS_SSC_DELTA1//DDS SSC dither
amplitude control for initial
+
[PATCH v9 13/15] staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG definition
RALINK_PCI_CONFIG_DATA_VIRTUAL_REG is a very long name. Make it a bit
shorter renaming it to RALINK_PCI_CONFIG_DATA.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index d6f4085..491dda7 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -67,7 +67,7 @@
#define RALINK_PCIE2_CLK_ENBIT(26)
#define RALINK_PCI_CONFIG_ADDR 0x20
-#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
+#define RALINK_PCI_CONFIG_DATA 0x24
#define RALINK_PCI_MEMBASE 0x28
#define RALINK_PCI_IOBASE 0x2C
#define RALINK_PCIE0_RST BIT(24)
@@ -176,7 +176,7 @@ static void __iomem *mt7621_pcie_map_bus(struct pci_bus
*bus,
writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
- return pcie->base + RALINK_PCI_CONFIG_DATA_VIRTUAL_REG + (where & 3);
+ return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
}
struct pci_ops mt7621_pci_ops = {
@@ -191,7 +191,7 @@ read_config(struct mt7621_pcie *pcie, unsigned int dev, u32
reg)
u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
- return pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
+ return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
}
static void
@@ -200,7 +200,7 @@ write_config(struct mt7621_pcie *pcie, unsigned int dev,
u32 reg, u32 val)
u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
- pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
+ pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
}
int
--
2.7.4
___
devel mailing list
de...@linuxdriverproject.org
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[PATCH v9 12/15] staging: mt7621-pci: use BIT macro in preprocessor definitions
Some preprocessor definitions are using a custom implementation of BIT macro. Just use linux kernel BIT macro instead. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 288f83a..d6f4085 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -62,17 +62,17 @@ * devices. */ -#define RALINK_PCIE0_CLK_EN(1<<24) -#define RALINK_PCIE1_CLK_EN(1<<25) -#define RALINK_PCIE2_CLK_EN(1<<26) +#define RALINK_PCIE0_CLK_ENBIT(24) +#define RALINK_PCIE1_CLK_ENBIT(25) +#define RALINK_PCIE2_CLK_ENBIT(26) #define RALINK_PCI_CONFIG_ADDR 0x20 #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24 #define RALINK_PCI_MEMBASE 0x28 #define RALINK_PCI_IOBASE 0x2C -#define RALINK_PCIE0_RST (1<<24) -#define RALINK_PCIE1_RST (1<<25) -#define RALINK_PCIE2_RST (1<<26) +#define RALINK_PCIE0_RST BIT(24) +#define RALINK_PCIE1_RST BIT(25) +#define RALINK_PCIE2_RST BIT(26) #define RALINK_PCI_PCICFG_ADDR 0x #define RALINK_PCI_PCIMSK_ADDR 0x000C @@ -115,11 +115,11 @@ #define RALINK_PCIE_CLK_GEN0x7c #define RALINK_PCIE_CLK_GEN1 0x80 //RALINK_RSTCTRL bit -#define RALINK_PCIE_RST(1<<23) -#define RALINK_PCI_RST (1<<24) +#define RALINK_PCIE_RSTBIT(23) +#define RALINK_PCI_RST BIT(24) //RALINK_CLKCFG1 bit -#define RALINK_PCI_CLK_EN (1<<19) -#define RALINK_PCIE_CLK_EN (1<<21) +#define RALINK_PCI_CLK_EN BIT(19) +#define RALINK_PCIE_CLK_EN BIT(21) #define MEMORY_BASE 0x0 static int pcie_link_status = 0; -- 2.7.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH v9 05/15] staging: mt7621-pci: simplify read_config function
read_config function is always called with bus and func
being 0. Avoid those params and just use 0 inside the
function. Return readed value instead pass a reference
parameter.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 32 +++-
1 file changed, 15 insertions(+), 17 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index d5b939d..c724165 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -228,15 +228,13 @@ struct pci_ops mt7621_pci_ops = {
.write = pci_generic_config_write,
};
-static void
-read_config(struct mt7621_pcie *pcie,
- unsigned long bus, unsigned long dev,
- unsigned long func, unsigned long reg, unsigned long *val)
+static u32
+read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
{
- u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+ u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
- *val = pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
+ return pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
}
static void
@@ -260,7 +258,7 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
if (dev->bus->number == 0) {
write_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
- read_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned
long *)&val);
+ val = read_config(pcie, slot, PCI_BASE_ADDRESS_0);
printk("BAR0 at slot %d = %x\n", slot, val);
}
@@ -494,7 +492,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
struct mt7621_pcie *pcie;
struct pci_host_bridge *bridge;
int err;
- unsigned long val = 0;
+ u32 val = 0;
LIST_HEAD(res);
if (!dev->of_node)
@@ -546,13 +544,13 @@ static int mt7621_pci_probe(struct platform_device *pdev)
bypass_pipe_rst();
set_phy_for_ssc();
- read_config(pcie, 0, 0, 0, 0x70c, &val);
+ val = read_config(pcie, 0, 0x70c);
printk("Port 0 N_FTS = %x\n", (unsigned int)val);
- read_config(pcie, 0, 1, 0, 0x70c, &val);
+ val = read_config(pcie, 1, 0x70c);
printk("Port 1 N_FTS = %x\n", (unsigned int)val);
- read_config(pcie, 0, 2, 0, 0x70c, &val);
+ val = read_config(pcie, 2, 0x70c);
printk("Port 2 N_FTS = %x\n", (unsigned int)val);
rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
@@ -673,25 +671,25 @@ pcie(2/1/0) link status pcie2_num pcie1_num
pcie0_num
switch (pcie_link_status) {
case 7:
- read_config(pcie, 0, 2, 0, 0x4, &val);
+ val = read_config(pcie, 2, 0x4);
write_config(pcie, 0, 2, 0, 0x4, val|0x4);
- read_config(pcie, 0, 2, 0, 0x70c, &val);
+ val = read_config(pcie, 2, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
write_config(pcie, 0, 2, 0, 0x70c, val);
case 3:
case 5:
case 6:
- read_config(pcie, 0, 1, 0, 0x4, &val);
+ val = read_config(pcie, 1, 0x4);
write_config(pcie, 0, 1, 0, 0x4, val|0x4);
- read_config(pcie, 0, 1, 0, 0x70c, &val);
+ val = read_config(pcie, 1, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
write_config(pcie, 0, 1, 0, 0x70c, val);
default:
- read_config(pcie, 0, 0, 0, 0x4, &val);
+ val = read_config(pcie, 0, 0x4);
write_config(pcie, 0, 0, 0, 0x4, val|0x4); //bus master enable
- read_config(pcie, 0, 0, 0, 0x70c, &val);
+ val = read_config(pcie, 0, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
write_config(pcie, 0, 0, 0, 0x70c, val);
--
2.7.4
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[PATCH v9 08/15] staging: mt7621-pci: avoid register duplication per controller using pcie_[read|write]
Use pcie_[read|write] fucntions to read and write controller registers.
Define those only by offset and pass controller offset + register offset
relative to base address to functions.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 70 -
1 file changed, 34 insertions(+), 36 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 65c573c..2533dfc 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -74,8 +74,8 @@
#define RALINK_PCI_CONFIG_ADDR 0x20
#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
-#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE +
0x0028)
-#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE +
0x002C)
+#define RALINK_PCI_MEMBASE 0x28
+#define RALINK_PCI_IOBASE 0x2C
#define RALINK_PCIE0_RST (1<<24)
#define RALINK_PCIE1_RST (1<<25)
#define RALINK_PCIE2_RST (1<<26)
@@ -88,26 +88,12 @@
#define RT6855_PCIE1_OFFSET0x3000
#define RT6855_PCIE2_OFFSET0x4000
-#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE0_OFFSET + 0x0010)
-#define RALINK_PCI0_IMBASEBAR0_ADDR*(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE0_OFFSET + 0x0018)
-#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE0_OFFSET + 0x0030)
-#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE0_OFFSET + 0x0034)
-#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE0_OFFSET + 0x0038)
-#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE0_OFFSET + 0x0050)
-
-#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE1_OFFSET + 0x0010)
-#define RALINK_PCI1_IMBASEBAR0_ADDR*(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE1_OFFSET + 0x0018)
-#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE1_OFFSET + 0x0030)
-#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE1_OFFSET + 0x0034)
-#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE1_OFFSET + 0x0038)
-#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE1_OFFSET + 0x0050)
-
-#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE2_OFFSET + 0x0010)
-#define RALINK_PCI2_IMBASEBAR0_ADDR*(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE2_OFFSET + 0x0018)
-#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE2_OFFSET + 0x0030)
-#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE2_OFFSET + 0x0034)
-#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE2_OFFSET + 0x0038)
-#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE +
RT6855_PCIE2_OFFSET + 0x0050)
+#define RALINK_PCI_BAR0SETUP_ADDR 0x0010
+#define RALINK_PCI_IMBASEBAR0_ADDR 0x0018
+#define RALINK_PCI_ID 0x0030
+#define RALINK_PCI_CLASS 0x0034
+#define RALINK_PCI_SUBID 0x0038
+#define RALINK_PCI_STATUS 0x0050
#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
@@ -543,7 +529,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;
// set DATA
mdelay(1000);
- if ((RALINK_PCI0_STATUS & 0x1) == 0) {
+ if ((pcie_read(pcie, RT6855_PCIE0_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
printk("PCIE0 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
@@ -553,7 +539,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
}
- if ((RALINK_PCI1_STATUS & 0x1) == 0) {
+ if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
printk("PCIE1 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1);
@@ -563,7 +549,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
}
- if ((RALINK_PCI2_STATUS & 0x1) == 0) {
+ if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) ==
0) {
printk("PCIE2 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
rt_
[PATCH v9 15/15] staging: mt7621-dts: add pcie controller port registers
The pcie node of the device tree only contains registers
for the host-bridge and pcie port 0. Add the pcie port 1
and pcie port 2 also.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-dts/mt7621.dtsi | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 4610403..2e837e6 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -394,8 +394,10 @@
pcie: pcie@1e14 {
compatible = "mediatek,mt7621-pci";
- reg = <0x1e14 0x100
- 0x1e142000 0x100>;
+ reg = <0x1e14 0x100 /* host-pci bridge registers */
+ 0x1e142000 0x100/* pcie port 0 RC control registers
*/
+ 0x1e143000 0x100/* pcie port 1 RC control registers
*/
+ 0x1e144000 0x100>; /* pcie port 2 RC control registers
*/
#address-cells = <3>;
#size-cells = <2>;
--
2.7.4
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[PATCH v9 14/15] staging: mt7621-pci: remove remaining pci_legacy dependant code
pcibios_* remaining code is not neccessary at all. We can use
map_irq set to of_irq_parse_and_map_pci driver 'probe' function.
Remove this code.
Signed-off-by: Sergio Paracuellos
---
drivers/staging/mt7621-pci/pci-mt7621.c | 33 +
1 file changed, 1 insertion(+), 32 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 491dda7..e224d30 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -203,32 +203,6 @@ write_config(struct mt7621_pcie *pcie, unsigned int dev,
u32 reg, u32 val)
pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
}
-int
-pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- struct mt7621_pcie *pcie = dev->bus->sysdata;
- u16 cmd;
- u32 val;
- int irq;
-
- if (dev->bus->number == 0) {
- write_config(pcie, slot, PCI_BASE_ADDRESS_0, MEMORY_BASE);
- val = read_config(pcie, slot, PCI_BASE_ADDRESS_0);
- printk("BAR0 at slot %d = %x\n", slot, val);
- }
-
- pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure
cache line size 0x14
- pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure
latency timer 0x10
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
- pci_write_config_word(dev, PCI_COMMAND, cmd);
-
- irq = of_irq_parse_and_map_pci(dev, slot, pin);
-
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
- return irq;
-}
-
void
set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
int start_b, int bits, int val)
@@ -438,7 +412,7 @@ static int mt7621_pcie_register_host(struct pci_host_bridge
*host,
host->busnr = 0;
host->dev.parent = pcie->dev;
host->ops = &mt7621_pci_ops;
- host->map_irq = pcibios_map_irq;
+ host->map_irq = of_irq_parse_and_map_pci;
host->swizzle_irq = pci_common_swizzle;
host->sysdata = pcie;
@@ -695,11 +669,6 @@ pcie(2/1/0) link statuspcie2_num pcie1_num
pcie0_num
return 0;
}
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
-
static const struct of_device_id mt7621_pci_ids[] = {
{ .compatible = "mediatek,mt7621-pci" },
{},
--
2.7.4
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Re: [PATCH char-misc 1/1] Drivers: hv: vmbus: Cleanup synic memory free path
On Wed, Aug 01, 2018 at 03:45:13PM -0700, mhkelle...@gmail.com wrote:
> From: Michael Kelley
>
> clk_evt memory is not being freed when the synic is shutdown
> or when there is an allocation error. Add the appropriate
> kfree() call, along with a comment to clarify how the memory
> gets freed after an allocation error. Make the free path
> consistent by removing checks for NULL since kfree() and
> free_page() already do the check.
>
> Signed-off-by: Michael Kelley
> Reported-by: Dan Carpenter
> ---
> drivers/hv/hv.c | 14 --
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/hv/hv.c b/drivers/hv/hv.c
> index 8d4fe0e..1fb9a6b 100644
> --- a/drivers/hv/hv.c
> +++ b/drivers/hv/hv.c
> @@ -240,6 +240,10 @@ int hv_synic_alloc(void)
>
> return 0;
> err:
> + /*
> + * Any memory allocations that succeeded will be freed when
> + * the caller cleans up by calling hv_synic_free()
> + */
> return -ENOMEM;
> }
>
> @@ -252,12 +256,10 @@ void hv_synic_free(void)
> for_each_present_cpu(cpu) {
> struct hv_per_cpu_context *hv_cpu
> = per_cpu_ptr(hv_context.cpu_context, cpu);
>
> - if (hv_cpu->synic_event_page)
> - free_page((unsigned long)hv_cpu->synic_event_page);
> - if (hv_cpu->synic_message_page)
> - free_page((unsigned long)hv_cpu->synic_message_page);
> - if (hv_cpu->post_msg_page)
> - free_page((unsigned long)hv_cpu->post_msg_page);
> + kfree(hv_cpu->clk_evt);
> + free_page((unsigned long)hv_cpu->synic_event_page);
> + free_page((unsigned long)hv_cpu->synic_message_page);
> + free_page((unsigned long)hv_cpu->post_msg_page);
This looks buggy.
We can pass NULLs to free_page() so that's fine. So the error handling assumes
that hv_cpu->clk_evt is either NULL or allocated. Here is how it is allocated:
189 int hv_synic_alloc(void)
190 {
191 int cpu;
192
193 hv_context.hv_numa_map = kcalloc(nr_node_ids, sizeof(struct
cpumask),
194 GFP_KERNEL);
195 if (hv_context.hv_numa_map == NULL) {
196 pr_err("Unable to allocate NUMA map\n");
197 goto err;
198 }
199
200 for_each_present_cpu(cpu) {
^^^
We loop over each CPU.
201 struct hv_per_cpu_context *hv_cpu
202 = per_cpu_ptr(hv_context.cpu_context, cpu);
203
204 memset(hv_cpu, 0, sizeof(*hv_cpu));
^^
We set this cpu memory to NULL.
205 tasklet_init(&hv_cpu->msg_dpc,
206 vmbus_on_msg_dpc, (unsigned long) hv_cpu);
207
208 hv_cpu->clk_evt = kzalloc(sizeof(struct
clock_event_device),
209GFP_KERNEL);
210 if (hv_cpu->clk_evt == NULL) {
^^^
Let's assume this fails on the first iteration through the loop. We
haven't memset the next cpu to NULL or allocated it. But we loop over
all the cpus in the error handling. Since we didn't set everything to NULL in
hv_synic_free() then it seems like this could be a double free. It's possible I
am misreading the code, but either it's buggy or the memset() can be removed.
This is a very typical bug for this style of error handling where we free
things which were never allocated.
211 pr_err("Unable to allocate clock event
device\n");
212 goto err;
213 }
regards,
dan carpenter
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