[PATCH 1/2] staging: dgnc: remove redundant NULL check for brd
the "brd" value cannot be NULL in dgnc_finalize_board_init().
Because "brd" as a parameter of this function was already
checked for NULL.
Signed-off-by: Daeseok Youn
---
drivers/staging/dgnc/dgnc_driver.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/staging/dgnc/dgnc_driver.c
b/drivers/staging/dgnc/dgnc_driver.c
index af2e835..22257d2 100644
--- a/drivers/staging/dgnc/dgnc_driver.c
+++ b/drivers/staging/dgnc/dgnc_driver.c
@@ -579,9 +579,6 @@ static int dgnc_finalize_board_init(struct dgnc_board *brd)
{
int rc = 0;
- if (!brd || brd->magic != DGNC_BOARD_MAGIC)
- return -ENODEV;
-
if (brd->irq) {
rc = request_irq(brd->irq, brd->bd_ops->intr,
IRQF_SHARED, "DGNC", brd);
--
1.9.1
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[PATCH 2/2] staging: dgnc: remove redundant null check in
the "brd" was already checked for NULL before calling dgnc_do_remap().
Signed-off-by: Daeseok Youn
---
drivers/staging/dgnc/dgnc_driver.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/staging/dgnc/dgnc_driver.c
b/drivers/staging/dgnc/dgnc_driver.c
index 22257d2..1882ef5 100644
--- a/drivers/staging/dgnc/dgnc_driver.c
+++ b/drivers/staging/dgnc/dgnc_driver.c
@@ -599,9 +599,6 @@ static int dgnc_finalize_board_init(struct dgnc_board *brd)
*/
static void dgnc_do_remap(struct dgnc_board *brd)
{
- if (!brd || brd->magic != DGNC_BOARD_MAGIC)
- return;
-
brd->re_map_membase = ioremap(brd->membase, 0x1000);
}
--
1.9.1
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Re: [PATCH v2 1/4] Staging: comedi: fix type issue in s626.c
On 20/05/16 07:21, Ravishankar Karkala Mallikarjunayya wrote:
This is a patch to the s626.c file that fixes up a type issues
found by the checkpatch.pl tool.
i.e Prefer kernel type 'u8' over 'uint8_t'
Prefer kernel type 'u16' over 'uint16_t'
Prefer kernel type 'u32' over 'uint32_t'
Prefer kernel type 's16' over 'int16_t'
Prefer kernel type 's32' over 'int32_t'
Signed-off-by: Ravishankar Karkala Mallikarjunayya
---
Changes since V1:
- Rework
---
drivers/staging/comedi/drivers/s626.c | 152 +-
1 file changed, 76 insertions(+), 76 deletions(-)
diff --git a/drivers/staging/comedi/drivers/s626.c
b/drivers/staging/comedi/drivers/s626.c
index c5e0863..6961550e 100644
--- a/drivers/staging/comedi/drivers/s626.c
+++ b/drivers/staging/comedi/drivers/s626.c
[snip]
@@ -516,12 +516,12 @@ static int s626_send_dac(struct comedi_device *dev,
uint32_t val)
* Private helper function: Write setpoint to an application DAC channel.
*/
static int s626_set_dac(struct comedi_device *dev,
- uint16_t chan, int16_t dacdata)
+ u16 chan, int16_t dacdata)
There are quite a few instances of int16_t, uint8_t, uint16_t, and
uint32_t that you didn't convert, including the `int16_t dacdata` above.
[snip]
@@ -1935,7 +1935,7 @@ static int s626_ns_to_timer(unsigned int *nanosec,
unsigned int flags)
static void s626_timer_load(struct comedi_device *dev,
unsigned int chan, int tick)
{
- uint16_t setup =
+ u16 setup =
/* Preload upon index. */
S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
/* Disable hardware index. */
The declaration of `u16 setup` starts at the wrong indentation level.
@@ -1948,7 +1948,7 @@ static void s626_timer_load(struct comedi_device *dev,
S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
/* Enabled by index */
S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
- uint16_t value_latchsrc = S626_LATCHSRC_A_INDXA;
+ u16 value_latchsrc = S626_LATCHSRC_A_INDXA;
/* uint16_t enab = S626_CLKENAB_ALWAYS; */
s626_set_mode(dev, chan, setup, false);
`u16 value_latchsrc` starts at the wrong indentation level.
[snip]
@@ -2301,7 +2301,7 @@ static int s626_enc_insn_config(struct comedi_device *dev,
struct comedi_insn *insn, unsigned int *data)
{
unsigned int chan = CR_CHAN(insn->chanspec);
- uint16_t setup =
+ u16 setup =
/* Preload upon index. */
S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
/* Disable hardware index. */
`u16 setup` starts at the wrong indentation level.
[snip]
@@ -2384,7 +2384,7 @@ static void s626_write_misc2(struct comedi_device *dev,
uint16_t new_image)
static void s626_counters_init(struct comedi_device *dev)
{
int chan;
- uint16_t setup =
+ u16 setup =
/* Preload upon index. */
S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
/* Disable hardware index. */
Ditto.
--
-=( Ian Abbott @ MEV Ltd.E-mail: )=-
-=( Web: http://www.mev.co.uk/ )=-
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Re: [PATCH v2 3/4] Staging: comedi:Fix unsigned int to bare use of unsigned issue in s626.c
On 20/05/16 07:22, Ravishankar Karkala Mallikarjunayya wrote: This is a patch to the s626.c file that fixes up a WARNING: Prefer 'unsigned int' to bare use of 'unsigned' found by the checkpatch.pl tool Signed-off-by: Ravishankar Karkala Mallikarjunayya --- Changes since V1: - No change --- drivers/staging/comedi/drivers/s626.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) Thanks! Reviewed-by: Ian Abbott -- -=( Ian Abbott @ MEV Ltd.E-mail: )=- -=( Web: http://www.mev.co.uk/ )=- ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH v2 4/4] Staging: comedi: fix line over 80 characters issue in s626.c
On 20/05/16 07:22, Ravishankar Karkala Mallikarjunayya wrote: This is a patch to the s626.c file that fixes up a line over 80 characters issues found by the checkpatch.pl tool. Signed-off-by: Ravishankar Karkala Mallikarjunayya --- Changes since V1: - No change --- drivers/staging/comedi/drivers/s626.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) Thanks! Reviewed-by: Ian Abbott -- -=( Ian Abbott @ MEV Ltd.E-mail: )=- -=( Web: http://www.mev.co.uk/ )=- ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH 06/20] staging: comedi: drivers: re-do PLX PCI 9080 MARBR register values
Replace `enum marb_bits` in "plx9080.h" with a bunch of macros defining
values for the MARBR and DMAARB registers (which are the same
Mode/Arbitation register at two different offsets). Use the prefix
`PLX_MARBR_` for the macros. Make use of the `BIT(x)` and
`GENMASK(h,l)` macros to define the values.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/plx9080.h | 60 +---
1 file changed, 40 insertions(+), 20 deletions(-)
diff --git a/drivers/staging/comedi/drivers/plx9080.h
b/drivers/staging/comedi/drivers/plx9080.h
index 140135c..0bcdbad 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -81,26 +81,46 @@ struct plx_dma_desc {
/* DMA Arbitration Register (alias of MARBR). */
#define PLX_REG_DMAARB 0x00ac
-enum marb_bits {
- MARB_LLT_MASK = 0x00ff, /* Local Bus Latency Timer */
- MARB_LPT_MASK = 0xff00, /* Local Bus Pause Timer */
- MARB_LTEN = 0x0001, /* Latency Timer Enable */
- MARB_LPEN = 0x0002, /* Pause Timer Enable */
- MARB_BREQ = 0x0004, /* Local Bus BREQ Enable */
- MARB_DMA_PRIORITY_MASK = 0x0018,
- /* local bus direct slave give up bus mode */
- MARB_LBDS_GIVE_UP_BUS_MODE = 0x0020,
- /* direct slave LLOCKo# enable */
- MARB_DS_LLOCK_ENABLE = 0x0040,
- MARB_PCI_REQUEST_MODE = 0x0080,
- MARB_PCIV21_MODE = 0x0100, /* pci specification v2.1 mode */
- MARB_PCI_READ_NO_WRITE_MODE = 0x0200,
- MARB_PCI_READ_WITH_WRITE_FLUSH_MODE = 0x0400,
- /* gate local bus latency timer with BREQ */
- MARB_GATE_TIMER_WITH_BREQ = 0x0800,
- MARB_PCI_READ_NO_FLUSH_MODE = 0x1000,
- MARB_USE_SUBSYSTEM_IDS = 0x2000,
-};
+/* Local Bus Latency Timer */
+#define PLX_MARBR_LT(x)(BIT(0) * ((x) & 0xff))
+#define PLX_MARBR_LT_MASK GENMASK(7, 0)
+#define PLX_MARBR_LT_SHIFT 0
+/* Local Bus Pause Timer */
+#define PLX_MARBR_PT(x)(BIT(8) * ((x) & 0xff))
+#define PLX_MARBR_PT_MASK GENMASK(15, 8)
+#define PLX_MARBR_PT_SHIFT 8
+/* Local Bus Latency Timer Enable */
+#define PLX_MARBR_LTEN BIT(16)
+/* Local Bus Pause Timer Enable */
+#define PLX_MARBR_PTEN BIT(17)
+/* Local Bus BREQ Enable */
+#define PLX_MARBR_BREQEN BIT(18)
+/* DMA Channel Priority */
+#define PLX_MARBR_PRIO_ROT (BIT(19) * 0) /* Rotational priority */
+#define PLX_MARBR_PRIO_DMA0(BIT(19) * 1) /* DMA channel 0 has priority */
+#define PLX_MARBR_PRIO_DMA1(BIT(19) * 2) /* DMA channel 1 has priority */
+#define PLX_MARBR_PRIO_MASKGENMASK(20, 19)
+/* Local Bus Direct Slave Give Up Bus Mode */
+#define PLX_MARBR_DSGUBM BIT(21)
+/* Direct Slace LLOCKo# Enable */
+#define PLX_MARBR_DSLLOCKOEN BIT(22)
+/* PCI Request Mode */
+#define PLX_MARBR_PCIREQM BIT(23)
+/* PCI Specification v2.1 Mode */
+#define PLX_MARBR_PCIV21M BIT(24)
+/* PCI Read No Write Mode */
+#define PLX_MARBR_PCIRNWM BIT(25)
+/* PCI Read with Write Flush Mode */
+#define PLX_MARBR_PCIRWFM BIT(26)
+/* Gate Local Bus Latency Timer with BREQ */
+#define PLX_MARBR_GLTBREQ BIT(27)
+/* PCI Read No Flush Mode */
+#define PLX_MARBR_PCIRNFM BIT(28)
+/*
+ * Make reads from PCI Configuration register 0 return Subsystem ID and
+ * Subsystem Vendor ID instead of Device ID and Vendor ID
+ */
+#define PLX_MARBR_SUBSYSIDSBIT(29)
/* Big/Little Endian Descriptor Register */
#define PLX_REG_BIGEND 0x000c
--
2.8.1
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[PATCH 01/20] staging: comedi: plx9080.h: correct LRNG_IO_MASK and LMAP_IO_MASK
For the PLX local address space range registers, LAS0RR and LAS1RR, bit
0 indicates whether the local address space will be mapped to memory
space or I/O space. If mapped to I/O space, bit 1 must be set to 0, and
bits 31 to 2 form the address decoding mask, which should be -2^N mod
2^32 for a range of length 2^N.
The `LRNG_IO_MASK` macro is supposed to specify the address decoding
bits for I/O space. It currently has the value `0xfffa`, but should
be `0xfffc`, or possibly `0xfffe` (it doesn't really matter,
since bit 1 is required to be set to 0). Change it to `0xfffc`.
Similarly, for the PLX local address space local base address (remap)
registers, LAS0BA and LAS1BA, bits 31 to 2, masked with the
corresponding "range" register form the local base address for the local
address space. The `LMAP_IO_MASK` macro is supposed to mask the valid
bits for I/O space. Change its value from `0xfffa` to `0xfffc`
to match `LRNG_IO_MASK`.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/plx9080.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/comedi/drivers/plx9080.h
b/drivers/staging/comedi/drivers/plx9080.h
index 8d1aee00b1..7d6311c 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -60,7 +60,7 @@ struct plx_dma_desc {
/* bits that specify range for memory io */
#define LRNG_MEM_MASK 0xfff0
/* bits that specify range for normal io */
-#define LRNG_IO_MASK 0xfffa
+#define LRNG_IO_MASK 0xfffc
/* L, Local Addr Space 0 Remap Register */
#define PLX_LAS0MAP_REG 0x0004
/* L, Local Addr Space 1 Remap Register */
@@ -69,7 +69,7 @@ struct plx_dma_desc {
/* bits that specify decode for memory io */
#define LMAP_MEM_MASK 0xfff0
/* bits that specify decode bits for normal io */
-#define LMAP_IO_MASK 0xfffa
+#define LMAP_IO_MASK 0xfffc
/*
* Mode/Arbitration Register.
--
2.8.1
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[PATCH 03/20] staging: comedi: drivers: rename PLX PCI 9080 register offsets
Rename the macros in "plx9080.h" that define the offsets of registers,
following the pattern `PLX_REG_`, where `` is the register
name from the PLX PCI 9080 Data Book.
Add defines for the "Mailbox" registers, and add parameterized macros
for the mailbox registers and the DMA control registers. Make use of
the parameterized versions of the macros where it seems appropriate.
The registers for supporting the I2O (Intelligent Input/Output) feature
are largely left undefined, just defining enough to allow the I2O
feature to be disabled.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/cb_pcidas64.c | 96 ++-
drivers/staging/comedi/drivers/gsc_hpdi.c| 39 +++---
drivers/staging/comedi/drivers/plx9080.h | 177 +++
drivers/staging/comedi/drivers/rtd520.c | 4 +-
4 files changed, 185 insertions(+), 131 deletions(-)
diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c
b/drivers/staging/comedi/drivers/cb_pcidas64.c
index c773b8c..d9468db 100644
--- a/drivers/staging/comedi/drivers/cb_pcidas64.c
+++ b/drivers/staging/comedi/drivers/cb_pcidas64.c
@@ -1238,7 +1238,7 @@ static void disable_plx_interrupts(struct comedi_device
*dev)
devpriv->plx_intcsr_bits = 0;
writel(devpriv->plx_intcsr_bits,
- devpriv->plx9080_iobase + PLX_INTRCS_REG);
+ devpriv->plx9080_iobase + PLX_REG_INTCSR);
}
static void disable_ai_interrupts(struct comedi_device *dev)
@@ -1291,14 +1291,14 @@ static void init_plx9080(struct comedi_device *dev)
void __iomem *plx_iobase = devpriv->plx9080_iobase;
devpriv->plx_control_bits =
- readl(devpriv->plx9080_iobase + PLX_CONTROL_REG);
+ readl(devpriv->plx9080_iobase + PLX_REG_CNTRL);
#ifdef __BIG_ENDIAN
bits = BIGEND_DMA0 | BIGEND_DMA1;
#else
bits = 0;
#endif
- writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
+ writel(bits, devpriv->plx9080_iobase + PLX_REG_BIGEND);
disable_plx_interrupts(dev);
@@ -1330,16 +1330,16 @@ static void init_plx9080(struct comedi_device *dev)
bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
else/* localspace0 bus is 16 bits wide */
bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
- writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
+ writel(bits, plx_iobase + PLX_REG_DMAMODE1);
if (ao_cmd_is_supported(board))
- writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
+ writel(bits, plx_iobase + PLX_REG_DMAMODE0);
/* enable interrupts on plx 9080 */
devpriv->plx_intcsr_bits |=
ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
ICS_DMA0_E | ICS_DMA1_E;
writel(devpriv->plx_intcsr_bits,
- devpriv->plx9080_iobase + PLX_INTRCS_REG);
+ devpriv->plx9080_iobase + PLX_REG_INTCSR);
}
static void disable_ai_pacing(struct comedi_device *dev)
@@ -1615,7 +1615,7 @@ static void i2c_set_sda(struct comedi_device *dev, int
state)
struct pcidas64_private *devpriv = dev->private;
static const int data_bit = CTL_EE_W;
void __iomem *plx_control_addr = devpriv->plx9080_iobase +
-PLX_CONTROL_REG;
+PLX_REG_CNTRL;
if (state) {
/* set data line high */
@@ -1636,7 +1636,7 @@ static void i2c_set_scl(struct comedi_device *dev, int
state)
struct pcidas64_private *devpriv = dev->private;
static const int clock_bit = CTL_USERO;
void __iomem *plx_control_addr = devpriv->plx9080_iobase +
-PLX_CONTROL_REG;
+PLX_REG_CNTRL;
if (state) {
/* set clock line high */
@@ -2367,14 +2367,8 @@ static inline void dma_start_sync(struct comedi_device
*dev,
/* spinlock for plx dma control/status reg */
spin_lock_irqsave(&dev->spinlock, flags);
- if (channel)
- writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
- PLX_CLEAR_DMA_INTR_BIT,
- devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
- else
- writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
- PLX_CLEAR_DMA_INTR_BIT,
- devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
+ writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
+ devpriv->plx9080_iobase + PLX_REG_DMACSR(channel));
spin_unlock_irqrestore(&dev->spinlock, flags);
}
@@ -2552,21 +2546,17 @@ static inline void load_first_dma_descriptor(struct
comedi_device *dev,
* block. Initializing them to zero seems to fix the problem.
*/
if (dma_channel) {
- writel(0,
- devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
- writel(0, devpriv->plx9080_iobase + PLX_DMA1_PC
[PATCH 09/20] staging: comedi: drivers: re-do PLX PCI 9080 DMPBAM register values
Replace the existing macros in "plx9080.h" that define values for the
DMPBAM register. Use the prefix `PLX_DMPBAM_` for the macros. Make use
of the `BIT(x)` and `GENMASK(h,l)` macros to define the values.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/plx9080.h | 48 ++--
1 file changed, 34 insertions(+), 14 deletions(-)
diff --git a/drivers/staging/comedi/drivers/plx9080.h
b/drivers/staging/comedi/drivers/plx9080.h
index 93b2e89..ab90837 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -228,20 +228,40 @@ struct plx_dma_desc {
/* PCI Base Address (Remap) Register for Direct Master to PCI Memory */
#define PLX_REG_DMPBAM 0x0028
-#define DMM_MAE 0x0001 /* Direct Mstr Memory Acc Enable */
-#define DMM_IAE 0x0002 /* Direct Mstr I/O Acc Enable */
-#define DMM_LCK 0x0004 /* LOCK Input Enable */
-#define DMM_PF4 0x0008 /* Prefetch 4 Mode Enable */
-#define DMM_THROT 0x0010 /* Assert IRDY when read FIFO full */
-#define DMM_PAF0 0x /* Programmable Almost fill level */
-#define DMM_PAF1 0x0020 /* Programmable Almost fill level */
-#define DMM_PAF2 0x0040 /* Programmable Almost fill level */
-#define DMM_PAF3 0x0060 /* Programmable Almost fill level */
-#define DMM_PAF4 0x0080 /* Programmable Almost fill level */
-#define DMM_PAF5 0x00A0 /* Programmable Almost fill level */
-#define DMM_PAF6 0x00C0 /* Programmable Almost fill level */
-#define DMM_PAF7 0x00D0 /* Programmable Almost fill level */
-#define DMM_MAP 0x /* Remap Address Bits */
+/* Direct Master Memory Access Enable */
+#define PLX_DMPBAM_MEMACCENBIT(0)
+/* Direct Master I/O Access Enable */
+#define PLX_DMPBAM_IOACCEN BIT(1)
+/* LLOCK# Input Enable */
+#define PLX_DMPBAM_LLOCKIENBIT(2)
+/* Direct Master Read Prefetch Size Control (bits 12, 3) */
+#define PLX_DMPBAM_RPSIZECONT ((BIT(12) * 0) | (BIT(3) * 0))
+#define PLX_DMPBAM_RPSIZE4 ((BIT(12) * 0) | (BIT(3) * 1))
+#define PLX_DMPBAM_RPSIZE8 ((BIT(12) * 1) | (BIT(3) * 0))
+#define PLX_DMPBAM_RPSIZE16((BIT(12) * 1) | (BIT(3) * 1))
+#define PLX_DMPBAM_RPSIZE_MASK (BIT(12) | BIT(3))
+/* Direct Master PCI Read Mode - deassert IRDY when FIFO full */
+#define PLX_DMPBAM_RMIRDY BIT(4)
+/* Programmable Almost Full Level (bits 10, 8:5) */
+#define PLX_DMPBAM_PAFL(x) ((BIT(10) * !!((x) & 0x10)) | \
+(BIT(5) * ((x) & 0xf)))
+#define PLX_DMPBAM_TO_PAFL(v) BIT(10) & (v)) >> 1) | \
+ (GENMASK(8, 5) & (v))) >> 5)
+#define PLX_DMPBAM_PAFL_MASK (BIT(10) | GENMASK(8, 5))
+/* Write And Invalidate Mode */
+#define PLX_DMPBAM_WIM BIT(9)
+/* Direct Master Prefetch Limit */
+#define PLX_DBPBAM_PFLIMIT BIT(11)
+/* I/O Remap Select */
+#define PLX_DMPBAM_IOREMAPSEL BIT(13)
+/* Direct Master Write Delay */
+#define PLX_DMPBAM_WDELAYNONE (BIT(14) * 0)
+#define PLX_DMPBAM_WDELAY4 (BIT(14) * 1)
+#define PLX_DMPBAM_WDELAY8 (BIT(14) * 2)
+#define PLX_DMPBAM_WDELAY16(BIT(14) * 3)
+#define PLX_DMPBAM_WDELAY_MASK GENMASK(15, 14)
+/* Remap of Local-to-PCI Space Into PCI Address Space */
+#define PLX_DMPBAM_REMAP_MASK GENMASK(31, 16)
/* PCI Configuration Address Register for Direct Master to PCI IO/CFG */
#define PLX_REG_DMCFGA 0x002c
--
2.8.1
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[PATCH 02/20] staging: comedi: plx9080.h: remove Power-Up Test Suite stuff
The defines related to the Power-Up Test Suite (PUTS) are just cruft that
has nothing to do with the PLX PCI-9080 chip. They seem to have been
inherited from "drivers/net/plx9060.h" in the kernel 2.2.16 sources for
use by the "wanxl" driver. Remove them.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/plx9080.h | 120 ---
1 file changed, 120 deletions(-)
diff --git a/drivers/staging/comedi/drivers/plx9080.h
b/drivers/staging/comedi/drivers/plx9080.h
index 7d6311c..3759a19 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -294,126 +294,6 @@ enum bigend_bits {
#define PLX_PREFETCH 32
-/*
- * The PCI Interface, via the PCI-9060 Chip, has up to eight (8) Mailbox
- * Registers. The PUTS (Power-Up Test Suite) handles the board-side
- * interface/interaction using the first 4 registers. Specifications for
- * the use of the full PUTS' command and status interface is contained
- * within a separate SBE PUTS Manual. The Host-Side Device Driver only
- * uses a subset of the full PUTS interface.
- */
-
-/*/
-/***MAILBOX #(-1) - MEM ACCESS STS ***/
-/*/
-
-#define MBX_STS_VALID 0x57584744 /* 'WXGD' */
-#define MBX_STS_DILAV 0x44475857 /* swapped = 'DGXW' */
-
-/*/
-/***MAILBOX #0 - PUTS STATUS ***/
-/*/
-
-#define MBX_STS_MASK 0x00ff /* PUTS Status Register bits */
-#define MBX_STS_TMASK 0x000f /* register bits for TEST number */
-
-#define MBX_STS_PCIRESET 0x0100 /* Host issued PCI reset request */
-#define MBX_STS_BUSY 0x0080 /* PUTS is in progress */
-#define MBX_STS_ERROR 0x0040 /* PUTS has failed */
-/*
- * Undefined -> status in transition. We are in process of changing bits;
- * we SET Error bit before RESET of Busy bit
- */
-#define MBX_STS_RESERVED 0x00c0
-
-#define MBX_RESERVED_5 0x0020 /* FYI: reserved/unused bit */
-#define MBX_RESERVED_4 0x0010 /* FYI: reserved/unused bit */
-
-/**/
-/***MAILBOX #1 - PUTS COMMANDS***/
-/**/
-
-/*
- * Any attempt to execute an unimplement command results in the PUTS
- * interface executing a NOOP and continuing as if the offending command
- * completed normally. Note: this supplies a simple method to interrogate
- * mailbox command processing functionality.
- */
-
-#define MBX_CMD_MASK 0x /* PUTS Command Register bits */
-
-#define MBX_CMD_ABORTJ 0x8500 /* abort and jump */
-#define MBX_CMD_RESETP 0x8600 /* reset and pause at start */
-#define MBX_CMD_PAUSE 0x8700 /* pause immediately */
-#define MBX_CMD_PAUSEC 0x8800 /* pause on completion */
-#define MBX_CMD_RESUME 0x8900 /* resume operation */
-#define MBX_CMD_STEP 0x8a00 /* single step tests */
-
-#define MBX_CMD_BSWAP 0x8c00 /* identify byte swap scheme */
-#define MBX_CMD_BSWAP_00x8c00 /* use scheme 0 */
-#define MBX_CMD_BSWAP_10x8c01 /* use scheme 1 */
-
-/* setup host memory access window size */
-#define MBX_CMD_SETHMS 0x8d00
-/* setup host memory access base address */
-#define MBX_CMD_SETHBA 0x8e00
-/* perform memory setup and continue (IE. Done) */
-#define MBX_CMD_MGO0x8f00
-#define MBX_CMD_NOOP 0xFF00 /* dummy, illegal command */
-
-/*/
-/***MAILBOX #2 - MEMORY SIZE ***/
-/*/
-
-#define MBX_MEMSZ_MASK 0x /* PUTS Memory Size Register bits */
-
-#define MBX_MEMSZ_128KB0x0002 /* 128 kilobyte board */
-#define MBX_MEMSZ_256KB0x0004 /* 256 kilobyte board */
-#define MBX_MEMSZ_512KB0x0008 /* 512 kilobyte board */
-#define MBX_MEMSZ_1MB 0x0010 /* 1 megabyte board */
-#define MBX_MEMSZ_2MB 0x0020 /* 2 megabyte board */
-#define MBX_MEMSZ_4MB 0x0040 /* 4 megabyte board */
-#define MBX_MEMSZ_8MB 0x0080 /* 8 megabyte board */
-#define MBX_MEMSZ_16MB 0x0100 /* 16 megabyte board */
-
-/***/
-/***MAILBOX #2 - BOARD TYPE***/
-/***/
-
-#define MBX_BTYPE_MASK 0x /* PUTS Board Type Register */
-/* PUTS Board Family Register */
-#define MBX_BTYPE_FAMILY_MASK 0xff00
-#define MBX_BTYPE_SUBTYPE_MASK 0x00ff /* PUTS Board Subtype */
-
-#define MBX_BTYPE_PLX9060 0x0100 /* PLX family type */
-#define MBX_BTYPE_PLX9080 0x0300 /* PLX wanXL100s family type */
-
-#define MBX_BTYPE_WANXL_4 0x0104 /* wanXL400, 4-port */
-#define MBX_BTYPE_WANXL_2 0x0102 /* wanXL200, 2-port */
-#define MBX_BTYPE_WANXL_1s
[PATCH 10/20] staging: comedi: drivers: re-do PLX PCI 9080 DMCFGA register values
Replace the existing macros in "plx9080.h" that define values for the
DMCFGA register. Use the prefix `PLX_DMCFGA_` for the macros. Make use
of the `BIT(x)` and `GENMASK(h,l)` macros to define the values.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/plx9080.h | 29 ++---
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/comedi/drivers/plx9080.h
b/drivers/staging/comedi/drivers/plx9080.h
index ab90837..e544327 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -266,13 +266,28 @@ struct plx_dma_desc {
/* PCI Configuration Address Register for Direct Master to PCI IO/CFG */
#define PLX_REG_DMCFGA 0x002c
-#define CAR_CT0 0x /* Config Type 0 */
-#define CAR_CT1 0x0001 /* Config Type 1 */
-#define CAR_REG 0x00FC /* Register Number Bits */
-#define CAR_FUN 0x0700 /* Function Number Bits */
-#define CAR_DEV 0xF800 /* Device Number Bits */
-#define CAR_BUS 0x00FF /* Bus Number Bits */
-#define CAR_CFG 0x8000 /* Config Spc Access Enable */
+/* Congiguration Type */
+#define PLX_DMCFGA_TYPE0 (BIT(0) * 0)
+#define PLX_DMCFGA_TYPE1 (BIT(0) * 1)
+#define PLX_DMCFGA_TYPE_MASK GENMASK(1, 0)
+/* Register Number */
+#define PLX_DMCFGA_REGNUM(x) (BIT(2) * ((x) & 0x3f))
+#define PLX_DMCFGA_REGNUM_MASK GENMASK(7, 2)
+#define PLX_DMCFGA_REGNUM_SHIFT2
+/* Function Number */
+#define PLX_DMCFGA_FUNCNUM(x) (BIT(8) * ((x) & 0x7))
+#define PLX_DMCFGA_FUNCNUM_MASKGENMASK(10, 8)
+#define PLX_DMCFGA_FUNCNUM_SHIFT 8
+/* Device Number */
+#define PLX_DMCFGA_DEVNUM(x) (BIT(11) * ((x) & 0x1f))
+#define PLX_DMCFGA_DEVNUM_MASK GENMASK(15, 11)
+#define PLX_DMCFGA_DEVNUM_SHIFT11
+/* Bus Number */
+#define PLX_DMCFGA_BUSNUM(x) (BIT(16) * ((x) & 0xff))
+#define PLX_DMCFGA_BUSNUM_MASK GENMASK(23, 16)
+#define PLX_DMCFGA_BUSNUM_SHIFT16
+/* Configuration Enable */
+#define PLX_DMCFGA_CONFIGENBIT(31)
/*
* Mailbox Register N (N <= 7)
--
2.8.1
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[PATCH 05/20] staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxBA values
Replace the existing macros in "plx9080.h" that define values for the
LAS0BA and LAS1BA registers. Use the prefix `PLX_LASBA_` for the
macros. Make use of the `BIT(x)` and `GENMASK(h,l)` macros to define
the macros.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/cb_pcidas64.c | 4 ++--
drivers/staging/comedi/drivers/plx9080.h | 10 +-
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c
b/drivers/staging/comedi/drivers/cb_pcidas64.c
index 59d81e8..f997c1f 100644
--- a/drivers/staging/comedi/drivers/cb_pcidas64.c
+++ b/drivers/staging/comedi/drivers/cb_pcidas64.c
@@ -4006,13 +4006,13 @@ static int auto_attach(struct comedi_device *dev,
local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS0RR) &
PLX_LASRR_MEM_MASK;
local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS0BA) &
- local_range & LMAP_MEM_MASK;
+ local_range & PLX_LASBA_MEM_MASK;
devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
~local_range) | local_decode;
local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS1RR) &
PLX_LASRR_MEM_MASK;
local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS1BA) &
- local_range & LMAP_MEM_MASK;
+ local_range & PLX_LASBA_MEM_MASK;
devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
~local_range) | local_decode;
diff --git a/drivers/staging/comedi/drivers/plx9080.h
b/drivers/staging/comedi/drivers/plx9080.h
index 8788117..140135c 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -70,11 +70,11 @@ struct plx_dma_desc {
/* Local Address Space 1 Local Base Address (Remap) Register */
#define PLX_REG_LAS1BA 0x00f4
-#define LMAP_EN 0x0001 /* Enable slave decode */
-/* bits that specify decode for memory io */
-#define LMAP_MEM_MASK 0xfff0
-/* bits that specify decode bits for normal io */
-#define LMAP_IO_MASK 0xfffc
+#define PLX_LASBA_EN BIT(0) /* Enable slave decode */
+/* bits that specify local base address for memory space */
+#define PLX_LASBA_MEM_MASK GENMASK(31, 4)
+/* bits that specify local base address for i/o space */
+#define PLX_LASBA_IO_MASK GENMASK(31, 2)
/* Mode/Arbitration Register */
#define PLX_REG_MARBR 0x0008
--
2.8.1
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[PATCH 08/20] staging: comedi: drivers: re-do PLX PCI 9080 LBRDx register values
Replace the existing macros in "plx9080.h" that define values for the
LBRD0 and LBRD1 registers. Use the prefix `PLX_LBRD_` for macros that
apply to both registers, `PLX_LBRD0_` for macros that apply only to the
LBRD0 register, and `PLX_LBRD1_` for macros that apply only to the LBRD1
register. Make use of the `BIT(x)` and `GENMASK(h,l)` macros to define
the values.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/plx9080.h | 80 ++--
1 file changed, 56 insertions(+), 24 deletions(-)
diff --git a/drivers/staging/comedi/drivers/plx9080.h
b/drivers/staging/comedi/drivers/plx9080.h
index 84dd366..93b2e89 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -159,30 +159,62 @@ struct plx_dma_desc {
/* Local Address Space 1 Bus Region Descriptor Register */
#define PLX_REG_LBRD1 0x00f8
-#define RGN_WIDTH 0x0002 /* Local bus width bits */
-#define RGN_8BITS 0x /* 08 bit Local Bus */
-#define RGN_16BITS0x0001 /* 16 bit Local Bus */
-#define RGN_32BITS0x0002 /* 32 bit Local Bus */
-#define RGN_MWS 0x003C /* Memory Access Wait States */
-#define RGN_0MWS 0x
-#define RGN_1MWS 0x0004
-#define RGN_2MWS 0x0008
-#define RGN_3MWS 0x000C
-#define RGN_4MWS 0x0010
-#define RGN_6MWS 0x0018
-#define RGN_8MWS 0x0020
-#define RGN_MRE 0x0040 /* Memory Space Ready Input Enable */
-#define RGN_MBE 0x0080 /* Memory Space Bterm Input Enable */
-#define RGN_READ_PREFETCH_DISABLE 0x0100
-#define RGN_ROM_PREFETCH_DISABLE 0x0200
-#define RGN_READ_PREFETCH_COUNT_ENABLE 0x0400
-#define RGN_RWS 0x003C /* Expn ROM Wait States */
-#define RGN_RRE 0x0040 /* ROM Space Ready Input Enable */
-#define RGN_RBE 0x0080 /* ROM Space Bterm Input Enable */
-#define RGN_MBEN 0x0100 /* Memory Space Burst Enable */
-#define RGN_RBEN 0x0400 /* ROM Space Burst Enable */
-#define RGN_THROT 0x0800 /* De-assert TRDY when FIFO full */
-#define RGN_TRD 0xF000 /* Target Ready Delay /8 */
+/* Memory Space Local Bus Width */
+#define PLX_LBRD_MSWIDTH8 (BIT(0) * 0)/* 8 bits wide */
+#define PLX_LBRD_MSWIDTH16 (BIT(0) * 1)/* 16 bits wide */
+#define PLX_LBRD_MSWIDTH32 (BIT(0) * 2)/* 32 bits wide */
+#define PLX_LBRD_MSWIDTH32A(BIT(0) * 3)/* 32 bits wide */
+#define PLX_LBRD_MSWIDTH_MASK GENMASK(1, 0)
+#define PLX_LBRD_MSWIDTH_SHIFT 0
+/* Memory Space Internal Wait States */
+#define PLX_LBRD_MSIWS(x) (BIT(2) * ((x) & 0xf))
+#define PLX_LBRD_MSIWS_MASKGENMASK(5, 2)
+#define PLX_LBRD_MSIWS_SHIFT 2
+/* Memory Space Ready Input Enable */
+#define PLX_LBRD_MSREADYIENBIT(6)
+/* Memory Space BTERM# Input Enable */
+#define PLX_LBRD_MSBTERMIENBIT(7)
+/* Memory Space 0 Prefetch Disable (LBRD0 only) */
+#define PLX_LBRD0_MSPREDIS BIT(8)
+/* Memory Space 1 Burst Enable (LBRD1 only) */
+#define PLX_LBRD1_MSBURSTENBIT(8)
+/* Expansion ROM Space Prefetch Disable (LBRD0 only) */
+#define PLX_LBRD0_EROMPREDIS BIT(9)
+/* Memory Space 1 Prefetch Disable (LBRD1 only) */
+#define PLX_LBRD1_MSPREDIS BIT(9)
+/* Read Prefetch Count Enable */
+#define PLX_LBRD_RPFCOUNTENBIT(10)
+/* Prefetch Counter */
+#define PLX_LBRD_PFCOUNT(x)(BIT(11) * ((x) & 0xf))
+#define PLX_LBRD_PFCOUNT_MASK GENMASK(14, 11)
+#define PLX_LBRD_PFCOUNT_SHIFT 11
+/* Expansion ROM Space Local Bus Width (LBRD0 only) */
+#define PLX_LBRD0_EROMWIDTH8 (BIT(16) * 0) /* 8 bits wide */
+#define PLX_LBRD0_EROMWIDTH16 (BIT(16) * 1) /* 16 bits wide */
+#define PLX_LBRD0_EROMWIDTH32 (BIT(16) * 2) /* 32 bits wide */
+#define PLX_LBRD0_EROMWIDTH32A (BIT(16) * 3) /* 32 bits wide */
+#define PLX_LBRD0_EROMWIDTH_MASK GENMASK(17, 16)
+#define PLX_LBRD0_EROMWIDTH_SHIFT 16
+/* Expansion ROM Space Internal Wait States (LBRD0 only) */
+#define PLX_LBRD0_EROMIWS(x) (BIT(18) * ((x) & 0xf))
+#define PLX_LBRD0_EROMIWS_MASK GENMASK(21, 18)
+#define PLX_LBRD0_EROMIWS_SHIFT18
+/* Expansion ROM Space Ready Input Enable (LBDR0 only) */
+#define PLX_LBRD0_EROMREADYIEN BIT(22)
+/* Expansion ROM Space BTERM# Input Enable (LBRD0 only) */
+#define PLX_LBRD0_EROMBTERMIEN BIT(23)
+/* Memory Space 0 Burst Enable (LBRD0 only) */
+#define PLX_LBRD0_MSBURSTENBIT(24)
+/* Extra Long Load From Serial EEPROM (LBRD0 only) */
+#define PLX_LBRD0_EELONGLOAD BIT(25)
+/* Expansion ROM Space Burst Enable (LBRD0 only) */
+#define PLX_LBRD0_EROMBURSTEN BIT(26)
+/* Direct Slave PCI Write Mode - assert TRDY# when FIFO full (LBRD0 only) */
+#define PLX_LBRD0_DSWMTRDY BIT(27)
+/* PCI Target Retry Delay Clocks / 8 (LBRD0 only) */
+#define PLX_LBRD0_TRDELAY(x) (BIT(28) * ((x) & 0xF))
+#define PLX_LBRD0_TRDELAY_MASK GENMASK(31
[PATCH 04/20] staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxRR values
Rename the macros for the PLX PCI 9080 LAS0RR and LAS1RR registers in
"plx9080.h", using the prefix `PLX_LASRR_`. Make use of the `BIT(x)`
and `GENMASK(h,l)` macros to define the values.
Define a macro `PLX_LASRR_PREFETCH` for the "prefetchable memory" bit in
this register, and define a macro `PLX_LASRR_MLOC_MASK` to mask the PCI
memory location control bits.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/cb_pcidas64.c | 4 ++--
drivers/staging/comedi/drivers/plx9080.h | 18 ++
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c
b/drivers/staging/comedi/drivers/cb_pcidas64.c
index d9468db..59d81e8 100644
--- a/drivers/staging/comedi/drivers/cb_pcidas64.c
+++ b/drivers/staging/comedi/drivers/cb_pcidas64.c
@@ -4004,13 +4004,13 @@ static int auto_attach(struct comedi_device *dev,
/* figure out what local addresses are */
local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS0RR) &
- LRNG_MEM_MASK;
+ PLX_LASRR_MEM_MASK;
local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS0BA) &
local_range & LMAP_MEM_MASK;
devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
~local_range) | local_decode;
local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS1RR) &
- LRNG_MEM_MASK;
+ PLX_LASRR_MEM_MASK;
local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS1BA) &
local_range & LMAP_MEM_MASK;
devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
diff --git a/drivers/staging/comedi/drivers/plx9080.h
b/drivers/staging/comedi/drivers/plx9080.h
index 92d2480..8788117 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -54,14 +54,16 @@ struct plx_dma_desc {
/* Local Address Space 1 Range Register */
#define PLX_REG_LAS1RR 0x00f0
-#define LRNG_IO 0x0001 /* Map to: 1=I/O, 0=Mem */
-#define LRNG_ANY320x /* Locate anywhere in 32 bit */
-#define LRNG_LT1MB0x0002 /* Locate in 1st meg */
-#define LRNG_ANY640x0004 /* Locate anywhere in 64 bit */
-/* bits that specify range for memory io */
-#define LRNG_MEM_MASK 0xfff0
-/* bits that specify range for normal io */
-#define LRNG_IO_MASK 0xfffc
+#define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem */
+#define PLX_LASRR_ANY32(BIT(1) * 0)/* Locate anywhere in
32 bit */
+#define PLX_LASRR_LT1MB(BIT(1) * 1)/* Locate in 1st meg */
+#define PLX_LASRR_ANY64(BIT(1) * 2)/* Locate anywhere in
64 bit */
+#define PLX_LASRR_MLOC_MASKGENMASK(2, 1) /* Memory location bits */
+#define PLX_LASRR_PREFETCH BIT(3) /* Memory is prefetchable */
+/* bits that specify range for memory space decode bits */
+#define PLX_LASRR_MEM_MASK GENMASK(31, 4)
+/* bits that specify range for i/o space decode bits */
+#define PLX_LASRR_IO_MASK GENMASK(31, 2)
/* Local Address Space 0 Local Base Address (Remap) Register */
#define PLX_REG_LAS0BA 0x0004
--
2.8.1
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[PATCH 00/20] staging: comedi: re-do drivers/plx9080.h
Re-do "drivers/staging/comedi/drivers/plx9080.h". It mostly contains defines for register offsets and values for the PLX PCI 9080 PCI interface chip. To make it easier to follow, base the macro names for register offsets on the register names from the PLX PCI 9080 data book. Base the macro names used to construct register values on the names of the corresponding registers. Make use of the `BIT(x)` and `GENMASK(h,l)` macros to define register values and masks. Add kerneldoc comments for structs and inline functions. Add `#include` directives to declare things used within the code. 01) staging: comedi: plx9080.h: correct LRNG_IO_MASK and LMAP_IO_MASK 02) staging: comedi: plx9080.h: remove Power-Up Test Suite stuff 03) staging: comedi: drivers: rename PLX PCI 9080 register offsets 04) staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxRR values 05) staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxBA values 06) staging: comedi: drivers: re-do PLX PCI 9080 MARBR register values 07) staging: comedi: drivers: re-do PLX PCI 9080 BIGEND register values 08) staging: comedi: drivers: re-do PLX PCI 9080 LBRDx register values 09) staging: comedi: drivers: re-do PLX PCI 9080 DMPBAM register values 10) staging: comedi: drivers: re-do PLX PCI 9080 DMCFGA register values 11) staging: comedi: drivers: re-do PLX PCI 9080 INTCSR register values 12) staging: comedi: drivers: re-do PLX PCI 9080 CNTRL register values 13) staging: comedi: plx9080.h: add hard-coded PCIHIDR register value 14) staging: comedi: drivers: re-do PLX PCI 9080 DMAMODEx register values 15) staging: comedi: drivers: re-do PLX PCI 9080 DMADPRx register values 16) staging: comedi: drivers: re-do PLX PCI 9080 DMACSRx register values 17) staging: comedi: drivers: add PLX PCI 9080 DMATHR register values 18) staging: comedi: plx9080.h: tidy up some comments 19) staging: comedi: plx9080.h: Add kerneldoc comments 20) staging: comedi: plx9080.h: include headers for declarations drivers/staging/comedi/drivers/cb_pcidas64.c | 209 +++--- drivers/staging/comedi/drivers/gsc_hpdi.c| 87 ++- drivers/staging/comedi/drivers/plx9080.h | 957 --- drivers/staging/comedi/drivers/rtd520.c | 5 +- 4 files changed, 726 insertions(+), 532 deletions(-) ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH 17/20] staging: comedi: drivers: add PLX PCI 9080 DMATHR register values
Add macros in "plx9080.h" that define values for the DMATHR register
values. Use the prefix `PLX_DMATHR_` for the macros. Make use of the
`BIT(x)` and `GENMASK(h,l)` macros to define the values.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/plx9080.h | 41
1 file changed, 41 insertions(+)
diff --git a/drivers/staging/comedi/drivers/plx9080.h
b/drivers/staging/comedi/drivers/plx9080.h
index 9e76342..50d0b1b 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -544,6 +544,47 @@ struct plx_dma_desc {
#define PLX_REG_DMATHR 0x00b0
/*
+ * DMA Threshold constraints:
+ * (C0PLAF + 1) + (C0PLAE + 1) <= 32
+ * (C0LPAF + 1) + (C0LPAE + 1) <= 32
+ * (C1PLAF + 1) + (C1PLAE + 1) <= 16
+ * (C1LPAF + 1) + (C1LPAE + 1) <= 16
+ */
+
+/* DMA Channel 0 PCI-to-Local Almost Full (divided by 2, minus 1) */
+#define PLX_DMATHR_C0PLAF(x) (BIT(0) * ((x) & 0xf))
+#define PLX_DMATHR_C0PLAF_MASK GENMASK(3, 0)
+#define PLX_DMATHR_C0PLAF_SHIFT0
+/* DMA Channel 0 Local-to-PCI Almost Empty (divided by 2, minus 1) */
+#define PLX_DMATHR_C0LPAE(x) (BIT(4) * ((x) & 0xf))
+#define PLX_DMATHR_C0LPAE_MASK GENMASK(7, 4)
+#define PLX_DMATHR_C0LPAE_SHIFT4
+/* DMA Channel 0 Local-to-PCI Almost Full (divided by 2, minus 1) */
+#define PLX_DMATHR_C0LPAF(x) (BIT(8) * ((x) & 0xf))
+#define PLX_DMATHR_C0LPAF_MASK GENMASK(11, 8)
+#define PLX_DMATHR_C0LPAF_SHIFT8
+/* DMA Channel 0 PCI-to-Local Almost Empty (divided by 2, minus 1) */
+#define PLX_DMATHR_C0PLAE(x) (BIT(12) * ((x) & 0xf))
+#define PLX_DMATHR_C0PLAE_MASK GENMASK(15, 12)
+#define PLX_DMATHR_C0PLAE_SHIFT12
+/* DMA Channel 1 PCI-to-Local Almost Full (divided by 2, minus 1) */
+#define PLX_DMATHR_C1PLAF(x) (BIT(16) * ((x) & 0xf))
+#define PLX_DMATHR_C1PLAF_MASK GENMASK(19, 16)
+#define PLX_DMATHR_C1PLAF_SHIFT16
+/* DMA Channel 1 Local-to-PCI Almost Empty (divided by 2, minus 1) */
+#define PLX_DMATHR_C1LPAE(x) (BIT(20) * ((x) & 0xf))
+#define PLX_DMATHR_C1LPAE_MASK GENMASK(23, 20)
+#define PLX_DMATHR_C1LPAE_SHIFT20
+/* DMA Channel 1 Local-to-PCI Almost Full (divided by 2, minus 1) */
+#define PLX_DMATHR_C1LPAF(x) (BIT(24) * ((x) & 0xf))
+#define PLX_DMATHR_C1LPAF_MASK GENMASK(27, 24)
+#define PLX_DMATHR_C1LPAF_SHIFT24
+/* DMA Channel 1 PCI-to-Local Almost Empty (divided by 2, minus 1) */
+#define PLX_DMATHR_C1PLAE(x) (BIT(28) * ((x) & 0xf))
+#define PLX_DMATHR_C1PLAE_MASK GENMASK(31, 28)
+#define PLX_DMATHR_C1PLAE_SHIFT28
+
+/*
* Messaging Queue Registers OPLFIS, OPLFIM, IQP, OQP, MQCR, QBAR, IFHPR,
* IFTPR, IPHPR, IPTPR, OFHPR, OFTPR, OPHPR, OPTPR, and QSR have been omitted.
* They are used by the I2O feature. (IQP and OQP occupy the usual offsets of
--
2.8.1
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[PATCH 14/20] staging: comedi: drivers: re-do PLX PCI 9080 DMAMODEx register values
Replace the existing macros in "plx9080.h" that define values for the
DMAMODE0 and DMAMODE1 registers. Use the prefix `PLX_DMAMODE_` for the
macros. Make use of the `BIT(x)` and `GENMASK(h,l)` macros to define
the values.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/cb_pcidas64.c | 20 +--
drivers/staging/comedi/drivers/gsc_hpdi.c| 16 -
drivers/staging/comedi/drivers/plx9080.h | 52 +++-
3 files changed, 53 insertions(+), 35 deletions(-)
diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c
b/drivers/staging/comedi/drivers/cb_pcidas64.c
index dfb2ae8..48aca06 100644
--- a/drivers/staging/comedi/drivers/cb_pcidas64.c
+++ b/drivers/staging/comedi/drivers/cb_pcidas64.c
@@ -1308,28 +1308,28 @@ static void init_plx9080(struct comedi_device *dev)
/* configure dma0 mode */
bits = 0;
/* enable ready input, not sure if this is necessary */
- bits |= PLX_DMA_EN_READYIN_BIT;
+ bits |= PLX_DMAMODE_READYIEN;
/* enable bterm, not sure if this is necessary */
- bits |= PLX_EN_BTERM_BIT;
+ bits |= PLX_DMAMODE_BTERMIEN;
/* enable dma chaining */
- bits |= PLX_EN_CHAIN_BIT;
+ bits |= PLX_DMAMODE_CHAINEN;
/* enable interrupt on dma done
* (probably don't need this, since chain never finishes) */
- bits |= PLX_EN_DMA_DONE_INTR_BIT;
+ bits |= PLX_DMAMODE_DONEIEN;
/* don't increment local address during transfers
* (we are transferring from a fixed fifo register) */
- bits |= PLX_LOCAL_ADDR_CONST_BIT;
+ bits |= PLX_DMAMODE_LACONST;
/* route dma interrupt to pci bus */
- bits |= PLX_DMA_INTR_PCI_BIT;
+ bits |= PLX_DMAMODE_INTRPCI;
/* enable demand mode */
- bits |= PLX_DEMAND_MODE_BIT;
+ bits |= PLX_DMAMODE_DEMAND;
/* enable local burst mode */
- bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
+ bits |= PLX_DMAMODE_BURSTEN;
/* 4020 uses 32 bit dma */
if (board->layout == LAYOUT_4020)
- bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
+ bits |= PLX_DMAMODE_WIDTH32;
else/* localspace0 bus is 16 bits wide */
- bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
+ bits |= PLX_DMAMODE_WIDTH16;
writel(bits, plx_iobase + PLX_REG_DMAMODE1);
if (ao_cmd_is_supported(board))
writel(bits, plx_iobase + PLX_REG_DMAMODE0);
diff --git a/drivers/staging/comedi/drivers/gsc_hpdi.c
b/drivers/staging/comedi/drivers/gsc_hpdi.c
index e288798..d63dc46 100644
--- a/drivers/staging/comedi/drivers/gsc_hpdi.c
+++ b/drivers/staging/comedi/drivers/gsc_hpdi.c
@@ -563,26 +563,26 @@ static void gsc_hpdi_init_plx9080(struct comedi_device
*dev)
/* configure dma0 mode */
bits = 0;
/* enable ready input */
- bits |= PLX_DMA_EN_READYIN_BIT;
+ bits |= PLX_DMAMODE_READYIEN;
/* enable dma chaining */
- bits |= PLX_EN_CHAIN_BIT;
+ bits |= PLX_DMAMODE_CHAINEN;
/*
* enable interrupt on dma done
* (probably don't need this, since chain never finishes)
*/
- bits |= PLX_EN_DMA_DONE_INTR_BIT;
+ bits |= PLX_DMAMODE_DONEIEN;
/*
* don't increment local address during transfers
* (we are transferring from a fixed fifo register)
*/
- bits |= PLX_LOCAL_ADDR_CONST_BIT;
+ bits |= PLX_DMAMODE_LACONST;
/* route dma interrupt to pci bus */
- bits |= PLX_DMA_INTR_PCI_BIT;
+ bits |= PLX_DMAMODE_INTRPCI;
/* enable demand mode */
- bits |= PLX_DEMAND_MODE_BIT;
+ bits |= PLX_DMAMODE_DEMAND;
/* enable local burst mode */
- bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
- bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
+ bits |= PLX_DMAMODE_BURSTEN;
+ bits |= PLX_DMAMODE_WIDTH32;
writel(bits, plx_iobase + PLX_REG_DMAMODE0);
}
diff --git a/drivers/staging/comedi/drivers/plx9080.h
b/drivers/staging/comedi/drivers/plx9080.h
index c70af5e..99c075c 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -457,23 +457,41 @@ struct plx_dma_desc {
#define PLX_REG_DMAMODE0 0x0080
#define PLX_REG_DMAMODE1 0x0094
-#define PLX_LOCAL_BUS_16_WIDE_BITS0x1
-#define PLX_LOCAL_BUS_32_WIDE_BITS0x3
-#define PLX_LOCAL_BUS_WIDTH_MASK 0x3
-#define PLX_DMA_EN_READYIN_BIT0x40/* enable ready in input */
-#define PLX_EN_BTERM_BIT 0x80/* enable BTERM# input */
-#define PLX_DMA_LOCAL_BURST_EN_BIT0x100 /* enable local burst mode */
-#define PLX_EN_CHAIN_BIT 0x200 /* enables chaining */
-/* enables interrupt on dma done */
-#define PLX_EN_DMA_DONE_INTR_BIT 0x400
-/* hold local address constant (don't increment) */
-#define PLX_LOCAL_ADDR_CONST_BIT 0x800
-/* enables demand-mode for dma transfer */
-#define PLX_DEMAND_MODE_
[PATCH 15/20] staging: comedi: drivers: re-do PLX PCI 9080 DMADPRx register values
Replace the existing macros in "plx9080.h" that define values for the
DMADPR0 and DMADPR1 registers. (A little-endian version of the register
value is also placed in the `next` member of `struct plx_dma_desc`.)
Use the prefix `PLX_DMADPR_` for the macros. Make use of the `BIT(x)`
and `GENMASK(h,l)` macros to define the values.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/cb_pcidas64.c | 22 +++---
drivers/staging/comedi/drivers/gsc_hpdi.c| 8
drivers/staging/comedi/drivers/plx9080.h | 17 ++---
3 files changed, 25 insertions(+), 22 deletions(-)
diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c
b/drivers/staging/comedi/drivers/cb_pcidas64.c
index 48aca06..a4d10a3 100644
--- a/drivers/staging/comedi/drivers/cb_pcidas64.c
+++ b/drivers/staging/comedi/drivers/cb_pcidas64.c
@@ -1534,8 +1534,8 @@ static int alloc_and_init_dma_members(struct
comedi_device *dev)
cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
((i + 1) % ai_dma_ring_count(board)) *
sizeof(devpriv->ai_dma_desc[0])) |
- PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
- PLX_XFER_LOCAL_TO_PCI);
+ PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR |
+ PLX_DMADPR_XFERL2P);
}
if (ao_cmd_is_supported(board)) {
for (i = 0; i < AO_DMA_RING_COUNT; i++) {
@@ -1549,8 +1549,8 @@ static int alloc_and_init_dma_members(struct
comedi_device *dev)
cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
((i + 1) % (AO_DMA_RING_COUNT)) *
sizeof(devpriv->ao_dma_desc[0])) |
- PLX_DESC_IN_PCI_BIT |
- PLX_INTR_TERM_COUNT);
+ PLX_DMADPR_DESCPCI |
+ PLX_DMADPR_TCINTR);
}
}
return 0;
@@ -2634,9 +2634,9 @@ static int ai_cmd(struct comedi_device *dev, struct
comedi_subdevice *s)
/* give location of first dma descriptor */
load_first_dma_descriptor(dev, 1,
devpriv->ai_dma_desc_bus_addr |
- PLX_DESC_IN_PCI_BIT |
- PLX_INTR_TERM_COUNT |
- PLX_XFER_LOCAL_TO_PCI);
+ PLX_DMADPR_DESCPCI |
+ PLX_DMADPR_TCINTR |
+ PLX_DMADPR_XFERL2P);
dma_start_sync(dev, 1);
}
@@ -2918,7 +2918,7 @@ static void restart_ao_dma(struct comedi_device *dev)
unsigned int dma_desc_bits;
dma_desc_bits = readl(devpriv->plx9080_iobase + PLX_REG_DMADPR0);
- dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
+ dma_desc_bits &= ~PLX_DMADPR_CHAINEND;
load_first_dma_descriptor(dev, 0, dma_desc_bits);
dma_start_sync(dev, 0);
@@ -2959,14 +2959,14 @@ static unsigned int load_ao_dma_buffer(struct
comedi_device *dev,
devpriv->ao_dma_desc[buffer_index].transfer_size = cpu_to_le32(nbytes);
/* set end of chain bit so we catch underruns */
next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
- next_bits |= PLX_END_OF_CHAIN_BIT;
+ next_bits |= PLX_DMADPR_CHAINEND;
devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
/*
* clear end of chain bit on previous buffer now that we have set it
* for the last buffer
*/
next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
- next_bits &= ~PLX_END_OF_CHAIN_BIT;
+ next_bits &= ~PLX_DMADPR_CHAINEND;
devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
@@ -3310,7 +3310,7 @@ static int ao_cmd(struct comedi_device *dev, struct
comedi_subdevice *s)
set_dac_select_reg(dev, cmd);
set_dac_interval_regs(dev, cmd);
load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
- PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
+ PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR);
set_dac_control1_reg(dev, cmd);
s->async->inttrig = ao_inttrig;
diff --git a/drivers/staging/comedi/drivers/gsc_hpdi.c
b/drivers/staging/comedi/drivers/gsc_hpdi.c
index d63dc46..f2f1874 100644
--- a/drivers/staging/comedi/drivers/gsc_hpdi.c
+++ b/drivers/staging/comedi/drivers/gsc_hpdi.c
@@ -310,8 +310,8 @@ static int gsc_hpdi_cmd(struct comedi_device *dev,
writel(0, devpriv->plx9080_mmio
[PATCH 07/20] staging: comedi: drivers: re-do PLX PCI 9080 BIGEND register values
Replace `enum bigend_bits` in "plx9080.h" with a bunch of macros
defining values for the BIGEND register. Use the prefix `PLX_BIGEND_`
for the macro names. Make use of the `BIT(x)` and `GENMASK(h,l)` macros
to define the values.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/cb_pcidas64.c | 2 +-
drivers/staging/comedi/drivers/gsc_hpdi.c| 2 +-
drivers/staging/comedi/drivers/plx9080.h | 33 +++-
3 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c
b/drivers/staging/comedi/drivers/cb_pcidas64.c
index f997c1f..4a8e88a 100644
--- a/drivers/staging/comedi/drivers/cb_pcidas64.c
+++ b/drivers/staging/comedi/drivers/cb_pcidas64.c
@@ -1294,7 +1294,7 @@ static void init_plx9080(struct comedi_device *dev)
readl(devpriv->plx9080_iobase + PLX_REG_CNTRL);
#ifdef __BIG_ENDIAN
- bits = BIGEND_DMA0 | BIGEND_DMA1;
+ bits = PLX_BIGEND_DMA0 | PLX_BIGEND_DMA1;
#else
bits = 0;
#endif
diff --git a/drivers/staging/comedi/drivers/gsc_hpdi.c
b/drivers/staging/comedi/drivers/gsc_hpdi.c
index e2831e1..536bebe 100644
--- a/drivers/staging/comedi/drivers/gsc_hpdi.c
+++ b/drivers/staging/comedi/drivers/gsc_hpdi.c
@@ -547,7 +547,7 @@ static void gsc_hpdi_init_plx9080(struct comedi_device *dev)
void __iomem *plx_iobase = devpriv->plx9080_mmio;
#ifdef __BIG_ENDIAN
- bits = BIGEND_DMA0 | BIGEND_DMA1;
+ bits = PLX_BIGEND_DMA0 | PLX_BIGEND_DMA1;
#else
bits = 0;
#endif
diff --git a/drivers/staging/comedi/drivers/plx9080.h
b/drivers/staging/comedi/drivers/plx9080.h
index 0bcdbad..84dd366 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -125,21 +125,24 @@ struct plx_dma_desc {
/* Big/Little Endian Descriptor Register */
#define PLX_REG_BIGEND 0x000c
-enum bigend_bits {
- /* use big endian ordering for configuration register accesses */
- BIGEND_CONFIG = 0x1,
- BIGEND_DIRECT_MASTER = 0x2,
- BIGEND_DIRECT_SLAVE_LOCAL0 = 0x4,
- BIGEND_ROM = 0x8,
- /*
-* use byte lane consisting of most significant bits instead of
-* least significant
-*/
- BIGEND_BYTE_LANE = 0x10,
- BIGEND_DIRECT_SLAVE_LOCAL1 = 0x20,
- BIGEND_DMA1 = 0x40,
- BIGEND_DMA0 = 0x80,
-};
+/* Configuration Register Big Endian Mode */
+#define PLX_BIGEND_CONFIG BIT(0)
+/* Direct Master Big Endian Mode */
+#define PLX_BIGEND_DM BIT(1)
+/* Direct Slave Address Space 0 Big Endian Mode */
+#define PLX_BIGEND_DSAS0 BIT(2)
+/* Direct Slave Expansion ROM Big Endian Mode */
+#define PLX_BIGEND_EROMBIT(3)
+/* Big Endian Byte Lane Mode - use most significant byte lanes */
+#define PLX_BIGEND_BEBLM BIT(4)
+/* Direct Slave Address Space 1 Big Endian Mode */
+#define PLX_BIGEND_DSAS1 BIT(5)
+/* DMA Channel 1 Big Endian Mode */
+#define PLX_BIGEND_DMA1BIT(6)
+/* DMA Channel 0 Big Endian Mode */
+#define PLX_BIGEND_DMA0BIT(7)
+/* DMA Channel N Big Endian Mode (N <= 1) */
+#define PLX_BIGEND_DMA(n) ((n) ? PLX_BIGEND_DMA1 : PLX_BIGEND_DMA0)
/*
** Note: The Expansion ROM stuff is only relevant to the PC environment.
--
2.8.1
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[PATCH 19/20] staging: comedi: plx9080.h: Add kerneldoc comments
Document the DMA descriptor `struct plx_dma_desc`, and the DMA abort
function `plx9080_abort_dma()`.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/plx9080.h | 35 ++--
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/comedi/drivers/plx9080.h
b/drivers/staging/comedi/drivers/plx9080.h
index d701b15..f67f9d7 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -19,16 +19,27 @@
#ifndef __COMEDI_PLX9080_H
#define __COMEDI_PLX9080_H
-/* descriptor block used for chained dma transfers */
+/**
+ * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
+ * @pci_start_addr:PCI Bus address for transfer (DMAPADR).
+ * @local_start_addr: Local Bus address for transfer (DMALADR).
+ * @transfer_size: Transfer size in bytes (max 8 MiB) (DMASIZ).
+ * @next: Address of next descriptor + flags (DMADPR).
+ *
+ * Describes the format of a scatter-gather DMA descriptor for the PLX
+ * PCI 9080. All members are raw, little-endian register values that
+ * will be transferred by the DMA engine from local or PCI memory into
+ * corresponding registers for the DMA channel.
+ *
+ * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0
+ * of @next contain flags describing the address space of the next
+ * descriptor (local or PCI), an "end of chain" marker, an "interrupt on
+ * terminal count" bit, and a data transfer direction.
+ */
struct plx_dma_desc {
__le32 pci_start_addr;
__le32 local_start_addr;
- /* transfer_size is in bytes, only first 23 bits of register are used */
__le32 transfer_size;
- /*
-* address of next descriptor (quad word aligned), plus some
-* additional bits (see PLX_REG_DMADPR)
-*/
__le32 next;
};
@@ -594,6 +605,18 @@ struct plx_dma_desc {
#define PLX_PREFETCH 32
+/**
+ * plx9080_abort_dma - Abort a PLX PCI 9080 DMA transfer
+ * @iobase:Remapped base address of configuration registers.
+ * @channel: DMA channel number (0 or 1).
+ *
+ * Aborts the DMA transfer on the channel, which must have been enabled
+ * and started beforehand.
+ *
+ * Return:
+ * %0 on success.
+ * -%ETIMEDOUT if timed out waiting for abort to complete.
+ */
static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel)
{
void __iomem *dma_cs_addr;
--
2.8.1
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[PATCH 16/20] staging: comedi: drivers: re-do PLX PCI 9080 DMACSRx register values
Replace the existing macros in "plx9080.h" that define values for the
DMACSR0 and DMACSR0 registers. Use the prefix `PLX_DMACSR_` for the
macros. Make use of the `BIT(x)` macro to define the values.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/cb_pcidas64.c | 22 +++---
drivers/staging/comedi/drivers/gsc_hpdi.c| 8
drivers/staging/comedi/drivers/plx9080.h | 23 ++-
3 files changed, 29 insertions(+), 24 deletions(-)
diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c
b/drivers/staging/comedi/drivers/cb_pcidas64.c
index a4d10a3..1f9c08a 100644
--- a/drivers/staging/comedi/drivers/cb_pcidas64.c
+++ b/drivers/staging/comedi/drivers/cb_pcidas64.c
@@ -2368,7 +2368,7 @@ static inline void dma_start_sync(struct comedi_device
*dev,
/* spinlock for plx dma control/status reg */
spin_lock_irqsave(&dev->spinlock, flags);
- writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
+ writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_START | PLX_DMACSR_CLEARINTR,
devpriv->plx9080_iobase + PLX_REG_DMACSR(channel));
spin_unlock_irqrestore(&dev->spinlock, flags);
}
@@ -2838,10 +2838,10 @@ static void handle_ai_interrupt(struct comedi_device
*dev,
spin_lock_irqsave(&dev->spinlock, flags);
dma1_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR1);
if (plx_status & PLX_INTCSR_DMA1IA) { /* dma chan 1 interrupt */
- writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
+ writeb((dma1_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR,
devpriv->plx9080_iobase + PLX_REG_DMACSR1);
- if (dma1_status & PLX_DMA_EN_BIT)
+ if (dma1_status & PLX_DMACSR_ENABLE)
drain_dma_buffers(dev, 1);
}
spin_unlock_irqrestore(&dev->spinlock, flags);
@@ -2889,7 +2889,7 @@ static int last_ao_dma_load_completed(struct
comedi_device *dev)
buffer_index = prev_ao_dma_index(dev);
dma_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0);
- if ((dma_status & PLX_DMA_DONE_BIT) == 0)
+ if ((dma_status & PLX_DMACSR_DONE) == 0)
return 0;
transfer_address =
@@ -2903,8 +2903,8 @@ static int last_ao_dma_load_completed(struct
comedi_device *dev)
static inline int ao_dma_needs_restart(struct comedi_device *dev,
unsigned short dma_status)
{
- if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
- (dma_status & PLX_DMA_EN_BIT) == 0)
+ if ((dma_status & PLX_DMACSR_DONE) == 0 ||
+ (dma_status & PLX_DMACSR_ENABLE) == 0)
return 0;
if (last_ao_dma_load_completed(dev))
return 0;
@@ -3016,16 +3016,16 @@ static void handle_ao_interrupt(struct comedi_device
*dev,
spin_lock_irqsave(&dev->spinlock, flags);
dma0_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0);
if (plx_status & PLX_INTCSR_DMA0IA) { /* dma chan 0 interrupt */
- if ((dma0_status & PLX_DMA_EN_BIT) &&
- !(dma0_status & PLX_DMA_DONE_BIT)) {
- writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
+ if ((dma0_status & PLX_DMACSR_ENABLE) &&
+ !(dma0_status & PLX_DMACSR_DONE)) {
+ writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_CLEARINTR,
devpriv->plx9080_iobase + PLX_REG_DMACSR0);
} else {
- writeb(PLX_CLEAR_DMA_INTR_BIT,
+ writeb(PLX_DMACSR_CLEARINTR,
devpriv->plx9080_iobase + PLX_REG_DMACSR0);
}
spin_unlock_irqrestore(&dev->spinlock, flags);
- if (dma0_status & PLX_DMA_EN_BIT) {
+ if (dma0_status & PLX_DMACSR_ENABLE) {
load_ao_dma(dev, cmd);
/* try to recover from dma end-of-chain event */
if (ao_dma_needs_restart(dev, dma0_status))
diff --git a/drivers/staging/comedi/drivers/gsc_hpdi.c
b/drivers/staging/comedi/drivers/gsc_hpdi.c
index f2f1874..af4b417 100644
--- a/drivers/staging/comedi/drivers/gsc_hpdi.c
+++ b/drivers/staging/comedi/drivers/gsc_hpdi.c
@@ -214,10 +214,10 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
dma0_status = readb(devpriv->plx9080_mmio + PLX_REG_DMACSR0);
if (plx_status & PLX_INTCSR_DMA0IA) {
/* dma chan 0 interrupt */
- writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
+ writeb((dma0_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR,
devpriv->plx9080_mmio + PLX_REG_DMACSR0);
- if (dma0_status & PLX_DMA_EN_BIT)
+ if (dma0_status & PLX_DMACSR_ENABLE)
gsc_hpdi_drain_dma(dev, 0);
}
spin_unl
[PATCH 20/20] staging: comedi: plx9080.h: include headers for declarations
Add `#include` lines to declare stuff used by "plx9080.h" itself. Signed-off-by: Ian Abbott --- drivers/staging/comedi/drivers/plx9080.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h index f67f9d7..0e20cc5 100644 --- a/drivers/staging/comedi/drivers/plx9080.h +++ b/drivers/staging/comedi/drivers/plx9080.h @@ -19,6 +19,13 @@ #ifndef __COMEDI_PLX9080_H #define __COMEDI_PLX9080_H +#include +#include +#include +#include +#include +#include + /** * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080 * @pci_start_addr:PCI Bus address for transfer (DMAPADR). -- 2.8.1 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH 12/20] staging: comedi: drivers: re-do PLX PCI 9080 CNTRL register values
Replace the existing macros in "plx9080.h" that define values for the
CNTRL register. Use the prefix `PLX_CNTRL_` for the macros. Make use
of the `BIT(x)` and `GENMASK(h,l)` macros to define the values.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/cb_pcidas64.c | 31 +++---
drivers/staging/comedi/drivers/plx9080.h | 63 +---
2 files changed, 65 insertions(+), 29 deletions(-)
diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c
b/drivers/staging/comedi/drivers/cb_pcidas64.c
index 6b3f4dc..dfb2ae8 100644
--- a/drivers/staging/comedi/drivers/cb_pcidas64.c
+++ b/drivers/staging/comedi/drivers/cb_pcidas64.c
@@ -1614,7 +1614,7 @@ static const int i2c_low_udelay = 10;
static void i2c_set_sda(struct comedi_device *dev, int state)
{
struct pcidas64_private *devpriv = dev->private;
- static const int data_bit = CTL_EE_W;
+ static const int data_bit = PLX_CNTRL_EEWB;
void __iomem *plx_control_addr = devpriv->plx9080_iobase +
PLX_REG_CNTRL;
@@ -1635,7 +1635,7 @@ static void i2c_set_sda(struct comedi_device *dev, int
state)
static void i2c_set_scl(struct comedi_device *dev, int state)
{
struct pcidas64_private *devpriv = dev->private;
- static const int clock_bit = CTL_USERO;
+ static const int clock_bit = PLX_CNTRL_USERO;
void __iomem *plx_control_addr = devpriv->plx9080_iobase +
PLX_REG_CNTRL;
@@ -1708,7 +1708,7 @@ static void i2c_write(struct comedi_device *dev, unsigned
int address,
*/
/* make sure we dont send anything to eeprom */
- devpriv->plx_control_bits &= ~CTL_EE_CS;
+ devpriv->plx_control_bits &= ~PLX_CNTRL_EECS;
i2c_stop(dev);
i2c_start(dev);
@@ -3717,13 +3717,13 @@ static uint16_t read_eeprom(struct comedi_device *dev,
uint8_t address)
static const int eeprom_udelay = 1;
udelay(eeprom_udelay);
- devpriv->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
+ devpriv->plx_control_bits &= ~PLX_CNTRL_EESK & ~PLX_CNTRL_EECS;
/* make sure we don't send anything to the i2c bus on 4020 */
- devpriv->plx_control_bits |= CTL_USERO;
+ devpriv->plx_control_bits |= PLX_CNTRL_USERO;
writel(devpriv->plx_control_bits, plx_control_addr);
/* activate serial eeprom */
udelay(eeprom_udelay);
- devpriv->plx_control_bits |= CTL_EE_CS;
+ devpriv->plx_control_bits |= PLX_CNTRL_EECS;
writel(devpriv->plx_control_bits, plx_control_addr);
/* write read command and desired memory address */
@@ -3731,16 +3731,16 @@ static uint16_t read_eeprom(struct comedi_device *dev,
uint8_t address)
/* set bit to be written */
udelay(eeprom_udelay);
if (bitstream & bit)
- devpriv->plx_control_bits |= CTL_EE_W;
+ devpriv->plx_control_bits |= PLX_CNTRL_EEWB;
else
- devpriv->plx_control_bits &= ~CTL_EE_W;
+ devpriv->plx_control_bits &= ~PLX_CNTRL_EEWB;
writel(devpriv->plx_control_bits, plx_control_addr);
/* clock in bit */
udelay(eeprom_udelay);
- devpriv->plx_control_bits |= CTL_EE_CLK;
+ devpriv->plx_control_bits |= PLX_CNTRL_EESK;
writel(devpriv->plx_control_bits, plx_control_addr);
udelay(eeprom_udelay);
- devpriv->plx_control_bits &= ~CTL_EE_CLK;
+ devpriv->plx_control_bits &= ~PLX_CNTRL_EESK;
writel(devpriv->plx_control_bits, plx_control_addr);
}
/* read back value from eeprom memory location */
@@ -3748,19 +3748,19 @@ static uint16_t read_eeprom(struct comedi_device *dev,
uint8_t address)
for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
/* clock out bit */
udelay(eeprom_udelay);
- devpriv->plx_control_bits |= CTL_EE_CLK;
+ devpriv->plx_control_bits |= PLX_CNTRL_EESK;
writel(devpriv->plx_control_bits, plx_control_addr);
udelay(eeprom_udelay);
- devpriv->plx_control_bits &= ~CTL_EE_CLK;
+ devpriv->plx_control_bits &= ~PLX_CNTRL_EESK;
writel(devpriv->plx_control_bits, plx_control_addr);
udelay(eeprom_udelay);
- if (readl(plx_control_addr) & CTL_EE_R)
+ if (readl(plx_control_addr) & PLX_CNTRL_EERB)
value |= bit;
}
/* deactivate eeprom serial input */
udelay(eeprom_udelay);
- devpriv->plx_control_bits &= ~CTL_EE_CS;
+ devpriv->plx_control_bits &= ~PLX_CNTRL_EECS;
writel(devpriv->plx_control_bits, plx_control_addr);
return value;
@@ -3948,7 +3948,8 @@ static int setup_subdevices(struct comedi_device *dev
[PATCH 13/20] staging: comedi: plx9080.h: add hard-coded PCIHIDR register value
For the PLX PCI 9080, the read-only PCIHIDR register is hard-coded with
the value `0x908010b5`. Add a macro `PLX_PCIHIDR_9080` that expands to
this value.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/plx9080.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/staging/comedi/drivers/plx9080.h
b/drivers/staging/comedi/drivers/plx9080.h
index 4ad9464..c70af5e 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -446,6 +446,9 @@ struct plx_dma_desc {
/* PCI Permanent Configuration ID Register (hard-coded PLX vendor and device)
*/
#define PLX_REG_PCIHIDR0x0070
+/* Hard-coded ID for PLX PCI 9080 */
+#define PLX_PCIHIDR_9080 0x908010b5
+
/* PCI Permanent Revision ID Register (hard-coded silicon revision) (8-bit). */
#define PLX_REG_PCIHREV0x0074
--
2.8.1
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[PATCH 11/20] staging: comedi: drivers: re-do PLX PCI 9080 INTCSR register values
Replace the existing macros in "plx9080.h" that define values for the
INTCSR register. Use the prefix `PLX_INTCSR_` for the macros. Make use
of the `BIT(x)` and `GENMASK(h,l)` macros to define the values.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/cb_pcidas64.c | 14 +++--
drivers/staging/comedi/drivers/gsc_hpdi.c| 14 +++--
drivers/staging/comedi/drivers/plx9080.h | 91
drivers/staging/comedi/drivers/rtd520.c | 3 +-
4 files changed, 83 insertions(+), 39 deletions(-)
diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c
b/drivers/staging/comedi/drivers/cb_pcidas64.c
index 4a8e88a..6b3f4dc 100644
--- a/drivers/staging/comedi/drivers/cb_pcidas64.c
+++ b/drivers/staging/comedi/drivers/cb_pcidas64.c
@@ -1336,8 +1336,9 @@ static void init_plx9080(struct comedi_device *dev)
/* enable interrupts on plx 9080 */
devpriv->plx_intcsr_bits |=
- ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
- ICS_DMA0_E | ICS_DMA1_E;
+ PLX_INTCSR_LSEABORTEN | PLX_INTCSR_LSEPARITYEN | PLX_INTCSR_PIEN |
+ PLX_INTCSR_PLIEN | PLX_INTCSR_PABORTIEN | PLX_INTCSR_LIOEN |
+ PLX_INTCSR_DMA0IEN | PLX_INTCSR_DMA1IEN;
writel(devpriv->plx_intcsr_bits,
devpriv->plx9080_iobase + PLX_REG_INTCSR);
}
@@ -2836,7 +2837,7 @@ static void handle_ai_interrupt(struct comedi_device *dev,
/* spin lock makes sure no one else changes plx dma control reg */
spin_lock_irqsave(&dev->spinlock, flags);
dma1_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR1);
- if (plx_status & ICS_DMA1_A) { /* dma chan 1 interrupt */
+ if (plx_status & PLX_INTCSR_DMA1IA) { /* dma chan 1 interrupt */
writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
devpriv->plx9080_iobase + PLX_REG_DMACSR1);
@@ -3014,7 +3015,7 @@ static void handle_ao_interrupt(struct comedi_device *dev,
/* spin lock makes sure no one else changes plx dma control reg */
spin_lock_irqsave(&dev->spinlock, flags);
dma0_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0);
- if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
+ if (plx_status & PLX_INTCSR_DMA0IA) { /* dma chan 0 interrupt */
if ((dma0_status & PLX_DMA_EN_BIT) &&
!(dma0_status & PLX_DMA_DONE_BIT)) {
writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
@@ -3067,8 +3068,9 @@ static irqreturn_t handle_interrupt(int irq, void *d)
handle_ai_interrupt(dev, status, plx_status);
handle_ao_interrupt(dev, status, plx_status);
- /* clear possible plx9080 interrupt sources */
- if (plx_status & ICS_LDIA) {/* clear local doorbell interrupt */
+ /* clear possible plx9080 interrupt sources */
+ if (plx_status & PLX_INTCSR_LDBIA) {
+ /* clear local doorbell interrupt */
plx_bits = readl(devpriv->plx9080_iobase + PLX_REG_L2PDBELL);
writel(plx_bits, devpriv->plx9080_iobase + PLX_REG_L2PDBELL);
}
diff --git a/drivers/staging/comedi/drivers/gsc_hpdi.c
b/drivers/staging/comedi/drivers/gsc_hpdi.c
index 536bebe..e288798 100644
--- a/drivers/staging/comedi/drivers/gsc_hpdi.c
+++ b/drivers/staging/comedi/drivers/gsc_hpdi.c
@@ -199,7 +199,8 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
return IRQ_NONE;
plx_status = readl(devpriv->plx9080_mmio + PLX_REG_INTCSR);
- if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
+ if ((plx_status &
+(PLX_INTCSR_DMA0IA | PLX_INTCSR_DMA1IA | PLX_INTCSR_PLIA)) == 0)
return IRQ_NONE;
hpdi_intr_status = readl(dev->mmio + INTERRUPT_STATUS_REG);
@@ -211,7 +212,7 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
/* spin lock makes sure no one else changes plx dma control reg */
spin_lock_irqsave(&dev->spinlock, flags);
dma0_status = readb(devpriv->plx9080_mmio + PLX_REG_DMACSR0);
- if (plx_status & ICS_DMA0_A) {
+ if (plx_status & PLX_INTCSR_DMA0IA) {
/* dma chan 0 interrupt */
writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
devpriv->plx9080_mmio + PLX_REG_DMACSR0);
@@ -224,7 +225,7 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
/* spin lock makes sure no one else changes plx dma control reg */
spin_lock_irqsave(&dev->spinlock, flags);
dma1_status = readb(devpriv->plx9080_mmio + PLX_REG_DMACSR1);
- if (plx_status & ICS_DMA1_A) {
+ if (plx_status & PLX_INTCSR_DMA1IA) {
/* XXX */ /* dma chan 1 interrupt */
writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
devpriv->plx9080_mmio + PLX_REG_DMACSR1);
@@ -232,7 +233,7 @@ static irqreturn_t gsc_hpdi_
[PATCH 18/20] staging: comedi: plx9080.h: tidy up some comments
Use the usual block comment style and remove some excess spaces from
single-line comments. Remove some obvious stuff about register offsets
being zero relative. Remove some text about the original history of the
file, as it bears hardly any resemblance to it now.
Signed-off-by: Ian Abbott
---
drivers/staging/comedi/drivers/plx9080.h | 36 +++-
1 file changed, 12 insertions(+), 24 deletions(-)
diff --git a/drivers/staging/comedi/drivers/plx9080.h
b/drivers/staging/comedi/drivers/plx9080.h
index 50d0b1b..d701b15 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -3,15 +3,6 @@
*
* Copyright (C) 2002,2003 Frank Mori Hess
*
- * I modified this file from the plx9060.h header for the
- * wanXL device driver in the linux kernel,
- * for the register offsets and bit definitions. Made minor modifications,
- * added plx9080 registers and
- * stripped out stuff that was specifically for the wanXL driver.
- * Note: I've only made sure the definitions are correct as far
- * as I make use of them. There are still various plx9060-isms
- * left in this header file.
- *
*
* Copyright (C) 1999 RG Studio s.c.
@@ -28,7 +19,7 @@
#ifndef __COMEDI_PLX9080_H
#define __COMEDI_PLX9080_H
-/* descriptor block used for chained dma transfers */
+/* descriptor block used for chained dma transfers */
struct plx_dma_desc {
__le32 pci_start_addr;
__le32 local_start_addr;
@@ -41,13 +32,9 @@ struct plx_dma_desc {
__le32 next;
};
-/**
-**Register Offsets and Bit Definitions
-**
-** Note: All offsets zero relative. IE. Some standard base address
-** must be added to the Register Number to properly access the register.
-**
-**/
+/*
+ * Register Offsets and Bit Definitions
+ */
/* Local Address Space 0 Range Register */
#define PLX_REG_LAS0RR 0x
@@ -145,10 +132,11 @@ struct plx_dma_desc {
#define PLX_BIGEND_DMA(n) ((n) ? PLX_BIGEND_DMA1 : PLX_BIGEND_DMA0)
/*
-** Note: The Expansion ROM stuff is only relevant to the PC environment.
-** This expansion ROM code is executed by the host CPU at boot time.
-** For this reason no bit definitions are provided here.
+ * Note: The Expansion ROM stuff is only relevant to the PC environment.
+ * This expansion ROM code is executed by the host CPU at boot time.
+ * For this reason no bit definitions are provided here.
*/
+
/* Expansion ROM Range Register */
#define PLX_REG_EROMRR 0x0010
/* Expansion ROM Local Base Address (Remap) Register */
@@ -615,12 +603,12 @@ static inline int plx9080_abort_dma(void __iomem *iobase,
unsigned int channel)
dma_cs_addr = iobase + PLX_REG_DMACSR(channel);
- /* abort dma transfer if necessary */
+ /* abort dma transfer if necessary */
dma_status = readb(dma_cs_addr);
if ((dma_status & PLX_DMACSR_ENABLE) == 0)
return 0;
- /* wait to make sure done bit is zero */
+ /* wait to make sure done bit is zero */
for (i = 0; (dma_status & PLX_DMACSR_DONE) && i < timeout; i++) {
udelay(1);
dma_status = readb(dma_cs_addr);
@@ -628,9 +616,9 @@ static inline int plx9080_abort_dma(void __iomem *iobase,
unsigned int channel)
if (i == timeout)
return -ETIMEDOUT;
- /* disable and abort channel */
+ /* disable and abort channel */
writeb(PLX_DMACSR_ABORT, dma_cs_addr);
- /* wait for dma done bit */
+ /* wait for dma done bit */
dma_status = readb(dma_cs_addr);
for (i = 0; (dma_status & PLX_DMACSR_DONE) == 0 && i < timeout; i++) {
udelay(1);
--
2.8.1
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RE: [PATCH v2] Drivers: hv: vmbus: fix the race when querying & updating the percpu list
> From: devel [mailto:driverdev-devel-boun...@linuxdriverproject.org] On > Behalf Of Dexuan Cui > Sent: Wednesday, May 18, 2016 11:44 > To: gre...@linuxfoundation.org; linux-ker...@vger.kernel.org; driverdev- > de...@linuxdriverproject.org; o...@aepfle.de; a...@canonical.com; > jasow...@redhat.com; KY Srinivasan ; > vkuzn...@redhat.com > Cc: Haiyang Zhang > Subject: [PATCH v2] Drivers: hv: vmbus: fix the race when querying & > updating the percpu list > > There is a rare race when we remove an entry from the global list > hv_context.percpu_list[cpu] in hv_process_channel_removal() -> > percpu_channel_deq() -> list_del(): at this time, if vmbus_on_event() -> > process_chn_event() -> pcpu_relid2channel() is trying to query the list, > we can get the general protection fault: > > general protection fault: [#1] SMP > ... > RIP: 0010:[] [] > vmbus_on_event+0xc4/0x149 > > Similarly, we also have the issue in the code path: vmbus_process_offer() -> > percpu_channel_enq(). > > We can resolve the issue by disabling the tasklet when updating the list. > > Reported-by: Rolf Neugebauer > Cc: Vitaly Kuznetsov > Signed-off-by: Dexuan Cui > --- > > v2: added tasklet_schedule() after tasklet_enable(). Thanks, Vitaly! Please ignore the patch for now. I found an issue with the patch: after I moved percpu_channel_deq() from hv_process_channel_removal() to vmbus_close_internal(), the channel couldn't be removed from the per-cpu list, if the channel state was not CHANNEL_OPENED_STATE. I'll have to think about this and fix the issue in the next version. Thanks, -- Dexuan ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
RE: [PATCH 03/20] staging: comedi: drivers: rename PLX PCI 9080 register offsets
On Friday, May 20, 2016 6:49 AM, Ian Abbott wrote: > Rename the macros in "plx9080.h" that define the offsets of registers, > following the pattern `PLX_REG_`, where `` is the register > name from the PLX PCI 9080 Data Book. > > Add defines for the "Mailbox" registers, and add parameterized macros > for the mailbox registers and the DMA control registers. Make use of > the parameterized versions of the macros where it seems appropriate. > > The registers for supporting the I2O (Intelligent Input/Output) feature > are largely left undefined, just defining enough to allow the I2O > feature to be disabled. > > Signed-off-by: Ian Abbott Ian, Just an comment on your renaming. You also renamed the registers in the daqbook2000 driver in the _REG_ format. Personally I prefer the format to be __REG. That way a grep for _ will return both the register and bit uses. Currently the _REG_ form is not as common in comedi. Looks like it's only used in amcc_35933.h and will be in daqboard2000.c. The __REG form is used a lot. Not a big deal, just a comment. Hartley ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH] staging/vme: explicitly use `unsigned int` instead of `unsigned`
Kernel code style is to prefer the former so add `int` to the method
parameters.
Signed-off-by: Daniel Lockyer
---
drivers/staging/vme/devices/vme_pio2_gpio.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/vme/devices/vme_pio2_gpio.c
b/drivers/staging/vme/devices/vme_pio2_gpio.c
index 6d361201..765cb2d 100644
--- a/drivers/staging/vme/devices/vme_pio2_gpio.c
+++ b/drivers/staging/vme/devices/vme_pio2_gpio.c
@@ -92,7 +92,7 @@ static void pio2_gpio_set(struct gpio_chip *chip,
}
/* Directionality configured at board build - send appropriate response */
-static int pio2_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
+static int pio2_gpio_dir_in(struct gpio_chip *chip, unsigned int offset)
{
int data;
struct pio2_card *card = gpiochip_get_data(chip);
@@ -111,7 +111,7 @@ static int pio2_gpio_dir_in(struct gpio_chip *chip,
unsigned offset)
}
/* Directionality configured at board build - send appropriate response */
-static int pio2_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int
value)
+static int pio2_gpio_dir_out(struct gpio_chip *chip, unsigned int offset, int
value)
{
int data;
struct pio2_card *card = gpiochip_get_data(chip);
--
2.8.2
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Re: [PATCH 03/20] staging: comedi: drivers: rename PLX PCI 9080 register offsets
On 20/05/16 17:21, Hartley Sweeten wrote: On Friday, May 20, 2016 6:49 AM, Ian Abbott wrote: Rename the macros in "plx9080.h" that define the offsets of registers, following the pattern `PLX_REG_`, where `` is the register name from the PLX PCI 9080 Data Book. Add defines for the "Mailbox" registers, and add parameterized macros for the mailbox registers and the DMA control registers. Make use of the parameterized versions of the macros where it seems appropriate. The registers for supporting the I2O (Intelligent Input/Output) feature are largely left undefined, just defining enough to allow the I2O feature to be disabled. Signed-off-by: Ian Abbott Ian, Just an comment on your renaming. You also renamed the registers in the daqbook2000 driver in the _REG_ format. Personally I prefer the format to be __REG. That way a grep for _ will return both the register and bit uses. Currently the _REG_ form is not as common in comedi. Looks like it's only used in amcc_35933.h and will be in daqboard2000.c. The __REG form is used a lot. Not a big deal, just a comment. It makes it easier to distinguish the register offsets from the register values, imho. -- -=( Ian Abbott @ MEV Ltd.E-mail: )=- -=( Web: http://www.mev.co.uk/ )=- ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
RE: [PATCH 04/20] staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxRR values
On Friday, May 20, 2016 6:49 AM, Ian Abbott wrote:
> Rename the macros for the PLX PCI 9080 LAS0RR and LAS1RR registers in
> "plx9080.h", using the prefix `PLX_LASRR_`. Make use of the `BIT(x)`
> and `GENMASK(h,l)` macros to define the values.
>
> Define a macro `PLX_LASRR_PREFETCH` for the "prefetchable memory" bit in
> this register, and define a macro `PLX_LASRR_MLOC_MASK` to mask the PCI
> memory location control bits.
>
> Signed-off-by: Ian Abbott
> ---
[snip]
> diff --git a/drivers/staging/comedi/drivers/plx9080.h
> b/drivers/staging/comedi/drivers/plx9080.h
> index 92d2480..8788117 100644
> --- a/drivers/staging/comedi/drivers/plx9080.h
> +++ b/drivers/staging/comedi/drivers/plx9080.h
> @@ -54,14 +54,16 @@ struct plx_dma_desc {
> /* Local Address Space 1 Range Register */
> #define PLX_REG_LAS1RR 0x00f0
>
> -#define LRNG_IO 0x0001/* Map to: 1=I/O, 0=Mem */
> -#define LRNG_ANY320x/* Locate anywhere in 32 bit */
> -#define LRNG_LT1MB0x0002/* Locate in 1st meg */
> -#define LRNG_ANY640x0004/* Locate anywhere in 64 bit */
> -/* bits that specify range for memory io */
> -#define LRNG_MEM_MASK 0xfff0
> -/* bits that specify range for normal io */
> -#define LRNG_IO_MASK 0xfffc
> +#define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem */
> +#define PLX_LASRR_ANY32 (BIT(1) * 0)/* Locate anywhere in
> 32 bit */
> +#define PLX_LASRR_LT1MB (BIT(1) * 1)/* Locate in 1st meg */
> +#define PLX_LASRR_ANY64 (BIT(1) * 2)/* Locate anywhere in
> 64 bit */
The (BIT(n) * x) looks ugly.
These bit define the memory space encoding. I would prefer something
like this:
#define PLX_LASSR_MLOC(x) (((x) & 0x3) << 1)
#define PLX_LASSR_MLOC_ANY32PLX_LASSR_MLOC(0)
#define PLX_LASSR_MLOC_LT1MBPLX_LASSR_MLOC(1)
#define PLX_LASSR_MLOC_ANY64PLX_LASSR_MLOC(2)
> +#define PLX_LASRR_MLOC_MASK GENMASK(2, 1) /* Memory location bits */
I guess the GENMASK() macro is common but it's currently
not used by any of the comedi code.
Using the macro above, the 'mask' would be:
#define PLX_LASSR_MLOC_MASK PLX_LASSR_MLOC(3)
> +#define PLX_LASRR_PREFETCH BIT(3) /* Memory is prefetchable */
> +/* bits that specify range for memory space decode bits */
> +#define PLX_LASRR_MEM_MASK GENMASK(31, 4)
> +/* bits that specify range for i/o space decode bits */
> +#define PLX_LASRR_IO_MASKGENMASK(31, 2)
I suppose the GENMASK() use makes sense for these.
Regards,
Hartley
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RE: [PATCH 03/20] staging: comedi: drivers: rename PLX PCI 9080 register offsets
On Friday, May 20, 2016 9:31 AM, Ian Abbott wrote: > On 20/05/16 17:21, Hartley Sweeten wrote: >> Just an comment on your renaming. >> >> You also renamed the registers in the daqbook2000 driver in the >> _REG_ format. Personally I prefer the format to be >> __REG. That way a grep for _ will >> return both the register and bit uses. > > It makes it easier to distinguish the register offsets from the register > values, imho. I guess. It's just not as common in comedi right now and it does make grep'ing for all the register/bit uses a bit more cumbersome. Regards, Hartley ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH 04/20] staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxRR values
On 20/05/16 17:37, Hartley Sweeten wrote:
On Friday, May 20, 2016 6:49 AM, Ian Abbott wrote:
Rename the macros for the PLX PCI 9080 LAS0RR and LAS1RR registers in
"plx9080.h", using the prefix `PLX_LASRR_`. Make use of the `BIT(x)`
and `GENMASK(h,l)` macros to define the values.
Define a macro `PLX_LASRR_PREFETCH` for the "prefetchable memory" bit in
this register, and define a macro `PLX_LASRR_MLOC_MASK` to mask the PCI
memory location control bits.
Signed-off-by: Ian Abbott
---
[snip]
diff --git a/drivers/staging/comedi/drivers/plx9080.h
b/drivers/staging/comedi/drivers/plx9080.h
index 92d2480..8788117 100644
--- a/drivers/staging/comedi/drivers/plx9080.h
+++ b/drivers/staging/comedi/drivers/plx9080.h
@@ -54,14 +54,16 @@ struct plx_dma_desc {
/* Local Address Space 1 Range Register */
#define PLX_REG_LAS1RR0x00f0
-#define LRNG_IO 0x0001 /* Map to: 1=I/O, 0=Mem */
-#define LRNG_ANY320x /* Locate anywhere in 32 bit */
-#define LRNG_LT1MB0x0002 /* Locate in 1st meg */
-#define LRNG_ANY640x0004 /* Locate anywhere in 64 bit */
-/* bits that specify range for memory io */
-#define LRNG_MEM_MASK 0xfff0
-/* bits that specify range for normal io */
-#define LRNG_IO_MASK 0xfffc
+#define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem */
+#define PLX_LASRR_ANY32(BIT(1) * 0)/* Locate anywhere in
32 bit */
+#define PLX_LASRR_LT1MB(BIT(1) * 1)/* Locate in 1st meg */
+#define PLX_LASRR_ANY64(BIT(1) * 2)/* Locate anywhere in
64 bit */
The (BIT(n) * x) looks ugly.
You won't like the remaining patches then!
FWIW, all the constants end up with the same type (unsigned long) this way.
I have been looking for a solution to the problem where random people
change something like this:
#define MY_COOLREG_VAL_FOO (0 << 5)
#define MY_COOLREG_VAL_BAR (1 << 5)
#define MY_COOLREG_VAL_BAZ (2 << 5)
to:
#define MY_COOLREG_VAL_FOO (0 << 5)
#define MY_COOLREG_VAL_BAR BIT(5)
#define MY_COOLREG_VAL_BAZ (2 << 5)
and this seemed like one way to do it.
These bit define the memory space encoding. I would prefer something
like this:
#define PLX_LASSR_MLOC(x) (((x) & 0x3) << 1)
#define PLX_LASSR_MLOC_ANY32PLX_LASSR_MLOC(0)
#define PLX_LASSR_MLOC_LT1MBPLX_LASSR_MLOC(1)
#define PLX_LASSR_MLOC_ANY64PLX_LASSR_MLOC(2)
+#define PLX_LASRR_MLOC_MASKGENMASK(2, 1) /* Memory location bits */
I guess the GENMASK() macro is common but it's currently
not used by any of the comedi code.
It is handy when matching it up with the data sheet though. I have a
field that occupies bits 2 and 1. It also doesn't expose a fairly
useless PLX_LASRR_MLOC() macro to the user of the header file.
Using the macro above, the 'mask' would be:
#define PLX_LASSR_MLOC_MASK PLX_LASSR_MLOC(3)
+#define PLX_LASRR_PREFETCH BIT(3) /* Memory is prefetchable */
+/* bits that specify range for memory space decode bits */
+#define PLX_LASRR_MEM_MASK GENMASK(31, 4)
+/* bits that specify range for i/o space decode bits */
+#define PLX_LASRR_IO_MASK GENMASK(31, 2)
I suppose the GENMASK() use makes sense for these.
Regards,
Hartley
--
-=( Ian Abbott @ MEV Ltd.E-mail: )=-
-=( Web: http://www.mev.co.uk/ )=-
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RE: [PATCH 04/20] staging: comedi: drivers: re-do macros for PLX PCI 9080 LASxRR values
On Friday, May 20, 2016 10:18 AM, Ian Abbott wrote: > On 20/05/16 17:37, Hartley Sweeten wrote: >> On Friday, May 20, 2016 6:49 AM, Ian Abbott wrote: >>> Rename the macros for the PLX PCI 9080 LAS0RR and LAS1RR registers in >>> "plx9080.h", using the prefix `PLX_LASRR_`. Make use of the `BIT(x)` >>> and `GENMASK(h,l)` macros to define the values. >>> >>> Define a macro `PLX_LASRR_PREFETCH` for the "prefetchable memory" bit in >>> this register, and define a macro `PLX_LASRR_MLOC_MASK` to mask the PCI >>> memory location control bits. [snip] >>> +#define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem >>> */ >>> +#define PLX_LASRR_ANY32(BIT(1) * 0)/* Locate anywhere in >>> 32 bit */ >>> +#define PLX_LASRR_LT1MB(BIT(1) * 1)/* Locate in 1st meg */ >>> +#define PLX_LASRR_ANY64(BIT(1) * 2)/* Locate anywhere in >>> 64 bit */ >> >> The (BIT(n) * x) looks ugly. > > You won't like the remaining patches then! You are correct... ;-) > FWIW, all the constants end up with the same type (unsigned long) this way. That's probably good but it sure makes the defines look ugly, and a bit hard to understand imoh. You also don't know what the 'max' value for the bit-field is without further digging. I applied your whole series to see what the final header looks like. To me it actually looks worse than the original. The original had a number of whitespace issues that made it hard to follow and the defines were lacking namespace. Personally I also don't can for all the enums since the symbols are not actually used as enums just as raw values. But the 'bit' usage of the registers was fairly clear. With your series applied the whtespace and namespace issues are addressed. You also converted all the enums to defines which is great. But the 'bit' usage now is a bit muddled. I really don't care for the (BIT(n) * (x)) stuff. There are also the various, unused and unnecessary, _SHIFT defines. Those just add additional cruft. I'm also not sure if all the bits require a comment. They seem to clutter the header. Datasheets for the PLX-9080 are easy to find. Maybe just have a comment for each register and remove all the bit comments. > I have been looking for a solution to the problem where random people > change something like this: > > #define MY_COOLREG_VAL_FOO(0 << 5) > #define MY_COOLREG_VAL_BAR(1 << 5) > #define MY_COOLREG_VAL_BAZ(2 << 5) > > to: > > #define MY_COOLREG_VAL_FOO(0 << 5) > #define MY_COOLREG_VAL_BARBIT(5) > #define MY_COOLREG_VAL_BAZ(2 << 5) > > and this seemed like one way to do it. Like I stated previously, I prefer something like this for the multi-bit fields of a register. >> #define PLX_LASSR_MLOC(x)(((x) & 0x3) << 1) >> #define PLX_LASSR_MLOC_ANY32 PLX_LASSR_MLOC(0) >> #define PLX_LASSR_MLOC_LT1MB PLX_LASSR_MLOC(1) >> #define PLX_LASSR_MLOC_ANY64 PLX_LASSR_MLOC(2) >> #define PLX_LASSR_MLOC_MASK PLX_LASSR_MLOC(3) > > It is handy when matching it up with the data sheet though. I have a > field that occupies bits 2 and 1. It also doesn't expose a fairly > useless PLX_LASRR_MLOC() macro to the user of the header file. The (BIT(n) * (x)) just looks odd. The GENMASK() for a multi-bit field also makes it more difficult to figure out what the maximum value for the field is when there are more than just a few bits and the lower bit is not 0. Anyway.. Technically it looks like your series doesn't break anything I just don't feel that it adds much clarity. I'm still looking it over... Maybe I'll change my mind... ;-) Regards, Hartley ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH 1/3] Staging: wlan-ng: fix Alignment should match open parenthesis. This patch fixes alignment of parenthesis found by checkpatch.pl tool.
Signed-off-by: Kevin McKinney
---
drivers/staging/wlan-ng/prism2usb.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/wlan-ng/prism2usb.c
b/drivers/staging/wlan-ng/prism2usb.c
index b26d09f..43123f3 100644
--- a/drivers/staging/wlan-ng/prism2usb.c
+++ b/drivers/staging/wlan-ng/prism2usb.c
@@ -47,11 +47,11 @@ static const struct usb_device_id usb_prism_tbl[] = {
PRISM_DEV(0x0bb2, 0x0302, "Ambit Microsystems Corp."),
PRISM_DEV(0x9016, 0x182d, "Sitecom WL-022 802.11b USB Adapter"),
PRISM_DEV(0x0543, 0x0f01,
- "ViewSonic Airsync USB Adapter 11Mbps (Prism2.5)"),
+ "ViewSonic Airsync USB Adapter 11Mbps (Prism2.5)"),
PRISM_DEV(0x067c, 0x1022,
- "Siemens SpeedStream 1022 11Mbps WLAN USB Adapter"),
+ "Siemens SpeedStream 1022 11Mbps WLAN USB Adapter"),
PRISM_DEV(0x049f, 0x0033,
- "Compaq/Intel W100 PRO/Wireless 11Mbps multiport WLAN Adapter"),
+ "Compaq/Intel W100 PRO/Wireless 11Mbps multiport WLAN
Adapter"),
{ } /* terminator */
};
MODULE_DEVICE_TABLE(usb, usb_prism_tbl);
@@ -216,7 +216,7 @@ exit:
#ifdef CONFIG_PM
static int prism2sta_suspend(struct usb_interface *interface,
- pm_message_t message)
+pm_message_t message)
{
hfa384x_t *hw = NULL;
wlandevice_t *wlandev;
--
2.1.4
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[PATCH 0/3] fix wlan-ng/prism2usb.c
This patchset will fix the below issues reported checkpatch.pl tool. Kevin McKinney (3): Staging: wlan-ng: fix Alignment should match open parenthesis. This patch fixes alignment of parenthesis found by checkpatch.pl tool. Staging: wlan-ng: fix unnecessary parentheses around interface-dev. This is a path to fix unnecessary parentheses around interface-dev found by checkpatch.pl tool. Staging: wlan-ng: fix comparison to NULL. This patch fixes comparison to NULL found by checkpatch.pl tool. drivers/staging/wlan-ng/prism2usb.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.1.4 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH 2/3] Staging: wlan-ng: fix unnecessary parentheses around interface-dev. This is a path to fix unnecessary parentheses around interface-dev found by checkpatch.pl tool.
Signed-off-by: Kevin McKinney
---
drivers/staging/wlan-ng/prism2usb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/wlan-ng/prism2usb.c
b/drivers/staging/wlan-ng/prism2usb.c
index 43123f3..82be343 100644
--- a/drivers/staging/wlan-ng/prism2usb.c
+++ b/drivers/staging/wlan-ng/prism2usb.c
@@ -74,7 +74,7 @@ static int prism2sta_probe_usb(struct usb_interface
*interface,
}
hw = wlandev->priv;
- if (wlan_setup(wlandev, &(interface->dev)) != 0) {
+ if (wlan_setup(wlandev, &interface->dev) != 0) {
dev_err(&interface->dev, "wlan_setup() failed.\n");
result = -EIO;
goto failed;
@@ -87,7 +87,7 @@ static int prism2sta_probe_usb(struct usb_interface
*interface,
/* Register the wlandev, this gets us a name and registers the
* linux netdevice.
*/
- SET_NETDEV_DEV(wlandev->netdev, &(interface->dev));
+ SET_NETDEV_DEV(wlandev->netdev, &interface->dev);
/* Do a chip-level reset on the MAC */
if (prism2_doreset) {
--
2.1.4
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[PATCH 3/3] Staging: wlan-ng: fix comparison to NULL. This patch fixes comparison to NULL found by checkpatch.pl tool.
Signed-off-by: Kevin McKinney
---
drivers/staging/wlan-ng/prism2usb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/wlan-ng/prism2usb.c
b/drivers/staging/wlan-ng/prism2usb.c
index 82be343..0463ec1 100644
--- a/drivers/staging/wlan-ng/prism2usb.c
+++ b/drivers/staging/wlan-ng/prism2usb.c
@@ -137,7 +137,7 @@ static void prism2sta_disconnect_usb(struct usb_interface
*interface)
wlandevice_t *wlandev;
wlandev = (wlandevice_t *)usb_get_intfdata(interface);
- if (wlandev != NULL) {
+ if (wlandev) {
LIST_HEAD(cleanlist);
hfa384x_usbctlx_t *ctlx, *temp;
unsigned long flags;
--
2.1.4
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[PATCH] Staging: unisys: visorhba: visorhba_main: fixed a coding style issue
fixed checkpatch.pl warning about 'Prefer 'unsigned int' to bare use of 'unsigned' Signed-off-by: Rumesh Hapuarahcchi --- drivers/staging/unisys/visorhba/visorhba_main.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/staging/unisys/visorhba/visorhba_main.c b/drivers/staging/unisys/visorhba/visorhba_main.c index 6a4570d..3b69b33 100644 --- a/drivers/staging/unisys/visorhba/visorhba_main.c +++ b/drivers/staging/unisys/visorhba/visorhba_main.c @@ -1122,9 +1122,9 @@ static int visorhba_probe(struct visor_device *dev) if (err < 0) goto err_scsi_host_put; - scsihost->max_id = (unsigned)max.max_id; - scsihost->max_lun = (unsigned)max.max_lun; - scsihost->cmd_per_lun = (unsigned)max.cmd_per_lun; + scsihost->max_id = (unsigned int)max.max_id; + scsihost->max_lun = (unsigned int)max.max_lun; + scsihost->cmd_per_lun = (unsigned int)max.cmd_per_lun; scsihost->max_sectors = (unsigned short)(max.max_io_size >> 9); scsihost->sg_tablesize = -- 1.9.1 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[GIT PULL] Staging driver update for 4.7-rc1
The following changes since commit 44549e8f5eea4e0a41b487b63e616cb089922b99:
Linux 4.6-rc7 (2016-05-08 14:38:32 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git/
tags/staging-4.7-rc1
for you to fetch changes up to ffc83a79b44e02995ab5e93af07e26f6c7243c53:
Staging: emxx_udc: emxx_udc: fixed coding style issue (2016-05-09 14:25:52
+0200)
Staging and IIO driver update for 4.7-rc1
Here's the big staging and iio driver update for 4.7-rc1.
I think we almost broke even with this release, only adding a few more
lines than we removed, which isn't bad overall given that there's a
bunch of new iio drivers added. The Lustre developers seem to have
woken up from their sleep and have been doing a great job in cleaning up
the code and pruning unused or old cruft, the filesystem is almost
readable :)
Other than that, just a lot of basic coding style cleanups in the churn.
All have been in linux-next for a while with no reported issues.
Signed-off-by: Greg Kroah-Hartman
Adriana Reus (2):
iio: accel: kxcjk-1013: use available_scan_masks
iio: accel: kxcjk-1013: optimize i2c transfers in trigger handler
Akinobu Mita (2):
iio: pressure: bmp280: add support for BMP180
iio: pressure: bmp280: add ability to control oversampling rate
Aleksei Fedotov (1):
staging: lustre: libcfs: Fix libcfs_ioctl() prototype.
Alexander Boyko (2):
staging: lustre: brw: added OBDO short io flag
staging: lustre: osc: Allow lock to be canceled at ENQ time
Alexander Curtin (14):
staging: unisys: visorbus: replaced vague variable name in typeguid_show
staging: unisys: visorbus: replaced vague variable name in zoneguid_show
staging: unisys: visorbus: replaced vague 'p' variable with 'pos'
staging: unisys: visorbus: replaced use of vague 'x' variable
staging: unisys: include: changed 'v' variable to 'state'
staging: unisys: removed unused switch/port info from visorbus.h
staging: unisys: include: removed unused 'visor_device.description'
staging: unisys: removed unused visor_device.type field
staging: unisys: removed 'visor_device.devnodes' field
staging: unisys: removed unused channel_bytes attribute
staging: unisys: removed unused 'visor_device.respond_to_device_create'
staging: unisys: include: Added kernel-doc for struct visor_driver
staging: unisys: include: Added kerneldoc comments to visor_device
staging: unisys: visorhba: replace functionlike macro with function
Alison Schofield (18):
iio: core: implement iio_device_{claim|release}_direct_mode()
staging: iio: ad7192: use iio_device_{claim|release}_direct_mode()
staging: iio: isl29028: use regmap to retrieve struct device
staging: iio: convert bare unsigned usage to unsigned int
staging: iio: meter: remove fixme comment on device remove
staging: iio: ad5933: use dev_get_platdata()
staging: iio: io-trig-bfin-timer: use dev_get_platdata()
staging: iio: ad5933: move contents of header file to source file
staging: iio: ad5933: remove unused #includes
staging: wilc1000: replace semaphore sem_inactive_time with a completion
staging: wilc1000: replace semaphore sem_get_rssi with a completion
staging: wilc1000: replace sem_test_disconn_block with a completion
staging: wilc1000: replace sem_test_key_block with a completion
staging: iio: use kernel preferred block commenting style
iio: accel: mma7455: use regmap to retrieve struct device
staging: iio: ad7606: use iio_device_{claim|release}_direct_mode()
iio: accel: bmc150: use regmap to retrieve struct device
iio: gyro: bmg160: use regmap to retrieve struct device
Amir Shehata (12):
staging: lustre: obd: remove newline from LCONSOLE string
staging: lustre: obd: add newline for dumped config record
staging: lustre: lnet: use struct lnet_ioctl_config_data for NI bring up
staging: lustre: lnet: use struct lnet_ioctl_config_data for NI query
staging: lustre: lnet: add per NI configuration structures
staging: lustre: o2iblnd: convert macros to inline functions
staging: lustre: o2iblnd: create default o2iblnd tunable settings
staging: lustre: o2iblnd: use data in lnet_ni_t instead of kiblnd_tunables
staging: lustre: o2iblnd: per NI map-on-demand value
staging: lustre: o2iblnd: remove last of kiblnd_tunables_fini
staging: lustre: o2iblnd: properly set ibr_why
staging: lustre: lnet: enable configuration per NI interface
Amitoj Kaur Chawla (7):
iio: light: tsl2563: Remove flush_scheduled_work
staging: lustre: lnet: Replace sg++ with sg = sg_next(sg)
staging: slicoss: Add error check for pci_map_single
staging: media: omap1: Rep
