[bug report] drm/ingenic: Add support for the IPU
Hello Paul Cercueil,
The patch fc1acf317b01: "drm/ingenic: Add support for the IPU" from
Jul 16, 2020, leads to the following static checker warning:
drivers/gpu/drm/ingenic/ingenic-drm-drv.c:232
ingenic_drm_crtc_atomic_check()
error: potentially dereferencing uninitialized 'ipu_state'.
drivers/gpu/drm/ingenic/ingenic-drm-drv.c
197 static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc,
198 struct drm_crtc_state *state)
199 {
200 struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
201 struct drm_plane_state *f1_state, *f0_state, *ipu_state;
202 long rate;
203
204 if (!drm_atomic_crtc_needs_modeset(state))
205 return 0;
206
207 if (state->mode.hdisplay > priv->soc_info->max_width ||
208 state->mode.vdisplay > priv->soc_info->max_height)
209 return -EINVAL;
210
211 rate = clk_round_rate(priv->pix_clk,
212state->adjusted_mode.clock * 1000);
213 if (rate < 0)
214 return rate;
215
216 if (priv->soc_info->has_osd) {
217 f1_state = drm_atomic_get_plane_state(state->state,
&priv->f1);
218 f0_state = drm_atomic_get_plane_state(state->state,
&priv->f0);
219
220 if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) &&
priv->ipu_plane) {
Do we need to check both the CONFIG and the priv->ipu_plane or would it
be sufficient to just check if (priv->ipu_plane) {?
221 ipu_state =
drm_atomic_get_plane_state(state->state, priv->ipu_plane);
222
223 /* IPU and F1 planes cannot be enabled at the
same time. */
224 if (f1_state->fb && ipu_state->fb) {
225 dev_dbg(priv->dev, "Cannot enable both
F1 and IPU\n");
226 return -EINVAL;
227 }
228 }
229
230 /* If all the planes are disabled, we won't get a
VBLANK IRQ */
231 priv->no_vblank = !f1_state->fb && !f0_state->fb &&
232!(priv->ipu_plane && ipu_state->fb);
^^^
Because here we're only checking "priv->ipu_plane".
233 }
234
235 return 0;
236 }
regards,
dan carpenter
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[bug report] drm: xlnx: DRM/KMS driver for Xilinx ZynqMP DisplayPort Subsystem
Hello Hyun Kwon,
The patch d76271d22694: "drm: xlnx: DRM/KMS driver for Xilinx ZynqMP
DisplayPort Subsystem" from Jul 7, 2018, leads to the following
static checker warning:
drivers/gpu/drm/xlnx/zynqmp_dp.c:594 zynqmp_dp_mode_configure()
error: iterator underflow 'bws' (-1)-2
drivers/gpu/drm/xlnx/zynqmp_dp.c
566 static int zynqmp_dp_mode_configure(struct zynqmp_dp *dp, int pclock,
567 u8 current_bw)
568 {
569 int max_rate = dp->link_config.max_rate;
570 u8 bws[3] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
571 u8 max_lanes = dp->link_config.max_lanes;
572 u8 max_link_rate_code = drm_dp_link_rate_to_bw_code(max_rate);
573 u8 bpp = dp->config.bpp;
574 u8 lane_cnt;
575 s8 i;
576
577 if (current_bw == DP_LINK_BW_1_62) {
578 dev_err(dp->dev, "can't downshift. already lowest link
rate\n");
579 return -EINVAL;
580 }
581
582 for (i = ARRAY_SIZE(bws) - 1; i >= 0; i--) {
^^
This exits with i == -1.
583 if (current_bw && bws[i] >= current_bw)
584 continue;
585
586 if (bws[i] <= max_link_rate_code)
587 break;
588 }
589
590 for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) {
591 int bw;
592 u32 rate;
593
594 bw = drm_dp_bw_code_to_link_rate(bws[i]);
^^
Potential negative array offset.
595 rate = zynqmp_dp_max_rate(bw, lane_cnt, bpp);
596 if (pclock <= rate) {
597 dp->mode.bw_code = bws[i];
598 dp->mode.lane_cnt = lane_cnt;
599 dp->mode.pclock = pclock;
600 return dp->mode.bw_code;
601 }
602 }
603
604 dev_err(dp->dev, "failed to configure link values\n");
605
606 return -EINVAL;
607 }
regards,
dan carpenter
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