Re: [PATCH] drm/sun4i: Workaround TCON TOP conflict between DE0 and DE1
On 11/8/24 6:59 PM, John Watts wrote: > On Fri, Nov 08, 2024 at 11:53:57AM +, Andre Przywara wrote: >> Hi John, > > Hi Andre! > >> Can you say *why* this patch is needed? Is there something broken that >> needs fixing? Where does this show and why wasn't this a problem before? > > Oops, that's a good point. There is currently a bug where the LCD output will > be tinted. I have full context here which I should have probably linked in the > patch description: > > https://lore.kernel.org/linux-sunxi/Zn8GVkpwXwhaUFno@titan/T/#u > >> To be honest, given the isolation on this patch, I'd rather wait for this >> full fledged solution, especially if there is no pressing need (see above). > > I'd be interested to hear if that's still the wanted solution given the link > above. This currently blocks many people from having working LCD output. > > Doing it the proper way might be overkill for now unless someone deliberately > tries to run two DEs to the same output. I haven't seen this use case. > > Allwinner kernel fork initially sets them up to values like these then makes > sure both DEs can't be set to the same TCON. > >>> - writel(0, regs + TCON_TOP_PORT_SEL_REG); >>> + writel(0x20, regs + TCON_TOP_PORT_SEL_REG); >> >> Sorry, but that looks weird: >> First, please explain the 0x20. Is it bit 5? If yes, what does that bit >> mean? The commit message suggests you know that? >> >> And second: the comment above clearly states that those two writes just >> *clear* some registers, to have some sane base line. So please adjust this >> comment, and copy in some of the rationale from the commit message. >> Explaining things in the commit message is good (so thanks for that!), but >> having at least some terse technical explanations near the code, in a >> comment, is better. > > Bit 5 is value 3 of TCON_TOP_PORT_DE1_MSK. The R40 datasheet explains the > values of both masks as follows: > > 00: TCON_LCD0 > 01: TCON_LCD1 > 10: TCON_TV0 > 11: TCON_TV1 > > So this sets DE1's input to DE0. To add, 0x20 will be DE0 <--> LCD0 and DE1 <--> TV0. Below note (copied from R40) states the priority of the DE selection, which fails to work? Not sure, may be disabling CORE1_SCLK_GATE and CORE1_HCLK_GATE in de2-clk helps. With A133 following the same as T113 with single mixer without TV, still sets 0x20 in vendor kernel. copied from R40: Note: The priority of DE0 is higher than DE1. If TCON_LCD0 selects DE0 and DE1 as source at the same time, then DE0 will be used for the source of TCON_LCD0. Thanks, Parthiban > >> >> Cheers, >> Andre > > Thanks, > John Watts >
Re: [PATCH] drm/sun4i: Workaround TCON TOP conflict between DE0 and DE1
On 11/12/24 5:27 PM, John Watts wrote: > Hey everyone, > > I'm not sure exactly where to add this but I discussed some of this with > Parthiban on #linux-sunxi a few days ago, so I want to write it down > before I work on the next version of the patch. > > I had assumed for some reason in my mind that DE0 and DE1 here referred > to mixers, but they actually refer to chips that have multiple DEs. It > looks like at least with the A133 it has two DEs instead of two mixers. > > This can be found by looking at the Allwinner BSP: SUN50IW10 requires > CONFIG_INDEPENDENT_DE and has a device tree with an extra reg and clock: > > <0x0 0x0680 0x0 0x3f>,/*de1*/ > <&clk_dpss_top1> Independent DE is unique to A133/A100 AFAIK. > > However the tcon-top code seems to conflate mixers and DE in the > mainline code and the Allwinner code. So ... It seems like 'DE0' and > 'DE1' really do mean mixers in this case. It's probably best to note #define TCON_TOP_PORT_DE0_MSK GENMASK(1, 0) #define TCON_TOP_PORT_DE1_MSK GENMASK(5, 4) references towards DE0 and DE1 is for DE itself, not the mixers in the current implementation. Handling for mixer0 <-> lcd1 and mixer1 <-> lcd0 also needs to set DE2TCON_MUX in de clock, which is missing now. > that down. > > I thought a bit more about how to solve this properly- setting two > mixers to the same output is something people probably won't do in > practice, so the only way you could really arrive at this bugged state > is by setting it as the default state. This patch may be the correct > solution after all. sun8i_tcon_top_set_hdmi_src for R40 already sets these values via quirks. i.e controlling the port muxing. Also D1 quirks is same as R40. So the original changes to make the DE1 point to TVx can also done in this quirk without hardcoded value? Thanks, Parthiban > > John Watts > > On Sat, Nov 09, 2024 at 01:15:16AM +1100, John Watts wrote: >> On Fri, Nov 08, 2024 at 07:36:16PM +0530, Parthiban wrote: >>> To add, 0x20 will be DE0 <--> LCD0 and DE1 <--> TV0. Below note (copied from >>> R40) states the priority of the DE selection, which fails to work? Not sure, >>> may be disabling CORE1_SCLK_GATE and CORE1_HCLK_GATE in de2-clk helps. >>> >>> With A133 following the same as T113 with single mixer without TV, still >>> sets 0x20 in vendor kernel. >>> >>> copied from R40: >>> Note: The priority of DE0 is higher than DE1. >>> If TCON_LCD0 selects DE0 and DE1 as source at the same time, then >>> DE0 will be used for the source of TCON_LCD0. >> >> Hi there, >> >> Yes that was a pretty bad typo, I meant to say DE1 to TV0 >> The prioritization seems broken in the T113 at least, it's racy from >> what I see in testing. I should note this in the patch too. >> >> I looked at the datasheets and kernel code briefly: I can't seem to >> figure out what SCLK/HCLK gating does and I don't think the kernel >> touches these registers which are gated by default. >> >>> Thanks, >>> Parthiban >> >> John Watts
Re: [PATCH] drm/sun4i: Workaround TCON TOP conflict between DE0 and DE1
On 11/13/24 5:03 AM, John Watts wrote: > Hi there, > > On Tue, Nov 12, 2024 at 10:43:44PM +0530, Parthiban wrote: >> #define TCON_TOP_PORT_DE0_MSK GENMASK(1, 0) >> #define TCON_TOP_PORT_DE1_MSK GENMASK(5, 4) >> >> references towards DE0 and DE1 is for DE itself, not the mixers in the >> current implementation. > > So the datasheet says it's for DE0/DE1 but the Allwinner driver and mainline > driver assume it's for mixers. There's a conflation between mixer and DE in No, Mixers in upstream refers to RT-Mixers inside the DE. It's only the quirk for R40/D1 setting the DE ports using mixer numbering. > this case, especially because everywhere mixer1 is used on the A133 it is > switched to DE1. I'm also unaware of the R40 having two DEs which kind of > confirms this might be a typo. If anyone has actually tested the second output > of this it would help find out if it actually means DE1 or mixer1. Gave a quick try, but display went blue. My current assumption is that it's called INDEPENDENT DE, so DE1 <-> LCD1 is the only possibility. Yet to try that pipeline. > >> Handling for mixer0 <-> lcd1 and mixer1 <-> lcd0 also needs to set >> DE2TCON_MUX in de clock, which is missing now. > > Hmm. Are you sure? Looking at the Allwinner drivers it has the method > de_top_set_de2tcon_mux in > drivers/video/fbdev/sunxi/disp2/disp/de/lowlevel_v33x/de330/de_top.c > which I think means it's for DE3? But I don't see it called anywhere? Missing in the upstream. > > This might be worth discussing in the DE3 patchset. > >> sun8i_tcon_top_set_hdmi_src for R40 already sets these values via quirks. >> i.e controlling the port muxing. Also D1 quirks is same as R40. So the >> original changes to make the DE1 point to TVx can also done in this quirk >> without hardcoded value? > > In this case I'm using an LCD which isn't HDMI, so I'm not too sure how much > this would help. Having it as a quirk also seems a bit overkill if this is a > general preventative fix, especially since Allwinner doesn't seem to test > their > functionality. Relying on it seems like a mistake in this case. > > My other thought is that when sun8i_tcon_top_de_config is called it could do > something. But I'm not sure what that something would actually be, given it > may > be called twice in an (I assume) unknown order. > > Say, if mixer1 is set as TV0 and and mixer0 is set as TV1 we would try to set > mixer1 > first, see that mixer0 is already set to TV0 then ... error? Even though the > final configuration doesn't have any conflicts. > > I was thinking something like this for my next patch: > > /* >* Make sure that by default DE0 and DE1 are set to different outputs, >* otherwise we get a strange tinting or unusable display on the T113. > */ > reg = readl(regs + TCON_TOP_PORT_SEL_REG); > reg &= ~TCON_TOP_PORT_DE0_MSK; > reg |= FIELD_PREP(TCON_TOP_PORT_DE0_MSK, 0); > reg &= ~TCON_TOP_PORT_DE1_MSK; > reg |= FIELD_PREP(TCON_TOP_PORT_DE1_MSK, 1); > writel(reg, regs + TCON_TOP_PORT_SEL_REG); > > Perhaps this could be hidden behind a quirk? I would have to check to see > which > chips have this behaviour, I'm not sure if it's a bug specific to the T113 or > D1/T113 or R40 too. > > Also noting at the top of the file that DE0 and DE1 mean mixer0 and mixer1 > might be good to reduce confusion. > > What do you think? :) So far there is no real user for DE1 in upstream. DE_PORT_SELECT_REG value for DE1 can be negate of DE0, so that they won't conflict or cause timing issues. Also DE_PORT_SELECT_REG mentions only about TV and LCD muxing, but missing HDMI, DSI and so. Otherwise, if I get DE1 working in A133, I will try to add quirk to set DE0 and DE1 port mapping in that case to respective connector. Thanks, Parthiban > >> Thanks, >> Parthiban > > Thanks for your input! > > John Watts
Re: [PATCH] drm/sun4i: Workaround TCON TOP conflict between DE0 and DE1
On 11/13/24 1:45 PM, John Watts wrote: > It really seems like the code means mixers here. True, I was wrong about my statement. But with A133, the case of independent DE is unique, which I couldn't test yet. > If my thoughts are correct, this would break use of mixer0 and mixer1 at the > same time. Agreed. But back to the original discussion about setting 0x20 to the port register, it work fine in my end without that changes for A133 display pipeline with LVDS. Not sure if the reason is independent DE. Thanks, Parthiban
Re: [PATCH 1/2] dt-bindings: gpu: add reset control property
On 11/25/24 11:37 PM, Conor Dooley wrote: > On Mon, Nov 25, 2024 at 10:07:03PM +0530, Parthiban Nallathambi wrote: >> GE8300 in Allwinner A133 have reset control from the ccu. >> Add the resets property as optional one to control it. > > There's no specific compatible here for an a133, but the binding > requires one. Where is your dts patch? A133 GPU is still work in progress in both Kernel and Mesa3D. Also power domain support needs an additional driver. But reset control is independent of those changes. Should reset control needs to be clubbed GPU dts changes? Thanks, Parthiban > >> >> Signed-off-by: Parthiban Nallathambi >> --- >> Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml >> b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml >> index 256e252f8087..bb607d4b1e07 100644 >> --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml >> +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml >> @@ -37,6 +37,9 @@ properties: >>power-domains: >> maxItems: 1 >> >> + resets: >> +maxItems: 1 >> + >> required: >>- compatible >>- reg >> >> -- >> 2.39.2 >>
Re: [PATCH v2 02/21] dt-bindings: gpu: img: Further constrain clocks
On 11/18/24 6:31 PM, Matt Coster wrote: > All Imagination GPUs use three clocks: core, mem and sys. All reasonably > modern Imagination GPUs also support a single-clock mode where the SoC > only hooks up core and the other two are derived internally. On GPUs which > support this mode, it is the default and most commonly used integration. > > Codify this "1 or 3" constraint in our bindings and hang the specifics off > the vendor compatible string to mirror the integration-time choice. > > Signed-off-by: Matt Coster > --- > Changes in v2: > - Simplified clocks constraints (P2) > - Link to v1: > https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-2-4ed30e865...@imgtec.com > --- > .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 20 > +++- > 1 file changed, 11 insertions(+), 9 deletions(-) > > diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > index > ef7070daf213277d0190fe319e202fdc597337d4..3b5a5b966585ac29ad104c7aef19881eca73ce80 > 100644 > --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml > @@ -29,16 +29,16 @@ properties: >reg: > maxItems: 1 > > - clocks: > -minItems: 1 > -maxItems: 3 > + clocks: true > >clock-names: > -items: > - - const: core > - - const: mem > - - const: sys > -minItems: 1 > +oneOf: > + - items: > + - const: core > + - items: > + - const: core > + - const: mem > + - const: sys Clock for GE8300 in Allwinner A133 is organized with core, bus and additional pll as input. Where "bus" controlled as gate clock and optionally using pll. If am not wrong, GE8300 also comes under rogue architecture without mem and sys clocks. Does this needs to be considered into separate bindings? Thanks, Parthiban > >interrupts: > maxItems: 1 > @@ -56,11 +56,13 @@ required: > additionalProperties: false > > allOf: > + # Vendor integrations using a single clock domain >- if: >properties: > compatible: >contains: > -const: ti,am62-gpu > +anyOf: > + - const: ti,am62-gpu > then: >properties: > clocks: >
Re: [PATCH 1/2] dt-bindings: gpu: add reset control property
On 11/26/24 3:02 PM, Krzysztof Kozlowski wrote: > On 26/11/2024 04:46, Parthiban wrote: >> On 11/25/24 11:37 PM, Conor Dooley wrote: >>> On Mon, Nov 25, 2024 at 10:07:03PM +0530, Parthiban Nallathambi wrote: >>>> GE8300 in Allwinner A133 have reset control from the ccu. >>>> Add the resets property as optional one to control it. >>> >>> There's no specific compatible here for an a133, but the binding >>> requires one. Where is your dts patch? >> A133 GPU is still work in progress in both Kernel and Mesa3D. Also power >> domain support needs an additional driver. >> >> But reset control is independent of those changes. Should reset control >> needs to be clubbed GPU dts changes? > How is it independent? Are you adding it for the new platforms? If yes, > then it is part of new platforms. Don't add properties which are not used. Thanks for the review. Will address the points together when adding support for GE8300 GPU. Thanks, Parthiban > > Best regards, > Krzysztof
Re: [PATCH 2/2] drm/imagination: add reset control support
On 11/26/24 2:59 PM, Philipp Zabel wrote: > On Mo, 2024-11-25 at 22:07 +0530, Parthiban Nallathambi wrote: >> On some platforms like Allwinner A133 with GE8300 includes >> reset control from reset control unit. Add reset control >> optionally from the devicetree. >> >> Signed-off-by: Parthiban Nallathambi >> --- >> drivers/gpu/drm/imagination/pvr_device.h | 8 >> drivers/gpu/drm/imagination/pvr_drv.c| 5 + >> drivers/gpu/drm/imagination/pvr_power.c | 16 +++- >> 3 files changed, 28 insertions(+), 1 deletion(-) Thanks for the reviews. As with the binding patch comments, reset control needs to be added together with the consumer i.e in this case GE8300 GPU in Allwinner A133 SoC. I will address the comments when sending patch with support for GE8300. Thanks, Parthiban
Re: [PATCH RESEND 00/22] Add support for A100/A133 display
On 12/30/24 7:41 PM, Andre Przywara wrote: > On Fri, 27 Dec 2024 20:06:30 +0530 > Parthiban wrote: > >> On 12/27/24 6:30 PM, Parthiban Nallathambi wrote: >>> This series depends on [1] for the eMMC/MMC controller to work and >>> [2] (lined up for 6.14) which adds support for the sram nodes and >>> display engine extends it's usage. Idea of this series to get initial >>> feedback and adjust, which will be rebased for 6.14 once [2] is merged. >>> >>> This patch series adds support for A133 display pipeline based on >>> LVDS. dt-bindigs are organized in the start and later with code >>> changes. >>> >>> PHY is shared between DSI and LVDS, so to control the PHY specific >>> to DSI/LVDS, phy_ops set_mode is introduced. To enable the DSI >>> using set_mode, analog control register MIPI Enable is used, which >>> may not be available for A31 (shares the same driver). >>> >>> Otherwise, A133 also got hidden independent display engine i.e >>> mixer + tcon top to handle parallel display. But this patch series >>> adds only support for the 1 mixer which is documented. >>> >>> [1]: >>> https://lore.kernel.org/linux-sunxi/20241109003739.3440904-1-masterr3c0rd@epochal.quest/ >>> [2]: >>> https://lore.kernel.org/linux-sunxi/20241218-a100-syscon-v2-0-dae60b9ce192@epochal.quest/ >>> >>> Signed-off-by: Parthiban Nallathambi >> Apologize for polluting with resend again. My internal mail server got >> blocked due to >> volume count, which resulted in incomplete series again. > > I guess an incomplete send was the reason for the original resend? Please > note this at the top of the cover letter then, otherwise it's not easy > to see why you send something again. Something like: > > *** Re-sent due to mail server not sending out the complete series. *** Yes I did add that using b4 as below, but "b4 send --resend" didn't pick the updated cover letter though. I will check with "--reflect" next time. EDIT: Due to internal mail server issue, [3] missed few patches in series. So am resending to hope that it will get through this time. Sorry to pollute. [3]: https://lore.kernel.org/linux-sunxi/20241227-a133-display-support-v1-0-13b52f71f...@linumiz.com > > It also helps to split up the recipients, so that everyone gets the cover > letter, but only the respective subsystem maintainers get the patches > touching their subsystem. I would CC: the DT maintainers on every patch, > though. > It's a bit more complicated to set up, but keeps the noise down for those > large-ish series, for instance for the IOMMU people, who presumably have > little interest in DT or graphics code. The whole series based on b4 and the list is auto prepared using "b4 prep --auto-to-cc". Sure, I will add the dt list in all the patches. Also many thanks for your review and feedback. Thanks, Parthiban > > Cheers, > Andre > >> I will fix the mail server issue before resending the series. Sorry. >> >> Thanks, >> Parthiban >> >> > >
Re: [PATCH RESEND 00/22] Add support for A100/A133 display
On 12/27/24 6:30 PM, Parthiban Nallathambi wrote: > This series depends on [1] for the eMMC/MMC controller to work and > [2] (lined up for 6.14) which adds support for the sram nodes and > display engine extends it's usage. Idea of this series to get initial > feedback and adjust, which will be rebased for 6.14 once [2] is merged. > > This patch series adds support for A133 display pipeline based on > LVDS. dt-bindigs are organized in the start and later with code > changes. > > PHY is shared between DSI and LVDS, so to control the PHY specific > to DSI/LVDS, phy_ops set_mode is introduced. To enable the DSI > using set_mode, analog control register MIPI Enable is used, which > may not be available for A31 (shares the same driver). > > Otherwise, A133 also got hidden independent display engine i.e > mixer + tcon top to handle parallel display. But this patch series > adds only support for the 1 mixer which is documented. > > [1]: > https://lore.kernel.org/linux-sunxi/20241109003739.3440904-1-masterr3c0rd@epochal.quest/ > [2]: > https://lore.kernel.org/linux-sunxi/20241218-a100-syscon-v2-0-dae60b9ce192@epochal.quest/ > > Signed-off-by: Parthiban Nallathambi Apologize for polluting with resend again. My internal mail server got blocked due to volume count, which resulted in incomplete series again. I will fix the mail server issue before resending the series. Sorry. Thanks, Parthiban
[PATCH 1/2] dt-bindings: gpu: add reset control property
GE8300 in Allwinner A133 have reset control from the ccu. Add the resets property as optional one to control it. Signed-off-by: Parthiban Nallathambi --- Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 256e252f8087..bb607d4b1e07 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -37,6 +37,9 @@ properties: power-domains: maxItems: 1 + resets: +maxItems: 1 + required: - compatible - reg -- 2.39.2
[PATCH 2/2] drm/imagination: add reset control support
On some platforms like Allwinner A133 with GE8300 includes
reset control from reset control unit. Add reset control
optionally from the devicetree.
Signed-off-by: Parthiban Nallathambi
---
drivers/gpu/drm/imagination/pvr_device.h | 8
drivers/gpu/drm/imagination/pvr_drv.c| 5 +
drivers/gpu/drm/imagination/pvr_power.c | 16 +++-
3 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/imagination/pvr_device.h
b/drivers/gpu/drm/imagination/pvr_device.h
index 6d0dfacb677b..21ec7dd64415 100644
--- a/drivers/gpu/drm/imagination/pvr_device.h
+++ b/drivers/gpu/drm/imagination/pvr_device.h
@@ -23,6 +23,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -131,6 +132,13 @@ struct pvr_device {
*/
struct clk *mem_clk;
+ /**
+* @reset: Optional reset control
+*
+* This may be used on some platforms to reset the GPU module/IP.
+*/
+ struct reset_control *reset;
+
/** @irq: IRQ number. */
int irq;
diff --git a/drivers/gpu/drm/imagination/pvr_drv.c
b/drivers/gpu/drm/imagination/pvr_drv.c
index fb17196e05f4..d9b918410ea9 100644
--- a/drivers/gpu/drm/imagination/pvr_drv.c
+++ b/drivers/gpu/drm/imagination/pvr_drv.c
@@ -36,6 +36,7 @@
#include
#include
#include
+#include
#include
/**
@@ -1427,6 +1428,10 @@ pvr_probe(struct platform_device *plat_dev)
pm_runtime_use_autosuspend(&plat_dev->dev);
pvr_watchdog_init(pvr_dev);
+ pvr_dev->reset =
devm_reset_control_get_optional_exclusive(&plat_dev->dev, "ahb");
+ if (PTR_ERR(pvr_dev->reset) == -EPROBE_DEFER)
+ return PTR_ERR(pvr_dev->reset);
+
err = pvr_device_init(pvr_dev);
if (err)
goto err_watchdog_fini;
diff --git a/drivers/gpu/drm/imagination/pvr_power.c
b/drivers/gpu/drm/imagination/pvr_power.c
index ba7816fd28ec..a24ed85f36c7 100644
--- a/drivers/gpu/drm/imagination/pvr_power.c
+++ b/drivers/gpu/drm/imagination/pvr_power.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -252,6 +253,9 @@ pvr_power_device_suspend(struct device *dev)
clk_disable_unprepare(pvr_dev->sys_clk);
clk_disable_unprepare(pvr_dev->core_clk);
+ if (!IS_ERR(pvr_dev->reset))
+ reset_control_assert(pvr_dev->reset);
+
err_drm_dev_exit:
drm_dev_exit(idx);
@@ -270,9 +274,15 @@ pvr_power_device_resume(struct device *dev)
if (!drm_dev_enter(drm_dev, &idx))
return -EIO;
+ if (!IS_ERR(pvr_dev->reset)) {
+ err = reset_control_reset(pvr_dev->reset);
+ if (err)
+ goto err_drm_dev_exit;
+ }
+
err = clk_prepare_enable(pvr_dev->core_clk);
if (err)
- goto err_drm_dev_exit;
+ goto err_reset_exit;
err = clk_prepare_enable(pvr_dev->sys_clk);
if (err)
@@ -301,6 +311,10 @@ pvr_power_device_resume(struct device *dev)
err_core_clk_disable:
clk_disable_unprepare(pvr_dev->core_clk);
+err_reset_exit:
+ if (!IS_ERR(pvr_dev->reset))
+ reset_control_assert(pvr_dev->reset);
+
err_drm_dev_exit:
drm_dev_exit(idx);
--
2.39.2
[PATCH 0/2] drm/imagination: add reset handling
reset control is included in platforms from Allwinner, specifically A133, A733. Add reset control from devicetree and these changes are tested with A133 based helper board, which will be upstremed after Allwinner power domain controller. Firmware is used from [1]. [1]: https://gitlab.freedesktop.org/imagination/linux-firmware/-/issues/5 Signed-off-by: Parthiban Nallathambi --- Parthiban Nallathambi (2): dt-bindings: gpu: add reset control property drm/imagination: add reset control support .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 3 +++ drivers/gpu/drm/imagination/pvr_device.h | 8 drivers/gpu/drm/imagination/pvr_drv.c| 5 + drivers/gpu/drm/imagination/pvr_power.c | 16 +++- 4 files changed, 31 insertions(+), 1 deletion(-) --- base-commit: adc218676eef25575469234709c2d87185ca223a change-id: 20241125-pvr-reset-0a27fbae5ebc Best regards, -- Parthiban Nallathambi
[PATCH RESEND 03/22] dt-bindings: clock: sun8i de2 clock: Add PLL com clock
Some platforms like A100/A133 also uses pll-com clock as additional clock source for the display clock. This is not documents both in user manual and DE 2.0 specification. These changes are mainly from vendor BSP. Signed-off-by: Parthiban Nallathambi --- .../devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml index 70369bd633e4..3e00905b66ca 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml @@ -39,11 +39,13 @@ properties: items: - description: Bus Clock - description: Module Clock + - description: PLL common clock clock-names: items: - const: bus - const: mod + - const: pll-com resets: maxItems: 1 -- 2.39.5
[PATCH 00/22] Add support for A100/A133 display
This series depends on [1] for the eMMC/MMC controller to work and [2] (lined up for 6.14) which adds support for the sram nodes and display engine extends it's usage. Idea of this series to get initial feedback and adjust, which will be rebased for 6.14 once [2] is merged. This patch series adds support for A133 display pipeline based on LVDS. dt-bindigs are organized in the start and later with code changes. PHY is shared between DSI and LVDS, so to control the PHY specific to DSI/LVDS, phy_ops set_mode is introduced. To enable the DSI using set_mode, analog control register MIPI Enable is used, which may not be available for A31 (shares the same driver). Otherwise, A133 also got hidden independent display engine i.e mixer + tcon top to handle parallel display. But this patch series adds only support for the 1 mixer which is documented. [1]: https://lore.kernel.org/linux-sunxi/20241109003739.3440904-1-masterr3c0rd@epochal.quest/ [2]: https://lore.kernel.org/linux-sunxi/20241218-a100-syscon-v2-0-dae60b9ce192@epochal.quest/ Signed-off-by: Parthiban Nallathambi --- Parthiban Nallathambi (22): dt-bindings: iommu: sun50i: remove resets from required property dt-bindings: display: sunxi: Add a100/a133 display engine compatibles dt-bindings: clock: sun8i de2 clock: Add PLL com clock dt-bindings: clock: sun8i de2 clock: Add a100/a133 compatible dt-bindings: display: sun4i: add phy property dt-bindings: display: sun4i: add a100/a133 tcon lcd dt-bindings: vendor-prefixes: Shenzhen Baijie Technology dt-bindings: arm: sunxi: document Szbaijie A133 helper board iommu: sun50i: make reset control optional pinctrl: sunxi: add missed lvds pins for a100/a133 drm/sun4i: Add support for a100/a133 display engine drm/sun4i: Add support for a100/a133 mixer drm/sun4i: make tcon top tv0 optional drm/sun4i: add a100/a133 tcon top quirks clk: sunxi-ng: sun8i-de2: add pll-com clock support clk: sunxi-ng: sun8i-de2: Add support for a100/a133 phy: allwinner: phy-sun6i-mipi-dphy: add LVDS support drm/sun4i: tcon: add a100/a133 lcd controller support arm64: dts: allwinner: a100: add iommu clk: sunxi-ng: add missing pll-com binding arm64: dts: allwinner: a100: add display pipeline arm64: dts: allwinner: a133: add szbaijie helper board Documentation/devicetree/bindings/arm/sunxi.yaml | 6 + .../clock/allwinner,sun8i-a83t-de2-clk.yaml| 6 + .../allwinner,sun4i-a10-display-engine.yaml| 2 + .../bindings/display/allwinner,sun4i-a10-tcon.yaml | 7 + .../display/allwinner,sun8i-a83t-de2-mixer.yaml| 1 + .../display/allwinner,sun8i-r40-tcon-top.yaml | 17 ++ .../bindings/iommu/allwinner,sun50i-h6-iommu.yaml | 1 - .../devicetree/bindings/vendor-prefixes.yaml | 2 + arch/arm64/boot/dts/allwinner/Makefile | 1 + arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 165 ++ .../dts/allwinner/sun50i-a133-helper-board.dts | 129 ++ .../dts/allwinner/sun50i-a133-helper-core.dtsi | 190 + drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 23 ++- drivers/gpu/drm/sun4i/sun4i_drv.c | 1 + drivers/gpu/drm/sun4i/sun4i_tcon.c | 23 +++ drivers/gpu/drm/sun4i/sun8i_mixer.c| 13 ++ drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 42 +++-- drivers/iommu/sun50i-iommu.c | 2 +- drivers/phy/allwinner/phy-sun6i-mipi-dphy.c| 23 ++- drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c| 12 ++ include/dt-bindings/clock/sun50i-a100-ccu.h| 1 + 21 files changed, 645 insertions(+), 22 deletions(-) --- base-commit: 6c086b91df8c6619239c6d6d6cbf6ae50da6c110 change-id: 20241126-a133-display-support-ab43af32180a Best regards, -- Parthiban Nallathambi
[PATCH 02/22] dt-bindings: display: sunxi: Add a100/a133 display engine compatibles
A100/A133 comes with display enginer 2.0 with 1 x Mixer with write back support and 1 tcon top. Mixer can be used with lcd/lvds/dsi, but shares the same GPIO bank. Signed-off-by: Parthiban Nallathambi --- .../display/allwinner,sun4i-a10-display-engine.yaml | 2 ++ .../display/allwinner,sun8i-a83t-de2-mixer.yaml | 1 + .../bindings/display/allwinner,sun8i-r40-tcon-top.yaml | 17 + 3 files changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml index e6088f379f70..dc47c684fcb0 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml @@ -64,6 +64,7 @@ properties: - allwinner,sun9i-a80-display-engine - allwinner,sun20i-d1-display-engine - allwinner,sun50i-a64-display-engine + - allwinner,sun50i-a100-display-engine - allwinner,sun50i-h6-display-engine allwinner,pipelines: @@ -96,6 +97,7 @@ if: - allwinner,sun9i-a80-display-engine - allwinner,sun20i-d1-display-engine - allwinner,sun50i-a64-display-engine + - allwinner,sun50i-a100-display-engine then: properties: diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml index b75c1ec686ad..ebcddca2efb3 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml @@ -23,6 +23,7 @@ properties: - allwinner,sun20i-d1-de2-mixer-1 - allwinner,sun50i-a64-de2-mixer-0 - allwinner,sun50i-a64-de2-mixer-1 + - allwinner,sun50i-a100-de2-mixer-0 - allwinner,sun50i-h6-de3-mixer-0 reg: diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml index 7d849c4095a3..9b14b7fb2d2f 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml @@ -42,6 +42,7 @@ properties: enum: - allwinner,sun8i-r40-tcon-top - allwinner,sun20i-d1-tcon-top + - allwinner,sun50i-a100-tcon-top - allwinner,sun50i-h6-tcon-top reg: @@ -179,6 +180,22 @@ allOf: - description: TCON TV0 output clock name - description: DSI output clock name + - if: + properties: +compatible: + contains: +const: allwinner,sun50i-a100-tcon-top + +then: + properties: +clocks: + items: +- description: The TCON TOP interface clock + +clock-names: + items: +- const: bus + - if: properties: compatible: -- 2.39.5
[PATCH 04/22] dt-bindings: clock: sun8i de2 clock: Add a100/a133 compatible
A100/A133 uses one mixer without rotation support, which is same as sun8i v3s. Add it with fallback to v3s compatible. Signed-off-by: Parthiban Nallathambi --- .../devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml index 3e00905b66ca..ed038967929b 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml @@ -23,6 +23,7 @@ properties: - const: allwinner,sun8i-h3-de2-clk - const: allwinner,sun8i-v3s-de2-clk - const: allwinner,sun50i-a64-de2-clk + - const: allwinner,sun50i-a100-de2-clk - const: allwinner,sun50i-h5-de2-clk - const: allwinner,sun50i-h6-de3-clk - items: @@ -31,6 +32,9 @@ properties: - items: - const: allwinner,sun20i-d1-de2-clk - const: allwinner,sun50i-h5-de2-clk + - items: + - const: allwinner,sun50i-a100-de2-clk + - const: allwinner,sun8i-v3s-de2-clk reg: maxItems: 1 -- 2.39.5
[PATCH 03/22] dt-bindings: clock: sun8i de2 clock: Add PLL com clock
Some platforms like A100/A133 also uses pll-com clock as additional clock source for the display clock. This is not documents both in user manual and DE 2.0 specification. These changes are mainly from vendor BSP. Signed-off-by: Parthiban Nallathambi --- .../devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml index 70369bd633e4..3e00905b66ca 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml @@ -39,11 +39,13 @@ properties: items: - description: Bus Clock - description: Module Clock + - description: PLL common clock clock-names: items: - const: bus - const: mod + - const: pll-com resets: maxItems: 1 -- 2.39.5
[PATCH 05/22] dt-bindings: display: sun4i: add phy property
lvds in A100/A133 platform uses phy from DSI block, which needs to be handled in phy driver. Add phy property to tcon with generic name 'phy'. Signed-off-by: Parthiban Nallathambi --- .../devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml index 724d93b9193b..6d8ae781c230 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml @@ -115,6 +115,12 @@ properties: - const: edp - const: lvds + phys: +maxItems: 1 + + phy-names: +const: phy + ports: $ref: /schemas/graph.yaml#/properties/ports -- 2.39.5
[PATCH 06/22] dt-bindings: display: sun4i: add a100/a133 tcon lcd
A100/A133 has one 18 bit LCD / 2 x LVDS / 1 x DSI. All the controller shares the same GPIO D block, where LVDS controller can co-exits. Although 2 LVDS controller is available, there is no document details for the second. Add compatible for a100 lcd controller. Signed-off-by: Parthiban Nallathambi --- Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml index 6d8ae781c230..7ea45a0a2073 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml @@ -35,6 +35,7 @@ properties: - const: allwinner,sun9i-a80-tcon-tv - const: allwinner,sun20i-d1-tcon-lcd - const: allwinner,sun20i-d1-tcon-tv + - const: allwinner,sun50i-a100-tcon-lcd - items: - enum: -- 2.39.5
[PATCH 01/22] dt-bindings: iommu: sun50i: remove resets from required property
iommu in a133/a100 does not have reset control. remove it from required property to make it optional. Signed-off-by: Parthiban Nallathambi --- Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml b/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml index a8409db4a3e3..03176f68485b 100644 --- a/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml @@ -42,7 +42,6 @@ required: - reg - interrupts - clocks - - resets additionalProperties: false -- 2.39.5
[PATCH 17/22] phy: allwinner: phy-sun6i-mipi-dphy: add LVDS support
DPHY in A100/A133 supports both LVDS and DSI. Combo phy register
have BIT(2) for enabling LVDS specifically, but enabling it alone
isn't functional.
Both MIPI and LVDS needs to be enabled in the combo phy to get
the display working under LVDS mode. There is no specific enable
bit for LVDS apart from the one in combo phy. MIPI got enable
control in analog 4 register which must be disabled when using
in LVDS mode.
Introduce set_mode in phy ops to control only for MIPI DSI.
Signed-off-by: Parthiban Nallathambi
---
drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 36eab95271b2..d164b2ea5dfd 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -314,13 +314,11 @@ static void sun50i_a100_mipi_dphy_tx_power_on(struct
sun6i_dphy *dphy)
/* Disable sigma-delta modulation. */
regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG2, 0);
- regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG,
- SUN6I_DPHY_ANA4_REG_EN_MIPI,
- SUN6I_DPHY_ANA4_REG_EN_MIPI);
-
regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0,
+ SUN50I_COMBO_PHY_REG0_EN_LVDS |
SUN50I_COMBO_PHY_REG0_EN_MIPI |
SUN50I_COMBO_PHY_REG0_EN_COMBOLDO,
+ SUN50I_COMBO_PHY_REG0_EN_LVDS |
SUN50I_COMBO_PHY_REG0_EN_MIPI |
SUN50I_COMBO_PHY_REG0_EN_COMBOLDO);
@@ -528,6 +526,22 @@ static int sun6i_dphy_exit(struct phy *phy)
return 0;
}
+static int sun6i_set_mode(struct phy *phy, enum phy_mode mode, int submode)
+{
+ struct sun6i_dphy *dphy = phy_get_drvdata(phy);
+
+ switch (mode) {
+ case PHY_MODE_MIPI_DPHY:
+ regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG,
+ SUN6I_DPHY_ANA4_REG_EN_MIPI,
+ SUN6I_DPHY_ANA4_REG_EN_MIPI);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
static const struct phy_ops sun6i_dphy_ops = {
.configure = sun6i_dphy_configure,
@@ -535,6 +549,7 @@ static const struct phy_ops sun6i_dphy_ops = {
.power_off = sun6i_dphy_power_off,
.init = sun6i_dphy_init,
.exit = sun6i_dphy_exit,
+ .set_mode = sun6i_set_mode,
};
static const struct regmap_config sun6i_dphy_regmap_config = {
--
2.39.5
[PATCH 09/22] iommu: sun50i: make reset control optional
A133/A100 SoC doesn't have reset control from the CCU. Get reset
control line optionally.
Signed-off-by: Parthiban Nallathambi
---
drivers/iommu/sun50i-iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c
index 8d8f11854676..2ba804d682dc 100644
--- a/drivers/iommu/sun50i-iommu.c
+++ b/drivers/iommu/sun50i-iommu.c
@@ -1030,7 +1030,7 @@ static int sun50i_iommu_probe(struct platform_device
*pdev)
goto err_free_cache;
}
- iommu->reset = devm_reset_control_get(&pdev->dev, NULL);
+ iommu->reset = devm_reset_control_get_optional(&pdev->dev, NULL);
if (IS_ERR(iommu->reset)) {
dev_err(&pdev->dev, "Couldn't get our reset line.\n");
ret = PTR_ERR(iommu->reset);
--
2.39.5
[PATCH 10/22] pinctrl: sunxi: add missed lvds pins for a100/a133
lvds, lcd, dsi all shares the same GPIO D bank and lvds0
data 3 lines and lvds1 pins are missed, add them.
Signed-off-by: Parthiban Nallathambi
---
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
index df90c75fb3c5..b97de80ae2f3 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
@@ -256,72 +256,84 @@ static const struct sunxi_desc_pin a100_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* D3P */
SUNXI_FUNCTION(0x4, "dsi0"), /* DP3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* D3N */
SUNXI_FUNCTION(0x4, "dsi0"), /* DM3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D0P */
SUNXI_FUNCTION(0x4, "spi1"), /* CS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D0N */
SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D1P */
SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D1N */
SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D2P */
SUNXI_FUNCTION(0x4, "uart3"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D2N */
SUNXI_FUNCTION(0x4, "uart3"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* CKP */
SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* CKN */
SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x
[PATCH 13/22] drm/sun4i: make tcon top tv0 optional
current implementation of tcon top assumes tv0 is always present, which
isn't case in A100/A133 SoC's. Make tv0 optional by introducing another
control similar to tv1 and make existing users with true/present.
Signed-off-by: Parthiban Nallathambi
---
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 34 --
1 file changed, 20 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
index 8adda578c51b..bd9d0840ead7 100644
--- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
+++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
@@ -16,6 +16,7 @@
#include "sun8i_tcon_top.h"
struct sun8i_tcon_top_quirks {
+ bool has_tcon_tv0;
bool has_tcon_tv1;
bool has_dsi;
};
@@ -191,10 +192,11 @@ static int sun8i_tcon_top_bind(struct device *dev, struct
device *master,
* to TVE clock parent.
*/
i = 0;
- clk_data->hws[CLK_TCON_TOP_TV0] =
- sun8i_tcon_top_register_gate(dev, "tcon-tv0", regs,
-&tcon_top->reg_lock,
-TCON_TOP_TCON_TV0_GATE, i++);
+ if (quirks->has_tcon_tv0)
+ clk_data->hws[CLK_TCON_TOP_TV0] =
+ sun8i_tcon_top_register_gate(dev, "tcon-tv0", regs,
+&tcon_top->reg_lock,
+TCON_TOP_TCON_TV0_GATE,
i++);
if (quirks->has_tcon_tv1)
clk_data->hws[CLK_TCON_TOP_TV1] =
@@ -208,16 +210,18 @@ static int sun8i_tcon_top_bind(struct device *dev, struct
device *master,
&tcon_top->reg_lock,
TCON_TOP_TCON_DSI_GATE,
i++);
- for (i = 0; i < CLK_NUM; i++)
- if (IS_ERR(clk_data->hws[i])) {
- ret = PTR_ERR(clk_data->hws[i]);
- goto err_unregister_gates;
- }
+ if (i) {
+ for (i = 0; i < CLK_NUM; i++)
+ if (IS_ERR(clk_data->hws[i])) {
+ ret = PTR_ERR(clk_data->hws[i]);
+ goto err_unregister_gates;
+ }
- ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
-clk_data);
- if (ret)
- goto err_unregister_gates;
+ ret = of_clk_add_hw_provider(dev->of_node,
of_clk_hw_onecell_get,
+ clk_data);
+ if (ret)
+ goto err_unregister_gates;
+ }
dev_set_drvdata(dev, tcon_top);
@@ -266,16 +270,18 @@ static void sun8i_tcon_top_remove(struct platform_device
*pdev)
}
static const struct sun8i_tcon_top_quirks sun8i_r40_tcon_top_quirks = {
+ .has_tcon_tv0 = true,
.has_tcon_tv1 = true,
.has_dsi= true,
};
static const struct sun8i_tcon_top_quirks sun20i_d1_tcon_top_quirks = {
+ .has_tcon_tv0 = true,
.has_dsi= true,
};
static const struct sun8i_tcon_top_quirks sun50i_h6_tcon_top_quirks = {
- /* Nothing special */
+ .has_tcon_tv0 = true,
};
/* sun4i_drv uses this list to check if a device node is a TCON TOP */
--
2.39.5
[PATCH 15/22] clk: sunxi-ng: sun8i-de2: add pll-com clock support
add optional pll-com support which is available in some platforms
like A100/A133, which is used by the display clock. There is no
documentation reference or details in DE 2.0 specification.
But these changes are needed to get the display clock to work and
this is inherited from the vendor BSP.
Signed-off-by: Parthiban Nallathambi
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index f2aa71206bc2..3e28c32050e0 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -241,7 +241,7 @@ static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc =
{
static int sunxi_de2_clk_probe(struct platform_device *pdev)
{
- struct clk *bus_clk, *mod_clk;
+ struct clk *bus_clk, *mod_clk, *pll_clk;
struct reset_control *rstc;
void __iomem *reg;
const struct sunxi_ccu_desc *ccu_desc;
@@ -265,6 +265,11 @@ static int sunxi_de2_clk_probe(struct platform_device
*pdev)
return dev_err_probe(&pdev->dev, PTR_ERR(mod_clk),
"Couldn't get mod clk\n");
+ pll_clk = devm_clk_get_optional(&pdev->dev, "pll-com");
+ if (IS_ERR(pll_clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(pll_clk),
+"Couldn't get pll clk\n");
+
rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(rstc))
return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
@@ -283,12 +288,20 @@ static int sunxi_de2_clk_probe(struct platform_device
*pdev)
goto err_disable_bus_clk;
}
+ if (pll_clk) {
+ ret = clk_prepare_enable(pll_clk);
+ if (ret) {
+ dev_err(&pdev->dev, "Couldn't enable pll clk: %d\n",
ret);
+ goto err_disable_mod_clk;
+ }
+ }
+
/* The reset control needs to be asserted for the controls to work */
ret = reset_control_deassert(rstc);
if (ret) {
dev_err(&pdev->dev,
"Couldn't deassert reset control: %d\n", ret);
- goto err_disable_mod_clk;
+ goto err_disable_pll_clk;
}
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, ccu_desc);
@@ -299,6 +312,8 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev)
err_assert_reset:
reset_control_assert(rstc);
+err_disable_pll_clk:
+ clk_disable_unprepare(pll_clk);
err_disable_mod_clk:
clk_disable_unprepare(mod_clk);
err_disable_bus_clk:
--
2.39.5
[PATCH 07/22] dt-bindings: vendor-prefixes: Shenzhen Baijie Technology
Add entry for Shenzhen Baijie Technology (https://szbaijie.com) Signed-off-by: Parthiban Nallathambi --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index da01616802c7..81cbc8b6b195 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1466,6 +1466,8 @@ patternProperties: "^synopsys,.*": description: Synopsys, Inc. (deprecated, use snps) deprecated: true + "^szbaijie,.*": +description: Shenzhen Baijie Technology Co., Ltd. "^tbs,.*": description: TBS Technologies "^tbs-biometrics,.*": -- 2.39.5
[PATCH 08/22] dt-bindings: arm: sunxi: document Szbaijie A133 helper board
Szbaijie Baijie Technology A133 helper board is an evaluation board of their A133-Core SoM. Add its compatible (with the SoM compatible) to the sunxi board DT binding file. Signed-off-by: Parthiban Nallathambi --- Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 046536d02706..eb19f8b1fe68 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -891,6 +891,12 @@ properties: - const: allwinner,sl631 - const: allwinner,sun8i-v3 + - description: Szbaijie A133 Helper board +items: + - const: szbaijie,helper-a133 + - const: szbaijie,helper-a133-core + - const: allwinner,sun50i-a133 + - description: Tanix TX1 items: - const: oranth,tanix-tx1 -- 2.39.5
[PATCH 12/22] drm/sun4i: Add support for a100/a133 mixer
Mixers in Allwinner A100/A133 have similar capabilities as others
SoCs with DE2. Add support for them.
Signed-off-by: Parthiban Nallathambi
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 8b41d33baa30..0a1fccb87d5d 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -714,6 +714,15 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg
= {
.vi_num = 1,
};
+static const struct sun8i_mixer_cfg sun50i_a100_mixer0_cfg = {
+ .ccsc = CCSC_MIXER0_LAYOUT,
+ .mod_rate = 3,
+ .scaler_mask= 0xf,
+ .scanline_yuv = 2560,
+ .ui_num = 2,
+ .vi_num = 2,
+};
+
static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = {
.ccsc = CCSC_MIXER0_LAYOUT,
.is_de3 = true,
@@ -765,6 +774,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = {
.compatible = "allwinner,sun50i-a64-de2-mixer-1",
.data = &sun50i_a64_mixer1_cfg,
},
+ {
+ .compatible = "allwinner,sun50i-a100-de2-mixer-0",
+ .data = &sun50i_a100_mixer0_cfg,
+ },
{
.compatible = "allwinner,sun50i-h6-de3-mixer-0",
.data = &sun50i_h6_mixer0_cfg,
--
2.39.5
[PATCH 14/22] drm/sun4i: add a100/a133 tcon top quirks
A100/A133 comes with 2 x LVDS, 1 x DSI without TV support. Add
quirks with tv0 disabled. DSI support is not added.
Signed-off-by: Parthiban Nallathambi
---
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
index bd9d0840ead7..a777b30ecea0 100644
--- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
+++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
@@ -280,6 +280,10 @@ static const struct sun8i_tcon_top_quirks
sun20i_d1_tcon_top_quirks = {
.has_dsi= true,
};
+static const struct sun8i_tcon_top_quirks sun50i_a100_tcon_top_quirks = {
+ /* TODO DSI support */
+};
+
static const struct sun8i_tcon_top_quirks sun50i_h6_tcon_top_quirks = {
.has_tcon_tv0 = true,
};
@@ -294,6 +298,10 @@ const struct of_device_id sun8i_tcon_top_of_table[] = {
.compatible = "allwinner,sun20i-d1-tcon-top",
.data = &sun20i_d1_tcon_top_quirks
},
+ {
+ .compatible = "allwinner,sun50i-a100-tcon-top",
+ .data = &sun50i_a100_tcon_top_quirks
+ },
{
.compatible = "allwinner,sun50i-h6-tcon-top",
.data = &sun50i_h6_tcon_top_quirks
--
2.39.5
[PATCH 11/22] drm/sun4i: Add support for a100/a133 display engine
Display Engine(DE2) in Allwinner A100/A133 has one mixers and tcon.
The routing for mixer0 is through tcon0 and connected to
LVDS/RGB/MIPI-DSI controller.
Signed-off-by: Parthiban Nallathambi
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 5eccf58f2e17..e012a6316bba 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -436,6 +436,7 @@ static const struct of_device_id sun4i_drv_of_table[] = {
{ .compatible = "allwinner,sun9i-a80-display-engine" },
{ .compatible = "allwinner,sun20i-d1-display-engine" },
{ .compatible = "allwinner,sun50i-a64-display-engine" },
+ { .compatible = "allwinner,sun50i-a100-display-engine" },
{ .compatible = "allwinner,sun50i-h6-display-engine" },
{ }
};
--
2.39.5
[PATCH 16/22] clk: sunxi-ng: sun8i-de2: Add support for a100/a133
Display clock uses 1 mixer without rotation support is same
as v3s. There is also a hidden independent display engine
with independent tcon_top available in A100/A133 bin (based
on vendor BSP).
Add new compatible for A100/A133 to accommodate the future changes
for the independent DE.
Signed-off-by: Parthiban Nallathambi
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 3e28c32050e0..067820ab704d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -342,6 +342,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
.compatible = "allwinner,sun50i-a64-de2-clk",
.data = &sun50i_a64_de2_clk_desc,
},
+ {
+ .compatible = "allwinner,sun50i-a100-de2-clk",
+ .data = &sun8i_v3s_de2_clk_desc,
+ },
{
.compatible = "allwinner,sun50i-h5-de2-clk",
.data = &sun50i_h5_de2_clk_desc,
--
2.39.5
[PATCH RESEND 00/22] Add support for A100/A133 display
This series depends on [1] for the eMMC/MMC controller to work and [2] (lined up for 6.14) which adds support for the sram nodes and display engine extends it's usage. Idea of this series to get initial feedback and adjust, which will be rebased for 6.14 once [2] is merged. This patch series adds support for A133 display pipeline based on LVDS. dt-bindigs are organized in the start and later with code changes. PHY is shared between DSI and LVDS, so to control the PHY specific to DSI/LVDS, phy_ops set_mode is introduced. To enable the DSI using set_mode, analog control register MIPI Enable is used, which may not be available for A31 (shares the same driver). Otherwise, A133 also got hidden independent display engine i.e mixer + tcon top to handle parallel display. But this patch series adds only support for the 1 mixer which is documented. [1]: https://lore.kernel.org/linux-sunxi/20241109003739.3440904-1-masterr3c0rd@epochal.quest/ [2]: https://lore.kernel.org/linux-sunxi/20241218-a100-syscon-v2-0-dae60b9ce192@epochal.quest/ Signed-off-by: Parthiban Nallathambi --- Parthiban Nallathambi (22): dt-bindings: iommu: sun50i: remove resets from required property dt-bindings: display: sunxi: Add a100/a133 display engine compatibles dt-bindings: clock: sun8i de2 clock: Add PLL com clock dt-bindings: clock: sun8i de2 clock: Add a100/a133 compatible dt-bindings: display: sun4i: add phy property dt-bindings: display: sun4i: add a100/a133 tcon lcd dt-bindings: vendor-prefixes: Shenzhen Baijie Technology dt-bindings: arm: sunxi: document Szbaijie A133 helper board iommu: sun50i: make reset control optional pinctrl: sunxi: add missed lvds pins for a100/a133 drm/sun4i: Add support for a100/a133 display engine drm/sun4i: Add support for a100/a133 mixer drm/sun4i: make tcon top tv0 optional drm/sun4i: add a100/a133 tcon top quirks clk: sunxi-ng: sun8i-de2: add pll-com clock support clk: sunxi-ng: sun8i-de2: Add support for a100/a133 phy: allwinner: phy-sun6i-mipi-dphy: add LVDS support drm/sun4i: tcon: add a100/a133 lcd controller support arm64: dts: allwinner: a100: add iommu clk: sunxi-ng: add missing pll-com binding arm64: dts: allwinner: a100: add display pipeline arm64: dts: allwinner: a133: add szbaijie helper board Documentation/devicetree/bindings/arm/sunxi.yaml | 6 + .../clock/allwinner,sun8i-a83t-de2-clk.yaml| 6 + .../allwinner,sun4i-a10-display-engine.yaml| 2 + .../bindings/display/allwinner,sun4i-a10-tcon.yaml | 7 + .../display/allwinner,sun8i-a83t-de2-mixer.yaml| 1 + .../display/allwinner,sun8i-r40-tcon-top.yaml | 17 ++ .../bindings/iommu/allwinner,sun50i-h6-iommu.yaml | 1 - .../devicetree/bindings/vendor-prefixes.yaml | 2 + arch/arm64/boot/dts/allwinner/Makefile | 1 + arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 165 ++ .../dts/allwinner/sun50i-a133-helper-board.dts | 129 ++ .../dts/allwinner/sun50i-a133-helper-core.dtsi | 190 + drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 23 ++- drivers/gpu/drm/sun4i/sun4i_drv.c | 1 + drivers/gpu/drm/sun4i/sun4i_tcon.c | 23 +++ drivers/gpu/drm/sun4i/sun8i_mixer.c| 13 ++ drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 42 +++-- drivers/iommu/sun50i-iommu.c | 2 +- drivers/phy/allwinner/phy-sun6i-mipi-dphy.c| 23 ++- drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c| 12 ++ include/dt-bindings/clock/sun50i-a100-ccu.h| 1 + 21 files changed, 645 insertions(+), 22 deletions(-) --- base-commit: 6c086b91df8c6619239c6d6d6cbf6ae50da6c110 change-id: 20241126-a133-display-support-ab43af32180a Best regards, -- Parthiban Nallathambi
[PATCH RESEND 01/22] dt-bindings: iommu: sun50i: remove resets from required property
iommu in a133/a100 does not have reset control. remove it from required property to make it optional. Signed-off-by: Parthiban Nallathambi --- Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml b/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml index a8409db4a3e3..03176f68485b 100644 --- a/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml @@ -42,7 +42,6 @@ required: - reg - interrupts - clocks - - resets additionalProperties: false -- 2.39.5
[PATCH RESEND 02/22] dt-bindings: display: sunxi: Add a100/a133 display engine compatibles
A100/A133 comes with display enginer 2.0 with 1 x Mixer with write back support and 1 tcon top. Mixer can be used with lcd/lvds/dsi, but shares the same GPIO bank. Signed-off-by: Parthiban Nallathambi --- .../display/allwinner,sun4i-a10-display-engine.yaml | 2 ++ .../display/allwinner,sun8i-a83t-de2-mixer.yaml | 1 + .../bindings/display/allwinner,sun8i-r40-tcon-top.yaml | 17 + 3 files changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml index e6088f379f70..dc47c684fcb0 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml @@ -64,6 +64,7 @@ properties: - allwinner,sun9i-a80-display-engine - allwinner,sun20i-d1-display-engine - allwinner,sun50i-a64-display-engine + - allwinner,sun50i-a100-display-engine - allwinner,sun50i-h6-display-engine allwinner,pipelines: @@ -96,6 +97,7 @@ if: - allwinner,sun9i-a80-display-engine - allwinner,sun20i-d1-display-engine - allwinner,sun50i-a64-display-engine + - allwinner,sun50i-a100-display-engine then: properties: diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml index b75c1ec686ad..ebcddca2efb3 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml @@ -23,6 +23,7 @@ properties: - allwinner,sun20i-d1-de2-mixer-1 - allwinner,sun50i-a64-de2-mixer-0 - allwinner,sun50i-a64-de2-mixer-1 + - allwinner,sun50i-a100-de2-mixer-0 - allwinner,sun50i-h6-de3-mixer-0 reg: diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml index 7d849c4095a3..9b14b7fb2d2f 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml @@ -42,6 +42,7 @@ properties: enum: - allwinner,sun8i-r40-tcon-top - allwinner,sun20i-d1-tcon-top + - allwinner,sun50i-a100-tcon-top - allwinner,sun50i-h6-tcon-top reg: @@ -179,6 +180,22 @@ allOf: - description: TCON TV0 output clock name - description: DSI output clock name + - if: + properties: +compatible: + contains: +const: allwinner,sun50i-a100-tcon-top + +then: + properties: +clocks: + items: +- description: The TCON TOP interface clock + +clock-names: + items: +- const: bus + - if: properties: compatible: -- 2.39.5
[PATCH RESEND 04/22] dt-bindings: clock: sun8i de2 clock: Add a100/a133 compatible
A100/A133 uses one mixer without rotation support, which is same as sun8i v3s. Add it with fallback to v3s compatible. Signed-off-by: Parthiban Nallathambi --- .../devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml index 3e00905b66ca..ed038967929b 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml @@ -23,6 +23,7 @@ properties: - const: allwinner,sun8i-h3-de2-clk - const: allwinner,sun8i-v3s-de2-clk - const: allwinner,sun50i-a64-de2-clk + - const: allwinner,sun50i-a100-de2-clk - const: allwinner,sun50i-h5-de2-clk - const: allwinner,sun50i-h6-de3-clk - items: @@ -31,6 +32,9 @@ properties: - items: - const: allwinner,sun20i-d1-de2-clk - const: allwinner,sun50i-h5-de2-clk + - items: + - const: allwinner,sun50i-a100-de2-clk + - const: allwinner,sun8i-v3s-de2-clk reg: maxItems: 1 -- 2.39.5
[PATCH RESEND 05/22] dt-bindings: display: sun4i: add phy property
lvds in A100/A133 platform uses phy from DSI block, which needs to be handled in phy driver. Add phy property to tcon with generic name 'phy'. Signed-off-by: Parthiban Nallathambi --- .../devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml index 724d93b9193b..6d8ae781c230 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml @@ -115,6 +115,12 @@ properties: - const: edp - const: lvds + phys: +maxItems: 1 + + phy-names: +const: phy + ports: $ref: /schemas/graph.yaml#/properties/ports -- 2.39.5
[PATCH RESEND 07/22] dt-bindings: vendor-prefixes: Shenzhen Baijie Technology
Add entry for Shenzhen Baijie Technology (https://szbaijie.com) Signed-off-by: Parthiban Nallathambi --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index da01616802c7..81cbc8b6b195 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1466,6 +1466,8 @@ patternProperties: "^synopsys,.*": description: Synopsys, Inc. (deprecated, use snps) deprecated: true + "^szbaijie,.*": +description: Shenzhen Baijie Technology Co., Ltd. "^tbs,.*": description: TBS Technologies "^tbs-biometrics,.*": -- 2.39.5
[PATCH RESEND 10/22] pinctrl: sunxi: add missed lvds pins for a100/a133
lvds, lcd, dsi all shares the same GPIO D bank and lvds0
data 3 lines and lvds1 pins are missed, add them.
Signed-off-by: Parthiban Nallathambi
---
drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
index df90c75fb3c5..b97de80ae2f3 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
@@ -256,72 +256,84 @@ static const struct sunxi_desc_pin a100_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* D3P */
SUNXI_FUNCTION(0x4, "dsi0"), /* DP3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
+ SUNXI_FUNCTION(0x3, "lvds0"), /* D3N */
SUNXI_FUNCTION(0x4, "dsi0"), /* DM3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D0P */
SUNXI_FUNCTION(0x4, "spi1"), /* CS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D0N */
SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D1P */
SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D1N */
SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D2P */
SUNXI_FUNCTION(0x4, "uart3"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* D2N */
SUNXI_FUNCTION(0x4, "uart3"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* CKP */
SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
+ SUNXI_FUNCTION(0x3, "lvds1"), /* CKN */
SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x
[PATCH RESEND 15/22] clk: sunxi-ng: sun8i-de2: add pll-com clock support
add optional pll-com support which is available in some platforms
like A100/A133, which is used by the display clock. There is no
documentation reference or details in DE 2.0 specification.
But these changes are needed to get the display clock to work and
this is inherited from the vendor BSP.
Signed-off-by: Parthiban Nallathambi
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index f2aa71206bc2..3e28c32050e0 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -241,7 +241,7 @@ static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc =
{
static int sunxi_de2_clk_probe(struct platform_device *pdev)
{
- struct clk *bus_clk, *mod_clk;
+ struct clk *bus_clk, *mod_clk, *pll_clk;
struct reset_control *rstc;
void __iomem *reg;
const struct sunxi_ccu_desc *ccu_desc;
@@ -265,6 +265,11 @@ static int sunxi_de2_clk_probe(struct platform_device
*pdev)
return dev_err_probe(&pdev->dev, PTR_ERR(mod_clk),
"Couldn't get mod clk\n");
+ pll_clk = devm_clk_get_optional(&pdev->dev, "pll-com");
+ if (IS_ERR(pll_clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(pll_clk),
+"Couldn't get pll clk\n");
+
rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(rstc))
return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
@@ -283,12 +288,20 @@ static int sunxi_de2_clk_probe(struct platform_device
*pdev)
goto err_disable_bus_clk;
}
+ if (pll_clk) {
+ ret = clk_prepare_enable(pll_clk);
+ if (ret) {
+ dev_err(&pdev->dev, "Couldn't enable pll clk: %d\n",
ret);
+ goto err_disable_mod_clk;
+ }
+ }
+
/* The reset control needs to be asserted for the controls to work */
ret = reset_control_deassert(rstc);
if (ret) {
dev_err(&pdev->dev,
"Couldn't deassert reset control: %d\n", ret);
- goto err_disable_mod_clk;
+ goto err_disable_pll_clk;
}
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, ccu_desc);
@@ -299,6 +312,8 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev)
err_assert_reset:
reset_control_assert(rstc);
+err_disable_pll_clk:
+ clk_disable_unprepare(pll_clk);
err_disable_mod_clk:
clk_disable_unprepare(mod_clk);
err_disable_bus_clk:
--
2.39.5
[PATCH RESEND 14/22] drm/sun4i: add a100/a133 tcon top quirks
A100/A133 comes with 2 x LVDS, 1 x DSI without TV support. Add
quirks with tv0 disabled. DSI support is not added.
Signed-off-by: Parthiban Nallathambi
---
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
index bd9d0840ead7..a777b30ecea0 100644
--- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
+++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
@@ -280,6 +280,10 @@ static const struct sun8i_tcon_top_quirks
sun20i_d1_tcon_top_quirks = {
.has_dsi= true,
};
+static const struct sun8i_tcon_top_quirks sun50i_a100_tcon_top_quirks = {
+ /* TODO DSI support */
+};
+
static const struct sun8i_tcon_top_quirks sun50i_h6_tcon_top_quirks = {
.has_tcon_tv0 = true,
};
@@ -294,6 +298,10 @@ const struct of_device_id sun8i_tcon_top_of_table[] = {
.compatible = "allwinner,sun20i-d1-tcon-top",
.data = &sun20i_d1_tcon_top_quirks
},
+ {
+ .compatible = "allwinner,sun50i-a100-tcon-top",
+ .data = &sun50i_a100_tcon_top_quirks
+ },
{
.compatible = "allwinner,sun50i-h6-tcon-top",
.data = &sun50i_h6_tcon_top_quirks
--
2.39.5
[PATCH RESEND 13/22] drm/sun4i: make tcon top tv0 optional
current implementation of tcon top assumes tv0 is always present, which
isn't case in A100/A133 SoC's. Make tv0 optional by introducing another
control similar to tv1 and make existing users with true/present.
Signed-off-by: Parthiban Nallathambi
---
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 34 --
1 file changed, 20 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
index 8adda578c51b..bd9d0840ead7 100644
--- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
+++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
@@ -16,6 +16,7 @@
#include "sun8i_tcon_top.h"
struct sun8i_tcon_top_quirks {
+ bool has_tcon_tv0;
bool has_tcon_tv1;
bool has_dsi;
};
@@ -191,10 +192,11 @@ static int sun8i_tcon_top_bind(struct device *dev, struct
device *master,
* to TVE clock parent.
*/
i = 0;
- clk_data->hws[CLK_TCON_TOP_TV0] =
- sun8i_tcon_top_register_gate(dev, "tcon-tv0", regs,
-&tcon_top->reg_lock,
-TCON_TOP_TCON_TV0_GATE, i++);
+ if (quirks->has_tcon_tv0)
+ clk_data->hws[CLK_TCON_TOP_TV0] =
+ sun8i_tcon_top_register_gate(dev, "tcon-tv0", regs,
+&tcon_top->reg_lock,
+TCON_TOP_TCON_TV0_GATE,
i++);
if (quirks->has_tcon_tv1)
clk_data->hws[CLK_TCON_TOP_TV1] =
@@ -208,16 +210,18 @@ static int sun8i_tcon_top_bind(struct device *dev, struct
device *master,
&tcon_top->reg_lock,
TCON_TOP_TCON_DSI_GATE,
i++);
- for (i = 0; i < CLK_NUM; i++)
- if (IS_ERR(clk_data->hws[i])) {
- ret = PTR_ERR(clk_data->hws[i]);
- goto err_unregister_gates;
- }
+ if (i) {
+ for (i = 0; i < CLK_NUM; i++)
+ if (IS_ERR(clk_data->hws[i])) {
+ ret = PTR_ERR(clk_data->hws[i]);
+ goto err_unregister_gates;
+ }
- ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
-clk_data);
- if (ret)
- goto err_unregister_gates;
+ ret = of_clk_add_hw_provider(dev->of_node,
of_clk_hw_onecell_get,
+ clk_data);
+ if (ret)
+ goto err_unregister_gates;
+ }
dev_set_drvdata(dev, tcon_top);
@@ -266,16 +270,18 @@ static void sun8i_tcon_top_remove(struct platform_device
*pdev)
}
static const struct sun8i_tcon_top_quirks sun8i_r40_tcon_top_quirks = {
+ .has_tcon_tv0 = true,
.has_tcon_tv1 = true,
.has_dsi= true,
};
static const struct sun8i_tcon_top_quirks sun20i_d1_tcon_top_quirks = {
+ .has_tcon_tv0 = true,
.has_dsi= true,
};
static const struct sun8i_tcon_top_quirks sun50i_h6_tcon_top_quirks = {
- /* Nothing special */
+ .has_tcon_tv0 = true,
};
/* sun4i_drv uses this list to check if a device node is a TCON TOP */
--
2.39.5
[PATCH RESEND 09/22] iommu: sun50i: make reset control optional
A133/A100 SoC doesn't have reset control from the CCU. Get reset
control line optionally.
Signed-off-by: Parthiban Nallathambi
---
drivers/iommu/sun50i-iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c
index 8d8f11854676..2ba804d682dc 100644
--- a/drivers/iommu/sun50i-iommu.c
+++ b/drivers/iommu/sun50i-iommu.c
@@ -1030,7 +1030,7 @@ static int sun50i_iommu_probe(struct platform_device
*pdev)
goto err_free_cache;
}
- iommu->reset = devm_reset_control_get(&pdev->dev, NULL);
+ iommu->reset = devm_reset_control_get_optional(&pdev->dev, NULL);
if (IS_ERR(iommu->reset)) {
dev_err(&pdev->dev, "Couldn't get our reset line.\n");
ret = PTR_ERR(iommu->reset);
--
2.39.5
[PATCH RESEND 06/22] dt-bindings: display: sun4i: add a100/a133 tcon lcd
A100/A133 has one 18 bit LCD / 2 x LVDS / 1 x DSI. All the controller shares the same GPIO D block, where LVDS controller can co-exits. Although 2 LVDS controller is available, there is no document details for the second. Add compatible for a100 lcd controller. Signed-off-by: Parthiban Nallathambi --- Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml index 6d8ae781c230..7ea45a0a2073 100644 --- a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml @@ -35,6 +35,7 @@ properties: - const: allwinner,sun9i-a80-tcon-tv - const: allwinner,sun20i-d1-tcon-lcd - const: allwinner,sun20i-d1-tcon-tv + - const: allwinner,sun50i-a100-tcon-lcd - items: - enum: -- 2.39.5
[PATCH RESEND 12/22] drm/sun4i: Add support for a100/a133 mixer
Mixers in Allwinner A100/A133 have similar capabilities as others
SoCs with DE2. Add support for them.
Signed-off-by: Parthiban Nallathambi
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 8b41d33baa30..0a1fccb87d5d 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -714,6 +714,15 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg
= {
.vi_num = 1,
};
+static const struct sun8i_mixer_cfg sun50i_a100_mixer0_cfg = {
+ .ccsc = CCSC_MIXER0_LAYOUT,
+ .mod_rate = 3,
+ .scaler_mask= 0xf,
+ .scanline_yuv = 2560,
+ .ui_num = 2,
+ .vi_num = 2,
+};
+
static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = {
.ccsc = CCSC_MIXER0_LAYOUT,
.is_de3 = true,
@@ -765,6 +774,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = {
.compatible = "allwinner,sun50i-a64-de2-mixer-1",
.data = &sun50i_a64_mixer1_cfg,
},
+ {
+ .compatible = "allwinner,sun50i-a100-de2-mixer-0",
+ .data = &sun50i_a100_mixer0_cfg,
+ },
{
.compatible = "allwinner,sun50i-h6-de3-mixer-0",
.data = &sun50i_h6_mixer0_cfg,
--
2.39.5
[PATCH RESEND 11/22] drm/sun4i: Add support for a100/a133 display engine
Display Engine(DE2) in Allwinner A100/A133 has one mixers and tcon.
The routing for mixer0 is through tcon0 and connected to
LVDS/RGB/MIPI-DSI controller.
Signed-off-by: Parthiban Nallathambi
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 5eccf58f2e17..e012a6316bba 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -436,6 +436,7 @@ static const struct of_device_id sun4i_drv_of_table[] = {
{ .compatible = "allwinner,sun9i-a80-display-engine" },
{ .compatible = "allwinner,sun20i-d1-display-engine" },
{ .compatible = "allwinner,sun50i-a64-display-engine" },
+ { .compatible = "allwinner,sun50i-a100-display-engine" },
{ .compatible = "allwinner,sun50i-h6-display-engine" },
{ }
};
--
2.39.5
[PATCH RESEND 08/22] dt-bindings: arm: sunxi: document Szbaijie A133 helper board
Szbaijie Baijie Technology A133 helper board is an evaluation board of their A133-Core SoM. Add its compatible (with the SoM compatible) to the sunxi board DT binding file. Signed-off-by: Parthiban Nallathambi --- Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 046536d02706..eb19f8b1fe68 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -891,6 +891,12 @@ properties: - const: allwinner,sl631 - const: allwinner,sun8i-v3 + - description: Szbaijie A133 Helper board +items: + - const: szbaijie,helper-a133 + - const: szbaijie,helper-a133-core + - const: allwinner,sun50i-a133 + - description: Tanix TX1 items: - const: oranth,tanix-tx1 -- 2.39.5
[PATCH RESEND 16/22] clk: sunxi-ng: sun8i-de2: Add support for a100/a133
Display clock uses 1 mixer without rotation support is same
as v3s. There is also a hidden independent display engine
with independent tcon_top available in A100/A133 bin (based
on vendor BSP).
Add new compatible for A100/A133 to accommodate the future changes
for the independent DE.
Signed-off-by: Parthiban Nallathambi
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 3e28c32050e0..067820ab704d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -342,6 +342,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
.compatible = "allwinner,sun50i-a64-de2-clk",
.data = &sun50i_a64_de2_clk_desc,
},
+ {
+ .compatible = "allwinner,sun50i-a100-de2-clk",
+ .data = &sun8i_v3s_de2_clk_desc,
+ },
{
.compatible = "allwinner,sun50i-h5-de2-clk",
.data = &sun50i_h5_de2_clk_desc,
--
2.39.5
