[PATCH 0/5] Add display support for Qualcomm SA8775P platform
Add support for mdss and dpu driver on Qualcomm SA8775P platform. --- This series depends on following series: https://lore.kernel.org/all/20240816-sa8775p-mm-v3-v1-0-77d53c3c0...@quicinc.com/ --- Mahadevan (5): dt-bindings: display/msm: Document MDSS on SA8775P dt-bindings: display/msm: Document the DPU for SA8775P drm/msm: mdss: Add SA8775P support drm/msm/dpu: Add SA8775P support arm64: dts: qcom: sa8775p: add display dt nodes .../display/msm/qcom,sa8775p-dpu.yaml | 120 + .../display/msm/qcom,sa8775p-mdss.yaml| 225 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 85 +++ .../msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 485 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 3 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +- drivers/gpu/drm/msm/msm_mdss.c| 10 + 8 files changed, 931 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sa8775p-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h -- 2.34.1
[PATCH 3/5] drm/msm: mdss: Add SA8775P support
Add support for MDSS on SA8775P.
Signed-off-by: Mahadevan
---
drivers/gpu/drm/msm/msm_mdss.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index faa88fd6eb4d..272207573dbb 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -684,6 +684,15 @@ static const struct msm_mdss_data sm8350_data = {
.reg_bus_bw = 74000,
};
+static const struct msm_mdss_data sa8775p_data = {
+ .ubwc_enc_version = UBWC_4_0,
+ .ubwc_dec_version = UBWC_4_0,
+ .ubwc_swizzle = 4,
+ .ubwc_static = 1,
+ .highest_bank_bit = 0,
+ .macrotile_mode = 1,
+};
+
static const struct msm_mdss_data sm8550_data = {
.ubwc_enc_version = UBWC_4_0,
.ubwc_dec_version = UBWC_4_3,
@@ -725,6 +734,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
{ .compatible = "qcom,sm8350-mdss", .data = &sm8350_data },
{ .compatible = "qcom,sm8450-mdss", .data = &sm8350_data },
+ { .compatible = "qcom,sa8775p-mdss", .data = &sa8775p_data },
{ .compatible = "qcom,sm8550-mdss", .data = &sm8550_data },
{ .compatible = "qcom,sm8650-mdss", .data = &sm8550_data},
{ .compatible = "qcom,x1e80100-mdss", .data = &x1e80100_data},
--
2.34.1
[PATCH 4/5] drm/msm/dpu: Add SA8775P support
Add definitions for the display hardware used on the
Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
.../msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 485 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 3 +-
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 3 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +-
4 files changed, 491 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
new file mode 100644
index ..14d65b5d4093
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
@@ -0,0 +1,485 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_8_4_SA8775P_H
+#define _DPU_8_4_SA8775P_H
+
+static const struct dpu_caps sa8775p_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 5120,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_mdp_cfg sa8775p_mdp = {
+ .name = "top_0",
+ .base = 0x0, .len = 0x494,
+ .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
+ [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
support */
+static const struct dpu_ctl_cfg sa8775p_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
+static const struct dpu_sspp_cfg sa8775p_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 8,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VI
[PATCH 1/5] dt-bindings: display/msm: Document MDSS on SA8775P
Document the MDSS hardware found on the Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
.../display/msm/qcom,sa8775p-mdss.yaml| 225 ++
1 file changed, 225 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
new file mode 100644
index ..85da693f1f6d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
@@ -0,0 +1,225 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SA87755P Display MDSS
+
+maintainers:
+ - Mahadevan
+
+description:
+ SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks
like
+ DPU display controller, DP interfaces and EDP etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sa8775p-mdss
+
+ clocks:
+items:
+ - description: Display AHB
+ - description: Display hf AXI
+ - description: Display core
+
+ iommus:
+maxItems: 1
+
+ interconnects:
+maxItems: 3
+
+ interconnect-names:
+maxItems: 3
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,sa8775p-dpu
+
+ "^displayport-controller@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+items:
+ - const: qcom,sa8775p-dp
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+#include
+
+mdss0: display-subsystem@ae0 {
+compatible = "qcom,sa8775p-mdss";
+reg = <0 0x0ae0 0 0x1000>;
+reg-names = "mdss";
+
+/* same path used twice */
+interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
+<&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>,
+<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+&config_noc SLAVE_DISPLAY_CFG
QCOM_ICC_TAG_ACTIVE_ONLY>;
+interconnect-names = "mdp0-mem",
+ "mdp1-mem",
+ "cpu-cfg";
+
+power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>;
+
+clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>;
+
+interrupts = ;
+interrupt-controller;
+#interrupt-cells = <1>;
+
+iommus = <&apps_smmu 0x1000 0x402>;
+
+#address-cells = <2>;
+#size-cells = <2>;
+ranges;
+
+status = "disabled";
+
+mdss_mdp: display-controller@ae01000 {
+compatible = "qcom,sa8775p-dpu";
+reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+operating-points-v2 = <&mdss0_mdp_opp_table>;
+power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+interrupt-parent = <&mdss0>;
+interrupts = <0>;
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+port@0 {
+reg = <0>;
+dpu_intf0_out: endpoint {
+ remote-endpoint = <&mdss0_dp0_in>;
+};
+};
+};
+
+mdss0_mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-37500 {
+opp-hz = /bits/ 64 <37500>;
+required-opps = <&rpmhpd_opp_svs
[PATCH 2/5] dt-bindings: display/msm: Document the DPU for SA8775P
Document the DPU for Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
.../display/msm/qcom,sa8775p-dpu.yaml | 120 ++
1 file changed, 120 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sa8775p-dpu.yaml
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-dpu.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-dpu.yaml
new file mode 100644
index ..4e1bf5ffa2ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-dpu.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SA8775P Display DPU
+
+maintainers:
+ - Mahadevan
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sa8775p-dpu
+
+ reg:
+items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+items:
+ - description: Display hf axi
+ - description: Display ahb
+ - description: Display lut
+ - description: Display core
+ - description: Display vsync
+
+ clock-names:
+items:
+ - const: bus
+ - const: iface
+ - const: lut
+ - const: core
+ - const: vsync
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+
+display-controller@ae01000 {
+compatible = "qcom,sa8775p-dpu";
+reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+operating-points-v2 = <&mdss0_mdp_opp_table>;
+power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+interrupt-parent = <&mdss0>;
+interrupts = <0>;
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+port@0 {
+reg = <0>;
+dpu_intf0_out: endpoint {
+remote-endpoint = <&mdss0_dp0_in>;
+};
+};
+};
+
+mdss0_mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-37500 {
+opp-hz = /bits/ 64 <37500>;
+required-opps = <&rpmhpd_opp_svs_l1>;
+};
+
+opp-5 {
+opp-hz = /bits/ 64 <5>;
+required-opps = <&rpmhpd_opp_nom>;
+};
+
+opp-57500 {
+opp-hz = /bits/ 64 <57500>;
+required-opps = <&rpmhpd_opp_turbo>;
+};
+
+opp-65000 {
+opp-hz = /bits/ 64 <65000>;
+required-opps = <&rpmhpd_opp_turbo_l1>;
+};
+};
+};
+...
--
2.34.1
[PATCH 5/5] arm64: dts: qcom: sa8775p: add display dt nodes
Add mdss and mdp DT nodes for SA8775P.
Signed-off-by: Mahadevan
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 85 +++
1 file changed, 85 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 67ba124d20f8..d5d8e02fdb29 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -2937,6 +2938,90 @@ camcc: clock-controller@ade {
#power-domain-cells = <1>;
};
+ mdss0: display-subsystem@ae0 {
+ compatible = "qcom,sa8775p-mdss";
+ reg = <0x0 0x0ae0 0x0 0x1000>;
+ reg-names = "mdss";
+
+ /* same path used twice */
+ interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt
SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_MDP1 0 &mc_virt
SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC
QCOM_ICC_TAG_ACTIVE_ONLY
+&config_noc SLAVE_DISPLAY_CFG
QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+"mdp1-mem",
+"cpu-cfg";
+
+ power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>;
+
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+<&gcc GCC_DISP_HF_AXI_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>;
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x1000 0x402>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss0_mdp: display-controller@ae01000 {
+ compatible = "qcom,sa8775p-dpu";
+ reg = <0x0 0x0ae01000 0x0 0x8f000>,
+ <0x0 0x0aeb 0x0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc0
MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc0
MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <1920>;
+
+ operating-points-v2 = <&mdss0_mdp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ interrupt-parent = <&mdss0>;
+ interrupts = <0>;
+
+ mdss0_mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-37500 {
+ opp-hz = /bits/ 64 <37500>;
+ required-opps =
<&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-5 {
+ opp-hz = /bits/ 64 <5>;
+ required-opps =
<&rpmhpd_opp_nom>;
+ };
+
+ opp-57500 {
+ opp-hz = /bits/ 64 <57500>;
+ required-opps =
<&rpmhpd_opp_turbo>;
+ };
+
+ opp-65000 {
+ opp-hz = /bits/ 64 <65000>;
+ required-opps =
<&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
+ };
+
dispcc0: clock-controller@af0 {
compatible = "qcom,sa8775p-dispcc0";
reg = <0x0 0x0af0 0x0 0x2>;
--
2.34.1
[PATCH v4 4/5] drm/msm/dpu: Add SA8775P support
Add definitions for the display hardware used on the
Qualcomm SA8775P platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Mahadevan
---
.../drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h| 485 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 +
4 files changed, 488 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
new file mode 100644
index
..907b4d7ceb470b0391d2bbbab3ce520efa2b3263
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
@@ -0,0 +1,485 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DPU_8_4_SA8775P_H
+#define _DPU_8_4_SA8775P_H
+
+static const struct dpu_caps sa8775p_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 5120,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_mdp_cfg sa8775p_mdp = {
+ .name = "top_0",
+ .base = 0x0, .len = 0x494,
+ .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
+ [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
support */
+static const struct dpu_ctl_cfg sa8775p_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
+static const struct dpu_sspp_cfg sa8775p_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 8,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG2,
+ }, {
+ .name = "sspp_3", .id = SSPP_V
[PATCH v4 5/5] arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU
Add devicetree changes to enable MDSS0 display-subsystem its
display-controller(DPU) for Qualcomm SA8775P platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Mahadevan
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 89 +++
1 file changed, 89 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index
8fd68a8aa916e6595134b470f87b18b509178a51..66bd5e1c82a426f93097dee63a69c03527f04b3e
100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -2937,6 +2938,94 @@ camcc: clock-controller@ade {
#power-domain-cells = <1>;
};
+ mdss0: display-subsystem@ae0 {
+ compatible = "qcom,sa8775p-mdss";
+ reg = <0x0 0x0ae0 0x0 0x1000>;
+ reg-names = "mdss";
+
+ /* same path used twice */
+ interconnects = <&mmss_noc MASTER_MDP0
QCOM_ICC_TAG_ACTIVE_ONLY
+&mc_virt SLAVE_EBI1
QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_MDP1
QCOM_ICC_TAG_ACTIVE_ONLY
+&mc_virt SLAVE_EBI1
QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&gem_noc MASTER_APPSS_PROC
QCOM_ICC_TAG_ACTIVE_ONLY
+&config_noc SLAVE_DISPLAY_CFG
QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+"mdp1-mem",
+"cpu-cfg";
+
+ resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>;
+
+ power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>;
+
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+<&gcc GCC_DISP_HF_AXI_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>;
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x1000 0x402>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss0_mdp: display-controller@ae01000 {
+ compatible = "qcom,sa8775p-dpu";
+ reg = <0x0 0x0ae01000 0x0 0x8f000>,
+ <0x0 0x0aeb 0x0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+<&dispcc0
MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc0
MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <1920>;
+
+ operating-points-v2 = <&mdss0_mdp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ interrupt-parent = <&mdss0>;
+ interrupts = <0>;
+
+ mdss0_mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-37500 {
+ opp-hz = /bits/ 64 <37500>;
+ required-opps =
<&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-5 {
+ opp-hz = /bits/ 64 <5>;
+ required-opps =
<&rpmhpd_opp_nom>;
+
[PATCH v4 0/5] Display enablement changes for Qualcomm SA8775P platform
This series introduces support to enable the Mobile Display Subsystem (MDSS) and Display Processing Unit (DPU) for the Qualcomm SA8775P target. It includes the addition of the hardware catalog, compatible string, relevant device tree changes, and their YAML bindings. --- In this series - PATCH 1: "dt-bindings: display/msm: Document MDSS on SA8775P" depends on dp binding documetion in this change: https://lore.kernel.org/all/20240923113150.24711-5-quic_mukho...@quicinc.com/ - PATCH 5: "arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU" depends on the clock enablement change: https://lore.kernel.org/all/20240816-sa8775p-mm-v3-v1-0-77d53c3c0...@quicinc.com/ --- [v4] - Removed new YAML added for sa8775p dpu dt-binding documention as it is similar to qcom,sm8650-dpu.yaml and added the compatible in same. [Krzysztof] [v3] -Edited copyright for catalog changes. [Dmitry] -Fix dt_binding_check tool errors(update reg address as address-cells and size-cells of root node one and maintain the same for child nodes of mdss, added additionalProperties in schema). [Rob, Bjorn, Krzysztof] -Add QCOM_ICC_TAG_ACTIVE_ONLY interconnect path tag to mdp0-mem and mdp1-mem path in devicetree. [Dmitry] -Update commit subject and message for DT change. [Dmitry] -Remove interconnect path tags from dt bindings. (ref sm8450-mdss yaml) [v2] - Updated cover letter subject and message. [Dmitry] - Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry] - Update bindings by fixing dt_binding_check tool errors (update includes in example), adding proper spacing and indentation in the binding example, droping unused labels, droping status disable, adding reset node. [Dmitry, Rob, Krzysztof] - Reorder compatible string of MDSS and DPU based on alphabetical order.[Dmitry] - add reg_bus_bw in msm_mdss_data. [Dmitry] - Fix indentation in the devicetree. [Dmitry] -- 2.34.1 --- Mahadevan (5): dt-bindings: display/msm: Document MDSS on SA8775P dt-bindings: display/msm: Document the DPU for SA8775P drm/msm: mdss: Add SA8775P support drm/msm/dpu: Add SA8775P support arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU .../bindings/display/msm/qcom,sa8775p-mdss.yaml| 241 ++ .../bindings/display/msm/qcom,sm8650-dpu.yaml | 1 + arch/arm64/boot/dts/qcom/sa8775p.dtsi | 89 .../drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h| 485 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 + drivers/gpu/drm/msm/msm_mdss.c | 11 + 8 files changed, 830 insertions(+) --- base-commit: e390603cfa79c860ed35e073f5fe77805b067a8e change-id: 20240930-patchv3_1-600cbc1549e8 Best regards, -- Mahadevan
[PATCH v4 1/5] dt-bindings: display/msm: Document MDSS on SA8775P
Document the MDSS hardware found on the Qualcomm SA8775P platform.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Mahadevan
---
.../bindings/display/msm/qcom,sa8775p-mdss.yaml| 241 +
1 file changed, 241 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
new file mode 100644
index
..37c04ae6876f873c2cddc51b5160b1f54e2b5118
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
@@ -0,0 +1,241 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SA87755P Display MDSS
+
+maintainers:
+ - Mahadevan
+
+description:
+ SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks
like
+ DPU display controller, DP interfaces and EDP etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sa8775p-mdss
+
+ clocks:
+items:
+ - description: Display AHB
+ - description: Display hf AXI
+ - description: Display core
+
+ iommus:
+maxItems: 1
+
+ interconnects:
+maxItems: 3
+
+ interconnect-names:
+maxItems: 3
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+ compatible:
+const: qcom,sa8775p-dpu
+
+ "^displayport-controller@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+ compatible:
+items:
+ - const: qcom,sa8775p-dp
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+#include
+
+display-subsystem@ae0 {
+compatible = "qcom,sa8775p-mdss";
+reg = <0x0ae0 0x1000>;
+reg-names = "mdss";
+
+interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
+<&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>,
+<&gem_noc MASTER_APPSS_PROC &config_noc
SLAVE_DISPLAY_CFG>;
+interconnect-names = "mdp0-mem",
+ "mdp1-mem",
+ "cpu-cfg";
+
+
+resets = <&dispcc_core_bcr>;
+power-domains = <&dispcc_gdsc>;
+
+clocks = <&dispcc_ahb_clk>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc_mdp_clk>;
+
+interrupts = ;
+interrupt-controller;
+#interrupt-cells = <1>;
+
+iommus = <&apps_smmu 0x1000 0x402>;
+
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+
+display-controller@ae01000 {
+compatible = "qcom,sa8775p-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc_ahb_clk>,
+ <&dispcc_mdp_lut_clk>,
+ <&dispcc_mdp_clk>,
+ <&dispcc_mdp_vsync_clk>;
+clock-names = "bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = <&dispcc_mdp_vsync_clk>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdss0_mdp_opp_table>;
+power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+interrupt-parent = <&mdss0>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf0_out: endpoint {
+ remote-endpoint = <&mdss0_dp0_in>;
+};
+};
+};
+
+mdss0_mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-37500 {
+opp-hz = /bits/ 64 <37500>;
+required-opps = <&rpmhpd_opp_svs_l1>;
+};
+
+opp-5 {
+opp-hz = /bits/ 64 <5>;
+required-opps = <&rpmhpd_opp_nom>;
+
[PATCH v4 2/5] dt-bindings: display/msm: Document the DPU for SA8775P
Document the DPU for Qualcomm SA8775P platform. Signed-off-by: Mahadevan --- Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml index c4087cc5abbdd44885a6755e1facda767a16f35d..01cf79bd754b491349c52c5aef49ba06e835d0bf 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml @@ -14,6 +14,7 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: enum: + - qcom,sa8775p-dpu - qcom,sm8650-dpu - qcom,x1e80100-dpu -- 2.34.1
[PATCH v4 3/5] drm/msm: mdss: Add SA8775P support
Add Mobile Display Subsystem (MDSS) support for the SA8775P platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Mahadevan
---
drivers/gpu/drm/msm/msm_mdss.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index
faa88fd6eb4d6aec383a242b66a2b5125c91b3bc..8f1d42a43bd02dd79acf222a3423d11ff3b3cba3
100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -573,6 +573,16 @@ static const struct msm_mdss_data qcm2290_data = {
.reg_bus_bw = 76800,
};
+static const struct msm_mdss_data sa8775p_data = {
+ .ubwc_enc_version = UBWC_4_0,
+ .ubwc_dec_version = UBWC_4_0,
+ .ubwc_swizzle = 4,
+ .ubwc_static = 1,
+ .highest_bank_bit = 0,
+ .macrotile_mode = 1,
+ .reg_bus_bw = 74000,
+};
+
static const struct msm_mdss_data sc7180_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
@@ -710,6 +720,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,mdss" },
{ .compatible = "qcom,msm8998-mdss", .data = &msm8998_data },
{ .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data },
+ { .compatible = "qcom,sa8775p-mdss", .data = &sa8775p_data },
{ .compatible = "qcom,sdm670-mdss", .data = &sdm670_data },
{ .compatible = "qcom,sdm845-mdss", .data = &sdm845_data },
{ .compatible = "qcom,sc7180-mdss", .data = &sc7180_data },
--
2.34.1
[PATCH v5 1/5] dt-bindings: display/msm: Document MDSS on SA8775P
Document the MDSS hardware found on the Qualcomm SA8775P platform.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Mahadevan
---
.../bindings/display/msm/qcom,sa8775p-mdss.yaml| 241 +
1 file changed, 241 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
new file mode 100644
index
..58f8a01f29c7aaa9dc943c232363075686c06a7c
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
@@ -0,0 +1,241 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SA87755P Display MDSS
+
+maintainers:
+ - Mahadevan
+
+description:
+ SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks
like
+ DPU display controller, DP interfaces and EDP etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sa8775p-mdss
+
+ clocks:
+items:
+ - description: Display AHB
+ - description: Display hf AXI
+ - description: Display core
+
+ iommus:
+maxItems: 1
+
+ interconnects:
+maxItems: 3
+
+ interconnect-names:
+maxItems: 3
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+ compatible:
+const: qcom,sa8775p-dpu
+
+ "^displayport-controller@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+ compatible:
+items:
+ - const: qcom,sa8775p-dp
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+#include
+
+display-subsystem@ae0 {
+compatible = "qcom,sa8775p-mdss";
+reg = <0x0ae0 0x1000>;
+reg-names = "mdss";
+
+interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
+<&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>,
+<&gem_noc MASTER_APPSS_PROC &config_noc
SLAVE_DISPLAY_CFG>;
+interconnect-names = "mdp0-mem",
+ "mdp1-mem",
+ "cpu-cfg";
+
+
+resets = <&dispcc_core_bcr>;
+power-domains = <&dispcc_gdsc>;
+
+clocks = <&dispcc_ahb_clk>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc_mdp_clk>;
+
+interrupts = ;
+interrupt-controller;
+#interrupt-cells = <1>;
+
+iommus = <&apps_smmu 0x1000 0x402>;
+
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+
+display-controller@ae01000 {
+compatible = "qcom,sa8775p-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc_ahb_clk>,
+ <&dispcc_mdp_lut_clk>,
+ <&dispcc_mdp_clk>,
+ <&dispcc_mdp_vsync_clk>;
+clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = <&dispcc_mdp_vsync_clk>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdss0_mdp_opp_table>;
+power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+interrupt-parent = <&mdss0>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf0_out: endpoint {
+ remote-endpoint = <&mdss0_dp0_in>;
+};
+};
+};
+
+mdss0_mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-37500 {
+opp-hz = /bits/ 64 <37500>;
+required-opps = <&rpmhpd_opp_svs_l1>;
+};
+
+opp-5 {
+opp-hz = /bits/ 64 <5>;
+required-opps = <&rpmhpd_opp_nom>;
+
[PATCH v5 2/5] dt-bindings: display/msm: Document the DPU for SA8775P
Document the DPU for Qualcomm SA8775P platform. Signed-off-by: Mahadevan --- Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml index c4087cc5abbdd44885a6755e1facda767a16f35d..01cf79bd754b491349c52c5aef49ba06e835d0bf 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml @@ -14,6 +14,7 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: enum: + - qcom,sa8775p-dpu - qcom,sm8650-dpu - qcom,x1e80100-dpu -- 2.34.1
[PATCH v5 3/5] drm/msm: mdss: Add SA8775P support
Add Mobile Display Subsystem (MDSS) support for the SA8775P platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Mahadevan
---
drivers/gpu/drm/msm/msm_mdss.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index
faa88fd6eb4d6aec383a242b66a2b5125c91b3bc..8f1d42a43bd02dd79acf222a3423d11ff3b3cba3
100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -573,6 +573,16 @@ static const struct msm_mdss_data qcm2290_data = {
.reg_bus_bw = 76800,
};
+static const struct msm_mdss_data sa8775p_data = {
+ .ubwc_enc_version = UBWC_4_0,
+ .ubwc_dec_version = UBWC_4_0,
+ .ubwc_swizzle = 4,
+ .ubwc_static = 1,
+ .highest_bank_bit = 0,
+ .macrotile_mode = 1,
+ .reg_bus_bw = 74000,
+};
+
static const struct msm_mdss_data sc7180_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
@@ -710,6 +720,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,mdss" },
{ .compatible = "qcom,msm8998-mdss", .data = &msm8998_data },
{ .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data },
+ { .compatible = "qcom,sa8775p-mdss", .data = &sa8775p_data },
{ .compatible = "qcom,sdm670-mdss", .data = &sdm670_data },
{ .compatible = "qcom,sdm845-mdss", .data = &sdm845_data },
{ .compatible = "qcom,sc7180-mdss", .data = &sc7180_data },
--
2.34.1
[PATCH v5 4/5] drm/msm/dpu: Add SA8775P support
Add definitions for the display hardware used on the
Qualcomm SA8775P platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Mahadevan
---
.../drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h| 485 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 +
4 files changed, 488 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
new file mode 100644
index
..907b4d7ceb470b0391d2bbbab3ce520efa2b3263
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
@@ -0,0 +1,485 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DPU_8_4_SA8775P_H
+#define _DPU_8_4_SA8775P_H
+
+static const struct dpu_caps sa8775p_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 5120,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_mdp_cfg sa8775p_mdp = {
+ .name = "top_0",
+ .base = 0x0, .len = 0x494,
+ .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
+ [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
support */
+static const struct dpu_ctl_cfg sa8775p_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
+static const struct dpu_sspp_cfg sa8775p_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 8,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG2,
+ }, {
+ .name = "sspp_3", .id = SSPP_V
[PATCH v4 1/5] dt-bindings: display/msm: Document MDSS on SA8775P
Document the MDSS hardware found on the Qualcomm SA8775P platform.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Mahadevan
---
.../bindings/display/msm/qcom,sa8775p-mdss.yaml| 241 +
1 file changed, 241 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
new file mode 100644
index
..58f8a01f29c7aaa9dc943c232363075686c06a7c
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
@@ -0,0 +1,241 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SA87755P Display MDSS
+
+maintainers:
+ - Mahadevan
+
+description:
+ SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks
like
+ DPU display controller, DP interfaces and EDP etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sa8775p-mdss
+
+ clocks:
+items:
+ - description: Display AHB
+ - description: Display hf AXI
+ - description: Display core
+
+ iommus:
+maxItems: 1
+
+ interconnects:
+maxItems: 3
+
+ interconnect-names:
+maxItems: 3
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+ compatible:
+const: qcom,sa8775p-dpu
+
+ "^displayport-controller@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+ compatible:
+items:
+ - const: qcom,sa8775p-dp
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+#include
+
+display-subsystem@ae0 {
+compatible = "qcom,sa8775p-mdss";
+reg = <0x0ae0 0x1000>;
+reg-names = "mdss";
+
+interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
+<&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>,
+<&gem_noc MASTER_APPSS_PROC &config_noc
SLAVE_DISPLAY_CFG>;
+interconnect-names = "mdp0-mem",
+ "mdp1-mem",
+ "cpu-cfg";
+
+
+resets = <&dispcc_core_bcr>;
+power-domains = <&dispcc_gdsc>;
+
+clocks = <&dispcc_ahb_clk>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc_mdp_clk>;
+
+interrupts = ;
+interrupt-controller;
+#interrupt-cells = <1>;
+
+iommus = <&apps_smmu 0x1000 0x402>;
+
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+
+display-controller@ae01000 {
+compatible = "qcom,sa8775p-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc_ahb_clk>,
+ <&dispcc_mdp_lut_clk>,
+ <&dispcc_mdp_clk>,
+ <&dispcc_mdp_vsync_clk>;
+clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = <&dispcc_mdp_vsync_clk>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdss0_mdp_opp_table>;
+power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+interrupt-parent = <&mdss0>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf0_out: endpoint {
+ remote-endpoint = <&mdss0_dp0_in>;
+};
+};
+};
+
+mdss0_mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-37500 {
+opp-hz = /bits/ 64 <37500>;
+required-opps = <&rpmhpd_opp_svs_l1>;
+};
+
+opp-5 {
+opp-hz = /bits/ 64 <5>;
+required-opps = <&rpmhpd_opp_nom>;
+
[PATCH v4 3/5] drm/msm: mdss: Add SA8775P support
Add Mobile Display Subsystem (MDSS) support for the SA8775P platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Mahadevan
---
drivers/gpu/drm/msm/msm_mdss.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index
faa88fd6eb4d6aec383a242b66a2b5125c91b3bc..8f1d42a43bd02dd79acf222a3423d11ff3b3cba3
100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -573,6 +573,16 @@ static const struct msm_mdss_data qcm2290_data = {
.reg_bus_bw = 76800,
};
+static const struct msm_mdss_data sa8775p_data = {
+ .ubwc_enc_version = UBWC_4_0,
+ .ubwc_dec_version = UBWC_4_0,
+ .ubwc_swizzle = 4,
+ .ubwc_static = 1,
+ .highest_bank_bit = 0,
+ .macrotile_mode = 1,
+ .reg_bus_bw = 74000,
+};
+
static const struct msm_mdss_data sc7180_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
@@ -710,6 +720,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,mdss" },
{ .compatible = "qcom,msm8998-mdss", .data = &msm8998_data },
{ .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data },
+ { .compatible = "qcom,sa8775p-mdss", .data = &sa8775p_data },
{ .compatible = "qcom,sdm670-mdss", .data = &sdm670_data },
{ .compatible = "qcom,sdm845-mdss", .data = &sdm845_data },
{ .compatible = "qcom,sc7180-mdss", .data = &sc7180_data },
--
2.34.1
[PATCH v4 2/5] dt-bindings: display/msm: Document the DPU for SA8775P
Document the DPU for Qualcomm SA8775P platform. Signed-off-by: Mahadevan --- Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml index c4087cc5abbdd44885a6755e1facda767a16f35d..01cf79bd754b491349c52c5aef49ba06e835d0bf 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml @@ -14,6 +14,7 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: enum: + - qcom,sa8775p-dpu - qcom,sm8650-dpu - qcom,x1e80100-dpu -- 2.34.1
[PATCH v4 0/5] Display enablement changes for Qualcomm SA8775P platform
This series introduces support to enable the Mobile Display Subsystem (MDSS) and Display Processing Unit (DPU) for the Qualcomm SA8775P target. It includes the addition of the hardware catalog, compatible string, relevant device tree changes, and their YAML bindings. --- In this series - PATCH 1: "dt-bindings: display/msm: Document MDSS on SA8775P" depends on dp binding documetion in this change: https://lore.kernel.org/all/20240923113150.24711-5-quic_mukho...@quicinc.com/ - PATCH 5: "arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU" depends on the clock enablement change: https://lore.kernel.org/all/20240816-sa8775p-mm-v3-v1-0-77d53c3c0...@quicinc.com/ --- [v5] - Update clock-name of display-controller in MDSS documentation to align with qcom,sm8650-dpu.yaml. [Rob] - Update power-domains of display-controller in DT to do proper voting on MMCX rail. [Internal Review] [v4] - Removed new YAML added for sa8775p dpu dt-binding documention as it is similar to qcom,sm8650-dpu.yaml and added the compatible in same. [Krzysztof] [v3] -Edited copyright for catalog changes. [Dmitry] -Fix dt_binding_check tool errors(update reg address as address-cells and size-cells of root node one and maintain the same for child nodes of mdss, added additionalProperties in schema). [Rob, Bjorn, Krzysztof] -Add QCOM_ICC_TAG_ACTIVE_ONLY interconnect path tag to mdp0-mem and mdp1-mem path in devicetree. [Dmitry] -Update commit subject and message for DT change. [Dmitry] -Remove interconnect path tags from dt bindings. (ref sm8450-mdss yaml) [v2] - Updated cover letter subject and message. [Dmitry] - Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry] - Update bindings by fixing dt_binding_check tool errors (update includes in example), adding proper spacing and indentation in the binding example, droping unused labels, droping status disable, adding reset node. [Dmitry, Rob, Krzysztof] - Reorder compatible string of MDSS and DPU based on alphabetical order.[Dmitry] - add reg_bus_bw in msm_mdss_data. [Dmitry] - Fix indentation in the devicetree. [Dmitry] -- 2.34.1 --- Mahadevan (5): dt-bindings: display/msm: Document MDSS on SA8775P dt-bindings: display/msm: Document the DPU for SA8775P drm/msm: mdss: Add SA8775P support drm/msm/dpu: Add SA8775P support arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU .../bindings/display/msm/qcom,sa8775p-mdss.yaml| 241 ++ .../bindings/display/msm/qcom,sm8650-dpu.yaml | 1 + arch/arm64/boot/dts/qcom/sa8775p.dtsi | 89 .../drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h| 485 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 + drivers/gpu/drm/msm/msm_mdss.c | 11 + 8 files changed, 830 insertions(+) --- base-commit: e390603cfa79c860ed35e073f5fe77805b067a8e change-id: 20240930-patchv3_1-600cbc1549e8 Best regards, -- Mahadevan
[PATCH v4 4/5] drm/msm/dpu: Add SA8775P support
Add definitions for the display hardware used on the
Qualcomm SA8775P platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Mahadevan
---
.../drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h| 485 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 +
4 files changed, 488 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
new file mode 100644
index
..907b4d7ceb470b0391d2bbbab3ce520efa2b3263
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
@@ -0,0 +1,485 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DPU_8_4_SA8775P_H
+#define _DPU_8_4_SA8775P_H
+
+static const struct dpu_caps sa8775p_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 5120,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_mdp_cfg sa8775p_mdp = {
+ .name = "top_0",
+ .base = 0x0, .len = 0x494,
+ .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
+ [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
support */
+static const struct dpu_ctl_cfg sa8775p_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
+static const struct dpu_sspp_cfg sa8775p_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 8,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG2,
+ }, {
+ .name = "sspp_3", .id = SSPP_V
[PATCH v4 5/5] arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU
Add devicetree changes to enable MDSS0 display-subsystem its
display-controller(DPU) for Qualcomm SA8775P platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Mahadevan
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 89 +++
1 file changed, 89 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index
8fd68a8aa916e6595134b470f87b18b509178a51..5f6b7b59ec707490b162649d0fd97f85b1489e45
100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -2937,6 +2938,94 @@ camcc: clock-controller@ade {
#power-domain-cells = <1>;
};
+ mdss0: display-subsystem@ae0 {
+ compatible = "qcom,sa8775p-mdss";
+ reg = <0x0 0x0ae0 0x0 0x1000>;
+ reg-names = "mdss";
+
+ /* same path used twice */
+ interconnects = <&mmss_noc MASTER_MDP0
QCOM_ICC_TAG_ACTIVE_ONLY
+&mc_virt SLAVE_EBI1
QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_MDP1
QCOM_ICC_TAG_ACTIVE_ONLY
+&mc_virt SLAVE_EBI1
QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&gem_noc MASTER_APPSS_PROC
QCOM_ICC_TAG_ACTIVE_ONLY
+&config_noc SLAVE_DISPLAY_CFG
QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+"mdp1-mem",
+"cpu-cfg";
+
+ resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>;
+
+ power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>;
+
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+<&gcc GCC_DISP_HF_AXI_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>;
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x1000 0x402>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss0_mdp: display-controller@ae01000 {
+ compatible = "qcom,sa8775p-dpu";
+ reg = <0x0 0x0ae01000 0x0 0x8f000>,
+ <0x0 0x0aeb 0x0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+<&dispcc0
MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc0
MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <1920>;
+
+ operating-points-v2 = <&mdss0_mdp_opp_table>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+
+ interrupt-parent = <&mdss0>;
+ interrupts = <0>;
+
+ mdss0_mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-37500 {
+ opp-hz = /bits/ 64 <37500>;
+ required-opps =
<&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-5 {
+ opp-hz = /bits/ 64 <5>;
+ required-opps =
<&rpmhpd_opp_nom>;
+
[PATCH v5 0/5] Display enablement changes for Qualcomm SA8775P platform
This series introduces support to enable the Mobile Display Subsystem (MDSS) and Display Processing Unit (DPU) for the Qualcomm SA8775P target. It includes the addition of the hardware catalog, compatible string, relevant device tree changes, and their YAML bindings. --- In this series - PATCH 1: "dt-bindings: display/msm: Document MDSS on SA8775P" depends on dp binding documetion in this change: https://lore.kernel.org/all/20240923113150.24711-5-quic_mukho...@quicinc.com/ - PATCH 5: "arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU" depends on the clock enablement change: https://lore.kernel.org/all/20240816-sa8775p-mm-v3-v1-0-77d53c3c0...@quicinc.com/ --- [v5] - Update clock-name of display-controller in MDSS documentation to align with qcom,sm8650-dpu.yaml. [Rob] - Update power-domains of display-controller in DT to do proper voting on MMCX rail. [Internal Review] [v4] - Removed new YAML added for sa8775p dpu dt-binding documention as it is similar to qcom,sm8650-dpu.yaml and added the compatible in same. [Krzysztof] [v3] -Edited copyright for catalog changes. [Dmitry] -Fix dt_binding_check tool errors(update reg address as address-cells and size-cells of root node one and maintain the same for child nodes of mdss, added additionalProperties in schema). [Rob, Bjorn, Krzysztof] -Add QCOM_ICC_TAG_ACTIVE_ONLY interconnect path tag to mdp0-mem and mdp1-mem path in devicetree. [Dmitry] -Update commit subject and message for DT change. [Dmitry] -Remove interconnect path tags from dt bindings. (ref sm8450-mdss yaml) [v2] - Updated cover letter subject and message. [Dmitry] - Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry] - Update bindings by fixing dt_binding_check tool errors (update includes in example), adding proper spacing and indentation in the binding example, droping unused labels, droping status disable, adding reset node. [Dmitry, Rob, Krzysztof] - Reorder compatible string of MDSS and DPU based on alphabetical order.[Dmitry] - add reg_bus_bw in msm_mdss_data. [Dmitry] - Fix indentation in the devicetree. [Dmitry] -- 2.34.1 --- --- Mahadevan (5): dt-bindings: display/msm: Document MDSS on SA8775P dt-bindings: display/msm: Document the DPU for SA8775P drm/msm: mdss: Add SA8775P support drm/msm/dpu: Add SA8775P support arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU .../bindings/display/msm/qcom,sa8775p-mdss.yaml| 241 ++ .../bindings/display/msm/qcom,sm8650-dpu.yaml | 1 + arch/arm64/boot/dts/qcom/sa8775p.dtsi | 89 .../drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h| 485 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 + drivers/gpu/drm/msm/msm_mdss.c | 11 + 8 files changed, 830 insertions(+) --- base-commit: e390603cfa79c860ed35e073f5fe77805b067a8e change-id: 20240930-patchv3_1-600cbc1549e8 Best regards, -- Mahadevan
[PATCH v5 5/5] arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU
Add devicetree changes to enable MDSS0 display-subsystem its
display-controller(DPU) for Qualcomm SA8775P platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Mahadevan
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 89 +++
1 file changed, 89 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index
8fd68a8aa916e6595134b470f87b18b509178a51..5f6b7b59ec707490b162649d0fd97f85b1489e45
100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -2937,6 +2938,94 @@ camcc: clock-controller@ade {
#power-domain-cells = <1>;
};
+ mdss0: display-subsystem@ae0 {
+ compatible = "qcom,sa8775p-mdss";
+ reg = <0x0 0x0ae0 0x0 0x1000>;
+ reg-names = "mdss";
+
+ /* same path used twice */
+ interconnects = <&mmss_noc MASTER_MDP0
QCOM_ICC_TAG_ACTIVE_ONLY
+&mc_virt SLAVE_EBI1
QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_MDP1
QCOM_ICC_TAG_ACTIVE_ONLY
+&mc_virt SLAVE_EBI1
QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&gem_noc MASTER_APPSS_PROC
QCOM_ICC_TAG_ACTIVE_ONLY
+&config_noc SLAVE_DISPLAY_CFG
QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+"mdp1-mem",
+"cpu-cfg";
+
+ resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>;
+
+ power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>;
+
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+<&gcc GCC_DISP_HF_AXI_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>;
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x1000 0x402>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss0_mdp: display-controller@ae01000 {
+ compatible = "qcom,sa8775p-dpu";
+ reg = <0x0 0x0ae01000 0x0 0x8f000>,
+ <0x0 0x0aeb 0x0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+<&dispcc0
MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc0
MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <1920>;
+
+ operating-points-v2 = <&mdss0_mdp_opp_table>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+
+ interrupt-parent = <&mdss0>;
+ interrupts = <0>;
+
+ mdss0_mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-37500 {
+ opp-hz = /bits/ 64 <37500>;
+ required-opps =
<&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-5 {
+ opp-hz = /bits/ 64 <5>;
+ required-opps =
<&rpmhpd_opp_nom>;
+
[PATCH v2 0/5] Display enablement changes for Qualcomm SA8775P platform
This series introduces support to enable the Mobile Display Subsystem (MDSS) and Display Processing Unit (DPU) for the Qualcomm SA8775P target. It includes the addition of the hardware catalog, compatible string, relevant device tree changes, and their YAML bindings. --- In this series PATCH 5: "arm64: dts: qcom: sa8775p: add display dt nodes" depends on the clock enablement change: https://lore.kernel.org/all/20240816-sa8775p-mm-v3-v1-0-77d53c3c0...@quicinc.com/ --- [v2] - Updated cover letter subject and message. [Dmitry] - Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry] - Update bindings by fixing dt_binding_check tool errors (update includes in example), adding proper spacing and indentation in the binding example, droping unused labels, droping status disable, adding reset node. [Dmitry, Rob, Krzysztof] - Reorder compatible string of MDSS and DPU based on alphabetical order.[Dmitry] - add reg_bus_bw in msm_mdss_data. [Dmitry] - Fix indentation in the devicetree. [Dmitry] --- Mahadevan (5): dt-bindings: display/msm: Document MDSS on SA8775P dt-bindings: display/msm: Document the DPU for SA8775P drm/msm: mdss: Add SA8775P support drm/msm/dpu: Add SA8775P support arm64: dts: qcom: sa8775p: add display dt nodes .../display/msm/qcom,sa8775p-dpu.yaml | 122 + .../display/msm/qcom,sa8775p-mdss.yaml| 239 + arch/arm64/boot/dts/qcom/sa8775p.dtsi | 87 .../msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 485 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 3 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +- drivers/gpu/drm/msm/msm_mdss.c| 11 + 8 files changed, 950 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sa8775p-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h -- 2.34.1
[PATCH v2 2/5] dt-bindings: display/msm: Document the DPU for SA8775P
Document the DPU for Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
[v2]
- Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry]
- Update bindings by fixing dt_binding_check tool errors (update includes in
example),
adding proper spacing and indentation in binding example. [Dmitry, Rob]
- Capitalize clock names in description. [Dmitry]
---
.../display/msm/qcom,sa8775p-dpu.yaml | 122 ++
1 file changed, 122 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sa8775p-dpu.yaml
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-dpu.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-dpu.yaml
new file mode 100644
index ..435e4c028bb8
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-dpu.yaml
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SA8775P Display DPU
+
+maintainers:
+ - Mahadevan
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sa8775p-dpu
+
+ reg:
+items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+items:
+ - description: Display hf AXI
+ - description: Display AHB
+ - description: Display lut
+ - description: Display core
+ - description: Display vsync
+
+ clock-names:
+items:
+ - const: bus
+ - const: iface
+ - const: lut
+ - const: core
+ - const: vsync
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+
+display-controller@ae01000 {
+compatible = "qcom,sa8775p-dpu";
+reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc_ahb_clk>,
+ <&dispcc_mdp_lut_clk>,
+ <&dispcc_mdp_clk>,
+ <&dispcc_vsync_clk>;
+clock-names = "bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = <&dispcc_vsync_clk>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdss0_mdp_opp_table>;
+power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+interrupt-parent = <&mdss0>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf0_out: endpoint {
+remote-endpoint = <&mdss0_dp0_in>;
+};
+};
+};
+
+mdss0_mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-37500 {
+opp-hz = /bits/ 64 <37500>;
+required-opps = <&rpmhpd_opp_svs_l1>;
+};
+
+opp-5 {
+opp-hz = /bits/ 64 <5>;
+required-opps = <&rpmhpd_opp_nom>;
+};
+
+opp-57500 {
+opp-hz = /bits/ 64 <57500>;
+required-opps = <&rpmhpd_opp_turbo>;
+};
+
+opp-65000 {
+opp-hz = /bits/ 64 <65000>;
+required-opps = <&rpmhpd_opp_turbo_l1>;
+};
+};
+};
+...
--
2.34.1
[PATCH v2 0/5] Display enablement changes for Qualcomm SA8775P platform
This series introduces support to enable the Mobile Display Subsystem (MDSS) and Display Processing Unit (DPU) for the Qualcomm SA8775P target. It includes the addition of the hardware catalog, compatible string, relevant device tree changes, and their YAML bindings. --- In this series PATCH 5: "arm64: dts: qcom: sa8775p: add display dt nodes" depends on the clock enablement change: https://lore.kernel.org/all/20240816-sa8775p-mm-v3-v1-0-77d53c3c0...@quicinc.com/ --- [v2] - Updated cover letter subject and message. [Dmitry] - Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry] - Update bindings by fixing dt_binding_check tool errors (update includes in example), adding proper spacing and indentation in the binding example, droping unused labels, droping status disable, adding reset node. [Dmitry, Rob, Krzysztof] - Reorder compatible string of MDSS and DPU based on alphabetical order.[Dmitry] - add reg_bus_bw in msm_mdss_data. [Dmitry] - Fix indentation in the devicetree. [Dmitry] --- Mahadevan (5): dt-bindings: display/msm: Document MDSS on SA8775P dt-bindings: display/msm: Document the DPU for SA8775P drm/msm: mdss: Add SA8775P support drm/msm/dpu: Add SA8775P support arm64: dts: qcom: sa8775p: add display dt nodes .../display/msm/qcom,sa8775p-dpu.yaml | 122 + .../display/msm/qcom,sa8775p-mdss.yaml| 239 + arch/arm64/boot/dts/qcom/sa8775p.dtsi | 87 .../msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 485 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 3 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +- drivers/gpu/drm/msm/msm_mdss.c| 11 + 8 files changed, 950 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sa8775p-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h -- 2.34.1
[PATCH v2 5/5] arm64: dts: qcom: sa8775p: add display dt nodes
Add mdss0 and mdp devicetree nodes for sa8775p target.
Signed-off-by: Mahadevan
---
This patch depends on the clock enablement change:
https://lore.kernel.org/all/20240816-sa8775p-mm-v3-v1-0-77d53c3c0...@quicinc.com/
---
[v2]
- Update commit message mentioning enablement of mdss0 only is done. [Dmitry]
- Add resets node and fix indentation. [Dmitry]
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 87 +++
1 file changed, 87 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 93be4683a31f..27ab1921c1f3 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -2937,6 +2938,92 @@ camcc: clock-controller@ade {
#power-domain-cells = <1>;
};
+ mdss0: display-subsystem@ae0 {
+ compatible = "qcom,sa8775p-mdss";
+ reg = <0x0 0x0ae0 0x0 0x1000>;
+ reg-names = "mdss";
+
+ /* same path used twice */
+ interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt
SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_MDP1 0 &mc_virt
SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC
QCOM_ICC_TAG_ACTIVE_ONLY
+&config_noc SLAVE_DISPLAY_CFG
QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+"mdp1-mem",
+"cpu-cfg";
+
+ resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>;
+
+ power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>;
+
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+<&gcc GCC_DISP_HF_AXI_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>;
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x1000 0x402>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss0_mdp: display-controller@ae01000 {
+ compatible = "qcom,sa8775p-dpu";
+ reg = <0x0 0x0ae01000 0x0 0x8f000>,
+ <0x0 0x0aeb 0x0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+<&dispcc0
MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc0
MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <1920>;
+
+ operating-points-v2 = <&mdss0_mdp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ interrupt-parent = <&mdss0>;
+ interrupts = <0>;
+
+ mdss0_mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-37500 {
+ opp-hz = /bits/ 64 <37500>;
+ required-opps =
<&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-5 {
+ opp-hz = /bits/ 64 <5>;
+ required-opps =
<&rpmhpd_opp_nom>;
+ };
+
+
[PATCH v2 3/5] drm/msm: mdss: Add SA8775P support
Add Mobile Display Subsystem (MDSS) support for the SA8775P platform.
Signed-off-by: Mahadevan
---
[v2]
- Update commit message. [Dmitry]
- Reorder compatible string of MDSS based on alphabetical order. [Dmitry]
- add reg_bus_bw in msm_mdss_data. [Dmitry]
---
drivers/gpu/drm/msm/msm_mdss.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index faa88fd6eb4d..8f1d42a43bd0 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -573,6 +573,16 @@ static const struct msm_mdss_data qcm2290_data = {
.reg_bus_bw = 76800,
};
+static const struct msm_mdss_data sa8775p_data = {
+ .ubwc_enc_version = UBWC_4_0,
+ .ubwc_dec_version = UBWC_4_0,
+ .ubwc_swizzle = 4,
+ .ubwc_static = 1,
+ .highest_bank_bit = 0,
+ .macrotile_mode = 1,
+ .reg_bus_bw = 74000,
+};
+
static const struct msm_mdss_data sc7180_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
@@ -710,6 +720,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,mdss" },
{ .compatible = "qcom,msm8998-mdss", .data = &msm8998_data },
{ .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data },
+ { .compatible = "qcom,sa8775p-mdss", .data = &sa8775p_data },
{ .compatible = "qcom,sdm670-mdss", .data = &sdm670_data },
{ .compatible = "qcom,sdm845-mdss", .data = &sdm845_data },
{ .compatible = "qcom,sc7180-mdss", .data = &sc7180_data },
--
2.34.1
[PATCH v2 4/5] drm/msm/dpu: Add SA8775P support
Add definitions for the display hardware used on the
Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
[v2]
- Reorder compatible string of DPU based on alphabetical order.[Dmitry]
---
.../msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 485 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 3 +-
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 3 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +-
4 files changed, 491 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
new file mode 100644
index ..14d65b5d4093
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
@@ -0,0 +1,485 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_8_4_SA8775P_H
+#define _DPU_8_4_SA8775P_H
+
+static const struct dpu_caps sa8775p_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 5120,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_mdp_cfg sa8775p_mdp = {
+ .name = "top_0",
+ .base = 0x0, .len = 0x494,
+ .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
+ [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
support */
+static const struct dpu_ctl_cfg sa8775p_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
+static const struct dpu_sspp_cfg sa8775p_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 8,
+ .t
[PATCH v2 1/5] dt-bindings: display/msm: Document MDSS on SA8775P
Document the MDSS hardware found on the Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
[v2]
- Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry]
- Update bindings by fixing dt_binding_check tool errors (update includes in
example),
adding proper spacing and indentation in binding example, dropping unused
labels,
dropping status disable, adding reset node. [Dmitry, Rob, Krzysztof]
---
.../display/msm/qcom,sa8775p-mdss.yaml| 239 ++
1 file changed, 239 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
new file mode 100644
index ..e610b66ffa9f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
@@ -0,0 +1,239 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SA87755P Display MDSS
+
+maintainers:
+ - Mahadevan
+
+description:
+ SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks
like
+ DPU display controller, DP interfaces and EDP etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sa8775p-mdss
+
+ clocks:
+items:
+ - description: Display AHB
+ - description: Display hf AXI
+ - description: Display core
+
+ iommus:
+maxItems: 1
+
+ interconnects:
+maxItems: 3
+
+ interconnect-names:
+maxItems: 3
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,sa8775p-dpu
+
+ "^displayport-controller@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+items:
+ - const: qcom,sa8775p-dp
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+#include
+
+display-subsystem@ae0 {
+compatible = "qcom,sa8775p-mdss";
+reg = <0 0x0ae0 0 0x1000>;
+reg-names = "mdss";
+
+/* same path used twice */
+interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
+<&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>,
+<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+&config_noc SLAVE_DISPLAY_CFG
QCOM_ICC_TAG_ACTIVE_ONLY>;
+interconnect-names = "mdp0-mem",
+ "mdp1-mem",
+ "cpu-cfg";
+
+
+resets = <&dispcc_core_bcr>;
+power-domains = <&dispcc_gdsc>;
+
+clocks = <&dispcc_ahb_clk>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc_mdp_clk>;
+
+interrupts = ;
+interrupt-controller;
+#interrupt-cells = <1>;
+
+iommus = <&apps_smmu 0x1000 0x402>;
+
+#address-cells = <2>;
+#size-cells = <2>;
+ranges;
+
+display-controller@ae01000 {
+compatible = "qcom,sa8775p-dpu";
+reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc_ahb_clk>,
+ <&dispcc_mdp_lut_clk>,
+ <&dispcc_mdp_clk>,
+ <&dispcc_mdp_vsync_clk>;
+clock-names = "bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = <&dispcc_mdp_vsync_clk>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdss0_mdp_opp_table>;
+power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+interrupt-parent = <&mdss0>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf0_out: endpoint {
+ remote-endpoint = <&mdss0_dp0_in>;
+};
+};
+};
+
+mdss0_mdp_opp_table: opp-table {
+compatible = "operating-point
Re: [PATCH v2 1/5] dt-bindings: display/msm: Document MDSS on SA8775P
On 9/26/2024 6:54 PM, Bjorn Andersson wrote:
On Thu, Sep 26, 2024 at 04:31:33PM +0530, Mahadevan wrote:
Document the MDSS hardware found on the Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
[v2]
- Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry]
- Update bindings by fixing dt_binding_check tool errors (update includes in
example),
adding proper spacing and indentation in binding example, dropping unused
labels,
dropping status disable, adding reset node. [Dmitry, Rob, Krzysztof]
No concerns with the changelog, but please adopt b4 (go/upstream has
instructions) for sending patches upstream.
Sure, will follow while posting next patch.
---
.../display/msm/qcom,sa8775p-mdss.yaml| 239 ++
1 file changed, 239 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
new file mode 100644
index ..e610b66ffa9f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
@@ -0,0 +1,239 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SA87755P Display MDSS
+
+maintainers:
+ - Mahadevan
Please use Firstname Lastname, if possible
My name has only First name, can I please go ahead with this.
+
+description:
+ SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks
like
+ DPU display controller, DP interfaces and EDP etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
[..]
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+#include
+
+display-subsystem@ae0 {
+compatible = "qcom,sa8775p-mdss";
+reg = <0 0x0ae0 0 0x1000>;
#address-cells and #size-cells are 1 in the example root node, so drop
the two 0 entries.
+reg-names = "mdss";
+
+/* same path used twice */
What do you mean? All three paths below are unique.
Yes all three are paths are unique, its same sm8450-mdss.
Will remove the comment /* same path used twice */.
+interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
+<&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>,
+<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+&config_noc SLAVE_DISPLAY_CFG
QCOM_ICC_TAG_ACTIVE_ONLY>;
+interconnect-names = "mdp0-mem",
+ "mdp1-mem",
+ "cpu-cfg";
+
+
Regards,
Bjorn
Thanks,
Mahadevan
Re: [PATCH v4 0/5] Display enablement changes for Qualcomm SA8775P platform
I apologize for the inconvenience caused by uploading the incorrect patch (v4). Kindly disregard it. On 10/19/2024 8:46 PM, Mahadevan wrote: This series introduces support to enable the Mobile Display Subsystem (MDSS) and Display Processing Unit (DPU) for the Qualcomm SA8775P target. It includes the addition of the hardware catalog, compatible string, relevant device tree changes, and their YAML bindings. --- In this series - PATCH 1: "dt-bindings: display/msm: Document MDSS on SA8775P" depends on dp binding documetion in this change: https://lore.kernel.org/all/20240923113150.24711-5-quic_mukho...@quicinc.com/ - PATCH 5: "arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU" depends on the clock enablement change: https://lore.kernel.org/all/20240816-sa8775p-mm-v3-v1-0-77d53c3c0...@quicinc.com/ --- [v5] - Update clock-name of display-controller in MDSS documentation to align with qcom,sm8650-dpu.yaml. [Rob] - Update power-domains of display-controller in DT to do proper voting on MMCX rail. [Internal Review] [v4] - Removed new YAML added for sa8775p dpu dt-binding documention as it is similar to qcom,sm8650-dpu.yaml and added the compatible in same. [Krzysztof] [v3] -Edited copyright for catalog changes. [Dmitry] -Fix dt_binding_check tool errors(update reg address as address-cells and size-cells of root node one and maintain the same for child nodes of mdss, added additionalProperties in schema). [Rob, Bjorn, Krzysztof] -Add QCOM_ICC_TAG_ACTIVE_ONLY interconnect path tag to mdp0-mem and mdp1-mem path in devicetree. [Dmitry] -Update commit subject and message for DT change. [Dmitry] -Remove interconnect path tags from dt bindings. (ref sm8450-mdss yaml) [v2] - Updated cover letter subject and message. [Dmitry] - Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry] - Update bindings by fixing dt_binding_check tool errors (update includes in example), adding proper spacing and indentation in the binding example, droping unused labels, droping status disable, adding reset node. [Dmitry, Rob, Krzysztof] - Reorder compatible string of MDSS and DPU based on alphabetical order.[Dmitry] - add reg_bus_bw in msm_mdss_data. [Dmitry] - Fix indentation in the devicetree. [Dmitry] -- 2.34.1 --- Mahadevan (5): dt-bindings: display/msm: Document MDSS on SA8775P dt-bindings: display/msm: Document the DPU for SA8775P drm/msm: mdss: Add SA8775P support drm/msm/dpu: Add SA8775P support arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU .../bindings/display/msm/qcom,sa8775p-mdss.yaml| 241 ++ .../bindings/display/msm/qcom,sm8650-dpu.yaml | 1 + arch/arm64/boot/dts/qcom/sa8775p.dtsi | 89 .../drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h| 485 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 + drivers/gpu/drm/msm/msm_mdss.c | 11 + 8 files changed, 830 insertions(+) --- base-commit: e390603cfa79c860ed35e073f5fe77805b067a8e change-id: 20240930-patchv3_1-600cbc1549e8 Best regards,
Re: [PATCH 4/5] drm/msm/dpu: Add SA8775P support
On 9/24/2024 4:42 PM, Mahadevan P wrote:
On 9/12/2024 1:34 PM, Dmitry Baryshkov wrote:
On Thu, Sep 12, 2024 at 12:44:36PM GMT, Mahadevan wrote:
Add definitions for the display hardware used on the
Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
.../msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 485
++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +-
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +-
4 files changed, 491 insertions(+), 3 deletions(-)
create mode 100644
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
new file mode 100644
index ..14d65b5d4093
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
@@ -0,0 +1,485 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights
reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights
reserved.
+ */
+
+#ifndef _DPU_8_4_SA8775P_H
+#define _DPU_8_4_SA8775P_H
+
+static const struct dpu_caps sa8775p_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 5120,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_mdp_cfg sa8775p_mdp = {
+ .name = "top_0",
+ .base = 0x0, .len = 0x494,
+ .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
+ [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper
ACTIVE_CTL support */
+static const struct dpu_ctl_cfg sa8775p_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
+static const struct dpu_sspp_cfg sa8775p_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 8,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG2,
+ }, {
+ .name = "sspp_3", .id = SSPP_VIG3,
+ .base = 0xa000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 12,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG3,
+ }, {
Re: [PATCH 4/5] drm/msm/dpu: Add SA8775P support
On 9/24/2024 5:46 PM, Dmitry Baryshkov wrote:
On Tue, Sep 24, 2024 at 04:42:02PM GMT, Mahadevan P wrote:
On 9/12/2024 1:34 PM, Dmitry Baryshkov wrote:
On Thu, Sep 12, 2024 at 12:44:36PM GMT, Mahadevan wrote:
Add definitions for the display hardware used on the
Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
.../msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 485 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 3 +-
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 3 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +-
4 files changed, 491 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
[...]
+static const struct dpu_intf_cfg sa8775p_intf[] = {
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x34000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x35000, .len = 0x300,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
+ }, {
+ .name = "intf_2", .id = INTF_2,
+ .base = 0x36000, .len = 0x300,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
+ }, {
+ .name = "intf_3", .id = INTF_3,
+ .base = 0x37000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_NONE,
+ .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for
DP MST */
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+ }, {
+ .name = "intf_4", .id = INTF_4,
+ .base = 0x38000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_1,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
+ }, {
Where is intf_5 ?
intf_5 of base address 0x39000 is not supported on this target.
Not supported by whom?
In sa8775p mdss architecture intf_5 is not present. So we are not adding
in SW too.
+ .name = "intf_6", .id = INTF_6,
+ .base = 0x3A000, .len = 0x280,
+ .features = INTF_SC7280_MASK,
+ .type = INTF_NONE,
+ .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for
DP MST */
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
+ }, {
[skipped]
@@ -1464,6 +1464,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
{ .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
{ .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, },
+ { .compatible = "qcom,sa8775p-dpu", .data = &dpu_sa8775p_cfg, },
Wrong sorting order
Sure will move below sm8650-dpu.
What makes you think that in a dictionary sa8775p comes after sm8650?
Will update according to alphabetical order in next patch.
{ .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, },
{ .compatible = "qcom,sm8650-dpu", .data = &dpu_sm8650_cfg, },
{ .compatible = "qcom,x1e80100-dpu", .data = &dpu_x1e80100_cfg, },
--
2.34.1
Re: [PATCH 4/5] drm/msm/dpu: Add SA8775P support
On 9/12/2024 1:34 PM, Dmitry Baryshkov wrote:
On Thu, Sep 12, 2024 at 12:44:36PM GMT, Mahadevan wrote:
Add definitions for the display hardware used on the
Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
.../msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 485 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 3 +-
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 3 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +-
4 files changed, 491 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
new file mode 100644
index ..14d65b5d4093
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
@@ -0,0 +1,485 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_8_4_SA8775P_H
+#define _DPU_8_4_SA8775P_H
+
+static const struct dpu_caps sa8775p_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 5120,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_mdp_cfg sa8775p_mdp = {
+ .name = "top_0",
+ .base = 0x0, .len = 0x494,
+ .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
+ [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
support */
+static const struct dpu_ctl_cfg sa8775p_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
+static const struct dpu_sspp_cfg sa8775p_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+
Re: [PATCH 0/5] Add display support for Qualcomm SA8775P platform
On 9/12/2024 1:26 PM, Dmitry Baryshkov wrote: On Thu, Sep 12, 2024 at 12:44:32PM GMT, Mahadevan wrote: Add support for mdss and dpu driver on Qualcomm SA8775P platform. --- This series depends on following series: https://lore.kernel.org/all/20240816-sa8775p-mm-v3-v1-0-77d53c3c0...@quicinc.com/ As such, it probably can not be merged before 6.14 (the mentioned series will go on 6.13, we usually don't do cross-tree merges into drm). Please rework the bindings to drop the dependency (it is possible, use fake nodes instead of using dispcc + ID). Then you can specify that only the DTS patch depends on the dispcc support, allowing driver changes to go in first. Can we use clocks = <&dummy_dispcc 0>, <&dummy_dispcc 1>, <&dummy_dispcc 2>; instead of clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; in dt bindings? --- Mahadevan (5): dt-bindings: display/msm: Document MDSS on SA8775P dt-bindings: display/msm: Document the DPU for SA8775P drm/msm: mdss: Add SA8775P support drm/msm/dpu: Add SA8775P support arm64: dts: qcom: sa8775p: add display dt nodes .../display/msm/qcom,sa8775p-dpu.yaml | 120 + .../display/msm/qcom,sa8775p-mdss.yaml| 225 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 85 +++ .../msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 485 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 3 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +- drivers/gpu/drm/msm/msm_mdss.c| 10 + 8 files changed, 931 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sa8775p-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h -- 2.34.1
Re: [PATCH v2 0/5] Display enablement changes for Qualcomm SA8775P platform
Sorry, Please ignore this thread/coverletter On 9/26/2024 4:33 PM, Mahadevan wrote: This series introduces support to enable the Mobile Display Subsystem (MDSS) and Display Processing Unit (DPU) for the Qualcomm SA8775P target. It includes the addition of the hardware catalog, compatible string, relevant device tree changes, and their YAML bindings. --- In this series PATCH 5: "arm64: dts: qcom: sa8775p: add display dt nodes" depends on the clock enablement change: https://lore.kernel.org/all/20240816-sa8775p-mm-v3-v1-0-77d53c3c0...@quicinc.com/ --- [v2] - Updated cover letter subject and message. [Dmitry] - Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry] - Update bindings by fixing dt_binding_check tool errors (update includes in example), adding proper spacing and indentation in the binding example, droping unused labels, droping status disable, adding reset node. [Dmitry, Rob, Krzysztof] - Reorder compatible string of MDSS and DPU based on alphabetical order.[Dmitry] - add reg_bus_bw in msm_mdss_data. [Dmitry] - Fix indentation in the devicetree. [Dmitry] --- Mahadevan (5): dt-bindings: display/msm: Document MDSS on SA8775P dt-bindings: display/msm: Document the DPU for SA8775P drm/msm: mdss: Add SA8775P support drm/msm/dpu: Add SA8775P support arm64: dts: qcom: sa8775p: add display dt nodes .../display/msm/qcom,sa8775p-dpu.yaml | 122 + .../display/msm/qcom,sa8775p-mdss.yaml| 239 + arch/arm64/boot/dts/qcom/sa8775p.dtsi | 87 .../msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 485 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 3 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +- drivers/gpu/drm/msm/msm_mdss.c| 11 + 8 files changed, 950 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sa8775p-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
Re: [PATCH v2 3/5] drm/msm: mdss: Add SA8775P support
On 9/26/2024 6:32 PM, Dmitry Baryshkov wrote:
On Thu, Sep 26, 2024 at 04:31:35PM GMT, Mahadevan wrote:
Add Mobile Display Subsystem (MDSS) support for the SA8775P platform.
Signed-off-by: Mahadevan
---
[v2]
- Update commit message. [Dmitry]
- Reorder compatible string of MDSS based on alphabetical order. [Dmitry]
- add reg_bus_bw in msm_mdss_data. [Dmitry]
---
drivers/gpu/drm/msm/msm_mdss.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index faa88fd6eb4d..8f1d42a43bd0 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -573,6 +573,16 @@ static const struct msm_mdss_data qcm2290_data = {
.reg_bus_bw = 76800,
};
+static const struct msm_mdss_data sa8775p_data = {
+ .ubwc_enc_version = UBWC_4_0,
+ .ubwc_dec_version = UBWC_4_0,
Just 4.0 or 4.3?
UBWC version has to be 4.0 as per UBWC reference document of sa8775p.
+ .ubwc_swizzle = 4,
+ .ubwc_static = 1,
+ .highest_bank_bit = 0,
+ .macrotile_mode = 1,
+ .reg_bus_bw = 74000,
+};
+
static const struct msm_mdss_data sc7180_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
@@ -710,6 +720,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,mdss" },
{ .compatible = "qcom,msm8998-mdss", .data = &msm8998_data },
{ .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data },
+ { .compatible = "qcom,sa8775p-mdss", .data = &sa8775p_data },
{ .compatible = "qcom,sdm670-mdss", .data = &sdm670_data },
{ .compatible = "qcom,sdm845-mdss", .data = &sdm845_data },
{ .compatible = "qcom,sc7180-mdss", .data = &sc7180_data },
--
2.34.1
Re: [PATCH v2 4/5] drm/msm/dpu: Add SA8775P support
On 9/26/2024 6:39 PM, Dmitry Baryshkov wrote:
On Thu, Sep 26, 2024 at 04:31:36PM GMT, Mahadevan wrote:
Add definitions for the display hardware used on the
Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
Reviewed-by: Dmitry Baryshkov
Minor nit below.
[v2]
- Reorder compatible string of DPU based on alphabetical order.[Dmitry]
---
.../msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 485 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 3 +-
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 3 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +-
4 files changed, 491 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
new file mode 100644
index ..14d65b5d4093
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
@@ -0,0 +1,485 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
What exactly is copyrighted by LF?
LF copyright is not needed.
Thanks for pointing out the copyrights in other files too. Will update
in subsequent patch.
+ */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index dcb4fd85e73b..6f60fff2c9a6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights
reserved.
+ * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights
reserved.
I am not a lawyer, but I don't think a single #include is copyrightable.
Neither are single data lines in other files.
*/
#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
@@ -699,6 +699,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
#include "catalog/dpu_8_0_sc8280xp.h"
#include "catalog/dpu_8_1_sm8450.h"
+#include "catalog/dpu_8_4_sa8775p.h"
#include "catalog/dpu_9_0_sm8550.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 37e18e820a20..cff16dcf277f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights
reserved.
+ * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights
reserved.
* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
*/
@@ -850,6 +850,7 @@ extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg;
extern const struct dpu_mdss_cfg dpu_sm8450_cfg;
+extern const struct dpu_mdss_cfg dpu_sa8775p_cfg;
extern const struct dpu_mdss_cfg dpu_sm8550_cfg;
extern const struct dpu_mdss_cfg dpu_sm8650_cfg;
extern const struct dpu_mdss_cfg dpu_x1e80100_cfg;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 9bcae53c4f45..16a0b417435e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -2,7 +2,7 @@
/*
* Copyright (C) 2013 Red Hat
* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights
reserved.
*
* Author: Rob Clark
*/
@@ -1447,6 +1447,7 @@ static const struct dev_pm_ops dpu_pm_ops = {
static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, },
{ .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, },
+ { .compatible = "qcom,sa8775p-dpu", .data = &dpu_sa8775p_cfg, },
{ .compatible = "qcom,sdm630-mdp5", .data = &dpu_sdm630_cfg, },
{ .compatible = "qcom,sdm660-mdp5", .data = &dpu_sdm660_cfg, },
{ .compatible = "qcom,sdm670-dpu", .data = &dpu_sdm670_cfg, },
--
2.34.1
Re: [PATCH 5/5] arm64: dts: qcom: sa8775p: add display dt nodes
On 9/12/2024 1:30 PM, Dmitry Baryshkov wrote:
On Thu, Sep 12, 2024 at 12:44:37PM GMT, Mahadevan wrote:
Add mdss and mdp DT nodes for SA8775P.
Signed-off-by: Mahadevan
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 85 +++
1 file changed, 85 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 67ba124d20f8..d5d8e02fdb29 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -2937,6 +2938,90 @@ camcc: clock-controller@ade {
#power-domain-cells = <1>;
};
+ mdss0: display-subsystem@ae0 {
Is there going to be mdss1?
Currently we don't have plan to enable mdss1. Do we need to rename label
to just "mdss" in that case?
+ compatible = "qcom,sa8775p-mdss";
+ reg = <0x0 0x0ae0 0x0 0x1000>;
+ reg-names = "mdss";
+
+ /* same path used twice */
+ interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt
SLAVE_EBI1 0>,
+ <&mmss_noc MASTER_MDP1 0 &mc_virt
SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC
QCOM_ICC_TAG_ACTIVE_ONLY
+&config_noc SLAVE_DISPLAY_CFG
QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+"mdp1-mem",
+"cpu-cfg";
+
+ power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>;
+
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+<&gcc GCC_DISP_HF_AXI_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>;
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x1000 0x402>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss0_mdp: display-controller@ae01000 {
+ compatible = "qcom,sa8775p-dpu";
+ reg = <0x0 0x0ae01000 0x0 0x8f000>,
+ <0x0 0x0aeb 0x0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc0
MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
Wrong indentation
Sure will correct.
+ clock-names = "bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc0
MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <1920>;
+
+ operating-points-v2 = <&mdss0_mdp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ interrupt-parent = <&mdss0>;
+ interrupts = <0>;
+
+ mdss0_mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-37500 {
+ opp-hz = /bits/ 64 <37500>;
+ required-opps =
<&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-5 {
+ opp-hz = /bits/ 64 <5>;
+ required-opps =
<&rpmhpd_opp_nom>;
+ };
+
+ opp-57500 {
Re: [PATCH v3 1/5] dt-bindings: display/msm: Document MDSS on SA8775P
On 10/3/2024 1:23 PM, Krzysztof Kozlowski wrote: On Tue, Oct 01, 2024 at 12:11:36PM +0530, Mahadevan wrote: +patternProperties: + "^display-controller@[0-9a-f]+$": +type: object +additionalProperties: true + +properties: + compatible: +const: qcom,sa8775p-dpu + + "^displayport-controller@[0-9a-f]+$": +type: object +additionalProperties: true + +properties: + compatible: +items: + - const: qcom,sa8775p-dp Where is this binding? The schema is incomplete. This binding is added as part of following change. https://lore.kernel.org/all/20240923113150.24711-5-quic_mukho...@quicinc.com/ I will mention the same in cover letter/commit message of subsequent patch. Best regards, Krzysztof Thanks, Mahadevan
[PATCH v3 5/5] arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU
From: Mahadevan
Add devicetree changes to enable MDSS0 display-subsystem its
display-controller(DPU) for Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 89 +++
1 file changed, 89 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index
8fd68a8aa916e6595134b470f87b18b509178a51..66bd5e1c82a426f93097dee63a69c03527f04b3e
100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -2937,6 +2938,94 @@ camcc: clock-controller@ade {
#power-domain-cells = <1>;
};
+ mdss0: display-subsystem@ae0 {
+ compatible = "qcom,sa8775p-mdss";
+ reg = <0x0 0x0ae0 0x0 0x1000>;
+ reg-names = "mdss";
+
+ /* same path used twice */
+ interconnects = <&mmss_noc MASTER_MDP0
QCOM_ICC_TAG_ACTIVE_ONLY
+&mc_virt SLAVE_EBI1
QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_MDP1
QCOM_ICC_TAG_ACTIVE_ONLY
+&mc_virt SLAVE_EBI1
QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&gem_noc MASTER_APPSS_PROC
QCOM_ICC_TAG_ACTIVE_ONLY
+&config_noc SLAVE_DISPLAY_CFG
QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+"mdp1-mem",
+"cpu-cfg";
+
+ resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>;
+
+ power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>;
+
+ clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+<&gcc GCC_DISP_HF_AXI_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>;
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x1000 0x402>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss0_mdp: display-controller@ae01000 {
+ compatible = "qcom,sa8775p-dpu";
+ reg = <0x0 0x0ae01000 0x0 0x8f000>,
+ <0x0 0x0aeb 0x0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+<&dispcc0
MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
+<&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc0
MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <1920>;
+
+ operating-points-v2 = <&mdss0_mdp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ interrupt-parent = <&mdss0>;
+ interrupts = <0>;
+
+ mdss0_mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-37500 {
+ opp-hz = /bits/ 64 <37500>;
+ required-opps =
<&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-5 {
+ opp-hz = /bits/ 64 <5>;
+ required-opps =
<&rpmhpd_opp_nom>;
+
[PATCH v3 3/5] drm/msm: mdss: Add SA8775P support
From: Mahadevan
Add Mobile Display Subsystem (MDSS) support for the SA8775P platform.
Signed-off-by: Mahadevan
---
drivers/gpu/drm/msm/msm_mdss.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index
faa88fd6eb4d6aec383a242b66a2b5125c91b3bc..8f1d42a43bd02dd79acf222a3423d11ff3b3cba3
100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -573,6 +573,16 @@ static const struct msm_mdss_data qcm2290_data = {
.reg_bus_bw = 76800,
};
+static const struct msm_mdss_data sa8775p_data = {
+ .ubwc_enc_version = UBWC_4_0,
+ .ubwc_dec_version = UBWC_4_0,
+ .ubwc_swizzle = 4,
+ .ubwc_static = 1,
+ .highest_bank_bit = 0,
+ .macrotile_mode = 1,
+ .reg_bus_bw = 74000,
+};
+
static const struct msm_mdss_data sc7180_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
@@ -710,6 +720,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,mdss" },
{ .compatible = "qcom,msm8998-mdss", .data = &msm8998_data },
{ .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data },
+ { .compatible = "qcom,sa8775p-mdss", .data = &sa8775p_data },
{ .compatible = "qcom,sdm670-mdss", .data = &sdm670_data },
{ .compatible = "qcom,sdm845-mdss", .data = &sdm845_data },
{ .compatible = "qcom,sc7180-mdss", .data = &sc7180_data },
--
2.34.1
[PATCH v3 4/5] drm/msm/dpu: Add SA8775P support
From: Mahadevan
Add definitions for the display hardware used on the
Qualcomm SA8775P platform.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Mahadevan
---
.../drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h| 485 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 +
4 files changed, 488 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
new file mode 100644
index
..907b4d7ceb470b0391d2bbbab3ce520efa2b3263
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
@@ -0,0 +1,485 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DPU_8_4_SA8775P_H
+#define _DPU_8_4_SA8775P_H
+
+static const struct dpu_caps sa8775p_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 5120,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_mdp_cfg sa8775p_mdp = {
+ .name = "top_0",
+ .base = 0x0, .len = 0x494,
+ .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
+ [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL
support */
+static const struct dpu_ctl_cfg sa8775p_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ }, {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ }, {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
+static const struct dpu_sspp_cfg sa8775p_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG0,
+ }, {
+ .name = "sspp_1", .id = SSPP_VIG1,
+ .base = 0x6000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 4,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG1,
+ }, {
+ .name = "sspp_2", .id = SSPP_VIG2,
+ .base = 0x8000, .len = 0x32c,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_1,
+ .xin_id = 8,
+ .type = SSPP_TYPE_VIG,
+ .clk_ctrl = DPU_CLK_CTRL_VIG2,
+ }, {
+ .name = "ssp
[PATCH v3 2/5] dt-bindings: display/msm: Document the DPU for SA8775P
From: Mahadevan
Document the DPU for Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
.../bindings/display/msm/qcom,sa8775p-dpu.yaml | 122 +
1 file changed, 122 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-dpu.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-dpu.yaml
new file mode 100644
index
..fda88bdbd04214e06255e105eae582ff926d72e9
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-dpu.yaml
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SA8775P Display DPU
+
+maintainers:
+ - Mahadevan
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sa8775p-dpu
+
+ reg:
+items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+items:
+ - description: Display hf AXI
+ - description: Display AHB
+ - description: Display lut
+ - description: Display core
+ - description: Display vsync
+
+ clock-names:
+items:
+ - const: bus
+ - const: iface
+ - const: lut
+ - const: core
+ - const: vsync
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+
+display-controller@ae01000 {
+compatible = "qcom,sa8775p-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc_ahb_clk>,
+ <&dispcc_mdp_lut_clk>,
+ <&dispcc_mdp_clk>,
+ <&dispcc_vsync_clk>;
+clock-names = "bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = <&dispcc_vsync_clk>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdss0_mdp_opp_table>;
+power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+interrupt-parent = <&mdss0>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf0_out: endpoint {
+remote-endpoint = <&mdss0_dp0_in>;
+};
+};
+};
+
+mdss0_mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-37500 {
+opp-hz = /bits/ 64 <37500>;
+required-opps = <&rpmhpd_opp_svs_l1>;
+};
+
+opp-5 {
+opp-hz = /bits/ 64 <5>;
+required-opps = <&rpmhpd_opp_nom>;
+};
+
+opp-57500 {
+opp-hz = /bits/ 64 <57500>;
+required-opps = <&rpmhpd_opp_turbo>;
+};
+
+opp-65000 {
+opp-hz = /bits/ 64 <65000>;
+required-opps = <&rpmhpd_opp_turbo_l1>;
+};
+};
+};
+...
--
2.34.1
[PATCH v3 0/5] Display enablement changes for Qualcomm SA8775P platform
This series introduces support to enable the Mobile Display Subsystem (MDSS) and Display Processing Unit (DPU) for the Qualcomm SA8775P target. It includes the addition of the hardware catalog, compatible string, relevant device tree changes, and their YAML bindings. --- In this series PATCH 5: "arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU" depends on the clock enablement change: https://lore.kernel.org/all/20240816-sa8775p-mm-v3-v1-0-77d53c3c0...@quicinc.com/ --- [v3] -Edited copyright for catalog changes. [Dmitry] -Fix dt_binding_check tool errors(update reg address as address-cells and size-cells of root node one and maintain the same for child nodes of mdss, added additionalProperties in schema). [Rob, Bjorn, Krzysztof] -Add QCOM_ICC_TAG_ACTIVE_ONLY interconnect path tag to mdp0-mem and mdp1-mem path in devicetree. [Dmitry] -Update commit subject and message for DT change. [Dmitry] -Remove interconnect path tags from dt bindings. (ref sm8450-mdss yaml) [v2] - Updated cover letter subject and message. [Dmitry] - Use fake DISPCC nodes to avoid clock dependencies in dt-bindings. [Dmitry] - Update bindings by fixing dt_binding_check tool errors (update includes in example), adding proper spacing and indentation in the binding example, droping unused labels, droping status disable, adding reset node. [Dmitry, Rob, Krzysztof] - Reorder compatible string of MDSS and DPU based on alphabetical order.[Dmitry] - add reg_bus_bw in msm_mdss_data. [Dmitry] - Fix indentation in the devicetree. [Dmitry] -- 2.34.1 --- Mahadevan (5): dt-bindings: display/msm: Document MDSS on SA8775P dt-bindings: display/msm: Document the DPU for SA8775P drm/msm: mdss: Add SA8775P support drm/msm/dpu: Add SA8775P support arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU .../bindings/display/msm/qcom,sa8775p-dpu.yaml | 122 ++ .../bindings/display/msm/qcom,sa8775p-mdss.yaml| 241 ++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 89 .../drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h| 485 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 1 + drivers/gpu/drm/msm/msm_mdss.c | 11 + 8 files changed, 951 insertions(+) --- base-commit: e390603cfa79c860ed35e073f5fe77805b067a8e change-id: 20240930-patchv3_1-600cbc1549e8 Best regards, -- Mahadevan
[PATCH v3 1/5] dt-bindings: display/msm: Document MDSS on SA8775P
From: Mahadevan
Document the MDSS hardware found on the Qualcomm SA8775P platform.
Signed-off-by: Mahadevan
---
.../bindings/display/msm/qcom,sa8775p-mdss.yaml| 241 +
1 file changed, 241 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
new file mode 100644
index
..37c04ae6876f873c2cddc51b5160b1f54e2b5118
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
@@ -0,0 +1,241 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SA87755P Display MDSS
+
+maintainers:
+ - Mahadevan
+
+description:
+ SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks
like
+ DPU display controller, DP interfaces and EDP etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sa8775p-mdss
+
+ clocks:
+items:
+ - description: Display AHB
+ - description: Display hf AXI
+ - description: Display core
+
+ iommus:
+maxItems: 1
+
+ interconnects:
+maxItems: 3
+
+ interconnect-names:
+maxItems: 3
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+ compatible:
+const: qcom,sa8775p-dpu
+
+ "^displayport-controller@[0-9a-f]+$":
+type: object
+additionalProperties: true
+
+properties:
+ compatible:
+items:
+ - const: qcom,sa8775p-dp
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+#include
+
+display-subsystem@ae0 {
+compatible = "qcom,sa8775p-mdss";
+reg = <0x0ae0 0x1000>;
+reg-names = "mdss";
+
+interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
+<&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>,
+<&gem_noc MASTER_APPSS_PROC &config_noc
SLAVE_DISPLAY_CFG>;
+interconnect-names = "mdp0-mem",
+ "mdp1-mem",
+ "cpu-cfg";
+
+
+resets = <&dispcc_core_bcr>;
+power-domains = <&dispcc_gdsc>;
+
+clocks = <&dispcc_ahb_clk>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc_mdp_clk>;
+
+interrupts = ;
+interrupt-controller;
+#interrupt-cells = <1>;
+
+iommus = <&apps_smmu 0x1000 0x402>;
+
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+
+display-controller@ae01000 {
+compatible = "qcom,sa8775p-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc_ahb_clk>,
+ <&dispcc_mdp_lut_clk>,
+ <&dispcc_mdp_clk>,
+ <&dispcc_mdp_vsync_clk>;
+clock-names = "bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = <&dispcc_mdp_vsync_clk>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <&mdss0_mdp_opp_table>;
+power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+interrupt-parent = <&mdss0>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf0_out: endpoint {
+ remote-endpoint = <&mdss0_dp0_in>;
+};
+};
+};
+
+mdss0_mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-37500 {
+opp-hz = /bits/ 64 <37500>;
+required-opps = <&rpmhpd_opp_svs_l1>;
+};
+
+opp-5 {
+opp-hz = /bits/ 64 <5>;
+required-opps = <&rpmhpd_opp_nom>;
+};
+
+
