[PATCH] drm/panfrost: devfreq: Don't display error for EPROBE_DEFER
From: Chris Morgan
Set a condition for the message of "Couldn't set OPP regulators" to not
display if the error code is EPROBE_DEFER. Note that I used an if
statement to capture the condition instead of the dev_err_probe
function because I didn't want to change the DRM_DEV_ERROR usage.
Signed-off-by: Chris Morgan
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index 3644652f726f..194af7f607a6 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -106,7 +106,8 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
if (ret) {
/* Continue if the optional regulator is missing */
if (ret != -ENODEV) {
- DRM_DEV_ERROR(dev, "Couldn't set OPP regulators\n");
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "Couldn't set OPP
regulators\n");
return ret;
}
}
--
2.25.1
[PATCH] drm/panel: add rotation support for Elida KD35T133 panels
Update the panel to allow setting the rotation value in device tree.
Tested on an Odroid Go Advance, where the panel is by default rotated 270
degrees.
Signed-off-by: Chris Morgan
---
drivers/gpu/drm/panel/panel-elida-kd35t133.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-elida-kd35t133.c
b/drivers/gpu/drm/panel/panel-elida-kd35t133.c
index bc36aa3c1123..d8534406d1ef 100644
--- a/drivers/gpu/drm/panel/panel-elida-kd35t133.c
+++ b/drivers/gpu/drm/panel/panel-elida-kd35t133.c
@@ -42,6 +42,7 @@ struct kd35t133 {
struct gpio_desc *reset_gpio;
struct regulator *vdd;
struct regulator *iovcc;
+ enum drm_panel_orientation orientation;
bool prepared;
};
@@ -216,6 +217,7 @@ static int kd35t133_get_modes(struct drm_panel *panel,
connector->display_info.width_mm = mode->width_mm;
connector->display_info.height_mm = mode->height_mm;
drm_mode_probed_add(connector, mode);
+ drm_connector_set_panel_orientation(connector, ctx->orientation);
return 1;
}
@@ -258,6 +260,12 @@ static int kd35t133_probe(struct mipi_dsi_device *dsi)
return ret;
}
+ ret = of_drm_get_panel_orientation(dev->of_node, &ctx->orientation);
+ if (ret < 0) {
+ dev_err(dev, "%pOF: failed to get orientation %d\n",
dev->of_node, ret);
+ return ret;
+ }
+
mipi_dsi_set_drvdata(dsi, ctx);
ctx->dev = dev;
--
2.25.1
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[PATCH] drm/panel: correct typo in comments for Elida KD35T133
Update the comments to state this is a 3.5" display and not a 5.5" display. Signed-off-by: Chris Morgan --- drivers/gpu/drm/panel/panel-elida-kd35t133.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panel/panel-elida-kd35t133.c b/drivers/gpu/drm/panel/panel-elida-kd35t133.c index d8534406d1ef..bce84d2e6ada 100644 --- a/drivers/gpu/drm/panel/panel-elida-kd35t133.c +++ b/drivers/gpu/drm/panel/panel-elida-kd35t133.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Elida kd35t133 5.5" MIPI-DSI panel driver + * Elida kd35t133 3.5" MIPI-DSI panel driver * Copyright (C) 2020 Theobroma Systems Design und Consulting GmbH * * based on -- 2.25.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 1/2] drm/panel: add rotation support for Elida KD35T133 panels
Update the panel to allow setting the rotation value in device tree.
Signed-off-by: Chris Morgan
---
drivers/gpu/drm/panel/panel-elida-kd35t133.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-elida-kd35t133.c
b/drivers/gpu/drm/panel/panel-elida-kd35t133.c
index bc36aa3c1123..d8534406d1ef 100644
--- a/drivers/gpu/drm/panel/panel-elida-kd35t133.c
+++ b/drivers/gpu/drm/panel/panel-elida-kd35t133.c
@@ -42,6 +42,7 @@ struct kd35t133 {
struct gpio_desc *reset_gpio;
struct regulator *vdd;
struct regulator *iovcc;
+ enum drm_panel_orientation orientation;
bool prepared;
};
@@ -216,6 +217,7 @@ static int kd35t133_get_modes(struct drm_panel *panel,
connector->display_info.width_mm = mode->width_mm;
connector->display_info.height_mm = mode->height_mm;
drm_mode_probed_add(connector, mode);
+ drm_connector_set_panel_orientation(connector, ctx->orientation);
return 1;
}
@@ -258,6 +260,12 @@ static int kd35t133_probe(struct mipi_dsi_device *dsi)
return ret;
}
+ ret = of_drm_get_panel_orientation(dev->of_node, &ctx->orientation);
+ if (ret < 0) {
+ dev_err(dev, "%pOF: failed to get orientation %d\n",
dev->of_node, ret);
+ return ret;
+ }
+
mipi_dsi_set_drvdata(dsi, ctx);
ctx->dev = dev;
--
2.25.1
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[PATCH 2/2] drm/panel: correct typo in comments for Elida KD35T133 panel driver
Update the comments to state this is a 3.5" display and not a 5.5" display Signed-off-by: Chris Morgan --- drivers/gpu/drm/panel/panel-elida-kd35t133.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panel/panel-elida-kd35t133.c b/drivers/gpu/drm/panel/panel-elida-kd35t133.c index d8534406d1ef..bce84d2e6ada 100644 --- a/drivers/gpu/drm/panel/panel-elida-kd35t133.c +++ b/drivers/gpu/drm/panel/panel-elida-kd35t133.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Elida kd35t133 5.5" MIPI-DSI panel driver + * Elida kd35t133 3.5" MIPI-DSI panel driver * Copyright (C) 2020 Theobroma Systems Design und Consulting GmbH * * based on -- 2.25.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm/panel: elida-kd35t133: allow using non-continuous dsi clock
This fixes an issue with the panel not working after
commit c6d94e37bdbb ("drm/bridge/synopsys: dsi: add support for non-continuous
HS clock").
With this change the panel inits successfully and displays an image.
Signed-off-by: Chris Morgan
---
drivers/gpu/drm/panel/panel-elida-kd35t133.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/panel/panel-elida-kd35t133.c
b/drivers/gpu/drm/panel/panel-elida-kd35t133.c
index bc36aa3c1123..fe5ac3ef9018 100644
--- a/drivers/gpu/drm/panel/panel-elida-kd35t133.c
+++ b/drivers/gpu/drm/panel/panel-elida-kd35t133.c
@@ -265,7 +265,8 @@ static int kd35t133_probe(struct mipi_dsi_device *dsi)
dsi->lanes = 1;
dsi->format = MIPI_DSI_FMT_RGB888;
dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
- MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET;
+ MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET |
+ MIPI_DSI_CLOCK_NON_CONTINUOUS;
drm_panel_init(&ctx->panel, &dsi->dev, &kd35t133_funcs,
DRM_MODE_CONNECTOR_DSI);
--
2.25.1
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[PATCH 0/2] chrontel-ch7033: Add byteswap order option
From: Chris Morgan This series adds the ability to set the byteswap order in the chrontel ch7033 driver via an optional devicetree node. This is necessary because the HDMI DIP of the NTC CHIP requires a byteswap order that differs from the default value of the driver. Signed-off-by: Chris Morgan Chris Morgan (2): dt-bindings: Add byteswap order to chrontel ch7033 drm/bridge: chrontel-ch7033: Add option for setting byteswap order .../bindings/display/bridge/chrontel,ch7033.yaml | 8 drivers/gpu/drm/bridge/chrontel-ch7033.c | 15 +-- 2 files changed, 21 insertions(+), 2 deletions(-) -- 2.25.1
[PATCH 1/2] dt-bindings: Add byteswap order to chrontel ch7033
From: Chris Morgan Update dt-binding documentation to add support for setting byteswap of chrontel ch7033. New property name of chrontel,byteswap added to set the byteswap order. This property is optional. Signed-off-by: Chris Morgan --- .../bindings/display/bridge/chrontel,ch7033.yaml | 8 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml index bb6289c7d375..ecd3062c5215 100644 --- a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml +++ b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml @@ -14,6 +14,14 @@ properties: compatible: const: chrontel,ch7033 + chrontel,byteswap: +$ref: /schemas/types.yaml#/definitions/uint8 +enum: [0, 1, 2, 3, 4, 5] +description: | + Set the byteswap value of the bridge. Values 0-5 correspond to + BYTE_SWAP_RGB, BYTE_SWAP_RBG, BYTE_SWAP_GRB, BYTE_SWAP_GBR, + BYTE_SWAP_BRG, and BYTE_SWAP_BGR respectively. + reg: maxItems: 1 description: I2C address of the device -- 2.25.1
[PATCH 2/2] drm/bridge: chrontel-ch7033: Add option for setting byteswap order
From: Chris Morgan
Add the option to set the byteswap order in the devicetree. For the
official HDMI DIP for the NTC CHIP the byteswap order needs to be
RGB, however the driver sets it as BGR. With this patch the driver
will remain at BGR unless manually specified via devicetree.
Signed-off-by: Chris Morgan
---
drivers/gpu/drm/bridge/chrontel-ch7033.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c
b/drivers/gpu/drm/bridge/chrontel-ch7033.c
index 486f405c2e16..88175b7e80d4 100644
--- a/drivers/gpu/drm/bridge/chrontel-ch7033.c
+++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c
@@ -67,6 +67,7 @@ enum {
BYTE_SWAP_GBR = 3,
BYTE_SWAP_BRG = 4,
BYTE_SWAP_BGR = 5,
+ BYTE_SWAP_MAX = 6,
};
/* Page 0, Register 0x19 */
@@ -354,6 +355,8 @@ static void ch7033_bridge_mode_set(struct drm_bridge
*bridge,
int hsynclen = mode->hsync_end - mode->hsync_start;
int vbporch = mode->vsync_start - mode->vdisplay;
int vsynclen = mode->vsync_end - mode->vsync_start;
+ u8 byte_swap;
+ int ret;
/*
* Page 4
@@ -397,8 +400,16 @@ static void ch7033_bridge_mode_set(struct drm_bridge
*bridge,
regmap_write(priv->regmap, 0x15, vbporch);
regmap_write(priv->regmap, 0x16, vsynclen);
- /* Input color swap. */
- regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR);
+ /* Input color swap. Byte order is optional and will default to
+* BYTE_SWAP_BGR to preserve backwards compatibility with existing
+* driver.
+*/
+ ret = of_property_read_u8(priv->bridge.of_node, "chrontel,byteswap",
+ &byte_swap);
+ if (!ret && byte_swap < BYTE_SWAP_MAX)
+ regmap_update_bits(priv->regmap, 0x18, SWAP, byte_swap);
+ else
+ regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR);
/* Input clock and sync polarity. */
regmap_update_bits(priv->regmap, 0x19, 0x1, mode->clock >> 16);
--
2.25.1
[PATCH] drm/rockchip: Update crtc fixup to account for fractional clk change
From: Chris Morgan
After commit 928f9e268611 ("clk: fractional-divider: Hide
clk_fractional_divider_ops from wide audience") was merged it appears
that the DSI panel on my Odroid Go Advance stopped working. Upon closer
examination of the problem, it looks like it was the fixup in the
rockchip_drm_vop.c file was causing the issue. The changes made to the
clk driver appear to change some assumptions made in the fixup.
After debugging the working 5.14 kernel and the no-longer working
5.15 kernel, it looks like this was broken all along but still
worked, whereas after the fractional clock change it stopped
working despite the issue (it went from sort-of broken to very broken).
In the 5.14 kernel the dclk_vopb_frac was being requested to be set to
17000999 on my board. The clock driver was taking the value of the
parent clock and attempting to divide the requested value from it
(1700/17000999 = 0), then subtracting 1 from it (making it -1),
and running it through fls_long to get 64. It would then subtract
the value of fd->mwidth from it to get 48, and then bit shift
17000999 to the left by 48, coming up with a very large number of
7649082492112076800. This resulted in a numerator of 65535 and a
denominator of 1 from the clk driver. The driver seemingly would
try again and get a correct 1:1 value later, and then move on.
Output from my 5.14 kernel (with some printfs for good measure):
[2.830066] rockchip-drm display-subsystem: bound ff46.vop (ops
vop_component_ops)
[2.839431] rockchip-drm display-subsystem: bound ff45.dsi (ops
dw_mipi_dsi_rockchip_ops)
[2.855980] Clock is dclk_vopb_frac
[2.856004] Scale 64, Rate 7649082492112076800, Oldrate 17000999, Parent
Rate 1700, Best Numerator 65535, Best Denominator 1, fd->mwidth 16
[2.903529] Clock is dclk_vopb_frac
[2.903556] Scale 0, Rate 1700, Oldrate 1700, Parent Rate 1700,
Best Numerator 1, Best Denominator 1, fd->mwidth 16
[2.903579] Clock is dclk_vopb_frac
[2.903583] Scale 0, Rate 1700, Oldrate 1700, Parent Rate 1700,
Best Numerator 1, Best Denominator 1, fd->mwidth 16
Contrast this with 5.15 after the clk change where the rate of 17000999
was getting passed and resulted in numerators/denomiators of 17001/
17000.
Output from my 5.15 kernel (with some printfs added for good measure):
[2.817571] rockchip-drm display-subsystem: bound ff46.vop (ops
vop_component_ops)
[2.826975] rockchip-drm display-subsystem: bound ff45.dsi (ops
dw_mipi_dsi_rockchip_ops)
[2.843430] Rate 17000999, Parent Rate 1700, Best Numerator 17018, Best
Denominator 17017
[2.891073] Rate 17001000, Parent Rate 1700, Best Numerator 17001, Best
Denominator 17000
[2.891269] Rate 17001000, Parent Rate 1700, Best Numerator 17001, Best
Denominator 17000
[2.891281] Rate 17001000, Parent Rate 1700, Best Numerator 17001, Best
Denominator 17000
After tracing through the code it appeared that this function here was
adding a 999 to the requested frequency because of how the clk driver
was rounding/accepting those frequencies. I believe after the changes
made in the commit listed above the assumptions listed in this driver
are no longer true. When I remove the + 999 from the driver the DSI
panel begins to work again.
Output from my 5.15 kernel with 999 removed (printfs added):
[2.852054] rockchip-drm display-subsystem: bound ff46.vop (ops
vop_component_ops)
[2.864483] rockchip-drm display-subsystem: bound ff45.dsi (ops
dw_mipi_dsi_rockchip_ops)
[2.880869] Clock is dclk_vopb_frac
[2.880892] Rate 1700, Parent Rate 1700, Best Numerator 1, Best
Denominator 1
[2.928521] Clock is dclk_vopb_frac
[2.928551] Rate 1700, Parent Rate 1700, Best Numerator 1, Best
Denominator 1
[2.928570] Clock is dclk_vopb_frac
[2.928574] Rate 1700, Parent Rate 1700, Best Numerator 1, Best
Denominator 1
I have tested the change extensively on my Odroid Go Advance (Rockchip
RK3326) and it appears to work well. However, this change will affect
all Rockchip SoCs that use this driver so I believe further testing
is warranted. Please note that without this change I can confirm
at least all PX30s with DSI panels will stop working with the 5.15
kernel.
Signed-off-by: Chris Morgan
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 21 +++--
1 file changed, 3 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index ba9e14da41b4..bfef4f52dce6 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1169,31 +1169,16 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
*
* - DRM works in in kHz.
* - Clock framework works in Hz.
-* - Rockchip's clock driver picks the clock rate that is the
-* same _OR LO
Re: [PATCH] drm/rockchip: Update crtc fixup to account for fractional clk change
On Wed, Sep 08, 2021 at 09:05:52PM +0300, Andy Shevchenko wrote:
> On Wed, Sep 08, 2021 at 08:53:56AM -0500, Chris Morgan wrote:
> > From: Chris Morgan
> >
> > After commit 928f9e268611 ("clk: fractional-divider: Hide
> > clk_fractional_divider_ops from wide audience") was merged it appears
> > that the DSI panel on my Odroid Go Advance stopped working. Upon closer
> > examination of the problem, it looks like it was the fixup in the
> > rockchip_drm_vop.c file was causing the issue. The changes made to the
> > clk driver appear to change some assumptions made in the fixup.
> >
> > After debugging the working 5.14 kernel and the no-longer working
> > 5.15 kernel, it looks like this was broken all along but still
> > worked, whereas after the fractional clock change it stopped
> > working despite the issue (it went from sort-of broken to very broken).
> >
> > In the 5.14 kernel the dclk_vopb_frac was being requested to be set to
> > 17000999 on my board. The clock driver was taking the value of the
> > parent clock and attempting to divide the requested value from it
> > (1700/17000999 = 0), then subtracting 1 from it (making it -1),
> > and running it through fls_long to get 64. It would then subtract
> > the value of fd->mwidth from it to get 48, and then bit shift
> > 17000999 to the left by 48, coming up with a very large number of
> > 7649082492112076800. This resulted in a numerator of 65535 and a
> > denominator of 1 from the clk driver. The driver seemingly would
> > try again and get a correct 1:1 value later, and then move on.
> >
> > Output from my 5.14 kernel (with some printfs for good measure):
> > [2.830066] rockchip-drm display-subsystem: bound ff46.vop (ops
> > vop_component_ops)
> > [2.839431] rockchip-drm display-subsystem: bound ff45.dsi (ops
> > dw_mipi_dsi_rockchip_ops)
> > [2.855980] Clock is dclk_vopb_frac
> > [2.856004] Scale 64, Rate 7649082492112076800, Oldrate 17000999, Parent
> > Rate 1700, Best Numerator 65535, Best Denominator 1, fd->mwidth 16
> > [2.903529] Clock is dclk_vopb_frac
> > [2.903556] Scale 0, Rate 1700, Oldrate 1700, Parent Rate
> > 1700, Best Numerator 1, Best Denominator 1, fd->mwidth 16
> > [2.903579] Clock is dclk_vopb_frac
> > [2.903583] Scale 0, Rate 1700, Oldrate 1700, Parent Rate
> > 1700, Best Numerator 1, Best Denominator 1, fd->mwidth 16
> >
> > Contrast this with 5.15 after the clk change where the rate of 17000999
> > was getting passed and resulted in numerators/denomiators of 17001/
> > 17000.
> >
> > Output from my 5.15 kernel (with some printfs added for good measure):
> > [2.817571] rockchip-drm display-subsystem: bound ff46.vop (ops
> > vop_component_ops)
> > [2.826975] rockchip-drm display-subsystem: bound ff45.dsi (ops
> > dw_mipi_dsi_rockchip_ops)
> > [2.843430] Rate 17000999, Parent Rate 1700, Best Numerator 17018,
> > Best Denominator 17017
> > [2.891073] Rate 17001000, Parent Rate 1700, Best Numerator 17001,
> > Best Denominator 17000
> > [2.891269] Rate 17001000, Parent Rate 1700, Best Numerator 17001,
> > Best Denominator 17000
> > [2.891281] Rate 17001000, Parent Rate 1700, Best Numerator 17001,
> > Best Denominator 17000
> >
> > After tracing through the code it appeared that this function here was
> > adding a 999 to the requested frequency because of how the clk driver
> > was rounding/accepting those frequencies. I believe after the changes
> > made in the commit listed above the assumptions listed in this driver
> > are no longer true. When I remove the + 999 from the driver the DSI
> > panel begins to work again.
> >
> > Output from my 5.15 kernel with 999 removed (printfs added):
> > [2.852054] rockchip-drm display-subsystem: bound ff46.vop (ops
> > vop_component_ops)
> > [2.864483] rockchip-drm display-subsystem: bound ff45.dsi (ops
> > dw_mipi_dsi_rockchip_ops)
> > [2.880869] Clock is dclk_vopb_frac
> > [2.880892] Rate 1700, Parent Rate 1700, Best Numerator 1, Best
> > Denominator 1
> > [2.928521] Clock is dclk_vopb_frac
> > [2.928551] Rate 1700, Parent Rate 1700, Best Numerator 1, Best
> > Denominator 1
> > [2.928570] Clock is dclk_vopb_frac
> > [2.928574] Rate 1700, Parent Rate 1700, Best Numerator 1, Best
> > Denominator 1
> >
> > I have tested the change extensively on my Odroid Go Advance (Rockchip
> > RK3326
Re: [PATCH] drm/rockchip: Update crtc fixup to account for fractional clk change
On Thu, Sep 16, 2021 at 10:08:05AM -0700, Doug Anderson wrote:
> Hi,
>
> On Tue, Sep 14, 2021 at 4:14 AM Heiko Stübner wrote:
> >
> > Hi,
> >
> > Am Mittwoch, 8. September 2021, 15:53:56 CEST schrieb Chris Morgan:
> > > From: Chris Morgan
> > >
> > > After commit 928f9e268611 ("clk: fractional-divider: Hide
> > > clk_fractional_divider_ops from wide audience") was merged it appears
> > > that the DSI panel on my Odroid Go Advance stopped working. Upon closer
> > > examination of the problem, it looks like it was the fixup in the
> > > rockchip_drm_vop.c file was causing the issue. The changes made to the
> > > clk driver appear to change some assumptions made in the fixup.
> > >
> > > After debugging the working 5.14 kernel and the no-longer working
> > > 5.15 kernel, it looks like this was broken all along but still
> > > worked, whereas after the fractional clock change it stopped
> > > working despite the issue (it went from sort-of broken to very broken).
> > >
> > > In the 5.14 kernel the dclk_vopb_frac was being requested to be set to
> > > 17000999 on my board. The clock driver was taking the value of the
> > > parent clock and attempting to divide the requested value from it
> > > (1700/17000999 = 0), then subtracting 1 from it (making it -1),
> > > and running it through fls_long to get 64. It would then subtract
> > > the value of fd->mwidth from it to get 48, and then bit shift
> > > 17000999 to the left by 48, coming up with a very large number of
> > > 7649082492112076800. This resulted in a numerator of 65535 and a
> > > denominator of 1 from the clk driver. The driver seemingly would
> > > try again and get a correct 1:1 value later, and then move on.
> > >
> > > Output from my 5.14 kernel (with some printfs for good measure):
> > > [2.830066] rockchip-drm display-subsystem: bound ff46.vop (ops
> > > vop_component_ops)
> > > [2.839431] rockchip-drm display-subsystem: bound ff45.dsi (ops
> > > dw_mipi_dsi_rockchip_ops)
> > > [2.855980] Clock is dclk_vopb_frac
> > > [2.856004] Scale 64, Rate 7649082492112076800, Oldrate 17000999,
> > > Parent Rate 1700, Best Numerator 65535, Best Denominator 1,
> > > fd->mwidth 16
> > > [2.903529] Clock is dclk_vopb_frac
> > > [2.903556] Scale 0, Rate 1700, Oldrate 1700, Parent Rate
> > > 1700, Best Numerator 1, Best Denominator 1, fd->mwidth 16
> > > [2.903579] Clock is dclk_vopb_frac
> > > [2.903583] Scale 0, Rate 1700, Oldrate 1700, Parent Rate
> > > 1700, Best Numerator 1, Best Denominator 1, fd->mwidth 16
> > >
> > > Contrast this with 5.15 after the clk change where the rate of 17000999
> > > was getting passed and resulted in numerators/denomiators of 17001/
> > > 17000.
> > >
> > > Output from my 5.15 kernel (with some printfs added for good measure):
> > > [2.817571] rockchip-drm display-subsystem: bound ff46.vop (ops
> > > vop_component_ops)
> > > [2.826975] rockchip-drm display-subsystem: bound ff45.dsi (ops
> > > dw_mipi_dsi_rockchip_ops)
> > > [2.843430] Rate 17000999, Parent Rate 1700, Best Numerator 17018,
> > > Best Denominator 17017
> > > [2.891073] Rate 17001000, Parent Rate 1700, Best Numerator 17001,
> > > Best Denominator 17000
> > > [2.891269] Rate 17001000, Parent Rate 1700, Best Numerator 17001,
> > > Best Denominator 17000
> > > [2.891281] Rate 17001000, Parent Rate 1700, Best Numerator 17001,
> > > Best Denominator 17000
> > >
> > > After tracing through the code it appeared that this function here was
> > > adding a 999 to the requested frequency because of how the clk driver
> > > was rounding/accepting those frequencies. I believe after the changes
> > > made in the commit listed above the assumptions listed in this driver
> > > are no longer true. When I remove the + 999 from the driver the DSI
> > > panel begins to work again.
> > >
> > > Output from my 5.15 kernel with 999 removed (printfs added):
> > > [2.852054] rockchip-drm display-subsystem: bound ff46.vop (ops
> > > vop_component_ops)
> > > [2.864483] rockchip-drm display-subsystem: bound ff45.dsi (ops
> > > dw_mipi_dsi_rockchip_ops)
> > > [2.880869] Clock is dclk_vopb_frac
> > > [2.880892] Rate 1700, Parent Rat
[PATCH v2] drm/rockchip: Update crtc fixup to account for fractional clk change
From: Chris Morgan
Fixes commit 287422a95fe2 ("drm/rockchip: Round up _before_ giving to
the clock framework")
After commit 928f9e268611 ("clk: fractional-divider: Hide
clk_fractional_divider_ops from wide audience") was merged it appears
that the DSI panel on my Odroid Go Advance stopped working. Upon closer
examination of the problem, it looks like it was the fixup in the
rockchip_drm_vop.c file was causing the issue. The changes made to the
clk driver appear to change some assumptions made in the fixup.
After debugging the working 5.14 kernel and the no-longer working
5.15 kernel, it looks like this was broken all along but still
worked, whereas after the fractional clock change it stopped
working despite the issue (it went from sort-of broken to very broken).
In the 5.14 kernel the dclk_vopb_frac was being requested to be set to
17000999 on my board. The clock driver was taking the value of the
parent clock and attempting to divide the requested value from it
(1700/17000999 = 0), then subtracting 1 from it (making it -1),
and running it through fls_long to get 64. It would then subtract
the value of fd->mwidth from it to get 48, and then bit shift
17000999 to the left by 48, coming up with a very large number of
7649082492112076800. This resulted in a numerator of 65535 and a
denominator of 1 from the clk driver. The driver seemingly would
try again and get a correct 1:1 value later, and then move on.
Output from my 5.14 kernel (with some printfs for good measure):
[2.830066] rockchip-drm display-subsystem: bound ff46.vop (ops
vop_component_ops)
[2.839431] rockchip-drm display-subsystem: bound ff45.dsi (ops
dw_mipi_dsi_rockchip_ops)
[2.855980] Clock is dclk_vopb_frac
[2.856004] Scale 64, Rate 7649082492112076800, Oldrate 17000999, Parent
Rate 1700, Best Numerator 65535, Best Denominator 1, fd->mwidth 16
[2.903529] Clock is dclk_vopb_frac
[2.903556] Scale 0, Rate 1700, Oldrate 1700, Parent Rate 1700,
Best Numerator 1, Best Denominator 1, fd->mwidth 16
[2.903579] Clock is dclk_vopb_frac
[2.903583] Scale 0, Rate 1700, Oldrate 1700, Parent Rate 1700,
Best Numerator 1, Best Denominator 1, fd->mwidth 16
Contrast this with 5.15 after the clk change where the rate of 17000999
was getting passed and resulted in numerators/denomiators of 17001/
17000.
Output from my 5.15 kernel (with some printfs added for good measure):
[2.817571] rockchip-drm display-subsystem: bound ff46.vop (ops
vop_component_ops)
[2.826975] rockchip-drm display-subsystem: bound ff45.dsi (ops
dw_mipi_dsi_rockchip_ops)
[2.843430] Rate 17000999, Parent Rate 1700, Best Numerator 17018, Best
Denominator 17017
[2.891073] Rate 17001000, Parent Rate 1700, Best Numerator 17001, Best
Denominator 17000
[2.891269] Rate 17001000, Parent Rate 1700, Best Numerator 17001, Best
Denominator 17000
[2.891281] Rate 17001000, Parent Rate 1700, Best Numerator 17001, Best
Denominator 17000
I have tested the change extensively on my Odroid Go Advance (Rockchip
RK3326) and it appears to work well. However, this change will affect
all Rockchip SoCs that use this driver so I believe further testing
is warranted. Please note that without this change I can confirm
at least all PX30s with DSI panels will stop working with the 5.15
kernel.
Upon advice from Doug Anderson it was decided
that we would first check if the clock rate can be set exactly as
requested, and only if it could not would we then add 999 to it and
attempt the process again. This way we can preserve the behavior for
clocks that still need it while resolving the specific issue for the
PX30 and DSI panels (since it is using a fractional clock).
Changes since v1:
- Made the addition of 999 conditional based on whether the clock
subsystem can set the actual clock rate as requested.
- Updated the notes in the fixup routine to reflect this new behavior.
- Added reference to original commit, as this has technically been
broken since then however only now is it an issue due to the clock
changes.
Signed-off-by: Chris Morgan
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 26 ++---
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index ba9e14da41b4..a25b98b7f5bd 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1174,26 +1174,24 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
*
* Action plan:
*
-* 1. When DRM gives us a mode, we should add 999 Hz to it. That way
-*if the clock we need is 6001 Hz (~60 MHz) and DRM tells us to
-*make 6 kHz then the clock framework will actually give us
-*the right clock.
+* 1. Try to set the exact rate first,
[PATCH v3] drm/rockchip: Update crtc fixup to account for fractional clk change
From: Chris Morgan
After commit 928f9e268611 ("clk: fractional-divider: Hide
clk_fractional_divider_ops from wide audience") was merged it appears
that the DSI panel on my Odroid Go Advance stopped working. Upon closer
examination of the problem, it looks like it was the fixup in the
rockchip_drm_vop.c file was causing the issue. The changes made to the
clk driver appear to change some assumptions made in the fixup.
After debugging the working 5.14 kernel and the no-longer working
5.15 kernel, it looks like this was broken all along but still
worked, whereas after the fractional clock change it stopped
working despite the issue (it went from sort-of broken to very broken).
In the 5.14 kernel the dclk_vopb_frac was being requested to be set to
17000999 on my board. The clock driver was taking the value of the
parent clock and attempting to divide the requested value from it
(1700/17000999 = 0), then subtracting 1 from it (making it -1),
and running it through fls_long to get 64. It would then subtract
the value of fd->mwidth from it to get 48, and then bit shift
17000999 to the left by 48, coming up with a very large number of
7649082492112076800. This resulted in a numerator of 65535 and a
denominator of 1 from the clk driver. The driver seemingly would
try again and get a correct 1:1 value later, and then move on.
Output from my 5.14 kernel (with some printfs for good measure):
[2.830066] rockchip-drm display-subsystem: bound ff46.vop (ops
vop_component_ops)
[2.839431] rockchip-drm display-subsystem: bound ff45.dsi (ops
dw_mipi_dsi_rockchip_ops)
[2.855980] Clock is dclk_vopb_frac
[2.856004] Scale 64, Rate 7649082492112076800, Oldrate 17000999, Parent
Rate 1700, Best Numerator 65535, Best Denominator 1, fd->mwidth 16
[2.903529] Clock is dclk_vopb_frac
[2.903556] Scale 0, Rate 1700, Oldrate 1700, Parent Rate 1700,
Best Numerator 1, Best Denominator 1, fd->mwidth 16
[2.903579] Clock is dclk_vopb_frac
[2.903583] Scale 0, Rate 1700, Oldrate 1700, Parent Rate 1700,
Best Numerator 1, Best Denominator 1, fd->mwidth 16
Contrast this with 5.15 after the clk change where the rate of 17000999
was getting passed and resulted in numerators/denomiators of 17001/
17000.
Output from my 5.15 kernel (with some printfs added for good measure):
[2.817571] rockchip-drm display-subsystem: bound ff46.vop (ops
vop_component_ops)
[2.826975] rockchip-drm display-subsystem: bound ff45.dsi (ops
dw_mipi_dsi_rockchip_ops)
[2.843430] Rate 17000999, Parent Rate 1700, Best Numerator 17018, Best
Denominator 17017
[2.891073] Rate 17001000, Parent Rate 1700, Best Numerator 17001, Best
Denominator 17000
[2.891269] Rate 17001000, Parent Rate 1700, Best Numerator 17001, Best
Denominator 17000
[2.891281] Rate 17001000, Parent Rate 1700, Best Numerator 17001, Best
Denominator 17000
I have tested the change extensively on my Odroid Go Advance (Rockchip
RK3326) and it appears to work well. However, this change will affect
all Rockchip SoCs that use this driver so I believe further testing
is warranted. Please note that without this change I can confirm
at least all PX30s with DSI panels will stop working with the 5.15
kernel.
Upon advice from Doug Anderson it was decided
that we would first check if the clock rate can be set exactly as
requested, and only if it could not would we then add 999 to it and
attempt the process again. This way we can preserve the behavior for
clocks that still need it while resolving the specific issue for the
PX30 and DSI panels (since it is using a fractional clock).
Changes since v2:
- Moved fixes to correct location.
Changes since v1:
- Made the addition of 999 conditional based on whether the clock
subsystem can set the actual clock rate as requested.
- Updated the notes in the fixup routine to reflect this new behavior.
- Added reference to original commit, as this has technically been
broken since then however only now is it an issue due to the clock
changes.
Fixes: 287422a95fe2 ("drm/rockchip: Round up _before_ giving to the clock
framework")
Signed-off-by: Chris Morgan
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 26 ++---
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index ba9e14da41b4..a25b98b7f5bd 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1174,26 +1174,24 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
*
* Action plan:
*
-* 1. When DRM gives us a mode, we should add 999 Hz to it. That way
-*if the clock we need is 6001 Hz (~60 MHz) and DRM tells us to
-*make 6 kHz then the clock framework will actually give us
-*the right clock.
+
Re: [PATCH v3] drm/rockchip: Update crtc fixup to account for fractional clk change
On Thu, Sep 16, 2021 at 01:49:07PM -0700, Brian Norris wrote:
> On Thu, Sep 16, 2021 at 03:29:07PM -0500, Chris Morgan wrote:
> > After commit 928f9e268611 ("clk: fractional-divider: Hide
> > clk_fractional_divider_ops from wide audience") was merged it appears
>
> What does that commit have to do with anything? Are you perhaps
> interested in its parent, where the rockchip clock driver was actually
> changed?
It was part of a series of 4 commits, basically there were 2 commits
from the series that had to be rolled back to make things work again
and this was one of the two. Sorry for the confusion. It turns out
that there was a change made some time ago (referenced by the Fixes:)
that broke how the clock was getting set for a specific clock, but
it wasn't until the patch series about the fractional dividers where
it went from "works despite being broken in this limited case" to
"doesn't work anymore in this limited case."
Thank you.
>
> 4e7cf74fa3b2 clk: fractional-divider: Export approximation algorithm to the
> CCF users
>
> I'm just trying to follow along what's going on here.
>
> Brian
[PATCH 0/6 v2] Support Geekworm MZP280 Panel for Raspberry Pi
From: Chris Morgan This patch series is to add support for the MZP280 panel for the Raspberry Pi. This panel requires adding support for Mode 3 of the Raspberry Pi DPI connector, which necessitates a new media bus format. This patch series has been tested on my Raspberry Pi 4 with version 1 of the panel in question. Changes since V1: - Added documentation for vendor string. Signed-off-by: Chris Morgan Chris Morgan (6): dt-bindings: vendor-prefixes: Add Geekworm media: uapi: Document format MEDIA_BUS_FMT_RGB565_1X24_CPADHI media: uapi: add MEDIA_BUS_FMT_RGB565_1X24_CPADHI dt-bindings: display: simple: add Geekworm MZP280 Panel drm/panel: simple: add Geekworm MZP280 Panel drm/vc4: dpi: Support DPI interface in mode3 for RGB565 .../bindings/display/panel/panel-simple.yaml | 2 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + .../media/v4l/subdev-formats.rst | 37 +++ drivers/gpu/drm/panel/panel-simple.c | 29 +++ drivers/gpu/drm/vc4/vc4_dpi.c | 4 ++ include/uapi/linux/media-bus-format.h | 3 +- 6 files changed, 76 insertions(+), 1 deletion(-) -- 2.25.1
[PATCH 2/6 v2] media: uapi: Document format MEDIA_BUS_FMT_RGB565_1X24_CPADHI
From: Chris Morgan Add support for MEDIA_BUS_FMT_RGB565_1X24_CPADHI. This format is used by the Geekworm MZP280 panel which interfaces with the Raspberry Pi. Signed-off-by: Chris Morgan --- .../media/v4l/subdev-formats.rst | 37 +++ 1 file changed, 37 insertions(+) diff --git a/Documentation/userspace-api/media/v4l/subdev-formats.rst b/Documentation/userspace-api/media/v4l/subdev-formats.rst index 0cbc045d5..e43e07634 100644 --- a/Documentation/userspace-api/media/v4l/subdev-formats.rst +++ b/Documentation/userspace-api/media/v4l/subdev-formats.rst @@ -624,6 +624,43 @@ The following tables list existing packed RGB formats. - b\ :sub:`2` - b\ :sub:`1` - b\ :sub:`0` +* .. _MEDIA_BUS_FMT_RGB565_1X24_CPADHI: + + - MEDIA_BUS_FMT_RGB565_1X24_CPADHI + - 0x101e + - + - + - + - + - + - + - + - + - + - 0 + - 0 + - 0 + - r\ :sub:`4` + - r\ :sub:`3` + - r\ :sub:`2` + - r\ :sub:`1` + - r\ :sub:`0` + - 0 + - 0 + - g\ :sub:`5` + - g\ :sub:`4` + - g\ :sub:`3` + - g\ :sub:`2` + - g\ :sub:`1` + - g\ :sub:`0` + - 0 + - 0 + - 0 + - b\ :sub:`4` + - b\ :sub:`3` + - b\ :sub:`2` + - b\ :sub:`1` + - b\ :sub:`0` * .. _MEDIA-BUS-FMT-BGR565-2X8-BE: - MEDIA_BUS_FMT_BGR565_2X8_BE -- 2.25.1
[PATCH 3/6 v2] media: uapi: add MEDIA_BUS_FMT_RGB565_1X24_CPADHI
From: Chris Morgan Add the MEDIA_BUS_FMT_RGB565_1X24_CPADHI format used by the Geekworm MZP280 panel for the Raspberry Pi. Signed-off-by: Chris Morgan --- include/uapi/linux/media-bus-format.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h index 0dfc11ee2..a7b765498 100644 --- a/include/uapi/linux/media-bus-format.h +++ b/include/uapi/linux/media-bus-format.h @@ -34,13 +34,14 @@ #define MEDIA_BUS_FMT_FIXED0x0001 -/* RGB - next is 0x101e */ +/* RGB - next is 0x101f */ #define MEDIA_BUS_FMT_RGB444_1X12 0x1016 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002 #define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003 #define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004 #define MEDIA_BUS_FMT_RGB565_1X16 0x1017 +#define MEDIA_BUS_FMT_RGB565_1X24_CPADHI 0x101e #define MEDIA_BUS_FMT_BGR565_2X8_BE0x1005 #define MEDIA_BUS_FMT_BGR565_2X8_LE0x1006 #define MEDIA_BUS_FMT_RGB565_2X8_BE0x1007 -- 2.25.1
[PATCH 5/6 v2] drm/panel: simple: add Geekworm MZP280 Panel
From: Chris Morgan
Add support for the Geekworm MZP280 Panel
Signed-off-by: Chris Morgan
Acked-by: Maxime Ripard
---
drivers/gpu/drm/panel/panel-simple.c | 29
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index 9e46db5e3..cbc1a4fd1 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1824,6 +1824,32 @@ static const struct panel_desc friendlyarm_hd702e = {
},
};
+static const struct drm_display_mode geekworm_mzp280_mode = {
+ .clock = 32000,
+ .hdisplay = 480,
+ .hsync_start = 480 + 41,
+ .hsync_end = 480 + 41 + 20,
+ .htotal = 480 + 41 + 20 + 60,
+ .vdisplay = 640,
+ .vsync_start = 640 + 5,
+ .vsync_end = 640 + 5 + 10,
+ .vtotal = 640 + 5 + 10 + 10,
+ .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
+};
+
+static const struct panel_desc geekworm_mzp280 = {
+ .modes = &geekworm_mzp280_mode,
+ .num_modes = 1,
+ .bpc = 6,
+ .size = {
+ .width = 47,
+ .height = 61,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB565_1X24_CPADHI,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
+ .connector_type = DRM_MODE_CONNECTOR_DPI,
+};
+
static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
.clock = 9000,
.hdisplay = 480,
@@ -3790,6 +3816,9 @@ static const struct of_device_id platform_of_match[] = {
}, {
.compatible = "friendlyarm,hd702e",
.data = &friendlyarm_hd702e,
+ }, {
+ .compatible = "geekworm,mzp280",
+ .data = &geekworm_mzp280,
}, {
.compatible = "giantplus,gpg482739qs5",
.data = &giantplus_gpg482739qs5
--
2.25.1
[PATCH 1/6 v2] dt-bindings: vendor-prefixes: Add Geekworm
From: Chris Morgan Add vendor prefix for Geekworm (https://geekworm.com). Signed-off-by: Chris Morgan --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 294093d45..c0c7627c6 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -455,6 +455,8 @@ patternProperties: description: General Electric Company "^geekbuying,.*": description: GeekBuying + "^geekworm,.*": +description: Geekworm "^gef,.*": description: GE Fanuc Intelligent Platforms Embedded Systems, Inc. "^GEFanuc,.*": -- 2.25.1
[PATCH 4/6 v2] dt-bindings: display: simple: add Geekworm MZP280 Panel
From: Chris Morgan The Geekworm MZP280 panel is a 480x640 (portrait) panel with a capacitive touch interface and a 40 pin header meant to interface directly with the Raspberry Pi. The screen is 2.8 inches diagonally, and there appear to be at least 4 distinct versions all with the same panel timings. Timings were derived from drivers posted on the github located here: https://github.com/tianyoujian/MZDPI/tree/master/vga Additional details about this panel family can be found here: https://wiki.geekworm.com/2.8_inch_Touch_Screen_for_Pi_zero Signed-off-by: Chris Morgan --- .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 62f5f050c..3d03d8276 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -148,6 +148,8 @@ properties: - frida,frd350h54004 # FriendlyELEC HD702E 800x1280 LCD panel - friendlyarm,hd702e +# Geekworm MZP280 2.8" 480x640 LCD panel with capacitive touch + - geekworm,mzp280 # GiantPlus GPG48273QS5 4.3" (480x272) WQVGA TFT LCD panel - giantplus,gpg48273qs5 # GiantPlus GPM940B0 3.0" QVGA TFT LCD panel -- 2.25.1
[PATCH 6/6 v2] drm/vc4: dpi: Support DPI interface in mode3 for RGB565
From: Chris Morgan
Add support for the VC4 DPI driver to utilize DPI mode 3. This is
defined here as xxxRxxGGxxxB:
https://www.raspberrypi.com/documentation/computers/raspberry-pi.html#parallel-display-interface-dpi
This mode is required to use the Geekworm MZP280 DPI display.
Signed-off-by: Chris Morgan
Reviewed-by: Dave Stevenson
---
drivers/gpu/drm/vc4/vc4_dpi.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_dpi.c b/drivers/gpu/drm/vc4/vc4_dpi.c
index c180eb60b..3c58ade25 100644
--- a/drivers/gpu/drm/vc4/vc4_dpi.c
+++ b/drivers/gpu/drm/vc4/vc4_dpi.c
@@ -173,6 +173,10 @@ static void vc4_dpi_encoder_enable(struct drm_encoder
*encoder)
dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3,
DPI_FORMAT);
break;
+ case MEDIA_BUS_FMT_RGB565_1X24_CPADHI:
+ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_2,
+ DPI_FORMAT);
+ break;
default:
DRM_ERROR("Unknown media bus format %d\n", bus_format);
break;
--
2.25.1
[PATCH 0/5] Support Geekworm MZP280 Panel for Raspberry Pi
From: Chris Morgan This patch series is to add support for the MZP280 panel for the Raspberry Pi. This panel requires adding support for Mode 3 of the Raspberry Pi DPI connector, which necessitates a new media bus format. This patch series has been tested on my Raspberry Pi 4 with version 1 of the panel in question. Signed-off-by: Chris Morgan Chris Morgan (5): media: uapi: Document format MEDIA_BUS_FMT_RGB565_1X24_CPADHI media: uapi: add MEDIA_BUS_FMT_RGB565_1X24_CPADHI dt-bindings: display: simple: add Geekworm MZP280 Panel drm/panel: simple: add Geekworm MZP280 Panel drm/vc4: dpi: Support DPI interface in mode3 for RGB565 .../bindings/display/panel/panel-simple.yaml | 2 + .../media/v4l/subdev-formats.rst | 37 +++ drivers/gpu/drm/panel/panel-simple.c | 29 +++ drivers/gpu/drm/vc4/vc4_dpi.c | 4 ++ include/uapi/linux/media-bus-format.h | 3 +- 5 files changed, 74 insertions(+), 1 deletion(-) -- 2.25.1
[PATCH 1/5] media: uapi: Document format MEDIA_BUS_FMT_RGB565_1X24_CPADHI
From: Chris Morgan Add support for MEDIA_BUS_FMT_RGB565_1X24_CPADHI. This format is used by the Geekworm MZP280 panel which interfaces with the Raspberry Pi. Signed-off-by: Chris Morgan --- .../media/v4l/subdev-formats.rst | 37 +++ 1 file changed, 37 insertions(+) diff --git a/Documentation/userspace-api/media/v4l/subdev-formats.rst b/Documentation/userspace-api/media/v4l/subdev-formats.rst index bd68588b2683..f3dcfa763ebc 100644 --- a/Documentation/userspace-api/media/v4l/subdev-formats.rst +++ b/Documentation/userspace-api/media/v4l/subdev-formats.rst @@ -624,6 +624,43 @@ The following tables list existing packed RGB formats. - b\ :sub:`2` - b\ :sub:`1` - b\ :sub:`0` +* .. _MEDIA_BUS_FMT_RGB565_1X24_CPADHI: + + - MEDIA_BUS_FMT_RGB565_1X24_CPADHI + - 0x101e + - + - + - + - + - + - + - + - + - + - 0 + - 0 + - 0 + - r\ :sub:`4` + - r\ :sub:`3` + - r\ :sub:`2` + - r\ :sub:`1` + - r\ :sub:`0` + - 0 + - 0 + - g\ :sub:`5` + - g\ :sub:`4` + - g\ :sub:`3` + - g\ :sub:`2` + - g\ :sub:`1` + - g\ :sub:`0` + - 0 + - 0 + - 0 + - b\ :sub:`4` + - b\ :sub:`3` + - b\ :sub:`2` + - b\ :sub:`1` + - b\ :sub:`0` * .. _MEDIA-BUS-FMT-BGR565-2X8-BE: - MEDIA_BUS_FMT_BGR565_2X8_BE -- 2.25.1
[PATCH 2/5] media: uapi: add MEDIA_BUS_FMT_RGB565_1X24_CPADHI
From: Chris Morgan Add the MEDIA_BUS_FMT_RGB565_1X24_CPADHI format used by the Geekworm MZP280 panel for the Raspberry Pi. Signed-off-by: Chris Morgan --- include/uapi/linux/media-bus-format.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h index 0dfc11ee243a..a7b7654985ee 100644 --- a/include/uapi/linux/media-bus-format.h +++ b/include/uapi/linux/media-bus-format.h @@ -34,13 +34,14 @@ #define MEDIA_BUS_FMT_FIXED0x0001 -/* RGB - next is 0x101e */ +/* RGB - next is 0x101f */ #define MEDIA_BUS_FMT_RGB444_1X12 0x1016 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002 #define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003 #define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004 #define MEDIA_BUS_FMT_RGB565_1X16 0x1017 +#define MEDIA_BUS_FMT_RGB565_1X24_CPADHI 0x101e #define MEDIA_BUS_FMT_BGR565_2X8_BE0x1005 #define MEDIA_BUS_FMT_BGR565_2X8_LE0x1006 #define MEDIA_BUS_FMT_RGB565_2X8_BE0x1007 -- 2.25.1
[PATCH 3/5] dt-bindings: display: simple: add Geekworm MZP280 Panel
From: Chris Morgan The Geekworm MZP280 panel is a 480x640 (portrait) panel with a capacitive touch interface and a 40 pin header meant to interface directly with the Raspberry Pi. The screen is 2.8 inches diagonally, and there appear to be at least 4 distinct versions all with the same panel timings. Timings were derived from drivers posted on the github located here: https://github.com/tianyoujian/MZDPI/tree/master/vga Additional details about this panel family can be found here: https://wiki.geekworm.com/2.8_inch_Touch_Screen_for_Pi_zero Signed-off-by: Chris Morgan --- .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index f3c9395d23b6..659db7206c96 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -148,6 +148,8 @@ properties: - frida,frd350h54004 # FriendlyELEC HD702E 800x1280 LCD panel - friendlyarm,hd702e +# Geekworm MZP280 2.8" 480x640 LCD panel with capacitive touch + - geekworm,mzp280 # GiantPlus GPG48273QS5 4.3" (480x272) WQVGA TFT LCD panel - giantplus,gpg48273qs5 # GiantPlus GPM940B0 3.0" QVGA TFT LCD panel -- 2.25.1
[PATCH 4/5] drm/panel: simple: add Geekworm MZP280 Panel
From: Chris Morgan
Add support for the Geekworm MZP280 Panel
Signed-off-by: Chris Morgan
---
drivers/gpu/drm/panel/panel-simple.c | 29
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index eb475a3a774b..f40f4e9a0e08 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1824,6 +1824,32 @@ static const struct panel_desc friendlyarm_hd702e = {
},
};
+static const struct drm_display_mode geekworm_mzp280_mode = {
+ .clock = 32000,
+ .hdisplay = 480,
+ .hsync_start = 480 + 41,
+ .hsync_end = 480 + 41 + 20,
+ .htotal = 480 + 41 + 20 + 60,
+ .vdisplay = 640,
+ .vsync_start = 640 + 5,
+ .vsync_end = 640 + 5 + 10,
+ .vtotal = 640 + 5 + 10 + 10,
+ .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
+};
+
+static const struct panel_desc geekworm_mzp280 = {
+ .modes = &geekworm_mzp280_mode,
+ .num_modes = 1,
+ .bpc = 6,
+ .size = {
+ .width = 47,
+ .height = 61,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB565_1X24_CPADHI,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
+ .connector_type = DRM_MODE_CONNECTOR_DPI,
+};
+
static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
.clock = 9000,
.hdisplay = 480,
@@ -3713,6 +3739,9 @@ static const struct of_device_id platform_of_match[] = {
}, {
.compatible = "friendlyarm,hd702e",
.data = &friendlyarm_hd702e,
+ }, {
+ .compatible = "geekworm,mzp280",
+ .data = &geekworm_mzp280,
}, {
.compatible = "giantplus,gpg482739qs5",
.data = &giantplus_gpg482739qs5
--
2.25.1
[PATCH 5/5] drm/vc4: dpi: Support DPI interface in mode3 for RGB565
From: Chris Morgan
Add support for the VC4 DPI driver to utilize DPI mode 3. This is
defined here as xxxRxxGGxxxB:
https://www.raspberrypi.com/documentation/computers/raspberry-pi.html#parallel-display-interface-dpi
This mode is required to use the Geekworm MZP280 DPI display.
Signed-off-by: Chris Morgan
---
drivers/gpu/drm/vc4/vc4_dpi.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_dpi.c b/drivers/gpu/drm/vc4/vc4_dpi.c
index c180eb60bee8..3c58ade2549e 100644
--- a/drivers/gpu/drm/vc4/vc4_dpi.c
+++ b/drivers/gpu/drm/vc4/vc4_dpi.c
@@ -173,6 +173,10 @@ static void vc4_dpi_encoder_enable(struct drm_encoder
*encoder)
dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3,
DPI_FORMAT);
break;
+ case MEDIA_BUS_FMT_RGB565_1X24_CPADHI:
+ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_2,
+ DPI_FORMAT);
+ break;
default:
DRM_ERROR("Unknown media bus format %d\n", bus_format);
break;
--
2.25.1
[RFC 0/4] rockchip-dsi for rk3568
From: Chris Morgan This series adds support for the dsi and dphy controllers on the Rockchip RK3568. I can confirm that for the Rockchip RK3568 this current series DOES NOT WORK properly yet. The image on the screen is shifted about 100 pixels to the right and does not appear to be a timing issue. This behavior was observed on both the Anbernic RG503 and RG353 portable gaming devices with different screens. These changes were also tested on an RK3326 based device (an Odroid Go Advance) with no noticeable regressions. An example of the issue on multiple devices: https://media.discordapp.net/attachments/973914035890290718/1007407064647221299/IMG_1999.jpg https://media.discordapp.net/attachments/995430498677571604/1003754966932008960/AB25898E-73EC-40A9-BD47-3FB970DDFB31.jpg Given the fact that the DSI controller is identical on the PX30 and RK3568 aside from different grf registers I am assuming the PHY is likely where the bugs are currently. I'm posting this as an RFC in the hopes that someone more knowledgeable than I can help identify the problem. Chris Morgan (4): dt-bindings: display: rockchip-dsi: add rk3568 compatible dt-bindings: phy: phy-rockchip-inno-dsidphy: add compatible for rk3568 drm/rockchip: dsi: add rk3568 support phy/rockchip: inno-dsidphy: Add support for rk3568 .../display/rockchip/dw_mipi_dsi_rockchip.txt | 1 + .../bindings/phy/rockchip,px30-dsi-dphy.yaml | 1 + .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 51 - .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 204 ++ 4 files changed, 209 insertions(+), 48 deletions(-) -- 2.25.1
[RFC 1/4] dt-bindings: display: rockchip-dsi: add rk3568 compatible
From: Chris Morgan The rk3568 uses the same dw-mipi-dsi controller as previous Rockchip SOCs, so add a compatible string for it. Signed-off-by: Chris Morgan --- .../bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt index 39792f051d2d..9a223df8530c 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt @@ -8,6 +8,7 @@ Required properties: "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi" "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi" "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi" + "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi" - reg: Represent the physical address range of the controller. - interrupts: Represent the controller's interrupt to the CPU(s). - clocks, clock-names: Phandles to the controller's pll reference -- 2.25.1
[RFC 2/4] dt-bindings: phy: phy-rockchip-inno-dsidphy: add compatible for rk3568
From: Chris Morgan Add a compatible string for the rk3568 dsi-dphy. Signed-off-by: Chris Morgan --- .../devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml index 8a3032a3bd73..5c35e5ceec0b 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml @@ -18,6 +18,7 @@ properties: - rockchip,px30-dsi-dphy - rockchip,rk3128-dsi-dphy - rockchip,rk3368-dsi-dphy + - rockchip,rk3568-dsi-dphy reg: maxItems: 1 -- 2.25.1
[RFC 3/4] drm/rockchip: dsi: add rk3568 support
From: Chris Morgan
Add the compatible and GRF definitions for the RK3568 soc.
Signed-off-by: Chris Morgan
---
.../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 51 ++-
1 file changed, 49 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 110e83aad9bb..bf6948125b84 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -179,6 +179,23 @@
#define RK3399_TXRX_SRC_SEL_ISP0 BIT(4)
#define RK3399_TXRX_TURNREQUESTGENMASK(3, 0)
+#define RK3568_GRF_VO_CON2 0x0368
+#define RK3568_DSI0_SKEWCALHS (0x1f << 11)
+#define RK3568_DSI0_FORCETXSTOPMODE(0xf << 4)
+#define RK3568_DSI0_TURNDISABLEBIT(2)
+#define RK3568_DSI0_FORCERXMODEBIT(0)
+
+/*
+ * Note these registers do not appear in the datasheet, they are
+ * however present in the BSP driver which is where these values
+ * come from. Name GRF_VO_CON3 is assumed.
+ */
+#define RK3568_GRF_VO_CON3 0x36c
+#define RK3568_DSI1_SKEWCALHS (0x1f << 11)
+#define RK3568_DSI1_FORCETXSTOPMODE(0xf << 4)
+#define RK3568_DSI1_TURNDISABLEBIT(2)
+#define RK3568_DSI1_FORCERXMODEBIT(0)
+
#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
enum {
@@ -735,8 +752,9 @@ static void dw_mipi_dsi_rockchip_config(struct
dw_mipi_dsi_rockchip *dsi)
static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi,
int mux)
{
- regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
- mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
+ if (dsi->cdata->lcdsel_grf_reg < 0)
+ regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
+ mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
}
static int
@@ -963,6 +981,8 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev,
DRM_DEV_ERROR(dev, "Failed to create drm encoder\n");
goto out_pll_clk;
}
+ rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder,
+ dev->of_node, 0, 0);
ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder);
if (ret) {
@@ -1612,6 +1632,30 @@ static const struct rockchip_dw_dsi_chip_data
rk3399_chip_data[] = {
{ /* sentinel */ }
};
+static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = {
+ {
+ .reg = 0xfe06,
+ .lcdsel_grf_reg = -1,
+ .lanecfg1_grf_reg = RK3568_GRF_VO_CON2,
+ .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI0_SKEWCALHS |
+ RK3568_DSI0_FORCETXSTOPMODE |
+ RK3568_DSI0_TURNDISABLE |
+ RK3568_DSI0_FORCERXMODE),
+ .max_data_lanes = 4,
+ },
+ {
+ .reg = 0xfe07,
+ .lcdsel_grf_reg = -1,
+ .lanecfg1_grf_reg = RK3568_GRF_VO_CON3,
+ .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI1_SKEWCALHS |
+ RK3568_DSI1_FORCETXSTOPMODE |
+ RK3568_DSI1_TURNDISABLE |
+ RK3568_DSI1_FORCERXMODE),
+ .max_data_lanes = 4,
+ },
+ { /* sentinel */ }
+};
+
static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
{
.compatible = "rockchip,px30-mipi-dsi",
@@ -1622,6 +1666,9 @@ static const struct of_device_id
dw_mipi_dsi_rockchip_dt_ids[] = {
}, {
.compatible = "rockchip,rk3399-mipi-dsi",
.data = &rk3399_chip_data,
+ }, {
+.compatible = "rockchip,rk3568-mipi-dsi",
+.data = &rk3568_chip_data,
},
{ /* sentinel */ }
};
--
2.25.1
[RFC 4/4] phy/rockchip: inno-dsidphy: Add support for rk3568
From: Chris Morgan
Add support for the Rockchip RK3568 DSI-DPHY. Registers were taken from
the BSP kernel driver and wherever possible cross referenced with the
TRM.
Signed-off-by: Chris Morgan
---
.../phy/rockchip/phy-rockchip-inno-dsidphy.c | 204 ++
1 file changed, 158 insertions(+), 46 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
index 630e01b5c19b..2c5847faff63 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
@@ -84,9 +84,25 @@
#define DATA_LANE_0_SKEW_PHASE_MASKGENMASK(2, 0)
#define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0)
/* Analog Register Part: reg08 */
+#define PLL_POST_DIV_ENABLE_MASK BIT(5)
+#define PLL_POST_DIV_ENABLEBIT(5)
#define SAMPLE_CLOCK_DIRECTION_MASKBIT(4)
#define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4)
#define SAMPLE_CLOCK_DIRECTION_FORWARD 0
+#define LOWFRE_EN_MASK BIT(5)
+#define PLL_OUTPUT_FREQUENCY_DIV_BY_1 0
+#define PLL_OUTPUT_FREQUENCY_DIV_BY_2 1
+/* Analog Register Part: reg0b */
+#define CLOCK_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
+#define CLOCK_LANE_VOD_RANGE_SET(x)UPDATE(x, 3, 0)
+#define VOD_MIN_RANGE 0x1
+#define VOD_MID_RANGE 0x3
+#define VOD_BIG_RANGE 0x7
+#define VOD_MAX_RANGE 0xf
+/* Analog Register Part: reg1E */
+#define PLL_MODE_SEL_MASK GENMASK(6, 5)
+#define PLL_MODE_SEL_LVDS_MODE 0
+#define PLL_MODE_SEL_MIPI_MODE BIT(5)
/* Digital Register Part: reg00 */
#define REG_DIG_RSTN_MASK BIT(0)
#define REG_DIG_RSTN_NORMALBIT(0)
@@ -102,20 +118,22 @@
#define T_LPX_CNT_MASK GENMASK(5, 0)
#define T_LPX_CNT(x) UPDATE(x, 5, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */
+#define T_HS_ZERO_CNT_HI_MASK BIT(7)
+#define T_HS_ZERO_CNT_HI(x)UPDATE(x, 7, 7)
#define T_HS_PREPARE_CNT_MASK GENMASK(6, 0)
#define T_HS_PREPARE_CNT(x)UPDATE(x, 6, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */
-#define T_HS_ZERO_CNT_MASK GENMASK(5, 0)
-#define T_HS_ZERO_CNT(x) UPDATE(x, 5, 0)
+#define T_HS_ZERO_CNT_LO_MASK GENMASK(5, 0)
+#define T_HS_ZERO_CNT_LO(x)UPDATE(x, 5, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */
#define T_HS_TRAIL_CNT_MASKGENMASK(6, 0)
#define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */
-#define T_HS_EXIT_CNT_MASK GENMASK(4, 0)
-#define T_HS_EXIT_CNT(x) UPDATE(x, 4, 0)
+#define T_HS_EXIT_CNT_LO_MASK GENMASK(4, 0)
+#define T_HS_EXIT_CNT_LO(x)UPDATE(x, 4, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */
-#define T_CLK_POST_CNT_MASKGENMASK(3, 0)
-#define T_CLK_POST_CNT(x) UPDATE(x, 3, 0)
+#define T_CLK_POST_CNT_LO_MASK GENMASK(3, 0)
+#define T_CLK_POST_CNT_LO(x) UPDATE(x, 3, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */
#define LPDT_TX_PPI_SYNC_MASK BIT(2)
#define LPDT_TX_PPI_SYNC_ENABLEBIT(2)
@@ -129,9 +147,13 @@
#define T_CLK_PRE_CNT_MASK GENMASK(3, 0)
#define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */
+#define T_CLK_POST_CNT_HI_MASK GENMASK(7, 6)
+#define T_CLK_POST_CNT_HI(x) UPDATE(x, 7, 6)
#define T_TA_GO_CNT_MASK GENMASK(5, 0)
#define T_TA_GO_CNT(x) UPDATE(x, 5, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */
+#define T_HS_EXIT_CNT_HI_MASK BIT(6)
+#define T_HS_EXIT_CNT_HI(x)UPDATE(x, 6, 6)
#define T_TA_SURE_CNT_MASK GENMASK(5, 0)
#define T_TA_SURE_CNT(x) UPDATE(x, 5, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */
@@ -169,11 +191,23 @@
#define DSI_PHY_STATUS 0xb0
#define PHY_LOCK BIT(0)
+enum phy_max_rate {
+ MAX_1GHZ,
+ MAX_2_5GHZ,
+};
+
+struct inno_video_phy_plat_data {
+ const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table;
+ const unsigned int num_timings;
+ enum phy_max_rate max_rate;
+};
+
struct inno_dsidphy {
struct device *dev;
struct clk *ref_clk;
struct clk *pclk_phy;
struct
[RESEND 0/6 v2] Support Geekworm MZP280 Panel for Raspberry Pi
From: Chris Morgan This patch series is to add support for the MZP280 panel for the Raspberry Pi. This panel requires adding support for Mode 3 of the Raspberry Pi DPI connector, which necessitates a new media bus format. This patch series has been tested on my Raspberry Pi 4 with version 1 of the panel in question. Changes since V1: - Added documentation for vendor string. Signed-off-by: Chris Morgan Chris Morgan (6): dt-bindings: vendor-prefixes: Add Geekworm media: uapi: Document format MEDIA_BUS_FMT_RGB565_1X24_CPADHI media: uapi: add MEDIA_BUS_FMT_RGB565_1X24_CPADHI dt-bindings: display: simple: add Geekworm MZP280 Panel drm/panel: simple: add Geekworm MZP280 Panel drm/vc4: dpi: Support DPI interface in mode3 for RGB565 .../bindings/display/panel/panel-simple.yaml | 2 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + .../media/v4l/subdev-formats.rst | 37 +++ drivers/gpu/drm/panel/panel-simple.c | 29 +++ drivers/gpu/drm/vc4/vc4_dpi.c | 4 ++ include/uapi/linux/media-bus-format.h | 3 +- 6 files changed, 76 insertions(+), 1 deletion(-) -- 2.25.1
[RESEND 2/6 v2] media: uapi: Document format MEDIA_BUS_FMT_RGB565_1X24_CPADHI
From: Chris Morgan Add support for MEDIA_BUS_FMT_RGB565_1X24_CPADHI. This format is used by the Geekworm MZP280 panel which interfaces with the Raspberry Pi. Signed-off-by: Chris Morgan --- .../media/v4l/subdev-formats.rst | 37 +++ 1 file changed, 37 insertions(+) diff --git a/Documentation/userspace-api/media/v4l/subdev-formats.rst b/Documentation/userspace-api/media/v4l/subdev-formats.rst index 0cbc045d5..e43e07634 100644 --- a/Documentation/userspace-api/media/v4l/subdev-formats.rst +++ b/Documentation/userspace-api/media/v4l/subdev-formats.rst @@ -624,6 +624,43 @@ The following tables list existing packed RGB formats. - b\ :sub:`2` - b\ :sub:`1` - b\ :sub:`0` +* .. _MEDIA_BUS_FMT_RGB565_1X24_CPADHI: + + - MEDIA_BUS_FMT_RGB565_1X24_CPADHI + - 0x101e + - + - + - + - + - + - + - + - + - + - 0 + - 0 + - 0 + - r\ :sub:`4` + - r\ :sub:`3` + - r\ :sub:`2` + - r\ :sub:`1` + - r\ :sub:`0` + - 0 + - 0 + - g\ :sub:`5` + - g\ :sub:`4` + - g\ :sub:`3` + - g\ :sub:`2` + - g\ :sub:`1` + - g\ :sub:`0` + - 0 + - 0 + - 0 + - b\ :sub:`4` + - b\ :sub:`3` + - b\ :sub:`2` + - b\ :sub:`1` + - b\ :sub:`0` * .. _MEDIA-BUS-FMT-BGR565-2X8-BE: - MEDIA_BUS_FMT_BGR565_2X8_BE -- 2.25.1
[RESEND 1/6 v2] dt-bindings: vendor-prefixes: Add Geekworm
From: Chris Morgan Add vendor prefix for Geekworm (https://geekworm.com). Signed-off-by: Chris Morgan --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 294093d45..c0c7627c6 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -455,6 +455,8 @@ patternProperties: description: General Electric Company "^geekbuying,.*": description: GeekBuying + "^geekworm,.*": +description: Geekworm "^gef,.*": description: GE Fanuc Intelligent Platforms Embedded Systems, Inc. "^GEFanuc,.*": -- 2.25.1
[RESEND 5/6 v2] drm/panel: simple: add Geekworm MZP280 Panel
From: Chris Morgan
Add support for the Geekworm MZP280 Panel
Signed-off-by: Chris Morgan
Acked-by: Maxime Ripard
---
drivers/gpu/drm/panel/panel-simple.c | 29
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index 9e46db5e3..cbc1a4fd1 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1824,6 +1824,32 @@ static const struct panel_desc friendlyarm_hd702e = {
},
};
+static const struct drm_display_mode geekworm_mzp280_mode = {
+ .clock = 32000,
+ .hdisplay = 480,
+ .hsync_start = 480 + 41,
+ .hsync_end = 480 + 41 + 20,
+ .htotal = 480 + 41 + 20 + 60,
+ .vdisplay = 640,
+ .vsync_start = 640 + 5,
+ .vsync_end = 640 + 5 + 10,
+ .vtotal = 640 + 5 + 10 + 10,
+ .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
+};
+
+static const struct panel_desc geekworm_mzp280 = {
+ .modes = &geekworm_mzp280_mode,
+ .num_modes = 1,
+ .bpc = 6,
+ .size = {
+ .width = 47,
+ .height = 61,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB565_1X24_CPADHI,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
+ .connector_type = DRM_MODE_CONNECTOR_DPI,
+};
+
static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
.clock = 9000,
.hdisplay = 480,
@@ -3790,6 +3816,9 @@ static const struct of_device_id platform_of_match[] = {
}, {
.compatible = "friendlyarm,hd702e",
.data = &friendlyarm_hd702e,
+ }, {
+ .compatible = "geekworm,mzp280",
+ .data = &geekworm_mzp280,
}, {
.compatible = "giantplus,gpg482739qs5",
.data = &giantplus_gpg482739qs5
--
2.25.1
[RESEND 4/6 v2] dt-bindings: display: simple: add Geekworm MZP280 Panel
From: Chris Morgan The Geekworm MZP280 panel is a 480x640 (portrait) panel with a capacitive touch interface and a 40 pin header meant to interface directly with the Raspberry Pi. The screen is 2.8 inches diagonally, and there appear to be at least 4 distinct versions all with the same panel timings. Timings were derived from drivers posted on the github located here: https://github.com/tianyoujian/MZDPI/tree/master/vga Additional details about this panel family can be found here: https://wiki.geekworm.com/2.8_inch_Touch_Screen_for_Pi_zero Signed-off-by: Chris Morgan --- .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 62f5f050c..3d03d8276 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -148,6 +148,8 @@ properties: - frida,frd350h54004 # FriendlyELEC HD702E 800x1280 LCD panel - friendlyarm,hd702e +# Geekworm MZP280 2.8" 480x640 LCD panel with capacitive touch + - geekworm,mzp280 # GiantPlus GPG48273QS5 4.3" (480x272) WQVGA TFT LCD panel - giantplus,gpg48273qs5 # GiantPlus GPM940B0 3.0" QVGA TFT LCD panel -- 2.25.1
[RESEND 6/6 v2] drm/vc4: dpi: Support DPI interface in mode3 for RGB565
From: Chris Morgan
Add support for the VC4 DPI driver to utilize DPI mode 3. This is
defined here as xxxRxxGGxxxB:
https://www.raspberrypi.com/documentation/computers/raspberry-pi.html#parallel-display-interface-dpi
This mode is required to use the Geekworm MZP280 DPI display.
Signed-off-by: Chris Morgan
Reviewed-by: Dave Stevenson
---
drivers/gpu/drm/vc4/vc4_dpi.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_dpi.c b/drivers/gpu/drm/vc4/vc4_dpi.c
index c180eb60b..3c58ade25 100644
--- a/drivers/gpu/drm/vc4/vc4_dpi.c
+++ b/drivers/gpu/drm/vc4/vc4_dpi.c
@@ -173,6 +173,10 @@ static void vc4_dpi_encoder_enable(struct drm_encoder
*encoder)
dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3,
DPI_FORMAT);
break;
+ case MEDIA_BUS_FMT_RGB565_1X24_CPADHI:
+ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_2,
+ DPI_FORMAT);
+ break;
default:
DRM_ERROR("Unknown media bus format %d\n", bus_format);
break;
--
2.25.1
[RESEND 3/6 v2] media: uapi: add MEDIA_BUS_FMT_RGB565_1X24_CPADHI
From: Chris Morgan Add the MEDIA_BUS_FMT_RGB565_1X24_CPADHI format used by the Geekworm MZP280 panel for the Raspberry Pi. Signed-off-by: Chris Morgan --- include/uapi/linux/media-bus-format.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h index 0dfc11ee2..a7b765498 100644 --- a/include/uapi/linux/media-bus-format.h +++ b/include/uapi/linux/media-bus-format.h @@ -34,13 +34,14 @@ #define MEDIA_BUS_FMT_FIXED0x0001 -/* RGB - next is 0x101e */ +/* RGB - next is 0x101f */ #define MEDIA_BUS_FMT_RGB444_1X12 0x1016 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002 #define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003 #define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004 #define MEDIA_BUS_FMT_RGB565_1X16 0x1017 +#define MEDIA_BUS_FMT_RGB565_1X24_CPADHI 0x101e #define MEDIA_BUS_FMT_BGR565_2X8_BE0x1005 #define MEDIA_BUS_FMT_BGR565_2X8_LE0x1006 #define MEDIA_BUS_FMT_RGB565_2X8_BE0x1007 -- 2.25.1
[PATCH V2 0/2] chrontel-ch7033: Add byteswap order option
From: Chris Morgan This series adds the ability to set the byteswap order in the chrontel ch7033 driver via an optional devicetree node. This is necessary because the HDMI DIP of the NTC CHIP requires a byteswap order that differs from the default value of the driver. Changes from V1: - Updated devicetree documentation to be easier to understand. Signed-off-by: Chris Morgan Chris Morgan (2): dt-bindings: Add byteswap order to chrontel ch7033 drm/bridge: chrontel-ch7033: Add byteswap order setting .../bindings/display/bridge/chrontel,ch7033.yaml | 13 + drivers/gpu/drm/bridge/chrontel-ch7033.c | 15 +-- 2 files changed, 26 insertions(+), 2 deletions(-) -- 2.25.1
[PATCH V2 1/2] dt-bindings: Add byteswap order to chrontel ch7033
From: Chris Morgan Update dt-binding documentation to add support for setting byteswap of chrontel ch7033. New property name of chrontel,byteswap added to set the byteswap order. This property is optional. Signed-off-by: Chris Morgan Reviewed-by: Robert Foss --- .../bindings/display/bridge/chrontel,ch7033.yaml| 13 + 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml index bb6289c7d375..984b90893583 100644 --- a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml +++ b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml @@ -14,6 +14,19 @@ properties: compatible: const: chrontel,ch7033 + chrontel,byteswap: +$ref: /schemas/types.yaml#/definitions/uint8 +enum: + - 0 # BYTE_SWAP_RGB + - 1 # BYTE_SWAP_RBG + - 2 # BYTE_SWAP_GRB + - 3 # BYTE_SWAP_GBR + - 4 # BYTE_SWAP_BRG + - 5 # BYTE_SWAP_BGR +description: | + Set the byteswap value of the bridge. This is optional and if not + set value of BYTE_SWAP_BGR is used. + reg: maxItems: 1 description: I2C address of the device -- 2.25.1
[PATCH V2 2/2] drm/bridge: chrontel-ch7033: Add byteswap order setting
From: Chris Morgan
Add the option to set the byteswap order in the devicetree. For the
official HDMI DIP for the NTC CHIP the byteswap order needs to be
RGB, however the driver sets it as BGR. With this patch the driver
will remain at BGR unless manually specified via devicetree.
Signed-off-by: Chris Morgan
Reviewed-by: Robert Foss
---
drivers/gpu/drm/bridge/chrontel-ch7033.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c
b/drivers/gpu/drm/bridge/chrontel-ch7033.c
index ba060277c3fd..c5719908ce2d 100644
--- a/drivers/gpu/drm/bridge/chrontel-ch7033.c
+++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c
@@ -68,6 +68,7 @@ enum {
BYTE_SWAP_GBR = 3,
BYTE_SWAP_BRG = 4,
BYTE_SWAP_BGR = 5,
+ BYTE_SWAP_MAX = 6,
};
/* Page 0, Register 0x19 */
@@ -355,6 +356,8 @@ static void ch7033_bridge_mode_set(struct drm_bridge
*bridge,
int hsynclen = mode->hsync_end - mode->hsync_start;
int vbporch = mode->vsync_start - mode->vdisplay;
int vsynclen = mode->vsync_end - mode->vsync_start;
+ u8 byte_swap;
+ int ret;
/*
* Page 4
@@ -398,8 +401,16 @@ static void ch7033_bridge_mode_set(struct drm_bridge
*bridge,
regmap_write(priv->regmap, 0x15, vbporch);
regmap_write(priv->regmap, 0x16, vsynclen);
- /* Input color swap. */
- regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR);
+ /* Input color swap. Byte order is optional and will default to
+* BYTE_SWAP_BGR to preserve backwards compatibility with existing
+* driver.
+*/
+ ret = of_property_read_u8(priv->bridge.of_node, "chrontel,byteswap",
+ &byte_swap);
+ if (!ret && byte_swap < BYTE_SWAP_MAX)
+ regmap_update_bits(priv->regmap, 0x18, SWAP, byte_swap);
+ else
+ regmap_update_bits(priv->regmap, 0x18, SWAP, BYTE_SWAP_BGR);
/* Input clock and sync polarity. */
regmap_update_bits(priv->regmap, 0x19, 0x1, mode->clock >> 16);
--
2.25.1
[PATCH v2 0/5] rockchip-dsi for rk3568
From: Chris Morgan This series adds support for the dsi and dphy controllers on the Rockchip RK3568. I can confirm that for the Rockchip RK3568 this current series DOES WORK now, but it requires rolling back clk changes made for the HDMI driver. If the clock changes are not rolled back, the image on the screen is shifted about 100 pixels to the right. Clk changes in question: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/clk/rockchip/clk-rk3568.c?id=ff3187eabb5ce478d15b6ed62eb286756adefac3 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/clk/rockchip/clk-rk3568.c?id=6e69052f01d9131388cfcfaee929120118a267f4 Tested on an Anbernic RG503 and RG353P with clock changes rolled back, the hardware works correctly on both devices. Changes since RFCv1: - Identified cause of image shift (clock changes). - Noted that driver works now. - Added devicetree nodes for rk356x.dtsi. Chris Morgan (5): dt-bindings: display: rockchip-dsi: add rk3568 compatible dt-bindings: phy-rockchip-inno-dsidphy: add compatible for rk3568 drm/rockchip: dsi: add rk3568 support phy/rockchip: inno-dsidphy: Add support for rk3568 arm64: dts: rockchip: Add DSI and DSI-DPHY nodes to rk356x .../display/rockchip/dw_mipi_dsi_rockchip.txt | 1 + .../bindings/phy/rockchip,px30-dsi-dphy.yaml | 1 + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 72 +++ .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 51 - .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 204 ++ 5 files changed, 281 insertions(+), 48 deletions(-) -- 2.25.1
[PATCH v2 1/5] dt-bindings: display: rockchip-dsi: add rk3568 compatible
From: Chris Morgan The rk3568 uses the same dw-mipi-dsi controller as previous Rockchip SOCs, so add a compatible string for it. Signed-off-by: Chris Morgan --- .../bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt index 39792f051d2d..9a223df8530c 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt @@ -8,6 +8,7 @@ Required properties: "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi" "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi" "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi" + "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi" - reg: Represent the physical address range of the controller. - interrupts: Represent the controller's interrupt to the CPU(s). - clocks, clock-names: Phandles to the controller's pll reference -- 2.25.1
[PATCH v2 2/5] dt-bindings: phy-rockchip-inno-dsidphy: add compatible for rk3568
From: Chris Morgan Add a compatible string for the rk3568 dsi-dphy. Signed-off-by: Chris Morgan --- .../devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml index 8a3032a3bd73..5c35e5ceec0b 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml @@ -18,6 +18,7 @@ properties: - rockchip,px30-dsi-dphy - rockchip,rk3128-dsi-dphy - rockchip,rk3368-dsi-dphy + - rockchip,rk3568-dsi-dphy reg: maxItems: 1 -- 2.25.1
[PATCH v2 3/5] drm/rockchip: dsi: add rk3568 support
From: Chris Morgan
Add the compatible and GRF definitions for the RK3568 soc.
Signed-off-by: Chris Morgan
---
.../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 51 ++-
1 file changed, 49 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 110e83aad9bb..bf6948125b84 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -179,6 +179,23 @@
#define RK3399_TXRX_SRC_SEL_ISP0 BIT(4)
#define RK3399_TXRX_TURNREQUESTGENMASK(3, 0)
+#define RK3568_GRF_VO_CON2 0x0368
+#define RK3568_DSI0_SKEWCALHS (0x1f << 11)
+#define RK3568_DSI0_FORCETXSTOPMODE(0xf << 4)
+#define RK3568_DSI0_TURNDISABLEBIT(2)
+#define RK3568_DSI0_FORCERXMODEBIT(0)
+
+/*
+ * Note these registers do not appear in the datasheet, they are
+ * however present in the BSP driver which is where these values
+ * come from. Name GRF_VO_CON3 is assumed.
+ */
+#define RK3568_GRF_VO_CON3 0x36c
+#define RK3568_DSI1_SKEWCALHS (0x1f << 11)
+#define RK3568_DSI1_FORCETXSTOPMODE(0xf << 4)
+#define RK3568_DSI1_TURNDISABLEBIT(2)
+#define RK3568_DSI1_FORCERXMODEBIT(0)
+
#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
enum {
@@ -735,8 +752,9 @@ static void dw_mipi_dsi_rockchip_config(struct
dw_mipi_dsi_rockchip *dsi)
static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi,
int mux)
{
- regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
- mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
+ if (dsi->cdata->lcdsel_grf_reg < 0)
+ regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
+ mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
}
static int
@@ -963,6 +981,8 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev,
DRM_DEV_ERROR(dev, "Failed to create drm encoder\n");
goto out_pll_clk;
}
+ rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder,
+ dev->of_node, 0, 0);
ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder);
if (ret) {
@@ -1612,6 +1632,30 @@ static const struct rockchip_dw_dsi_chip_data
rk3399_chip_data[] = {
{ /* sentinel */ }
};
+static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = {
+ {
+ .reg = 0xfe06,
+ .lcdsel_grf_reg = -1,
+ .lanecfg1_grf_reg = RK3568_GRF_VO_CON2,
+ .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI0_SKEWCALHS |
+ RK3568_DSI0_FORCETXSTOPMODE |
+ RK3568_DSI0_TURNDISABLE |
+ RK3568_DSI0_FORCERXMODE),
+ .max_data_lanes = 4,
+ },
+ {
+ .reg = 0xfe07,
+ .lcdsel_grf_reg = -1,
+ .lanecfg1_grf_reg = RK3568_GRF_VO_CON3,
+ .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI1_SKEWCALHS |
+ RK3568_DSI1_FORCETXSTOPMODE |
+ RK3568_DSI1_TURNDISABLE |
+ RK3568_DSI1_FORCERXMODE),
+ .max_data_lanes = 4,
+ },
+ { /* sentinel */ }
+};
+
static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
{
.compatible = "rockchip,px30-mipi-dsi",
@@ -1622,6 +1666,9 @@ static const struct of_device_id
dw_mipi_dsi_rockchip_dt_ids[] = {
}, {
.compatible = "rockchip,rk3399-mipi-dsi",
.data = &rk3399_chip_data,
+ }, {
+.compatible = "rockchip,rk3568-mipi-dsi",
+.data = &rk3568_chip_data,
},
{ /* sentinel */ }
};
--
2.25.1
[PATCH v2 5/5] arm64: dts: rockchip: Add DSI and DSI-DPHY nodes to rk356x
From: Chris Morgan
This adds the DSI controller nodes and DSI-DPHY controller nodes to the
rk356x device tree.
Signed-off-by: Chris Morgan
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 72
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 319981c3e9f7..d150568fde82 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -699,6 +699,54 @@ vop_mmu: iommu@fe043e00 {
status = "disabled";
};
+ dsi0: dsi@fe06 {
+ compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x00 0xfe06 0x00 0x1>;
+ interrupts = ;
+ clock-names = "pclk", "hclk";
+ clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
+ phy-names = "dphy";
+ phys = <&mipi_dphy0>;
+ power-domains = <&power RK3568_PD_VO>;
+ reset-names = "apb";
+ resets = <&cru SRST_P_DSITX_0>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+ };
+ };
+
+ dsi1: dsi@fe07 {
+ compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x0 0xfe07 0x0 0x1>;
+ interrupts = ;
+ clock-names = "pclk", "hclk";
+ clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
+ phy-names = "dphy";
+ phys = <&mipi_dphy1>;
+ power-domains = <&power RK3568_PD_VO>;
+ reset-names = "apb";
+ resets = <&cru SRST_P_DSITX_1>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+ };
+ };
+
hdmi: hdmi@fe0a {
compatible = "rockchip,rk3568-dw-hdmi";
reg = <0x0 0xfe0a 0x0 0x2>;
@@ -1594,6 +1642,30 @@ combphy2: phy@fe84 {
status = "disabled";
};
+ mipi_dphy0: mipi-dphy@fe85 {
+ compatible = "rockchip,rk3568-dsi-dphy";
+ reg = <0x0 0xfe85 0x0 0x1>;
+ clock-names = "ref", "pclk";
+ clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
+ #phy-cells = <0>;
+ power-domains = <&power RK3568_PD_VO>;
+ reset-names = "apb";
+ resets = <&cru SRST_P_MIPIDSIPHY0>;
+ status = "disabled";
+ };
+
+ mipi_dphy1: mipi-dphy@fe86 {
+ compatible = "rockchip,rk3568-dsi-dphy";
+ reg = <0x0 0xfe86 0x0 0x1>;
+ clock-names = "ref", "pclk";
+ clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
+ #phy-cells = <0>;
+ power-domains = <&power RK3568_PD_VO>;
+ reset-names = "apb";
+ resets = <&cru SRST_P_MIPIDSIPHY1>;
+ status = "disabled";
+ };
+
usb2phy0: usb2phy@fe8a {
compatible = "rockchip,rk3568-usb2phy";
reg = <0x0 0xfe8a 0x0 0x1>;
--
2.25.1
[PATCH v2 4/5] phy/rockchip: inno-dsidphy: Add support for rk3568
From: Chris Morgan
Add support for the Rockchip RK3568 DSI-DPHY. Registers were taken from
the BSP kernel driver and wherever possible cross referenced with the
TRM.
Signed-off-by: Chris Morgan
---
.../phy/rockchip/phy-rockchip-inno-dsidphy.c | 204 ++
1 file changed, 158 insertions(+), 46 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
index 630e01b5c19b..2c5847faff63 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
@@ -84,9 +84,25 @@
#define DATA_LANE_0_SKEW_PHASE_MASKGENMASK(2, 0)
#define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0)
/* Analog Register Part: reg08 */
+#define PLL_POST_DIV_ENABLE_MASK BIT(5)
+#define PLL_POST_DIV_ENABLEBIT(5)
#define SAMPLE_CLOCK_DIRECTION_MASKBIT(4)
#define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4)
#define SAMPLE_CLOCK_DIRECTION_FORWARD 0
+#define LOWFRE_EN_MASK BIT(5)
+#define PLL_OUTPUT_FREQUENCY_DIV_BY_1 0
+#define PLL_OUTPUT_FREQUENCY_DIV_BY_2 1
+/* Analog Register Part: reg0b */
+#define CLOCK_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
+#define CLOCK_LANE_VOD_RANGE_SET(x)UPDATE(x, 3, 0)
+#define VOD_MIN_RANGE 0x1
+#define VOD_MID_RANGE 0x3
+#define VOD_BIG_RANGE 0x7
+#define VOD_MAX_RANGE 0xf
+/* Analog Register Part: reg1E */
+#define PLL_MODE_SEL_MASK GENMASK(6, 5)
+#define PLL_MODE_SEL_LVDS_MODE 0
+#define PLL_MODE_SEL_MIPI_MODE BIT(5)
/* Digital Register Part: reg00 */
#define REG_DIG_RSTN_MASK BIT(0)
#define REG_DIG_RSTN_NORMALBIT(0)
@@ -102,20 +118,22 @@
#define T_LPX_CNT_MASK GENMASK(5, 0)
#define T_LPX_CNT(x) UPDATE(x, 5, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */
+#define T_HS_ZERO_CNT_HI_MASK BIT(7)
+#define T_HS_ZERO_CNT_HI(x)UPDATE(x, 7, 7)
#define T_HS_PREPARE_CNT_MASK GENMASK(6, 0)
#define T_HS_PREPARE_CNT(x)UPDATE(x, 6, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */
-#define T_HS_ZERO_CNT_MASK GENMASK(5, 0)
-#define T_HS_ZERO_CNT(x) UPDATE(x, 5, 0)
+#define T_HS_ZERO_CNT_LO_MASK GENMASK(5, 0)
+#define T_HS_ZERO_CNT_LO(x)UPDATE(x, 5, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */
#define T_HS_TRAIL_CNT_MASKGENMASK(6, 0)
#define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */
-#define T_HS_EXIT_CNT_MASK GENMASK(4, 0)
-#define T_HS_EXIT_CNT(x) UPDATE(x, 4, 0)
+#define T_HS_EXIT_CNT_LO_MASK GENMASK(4, 0)
+#define T_HS_EXIT_CNT_LO(x)UPDATE(x, 4, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */
-#define T_CLK_POST_CNT_MASKGENMASK(3, 0)
-#define T_CLK_POST_CNT(x) UPDATE(x, 3, 0)
+#define T_CLK_POST_CNT_LO_MASK GENMASK(3, 0)
+#define T_CLK_POST_CNT_LO(x) UPDATE(x, 3, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */
#define LPDT_TX_PPI_SYNC_MASK BIT(2)
#define LPDT_TX_PPI_SYNC_ENABLEBIT(2)
@@ -129,9 +147,13 @@
#define T_CLK_PRE_CNT_MASK GENMASK(3, 0)
#define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */
+#define T_CLK_POST_CNT_HI_MASK GENMASK(7, 6)
+#define T_CLK_POST_CNT_HI(x) UPDATE(x, 7, 6)
#define T_TA_GO_CNT_MASK GENMASK(5, 0)
#define T_TA_GO_CNT(x) UPDATE(x, 5, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */
+#define T_HS_EXIT_CNT_HI_MASK BIT(6)
+#define T_HS_EXIT_CNT_HI(x)UPDATE(x, 6, 6)
#define T_TA_SURE_CNT_MASK GENMASK(5, 0)
#define T_TA_SURE_CNT(x) UPDATE(x, 5, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */
@@ -169,11 +191,23 @@
#define DSI_PHY_STATUS 0xb0
#define PHY_LOCK BIT(0)
+enum phy_max_rate {
+ MAX_1GHZ,
+ MAX_2_5GHZ,
+};
+
+struct inno_video_phy_plat_data {
+ const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table;
+ const unsigned int num_timings;
+ enum phy_max_rate max_rate;
+};
+
struct inno_dsidphy {
struct device *dev;
struct clk *ref_clk;
struct clk *pclk_phy;
struct
[PATCH 1/2] dt-bindings: display: panel: Add Samsung AMS495QA01 panel bindings
From: Chris Morgan
Add documentation for the Samsung AMS495QA01 panel.
Signed-off-by: Chris Morgan
---
.../display/panel/samsung,ams495qa01.yaml | 49 +++
1 file changed, 49 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
diff --git
a/Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
b/Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
new file mode 100644
index ..e7373846e7d8
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/samsung,ams495qa01.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung AMS495QA01 4.95in 960x544 DSI/SPI panel
+
+maintainers:
+ - Chris Morgan
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+const: samsung,ams495qa01
+ reg: true
+ reset-gpios: true
+ elvdd-supply:
+description: regulator that supplies voltage to the panel
+ enable-gpios: true
+ port: true
+ vdd-supply:
+description: regulator that supplies voltage to panel logic
+
+required:
+ - compatible
+ - reg
+ - elvdd-supply
+ - vdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+spi {
+#address-cells = <1>;
+#size-cells = <0>;
+panel@0 {
+compatible = "samsung,ams495qa01";
+reg = <0>;
+backlight = <&backlight>;
+elvdd-supply = <&vcc_sys>;
+vdd-supply = <&vcc3v3_lcd0_n>;
+};
+};
+
+...
--
2.25.1
[PATCH 0/2] drm/panel: Add Samsung AMS495QA01 Panel
From: Chris Morgan Add the Samsung AMS495QA01 panel as found on the Anbernic RG503. This panel uses DSI to receive video signals, but 3-wire SPI to receive command signals. Chris Morgan (2): dt-bindings: display: panel: Add Samsung AMS495QA01 panel bindings drm/panel: Add Samsung AMS495QA01 MIPI-DSI LCD panel .../display/panel/samsung,ams495qa01.yaml | 49 ++ drivers/gpu/drm/panel/Kconfig | 10 + drivers/gpu/drm/panel/Makefile| 1 + .../gpu/drm/panel/panel-samsung-ams495qa01.c | 468 ++ 4 files changed, 528 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml create mode 100644 drivers/gpu/drm/panel/panel-samsung-ams495qa01.c -- 2.25.1
[PATCH 2/2] drm/panel: Add Samsung AMS495QA01 MIPI-DSI LCD panel
From: Chris Morgan
Support Samsung AMS495QA01 panel as found on the Anbernic RG503. Note
This panel receives video signals via DSI, however it receives
commands via 3-wire SPI.
Signed-off-by: Chris Morgan
---
drivers/gpu/drm/panel/Kconfig | 10 +
drivers/gpu/drm/panel/Makefile| 1 +
.../gpu/drm/panel/panel-samsung-ams495qa01.c | 468 ++
3 files changed, 479 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-samsung-ams495qa01.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index a9043eacce97..954b66a2adee 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -444,6 +444,16 @@ config DRM_PANEL_RONBO_RB070D30
Say Y here if you want to enable support for Ronbo Electronics
RB070D30 1024x600 DSI panel.
+config DRM_PANEL_SAMSUNG_AMS495QA01
+ tristate "Samsung AMS495QA01 DSI panel"
+ depends on OF && SPI
+ depends on DRM_MIPI_DSI
+ select DRM_MIPI_DBI
+ help
+ DRM panel driver for the Samsung AMS495QA01 panel. This panel
+ receives video data via DSI but commands via 3-Wire 9-bit
+ SPI.
+
config DRM_PANEL_SAMSUNG_ATNA33XC20
tristate "Samsung ATNA33XC20 eDP panel"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 34e717382dbb..de0b57baf851 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN) +=
panel-raspberrypi-touchscreen
obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM67191) += panel-raydium-rm67191.o
obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM68200) += panel-raydium-rm68200.o
obj-$(CONFIG_DRM_PANEL_RONBO_RB070D30) += panel-ronbo-rb070d30.o
+obj-$(CONFIG_DRM_PANEL_SAMSUNG_AMS495QA01) += panel-samsung-ams495qa01.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20) += panel-samsung-atna33xc20.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_DB7430) += panel-samsung-db7430.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o
diff --git a/drivers/gpu/drm/panel/panel-samsung-ams495qa01.c
b/drivers/gpu/drm/panel/panel-samsung-ams495qa01.c
new file mode 100644
index ..60afea40a60e
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-samsung-ams495qa01.c
@@ -0,0 +1,468 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung ams495qa01 MIPI-DSI panel driver
+ * Copyright (C) 2022 Chris Morgan
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+struct ams495qa01 {
+ /** @dev: the container device */
+ struct device *dev;
+ /** @dbi: the DBI bus abstraction handle */
+ struct mipi_dbi dbi;
+ /** @panel: the DRM panel instance for this device */
+ struct drm_panel panel;
+ /** @reset: reset GPIO line */
+ struct gpio_desc *reset;
+ /** @enable: enable GPIO line */
+ struct gpio_desc *enable;
+ /** @regulators: VDD and ELVDD supply regulators */
+ struct regulator_bulk_data regulators[2];
+ /** @dsi_dev: DSI child device (panel) */
+ struct mipi_dsi_device *dsi_dev;
+ /** @bl_dev: pseudo-backlight device for oled panel */
+ struct backlight_device *bl_dev;
+};
+
+static const struct drm_display_mode ams495qa01_mode = {
+ .clock = 33500,
+ .hdisplay = 960,
+ .hsync_start = 960 + 10,
+ .hsync_end = 960 + 10 + 2,
+ .htotal = 960 + 10 + 2 + 10,
+ .vdisplay = 544,
+ .vsync_start = 544 + 10,
+ .vsync_end = 544 + 10 + 2,
+ .vtotal = 544 + 10 + 2 + 10,
+ .width_mm = 117,
+ .height_mm = 74,
+ .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+};
+
+#define NUM_GAMMA_LEVELS 16
+#define GAMMA_TABLE_COUNT 23
+#define MAX_BRIGHTNESS (NUM_GAMMA_LEVELS - 1)
+
+/* Table of gamma values provided in datasheet */
+static u8 ams495qa01_gamma[NUM_GAMMA_LEVELS][GAMMA_TABLE_COUNT] = {
+ {0x01, 0x79, 0x78, 0x8d, 0xd9, 0xdf, 0xd5, 0xcb, 0xcf, 0xc5,
+0xe5, 0xe0, 0xe4, 0xdc, 0xb8, 0xd4, 0xfa, 0xed, 0xe6, 0x2f,
+0x00, 0x2f},
+ {0x01, 0x7d, 0x7c, 0x92, 0xd7, 0xdd, 0xd2, 0xcb, 0xd0, 0xc6,
+0xe5, 0xe1, 0xe3, 0xda, 0xbd, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+0x00, 0x2f},
+ {0x01, 0x7f, 0x7e, 0x95, 0xd7, 0xde, 0xd2, 0xcb, 0xcf, 0xc5,
+0xe5, 0xe3, 0xe3, 0xda, 0xbf, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+0x00, 0x2f},
+ {0x01, 0x82, 0x81, 0x99, 0xd6, 0xdd, 0xd1, 0xca, 0xcf, 0xc3,
+0xe4, 0xe3, 0xe3, 0xda, 0xc2, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+0x00, 0x2f},
+ {0x01, 0x84, 0x83, 0x9b, 0xd7, 0xde, 0xd2, 0xc8, 0xce, 0xc2,
+0xe4, 0xe3, 0xe2, 0xd9, 0xc3, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+0x00, 0x2f},
+ {0x01, 0x87, 0x86, 0x9f, 0xd6, 0xdd, 0xd1, 0xc7, 0xce, 0xc1,
+0xe4, 0xe3,
[PATCH 0/2] drm/panel: Add NewVision NV3051D Panels
From: Chris Morgan Add the NewVision NV3051D panel as found on the Anbernic RG353P and RG353V. The underlying LCD panel itself is unknown (the NV3051D is the controller), so the device name is used for the panel. Chris Morgan (2): dt-bindings: display: panel: Add NewVision NV3051D panel bindings drm/panel: Add NewVision NV3051D MIPI-DSI LCD panel .../display/panel/newvision,nv3051d.yaml | 48 ++ drivers/gpu/drm/panel/Kconfig | 9 + drivers/gpu/drm/panel/Makefile| 1 + .../gpu/drm/panel/panel-newvision-nv3051d.c | 478 ++ 4 files changed, 536 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml create mode 100644 drivers/gpu/drm/panel/panel-newvision-nv3051d.c -- 2.25.1
[PATCH 2/2] drm/panel: Add NewVision NV3051D MIPI-DSI LCD panel
From: Chris Morgan
Support NewVision NV3051D panels as found on the Anbernic RG353P and
RG353V. The underlying panel part number for the RG353x devices is
unknown, so the device name is used instead.
Signed-off-by: Chris Morgan
---
drivers/gpu/drm/panel/Kconfig | 9 +
drivers/gpu/drm/panel/Makefile| 1 +
.../gpu/drm/panel/panel-newvision-nv3051d.c | 478 ++
3 files changed, 488 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-newvision-nv3051d.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index a9043eacce97..7258d28dda2f 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -296,6 +296,15 @@ config DRM_PANEL_NEC_NL8048HL11
panel (found on the Zoom2/3/3630 SDP boards). To compile this driver
as a module, choose M here.
+config DRM_PANEL_NEWVISION_NV3051D
+ tristate "NewVision NV3051D DSI panel"
+ depends on OF
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ help
+ This driver supports the NV3051D based panel found on the Anbernic
+ RG353P and RG353V.
+
config DRM_PANEL_NEWVISION_NV3052C
tristate "NewVision NV3052C RGB/SPI panel"
depends on OF && SPI
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 34e717382dbb..cb03b3a82738 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829) +=
panel-leadtek-ltk500hd1829.o
obj-$(CONFIG_DRM_PANEL_LG_LB035Q02) += panel-lg-lb035q02.o
obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
obj-$(CONFIG_DRM_PANEL_NEC_NL8048HL11) += panel-nec-nl8048hl11.o
+obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3051D) += panel-newvision-nv3051d.o
obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3052C) += panel-newvision-nv3052c.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35510) += panel-novatek-nt35510.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35560) += panel-novatek-nt35560.o
diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3051d.c
b/drivers/gpu/drm/panel/panel-newvision-nv3051d.c
new file mode 100644
index ..c46edd4df765
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-newvision-nv3051d.c
@@ -0,0 +1,478 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * NV3051D MIPI-DSI panel driver for Anbernic RG353x
+ * Copyright (C) 2022 Chris Morgan
+ *
+ * based on
+ *
+ * Elida kd35t133 3.5" MIPI-DSI panel driver
+ * Copyright (C) Theobroma Systems 2020
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+
+struct panel_nv3051d {
+ struct device *dev;
+ struct drm_panel panel;
+ struct gpio_desc *reset_gpio;
+ struct regulator *vdd;
+ bool prepared;
+};
+
+static inline struct panel_nv3051d *panel_to_panelnv3051d(struct drm_panel
*panel)
+{
+ return container_of(panel, struct panel_nv3051d, panel);
+}
+
+#define dsi_dcs_write_seq(dsi, cmd, seq...) do { \
+ static const u8 b[] = { cmd, seq }; \
+ int ret;\
+ ret = mipi_dsi_dcs_write_buffer(dsi, b, ARRAY_SIZE(b)); \
+ if (ret < 0)\
+ return ret; \
+ } while (0)
+
+static int panel_nv3051d_init_sequence(struct panel_nv3051d *ctx)
+{
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+
+ /*
+* Init sequence was supplied by device vendor with no
+* documentation.
+*/
+
+ dsi_dcs_write_seq(dsi, 0xFF, 0x30);
+ dsi_dcs_write_seq(dsi, 0xFF, 0x52);
+ dsi_dcs_write_seq(dsi, 0xFF, 0x01);
+ dsi_dcs_write_seq(dsi, 0xE3, 0x00);
+ dsi_dcs_write_seq(dsi, 0x03, 0x40);
+ dsi_dcs_write_seq(dsi, 0x04, 0x00);
+ dsi_dcs_write_seq(dsi, 0x05, 0x03);
+ dsi_dcs_write_seq(dsi, 0x24, 0x12);
+ dsi_dcs_write_seq(dsi, 0x25, 0x1E);
+ dsi_dcs_write_seq(dsi, 0x26, 0x28);
+ dsi_dcs_write_seq(dsi, 0x27, 0x52);
+ dsi_dcs_write_seq(dsi, 0x28, 0x57);
+ dsi_dcs_write_seq(dsi, 0x29, 0x01);
+ dsi_dcs_write_seq(dsi, 0x2A, 0xDF);
+ dsi_dcs_write_seq(dsi, 0x38, 0x9C);
+ dsi_dcs_write_seq(dsi, 0x39, 0xA7);
+ dsi_dcs_write_seq(dsi, 0x3A, 0x53);
+ dsi_dcs_write_seq(dsi, 0x44, 0x00);
+ dsi_dcs_write_seq(dsi, 0x49, 0x3C);
+ dsi_dcs_write_seq(dsi, 0x59, 0xFE);
+ dsi_dcs_write_seq(dsi, 0x5C, 0x00);
+ dsi_dcs_write_seq(dsi, 0x91, 0x77);
+ dsi_dcs_write_seq(dsi, 0x92, 0x77);
+ dsi_dcs_write_seq(dsi, 0xA0, 0x55);
+ dsi_dcs_write_seq(dsi, 0xA1, 0x50);
+ dsi_dcs_write_seq(dsi, 0xA4, 0x9C);
+ dsi_dcs_write_seq(dsi, 0xA7, 0x02);
+ dsi_dcs_write_seq(dsi, 0xA
[PATCH 1/2] dt-bindings: display: panel: Add NewVision NV3051D panel bindings
From: Chris Morgan
Add documentation for the NewVision NV3051D panel bindings.
Note that for the two expected consumers of this panel binding
the underlying LCD model is unknown.
Signed-off-by: Chris Morgan
---
.../display/panel/newvision,nv3051d.yaml | 48 +++
1 file changed, 48 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml
diff --git
a/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml
b/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml
new file mode 100644
index ..016168d8d7b2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/newvision,nv3051d.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NewVision NV3051D based DSI panel driver
+
+maintainers:
+ - Chris Morgan
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+enum:
+ - anbernic,rg353p-panel
+ - anbernic,rg353v-panel
+ reg: true
+ backlight: true
+ port: true
+ reset-gpios: true
+ vdd-supply:
+description: regulator that supplies the vdd voltage
+
+required:
+ - compatible
+ - reg
+ - backlight
+ - vdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+dsi {
+#address-cells = <1>;
+#size-cells = <0>;
+panel@0 {
+compatible = "anbernic,rg353p-panel";
+reg = <0>;
+backlight = <&backlight>;
+vdd-supply = <&vcc3v3_lcd>;
+};
+};
+
+...
--
2.25.1
Re: [PATCH v2 0/5] rockchip-dsi for rk3568
On Tue, Sep 06, 2022 at 07:57:28PM +0200, Maya Matuszczyk wrote: > Hello, > What other patches would I need to apply to test this series > on Anbernic RG503? In addition to these patches you'd need the devicetree series: https://lore.kernel.org/linux-rockchip/20220906210324.28986-1-macroalph...@gmail.com/ You'd need the panel driver: https://lore.kernel.org/dri-devel/20220906183642.12505-1-macroalph...@gmail.com/ And you'd need to update the binding for the panel in the devicetree (example here): https://gist.github.com/macromorgan/caff01bfe4df6995d5f74cef701ede6d If you apply these patches and roll back the clock driver changes the panel should start working for you as it does for me. I tested by nuking my build-tree and starting fresh with just these patches. https://cdn.discordapp.com/attachments/973914035890290718/1015350475152949248/IMG_2028.jpg Thank you. > > Best Regards, > Maya Matuszczyk > > > wt., 6 wrz 2022 o 19:52 Chris Morgan napisał(a): > > > > From: Chris Morgan > > > > This series adds support for the dsi and dphy controllers on the > > Rockchip RK3568. I can confirm that for the Rockchip RK3568 this > > current series DOES WORK now, but it requires rolling back clk changes > > made for the HDMI driver. If the clock changes are not rolled back, the > > image on the screen is shifted about 100 pixels to the right. > > > > Clk changes in question: > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/clk/rockchip/clk-rk3568.c?id=ff3187eabb5ce478d15b6ed62eb286756adefac3 > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/clk/rockchip/clk-rk3568.c?id=6e69052f01d9131388cfcfaee929120118a267f4 > > > > Tested on an Anbernic RG503 and RG353P with clock changes rolled back, > > the hardware works correctly on both devices. > > > > Changes since RFCv1: > > - Identified cause of image shift (clock changes). > > - Noted that driver works now. > > - Added devicetree nodes for rk356x.dtsi. > > > > Chris Morgan (5): > > dt-bindings: display: rockchip-dsi: add rk3568 compatible > > dt-bindings: phy-rockchip-inno-dsidphy: add compatible for rk3568 > > drm/rockchip: dsi: add rk3568 support > > phy/rockchip: inno-dsidphy: Add support for rk3568 > > arm64: dts: rockchip: Add DSI and DSI-DPHY nodes to rk356x > > > > .../display/rockchip/dw_mipi_dsi_rockchip.txt | 1 + > > .../bindings/phy/rockchip,px30-dsi-dphy.yaml | 1 + > > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 72 +++ > > .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 51 - > > .../phy/rockchip/phy-rockchip-inno-dsidphy.c | 204 ++ > > 5 files changed, 281 insertions(+), 48 deletions(-) > > > > -- > > 2.25.1 > > > > > > ___ > > Linux-rockchip mailing list > > linux-rockc...@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-rockchip
Re: [PATCH V2 1/2] dt-bindings: Add byteswap order to chrontel ch7033
On Mon, Sep 05, 2022 at 05:20:57PM +0200, Robert Foss wrote: > Thanks Laurent, > > On Sat, 3 Sept 2022 at 02:17, Laurent Pinchart > wrote: > > > > Hi Chris, > > > > Thank you for the patch. > > > > On Fri, Sep 02, 2022 at 10:39:05AM -0500, Chris Morgan wrote: > > > From: Chris Morgan > > > > > > Update dt-binding documentation to add support for setting byteswap of > > > chrontel ch7033. > > > > > > New property name of chrontel,byteswap added to set the byteswap order. > > > This property is optional. > > > > > > Signed-off-by: Chris Morgan > > > Reviewed-by: Robert Foss > > > --- > > > .../bindings/display/bridge/chrontel,ch7033.yaml| 13 + > > > 1 file changed, 13 insertions(+) > > > > > > diff --git > > > a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml > > > b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml > > > index bb6289c7d375..984b90893583 100644 > > > --- > > > a/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml > > > +++ > > > b/Documentation/devicetree/bindings/display/bridge/chrontel,ch7033.yaml > > > @@ -14,6 +14,19 @@ properties: > > >compatible: > > > const: chrontel,ch7033 > > > > > > + chrontel,byteswap: > > > +$ref: /schemas/types.yaml#/definitions/uint8 > > > +enum: > > > + - 0 # BYTE_SWAP_RGB > > > + - 1 # BYTE_SWAP_RBG > > > + - 2 # BYTE_SWAP_GRB > > > + - 3 # BYTE_SWAP_GBR > > > + - 4 # BYTE_SWAP_BRG > > > + - 5 # BYTE_SWAP_BGR > > > +description: | > > > + Set the byteswap value of the bridge. This is optional and if not > > > + set value of BYTE_SWAP_BGR is used. > > > > I don't think this belongs to the device tree. The source of data > > connected to the CH7033 input could use different formats. This > > shouldn't be hardcoded, but queried at runtime, using the input and > > output media bus formats infrastructure that the DRM bridge framework > > includes. > > Chris, will you have a look at submitting a fix for this during the coming > days? > > If not, we can revert this series and apply a fixed version later. I'm not sure I understand (or know) what needs to be fixed. Presumably using something like EDID we can predict what color format we need to use for the connection between the bridge and the HDMI device, but wouldn't the color format between the SoC and bridge need to be constant? If there's something I'm missing please let me know, I'm relatively unfamiliar with the display subsystems as a whole. I'll be happy to make the change once I'm clear what I need to change. Thank you for your help. > > > > > > + > > >reg: > > > maxItems: 1 > > > description: I2C address of the device > > > > -- > > Regards, > > > > Laurent Pinchart
Re: [PATCH 1/2] dt-bindings: display: panel: Add NewVision NV3051D panel bindings
On Wed, Sep 07, 2022 at 02:53:56PM +0200, Krzysztof Kozlowski wrote: > On 06/09/2022 20:52, Chris Morgan wrote: > > From: Chris Morgan > > > > Add documentation for the NewVision NV3051D panel bindings. > > Note that for the two expected consumers of this panel binding > > the underlying LCD model is unknown. > > > > Signed-off-by: Chris Morgan > > --- > > .../display/panel/newvision,nv3051d.yaml | 48 +++ > > 1 file changed, 48 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > b/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > new file mode 100644 > > index ..016168d8d7b2 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > @@ -0,0 +1,48 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://nam12.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fdisplay%2Fpanel%2Fnewvision%2Cnv3051d.yaml%23&data=05%7C01%7C%7C69d30de15aea41517acb08da90d0079f%7C84df9e7fe9f640afb435%7C1%7C0%7C637981520397977782%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=qfuvbrQYP3rKnp%2ByPmPmn%2BCJJOQkNkTGT49FkJmIics%3D&reserved=0 > > You need to document vendor prefix... but the filename does not match > compatible. Okay, will do that. This is a tricky one because while I know the panel controller IC (a NewVision NV3051D) I don't actually know the LCD panel itself, the vendor is somewhat tight lipped. I do know the product it goes into, so that's why I did what I did with the compatible strings. If that's not correct I guess let me know. I did see for other drivers (such as the NewVision NV3052C) the driver was written for the IC and the panel name was listed differently, hence what I was going for here. > > > +$schema: > > https://nam12.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=05%7C01%7C%7C69d30de15aea41517acb08da90d0079f%7C84df9e7fe9f640afb435%7C1%7C0%7C637981520397977782%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=AYwypW%2BA9xWCN6YYwC7oI5UDW6QmiP7%2FmAoKlm7x3jM%3D&reserved=0 > > + > > +title: NewVision NV3051D based DSI panel driver > > This is confusing - compatibles say something else. > Right. Driver IC is the NV3051D, LCD panel itself is... well... not sure... > > + > > +maintainers: > > + - Chris Morgan > > + > > +allOf: > > + - $ref: panel-common.yaml# > > + > > +properties: > > + compatible: > > +enum: > > + - anbernic,rg353p-panel > > + - anbernic,rg353v-panel > > Missing space, missing documentation for vendor prefix. > > Strip "panel" suffix unless device is multifunctional. > The device name itself is Anbernic RG353P (and RG353V). The driver is not multifunctional but again I don't really know what the LCD itself is called so I'm trying to name it after the device. I only know the driver IC. > > + reg: true > > + backlight: true > > > Best regards, > Krzysztof Thank you once again for all your help, sorry to be such a bother in this. I'm honestly not sure the best way to name and document a panel when I only know one of the part numbers (the IC).
Re: [PATCH 1/2] dt-bindings: display: panel: Add Samsung AMS495QA01 panel bindings
On Tue, Sep 06, 2022 at 04:41:00PM -0500, Rob Herring wrote: > On Tue, 06 Sep 2022 13:36:41 -0500, Chris Morgan wrote: > > From: Chris Morgan > > > > Add documentation for the Samsung AMS495QA01 panel. > > > > Signed-off-by: Chris Morgan > > --- > > .../display/panel/samsung,ams495qa01.yaml | 49 +++ > > 1 file changed, 49 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.example.dtb: > panel@0: 'backlight' does not match any of the regexes: 'pinctrl-[0-9]+' > From schema: > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml > > doc reference errors (make refcheckdocs): > > See https://patchwork.ozlabs.org/patch/ > > This check can fail if there are any dependencies. The base for a patch > series is generally the most recent rc1. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit. > A dumb mistake on my part that I will fix for v2. OLED panels don't have backlights and I forgot to remove this from the example I copied. Thank you.
[PATCH] drm/rockchip: vop2: Fix Null Pointer Dereference on Multiple VPs
From: Chris Morgan
If I use more than one VP to output on an RK3566 based device I
receive the following error (and then everything freezes):
[0.838375] Unable to handle kernel NULL pointer dereference at virtual
address 0250
[0.839191] Mem abort info:
[0.839442] ESR = 0x9605
[0.839785] EC = 0x25: DABT (current EL), IL = 32 bits
[0.840256] SET = 0, FnV = 0
[0.840530] EA = 0, S1PTW = 0
[0.840821] FSC = 0x05: level 1 translation fault
[0.841254] Data abort info:
[0.841512] ISV = 0, ISS = 0x0005
[0.841864] CM = 0, WnR = 0
[0.842130] [0250] user address but active_mm is swapper
[0.842704] Internal error: Oops: 9605 [#1] SMP
[0.843139] Modules linked in:
[0.843420] CPU: 0 PID: 37 Comm: kworker/u8:1 Not tainted 6.0.0-rc5+ #40
[0.844013] Hardware name: RG503 (DT)
[0.844343] Workqueue: events_unbound deferred_probe_work_func
[0.844871] pstate: 8009 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[0.845487] pc : __drm_crtc_init_with_planes+0x48/0x2e4
[0.845956] lr : drm_crtc_init_with_planes+0x68/0x94
[0.846399] sp : ffc00a7a3710
[0.846695] x29: ffc00a7a3710 x28: ff8000fb4080 x27: ffc00a7a37a0
[0.847332] x26: ffc0097d01c7 x25: ff8000fb44d8 x24: ffc0097d01c7
[0.847967] x23: ffc009311870 x22: x21: 0008
[0.848603] x20: ff80010d0800 x19: ff8000fb44e8 x18:
[0.849237] x17: 08d1 x16: 0891 x15: 08c1
[0.849874] x14: x13: 3432564e3631564e x12: 3231564e36314742
[0.850509] x11: 3631475234324742 x10: 002d x9 : ffc008682004
[0.851144] x8 : 006f7475 x7 : fff0 x6 : ffc00a7a37a0
[0.851778] x5 : ffc0097d01c7 x4 : ffc009311870 x3 :
[0.852412] x2 : 0008 x1 : ff8000fb44e8 x0 : ff80010d0800
[0.853048] Call trace:
[0.853270] __drm_crtc_init_with_planes+0x48/0x2e4
[0.853706] drm_crtc_init_with_planes+0x68/0x94
[0.854118] vop2_bind+0x89c/0x920
[0.854429] component_bind_all+0x18c/0x290
[0.854805] rockchip_drm_bind+0xe4/0x1f0
[0.855166] try_to_bring_up_aggregate_device+0x9c/0x290
[0.855639] __component_add+0x110/0x168
[0.855991] component_add+0x1c/0x28
[0.856312] dw_mipi_dsi_rockchip_host_attach+0x98/0x10c
[0.856785] dw_mipi_dsi_host_attach+0xbc/0xd0
[0.857184] mipi_dsi_attach+0x30/0x44
[0.857521] devm_mipi_dsi_attach+0x2c/0x70
[0.857896] ams495qa01_probe+0x2d4/0x33c
[0.858257] spi_probe+0x8c/0xb8
[0.858550] really_probe+0x1e0/0x3b8
[0.858881] __driver_probe_device+0x16c/0x184
[0.859278] driver_probe_device+0x4c/0xfc
[0.859646] __device_attach_driver+0xf0/0x170
[0.860043] bus_for_each_drv+0xa4/0xcc
[0.860389] __device_attach+0xfc/0x1a8
[0.860733] device_initial_probe+0x1c/0x28
[0.861108] bus_probe_device+0x38/0x9c
[0.861452] deferred_probe_work_func+0xdc/0xf0
[0.861855] process_one_work+0x1b0/0x260
[0.862217] process_scheduled_works+0x4c/0x50
[0.862614] worker_thread+0x1f0/0x26c
[0.862949] kthread+0xc4/0xd4
[0.863227] ret_from_fork+0x10/0x20
[0.863553] Code: aa0503fa f9002bfb aa0603fb b4a2 (b9424840)
[0.864095] ---[ end trace ]---
A cursory reading of the datasheet suggests it's possible to have
simultaneous output to 2 distinct outputs. On page 13 it states:
Support two simultaneous displays(same source) in the following interfaces:
- MIPI_DSI_TX
- LVDS
- HDMI
- eDP
In order to achieve this though, I need to output to VP0 and VP1 (or
any 2 distinct VPs really). This is so I can have the ref clock set
to 24MHz for the HDMI and the pixel clock of the DSI panel (for the
example above it's 33.5MHz). Currently, only by removing this code
block is such a thing possible, though I'm not sure if long-term
there should only be 1 CRTC for the rk3566 (and 2 CRTCs for 3568)
along with a max of 2 encoders for rk3566 (and 3 encoders for 3568).
Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver")
Signed-off-by: Chris Morgan
---
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 14 --
1 file changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
index e4631f515ba4..f18d7f6f9f86 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
@@ -2289,20 +2289,6 @@ static int vop2_create_crtc(struct vop2 *vop2)
struct vop2_win *win = &vop2->win[i];
u32 possible_crtcs;
- if (vop2->data->soc_id == 3566) {
- /*
-* On RK3566 these windows don't have an independent
-* framebuf
Re: [PATCH v1 0/2] Revert chrontel-ch7033 byteswap order series
On Mon, Sep 12, 2022 at 01:38:54PM +0200, Robert Foss wrote: > After applying the "chrontel-ch7033: Add byteswap order option" series, > Laurent reported an issues with the approach. Since no fix has been submitted > for the issues outlined in time for the next kernel release, I'd like to > revert this series for now. > > Just to be clear I would very much like to see a v3 of this[1] series, where > the > issues outlined have been fixed. I will work on a v3 soon, I just have to finish a few other things first. That said, I'm not very familiar with what we're trying to do in an automated fashion. In my use case I have DPI output (from an Allwinner R8 to this bridge) which then connects via HDMI. I'm aware that we should be able to get the color space information from the HDMI connector, correct? Is it that information I would then need to use to set the bridge colorspace, or is it the color info from the DPI connector I'm using? I'm still pretty new to DRM drivers so this is mostly new to me. Thank you. > > [1] https://lore.kernel.org/all/20220902153906.31000-1-macroalph...@gmail.com/ > > Robert Foss (2): > Revert "dt-bindings: Add byteswap order to chrontel ch7033" > Revert "drm/bridge: ti-sn65dsi86: Implement bridge connector > operations for DP" > > .../display/bridge/chrontel,ch7033.yaml | 13 - > drivers/gpu/drm/bridge/ti-sn65dsi86.c | 28 --- > 2 files changed, 41 deletions(-) > > -- > 2.34.1 >
Re: [PATCH 1/2] dt-bindings: display: panel: Add NewVision NV3051D panel bindings
On Thu, Sep 08, 2022 at 08:42:35PM -0500, Rob Herring wrote: > On Wed, Sep 07, 2022 at 08:35:13AM -0500, Chris Morgan wrote: > > On Wed, Sep 07, 2022 at 02:53:56PM +0200, Krzysztof Kozlowski wrote: > > > On 06/09/2022 20:52, Chris Morgan wrote: > > > > From: Chris Morgan > > > > > > > > Add documentation for the NewVision NV3051D panel bindings. > > > > Note that for the two expected consumers of this panel binding > > > > the underlying LCD model is unknown. > > > > > > > > Signed-off-by: Chris Morgan > > > > --- > > > > .../display/panel/newvision,nv3051d.yaml | 48 +++ > > > > 1 file changed, 48 insertions(+) > > > > create mode 100644 > > > > Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > > > > > > > diff --git > > > > a/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > > > > > > > b/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > > > new file mode 100644 > > > > index ..016168d8d7b2 > > > > --- /dev/null > > > > +++ > > > > b/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > > > @@ -0,0 +1,48 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > +%YAML 1.2 > > > > +--- > > > > +$id: > > > > https://nam12.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fdisplay%2Fpanel%2Fnewvision%2Cnv3051d.yaml%23&data=05%7C01%7C%7Cab7f68ce677846b1638508da920493a4%7C84df9e7fe9f640afb435%7C1%7C0%7C637982845610791935%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=6XxrzD1zkl8SYQqV9nkH1WzKfdcy6doNfzan8r228W0%3D&reserved=0 > > > > > > You need to document vendor prefix... but the filename does not match > > > compatible. > > > > Okay, will do that. This is a tricky one because while I know the panel > > controller IC (a NewVision NV3051D) I don't actually know the LCD panel > > itself, the vendor is somewhat tight lipped. I do know the product it > > goes into, so that's why I did what I did with the compatible strings. > > If that's not correct I guess let me know. I did see for other drivers > > (such as the NewVision NV3052C) the driver was written for the IC > > and the panel name was listed differently, hence what I was going for > > here. > > I think most cases like this targeting a specific LCD driver IC, there's > a driver IC compatible as a fallback. > > (TBC, 'driver' here is not Linux driver, but the h/w chip.) > > Rob So in this case would my compatible string in the devicetree need to be something like "anbernic,rg353-panel", "newvision,nv3051d" then? And the module itself have the compatible string of "newvision,nv3051d"? My fear is that I write this as a newvision,nv3051d kernel module and then later on there comes a new panel using the nv3051d that wants to use this too. Again keeping things confusing I have no LCD panel part number from the manufacturer for this, and I cannot see anything on the panel itself denoting what LCD it is. Thank you for your help. Just wrapping up getting some of my favorite devices supported in mainline. :-)
Re: [PATCH] drm/rockchip: vop2: Fix Null Pointer Dereference on Multiple VPs
On Tue, Sep 13, 2022 at 11:10:16AM +0200, Piotr Oniszczuk wrote: > > > > Wiadomość napisana przez Michael Riesch w > > dniu 13.09.2022, o godz. 08:55: > > > > Hi, > > > > On 9/12/22 20:02, Chris Morgan wrote: > >> From: Chris Morgan > > > > Cc: Sascha -> any thoughts on this one? > > > > Best regards, > > Michael > > > >> If I use more than one VP to output on an RK3566 based device I > >> receive the following error (and then everything freezes): > >> > >> [0.838375] Unable to handle kernel NULL pointer dereference at virtual > >> address 0250 > >> [0.839191] Mem abort info: > >> [0.839442] ESR = 0x9605 > >> [0.839785] EC = 0x25: DABT (current EL), IL = 32 bits > >> [0.840256] SET = 0, FnV = 0 > >> [0.840530] EA = 0, S1PTW = 0 > >> [0.840821] FSC = 0x05: level 1 translation fault > >> [0.841254] Data abort info: > >> [0.841512] ISV = 0, ISS = 0x0005 > >> [0.841864] CM = 0, WnR = 0 > >> [0.842130] [0250] user address but active_mm is swapper > >> [0.842704] Internal error: Oops: 9605 [#1] SMP > >> [0.843139] Modules linked in: > >> [0.843420] CPU: 0 PID: 37 Comm: kworker/u8:1 Not tainted 6.0.0-rc5+ #40 > >> [0.844013] Hardware name: RG503 (DT) > >> [0.844343] Workqueue: events_unbound deferred_probe_work_func > >> [0.844871] pstate: 8009 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS > >> BTYPE=--) > >> [0.845487] pc : __drm_crtc_init_with_planes+0x48/0x2e4 > >> [0.845956] lr : drm_crtc_init_with_planes+0x68/0x94 > >> [0.846399] sp : ffc00a7a3710 > >> [0.846695] x29: ffc00a7a3710 x28: ff8000fb4080 x27: > >> ffc00a7a37a0 > >> [0.847332] x26: ffc0097d01c7 x25: ff8000fb44d8 x24: > >> ffc0097d01c7 > >> [0.847967] x23: ffc009311870 x22: x21: > >> 0008 > >> [0.848603] x20: ff80010d0800 x19: ff8000fb44e8 x18: > >> > >> [0.849237] x17: 08d1 x16: 0891 x15: > >> 08c1 > >> [0.849874] x14: x13: 3432564e3631564e x12: > >> 3231564e36314742 > >> [0.850509] x11: 3631475234324742 x10: 002d x9 : > >> ffc008682004 > >> [0.851144] x8 : 006f7475 x7 : fff0 x6 : > >> ffc00a7a37a0 > >> [0.851778] x5 : ffc0097d01c7 x4 : ffc009311870 x3 : > >> > >> [0.852412] x2 : 0008 x1 : ff8000fb44e8 x0 : > >> ff80010d0800 > >> [0.853048] Call trace: > >> [0.853270] __drm_crtc_init_with_planes+0x48/0x2e4 > >> [0.853706] drm_crtc_init_with_planes+0x68/0x94 > >> [0.854118] vop2_bind+0x89c/0x920 > >> [0.854429] component_bind_all+0x18c/0x290 > >> [0.854805] rockchip_drm_bind+0xe4/0x1f0 > >> [0.855166] try_to_bring_up_aggregate_device+0x9c/0x290 > >> [0.855639] __component_add+0x110/0x168 > >> [0.855991] component_add+0x1c/0x28 > >> [0.856312] dw_mipi_dsi_rockchip_host_attach+0x98/0x10c > >> [0.856785] dw_mipi_dsi_host_attach+0xbc/0xd0 > >> [0.857184] mipi_dsi_attach+0x30/0x44 > >> [0.857521] devm_mipi_dsi_attach+0x2c/0x70 > >> [0.857896] ams495qa01_probe+0x2d4/0x33c > >> [0.858257] spi_probe+0x8c/0xb8 > >> [0.858550] really_probe+0x1e0/0x3b8 > >> [0.858881] __driver_probe_device+0x16c/0x184 > >> [0.859278] driver_probe_device+0x4c/0xfc > >> [0.859646] __device_attach_driver+0xf0/0x170 > >> [0.860043] bus_for_each_drv+0xa4/0xcc > >> [0.860389] __device_attach+0xfc/0x1a8 > >> [0.860733] device_initial_probe+0x1c/0x28 > >> [0.861108] bus_probe_device+0x38/0x9c > >> [0.861452] deferred_probe_work_func+0xdc/0xf0 > >> [0.861855] process_one_work+0x1b0/0x260 > >> [0.862217] process_scheduled_works+0x4c/0x50 > >> [0.862614] worker_thread+0x1f0/0x26c > >> [0.862949] kthread+0xc4/0xd4 > >> [0.863227] ret_from_fork+0x10/0x20 > >> [0.863553] Code: aa0503fa f9002bfb aa0603fb b4a2 (b9424840) > >> [0.864095] ---[ end trace ]--- > >> > >> A cursory reading of the datasheet suggests it's possibl
Re: [PATCH] drm/rockchip: vop2: Fix Null Pointer Dereference on Multiple VPs
On Wed, Sep 14, 2022 at 08:49:27AM +0200, Sascha Hauer wrote: > On Tue, Sep 13, 2022 at 08:55:22AM +0200, Michael Riesch wrote: > > Hi, > > > > On 9/12/22 20:02, Chris Morgan wrote: > > > From: Chris Morgan > > > > Cc: Sascha -> any thoughts on this one? > > > > Best regards, > > Michael > > > > > If I use more than one VP to output on an RK3566 based device I > > > receive the following error (and then everything freezes): > > > > > > [0.838375] Unable to handle kernel NULL pointer dereference at > > > virtual address 0250 > > > [0.839191] Mem abort info: > > > [0.839442] ESR = 0x9605 > > > [0.839785] EC = 0x25: DABT (current EL), IL = 32 bits > > > [0.840256] SET = 0, FnV = 0 > > > [0.840530] EA = 0, S1PTW = 0 > > > [0.840821] FSC = 0x05: level 1 translation fault > > > [0.841254] Data abort info: > > > [0.841512] ISV = 0, ISS = 0x0005 > > > [0.841864] CM = 0, WnR = 0 > > > [0.842130] [0250] user address but active_mm is swapper > > > [0.842704] Internal error: Oops: 9605 [#1] SMP > > > [0.843139] Modules linked in: > > > [0.843420] CPU: 0 PID: 37 Comm: kworker/u8:1 Not tainted 6.0.0-rc5+ > > > #40 > > > [0.844013] Hardware name: RG503 (DT) > > > [0.844343] Workqueue: events_unbound deferred_probe_work_func > > > [0.844871] pstate: 8009 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS > > > BTYPE=--) > > > [0.845487] pc : __drm_crtc_init_with_planes+0x48/0x2e4 > > > [0.845956] lr : drm_crtc_init_with_planes+0x68/0x94 > > > [0.846399] sp : ffc00a7a3710 > > > [0.846695] x29: ffc00a7a3710 x28: ff8000fb4080 x27: > > > ffc00a7a37a0 > > > [0.847332] x26: ffc0097d01c7 x25: ff8000fb44d8 x24: > > > ffc0097d01c7 > > > [0.847967] x23: ffc009311870 x22: x21: > > > 0008 > > > [0.848603] x20: ff80010d0800 x19: ff8000fb44e8 x18: > > > > > > [0.849237] x17: 08d1 x16: 0891 x15: > > > 08c1 > > > [0.849874] x14: x13: 3432564e3631564e x12: > > > 3231564e36314742 > > > [0.850509] x11: 3631475234324742 x10: 002d x9 : > > > ffc008682004 > > > [0.851144] x8 : 006f7475 x7 : fff0 x6 : > > > ffc00a7a37a0 > > > [0.851778] x5 : ffc0097d01c7 x4 : ffc009311870 x3 : > > > > > > [0.852412] x2 : 0008 x1 : ff8000fb44e8 x0 : > > > ff80010d0800 > > > [0.853048] Call trace: > > > [0.853270] __drm_crtc_init_with_planes+0x48/0x2e4 > > > [0.853706] drm_crtc_init_with_planes+0x68/0x94 > > > [0.854118] vop2_bind+0x89c/0x920 > > > [0.854429] component_bind_all+0x18c/0x290 > > > [0.854805] rockchip_drm_bind+0xe4/0x1f0 > > > [0.855166] try_to_bring_up_aggregate_device+0x9c/0x290 > > > [0.855639] __component_add+0x110/0x168 > > > [0.855991] component_add+0x1c/0x28 > > > [0.856312] dw_mipi_dsi_rockchip_host_attach+0x98/0x10c > > > [0.856785] dw_mipi_dsi_host_attach+0xbc/0xd0 > > > [0.857184] mipi_dsi_attach+0x30/0x44 > > > [0.857521] devm_mipi_dsi_attach+0x2c/0x70 > > > [0.857896] ams495qa01_probe+0x2d4/0x33c > > > [0.858257] spi_probe+0x8c/0xb8 > > > [0.858550] really_probe+0x1e0/0x3b8 > > > [0.858881] __driver_probe_device+0x16c/0x184 > > > [0.859278] driver_probe_device+0x4c/0xfc > > > [0.859646] __device_attach_driver+0xf0/0x170 > > > [0.860043] bus_for_each_drv+0xa4/0xcc > > > [0.860389] __device_attach+0xfc/0x1a8 > > > [0.860733] device_initial_probe+0x1c/0x28 > > > [0.861108] bus_probe_device+0x38/0x9c > > > [0.861452] deferred_probe_work_func+0xdc/0xf0 > > > [0.861855] process_one_work+0x1b0/0x260 > > > [0.862217] process_scheduled_works+0x4c/0x50 > > > [0.862614] worker_thread+0x1f0/0x26c > > > [0.862949] kthread+0xc4/0xd4 > > > [0.863227] ret_from_fork+0x10/0x20 > > > [0.863553] Code: aa0503fa f9002bfb aa0603fb b4a2 (b9424840) > > > [0.864095] ---[ end trace ]--- > > > > > > A cursory reading of the
Re: [PATCH] drm/rockchip: vop2: Fix Null Pointer Dereference on Multiple VPs
On Wed, Sep 14, 2022 at 03:35:30PM +0200, Sascha Hauer wrote: > On Wed, Sep 14, 2022 at 08:04:18AM -0500, Chris Morgan wrote: > > On Wed, Sep 14, 2022 at 08:49:27AM +0200, Sascha Hauer wrote: > > > On Tue, Sep 13, 2022 at 08:55:22AM +0200, Michael Riesch wrote: > > > > Hi, > > > > > > > > On 9/12/22 20:02, Chris Morgan wrote: > > > > > From: Chris Morgan > > > > > > > > Cc: Sascha -> any thoughts on this one? > > > > > > > > Best regards, > > > > Michael > > > > > > > > > If I use more than one VP to output on an RK3566 based device I > > > > > receive the following error (and then everything freezes): > > > > > > > > > > [0.838375] Unable to handle kernel NULL pointer dereference at > > > > > virtual address 0250 > > > > > [0.839191] Mem abort info: > > > > > [0.839442] ESR = 0x9605 > > > > > [0.839785] EC = 0x25: DABT (current EL), IL = 32 bits > > > > > [0.840256] SET = 0, FnV = 0 > > > > > [0.840530] EA = 0, S1PTW = 0 > > > > > [0.840821] FSC = 0x05: level 1 translation fault > > > > > [0.841254] Data abort info: > > > > > [0.841512] ISV = 0, ISS = 0x0005 > > > > > [0.841864] CM = 0, WnR = 0 > > > > > [0.842130] [0250] user address but active_mm is > > > > > swapper > > > > > [0.842704] Internal error: Oops: 9605 [#1] SMP > > > > > [0.843139] Modules linked in: > > > > > [0.843420] CPU: 0 PID: 37 Comm: kworker/u8:1 Not tainted > > > > > 6.0.0-rc5+ #40 > > > > > [0.844013] Hardware name: RG503 (DT) > > > > > [0.844343] Workqueue: events_unbound deferred_probe_work_func > > > > > [0.844871] pstate: 8009 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS > > > > > BTYPE=--) > > > > > [0.845487] pc : __drm_crtc_init_with_planes+0x48/0x2e4 > > > > > [0.845956] lr : drm_crtc_init_with_planes+0x68/0x94 > > > > > [0.846399] sp : ffc00a7a3710 > > > > > [0.846695] x29: ffc00a7a3710 x28: ff8000fb4080 x27: > > > > > ffc00a7a37a0 > > > > > [0.847332] x26: ffc0097d01c7 x25: ff8000fb44d8 x24: > > > > > ffc0097d01c7 > > > > > [0.847967] x23: ffc009311870 x22: x21: > > > > > 0008 > > > > > [0.848603] x20: ff80010d0800 x19: ff8000fb44e8 x18: > > > > > > > > > > [0.849237] x17: 08d1 x16: 0891 x15: > > > > > 08c1 > > > > > [0.849874] x14: x13: 3432564e3631564e x12: > > > > > 3231564e36314742 > > > > > [0.850509] x11: 3631475234324742 x10: 002d x9 : > > > > > ffc008682004 > > > > > [0.851144] x8 : 006f7475 x7 : fff0 x6 : > > > > > ffc00a7a37a0 > > > > > [0.851778] x5 : ffc0097d01c7 x4 : ffc009311870 x3 : > > > > > > > > > > [0.852412] x2 : 0008 x1 : ff8000fb44e8 x0 : > > > > > ff80010d0800 > > > > > [0.853048] Call trace: > > > > > [0.853270] __drm_crtc_init_with_planes+0x48/0x2e4 > > > > > [0.853706] drm_crtc_init_with_planes+0x68/0x94 > > > > > [0.854118] vop2_bind+0x89c/0x920 > > > > > [0.854429] component_bind_all+0x18c/0x290 > > > > > [0.854805] rockchip_drm_bind+0xe4/0x1f0 > > > > > [0.855166] try_to_bring_up_aggregate_device+0x9c/0x290 > > > > > [0.855639] __component_add+0x110/0x168 > > > > > [0.855991] component_add+0x1c/0x28 > > > > > [0.856312] dw_mipi_dsi_rockchip_host_attach+0x98/0x10c > > > > > [0.856785] dw_mipi_dsi_host_attach+0xbc/0xd0 > > > > > [0.857184] mipi_dsi_attach+0x30/0x44 > > > > > [0.857521] devm_mipi_dsi_attach+0x2c/0x70 > > > > > [0.857896] ams495qa01_probe+0x2d4/0x33c > > > > > [0.858257] spi_probe+0x8c/0xb8 > > > > > [0.858550] really_probe+0x1e0/0x3b8 > > > > > [0.858881] __driver_probe_device+0x16c/0x184
[PATCH V2 0/3] drm/panel: Add NewVision NV3051D Panels
From: Chris Morgan Add the NewVision NV3051D panel as found on the Anbernic RG353P and RG353V. The underlying LCD panel itself is unknown (the NV3051D is the controller), so the device name is used for the panel with a fallback to the driver IC. Changes from V1: - Changed compatible string to the driver IC. - Updated documentation to use new compatible string with board name. - Refactored somewhat to make it easier to support other LCD panels with this kernel module. - Added support for 60hz mode. Adjusted pixel clock to ensure proper 60hz and 120hz (previously was running at 124hz). - Added vendor prefix for NewVision. Anbernic vendor prefix added in https://lore.kernel.org/linux-devicetree/20220906210324.28986-2-macroalph...@gmail.com Chris Morgan (3): dt-bindings: vendor-prefixes: add NewVision vendor prefix dt-bindings: display: panel: Add NewVision NV3051D bindings drm/panel: Add NewVision NV3051D MIPI-DSI LCD panel .../display/panel/newvision,nv3051d.yaml | 55 ++ .../devicetree/bindings/vendor-prefixes.yaml | 2 + drivers/gpu/drm/panel/Kconfig | 9 + drivers/gpu/drm/panel/Makefile| 1 + .../gpu/drm/panel/panel-newvision-nv3051d.c | 513 ++ 5 files changed, 580 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml create mode 100644 drivers/gpu/drm/panel/panel-newvision-nv3051d.c -- 2.25.1
[PATCH V2 2/3] dt-bindings: display: panel: Add NewVision NV3051D bindings
From: Chris Morgan
Add documentation for the NewVision NV3051D panel bindings.
Note that for the two expected consumers of this panel binding
the underlying LCD model is unknown. Name "anbernic,rg353p-panel"
is used because the hardware itself is known as "anbernic,rg353p".
Signed-off-by: Chris Morgan
---
.../display/panel/newvision,nv3051d.yaml | 55 +++
1 file changed, 55 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml
diff --git
a/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml
b/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml
new file mode 100644
index ..d90bca4171c2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/newvision,nv3051d.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NewVision NV3051D based LCD panel
+
+description: |
+ The NewVision NV3051D is a driver chip used to drive DSI panels. For now,
+ this driver only supports the 640x480 panels found in the Anbernic RG353
+ based devices.
+
+maintainers:
+ - Chris Morgan
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+items:
+ - enum:
+ - anbernic,rg353p-panel
+ - anbernic,rg353v-panel
+ - const: newvision,nv3051d
+ reg: true
+ backlight: true
+ port: true
+ reset-gpios: true
+ vdd-supply:
+description: regulator that supplies the vdd voltage
+
+required:
+ - compatible
+ - reg
+ - backlight
+ - vdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+dsi {
+#address-cells = <1>;
+#size-cells = <0>;
+panel@0 {
+compatible = "anbernic,rg353p-panel";
+reg = <0>;
+backlight = <&backlight>;
+vdd-supply = <&vcc3v3_lcd>;
+};
+};
+
+...
--
2.25.1
[PATCH V2 3/3] drm/panel: Add NewVision NV3051D MIPI-DSI LCD panel
From: Chris Morgan
Add NewVision NV3051D MIPI-DSI LCD panel
Support NewVision NV3051D panels as found on the Anbernic RG353P and
RG353V. The underlying LCD part number for the RG353x devices is
unknown, so the device name and a fallback for the driver IC is
used instead.
Signed-off-by: Chris Morgan
---
drivers/gpu/drm/panel/Kconfig | 9 +
drivers/gpu/drm/panel/Makefile| 1 +
.../gpu/drm/panel/panel-newvision-nv3051d.c | 513 ++
3 files changed, 523 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-newvision-nv3051d.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index a9043eacce97..7258d28dda2f 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -296,6 +296,15 @@ config DRM_PANEL_NEC_NL8048HL11
panel (found on the Zoom2/3/3630 SDP boards). To compile this driver
as a module, choose M here.
+config DRM_PANEL_NEWVISION_NV3051D
+ tristate "NewVision NV3051D DSI panel"
+ depends on OF
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ help
+ This driver supports the NV3051D based panel found on the Anbernic
+ RG353P and RG353V.
+
config DRM_PANEL_NEWVISION_NV3052C
tristate "NewVision NV3052C RGB/SPI panel"
depends on OF && SPI
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 34e717382dbb..cb03b3a82738 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829) +=
panel-leadtek-ltk500hd1829.o
obj-$(CONFIG_DRM_PANEL_LG_LB035Q02) += panel-lg-lb035q02.o
obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
obj-$(CONFIG_DRM_PANEL_NEC_NL8048HL11) += panel-nec-nl8048hl11.o
+obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3051D) += panel-newvision-nv3051d.o
obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3052C) += panel-newvision-nv3052c.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35510) += panel-novatek-nt35510.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35560) += panel-novatek-nt35560.o
diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3051d.c
b/drivers/gpu/drm/panel/panel-newvision-nv3051d.c
new file mode 100644
index ..be57b3579bd5
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-newvision-nv3051d.c
@@ -0,0 +1,513 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * NV3051D MIPI-DSI panel driver for Anbernic RG353x
+ * Copyright (C) 2022 Chris Morgan
+ *
+ * based on
+ *
+ * Elida kd35t133 3.5" MIPI-DSI panel driver
+ * Copyright (C) Theobroma Systems 2020
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+
+struct nv3051d_panel_info {
+ const struct drm_display_mode *display_modes;
+ unsigned int num_modes;
+ u16 width_mm, height_mm;
+ u32 bus_flags;
+};
+
+struct panel_nv3051d {
+ struct device *dev;
+ struct drm_panel panel;
+ struct gpio_desc *reset_gpio;
+ const struct nv3051d_panel_info *panel_info;
+ struct regulator *vdd;
+ bool prepared;
+};
+
+static inline struct panel_nv3051d *panel_to_panelnv3051d(struct drm_panel
*panel)
+{
+ return container_of(panel, struct panel_nv3051d, panel);
+}
+
+#define dsi_dcs_write_seq(dsi, cmd, seq...) do { \
+ static const u8 b[] = { cmd, seq }; \
+ int ret;\
+ ret = mipi_dsi_dcs_write_buffer(dsi, b, ARRAY_SIZE(b)); \
+ if (ret < 0)\
+ return ret; \
+ } while (0)
+
+static int panel_nv3051d_init_sequence(struct panel_nv3051d *ctx)
+{
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+
+ /*
+* Init sequence was supplied by device vendor with no
+* documentation.
+*/
+
+ dsi_dcs_write_seq(dsi, 0xFF, 0x30);
+ dsi_dcs_write_seq(dsi, 0xFF, 0x52);
+ dsi_dcs_write_seq(dsi, 0xFF, 0x01);
+ dsi_dcs_write_seq(dsi, 0xE3, 0x00);
+ dsi_dcs_write_seq(dsi, 0x03, 0x40);
+ dsi_dcs_write_seq(dsi, 0x04, 0x00);
+ dsi_dcs_write_seq(dsi, 0x05, 0x03);
+ dsi_dcs_write_seq(dsi, 0x24, 0x12);
+ dsi_dcs_write_seq(dsi, 0x25, 0x1E);
+ dsi_dcs_write_seq(dsi, 0x26, 0x28);
+ dsi_dcs_write_seq(dsi, 0x27, 0x52);
+ dsi_dcs_write_seq(dsi, 0x28, 0x57);
+ dsi_dcs_write_seq(dsi, 0x29, 0x01);
+ dsi_dcs_write_seq(dsi, 0x2A, 0xDF);
+ dsi_dcs_write_seq(dsi, 0x38, 0x9C);
+ dsi_dcs_write_seq(dsi, 0x39, 0xA7);
+ dsi_dcs_write_seq(dsi, 0x3A, 0x53);
+ dsi_dcs_write_seq(dsi, 0x44, 0x00);
+ dsi_dcs_write_seq(dsi, 0x49, 0x3C);
+ dsi_dcs_write_seq(dsi, 0x59, 0xFE);
+ dsi_dcs_write_seq(dsi, 0x5C, 0x0
[PATCH V2 1/3] dt-bindings: vendor-prefixes: add NewVision vendor prefix
From: Chris Morgan NewVision (also sometimes written as New Vision) is a company based in Shenzen that manufactures ICs for controlling LCD panels. https://www.newvisiondisplay.com/ Signed-off-by: Chris Morgan --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 2f0151e9f6be..d9c38e214863 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -873,6 +873,8 @@ patternProperties: description: Shenzhen Netxeon Technology CO., LTD "^neweast,.*": description: Guangdong Neweast Optoelectronics CO., LTD + "^newvision,.*": +description: New Vision Display (Shenzhen) Co., Ltd. "^nexbox,.*": description: Nexbox "^nextthing,.*": -- 2.25.1
[PATCH V2 0/2] drm/panel: Add Samsung AMS495QA01 Panel
From: Chris Morgan Add the Samsung AMS495QA01 panel as found on the Anbernic RG503. This panel uses DSI to receive video signals, but 3-wire SPI to receive command signals. Changes since V1: - Removed errant reference to backlight in documentation. This is an OLED panel. - Made elvss regulator optional. In my case its hard wired and not controllable. - Added "prepared" enum to track panel status to prevent unbalanced regulator enable/disable. Chris Morgan (2): dt-bindings: display: panel: Add Samsung AMS495QA01 bindings drm/panel: Add Samsung AMS495QA01 MIPI-DSI LCD panel .../display/panel/samsung,ams495qa01.yaml | 46 ++ drivers/gpu/drm/panel/Kconfig | 10 + drivers/gpu/drm/panel/Makefile| 1 + .../gpu/drm/panel/panel-samsung-ams495qa01.c | 505 ++ 4 files changed, 562 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml create mode 100644 drivers/gpu/drm/panel/panel-samsung-ams495qa01.c -- 2.25.1
[PATCH V2 2/2] drm/panel: Add Samsung AMS495QA01 MIPI-DSI LCD panel
From: Chris Morgan
Support Samsung AMS495QA01 panel as found on the Anbernic RG503. Note
This panel receives video signals via DSI, however it receives
commands via 3-wire SPI.
Signed-off-by: Chris Morgan
---
drivers/gpu/drm/panel/Kconfig | 10 +
drivers/gpu/drm/panel/Makefile| 1 +
.../gpu/drm/panel/panel-samsung-ams495qa01.c | 505 ++
3 files changed, 516 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-samsung-ams495qa01.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index a9043eacce97..954b66a2adee 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -444,6 +444,16 @@ config DRM_PANEL_RONBO_RB070D30
Say Y here if you want to enable support for Ronbo Electronics
RB070D30 1024x600 DSI panel.
+config DRM_PANEL_SAMSUNG_AMS495QA01
+ tristate "Samsung AMS495QA01 DSI panel"
+ depends on OF && SPI
+ depends on DRM_MIPI_DSI
+ select DRM_MIPI_DBI
+ help
+ DRM panel driver for the Samsung AMS495QA01 panel. This panel
+ receives video data via DSI but commands via 3-Wire 9-bit
+ SPI.
+
config DRM_PANEL_SAMSUNG_ATNA33XC20
tristate "Samsung ATNA33XC20 eDP panel"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 34e717382dbb..de0b57baf851 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN) +=
panel-raspberrypi-touchscreen
obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM67191) += panel-raydium-rm67191.o
obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM68200) += panel-raydium-rm68200.o
obj-$(CONFIG_DRM_PANEL_RONBO_RB070D30) += panel-ronbo-rb070d30.o
+obj-$(CONFIG_DRM_PANEL_SAMSUNG_AMS495QA01) += panel-samsung-ams495qa01.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20) += panel-samsung-atna33xc20.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_DB7430) += panel-samsung-db7430.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o
diff --git a/drivers/gpu/drm/panel/panel-samsung-ams495qa01.c
b/drivers/gpu/drm/panel/panel-samsung-ams495qa01.c
new file mode 100644
index ..d693ba5f20c9
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-samsung-ams495qa01.c
@@ -0,0 +1,505 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung ams495qa01 MIPI-DSI panel driver
+ * Copyright (C) 2022 Chris Morgan
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+struct ams495qa01 {
+ /** @dev: the container device */
+ struct device *dev;
+ /** @dbi: the DBI bus abstraction handle */
+ struct mipi_dbi dbi;
+ /** @panel: the DRM panel instance for this device */
+ struct drm_panel panel;
+ /** @reset: reset GPIO line */
+ struct gpio_desc *reset;
+ /** @enable: enable GPIO line */
+ struct gpio_desc *enable;
+ /** @reg_vdd: VDD supply regulator for panel logic */
+ struct regulator *reg_vdd;
+ /** @reg_elvdd: ELVDD supply regulator for panel display */
+ struct regulator *reg_elvdd;
+ /** @dsi_dev: DSI child device (panel) */
+ struct mipi_dsi_device *dsi_dev;
+ /** @bl_dev: pseudo-backlight device for oled panel */
+ struct backlight_device *bl_dev;
+ /** @prepared: value tracking panel prepare status */
+ bool prepared;
+};
+
+static const struct drm_display_mode ams495qa01_mode = {
+ .clock = 33500,
+ .hdisplay = 960,
+ .hsync_start = 960 + 10,
+ .hsync_end = 960 + 10 + 2,
+ .htotal = 960 + 10 + 2 + 10,
+ .vdisplay = 544,
+ .vsync_start = 544 + 10,
+ .vsync_end = 544 + 10 + 2,
+ .vtotal = 544 + 10 + 2 + 10,
+ .width_mm = 117,
+ .height_mm = 74,
+ .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+};
+
+#define NUM_GAMMA_LEVELS 16
+#define GAMMA_TABLE_COUNT 23
+#define MAX_BRIGHTNESS (NUM_GAMMA_LEVELS - 1)
+
+/* Table of gamma values provided in datasheet */
+static u8 ams495qa01_gamma[NUM_GAMMA_LEVELS][GAMMA_TABLE_COUNT] = {
+ {0x01, 0x79, 0x78, 0x8d, 0xd9, 0xdf, 0xd5, 0xcb, 0xcf, 0xc5,
+0xe5, 0xe0, 0xe4, 0xdc, 0xb8, 0xd4, 0xfa, 0xed, 0xe6, 0x2f,
+0x00, 0x2f},
+ {0x01, 0x7d, 0x7c, 0x92, 0xd7, 0xdd, 0xd2, 0xcb, 0xd0, 0xc6,
+0xe5, 0xe1, 0xe3, 0xda, 0xbd, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+0x00, 0x2f},
+ {0x01, 0x7f, 0x7e, 0x95, 0xd7, 0xde, 0xd2, 0xcb, 0xcf, 0xc5,
+0xe5, 0xe3, 0xe3, 0xda, 0xbf, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+0x00, 0x2f},
+ {0x01, 0x82, 0x81, 0x99, 0xd6, 0xdd, 0xd1, 0xca, 0xcf, 0xc3,
+0xe4, 0xe3, 0xe3, 0xda, 0xc2, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+0x00, 0x2f},
+ {0x01, 0x84, 0x83, 0x9b, 0xd7, 0xde, 0xd2, 0xc8, 0xce, 0xc2,
+
[PATCH V2 1/2] dt-bindings: display: panel: Add Samsung AMS495QA01 bindings
From: Chris Morgan
Add documentation for the Samsung AMS495QA01 panel.
Signed-off-by: Chris Morgan
---
.../display/panel/samsung,ams495qa01.yaml | 46 +++
1 file changed, 46 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
diff --git
a/Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
b/Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
new file mode 100644
index ..08358cdad19c
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/samsung,ams495qa01.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung AMS495QA01 4.95in 960x544 DSI/SPI panel
+
+maintainers:
+ - Chris Morgan
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+const: samsung,ams495qa01
+ reg: true
+ reset-gpios: true
+ elvdd-supply:
+description: regulator that supplies voltage to the panel display
+ enable-gpios: true
+ port: true
+ vdd-supply:
+description: regulator that supplies voltage to panel logic
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+spi {
+#address-cells = <1>;
+#size-cells = <0>;
+panel@0 {
+compatible = "samsung,ams495qa01";
+reg = <0>;
+vdd-supply = <&vcc3v3_lcd0_n>;
+};
+};
+
+...
--
2.25.1
Re: [PATCH V2 2/2] drm/panel: Add Samsung AMS495QA01 MIPI-DSI LCD panel
On Tue, Sep 20, 2022 at 07:33:00PM +0200, Maya Matuszczyk wrote:
> Hi Chris,
> Thanks for this patch,
>
> wt., 20 wrz 2022 o 19:10 Chris Morgan napisał(a):
> >
> > From: Chris Morgan
> >
> > Support Samsung AMS495QA01 panel as found on the Anbernic RG503. Note
> > This panel receives video signals via DSI, however it receives
> > commands via 3-wire SPI.
> >
> > Signed-off-by: Chris Morgan
> > ---
> > drivers/gpu/drm/panel/Kconfig | 10 +
> > drivers/gpu/drm/panel/Makefile| 1 +
> > .../gpu/drm/panel/panel-samsung-ams495qa01.c | 505 ++
> > 3 files changed, 516 insertions(+)
> > create mode 100644 drivers/gpu/drm/panel/panel-samsung-ams495qa01.c
> >
> > diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
> > index a9043eacce97..954b66a2adee 100644
> > --- a/drivers/gpu/drm/panel/Kconfig
> > +++ b/drivers/gpu/drm/panel/Kconfig
> > @@ -444,6 +444,16 @@ config DRM_PANEL_RONBO_RB070D30
> > Say Y here if you want to enable support for Ronbo Electronics
> > RB070D30 1024x600 DSI panel.
> >
> > +config DRM_PANEL_SAMSUNG_AMS495QA01
> > + tristate "Samsung AMS495QA01 DSI panel"
> > + depends on OF && SPI
> > + depends on DRM_MIPI_DSI
> > + select DRM_MIPI_DBI
> > + help
> > + DRM panel driver for the Samsung AMS495QA01 panel. This panel
> > + receives video data via DSI but commands via 3-Wire 9-bit
> > + SPI.
> > +
> > config DRM_PANEL_SAMSUNG_ATNA33XC20
> > tristate "Samsung ATNA33XC20 eDP panel"
> > depends on OF
> > diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
> > index 34e717382dbb..de0b57baf851 100644
> > --- a/drivers/gpu/drm/panel/Makefile
> > +++ b/drivers/gpu/drm/panel/Makefile
> > @@ -42,6 +42,7 @@ obj-$(CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN) +=
> > panel-raspberrypi-touchscreen
> > obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM67191) += panel-raydium-rm67191.o
> > obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM68200) += panel-raydium-rm68200.o
> > obj-$(CONFIG_DRM_PANEL_RONBO_RB070D30) += panel-ronbo-rb070d30.o
> > +obj-$(CONFIG_DRM_PANEL_SAMSUNG_AMS495QA01) += panel-samsung-ams495qa01.o
> > obj-$(CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20) += panel-samsung-atna33xc20.o
> > obj-$(CONFIG_DRM_PANEL_SAMSUNG_DB7430) += panel-samsung-db7430.o
> > obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o
> > diff --git a/drivers/gpu/drm/panel/panel-samsung-ams495qa01.c
> > b/drivers/gpu/drm/panel/panel-samsung-ams495qa01.c
> > new file mode 100644
> > index ..d693ba5f20c9
> > --- /dev/null
> > +++ b/drivers/gpu/drm/panel/panel-samsung-ams495qa01.c
> > @@ -0,0 +1,505 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Samsung ams495qa01 MIPI-DSI panel driver
> > + * Copyright (C) 2022 Chris Morgan
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#include
> > +
> > +struct ams495qa01 {
> > + /** @dev: the container device */
> > + struct device *dev;
> > + /** @dbi: the DBI bus abstraction handle */
> > + struct mipi_dbi dbi;
> > + /** @panel: the DRM panel instance for this device */
> > + struct drm_panel panel;
> > + /** @reset: reset GPIO line */
> > + struct gpio_desc *reset;
> > + /** @enable: enable GPIO line */
> > + struct gpio_desc *enable;
> > + /** @reg_vdd: VDD supply regulator for panel logic */
> > + struct regulator *reg_vdd;
> > + /** @reg_elvdd: ELVDD supply regulator for panel display */
> > + struct regulator *reg_elvdd;
> > + /** @dsi_dev: DSI child device (panel) */
> > + struct mipi_dsi_device *dsi_dev;
> > + /** @bl_dev: pseudo-backlight device for oled panel */
> > + struct backlight_device *bl_dev;
> > + /** @prepared: value tracking panel prepare status */
> > + bool prepared;
> > +};
> > +
> > +static const struct drm_display_mode ams495qa01_mode = {
> > + .clock = 33500,
> > + .hdisplay = 960,
> > + .hsync_start = 960 + 10,
> > + .hsync_end = 960 +
Re: [PATCH V2 2/3] dt-bindings: display: panel: Add NewVision NV3051D bindings
On Wed, Sep 21, 2022 at 08:51:34AM +0200, Krzysztof Kozlowski wrote: > On 20/09/2022 16:59, Chris Morgan wrote: > > From: Chris Morgan > > > > Add documentation for the NewVision NV3051D panel bindings. > > Note that for the two expected consumers of this panel binding > > the underlying LCD model is unknown. Name "anbernic,rg353p-panel" > > is used because the hardware itself is known as "anbernic,rg353p". > > > > Signed-off-by: Chris Morgan > > --- > > .../display/panel/newvision,nv3051d.yaml | 55 +++ > > 1 file changed, 55 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > b/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > new file mode 100644 > > index ..d90bca4171c2 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > @@ -0,0 +1,55 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://nam12.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fdisplay%2Fpanel%2Fnewvision%2Cnv3051d.yaml%23&data=05%7C01%7C%7C844872fdf91b413aa65a08da9b9db9e7%7C84df9e7fe9f640afb435%7C1%7C0%7C637993398994635658%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=eTM2IFjR0TKPlQNYfoq3Poao8QYLSHRVaqiXtufJ7VA%3D&reserved=0 > > +$schema: > > https://nam12.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=05%7C01%7C%7C844872fdf91b413aa65a08da9b9db9e7%7C84df9e7fe9f640afb435%7C1%7C0%7C637993398994635658%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=sjb7x2Z2wKu1C8mMBW1epwuXipe8V26zxpHcCAuKLZY%3D&reserved=0 > > + > > +title: NewVision NV3051D based LCD panel > > + > > +description: | > > + The NewVision NV3051D is a driver chip used to drive DSI panels. For now, > > + this driver only supports the 640x480 panels found in the Anbernic RG353 > > + based devices. > > + > > +maintainers: > > + - Chris Morgan > > + > > +allOf: > > + - $ref: panel-common.yaml# > > + > > +properties: > > + compatible: > > +items: > > + - enum: > > + - anbernic,rg353p-panel > > Are these vendor prefixs documented? Yes, they are in another patch series referenced in the cover letter. They were added for the Anbernic devicetrees and should (I believe) land in 6.1. > > > + - anbernic,rg353v-panel > > + - const: newvision,nv3051d > > Blank line. > Ack. > > + reg: true > > + backlight: true > > + port: true > > + reset-gpios: true > > + vdd-supply: > > +description: regulator that supplies the vdd voltage > > Skip description and make it just "true". It's kind of obvious. > Ack. > > + > > +required: > > + - compatible > > + - reg > > + - backlight > > + - vdd-supply > > Best regards, > Krzysztof
Re: [PATCH V2 2/3] dt-bindings: display: panel: Add NewVision NV3051D bindings
On Wed, Sep 21, 2022 at 05:21:19PM +0200, Krzysztof Kozlowski wrote: > On 21/09/2022 16:38, Chris Morgan wrote: > >>> + compatible: > >>> +items: > >>> + - enum: > >>> + - anbernic,rg353p-panel > >> > >> Are these vendor prefixs documented? > > > > Yes, they are in another patch series referenced in the cover letter. > > They were added for the Anbernic devicetrees and should (I believe) > > land in 6.1. > > OK... you still need to test your bindings. Your patch was clearly not > tested before sending. :( I did: yamllint, make dt_binding_check (with DT_SCHEMA_FILES specified), and make dtbs_check (with DT_SCHEMA_FILES specified again). That's the proper testing flow correct? In this case it's the pre-requisite that's causing the issue as I see on a pristine master tree I'm warned about the missing vendor prefix for anbernic. Should I wait for that to go upstream before I submit this again? I'll make the other change about the space and the description of the vdd-supply when I resubmit. Are we good with the panel compatibles? I'm still not entirely sure the best thing to name them as I have no part number whatsoever except the driver IC. Thank you. > > Best regards, > Krzysztof >
Re: [PATCH V2 2/3] dt-bindings: display: panel: Add NewVision NV3051D bindings
On Wed, Sep 21, 2022 at 05:57:55PM +0200, Krzysztof Kozlowski wrote: > On 21/09/2022 17:50, Chris Morgan wrote: > > On Wed, Sep 21, 2022 at 05:21:19PM +0200, Krzysztof Kozlowski wrote: > >> On 21/09/2022 16:38, Chris Morgan wrote: > >>>>> + compatible: > >>>>> +items: > >>>>> + - enum: > >>>>> + - anbernic,rg353p-panel > >>>> > >>>> Are these vendor prefixs documented? > >>> > >>> Yes, they are in another patch series referenced in the cover letter. > >>> They were added for the Anbernic devicetrees and should (I believe) > >>> land in 6.1. > >> > >> OK... you still need to test your bindings. Your patch was clearly not > >> tested before sending. :( > > > > I did: yamllint, make dt_binding_check (with DT_SCHEMA_FILES specified), and > > make dtbs_check (with DT_SCHEMA_FILES specified again). > > I have doubts. So if you say you did it, then you probably did not look > at the results... or whatever other reason the test was not effective, > because your binding cannot pass the dt_binding_check. > > > That's the proper > > testing flow correct? In this case it's the pre-requisite that's causing > > the issue as I see on a pristine master tree I'm warned about the missing > > vendor prefix for anbernic. Should I wait for that to go upstream before > > I submit this again? > > Not really. The testing fails on wrong compatible in example. My mistake, I see what I did wrong and apologize for the trouble. I misinterpreted the error I did get (I expected an issue with a missing vendor string, but as you correctly point out the received error is not for that). I'll correct and resend. Would you be so kind as to confirm if you're okay with the "anbernic,rg353-panel", "newvision,nv3051d" strings? Thank you once again and I apologize for my mistake. > > Best regards, > Krzysztof >
Re: [PATCH V2 2/3] dt-bindings: display: panel: Add NewVision NV3051D bindings
On Sat, Sep 24, 2022 at 12:07:44PM -0500, Rob Herring wrote: > On Tue, Sep 20, 2022 at 09:59:04AM -0500, Chris Morgan wrote: > > From: Chris Morgan > > > > Add documentation for the NewVision NV3051D panel bindings. > > Note that for the two expected consumers of this panel binding > > the underlying LCD model is unknown. Name "anbernic,rg353p-panel" > > is used because the hardware itself is known as "anbernic,rg353p". > > > > Signed-off-by: Chris Morgan > > --- > > .../display/panel/newvision,nv3051d.yaml | 55 +++ > > 1 file changed, 55 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > b/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > new file mode 100644 > > index ..d90bca4171c2 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml > > @@ -0,0 +1,55 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://nam12.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fdisplay%2Fpanel%2Fnewvision%2Cnv3051d.yaml%23&data=05%7C01%7C%7C4f204345128d4cb827ca08da9e4f4d06%7C84df9e7fe9f640afb435%7C1%7C0%7C637996360672620588%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=9%2B66S0t1p9EqWBdmaLBj8pKte2fjzsmL%2FSbmmD8eNi0%3D&reserved=0 > > +$schema: > > https://nam12.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=05%7C01%7C%7C4f204345128d4cb827ca08da9e4f4d06%7C84df9e7fe9f640afb435%7C1%7C0%7C637996360672620588%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=r%2BzTHlte226t9fXktNC9k4NO%2FE2RomRIxuWBuRshIw0%3D&reserved=0 > > + > > +title: NewVision NV3051D based LCD panel > > + > > +description: | > > + The NewVision NV3051D is a driver chip used to drive DSI panels. For now, > > + this driver only supports the 640x480 panels found in the Anbernic RG353 > > + based devices. > > + > > +maintainers: > > + - Chris Morgan > > + > > +allOf: > > + - $ref: panel-common.yaml# > > + > > +properties: > > + compatible: > > +items: > > + - enum: > > + - anbernic,rg353p-panel > > + - anbernic,rg353v-panel > > Is 'panel' redundant? IOW, could 'rg353v' identify something else other > than the panel? It is not redundant, the device itself is identified as "anbernic,rg353v". I don't have a part number for the LCD panel itself, only the controller IC. Thank you. > > Rob
Re: [PATCH] drm/rockchip: vop2: Register Esmart0-win0 as primary plane
On Mon, Sep 26, 2022 at 10:16:43AM +0200, Sascha Hauer wrote:
> Esmart0-win0 could serve as primary plane, so mark it as such. On
> RK3568 this window will never be used as primary plane, because the
> three windows at the beginning of the rk3568_vop_win_data[] array
> will be used. On RK3566 however, two of the windows at the beginning
> of the rk3568_vop_win_data[] array cannot not be used due to hardware
> limitations, so without this patch we end up with CRTCs without primary
> planes when multiple VPs are active.
>
> Signed-off-by: Sascha Hauer
I have been testing this for a few days and it works well for me on 2
distinct rk3566 based devices (Anbernic RG353P and Anbernic RG503).
Tested-by: Chris Morgan
> ---
> drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
> b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
> index 9bf0637bf8e26..9d30aa73b5422 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
> @@ -188,7 +188,7 @@ static const struct vop2_win_data rk3568_vop_win_data[] =
> {
> .base = 0x1800,
> .layer_sel_id = 2,
> .supported_rotations = DRM_MODE_REFLECT_Y,
> - .type = DRM_PLANE_TYPE_OVERLAY,
> + .type = DRM_PLANE_TYPE_PRIMARY,
> .max_upscale_factor = 8,
> .max_downscale_factor = 8,
> .dly = { 20, 47, 41 },
> --
> 2.30.2
>
Re: [PATCH] drm/rockchip: vop2: Fix Null Pointer Dereference on Multiple VPs
On Mon, Sep 26, 2022 at 10:17:40AM +0200, Sascha Hauer wrote: > On Thu, Sep 15, 2022 at 10:13:44AM -0500, Chris Morgan wrote: > > On Wed, Sep 14, 2022 at 03:35:30PM +0200, Sascha Hauer wrote: > > > On Wed, Sep 14, 2022 at 08:04:18AM -0500, Chris Morgan wrote: > > > > On Wed, Sep 14, 2022 at 08:49:27AM +0200, Sascha Hauer wrote: > > > > > On Tue, Sep 13, 2022 at 08:55:22AM +0200, Michael Riesch wrote: > > > > > > Hi, > > > > > > > > > > > > On 9/12/22 20:02, Chris Morgan wrote: > > > > > > > From: Chris Morgan > > > > > > > > > > > > Cc: Sascha -> any thoughts on this one? > > > > > > > > > > > > Best regards, > > > > > > Michael > > > > > > > > > > > > > If I use more than one VP to output on an RK3566 based device I > > > > > > > receive the following error (and then everything freezes): > > > > > > > > > > > > > > [0.838375] Unable to handle kernel NULL pointer dereference > > > > > > > at virtual address 0250 > > > > > > > [0.839191] Mem abort info: > > > > > > > [0.839442] ESR = 0x9605 > > > > > > > [0.839785] EC = 0x25: DABT (current EL), IL = 32 bits > > > > > > > [0.840256] SET = 0, FnV = 0 > > > > > > > [0.840530] EA = 0, S1PTW = 0 > > > > > > > [0.840821] FSC = 0x05: level 1 translation fault > > > > > > > [0.841254] Data abort info: > > > > > > > [0.841512] ISV = 0, ISS = 0x0005 > > > > > > > [0.841864] CM = 0, WnR = 0 > > > > > > > [0.842130] [0250] user address but active_mm is > > > > > > > swapper > > > > > > > [0.842704] Internal error: Oops: 9605 [#1] SMP > > > > > > > [0.843139] Modules linked in: > > > > > > > [0.843420] CPU: 0 PID: 37 Comm: kworker/u8:1 Not tainted > > > > > > > 6.0.0-rc5+ #40 > > > > > > > [0.844013] Hardware name: RG503 (DT) > > > > > > > [0.844343] Workqueue: events_unbound deferred_probe_work_func > > > > > > > [0.844871] pstate: 8009 (Nzcv daif -PAN -UAO -TCO -DIT > > > > > > > -SSBS BTYPE=--) > > > > > > > [0.845487] pc : __drm_crtc_init_with_planes+0x48/0x2e4 > > > > > > > [0.845956] lr : drm_crtc_init_with_planes+0x68/0x94 > > > > > > > [0.846399] sp : ffc00a7a3710 > > > > > > > [0.846695] x29: ffc00a7a3710 x28: ff8000fb4080 x27: > > > > > > > ffc00a7a37a0 > > > > > > > [0.847332] x26: ffc0097d01c7 x25: ff8000fb44d8 x24: > > > > > > > ffc0097d01c7 > > > > > > > [0.847967] x23: ffc009311870 x22: x21: > > > > > > > 0008 > > > > > > > [0.848603] x20: ff80010d0800 x19: ff8000fb44e8 x18: > > > > > > > > > > > > > > [0.849237] x17: 08d1 x16: 0891 x15: > > > > > > > 08c1 > > > > > > > [0.849874] x14: x13: 3432564e3631564e x12: > > > > > > > 3231564e36314742 > > > > > > > [0.850509] x11: 3631475234324742 x10: 002d x9 : > > > > > > > ffc008682004 > > > > > > > [0.851144] x8 : 006f7475 x7 : fff0 x6 : > > > > > > > ffc00a7a37a0 > > > > > > > [0.851778] x5 : ffc0097d01c7 x4 : ffc009311870 x3 : > > > > > > > > > > > > > > [0.852412] x2 : 0008 x1 : ff8000fb44e8 x0 : > > > > > > > ff80010d0800 > > > > > > > [0.853048] Call trace: > > > > > > > [0.853270] __drm_crtc_init_with_planes+0x48/0x2e4 > > > > > > > [0.853706] drm_crtc_init_with_planes+0x68/0x94 > > > > > > > [0.854118] vop2_bind+0x89c/0x920 > > > > > > > [0.854429] component_bind_all+0x18c/0x290 > > > > > > > [0.854805] rockchip_drm_bind+0xe4/0x1f0
[PATCH V3 0/2] drm/panel: Add Samsung AMS495QA01 Panel
From: Chris Morgan Add the Samsung AMS495QA01 panel as found on the Anbernic RG503. This panel uses DSI to receive video signals, but 3-wire SPI to receive command signals. Changes since V2: - Added 50hz mode at request of userspace devs. - Renamed "dupa" to panel name. Good catch Maya. - Added Maya's Signed-off-by. - Removed check for max backlight, since it is already done by backlight_device_set_brightness. - Fixed minor formatting issues on devicetree binding documentation and added port to provided example. Changes since V1: - Removed errant reference to backlight in documentation. This is an OLED panel. - Made elvss regulator optional. In my case its hard wired and not controllable. - Added "prepared" enum to track panel status to prevent unbalanced regulator enable/disable. Chris Morgan (2): dt-bindings: display: panel: Add Samsung AMS495QA01 bindings drm/panel: Add Samsung AMS495QA01 MIPI-DSI LCD panel .../display/panel/samsung,ams495qa01.yaml | 56 ++ drivers/gpu/drm/panel/Kconfig | 10 + drivers/gpu/drm/panel/Makefile| 1 + .../gpu/drm/panel/panel-samsung-ams495qa01.c | 547 ++ 4 files changed, 614 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml create mode 100644 drivers/gpu/drm/panel/panel-samsung-ams495qa01.c -- 2.25.1
[PATCH V3 1/2] dt-bindings: display: panel: Add Samsung AMS495QA01 bindings
From: Chris Morgan
Add documentation for the Samsung AMS495QA01 panel.
Signed-off-by: Chris Morgan
Signed-off-by: Maya Matuszczyk
---
.../display/panel/samsung,ams495qa01.yaml | 56 +++
1 file changed, 56 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
diff --git
a/Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
b/Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
new file mode 100644
index ..d736a536b919
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/samsung,ams495qa01.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung AMS495QA01 4.95in 960x544 DSI/SPI panel
+
+maintainers:
+ - Chris Morgan
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+const: samsung,ams495qa01
+
+ reg: true
+ reset-gpios: true
+ elvdd-supply:
+description: regulator that supplies voltage to the panel display
+ enable-gpios: true
+ port: true
+ vdd-supply:
+description: regulator that supplies voltage to panel logic
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+spi {
+#address-cells = <1>;
+#size-cells = <0>;
+panel@0 {
+compatible = "samsung,ams495qa01";
+reg = <0>;
+enable-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
+vdd-supply = <&vcc3v3_lcd0_n>;
+
+port {
+mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+};
+};
+};
+};
+
+...
--
2.25.1
[PATCH V3 2/2] drm/panel: Add Samsung AMS495QA01 MIPI-DSI LCD panel
From: Chris Morgan
Support Samsung AMS495QA01 panel as found on the Anbernic RG503. Note
This panel receives video signals via DSI, however it receives
commands via 3-wire SPI.
Signed-off-by: Chris Morgan
Signed-off-by: Maya Matuszczyk
---
drivers/gpu/drm/panel/Kconfig | 10 +
drivers/gpu/drm/panel/Makefile| 1 +
.../gpu/drm/panel/panel-samsung-ams495qa01.c | 547 ++
3 files changed, 558 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-samsung-ams495qa01.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index a9043eacce97..954b66a2adee 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -444,6 +444,16 @@ config DRM_PANEL_RONBO_RB070D30
Say Y here if you want to enable support for Ronbo Electronics
RB070D30 1024x600 DSI panel.
+config DRM_PANEL_SAMSUNG_AMS495QA01
+ tristate "Samsung AMS495QA01 DSI panel"
+ depends on OF && SPI
+ depends on DRM_MIPI_DSI
+ select DRM_MIPI_DBI
+ help
+ DRM panel driver for the Samsung AMS495QA01 panel. This panel
+ receives video data via DSI but commands via 3-Wire 9-bit
+ SPI.
+
config DRM_PANEL_SAMSUNG_ATNA33XC20
tristate "Samsung ATNA33XC20 eDP panel"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 34e717382dbb..de0b57baf851 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN) +=
panel-raspberrypi-touchscreen
obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM67191) += panel-raydium-rm67191.o
obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM68200) += panel-raydium-rm68200.o
obj-$(CONFIG_DRM_PANEL_RONBO_RB070D30) += panel-ronbo-rb070d30.o
+obj-$(CONFIG_DRM_PANEL_SAMSUNG_AMS495QA01) += panel-samsung-ams495qa01.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20) += panel-samsung-atna33xc20.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_DB7430) += panel-samsung-db7430.o
obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o
diff --git a/drivers/gpu/drm/panel/panel-samsung-ams495qa01.c
b/drivers/gpu/drm/panel/panel-samsung-ams495qa01.c
new file mode 100644
index ..b59839d026da
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-samsung-ams495qa01.c
@@ -0,0 +1,547 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung ams495qa01 MIPI-DSI panel driver
+ * Copyright (C) 2022 Chris Morgan
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+struct ams495qa01_panel_info {
+ /** @display_modes: the supported display modes */
+ const struct drm_display_mode *display_modes;
+ /** @num_modes: the number of supported display modes */
+ unsigned int num_modes;
+ /** @width_mm: panel width in mm */
+ u16 width_mm;
+ /** @height_mm: panel height in mm */
+ u16 height_mm;
+ /** @bus_flags: drm bus flags for panel */
+ u32 bus_flags;
+};
+
+struct ams495qa01 {
+ /** @dev: the container device */
+ struct device *dev;
+ /** @dbi: the DBI bus abstraction handle */
+ struct mipi_dbi dbi;
+ /** @panel: the DRM panel instance for this device */
+ struct drm_panel panel;
+ /** @reset: reset GPIO line */
+ struct gpio_desc *reset;
+ /** @enable: enable GPIO line */
+ struct gpio_desc *enable;
+ /** @reg_vdd: VDD supply regulator for panel logic */
+ struct regulator *reg_vdd;
+ /** @reg_elvdd: ELVDD supply regulator for panel display */
+ struct regulator *reg_elvdd;
+ /** @dsi_dev: DSI child device (panel) */
+ struct mipi_dsi_device *dsi_dev;
+ /** @bl_dev: pseudo-backlight device for oled panel */
+ struct backlight_device *bl_dev;
+ /** @panel_info: struct containing panel timing and info */
+ const struct ams495qa01_panel_info *panel_info;
+ /** @prepared: value tracking panel prepare status */
+ bool prepared;
+};
+
+#define NUM_GAMMA_LEVELS 16
+#define GAMMA_TABLE_COUNT 23
+#define MAX_BRIGHTNESS (NUM_GAMMA_LEVELS - 1)
+
+/* Table of gamma values provided in datasheet */
+static u8 ams495qa01_gamma[NUM_GAMMA_LEVELS][GAMMA_TABLE_COUNT] = {
+ {0x01, 0x79, 0x78, 0x8d, 0xd9, 0xdf, 0xd5, 0xcb, 0xcf, 0xc5,
+0xe5, 0xe0, 0xe4, 0xdc, 0xb8, 0xd4, 0xfa, 0xed, 0xe6, 0x2f,
+0x00, 0x2f},
+ {0x01, 0x7d, 0x7c, 0x92, 0xd7, 0xdd, 0xd2, 0xcb, 0xd0, 0xc6,
+0xe5, 0xe1, 0xe3, 0xda, 0xbd, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+0x00, 0x2f},
+ {0x01, 0x7f, 0x7e, 0x95, 0xd7, 0xde, 0xd2, 0xcb, 0xcf, 0xc5,
+0xe5, 0xe3, 0xe3, 0xda, 0xbf, 0xd3, 0xfa, 0xed, 0xe6, 0x2f,
+0x00, 0x2f},
+ {0x01, 0x82, 0x81, 0x99, 0xd6, 0xdd, 0xd1, 0xca, 0xcf, 0xc3,
+
[PATCH V3 0/3] drm/panel: Add NewVision NV3051D Panels
From: Chris Morgan Add the NewVision NV3051D panel as found on the Anbernic RG353P and RG353V. The underlying LCD panel itself is unknown (the NV3051D is the controller), so the device name is used for the panel with a fallback to the driver IC. Changes from V2: - Ensured dt_binding_check and dtbs_check successfully passed. - Corrected some minor formatting issues in documentation. - Added another mode per userspace request for 100hz. I was unable to find a supported 50hz mode that would also work, so for now only 60hz, 100hz, and 120hz are supported. Changes from V1: - Changed compatible string to the driver IC. - Updated documentation to use new compatible string with board name. - Refactored somewhat to make it easier to support other LCD panels with this kernel module. - Added support for 60hz mode. Adjusted pixel clock to ensure proper 60hz and 120hz (previously was running at 124hz). - Added vendor prefix for NewVision. Anbernic vendor prefix added in https://lore.kernel.org/linux-devicetree/20220906210324.28986-2-macroalph...@gmail.com Chris Morgan (3): dt-bindings: vendor-prefixes: add NewVision vendor prefix dt-bindings: display: panel: Add NewVision NV3051D bindings drm/panel: Add NewVision NV3051D MIPI-DSI LCD panel .../display/panel/newvision,nv3051d.yaml | 63 +++ .../devicetree/bindings/vendor-prefixes.yaml | 2 + drivers/gpu/drm/panel/Kconfig | 9 + drivers/gpu/drm/panel/Makefile| 1 + .../gpu/drm/panel/panel-newvision-nv3051d.c | 525 ++ 5 files changed, 600 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml create mode 100644 drivers/gpu/drm/panel/panel-newvision-nv3051d.c -- 2.25.1
[PATCH V3 2/3] dt-bindings: display: panel: Add NewVision NV3051D bindings
From: Chris Morgan
Add documentation for the NewVision NV3051D panel bindings.
Note that for the two expected consumers of this panel binding
the underlying LCD model is unknown. Name "anbernic,rg353p-panel"
is used because the hardware itself is known as "anbernic,rg353p".
Signed-off-by: Chris Morgan
---
.../display/panel/newvision,nv3051d.yaml | 63 +++
1 file changed, 63 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml
diff --git
a/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml
b/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml
new file mode 100644
index ..407de7fb5499
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/newvision,nv3051d.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/newvision,nv3051d.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NewVision NV3051D based LCD panel
+
+description: |
+ The NewVision NV3051D is a driver chip used to drive DSI panels. For now,
+ this driver only supports the 640x480 panels found in the Anbernic RG353
+ based devices.
+
+maintainers:
+ - Chris Morgan
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+items:
+ - enum:
+ - anbernic,rg353p-panel
+ - anbernic,rg353v-panel
+ - const: newvision,nv3051d
+
+ reg: true
+ backlight: true
+ port: true
+ reset-gpios: true
+ vdd-supply: true
+
+required:
+ - compatible
+ - reg
+ - backlight
+ - vdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+dsi {
+#address-cells = <1>;
+#size-cells = <0>;
+panel@0 {
+compatible = "anbernic,rg353p-panel", "newvision,nv3051d";
+reg = <0>;
+backlight = <&backlight>;
+reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
+vdd-supply = <&vcc3v3_lcd>;
+
+port {
+mipi_in_panel: endpoint {
+remote-endpoint = <&mipi_out_panel>;
+};
+};
+};
+};
+
+...
--
2.25.1
[PATCH V3 1/3] dt-bindings: vendor-prefixes: add NewVision vendor prefix
From: Chris Morgan NewVision (also sometimes written as New Vision) is a company based in Shenzen that manufactures ICs for controlling LCD panels. https://www.newvisiondisplay.com/ Signed-off-by: Chris Morgan Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 2f0151e9f6be..d9c38e214863 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -873,6 +873,8 @@ patternProperties: description: Shenzhen Netxeon Technology CO., LTD "^neweast,.*": description: Guangdong Neweast Optoelectronics CO., LTD + "^newvision,.*": +description: New Vision Display (Shenzhen) Co., Ltd. "^nexbox,.*": description: Nexbox "^nextthing,.*": -- 2.25.1
[PATCH V3 3/3] drm/panel: Add NewVision NV3051D MIPI-DSI LCD panel
From: Chris Morgan
Support NewVision NV3051D panels as found on the Anbernic RG353P and
RG353V. The underlying LCD part number for the RG353x devices is
unknown, so the device name and a fallback for the driver IC is
used instead.
Signed-off-by: Chris Morgan
---
drivers/gpu/drm/panel/Kconfig | 9 +
drivers/gpu/drm/panel/Makefile| 1 +
.../gpu/drm/panel/panel-newvision-nv3051d.c | 525 ++
3 files changed, 535 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-newvision-nv3051d.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index a9043eacce97..7258d28dda2f 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -296,6 +296,15 @@ config DRM_PANEL_NEC_NL8048HL11
panel (found on the Zoom2/3/3630 SDP boards). To compile this driver
as a module, choose M here.
+config DRM_PANEL_NEWVISION_NV3051D
+ tristate "NewVision NV3051D DSI panel"
+ depends on OF
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ help
+ This driver supports the NV3051D based panel found on the Anbernic
+ RG353P and RG353V.
+
config DRM_PANEL_NEWVISION_NV3052C
tristate "NewVision NV3052C RGB/SPI panel"
depends on OF && SPI
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 34e717382dbb..cb03b3a82738 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829) +=
panel-leadtek-ltk500hd1829.o
obj-$(CONFIG_DRM_PANEL_LG_LB035Q02) += panel-lg-lb035q02.o
obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
obj-$(CONFIG_DRM_PANEL_NEC_NL8048HL11) += panel-nec-nl8048hl11.o
+obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3051D) += panel-newvision-nv3051d.o
obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3052C) += panel-newvision-nv3052c.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35510) += panel-novatek-nt35510.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35560) += panel-novatek-nt35560.o
diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3051d.c
b/drivers/gpu/drm/panel/panel-newvision-nv3051d.c
new file mode 100644
index ..a15b6e4cb668
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-newvision-nv3051d.c
@@ -0,0 +1,525 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * NV3051D MIPI-DSI panel driver for Anbernic RG353x
+ * Copyright (C) 2022 Chris Morgan
+ *
+ * based on
+ *
+ * Elida kd35t133 3.5" MIPI-DSI panel driver
+ * Copyright (C) Theobroma Systems 2020
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+
+struct nv3051d_panel_info {
+ const struct drm_display_mode *display_modes;
+ unsigned int num_modes;
+ u16 width_mm, height_mm;
+ u32 bus_flags;
+};
+
+struct panel_nv3051d {
+ struct device *dev;
+ struct drm_panel panel;
+ struct gpio_desc *reset_gpio;
+ const struct nv3051d_panel_info *panel_info;
+ struct regulator *vdd;
+ bool prepared;
+};
+
+static inline struct panel_nv3051d *panel_to_panelnv3051d(struct drm_panel
*panel)
+{
+ return container_of(panel, struct panel_nv3051d, panel);
+}
+
+#define dsi_dcs_write_seq(dsi, cmd, seq...) do { \
+ static const u8 b[] = { cmd, seq }; \
+ int ret;\
+ ret = mipi_dsi_dcs_write_buffer(dsi, b, ARRAY_SIZE(b)); \
+ if (ret < 0)\
+ return ret; \
+ } while (0)
+
+static int panel_nv3051d_init_sequence(struct panel_nv3051d *ctx)
+{
+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+
+ /*
+* Init sequence was supplied by device vendor with no
+* documentation.
+*/
+
+ dsi_dcs_write_seq(dsi, 0xFF, 0x30);
+ dsi_dcs_write_seq(dsi, 0xFF, 0x52);
+ dsi_dcs_write_seq(dsi, 0xFF, 0x01);
+ dsi_dcs_write_seq(dsi, 0xE3, 0x00);
+ dsi_dcs_write_seq(dsi, 0x03, 0x40);
+ dsi_dcs_write_seq(dsi, 0x04, 0x00);
+ dsi_dcs_write_seq(dsi, 0x05, 0x03);
+ dsi_dcs_write_seq(dsi, 0x24, 0x12);
+ dsi_dcs_write_seq(dsi, 0x25, 0x1E);
+ dsi_dcs_write_seq(dsi, 0x26, 0x28);
+ dsi_dcs_write_seq(dsi, 0x27, 0x52);
+ dsi_dcs_write_seq(dsi, 0x28, 0x57);
+ dsi_dcs_write_seq(dsi, 0x29, 0x01);
+ dsi_dcs_write_seq(dsi, 0x2A, 0xDF);
+ dsi_dcs_write_seq(dsi, 0x38, 0x9C);
+ dsi_dcs_write_seq(dsi, 0x39, 0xA7);
+ dsi_dcs_write_seq(dsi, 0x3A, 0x53);
+ dsi_dcs_write_seq(dsi, 0x44, 0x00);
+ dsi_dcs_write_seq(dsi, 0x49, 0x3C);
+ dsi_dcs_write_seq(dsi, 0x59, 0xFE);
+ dsi_dcs_write_seq(dsi, 0x5C, 0x00);
+ dsi_dcs_write_seq(dsi, 0x91, 0x7
[PATCH v9 0/4] drm/panel: Add Magnachip D53E6EA8966 Panel Controller
From: Chris Morgan Add the Magnachip D53E6EA8966 panel IC controller for display panels such as the Samsung AMS495QA01 panel as found on the Anbernic RG503. This panel uses DSI to receive video signals, but 3-wire SPI to receive command signals using DBI. Changes since V8: - Set "placeholder" drm_of_get_dsi_bus in drm_of.h to static inline to hopefully eliminate the reported errors once and for all. Tested with 4 different kernel configurations provided by Intel's kernel test robot and no new warnings or errors were introduced. Reported-by: kernel test robot Changes since V7: - Removed Linus Walleij review note due to substantial changes. - Corrected documentation of drm_of_get_dsi_bus function. - Updated the drm_of_get_dsi_bus function to return pointer to mipi_dsi_host and use ERR_PTR macros. - Refactored drm_panel_funcs so that the prepare function calls panel specific function for init sequence and uses generic functions otherwise. - Renamed non-panel specific functions. - Changed backlight value to int instead of u32. - Corrected brightness function to use backlight_get_brightness(). - Fix an error reported when CONFIG_OF is selected but CONFIG_DRM_MIPI_DSI is not. Add an if function to drm_of_get_dsi_bus function to return -EINVAL in this instance. Reported-by: kernel test robot Changes since V6: - Fixed a trivial error with definition of drm_of_get_dsi_bus(). Reported-by: kernel test robot Changes since V5: - Reverted dt binding documentation name back to samsung,ams495qa01.yaml. - Removed no longer needed of_graph.h header file. - Added backlight as a dependency. Changes since V4: - Renamed driver from the panel model to the panel IC controller per DRM team. - Added a drm_of helper function of drm_of_get_dsi_bus() to handle finding and populating the DSI node when the DSI node is not the parent of the DSI controlled display. - Converted the documented commands to constants to make it more readable. - Reset GPIO is now required and documented as GPIO_ACTIVE_LOW. - Removed "prepared" logic from panel. Changes since V3: - Updated documentation to add spi-peripheral-props.yaml per updates made for similar devices. Note that I removed a "Reviewed-by" tag from Rob Herring since this change probably needs to be confirmed. - Added binding for RG503, since this device is now accepted with this request: https://lore.kernel.org/linux-rockchip/166274831283.21181.6861718157177507544.b4...@sntech.de/ Changes since V2: - Added 50hz mode at request of userspace devs. - Renamed "dupa" to panel name. Good catch Maya. - Added Maya's Signed-off-by. - Removed check for max backlight, since it is already done by backlight_device_set_brightness. - Fixed minor formatting issues on devicetree binding documentation and added port to provided example. Changes since V1: - Removed errant reference to backlight in documentation. This is an OLED panel. - Made elvss regulator optional. In my case its hard wired and not controllable. - Added "prepared" enum to track panel status to prevent unbalanced regulator enable/disable. Chris Morgan (4): drm: of: Add drm_of_get_dsi_bus helper function dt-bindings: display: panel: Add Samsung AMS495QA01 drm/panel: Add Magnachip D53E6EA8966 Panel Driver arm64: dts: rockchip: add display to RG503 .../display/panel/samsung,ams495qa01.yaml | 57 ++ .../dts/rockchip/rk3566-anbernic-rg503.dts| 55 ++ drivers/gpu/drm/drm_of.c | 70 +++ drivers/gpu/drm/panel/Kconfig | 11 + drivers/gpu/drm/panel/Makefile| 1 + .../drm/panel/panel-magnachip-d53e6ea8966.c | 522 ++ include/drm/drm_of.h | 10 + 7 files changed, 726 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml create mode 100644 drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c -- 2.34.1
[PATCH v9 1/4] drm: of: Add drm_of_get_dsi_bus helper function
From: Chris Morgan
Add helper function to find DSI host for devices where DSI panel is not
a minor of a DSI bus (such as the Samsung AMS495QA01 panel or the
official Raspberry Pi touchscreen display).
Signed-off-by: Chris Morgan
Signed-off-by: Maya Matuszczyk
---
drivers/gpu/drm/drm_of.c | 70
include/drm/drm_of.h | 10 ++
2 files changed, 80 insertions(+)
diff --git a/drivers/gpu/drm/drm_of.c b/drivers/gpu/drm/drm_of.c
index 7bbcb999bb75..4ebb5bc4b595 100644
--- a/drivers/gpu/drm/drm_of.c
+++ b/drivers/gpu/drm/drm_of.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
#include
@@ -493,3 +494,72 @@ int drm_of_get_data_lanes_count_ep(const struct
device_node *port,
return ret;
}
EXPORT_SYMBOL_GPL(drm_of_get_data_lanes_count_ep);
+
+/**
+ * drm_of_get_dsi_bus - find the DSI bus for a given device
+ * @dev: parent device of display (SPI, I2C)
+ * @info: DSI device info to be updated with correct DSI node
+ *
+ * Gets parent DSI bus for a DSI device controlled through a bus other
+ * than MIPI-DCS (SPI, I2C, etc.) using the Device Tree.
+ *
+ * Returns pointer to mipi_dsi_host if successful, -EINVAL if the
+ * request is unsupported, -EPROBE_DEFER if the DSI host is found but
+ * not available, or -ENODEV otherwise.
+ */
+struct mipi_dsi_host *drm_of_get_dsi_bus(struct device *dev,
+struct mipi_dsi_device_info *info)
+{
+ struct mipi_dsi_host *dsi_host;
+ struct device_node *endpoint, *dsi_host_node;
+
+ /*
+* Exit immediately if we attempt to call this function when
+* DRM_MIPI_DSI is not enabled, in the event CONFIG_OF is
+* enabled.
+*/
+ if (!IS_ENABLED(CONFIG_DRM_MIPI_DSI))
+ return ERR_PTR(-EINVAL);
+
+ /*
+* Get first endpoint child from device.
+*/
+ endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
+ if (!endpoint)
+ return ERR_PTR(-ENODEV);
+
+ /*
+* Follow the first endpoint to get the DSI host node.
+*/
+ dsi_host_node = of_graph_get_remote_port_parent(endpoint);
+ if (!dsi_host_node)
+ goto error;
+
+ /*
+* Get the DSI host from the DSI host node. If we get an error
+* or the return is null assume we're not ready to probe just
+* yet. Release the DSI host node since we're done with it.
+*/
+ dsi_host = of_find_mipi_dsi_host_by_node(dsi_host_node);
+ of_node_put(dsi_host_node);
+ if (IS_ERR_OR_NULL(dsi_host)) {
+ of_node_put(endpoint);
+ return ERR_PTR(-EPROBE_DEFER);
+ }
+
+ /*
+* Set the node of the mipi_dsi_device_info to the correct node
+* and then release the endpoint node since we're done with it.
+*/
+ info->node = of_graph_get_remote_port(endpoint);
+ if (IS_ERR_OR_NULL(info->node))
+ goto error;
+
+ of_node_put(endpoint);
+ return dsi_host;
+
+error:
+ of_node_put(endpoint);
+ return ERR_PTR(-ENODEV);
+}
+EXPORT_SYMBOL_GPL(drm_of_get_dsi_bus);
diff --git a/include/drm/drm_of.h b/include/drm/drm_of.h
index 10ab58c40746..705ea2caa494 100644
--- a/include/drm/drm_of.h
+++ b/include/drm/drm_of.h
@@ -15,6 +15,8 @@ struct drm_encoder;
struct drm_panel;
struct drm_bridge;
struct device_node;
+struct mipi_dsi_device_info;
+struct mipi_dsi_host;
/**
* enum drm_lvds_dual_link_pixels - Pixel order of an LVDS dual-link connection
@@ -56,6 +58,8 @@ int drm_of_get_data_lanes_count_ep(const struct device_node
*port,
int port_reg, int reg,
const unsigned int min,
const unsigned int max);
+struct mipi_dsi_host *drm_of_get_dsi_bus(struct device *dev,
+struct mipi_dsi_device_info *info);
#else
static inline uint32_t drm_of_crtc_port_mask(struct drm_device *dev,
struct device_node *port)
@@ -127,6 +131,12 @@ drm_of_get_data_lanes_count_ep(const struct device_node
*port,
{
return -EINVAL;
}
+static inline struct
+mipi_dsi_host *drm_of_get_dsi_bus(struct device *dev,
+struct mipi_dsi_device_info *info)
+{
+ return ERR_PTR(-EINVAL);
+}
#endif
/*
--
2.34.1
[PATCH v9 2/4] dt-bindings: display: panel: Add Samsung AMS495QA01
From: Chris Morgan
Add documentation for Samsung AMS495QA01 panel (with Magnachip
D53E6EA8966 controller IC).
Signed-off-by: Chris Morgan
Signed-off-by: Maya Matuszczyk
Reviewed-by: Rob Herring
---
.../display/panel/samsung,ams495qa01.yaml | 57 +++
1 file changed, 57 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
diff --git
a/Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
b/Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
new file mode 100644
index ..58fa073ce258
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/samsung,ams495qa01.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung AMS495QA01 panel with Magnachip D53E6EA8966 controller
+
+maintainers:
+ - Chris Morgan
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+const: samsung,ams495qa01
+
+ reg: true
+ reset-gpios:
+description: reset gpio, must be GPIO_ACTIVE_LOW
+ elvdd-supply:
+description: regulator that supplies voltage to the panel display
+ enable-gpios: true
+ port: true
+ vdd-supply:
+description: regulator that supplies voltage to panel logic
+
+required:
+ - compatible
+ - reg
+ - reset-gpios
+ - vdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+spi {
+#address-cells = <1>;
+#size-cells = <0>;
+panel@0 {
+compatible = "samsung,ams495qa01";
+reg = <0>;
+reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
+vdd-supply = <&vcc_3v3>;
+
+port {
+mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+};
+};
+};
+};
+
+...
--
2.34.1
[PATCH v9 4/4] arm64: dts: rockchip: add display to RG503
From: Chris Morgan
Add Samsung AMS495QA01 panel to RG503.
Signed-off-by: Chris Morgan
Signed-off-by: Maya Matuszczyk
---
.../dts/rockchip/rk3566-anbernic-rg503.dts| 55 +++
1 file changed, 55 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
index 5dafcc86296b..b4b2df821cba 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
@@ -47,6 +47,21 @@ gpio_spi: spi {
mosi-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
num-chipselects = <0>;
+
+ panel@0 {
+ compatible = "samsung,ams495qa01";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_reset>;
+ reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&vcc_3v3>;
+
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
+ };
};
/* Channels reversed for both headphones and speakers. */
@@ -94,6 +109,32 @@ &cru {
assigned-clock-rates = <12>, <2>, <5>;
};
+&dsi_dphy0 {
+ status = "okay";
+};
+
+&dsi0 {
+ status = "okay";
+
+ ports {
+ dsi0_in: port@0 {
+ reg = <0>;
+
+ dsi0_in_vp1: endpoint {
+ remote-endpoint = <&vp1_out_dsi0>;
+ };
+ };
+
+ dsi0_out: port@1 {
+ reg = <1>;
+
+ mipi_out_panel: endpoint {
+ remote-endpoint = <&mipi_in_panel>;
+ };
+ };
+ };
+};
+
&gpio_keys_control {
button-a {
gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
@@ -146,6 +187,13 @@ spk_amp_enable_h: spk-amp-enable-h {
};
};
+ gpio-lcd {
+ lcd_reset: lcd-reset {
+ rockchip,pins =
+ <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
gpio-spi {
spi_pins: spi-pins {
rockchip,pins =
@@ -164,3 +212,10 @@ rk817_charger: charger {
rockchip,sleep-filter-current-microamp = <10>;
};
};
+
+&vp1 {
+ vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 {
+ reg = ;
+ remote-endpoint = <&dsi0_in_vp1>;
+ };
+};
--
2.34.1
[PATCH v9 3/4] drm/panel: Add Magnachip D53E6EA8966 Panel Driver
From: Chris Morgan
Support Magnachip D53E6EA8966 based panels such as the Samsung
AMS495QA01 panel as found on the Anbernic RG503. Note this driver
supports only the AMS495QA01 today which receives video signals via DSI,
however it receives commands via 3-wire SPI using DBI.
Signed-off-by: Chris Morgan
Signed-off-by: Maya Matuszczyk
---
drivers/gpu/drm/panel/Kconfig | 11 +
drivers/gpu/drm/panel/Makefile| 1 +
.../drm/panel/panel-magnachip-d53e6ea8966.c | 522 ++
3 files changed, 534 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 737edcdf9eef..204b84a83604 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -298,6 +298,17 @@ config DRM_PANEL_LG_LG4573
Say Y here if you want to enable support for LG4573 RGB panel.
To compile this driver as a module, choose M here.
+config DRM_PANEL_MAGNACHIP_D53E6EA8966
+ tristate "Magnachip D53E6EA8966 DSI panel"
+ depends on OF && SPI
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ select DRM_MIPI_DBI
+ help
+ DRM panel driver for the Samsung AMS495QA01 panel controlled
+ with the Magnachip D53E6EA8966 panel IC. This panel receives
+ video data via DSI but commands via 9-bit SPI using DBI.
+
config DRM_PANEL_NEC_NL8048HL11
tristate "NEC NL8048HL11 RGB panel"
depends on GPIOLIB && OF && SPI
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index f8f9d9f6a307..20de312aa5e9 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W) +=
panel-leadtek-ltk050h3146w.o
obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829) += panel-leadtek-ltk500hd1829.o
obj-$(CONFIG_DRM_PANEL_LG_LB035Q02) += panel-lg-lb035q02.o
obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
+obj-$(CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966) += panel-magnachip-d53e6ea8966.o
obj-$(CONFIG_DRM_PANEL_NEC_NL8048HL11) += panel-nec-nl8048hl11.o
obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3051D) += panel-newvision-nv3051d.o
obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3052C) += panel-newvision-nv3052c.o
diff --git a/drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c
b/drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c
new file mode 100644
index ..09ee12f0a147
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c
@@ -0,0 +1,522 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Magnachip d53e6ea8966 MIPI-DSI panel driver
+ * Copyright (C) 2023 Chris Morgan
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+/* Forward declaration for use in backlight function */
+struct d53e6ea8966;
+
+/* Panel info, unique to each panel */
+struct d53e6ea8966_panel_info {
+ /** @display_modes: the supported display modes */
+ const struct drm_display_mode *display_modes;
+ /** @num_modes: the number of supported display modes */
+ unsigned int num_modes;
+ /** @width_mm: panel width in mm */
+ u16 width_mm;
+ /** @height_mm: panel height in mm */
+ u16 height_mm;
+ /** @bus_flags: drm bus flags for panel */
+ u32 bus_flags;
+ /** @panel_init_seq: panel specific init sequence */
+ void (*panel_init_seq)(struct d53e6ea8966 *db);
+ /** @backlight_register: panel backlight registration or NULL */
+ int (*backlight_register)(struct d53e6ea8966 *db);
+};
+
+struct d53e6ea8966 {
+ /** @dev: the container device */
+ struct device *dev;
+ /** @dbi: the DBI bus abstraction handle */
+ struct mipi_dbi dbi;
+ /** @panel: the DRM panel instance for this device */
+ struct drm_panel panel;
+ /** @reset: reset GPIO line */
+ struct gpio_desc *reset;
+ /** @enable: enable GPIO line */
+ struct gpio_desc *enable;
+ /** @reg_vdd: VDD supply regulator for panel logic */
+ struct regulator *reg_vdd;
+ /** @reg_elvdd: ELVDD supply regulator for panel display */
+ struct regulator *reg_elvdd;
+ /** @dsi_dev: DSI child device (panel) */
+ struct mipi_dsi_device *dsi_dev;
+ /** @bl_dev: pseudo-backlight device for oled panel */
+ struct backlight_device *bl_dev;
+ /** @panel_info: struct containing panel timing and info */
+ const struct d53e6ea8966_panel_info *panel_info;
+};
+
+#define NUM_GAMMA_LEVELS 16
+#define GAMMA_TABLE_COUNT 23
+#define MAX_BRIGHTNESS (NUM_GAMMA_LEVELS - 1)
+
+#define MCS_ELVSS_ON 0xb1
+#define MCS_TEMP_SWIRE 0xb2
+#define MCS_PASSWORD_0
Re: [PATCH v9 1/4] drm: of: Add drm_of_get_dsi_bus helper function
On Wed, Jan 11, 2023 at 05:39:26PM +0100, Maxime Ripard wrote:
> Hi,
>
> On Wed, Jan 11, 2023 at 10:30:09AM -0600, Chris Morgan wrote:
> > From: Chris Morgan
> >
> > Add helper function to find DSI host for devices where DSI panel is not
> > a minor of a DSI bus (such as the Samsung AMS495QA01 panel or the
> > official Raspberry Pi touchscreen display).
> >
> > Signed-off-by: Chris Morgan
> > Signed-off-by: Maya Matuszczyk
> > ---
> > drivers/gpu/drm/drm_of.c | 70
> > include/drm/drm_of.h | 10 ++
> > 2 files changed, 80 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_of.c b/drivers/gpu/drm/drm_of.c
> > index 7bbcb999bb75..4ebb5bc4b595 100644
> > --- a/drivers/gpu/drm/drm_of.c
> > +++ b/drivers/gpu/drm/drm_of.c
> > @@ -10,6 +10,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> >
> > @@ -493,3 +494,72 @@ int drm_of_get_data_lanes_count_ep(const struct
> > device_node *port,
> > return ret;
> > }
> > EXPORT_SYMBOL_GPL(drm_of_get_data_lanes_count_ep);
> > +
> > +/**
> > + * drm_of_get_dsi_bus - find the DSI bus for a given device
> > + * @dev: parent device of display (SPI, I2C)
> > + * @info: DSI device info to be updated with correct DSI node
> > + *
> > + * Gets parent DSI bus for a DSI device controlled through a bus other
> > + * than MIPI-DCS (SPI, I2C, etc.) using the Device Tree.
> > + *
> > + * Returns pointer to mipi_dsi_host if successful, -EINVAL if the
> > + * request is unsupported, -EPROBE_DEFER if the DSI host is found but
> > + * not available, or -ENODEV otherwise.
> > + */
> > +struct mipi_dsi_host *drm_of_get_dsi_bus(struct device *dev,
> > +struct mipi_dsi_device_info *info)
> > +{
> > + struct mipi_dsi_host *dsi_host;
> > + struct device_node *endpoint, *dsi_host_node;
> > +
> > + /*
> > +* Exit immediately if we attempt to call this function when
> > +* DRM_MIPI_DSI is not enabled, in the event CONFIG_OF is
> > +* enabled.
> > +*/
> > + if (!IS_ENABLED(CONFIG_DRM_MIPI_DSI))
> > + return ERR_PTR(-EINVAL);
>
> The commit log isn't super clear on why this is needed, but it would be
> more consistent to add an ifdef and only compile the entire function if
> DRM_MIPI_DSI is there, just like you did for OF already.
Thank you. I can do that, I just wasn't sure if "#ifdefs" were frowned
upon or not. That would probably be the easiest way to do this though.
>
> > + /*
> > +* Get first endpoint child from device.
> > +*/
> > + endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
> > + if (!endpoint)
> > + return ERR_PTR(-ENODEV);
> > +
> > + /*
> > +* Follow the first endpoint to get the DSI host node.
> > +*/
> > + dsi_host_node = of_graph_get_remote_port_parent(endpoint);
>
> There's no need to hold the reference to endpoint after that call. call
> of_node_put(endpoint) here, and it will simplify the error path.
>
> > + if (!dsi_host_node)
> > + goto error;
> > +
> > + /*
> > +* Get the DSI host from the DSI host node. If we get an error
> > +* or the return is null assume we're not ready to probe just
> > +* yet. Release the DSI host node since we're done with it.
> > +*/
> > + dsi_host = of_find_mipi_dsi_host_by_node(dsi_host_node);
> > + of_node_put(dsi_host_node);
> > + if (IS_ERR_OR_NULL(dsi_host)) {
> > + of_node_put(endpoint);
> > + return ERR_PTR(-EPROBE_DEFER);
> > + }
> > +
> > + /*
> > +* Set the node of the mipi_dsi_device_info to the correct node
> > +* and then release the endpoint node since we're done with it.
> > +*/
> > + info->node = of_graph_get_remote_port(endpoint);
>
> Ah, you're using it there.
>
> I think I'd rework the function to:
>
> - retrieve the endpoint
> - retrieve the remote port, give up the endpoint
> - retrieve the remote port parent
>
> Also, I'm not entirely sure what you had in mind, but info might not be
> there at all and it would be fine imho.
>
What if I make it optional and if a NULL is passed skip this step, but
otherwise populate the info node?
> Maxime
Thank you for your input. I'll wait for the bots to see if the previous
errors are really finally fixed, then I'll make these changes and
resubmit.
[PATCH V10 0/4] drm/panel: Add Magnachip D53E6EA8966 Panel Controller
From: Chris Morgan Add the Magnachip D53E6EA8966 panel IC controller for display panels such as the Samsung AMS495QA01 panel as found on the Anbernic RG503. This panel uses DSI to receive video signals, but 3-wire SPI to receive command signals using DBI. Changes since V9: - Set an ifdef to not add the drm_of_get_dsi_bus when MIPI_DSI is not part of the current kernel config. - Made "info" optional in the drm_of_get_dsi_bus() function. Changes since V8: - Set "placeholder" drm_of_get_dsi_bus in drm_of.h to static inline to hopefully eliminate the reported errors once and for all. Tested with 4 different kernel configurations provided by Intel's kernel test robot and no new warnings or errors were introduced. Reported-by: kernel test robot Changes since V7: - Removed Linus Walleij review note due to substantial changes. - Corrected documentation of drm_of_get_dsi_bus function. - Updated the drm_of_get_dsi_bus function to return pointer to mipi_dsi_host and use ERR_PTR macros. - Refactored drm_panel_funcs so that the prepare function calls panel specific function for init sequence and uses generic functions otherwise. - Renamed non-panel specific functions. - Changed backlight value to int instead of u32. - Corrected brightness function to use backlight_get_brightness(). - Fix an error reported when CONFIG_OF is selected but CONFIG_DRM_MIPI_DSI is not. Add an if function to drm_of_get_dsi_bus function to return -EINVAL in this instance. Reported-by: kernel test robot Changes since V6: - Fixed a trivial error with definition of drm_of_get_dsi_bus(). Reported-by: kernel test robot Changes since V5: - Reverted dt binding documentation name back to samsung,ams495qa01.yaml. - Removed no longer needed of_graph.h header file. - Added backlight as a dependency. Changes since V4: - Renamed driver from the panel model to the panel IC controller per DRM team. - Added a drm_of helper function of drm_of_get_dsi_bus() to handle finding and populating the DSI node when the DSI node is not the parent of the DSI controlled display. - Converted the documented commands to constants to make it more readable. - Reset GPIO is now required and documented as GPIO_ACTIVE_LOW. - Removed "prepared" logic from panel. Changes since V3: - Updated documentation to add spi-peripheral-props.yaml per updates made for similar devices. Note that I removed a "Reviewed-by" tag from Rob Herring since this change probably needs to be confirmed. - Added binding for RG503, since this device is now accepted with this request: https://lore.kernel.org/linux-rockchip/166274831283.21181.6861718157177507544.b4...@sntech.de/ Changes since V2: - Added 50hz mode at request of userspace devs. - Renamed "dupa" to panel name. Good catch Maya. - Added Maya's Signed-off-by. - Removed check for max backlight, since it is already done by backlight_device_set_brightness. - Fixed minor formatting issues on devicetree binding documentation and added port to provided example. Changes since V1: - Removed errant reference to backlight in documentation. This is an OLED panel. - Made elvss regulator optional. In my case its hard wired and not controllable. - Added "prepared" enum to track panel status to prevent unbalanced regulator enable/disable. Chris Morgan (4): drm: of: Add drm_of_get_dsi_bus helper function dt-bindings: display: panel: Add Samsung AMS495QA01 drm/panel: Add Magnachip D53E6EA8966 Panel Driver arm64: dts: rockchip: add display to RG503 .../display/panel/samsung,ams495qa01.yaml | 57 ++ .../dts/rockchip/rk3566-anbernic-rg503.dts| 55 ++ drivers/gpu/drm/drm_of.c | 70 +++ drivers/gpu/drm/panel/Kconfig | 11 + drivers/gpu/drm/panel/Makefile| 1 + .../drm/panel/panel-magnachip-d53e6ea8966.c | 522 ++ include/drm/drm_of.h | 10 + 7 files changed, 726 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml create mode 100644 drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c -- 2.34.1
[PATCH V10 4/4] arm64: dts: rockchip: add display to RG503
From: Chris Morgan
Add Samsung AMS495QA01 panel to RG503.
Signed-off-by: Chris Morgan
Signed-off-by: Maya Matuszczyk
---
.../dts/rockchip/rk3566-anbernic-rg503.dts| 55 +++
1 file changed, 55 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
index 5dafcc86296b..b4b2df821cba 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
@@ -47,6 +47,21 @@ gpio_spi: spi {
mosi-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
num-chipselects = <0>;
+
+ panel@0 {
+ compatible = "samsung,ams495qa01";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_reset>;
+ reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&vcc_3v3>;
+
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
+ };
};
/* Channels reversed for both headphones and speakers. */
@@ -94,6 +109,32 @@ &cru {
assigned-clock-rates = <12>, <2>, <5>;
};
+&dsi_dphy0 {
+ status = "okay";
+};
+
+&dsi0 {
+ status = "okay";
+
+ ports {
+ dsi0_in: port@0 {
+ reg = <0>;
+
+ dsi0_in_vp1: endpoint {
+ remote-endpoint = <&vp1_out_dsi0>;
+ };
+ };
+
+ dsi0_out: port@1 {
+ reg = <1>;
+
+ mipi_out_panel: endpoint {
+ remote-endpoint = <&mipi_in_panel>;
+ };
+ };
+ };
+};
+
&gpio_keys_control {
button-a {
gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
@@ -146,6 +187,13 @@ spk_amp_enable_h: spk-amp-enable-h {
};
};
+ gpio-lcd {
+ lcd_reset: lcd-reset {
+ rockchip,pins =
+ <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
gpio-spi {
spi_pins: spi-pins {
rockchip,pins =
@@ -164,3 +212,10 @@ rk817_charger: charger {
rockchip,sleep-filter-current-microamp = <10>;
};
};
+
+&vp1 {
+ vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 {
+ reg = ;
+ remote-endpoint = <&dsi0_in_vp1>;
+ };
+};
--
2.34.1
[PATCH V10 3/4] drm/panel: Add Magnachip D53E6EA8966 Panel Driver
From: Chris Morgan
Support Magnachip D53E6EA8966 based panels such as the Samsung
AMS495QA01 panel as found on the Anbernic RG503. Note this driver
supports only the AMS495QA01 today which receives video signals via DSI,
however it receives commands via 3-wire SPI using DBI.
Signed-off-by: Chris Morgan
Signed-off-by: Maya Matuszczyk
---
drivers/gpu/drm/panel/Kconfig | 11 +
drivers/gpu/drm/panel/Makefile| 1 +
.../drm/panel/panel-magnachip-d53e6ea8966.c | 522 ++
3 files changed, 534 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 737edcdf9eef..204b84a83604 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -298,6 +298,17 @@ config DRM_PANEL_LG_LG4573
Say Y here if you want to enable support for LG4573 RGB panel.
To compile this driver as a module, choose M here.
+config DRM_PANEL_MAGNACHIP_D53E6EA8966
+ tristate "Magnachip D53E6EA8966 DSI panel"
+ depends on OF && SPI
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ select DRM_MIPI_DBI
+ help
+ DRM panel driver for the Samsung AMS495QA01 panel controlled
+ with the Magnachip D53E6EA8966 panel IC. This panel receives
+ video data via DSI but commands via 9-bit SPI using DBI.
+
config DRM_PANEL_NEC_NL8048HL11
tristate "NEC NL8048HL11 RGB panel"
depends on GPIOLIB && OF && SPI
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index f8f9d9f6a307..20de312aa5e9 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W) +=
panel-leadtek-ltk050h3146w.o
obj-$(CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829) += panel-leadtek-ltk500hd1829.o
obj-$(CONFIG_DRM_PANEL_LG_LB035Q02) += panel-lg-lb035q02.o
obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
+obj-$(CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966) += panel-magnachip-d53e6ea8966.o
obj-$(CONFIG_DRM_PANEL_NEC_NL8048HL11) += panel-nec-nl8048hl11.o
obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3051D) += panel-newvision-nv3051d.o
obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3052C) += panel-newvision-nv3052c.o
diff --git a/drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c
b/drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c
new file mode 100644
index ..09ee12f0a147
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c
@@ -0,0 +1,522 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Magnachip d53e6ea8966 MIPI-DSI panel driver
+ * Copyright (C) 2023 Chris Morgan
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+/* Forward declaration for use in backlight function */
+struct d53e6ea8966;
+
+/* Panel info, unique to each panel */
+struct d53e6ea8966_panel_info {
+ /** @display_modes: the supported display modes */
+ const struct drm_display_mode *display_modes;
+ /** @num_modes: the number of supported display modes */
+ unsigned int num_modes;
+ /** @width_mm: panel width in mm */
+ u16 width_mm;
+ /** @height_mm: panel height in mm */
+ u16 height_mm;
+ /** @bus_flags: drm bus flags for panel */
+ u32 bus_flags;
+ /** @panel_init_seq: panel specific init sequence */
+ void (*panel_init_seq)(struct d53e6ea8966 *db);
+ /** @backlight_register: panel backlight registration or NULL */
+ int (*backlight_register)(struct d53e6ea8966 *db);
+};
+
+struct d53e6ea8966 {
+ /** @dev: the container device */
+ struct device *dev;
+ /** @dbi: the DBI bus abstraction handle */
+ struct mipi_dbi dbi;
+ /** @panel: the DRM panel instance for this device */
+ struct drm_panel panel;
+ /** @reset: reset GPIO line */
+ struct gpio_desc *reset;
+ /** @enable: enable GPIO line */
+ struct gpio_desc *enable;
+ /** @reg_vdd: VDD supply regulator for panel logic */
+ struct regulator *reg_vdd;
+ /** @reg_elvdd: ELVDD supply regulator for panel display */
+ struct regulator *reg_elvdd;
+ /** @dsi_dev: DSI child device (panel) */
+ struct mipi_dsi_device *dsi_dev;
+ /** @bl_dev: pseudo-backlight device for oled panel */
+ struct backlight_device *bl_dev;
+ /** @panel_info: struct containing panel timing and info */
+ const struct d53e6ea8966_panel_info *panel_info;
+};
+
+#define NUM_GAMMA_LEVELS 16
+#define GAMMA_TABLE_COUNT 23
+#define MAX_BRIGHTNESS (NUM_GAMMA_LEVELS - 1)
+
+#define MCS_ELVSS_ON 0xb1
+#define MCS_TEMP_SWIRE 0xb2
+#define MCS_PASSWORD_0
[PATCH V10 1/4] drm: of: Add drm_of_get_dsi_bus helper function
From: Chris Morgan
Add helper function to find DSI host for devices where DSI panel is not
a minor of a DSI bus (such as the Samsung AMS495QA01 panel or the
official Raspberry Pi touchscreen display).
Signed-off-by: Chris Morgan
Signed-off-by: Maya Matuszczyk
---
drivers/gpu/drm/drm_of.c | 70
include/drm/drm_of.h | 10 ++
2 files changed, 80 insertions(+)
diff --git a/drivers/gpu/drm/drm_of.c b/drivers/gpu/drm/drm_of.c
index 7bbcb999bb75..6c2c97a716fe 100644
--- a/drivers/gpu/drm/drm_of.c
+++ b/drivers/gpu/drm/drm_of.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
#include
@@ -493,3 +494,72 @@ int drm_of_get_data_lanes_count_ep(const struct
device_node *port,
return ret;
}
EXPORT_SYMBOL_GPL(drm_of_get_data_lanes_count_ep);
+
+#if IS_ENABLED(CONFIG_DRM_MIPI_DSI)
+
+/**
+ * drm_of_get_dsi_bus - find the DSI bus for a given device
+ * @dev: parent device of display (SPI, I2C)
+ * @info: DSI device info to be updated with DSI node. This is optional
+ * and if not needed can be NULL.
+ *
+ * Gets parent DSI bus for a DSI device controlled through a bus other
+ * than MIPI-DCS (SPI, I2C, etc.) using the Device Tree.
+ *
+ * Returns pointer to mipi_dsi_host if successful, -EINVAL if the
+ * request is unsupported, -EPROBE_DEFER if the DSI host is found but
+ * not available, or -ENODEV otherwise.
+ */
+struct mipi_dsi_host *drm_of_get_dsi_bus(struct device *dev,
+struct mipi_dsi_device_info *info)
+{
+ struct mipi_dsi_host *dsi_host;
+ struct device_node *endpoint, *dsi_host_node;
+
+ /*
+* Get first endpoint child from device.
+*/
+ endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
+ if (!endpoint)
+ return ERR_PTR(-ENODEV);
+
+ /*
+* Follow the first endpoint to get the DSI host node.
+*/
+ dsi_host_node = of_graph_get_remote_port_parent(endpoint);
+ if (!dsi_host_node)
+ goto error;
+
+ /*
+* Get the DSI host from the DSI host node. If we get an error
+* or the return is null assume we're not ready to probe just
+* yet. Release the DSI host node since we're done with it.
+*/
+ dsi_host = of_find_mipi_dsi_host_by_node(dsi_host_node);
+ of_node_put(dsi_host_node);
+ if (IS_ERR_OR_NULL(dsi_host)) {
+ of_node_put(endpoint);
+ return ERR_PTR(-EPROBE_DEFER);
+ }
+
+ /*
+* Set the node of the mipi_dsi_device_info to the correct node
+* and then release the endpoint node since we're done with it.
+* since this is optional, check if the info is NULL first.
+*/
+ if (info) {
+ info->node = of_graph_get_remote_port(endpoint);
+ if (IS_ERR_OR_NULL(info->node))
+ goto error;
+ }
+
+ of_node_put(endpoint);
+ return dsi_host;
+
+error:
+ of_node_put(endpoint);
+ return ERR_PTR(-ENODEV);
+}
+EXPORT_SYMBOL_GPL(drm_of_get_dsi_bus);
+
+#endif /* CONFIG_DRM_MIPI_DSI */
diff --git a/include/drm/drm_of.h b/include/drm/drm_of.h
index 10ab58c40746..705ea2caa494 100644
--- a/include/drm/drm_of.h
+++ b/include/drm/drm_of.h
@@ -15,6 +15,8 @@ struct drm_encoder;
struct drm_panel;
struct drm_bridge;
struct device_node;
+struct mipi_dsi_device_info;
+struct mipi_dsi_host;
/**
* enum drm_lvds_dual_link_pixels - Pixel order of an LVDS dual-link connection
@@ -56,6 +58,8 @@ int drm_of_get_data_lanes_count_ep(const struct device_node
*port,
int port_reg, int reg,
const unsigned int min,
const unsigned int max);
+struct mipi_dsi_host *drm_of_get_dsi_bus(struct device *dev,
+struct mipi_dsi_device_info *info);
#else
static inline uint32_t drm_of_crtc_port_mask(struct drm_device *dev,
struct device_node *port)
@@ -127,6 +131,12 @@ drm_of_get_data_lanes_count_ep(const struct device_node
*port,
{
return -EINVAL;
}
+static inline struct
+mipi_dsi_host *drm_of_get_dsi_bus(struct device *dev,
+struct mipi_dsi_device_info *info)
+{
+ return ERR_PTR(-EINVAL);
+}
#endif
/*
--
2.34.1
[PATCH V10 2/4] dt-bindings: display: panel: Add Samsung AMS495QA01
From: Chris Morgan
Add documentation for Samsung AMS495QA01 panel (with Magnachip
D53E6EA8966 controller IC).
Signed-off-by: Chris Morgan
Signed-off-by: Maya Matuszczyk
Reviewed-by: Rob Herring
---
.../display/panel/samsung,ams495qa01.yaml | 57 +++
1 file changed, 57 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
diff --git
a/Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
b/Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
new file mode 100644
index ..58fa073ce258
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/samsung,ams495qa01.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung AMS495QA01 panel with Magnachip D53E6EA8966 controller
+
+maintainers:
+ - Chris Morgan
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+const: samsung,ams495qa01
+
+ reg: true
+ reset-gpios:
+description: reset gpio, must be GPIO_ACTIVE_LOW
+ elvdd-supply:
+description: regulator that supplies voltage to the panel display
+ enable-gpios: true
+ port: true
+ vdd-supply:
+description: regulator that supplies voltage to panel logic
+
+required:
+ - compatible
+ - reg
+ - reset-gpios
+ - vdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+spi {
+#address-cells = <1>;
+#size-cells = <0>;
+panel@0 {
+compatible = "samsung,ams495qa01";
+reg = <0>;
+reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
+vdd-supply = <&vcc_3v3>;
+
+port {
+mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+};
+};
+};
+};
+
+...
--
2.34.1
Re: [PATCH V10 1/4] drm: of: Add drm_of_get_dsi_bus helper function
On Tue, Jan 17, 2023 at 05:58:19PM +0100, Maxime Ripard wrote:
> Hi,
>
> On Thu, Jan 12, 2023 at 11:53:55AM -0600, Chris Morgan wrote:
> > From: Chris Morgan
> >
> > Add helper function to find DSI host for devices where DSI panel is not
> > a minor of a DSI bus (such as the Samsung AMS495QA01 panel or the
> > official Raspberry Pi touchscreen display).
> >
> > Signed-off-by: Chris Morgan
> > Signed-off-by: Maya Matuszczyk
> > ---
> > drivers/gpu/drm/drm_of.c | 70
> > include/drm/drm_of.h | 10 ++
> > 2 files changed, 80 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_of.c b/drivers/gpu/drm/drm_of.c
> > index 7bbcb999bb75..6c2c97a716fe 100644
> > --- a/drivers/gpu/drm/drm_of.c
> > +++ b/drivers/gpu/drm/drm_of.c
> > @@ -10,6 +10,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> >
> > @@ -493,3 +494,72 @@ int drm_of_get_data_lanes_count_ep(const struct
> > device_node *port,
> > return ret;
> > }
> > EXPORT_SYMBOL_GPL(drm_of_get_data_lanes_count_ep);
> > +
> > +#if IS_ENABLED(CONFIG_DRM_MIPI_DSI)
> > +
> > +/**
> > + * drm_of_get_dsi_bus - find the DSI bus for a given device
> > + * @dev: parent device of display (SPI, I2C)
> > + * @info: DSI device info to be updated with DSI node. This is optional
> > + * and if not needed can be NULL.
> > + *
> > + * Gets parent DSI bus for a DSI device controlled through a bus other
> > + * than MIPI-DCS (SPI, I2C, etc.) using the Device Tree.
> > + *
> > + * Returns pointer to mipi_dsi_host if successful, -EINVAL if the
> > + * request is unsupported, -EPROBE_DEFER if the DSI host is found but
> > + * not available, or -ENODEV otherwise.
> > + */
> > +struct mipi_dsi_host *drm_of_get_dsi_bus(struct device *dev,
> > +struct mipi_dsi_device_info *info)
> > +{
> > + struct mipi_dsi_host *dsi_host;
> > + struct device_node *endpoint, *dsi_host_node;
> > +
> > + /*
> > +* Get first endpoint child from device.
> > +*/
> > + endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
> > + if (!endpoint)
> > + return ERR_PTR(-ENODEV);
> > +
> > + /*
> > +* Follow the first endpoint to get the DSI host node.
> > +*/
> > + dsi_host_node = of_graph_get_remote_port_parent(endpoint);
> > + if (!dsi_host_node)
> > + goto error;
> > +
> > + /*
> > +* Get the DSI host from the DSI host node. If we get an error
> > +* or the return is null assume we're not ready to probe just
> > +* yet. Release the DSI host node since we're done with it.
> > +*/
> > + dsi_host = of_find_mipi_dsi_host_by_node(dsi_host_node);
> > + of_node_put(dsi_host_node);
> > + if (IS_ERR_OR_NULL(dsi_host)) {
> > + of_node_put(endpoint);
> > + return ERR_PTR(-EPROBE_DEFER);
> > + }
> > +
> > + /*
> > +* Set the node of the mipi_dsi_device_info to the correct node
> > +* and then release the endpoint node since we're done with it.
> > +* since this is optional, check if the info is NULL first.
> > +*/
> > + if (info) {
> > + info->node = of_graph_get_remote_port(endpoint);
>
> it looks to me that the info->node is actually the DSI device OF node,
> not its host port. Which begs the question, why should we even return it
> there, since there's a pretty big chance that dev->of.node ==
> info->node, and you obviously don't care about the channel and type fields.
>
> I've had a look and node of the current users of
> mipi_dsi_device_register_full actually register a mipi_dsi_device_info
> with a node pointer set to !NULL, including the driver in this series.
>
> So, why do we care about the device info at all?
>
I honestly thought it might be useful, but I can try without it.
> > + if (IS_ERR_OR_NULL(info->node))
>
> of_graph_get_remote_port doesn't return an error pointer.
>
> > --- a/include/drm/drm_of.h
> > +++ b/include/drm/drm_of.h
> > @@ -15,6 +15,8 @@ struct drm_encoder;
> > struct drm_panel;
> > struct drm_bridge;
> > struct device_node;
> > +struct mipi_dsi_device_info;
> > +struct mipi_dsi_host;
> >
> > /**
> > * enum drm_lvds_dual_link_pixels - Pixel order of an LVDS dual-link
> > connection
> > @@ -56,6 +58,8 @@
[PATCH V11 1/4] drm: of: Add drm_of_get_dsi_bus helper function
From: Chris Morgan
Add helper function to find DSI host for devices where DSI panel is not
a minor of a DSI bus (such as the Samsung AMS495QA01 panel or the
official Raspberry Pi touchscreen display).
Signed-off-by: Chris Morgan
Signed-off-by: Maya Matuszczyk
---
drivers/gpu/drm/drm_of.c | 51
include/drm/drm_of.h | 12 ++
2 files changed, 63 insertions(+)
diff --git a/drivers/gpu/drm/drm_of.c b/drivers/gpu/drm/drm_of.c
index 7bbcb999bb75..177b600895d3 100644
--- a/drivers/gpu/drm/drm_of.c
+++ b/drivers/gpu/drm/drm_of.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
#include
@@ -493,3 +494,53 @@ int drm_of_get_data_lanes_count_ep(const struct
device_node *port,
return ret;
}
EXPORT_SYMBOL_GPL(drm_of_get_data_lanes_count_ep);
+
+#if IS_ENABLED(CONFIG_DRM_MIPI_DSI)
+
+/**
+ * drm_of_get_dsi_bus - find the DSI bus for a given device
+ * @dev: parent device of display (SPI, I2C)
+ *
+ * Gets parent DSI bus for a DSI device controlled through a bus other
+ * than MIPI-DCS (SPI, I2C, etc.) using the Device Tree.
+ *
+ * Returns pointer to mipi_dsi_host if successful, -EINVAL if the
+ * request is unsupported, -EPROBE_DEFER if the DSI host is found but
+ * not available, or -ENODEV otherwise.
+ */
+struct mipi_dsi_host *drm_of_get_dsi_bus(struct device *dev)
+{
+ struct mipi_dsi_host *dsi_host;
+ struct device_node *endpoint, *dsi_host_node;
+
+ /*
+* Get first endpoint child from device.
+*/
+ endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
+ if (!endpoint)
+ return ERR_PTR(-ENODEV);
+
+ /*
+* Follow the first endpoint to get the DSI host node and then
+* release the endpoint since we no longer need it.
+*/
+ dsi_host_node = of_graph_get_remote_port_parent(endpoint);
+ of_node_put(endpoint);
+ if (!dsi_host_node)
+ return ERR_PTR(-ENODEV);
+
+ /*
+* Get the DSI host from the DSI host node. If we get an error
+* or the return is null assume we're not ready to probe just
+* yet. Release the DSI host node since we're done with it.
+*/
+ dsi_host = of_find_mipi_dsi_host_by_node(dsi_host_node);
+ of_node_put(dsi_host_node);
+ if (IS_ERR_OR_NULL(dsi_host))
+ return ERR_PTR(-EPROBE_DEFER);
+
+ return dsi_host;
+}
+EXPORT_SYMBOL_GPL(drm_of_get_dsi_bus);
+
+#endif /* CONFIG_DRM_MIPI_DSI */
diff --git a/include/drm/drm_of.h b/include/drm/drm_of.h
index 10ab58c40746..082a6e980d01 100644
--- a/include/drm/drm_of.h
+++ b/include/drm/drm_of.h
@@ -15,6 +15,8 @@ struct drm_encoder;
struct drm_panel;
struct drm_bridge;
struct device_node;
+struct mipi_dsi_device_info;
+struct mipi_dsi_host;
/**
* enum drm_lvds_dual_link_pixels - Pixel order of an LVDS dual-link connection
@@ -129,6 +131,16 @@ drm_of_get_data_lanes_count_ep(const struct device_node
*port,
}
#endif
+#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DRM_MIPI_DSI)
+struct mipi_dsi_host *drm_of_get_dsi_bus(struct device *dev);
+#else
+static inline struct
+mipi_dsi_host *drm_of_get_dsi_bus(struct device *dev)
+{
+ return ERR_PTR(-EINVAL);
+}
+#endif /* CONFIG_OF && CONFIG_DRM_MIPI_DSI */
+
/*
* drm_of_panel_bridge_remove - remove panel bridge
* @np: device tree node containing panel bridge output ports
--
2.34.1
[PATCH V11 0/4] drm/panel: Add Magnachip D53E6EA8966 Panel Controller
From: Chris Morgan Add the Magnachip D53E6EA8966 panel IC controller for display panels such as the Samsung AMS495QA01 panel as found on the Anbernic RG503. This panel uses DSI to receive video signals, but 3-wire SPI to receive command signals using DBI. Changes since V10: - Guarded definition in drm_of.h with an additional #if statement. - Narrowed focus of drm_of_get_dsi_bus() to only return dsi_host (no longer populates node on the mipi_dsi_device_info struct). Changes since V9: - Set an ifdef to not add the drm_of_get_dsi_bus when MIPI_DSI is not part of the current kernel config. - Made "info" optional in the drm_of_get_dsi_bus() function. Changes since V8: - Set "placeholder" drm_of_get_dsi_bus in drm_of.h to static inline to hopefully eliminate the reported errors once and for all. Tested with 4 different kernel configurations provided by Intel's kernel test robot and no new warnings or errors were introduced. Reported-by: kernel test robot Changes since V7: - Removed Linus Walleij review note due to substantial changes. - Corrected documentation of drm_of_get_dsi_bus function. - Updated the drm_of_get_dsi_bus function to return pointer to mipi_dsi_host and use ERR_PTR macros. - Refactored drm_panel_funcs so that the prepare function calls panel specific function for init sequence and uses generic functions otherwise. - Renamed non-panel specific functions. - Changed backlight value to int instead of u32. - Corrected brightness function to use backlight_get_brightness(). - Fix an error reported when CONFIG_OF is selected but CONFIG_DRM_MIPI_DSI is not. Add an if function to drm_of_get_dsi_bus function to return -EINVAL in this instance. Reported-by: kernel test robot Changes since V6: - Fixed a trivial error with definition of drm_of_get_dsi_bus(). Reported-by: kernel test robot Changes since V5: - Reverted dt binding documentation name back to samsung,ams495qa01.yaml. - Removed no longer needed of_graph.h header file. - Added backlight as a dependency. Changes since V4: - Renamed driver from the panel model to the panel IC controller per DRM team. - Added a drm_of helper function of drm_of_get_dsi_bus() to handle finding and populating the DSI node when the DSI node is not the parent of the DSI controlled display. - Converted the documented commands to constants to make it more readable. - Reset GPIO is now required and documented as GPIO_ACTIVE_LOW. - Removed "prepared" logic from panel. Changes since V3: - Updated documentation to add spi-peripheral-props.yaml per updates made for similar devices. Note that I removed a "Reviewed-by" tag from Rob Herring since this change probably needs to be confirmed. - Added binding for RG503, since this device is now accepted with this request: https://lore.kernel.org/linux-rockchip/166274831283.21181.6861718157177507544.b4...@sntech.de/ Changes since V2: - Added 50hz mode at request of userspace devs. - Renamed "dupa" to panel name. Good catch Maya. - Added Maya's Signed-off-by. - Removed check for max backlight, since it is already done by backlight_device_set_brightness. - Fixed minor formatting issues on devicetree binding documentation and added port to provided example. Changes since V1: - Removed errant reference to backlight in documentation. This is an OLED panel. - Made elvss regulator optional. In my case its hard wired and not controllable. - Added "prepared" enum to track panel status to prevent unbalanced regulator enable/disable. Chris Morgan (4): drm: of: Add drm_of_get_dsi_bus helper function dt-bindings: display: panel: Add Samsung AMS495QA01 drm/panel: Add Magnachip D53E6EA8966 Panel Driver arm64: dts: rockchip: add display to RG503 .../display/panel/samsung,ams495qa01.yaml | 57 ++ .../dts/rockchip/rk3566-anbernic-rg503.dts| 55 ++ drivers/gpu/drm/drm_of.c | 51 ++ drivers/gpu/drm/panel/Kconfig | 11 + drivers/gpu/drm/panel/Makefile| 1 + .../drm/panel/panel-magnachip-d53e6ea8966.c | 522 ++ include/drm/drm_of.h | 12 + 7 files changed, 709 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/samsung,ams495qa01.yaml create mode 100644 drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c -- 2.34.1
