Re: [PATCH v5 0/4] drm/solomon: Add support for the SSD133x controller family
Javier Martinez Canillas writes: > Hello, > > This patch-set adds support for the family of SSD133x Solomon controllers, > such as the SSD1331. These are used for RGB Dot Matrix OLED/PLED panels. > > This is a v5 that is basically the same than the previous v4 but dropping > support for I2C since the ssd133x family does not support that interface. > > The patches were tested on a Waveshare SSD1331 display using glmark2-drm, > fbcon, fbtests and the retroarch emulator. The binding schema were tested > using the `make W=1 dt_binding_check` target. > > Patch #1 and #2 are fixes for the DT binding schema of the existing SSD130x > and SSD132x families. > > Patch #3 adds a DT binding schema for the SSD133x controllers and patch #4 > extends the ssd130x DRM driver to support the SSD133x controller family. > > Best regards, > Javier Pushed to drm-misc (drm-misc-next). Thanks! -- Best regards, Javier Martinez Canillas Core Platforms Red Hat
[PATCH v2 0/8] Add display support for stm32f769-disco board
The series adds display support for the stm32f769-disco board. It has been tested on hardware revisions MB1225-B03 and MB1166-A09. This required modifications to the nt35510 driver. As I do not have the Hydis HVA40WV1 display, it would be better if someone tested the driver in that configuration. Changes in v2: - Add Acked-by tag of Conor Dooley - Add a dash in front of each "items:" - Change the status of panel_backlight node to "disabled" - Delete backlight property from panel0 node. - Re-write the patch [7/8] "drm/panel: nt35510: refactor panel initialization" in the same style as the original driver in order to maintain the same structure. - Re-write the patch [8/8] "drm/panel: nt35510: support FRIDA FRD400B25025-A-CTK" in the same style as the original driver. Dario Binacchi (8): dt-bindings: mfd: stm32f7: Add binding definition for DSI ARM: dts: stm32: add DSI support on stm32f769 ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f769-disco ARM: dts: stm32: add display support on stm32f769-disco dt-bindings: nt35510: add compatible for FRIDA FRD400B25025-A-CTK ARM: dts: add stm32f769-disco-mb1225-revb03-mb1166-reva09 drm/panel: nt35510: move hardwired parameters to configuration drm/panel: nt35510: support FRIDA FRD400B25025-A-CTK .../display/panel/novatek,nt35510.yaml| 10 +- arch/arm/boot/dts/st/Makefile | 1 + ...f769-disco-mb1225-revb03-mb1166-reva09.dts | 18 + arch/arm/boot/dts/st/stm32f769-disco.dts | 78 +++- arch/arm/boot/dts/st/stm32f769.dtsi | 21 + drivers/gpu/drm/panel/panel-novatek-nt35510.c | 422 +++--- include/dt-bindings/mfd/stm32f7-rcc.h | 1 + 7 files changed, 488 insertions(+), 63 deletions(-) create mode 100644 arch/arm/boot/dts/st/stm32f769-disco-mb1225-revb03-mb1166-reva09.dts create mode 100644 arch/arm/boot/dts/st/stm32f769.dtsi -- 2.43.0
[PATCH v2 5/8] dt-bindings: nt35510: add compatible for FRIDA FRD400B25025-A-CTK
The patch adds the FRIDA FRD400B25025-A-CTK panel, which belongs to the Novatek NT35510-based panel family. Signed-off-by: Dario Binacchi --- Changes in v2: - Add a dash in front of each "items:" .../bindings/display/panel/novatek,nt35510.yaml| 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml index bc92928c805b..8e69446e00e0 100644 --- a/Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml +++ b/Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml @@ -14,9 +14,13 @@ allOf: properties: compatible: -items: - - const: hydis,hva40wv1 - - const: novatek,nt35510 +oneOf: + - items: + - const: hydis,hva40wv1 + - const: novatek,nt35510 + - items: + - const: frida,frd400b25025 + - const: novatek,nt35510 description: This indicates the panel manufacturer of the panel that is in turn using the NT35510 panel driver. The compatible string determines how the NT35510 panel driver shall be configured -- 2.43.0
[PATCH v2 7/8] drm/panel: nt35510: move hardwired parameters to configuration
This patch, preparatory for future developments, move the hardwired
parameters to configuration data to allow the addition of new
NT35510-based panels.
Signed-off-by: Dario Binacchi
---
Changes in v2:
- Re-write the patch [7/8] "drm/panel: nt35510: refactor panel initialization"
in the same style as the original driver in order to maintain the same
structure.
drivers/gpu/drm/panel/panel-novatek-nt35510.c | 140 ++
1 file changed, 115 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-novatek-nt35510.c
b/drivers/gpu/drm/panel/panel-novatek-nt35510.c
index d6dceb858008..ce8969f48286 100644
--- a/drivers/gpu/drm/panel/panel-novatek-nt35510.c
+++ b/drivers/gpu/drm/panel/panel-novatek-nt35510.c
@@ -171,6 +171,10 @@ struct nt35510_config {
* timing in the display controller.
*/
const struct drm_display_mode mode;
+ /**
+* @mode_flags: DSI operation mode related flags
+*/
+ unsigned long mode_flags;
/**
* @avdd: setting for AVDD ranging from 0x00 = 6.5V to 0x14 = 4.5V
* in 0.1V steps the default is 0x05 which means 6.0V
@@ -273,6 +277,100 @@ struct nt35510_config {
* same layout of bytes as @vgp.
*/
u8 vgn[NT35510_P1_VGN_LEN];
+ /**
+* @dopctr: setting optional control for display
+* ERR bits 0..1 in the first byte is the ERR pin output signal setting.
+* 0 = Disable, ERR pin output low
+* 1 = ERR pin output CRC error only
+* 2 = ERR pin output ECC error only
+* 3 = ERR pin output CRC and ECC error
+* The default is 0.
+* N565 bit 2 in the first byte is the 16-bit/pixel format selection.
+* 0 = R[4:0] + G[5:3] & G[2:0] + B[4:0]
+* 1 = G[2:0] + R[4:0] & B[4:0] + G[5:3]
+* The default is 0.
+* DIS_EoTP_HS bit 3 in the first byte is "DSI protocol violation" error
+* reporting.
+* 0 = reporting when error
+* 1 = not reporting when error
+* DSIM bit 4 in the first byte is the video mode data type enable
+* 0 = Video mode data type disable
+* 1 = Video mode data type enable
+* The default is 0.
+* DSIG bit 5 int the first byte is the generic r/w data type enable
+* 0 = Generic r/w disable
+* 1 = Generic r/w enable
+* The default is 0.
+* DSITE bit 6 in the first byte is TE line enable
+* 0 = TE line is disabled
+* 1 = TE line is enabled
+* The default is 0.
+* RAMKP bit 7 in the first byte is the frame memory keep/loss in
+* sleep-in mode
+* 0 = contents loss in sleep-in
+* 1 = contents keep in sleep-in
+* The default is 0.
+* CRL bit 1 in the second byte is the source driver data shift
+* direction selection. This bit is XOR operation with bit RSMX
+* of 3600h command.
+* 0 (RMSX = 0) = S1 -> S1440
+* 0 (RMSX = 1) = S1440 -> S1
+* 1 (RMSX = 0) = S1440 -> S1
+* 1 (RMSX = 1) = S1 -> S1440
+* The default is 0.
+* CTB bit 2 in the second byte is the vertical scanning direction
+* selection for gate control signals. This bit is XOR operation
+* with bit ML of 3600h command.
+* 0 (ML = 0) = Forward (top -> bottom)
+* 0 (ML = 1) = Reverse (bottom -> top)
+* 1 (ML = 0) = Reverse (bottom -> top)
+* 1 (ML = 1) = Forward (top -> bottom)
+* The default is 0.
+* CRGB bit 3 in the second byte is RGB-BGR order selection. This
+* bit is XOR operation with bit RGB of 3600h command.
+* 0 (RGB = 0) = RGB/Normal
+* 0 (RGB = 1) = BGR/RB swap
+* 1 (RGB = 0) = BGR/RB swap
+* 1 (RGB = 1) = RGB/Normal
+* The default is 0.
+* TE_PWR_SEL bit 4 in the second byte is the TE output voltage
+* level selection (only valid when DSTB_SEL = 0 or DSTB_SEL = 1,
+* VSEL = High and VDDI = 1.665~3.3V).
+* 0 = TE output voltage level is VDDI
+* 1 = TE output voltage level is VDDA
+* The default is 0.
+*/
+ u8 dopctr[NT35510_P0_DOPCTR_LEN];
+ /**
+* @madctl: Memory data access control
+* RSMY bit 0 is flip vertical. Flips the display image top to down.
+* RSMX bit 1 is flip horizontal. Flips the display image left to right.
+* MH bit 2 is the horizontal refresh order.
+* RGB bit 3 is the RGB-BGR order.
+* 0 = RGB color sequence
+* 1 = BGR color sequence
+* ML bit 4 is the vertical refresh order.
+* MV bit 5 is the row/column exchange.
+* MX bit 6 is the column address order.
+* MY bit 7 is the row address order.
+*/
+ u8 madctl;
+ /**
+* @sdhdtctr: source output data hold time
+* 0x00..0x3F = 0..31.5us in steps of 0.5us
+* The default is 0x05 = 2.5us.
+*/
+ u8
[PATCH v2 8/8] drm/panel: nt35510: support FRIDA FRD400B25025-A-CTK
The initialization commands are taken from the STMicroelectronics driver
found at [1].
To ensure backward compatibility, flags have been added to enable gamma
correction setting and display control. In other cases, registers have
been set to their default values according to the specifications found
in the datasheet.
[1]
https://github.com/STMicroelectronics/STM32CubeF7/blob/master/Drivers/BSP/Components/nt35510/
Signed-off-by: Dario Binacchi
---
Changes in v2:
- Re-write the patch [8/8] "drm/panel: nt35510: support FRIDA
FRD400B25025-A-CTK"
in the same style as the original driver.
drivers/gpu/drm/panel/panel-novatek-nt35510.c | 282 --
1 file changed, 251 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-novatek-nt35510.c
b/drivers/gpu/drm/panel/panel-novatek-nt35510.c
index ce8969f48286..c85dd0d0829d 100644
--- a/drivers/gpu/drm/panel/panel-novatek-nt35510.c
+++ b/drivers/gpu/drm/panel/panel-novatek-nt35510.c
@@ -36,6 +36,9 @@
#include
#include
+#define NT35510_CMD_CORRECT_GAMMA BIT(0)
+#define NT35510_CMD_CONTROL_DISPLAY BIT(1)
+
#define MCS_CMD_MAUCCTR0xF0 /* Manufacturer command enable */
#define MCS_CMD_READ_ID1 0xDA
#define MCS_CMD_READ_ID2 0xDB
@@ -112,18 +115,33 @@
/* AVDD and AVEE setting 3 bytes */
#define NT35510_P1_AVDD_LEN 3
#define NT35510_P1_AVEE_LEN 3
+#define NT35510_P1_VCL_LEN 3
#define NT35510_P1_VGH_LEN 3
#define NT35510_P1_VGL_LEN 3
#define NT35510_P1_VGP_LEN 3
#define NT35510_P1_VGN_LEN 3
+#define NT35510_P1_VCMOFF_LEN 2
/* BT1CTR thru BT5CTR setting 3 bytes */
#define NT35510_P1_BT1CTR_LEN 3
#define NT35510_P1_BT2CTR_LEN 3
+#define NT35510_P1_BT3CTR_LEN 3
#define NT35510_P1_BT4CTR_LEN 3
#define NT35510_P1_BT5CTR_LEN 3
/* 52 gamma parameters times two per color: positive and negative */
#define NT35510_P1_GAMMA_LEN 52
+#define NT35510_WRCTRLD_BCTRL BIT(5)
+#define NT35510_WRCTRLD_A BIT(4)
+#define NT35510_WRCTRLD_DD BIT(3)
+#define NT35510_WRCTRLD_BL BIT(2)
+#define NT35510_WRCTRLD_DB BIT(1)
+#define NT35510_WRCTRLD_G BIT(0)
+
+#define NT35510_WRCABC_OFF 0
+#define NT35510_WRCABC_UI_MODE 1
+#define NT35510_WRCABC_STILL_MODE 2
+#define NT35510_WRCABC_MOVING_MODE 3
+
/**
* struct nt35510_config - the display-specific NT35510 configuration
*
@@ -175,6 +193,10 @@ struct nt35510_config {
* @mode_flags: DSI operation mode related flags
*/
unsigned long mode_flags;
+ /**
+* @cmds: enable DSI commands
+*/
+ u32 cmds;
/**
* @avdd: setting for AVDD ranging from 0x00 = 6.5V to 0x14 = 4.5V
* in 0.1V steps the default is 0x05 which means 6.0V
@@ -224,6 +246,25 @@ struct nt35510_config {
* The defaults are 4 and 3 yielding 0x34
*/
u8 bt2ctr[NT35510_P1_BT2CTR_LEN];
+ /**
+* @vcl: setting for VCL ranging from 0x00 = -2.5V to 0x11 = -4.0V
+* in 1V steps, the default is 0x00 which means -2.5V
+*/
+ u8 vcl[NT35510_P1_VCL_LEN];
+ /**
+* @bt3ctr: setting for boost power control for the VCL step-up
+* circuit (3)
+* bits 0..2 in the lower nibble controls CLCK, the booster clock
+* frequency, the values are the same as for PCK in @bt1ctr.
+* bits 4..5 in the upper nibble controls BTCL, the boosting
+* amplification for the step-up circuit.
+* 0 = Disable
+* 1 = -0.5 x VDDB
+* 2 = -1 x VDDB
+* 3 = -2 x VDDB
+* The defaults are 4 and 2 yielding 0x24
+*/
+ u8 bt3ctr[NT35510_P1_BT3CTR_LEN];
/**
* @vgh: setting for VGH ranging from 0x00 = 7.0V to 0x0B = 18.0V
* in 1V steps, the default is 0x08 which means 15V
@@ -277,6 +318,19 @@ struct nt35510_config {
* same layout of bytes as @vgp.
*/
u8 vgn[NT35510_P1_VGN_LEN];
+ /**
+* @vcmoff: setting the DC VCOM offset voltage
+* The first byte contains bit 8 of VCM in bit 0 and VCMOFFSEL in bit 4.
+* The second byte contains bits 0..7 of VCM.
+* VCMOFFSEL the common voltage offset mode.
+* VCMOFFSEL 0x00 = VCOM .. 0x01 Gamma.
+* The default is 0x00.
+* VCM the VCOM output voltage (VCMOFFSEL = 0) or the internal register
+* offset for gamma voltage (VCMOFFSEL = 1).
+* VCM 0x00 = 0V/0 .. 0x118 = 3.5V/280 in steps of 12.5mV/1step
+* The default is 0x00 = 0V/0.
+*/
+ u8 vcmoff[NT35510_P1_VCMOFF_LEN];
/**
* @dopctr: setting optional control for display
* ERR bits 0..1 in the first byte is the ERR pin output signal setting.
@@ -441,6 +495,43 @@ struct nt35510_config {
* @gamma_corr_neg_b: Blue gamma correction parameters, negative
*/
u8 gamma_corr_neg_b[NT35510_P1_GAMMA_LEN];
+ /**
+* @wrdisbv: write display brightness
+* 0x00 value means the lowest brightness and 0xff value means
+* the highes
Re: [PATCH v2 5/8] dt-bindings: nt35510: add compatible for FRIDA FRD400B25025-A-CTK
On Mon, Jan 1, 2024 at 5:16 PM Dario Binacchi wrote: > The patch adds the FRIDA FRD400B25025-A-CTK panel, which belongs to the > Novatek NT35510-based panel family. > > Signed-off-by: Dario Binacchi Reviewed-by: Linus Walleij Yours, Linus Walleij
[PATCH 0/2] Fix panel polarity mixup in S6D7AA0 panel driver and Galaxy Tab 3 8.0 DTSI
Two small one-line patches to address a mixup in the Samsung S6D7AA0 panel driver and the Samsung Galaxy Tab 3 8.0 board it was initially added for. Signed-off-by: Artur Weber --- Artur Weber (2): ARM: dts: exynos4212-tab3: add samsung,invert-vclk flag to fimd drm/panel: samsung-s6d7aa0: drop DRM_BUS_FLAG_DE_HIGH for lsl080al02 arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi | 1 + drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) --- base-commit: 610a9b8f49fbcf1100716370d3b5f6f884a2835a change-id: 20240101-tab3-display-fixes-6516f0b6a1a1 Best regards, -- Artur Weber
[PATCH 1/2] ARM: dts: exynos4212-tab3: add samsung,invert-vclk flag to fimd
After more investigation, I've found that it's not the panel driver
config that needs to be modified to invert the data polarity, but
the FIMD config.
Add the missing invert-vclk option that is required to get the display
to work correctly.
Signed-off-by: Artur Weber
---
arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi
b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi
index d7954ff466b4..e5254e32aa8f 100644
--- a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi
+++ b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi
@@ -434,6 +434,7 @@ &exynos_usbphy {
};
&fimd {
+ samsung,invert-vclk;
status = "okay";
};
--
2.43.0
[PATCH 2/2] drm/panel: samsung-s6d7aa0: drop DRM_BUS_FLAG_DE_HIGH for lsl080al02
It turns out that I had misconfigured the device I was using the panel
with; the bus data polarity is not high for this panel, I had to change
the config on the display controller's side.
Fix the panel config to properly reflect its accurate settings.
Signed-off-by: Artur Weber
---
drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c
b/drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c
index ea5a85779382..f23d8832a1ad 100644
--- a/drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c
+++ b/drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c
@@ -309,7 +309,7 @@ static const struct s6d7aa0_panel_desc
s6d7aa0_lsl080al02_desc = {
.off_func = s6d7aa0_lsl080al02_off,
.drm_mode = &s6d7aa0_lsl080al02_mode,
.mode_flags = MIPI_DSI_MODE_VSYNC_FLUSH | MIPI_DSI_MODE_VIDEO_NO_HFP,
- .bus_flags = DRM_BUS_FLAG_DE_HIGH,
+ .bus_flags = 0,
.has_backlight = false,
.use_passwd3 = false,
--
2.43.0
linux-next: manual merge of the drm tree with the mm tree
Hi all,
Today's linux-next merge of the drm tree got a conflict in:
drivers/accel/qaic/qaic_data.c
between commit:
78f5d33f3dd4 ("mm, treewide: rename MAX_ORDER to MAX_PAGE_ORDER")
from the mm tree and commit:
47fbee5f27ed ("accel/qaic: Update MAX_ORDER use to be inclusive")
from the drm tree.
I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc drivers/accel/qaic/qaic_data.c
index 24e886f857d5,cf2898eda7ae..
--- a/drivers/accel/qaic/qaic_data.c
+++ b/drivers/accel/qaic/qaic_data.c
@@@ -451,7 -452,7 +452,7 @@@ static int create_sgt(struct qaic_devic
* later
*/
buf_extra = (PAGE_SIZE - size % PAGE_SIZE) % PAGE_SIZE;
- max_order = min(MAX_PAGE_ORDER - 1, get_order(size));
- max_order = min(MAX_ORDER, get_order(size));
++ max_order = min(MAX_PAGE_ORDER, get_order(size));
} else {
/* allocate a single page for book keeping */
nr_pages = 1;
pgpeuQxxZpI4w.pgp
Description: OpenPGP digital signature
linux-next: build warning after merge of the drm tree
Hi all,
After merging the drm tree, today's linux-next build (x86_64 allmodconfig)
produced this warning:
In file included from include/drm/drm_mm.h:51,
from drivers/gpu/drm/xe/xe_bo_types.h:11,
from drivers/gpu/drm/xe/xe_bo.h:11,
from
drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object.h:11,
from drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h:15,
from drivers/gpu/drm/i915/display/intel_display_power.c:8:
drivers/gpu/drm/i915/display/intel_display_power.c: In function
'print_async_put_domains_state':
drivers/gpu/drm/i915/display/intel_display_power.c:408:29: warning: format
'%lu' expects argument of type 'long unsigned int', but argument 5 has type
'int' [-Wformat=]
408 | drm_dbg(&i915->drm, "async_put_wakeref %lu\n",
| ^
409 | power_domains->async_put_wakeref);
|
| |
| int
include/drm/drm_print.h:410:39: note: in definition of macro 'drm_dev_dbg'
410 | __drm_dev_dbg(NULL, dev, cat, fmt, ##__VA_ARGS__)
| ^~~
include/drm/drm_print.h:510:33: note: in expansion of macro 'drm_dbg_driver'
510 | #define drm_dbg(drm, fmt, ...) drm_dbg_driver(drm, fmt, ##__VA_ARGS__)
| ^~
drivers/gpu/drm/i915/display/intel_display_power.c:408:9: note: in expansion of
macro 'drm_dbg'
408 | drm_dbg(&i915->drm, "async_put_wakeref %lu\n",
| ^~~
drivers/gpu/drm/i915/display/intel_display_power.c:408:50: note: format string
is defined here
408 | drm_dbg(&i915->drm, "async_put_wakeref %lu\n",
|~~^
| |
| long unsigned int
|%u
Introduced by commit
b49e894c3fd8 ("drm/i915: Replace custom intel runtime_pm tracker with
ref_tracker library")
This would be an error except that I am building with CONFIG_WERROR=n
--
Cheers,
Stephen Rothwell
pgp09KK2fauUz.pgp
Description: OpenPGP digital signature
Re: [PATCH v4 05/17] drm/mediatek: Set DRM mode configs accordingly
Re: [PATCH v4 06/17] drm/mediatek: Support alpha blending in OVL
Re: [PATCH v4 07/17] drm/mediatek: Support alpha blending in Mixer
Re: [PATCH v4 08/17] drm/mediatek: Support alpha blending in display driver
Re: [PATCH v4 09/17] drm/mediatek: Support CSC in OVL
Re: [PATCH v4 10/17] drm/mediatek: Support more color formats in OVL
Flaky tests for vkms
Hi Maintainers, The patch introducing vkms driver testing in drm-ci has been submitted upstream (https://patchwork.kernel.org/project/dri-devel/patch/20230922171237.550762-3-helen.ko...@collabora.com/) We will send an update to this patch with new test results from the latest drm-misc-next. There are some flaky tests reported for vkms with the latest tests. # Board Name: vkms # Failure Rate: 50 # IGT Version: 1.28-gd2af13d9f # Linux Version: 6.7.0-rc3 Pipeline url: https://gitlab.freedesktop.org/vigneshraman/linux/-/jobs/53081973 # Reported by deqp-runner kms_cursor_legacy@cursorA-vs-flipA-legacy kms_cursor_legacy@cursorA-vs-flipA-varying-size Will add these tests in drivers/gpu/drm/ci/xfails/vkms-none-flakes.txt (https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/Documentation/gpu/automated_testing.rst#n70) Please could you have a look at these test results and let us know if you need more information. Thank you. Regards, Vignesh
