Re: [PATCH] drm/sprd: remove redundant error logging
On Sun, 11 Dec 2022 at 21:55, Deepak R Varma wrote:
>
> A call to platform_get_irq() already prints an error on failure within
> its own implementation. So printing another error based on its return
> value in the caller is redundant and should be removed. The clean up
> also makes if condition block braces unnecessary. Remove that as well.
>
> Issue identified using platform_get_irq.cocci coccicheck script.
>
> Signed-off-by: Deepak R Varma
> ---
> drivers/gpu/drm/sprd/sprd_dpu.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/sprd/sprd_dpu.c b/drivers/gpu/drm/sprd/sprd_dpu.c
> index 88f4259680f1..db0bcea1d9f4 100644
> --- a/drivers/gpu/drm/sprd/sprd_dpu.c
> +++ b/drivers/gpu/drm/sprd/sprd_dpu.c
> @@ -803,10 +803,8 @@ static int sprd_dpu_context_init(struct sprd_dpu *dpu,
> }
>
> ctx->irq = platform_get_irq(pdev, 0);
> - if (ctx->irq < 0) {
> - dev_err(dev, "failed to get dpu irq\n");
> + if (ctx->irq < 0)
Thanks for the patch, it makes sense to me, so
Acked-by: Chunyan Zhang
> return ctx->irq;
> - }
>
> /* disable and clear interrupts before register dpu IRQ. */
> writel(0x00, ctx->base + REG_DPU_INT_EN);
> --
> 2.34.1
>
>
>
Re: [PATCH v2 2/2] dt-bindings: leds: backlight: Add Kinetic KTZ8866 backlight
On 21/12/2022 16:31, Jianhua Lu wrote: > Add Kinetic KTZ8866 backlight binding documentation. > > Signed-off-by: Jianhua Lu > --- Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof
[PATCH 2/4] fixup! drm/i915/gt: Remove platform comments from workarounds
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 2 +-
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c| 2 +-
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++
5 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index ef45dfc6adae..25a982925cf2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1614,7 +1614,7 @@ static void __gpm_wait_for_fw_complete(struct intel_gt
*gt, u32 fw_mask)
}
/*
- * Wa_22011802037
+ * Wa_22011802037 - In addition to stopping the cs, we need to wait for any
* pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
* pending status is indicated by bits[13:9] (masked by bits[29:25]) in the
* MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 9f232c743ee7..1510255f6a50 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2989,7 +2989,7 @@ static void execlists_reset_prepare(struct
intel_engine_cs *engine)
intel_engine_stop_cs(engine);
/*
-* Wa_22011802037
+* Wa_22011802037 - In addition to stopping the cs, we need
* to wait for any pending mi force wakeups
*/
if (IS_GRAPHICS_VER(engine->i915, 11, 12))
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index f59d38a5e2a0..b3ea634958d1 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -613,7 +613,7 @@ static int gen8_reset_engines(struct intel_gt *gt,
}
/*
-* Wa_22011100796
+* Wa_22011100796 - whenever Full soft reset is required,
* reset all individual engines firstly, and then do a full soft reset.
*
* This is best effort, so ignore any error from the initial reset.
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 704b50467ce3..5414df579341 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -317,9 +317,9 @@ static void reset_prepare(struct intel_engine_cs *engine)
* Thus assume it is best to stop engines on all gens
* where we have a gpu reset.
*
-* WaKBLVECSSemaphoreWaitPoll
+* WaKBLVECSSemaphoreWaitPoll - on ALL_ENGINES
*
-* WaMediaResetMainRingCleanup
+* WaMediaResetMainRingCleanup - presumably
* WaClearRingBufHeadRegAtInit
*
* FIXME: Wa for more modern gens needs to be validated
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index edfa7d98a409..b01af1ed2382 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1425,7 +1425,7 @@ tgl_gt_workarounds_init(struct intel_gt *gt, struct
i915_wa_list *wal)
SUBSLICE_UNIT_LEVEL_CLKGATE2,
CPSSUNIT_CLKGATE_DIS);
- /* Wa_1607087056 */
+ /* Wa_1607087056 - also know as BUG:1409180338 */
if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
wa_write_or(wal,
GEN11_SLICE_UNIT_LEVEL_CLKGATE,
@@ -2318,7 +2318,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
}
- /* Wa_1308578152 */
+ /* Wa_1308578152 - when first gslice is fused off */
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) &&
needs_wa_1308578152(engine)) {
wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON,
@@ -2417,8 +2417,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
/*
-* Wa_1606679103
-* (see also Wa_1606682166
+* Wa_1606679103 - see also Wa_1606682166
*/
wa_write_or(wal,
GEN7_SARCHKMD,
--
2.39.0
[PATCH 1/4] drm/i915/gt: Remove platform comments from workarounds
The comments are redundant to the checks being done to apply the
workarounds and very often get outdated as workarounds need to be
extended to new platforms or steppings. Remove them altogether with
the following matches (platforms extracted from intel_workarounds.c):
find drivers/gpu/drm/i915/gt/ -name '*.c' | xargs sed -i -E \
's/(Wa.*):(bdw|chv|bxt|glk|skl|kbl|cfl|cfl|whl|cml|aml|chv|cl|bw|ctg|elk|ilk|snb|dg|pvc|g4x|ilk|gen|glk|kbl|cml|glk|kbl|cml|hsw|icl|ehl|ivb|hsw|ivb|vlv|kbl|pvc|rkl|dg|adl|skl|skl|bxt|blk|cfl|cnl|glk|snb|tgl|vlv|xehpsdv).*/\1/'
find drivers/gpu/drm/i915/gt/ -name '*.c' | xargs sed -i -E \
's/(Wa.*):(bdw|chv|bxt|glk|skl|kbl|cfl|cfl|whl|cml|aml|chv|cl|bw|ctg|elk|ilk|snb|dg|pvc|g4x|ilk|gen|glk|kbl|cml|glk|kbl|cml|hsw|icl|ehl|ivb|hsw|ivb|vlv|kbl|pvc|rkl|dg|adl|skl|skl|bxt|blk|cfl|cnl|glk|snb|tgl|vlv|xehpsdv).*\*\//\1
Same things was executed in the gem directory, omitted here for brevity.
There were a few false positives that included the workaround
description. Those were manually patched.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 2 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 12 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
.../drm/i915/gt/intel_execlists_submission.c | 6 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 20 +-
drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 4 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 4 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 10 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 440 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 16 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
16 files changed, 266 insertions(+), 266 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index bc9521078807..a2a49cc25ca3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -46,7 +46,7 @@ int i915_gem_stolen_insert_node_in_range(struct
drm_i915_private *i915,
if (!drm_mm_initialized(&i915->mm.stolen))
return -ENODEV;
- /* WaSkipStolenMemoryFirstPage:bdw+ */
+ /* WaSkipStolenMemoryFirstPage */
if (GRAPHICS_VER(i915) >= 8 && start < 4096)
start = 4096;
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index e1c76e5bfa82..d7a40ed66d9e 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -42,7 +42,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
if (GRAPHICS_VER(rq->engine->i915) == 9)
vf_flush_wa = true;
- /* WaForGAMHang:kbl */
+ /* WaForGAMHang */
if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
dc_flush_wa = true;
}
@@ -189,7 +189,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
flags |= PIPE_CONTROL_FLUSH_L3;
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
- /* Wa_1409600907:tgl,adl-p */
+ /* Wa_1409600907 */
flags |= PIPE_CONTROL_DEPTH_STALL;
flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
flags |= PIPE_CONTROL_FLUSH_ENABLE;
@@ -462,7 +462,7 @@ int gen8_emit_bb_start_noarb(struct i915_request *rq,
return PTR_ERR(cs);
/*
-* WaDisableCtxRestoreArbitration:bdw,chv
+* WaDisableCtxRestoreArbitration
*
* We don't need to perform MI_ARB_ENABLE as often as we do (in
* particular all the gen that do not need the w/a at all!), if we
@@ -657,7 +657,7 @@ static u32 *gen12_emit_preempt_busywait(struct i915_request
*rq, u32 *cs)
return cs;
}
-/* Wa_14014475959:dg2 */
+/* Wa_14014475959 */
#define CCS_SEMAPHORE_PPHWSP_OFFSET0x540
static u32 ccs_semaphore_offset(struct i915_request *rq)
{
@@ -665,7 +665,7 @@ static u32 ccs_semaphore_offset(struct i915_request *rq)
(LRC_PPHWSP_PN * PAGE_SIZE) + CCS_SEMAPHORE_PPHWSP_OFFSET;
}
-/* Wa_14014475959:dg2 */
+/* Wa_14014475959 */
static u32 *ccs_emit_wa_busywait(struct i915_request *rq, u32 *cs)
{
int i;
@@ -704,7 +704,7 @@ gen12_emit_fini_breadcrumb_tail(struct i915_request *rq,
u32 *cs)
!intel_uc_uses_guc_submission(&rq->engine->gt->uc))
cs = gen12_emit_preempt_busywait(rq, cs);
- /* Wa_14014475959:dg2 */
+ /* Wa_14014475959 */
if
[PATCH 0/4] Remove platform acronyms and stepping from comments
Cleanup gt and display wrt the comments for the workarounds. Rationale is in the patch itself. I'm providing the patches, as generated by the commands in the commit message, with a fixup on top to remove false positives. The intention for when this is ready to be applied is to squash the fixup: it's only provided for ease of review and rebase. Lucas De Marchi (4): drm/i915/gt: Remove platform comments from workarounds fixup! drm/i915/gt: Remove platform comments from workarounds drm/i915: Remove platform comments from workarounds fixup! drm/i915: Remove platform comments from workarounds drivers/gpu/drm/i915/display/g4x_hdmi.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/icl_dsi.c| 10 +- .../gpu/drm/i915/display/intel_atomic_plane.c | 2 +- drivers/gpu/drm/i915/display/intel_cdclk.c| 2 +- drivers/gpu/drm/i915/display/intel_cursor.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 20 +- .../drm/i915/display/intel_display_power.c| 8 +- .../i915/display/intel_display_power_well.c | 2 +- drivers/gpu/drm/i915/display/intel_dmc.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- drivers/gpu/drm/i915/display/intel_fbc.c | 10 +- drivers/gpu/drm/i915/display/intel_fdi.c | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- .../drm/i915/display/intel_modeset_setup.c| 4 +- .../gpu/drm/i915/display/intel_pch_refclk.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 24 +- drivers/gpu/drm/i915/display/intel_sprite.c | 2 +- drivers/gpu/drm/i915/display/intel_vga.c | 2 +- .../drm/i915/display/skl_universal_plane.c| 6 +- drivers/gpu/drm/i915/display/skl_watermark.c | 8 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 2 +- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 12 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- .../drm/i915/gt/intel_execlists_submission.c | 6 +- drivers/gpu/drm/i915/gt/intel_gt.c| 2 +- drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 20 +- drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 4 +- drivers/gpu/drm/i915/gt/intel_reset.c | 4 +- .../gpu/drm/i915/gt/intel_ring_submission.c | 10 +- drivers/gpu/drm/i915/gt/intel_rps.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 439 +- drivers/gpu/drm/i915/gt/uc/intel_guc.c| 16 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +- drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +- drivers/gpu/drm/i915/i915_perf.c | 10 +- drivers/gpu/drm/i915/intel_pm.c | 132 +++--- drivers/gpu/drm/i915/intel_uncore.c | 8 +- 42 files changed, 400 insertions(+), 401 deletions(-) -- 2.39.0
[PATCH 4/4] fixup! drm/i915: Remove platform comments from workarounds
---
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 4 ++--
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 328c886309f3..543881838def 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1636,7 +1636,7 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state
*crtc_state,
if (full_update) {
/*
-* Not applying Wa_14014971508
+* Not applying Wa_14014971508 as we do not support the
* feature that requires this workaround.
*/
val |= man_trk_ctl_single_full_frame_bit_get(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 49f7e1fbd96c..9e6686b8c8f0 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1590,7 +1590,7 @@ static void i915_oa_stream_destroy(struct
i915_perf_stream *stream)
free_oa_buffer(stream);
/*
-* Wa_16011777198
+* Wa_16011777198 - Unset the override of GUCRC mode to enable rc6.
*/
if (intel_uc_uses_guc_rc(>->uc) &&
(IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
@@ -3293,7 +3293,7 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
intel_uncore_forcewake_get(stream->uncore, FORCEWAKE_ALL);
/*
-* Wa_16011777198
+* Wa_16011777198 - GuC resets render as part of the Wa. This causes
* OA to lose the configuration state. Prevent this by overriding GUCRC
* mode.
*/
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 82a59738ca4a..492973085297 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4578,7 +4578,7 @@ static void ivb_init_clock_gating(struct drm_i915_private
*dev_priv)
/*
* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
-* This implements the WaDisableRCZUnitClockGating
+* This implements the WaDisableRCZUnitClockGating workaround.
*/
intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
@@ -4615,7 +4615,7 @@ static void vlv_init_clock_gating(struct drm_i915_private
*dev_priv)
/*
* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
-* This implements the WaDisableRCZUnitClockGating
+* This implements the WaDisableRCZUnitClockGating workaround.
*/
intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index e56dbb20f2fe..182791a9cabb 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1887,7 +1887,7 @@ static const struct intel_forcewake_range
__xelpmp_fw_ranges[] = {
static void
ilk_dummy_write(struct intel_uncore *uncore)
{
- /* WaIssueDummyWriteToWakeupFromRC6
+ /* WaIssueDummyWriteToWakeupFromRC6 - Issue a dummy write to wake up
* the chip from rc6 before touching it for real. MI_MODE is masked,
* hence harmless to write 0 into. */
__raw_uncore_write32(uncore, RING_MI_MODE(RENDER_RING_BASE), 0);
--
2.39.0
[PATCH 3/4] drm/i915: Remove platform comments from workarounds
The comments are redundant to the checks being done to apply the
workarounds and very often get outdated as workarounds need to be
extended to new platforms or steppings. Remove them altogether with
the following matches (platforms extracted from intel_workarounds.c):
find drivers/gpu/drm/i915/ -name '*.c' | xargs sed -i -E \
's/(Wa.*):(bdw|chv|bxt|glk|skl|kbl|cfl|cfl|whl|cml|aml|chv|cl|bw|ctg|elk|ilk|snb|dg|pvc|g4x|ilk|gen|glk|kbl|cml|glk|kbl|cml|hsw|icl|ehl|ivb|hsw|ivb|vlv|kbl|pvc|rkl|dg|adl|skl|skl|bxt|blk|cfl|cnl|glk|snb|tgl|vlv|xehpsdv).*/\1/'
find drivers/gpu/drm/i915/ -name '*.c' | xargs sed -i -E \
's/(Wa.*):(bdw|chv|bxt|glk|skl|kbl|cfl|cfl|whl|cml|aml|chv|cl|bw|ctg|elk|ilk|snb|dg|pvc|g4x|ilk|gen|glk|kbl|cml|glk|kbl|cml|hsw|icl|ehl|ivb|hsw|ivb|vlv|kbl|pvc|rkl|dg|adl|skl|skl|bxt|blk|cfl|cnl|glk|snb|tgl|vlv|xehpsdv).*\*\//\1
There were a few false positives that included the workaround
description. Those were manually patched.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/g4x_hdmi.c | 2 +-
drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
drivers/gpu/drm/i915/display/icl_dsi.c| 10 +-
.../gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
drivers/gpu/drm/i915/display/intel_cdclk.c| 2 +-
drivers/gpu/drm/i915/display/intel_cursor.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 20 +--
.../drm/i915/display/intel_display_power.c| 8 +-
.../i915/display/intel_display_power_well.c | 2 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 10 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
.../drm/i915/display/intel_modeset_setup.c| 4 +-
.../gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 24 ++--
drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
drivers/gpu/drm/i915/display/intel_vga.c | 2 +-
.../drm/i915/display/skl_universal_plane.c| 6 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 8 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 10 +-
drivers/gpu/drm/i915/intel_pm.c | 132 +-
drivers/gpu/drm/i915/intel_uncore.c | 8 +-
26 files changed, 135 insertions(+), 135 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c
b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index c3580d96765c..7e6e51b496aa 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -261,7 +261,7 @@ static void cpt_enable_hdmi(struct intel_atomic_state
*state,
temp |= HDMI_AUDIO_ENABLE;
/*
-* WaEnableHDMI8bpcBefore12bpc:snb,ivb
+* WaEnableHDMI8bpcBefore12bpc
*
* The procedure for 12bpc is as follows:
* 1. disable HDMI clock gating
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index ecaeb7dc196b..dc26f2716dcb 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -807,7 +807,7 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
num_formats = ARRAY_SIZE(vlv_primary_formats);
} else if (DISPLAY_VER(dev_priv) >= 4) {
/*
-* WaFP16GammaEnabling:ivb
+* WaFP16GammaEnabling
* "Workaround : When using the 64-bit format, the plane
* output on each color channel has one quarter amplitude.
* It can be brought up to full amplitude by using pipe
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index ae14c794c4bc..eff1c46d6ab2 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1241,7 +1241,7 @@ static void gen11_dsi_pre_enable(struct
intel_atomic_state *state,
}
/*
- * Wa_1409054076:icl,jsl,ehl
+ * Wa_1409054076
* When pipe A is disabled and MIPI DSI is enabled on pipe B,
* the AMT KVMR feature will incorrectly see pipe A as enabled.
* Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave
@@ -1259,7 +1259,7 @@ static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder
*encoder,
}
/*
- * Wa_16012360555:adl-p
+ * Wa_16012360555
* SW will have to program the "LP to HS Wakeup Guardband"
* to account for the repeaters on the HS Request/Ready
* PPI signaling between the Display engine and the DPHY.
@@ -1288,10 +1288,10 @@ static void gen11_dsi_enable(struct intel_atomic_state
*state,
drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
- /* Wa_1409054076:icl,jsl,ehl */
+ /* Wa_1409054076
Re: [PATCH v2 00/21] Add Tegra20 parallel video input capture
Hello Dmitry, thanks for your review. On Tue, 20 Dec 2022 23:21:49 +0300 Dmitry Osipenko wrote: > 28.11.2022 18:23, Luca Ceresoli пишет: > > Tegra20 and other Tegra SoCs have a video input (VI) peripheral that can > > receive from either MIPI CSI-2 or parallel video (called respectively "CSI" > > and "VIP" in the documentation). The kernel currently has a staging driver > > for Tegra210 CSI capture. This patch set adds support for Tegra20 VIP > > capture. > > > > Unfortunately I had no real documentation available to base this work on. > > I only had a working downstream 3.1 kernel, so I started with the driver > > found there and heavily reworked it to fit into the mainline tegra-video > > driver structure. The existing code appears written with the intent of > > being modular and allow adding new input mechanisms and new SoCs while > > keeping a unique VI core module. However its modularity and extensibility > > was not enough to add Tegra20 VIP support, so I added some hooks to turn > > hard-coded behaviour into per-SoC or per-bus customizable code. There are > > also a fix, some generic cleanups and DT bindings. > > > > Quick tour of the patches: > > > > * Device tree bindings and minor DTS improvements > > > >01. dt-bindings: display: tegra: add Tegra20 VIP > >02. dt-bindings: display: tegra: vi: add 'vip' property and example > > This series adds the new DT node, but there are no board DTs in upstream > that will use VIP? Will we see the board patches? I'm afraid I have no such plan. I don't have any public hardware with Tegra20, with or without a parallel sensor. I have a custom board. > In any case, given that you're likely the only one here who has access > to hardware with VIP, Likely indeed. > you should promote yourself to the tegra-video > driver maintainers and confirm that you will be able to maintain and > test this code for years to come. I can definitely add myself as a maintainer of this driver and join the maintenance effort, I'm adding that in v3. I also have a board that I can permanently use for testing. -- Luca Ceresoli, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
Re: [PATCH v2 21/21] staging: media: tegra-video: add tegra20 variant
Hello Dmitry,
On Wed, 21 Dec 2022 00:40:20 +0300
Dmitry Osipenko wrote:
> 28.11.2022 18:23, Luca Ceresoli пишет:
> > +static int tegra20_channel_capture_frame(struct tegra_vi_channel *chan,
> > +struct tegra_channel_buffer *buf)
> > +{
> > + u32 value;
> > + int err;
> > +
> > + chan->next_out_sp_idx++;
> > +
> > + tegra20_channel_vi_buffer_setup(chan, buf);
> > +
> > + tegra20_vi_write(chan, TEGRA_VI_CAMERA_CONTROL,
> > VI_CAMERA_CONTROL_VIP_ENABLE);
> > +
> > + /* Wait for syncpt counter to reach frame start event threshold */
> > + err = host1x_syncpt_wait(chan->out_sp, chan->next_out_sp_idx,
> > +TEGRA_VI_SYNCPT_WAIT_TIMEOUT, &value);
>
> You're not using the "value" variable, it should be NULL.
Ah, sure, good catch.
> The "chan->out_sp" looks redundant, it duplicates the chan->mw_ack_sp.
I agree it is redundant and can be improved.
> AFAICS from the doc, T20 has two VI channels, and thus, two mw_ack_sp,
> like T210.
I'm confused by this. In the current driver, each VI channel has an
array of 2 mw_ack_sp, the second of which is only used the ganged
CSI ports. I have no docs mentioning ganged ports so I don't know
exactly how they work and whether T20 might need more than 1 syncpt per
channel or not for CSI. Definitely when using VIP only one such syncpt
per each VI (or per each VIP, as per your reply to patch 1) is needed.
Bottom line: I think I can simply remove the out_sp and in the VIP code
always use chan->mw_ack_sp[0], and document that it's what is called OUT
in VIP terms.
Does this plan seem good?
--
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Re: [PATCH v2 01/21] dt-bindings: display: tegra: add Tegra20 VIP
Hello Dmitry, On Tue, 20 Dec 2022 23:13:05 +0300 Dmitry Osipenko wrote: > 02.12.2022 11:11, Luca Ceresoli пишет: ... > >>> --- /dev/null > >>> +++ > >>> b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml > >>> @@ -0,0 +1,63 @@ > >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > >>> +%YAML 1.2 > >>> +--- > >>> +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vip.yaml# > >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >>> + > >>> +title: NVIDIA Tegra VIP (parallel video capture) controller > >>> + > >>> +maintainers: > >>> + - Luca Ceresoli > >>> + > >>> +properties: > >>> + compatible: > >>> +enum: > >>> + - nvidia,tegra20-vip > >>> + > >>> + "#address-cells": > >>> +const: 1 > >>> + > >>> + "#size-cells": > >>> +const: 0 > >>> + > >>> + channel@0: > >> Kind of odd there is only 1 channel with a unit-address. Are more > >> channels coming? Please make the binding as complete as possible even if > >> no driver support yet. > > This was discussed in v1 with Krzysztof and the outcome was that it's > > OK because it's likely that other SoCs have more, but the documentation > > is not public so I cannot add examples. > > > > Full discussion (pretty short indeed): > > > > https://lore.kernel.org/linux-devicetree/5292cc1b-c951-c5c5-b2ef-c154baf6d...@linaro.org/ > > > > Do you agree that the unit-address should be kept? > > It's doubtful that there is a SoC having a VIP with multiple channels. > I'd expect it to be multiple VIPs rather than channels. There are NVIDIA > people to confirm that. > > The "channel" itself looks redundant to me, i.e. the reg and ports > should be moved to the vip node. OK, will do in v3 unless there are different opinions. -- Luca Ceresoli, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
Re: [Intel-gfx] [PATCH] drm/i915/gt: Reset twice
On 12/15/22 10:07 PM, Rodrigo Vivi wrote:
On Wed, Dec 14, 2022 at 11:37:19PM +0100, Andi Shyti wrote:
Hi Rodrigo,
On Tue, Dec 13, 2022 at 01:18:48PM +, Vivi, Rodrigo wrote:
On Tue, 2022-12-13 at 00:08 +0100, Andi Shyti wrote:
Hi Rodrigo,
On Mon, Dec 12, 2022 at 11:55:10AM -0500, Rodrigo Vivi wrote:
On Mon, Dec 12, 2022 at 05:13:38PM +0100, Andi Shyti wrote:
From: Chris Wilson
After applying an engine reset, on some platforms like
Jasperlake, we
occasionally detect that the engine state is not cleared until
shortly
after the resume. As we try to resume the engine with volatile
internal
state, the first request fails with a spurious CS event (it looks
like
it reports a lite-restore to the hung context, instead of the
expected
idle->active context switch).
Signed-off-by: Chris Wilson
There's a typo in the signature email I'm afraid...
oh yes, I forgot the 'C' :)
you forgot?
who signed it off?
Chris, but as I was copy/pasting SoB's I might have
unintentionally removed the 'c'.
Other than that, have we checked the possibility of using the
driver-initiated-flr bit
instead of this second loop? That should be the right way to
guarantee everything is
cleared on gen11+...
maybe I am misinterpreting it, but is FLR the same as resetting
hardware domains individually?
No, it is bigger than that... almost the PCI FLR with some exceptions:
https://lists.freedesktop.org/archives/intel-gfx/2022-December/313956.html
yes, exactly... I would use FLR feedback if I was performing an
FLR reset. But here I'm not doing that, here I'm simply gating
off some power domains. It happens that those power domains turn
on and off engines making them reset.
is this issue only seeing when this reset is called from the
sanitize functions at probe and resumes?
Or from any kind of gt reset?
I don't remember seeing any reference link to the bug in the patch,
hence I'm assuming this is happening in any kind of gt reset that
ends up in this function.
FLR doesn't have anything to do here, also because if you want to
reset a single engine you go through this function, instead of
resetting the whole GPU with whatever is annexed.
yeap. That might be to extreme depending on the case. But all that
I asked was if we were considering this option since this is the
recommended way of reseting our engines nowadays.
This patch is not fixing the "reset" concept of i915, but it's
fixing a missing feedback that happens in one single platform
when trying to gate on/off a domain.
But it is changing the reset concept and timeouts for all the reset
cases in all the platforms.
Maybe I am completely off track, but I don't see connection with
FLR here.
The point is that if a reset is needed, for any reason,
the recommended way for Jasperlake, and any other newer platforms,
is to use the FLR rather than the engine reset. But we are using
the engine reset, and now twice, rather then attempt the recommended
way.
(besides FLR might not be present in all the platforms)
This issue is also not present in all the platforms and you are still
increasing the loops and delay for all the platforms.
Thanks a lot for your inputs,
have we looked to the Jasperlake workarounds to see if we are missing
anything there that could help us in this case instead of this extreme
approach of randomly increasing timeouts and attempts for all the
platforms?
Hi, Rodrigo
JSL_WA (Bspec: 33451) doesn't seem to have a WA similar to this issue.
(Please correct me if I can't find it.)
Andi
How am I supposed to use driver_initiated_flr() in this context?
Some drivers are not even using this gt reset anymore and going
directly with the driver-initiated FLR in case that guc reset failed.
I believe we can still keep the gt reset in our case as we currently
have, but instead of keep retrying it until it succeeds we probably
should go to the next level and do the driver initiated FLR when the GT
reset failed.
Thanks,
Andi
Cc: sta...@vger.kernel.org
Cc: Mika Kuoppala
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_reset.c | 34
++-
1 file changed, 28 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index ffde89c5835a4..88dfc0c5316ff 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -268,6 +268,7 @@ static int ilk_do_reset(struct intel_gt *gt,
intel_engine_mask_t engine_mask,
static int gen6_hw_domain_reset(struct intel_gt *gt, u32
hw_domain_mask)
{
struct intel_uncore *uncore = gt->uncore;
+ int loops = 2;
int err;
/*
@@ -275,18 +276,39 @@ static int gen6_hw_domain_reset(struct
intel_gt *gt, u32 hw_domain_mask)
* for fifo space for the write or forcewake the chip for
* the read
*/
- intel_uncore_write_fw(uncore, GEN6_GDRST,
hw_domain_mask);
+ do {
+ intel_uncore_write_fw(uncor
Re: [PATCH v2 RESEND 0/4] Add JDI LPM102A188A display panel support
On Mon, Nov 28, 2022 at 04:28:48PM +, Diogo Ivo wrote: > Hello, > > These patches add support for the JDI LPM102A188A display panel, > found in the Google Pixel C. Hello, Gentle ping on this series. Thank you, Diogo Ivo
Re: [PATCH 09/10] drm/drm_blend: Remove usage of deprecated DRM_DEBUG_ATOMIC
This patch is: Reviewed-by: Simon Ser
Re: [PATCH] treewide: Convert del_timer*() to timer_shutdown*()
On Tue, 2022-12-20 at 13:45 -0500, Steven Rostedt wrote: > [ > Linus, > > I ran the script against your latest master branch: > commit b6bb9676f2165d518b35ba3bea5f1fcfc0d969bf > > As the timer_shutdown*() code is now in your tree, I figured > we can start doing the conversions. At least add the trivial ones > now as Thomas suggested that this gets applied at the end of the > merge window, to avoid conflicts with linux-next during the > development cycle. I can wait to Friday to run it again, and > resubmit. > > What is the best way to handle this? > ] > > From: "Steven Rostedt (Google)" > > Due to several bugs caused by timers being re-armed after they are > shutdown and just before they are freed, a new state of timers was added > called "shutdown". After a timer is set to this state, then it can no > longer be re-armed. > > The following script was run to find all the trivial locations where > del_timer() or del_timer_sync() is called in the same function that the > object holding the timer is freed. It also ignores any locations where the > timer->function is modified between the del_timer*() and the free(), as > that is not considered a "trivial" case. > > This was created by using a coccinelle script and the following commands: > > $ cat timer.cocci > @@ > expression ptr, slab; > identifier timer, rfield; > @@ > ( > - del_timer(&ptr->timer); > + timer_shutdown(&ptr->timer); > > > - del_timer_sync(&ptr->timer); > + timer_shutdown_sync(&ptr->timer); > ) > ... when strict > when != ptr->timer > ( > kfree_rcu(ptr, rfield); > > > kmem_cache_free(slab, ptr); > > > kfree(ptr); > ) > > $ spatch timer.cocci . > /tmp/t.patch > $ patch -p1 < /tmp/t.patch > > Link: https://lore.kernel.org/lkml/20221123201306.823305...@linutronix.de/ > > Signed-off-by: Steven Rostedt (Google) For the networking bits: > drivers/net/ethernet/intel/i40e/i40e_main.c | 6 +++--- > drivers/net/ethernet/marvell/sky2.c | 2 +- > drivers/net/ethernet/sun/sunvnet.c | 2 +- > drivers/net/usb/sierra_net.c | 2 +- > net/802/garp.c | 2 +- > net/802/mrp.c| 4 ++-- > net/bridge/br_multicast.c| 8 > net/bridge/br_multicast_eht.c| 4 ++-- > net/core/gen_estimator.c | 2 +- > net/ipv4/ipmr.c | 2 +- > net/ipv6/ip6mr.c | 2 +- > net/mac80211/mesh_pathtbl.c | 2 +- > net/netfilter/ipset/ip_set_list_set.c| 2 +- > net/netfilter/ipvs/ip_vs_lblc.c | 2 +- > net/netfilter/ipvs/ip_vs_lblcr.c | 2 +- > net/netfilter/xt_IDLETIMER.c | 4 ++-- > net/netfilter/xt_LED.c | 2 +- > net/sched/cls_flow.c | 2 +- > net/sunrpc/svc.c | 2 +- > net/tipc/discover.c | 2 +- > net/tipc/monitor.c | 2 +- Acked-by: Paolo Abeni
Re: [PATCH 1/4] drm/i915/gt: Remove platform comments from workarounds
On 22/12/2022 08:25, Lucas De Marchi wrote:
The comments are redundant to the checks being done to apply the
workarounds and very often get outdated as workarounds need to be
extended to new platforms or steppings. Remove them altogether with
the following matches (platforms extracted from intel_workarounds.c):
find drivers/gpu/drm/i915/gt/ -name '*.c' | xargs sed -i -E \
's/(Wa.*):(bdw|chv|bxt|glk|skl|kbl|cfl|cfl|whl|cml|aml|chv|cl|bw|ctg|elk|ilk|snb|dg|pvc|g4x|ilk|gen|glk|kbl|cml|glk|kbl|cml|hsw|icl|ehl|ivb|hsw|ivb|vlv|kbl|pvc|rkl|dg|adl|skl|skl|bxt|blk|cfl|cnl|glk|snb|tgl|vlv|xehpsdv).*/\1/'
find drivers/gpu/drm/i915/gt/ -name '*.c' | xargs sed -i -E \
's/(Wa.*):(bdw|chv|bxt|glk|skl|kbl|cfl|cfl|whl|cml|aml|chv|cl|bw|ctg|elk|ilk|snb|dg|pvc|g4x|ilk|gen|glk|kbl|cml|glk|kbl|cml|hsw|icl|ehl|ivb|hsw|ivb|vlv|kbl|pvc|rkl|dg|adl|skl|skl|bxt|blk|cfl|cnl|glk|snb|tgl|vlv|xehpsdv).*\*\//\1
Same things was executed in the gem directory, omitted here for brevity.
There were a few false positives that included the workaround
description. Those were manually patched.
sed -E 's/(Wa[a-zA-Z0-9_]+)[:,]([a-zA-Z0-9,-_\+\[]{2,})/\1/'
Maybe..
Matt recently said he has this worked planned, but more importantly - I
gather then that the WA lookup tool definitely does not output these
strings?
Regards,
Tvrtko
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 2 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 12 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
.../drm/i915/gt/intel_execlists_submission.c | 6 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 20 +-
drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 4 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 4 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 10 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 440 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 16 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
16 files changed, 266 insertions(+), 266 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index bc9521078807..a2a49cc25ca3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -46,7 +46,7 @@ int i915_gem_stolen_insert_node_in_range(struct
drm_i915_private *i915,
if (!drm_mm_initialized(&i915->mm.stolen))
return -ENODEV;
- /* WaSkipStolenMemoryFirstPage:bdw+ */
+ /* WaSkipStolenMemoryFirstPage */
if (GRAPHICS_VER(i915) >= 8 && start < 4096)
start = 4096;
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index e1c76e5bfa82..d7a40ed66d9e 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -42,7 +42,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
if (GRAPHICS_VER(rq->engine->i915) == 9)
vf_flush_wa = true;
- /* WaForGAMHang:kbl */
+ /* WaForGAMHang */
if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
dc_flush_wa = true;
}
@@ -189,7 +189,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
flags |= PIPE_CONTROL_FLUSH_L3;
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
- /* Wa_1409600907:tgl,adl-p */
+ /* Wa_1409600907 */
flags |= PIPE_CONTROL_DEPTH_STALL;
flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
flags |= PIPE_CONTROL_FLUSH_ENABLE;
@@ -462,7 +462,7 @@ int gen8_emit_bb_start_noarb(struct i915_request *rq,
return PTR_ERR(cs);
/*
-* WaDisableCtxRestoreArbitration:bdw,chv
+* WaDisableCtxRestoreArbitration
*
* We don't need to perform MI_ARB_ENABLE as often as we do (in
* particular all the gen that do not need the w/a at all!), if we
@@ -657,7 +657,7 @@ static u32 *gen12_emit_preempt_busywait(struct i915_request
*rq, u32 *cs)
return cs;
}
-/* Wa_14014475959:dg2 */
+/* Wa_14014475959 */
#define CCS_SEMAPHORE_PPHWSP_OFFSET 0x540
static u32 ccs_semaphore_offset(struct i915_request *rq)
{
@@ -665,7 +665,7 @@ static u32 ccs_semaphore_offset(struct i915_request *rq)
(LRC_PPHWSP_PN * PAGE_SIZE) + CCS_SEMAPHORE_PPHWSP_OFFSET;
}
-/* Wa_14014475959:dg2 */
+/* Wa_14014475959 */
static u32 *ccs_emit_wa_busywait(struct i915_request *rq, u32 *cs
Re: [PATCH v14 1/5] arm64: dts: qcom: add data-lanes and link-freuencies into dp_out endpoint
On 16/12/2022 20:11, Kuogee Hsieh wrote:
> Move data-lanes property from mdss_dp node to dp_out endpoint. Also
> add link-frequencies property into dp_out endpoint as well. The last
> frequency specified at link-frequencies will be the max link rate
> supported by DP.
>
> Changes in v5:
> -- revert changes at sc7180.dtsi and sc7280.dtsi
> -- add &dp_out to sc7180-trogdor.dtsi and sc7280-herobrine.dtsi
>
> Changes in v6:
> -- add data-lanes and link-frequencies to yaml
>
> Changes in v7:
> -- change 16000 to 162000
> -- separate yaml to different patch
>
> Changes in v8:
> -- correct Bjorn mail address to kernel.org
>
> Changes in v9:
> -- use symbol rate (hz) for link-frequencies at dp_out at sc7180_trogdor.dtsi
>
> Changes in v13:
> -- delete an extra space at data-lanes
>
> Signed-off-by: Kuogee Hsieh
> ---
> arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 6 +-
> arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 4
> 2 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
> b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
> index eae22e6..e2783dd 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
> @@ -814,7 +814,11 @@ hp_i2c: &i2c9 {
> status = "okay";
> pinctrl-names = "default";
> pinctrl-0 = <&dp_hot_plug_det>;
> - data-lanes = <0 1>;
> +};
> +
> +&dp_out {
> +data-lanes = <0 1>;
> +link-frequencies = /bits/ 64 <162000 27 54>;
Messed order of nodes.
> };
>
> &pm6150_adc {
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
> b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
> index c11e371..3f363f8 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
> @@ -442,7 +442,11 @@ ap_i2c_tpm: &i2c14 {
> status = "okay";
> pinctrl-names = "default";
> pinctrl-0 = <&dp_hot_plug_det>;
> +};
> +
> +&dp_out {
Same problem here.
Best regards,
Krzysztof
Re: [PATCH v15 1/5] arm64: dts: qcom: add data-lanes and link-freuencies into dp_out endpoint
On 16/12/2022 22:44, Kuogee Hsieh wrote:
> Move data-lanes property from mdss_dp node to dp_out endpoint. Also
> add link-frequencies property into dp_out endpoint as well. The last
> frequency specified at link-frequencies will be the max link rate
> supported by DP.
>
> Changes in v5:
> -- revert changes at sc7180.dtsi and sc7280.dtsi
> -- add &dp_out to sc7180-trogdor.dtsi and sc7280-herobrine.dtsi
>
> Changes in v6:
> -- add data-lanes and link-frequencies to yaml
>
> Changes in v7:
> -- change 16000 to 162000
> -- separate yaml to different patch
>
> Changes in v8:
> -- correct Bjorn mail address to kernel.org
>
> Changes in v9:
> -- use symbol rate (hz) for link-frequencies at dp_out at sc7180_trogdor.dtsi
>
> Changes in v13:
> -- delete an extra space at data-lanes
>
> Changes in v15:
> -- replace space with tab at sc7180-trogdor.dtsi
>
> Signed-off-by: Kuogee Hsieh
> ---
> arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 4
> arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 4
> 2 files changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
> b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
> index eae22e6..ad98a87 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
> @@ -814,7 +814,11 @@ hp_i2c: &i2c9 {
> status = "okay";
> pinctrl-names = "default";
> pinctrl-0 = <&dp_hot_plug_det>;
> +};
> +
> +&dp_out {
Still wrong order, I think.
Best regards,
Krzysztof
Re: [PATCH] drm/vmwgfx: Fix passing partly uninitialized drm_mode_fb_cmd2 struct #forregzbot
[Note: this mail contains only information for Linux kernel regression tracking. Mails like these contain '#forregzbot' in the subject to make then easy to spot and filter out. The author also tried to remove most or all individuals from the list of recipients to spare them the hassle.] On 21.12.22 03:23, Kaiwan N Billimoria wrote: > [REGRESSION] ? > > Testing with 6.1, I find the same issue - VirtualBox VMs seem to hang > on boot, though the kernel has this patch applied of course... > Am running VirtualBox 7.0.4 on an x86_64 Linux (Ubuntu 22.04.1) host; > the system hangs on boot with the screen > going blank. > Passing 'nomodeset' via GRUB fixes it.. Thanks for the report. To be sure below issue doesn't fall through the cracks unnoticed, I'm adding it to regzbot, my Linux kernel regression tracking bot: #regzbot ^introduced v6.0..v6.1 #regzbot title dri: vmwgfx: boot hang in VirtualBox due to an oops #regzbot ignore-activity Ciao, Thorsten (wearing his 'the Linux kernel's regression tracker' hat) P.S.: As the Linux kernel's regression tracker I deal with a lot of reports and sometimes miss something important when writing mails like this. If that's the case here, don't hesitate to tell me in a public reply, it's in everyone's interest to set the public record straight.
[PATCH] drm/i915: Fix same object multiple mmap memory leak
From: Tvrtko Ursulin
This is the fix proposed by Chuansheng Liu to
close a memory leak caused by refactoring done in 786555987207
("drm/i915/gem: Store mmap_offsets in an rbtree rather than a plain list").
Original commit text from Liu was this:
>
> The below memory leak information is caught:
>
> unreferenced object 0x997dd4e3b240 (size 64):
> comm "gem_tiled_fence", pid 10332, jiffies 4294959326 (age 220778.420s)
> hex dump (first 32 bytes):
> 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00 00 00 00 00 00 00 00 00 be f2 d4 7d 99 ff ff }...
> backtrace:
> [] kmem_cache_alloc_trace+0x2e5/0x450
> [] drm_vma_node_allow+0x2c/0xe0 [drm]
> [] __assign_mmap_offset_handle+0x1da/0x4a0 [i915]
> [] i915_gem_mmap_offset_ioctl+0x55/0xb0 [i915]
> [] drm_ioctl_kernel+0xb4/0x140 [drm]
> [] drm_ioctl+0x257/0x410 [drm]
> [] __x64_sys_ioctl+0x8e/0xc0
> [] do_syscall_64+0x38/0xc0
> [] entry_SYSCALL_64_after_hwframe+0x44/0xae
>
> The issue is always reproduced with the test:
> gem_tiled_fence_blits --run-subtest basic
>
> It tries to mmap_gtt the same object several times, it is like:
> create BO
> mmap_gtt BO
> unmap BO
> mmap_gtt BO <== second time mmap_gtt
> unmap
> close BO
>
> The leak happens at the second time mmap_gtt in function
> mmap_offset_attach(),it will simply increase the reference
> count to 2 by calling drm_vma_node_allow() directly since
> the mmo has been created at the first time.
>
> However the driver just revokes the vma_node only one time
> when closing the object, it leads to memory leak easily.
>
> This patch is to fix the memory leak by calling drm_vma_node_allow() one
> time also.
Issue was later also reported by Mirsad:
>
> The problem is a kernel memory leak that is repeatedly occurring
> triggered during the execution of Chrome browser under the latest
> 6.1.0+ kernel of this morning and Almalinux 8.6 on a Lenovo
> desktop box with Intel(R) Core(TM) i5-8400 CPU @ 2.80GHz CPU.
>
> The build is with KMEMLEAK, KASAN and MGLRU turned on during the
> build, on a vanilla mainline kernel from Mr. Torvalds' tree.
>
> The leaks look like this one:
>
> unreferenced object 0x888131754880 (size 64):
>comm "chrome", pid 13058, jiffies 4298568878 (age 3708.084s)
>hex dump (first 32 bytes):
> 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00 00 00 00 00 00 00 00 00 80 1e 3e 83 88 ff ff ...>
>backtrace:
> [] slab_post_alloc_hook+0xb2/0x340
> [] __kmem_cache_alloc_node+0x1bf/0x2c0
> [] kmalloc_trace+0x2a/0xb0
> [] drm_vma_node_allow+0x45/0x150 [drm]
> [] __assign_mmap_offset_handle+0x615/0x820 [i915]
> [] i915_gem_mmap_offset_ioctl+0x77/0x110 [i915]
> [] drm_ioctl_kernel+0x181/0x280 [drm]
> [] drm_ioctl+0x2dd/0x6a0 [drm]
> [] __x64_sys_ioctl+0xc4/0x100
> [] do_syscall_64+0x58/0x80
> [] entry_SYSCALL_64_after_hwframe+0x72/0xdc
>
Root cause is that 786555987207 started caching (and sharing) the
i915_mmap_offset objects per object and same mmap type. This means that
reference count incremented by drm_vma_node_allow could grow beyond one,
while the object closure path calls drm_vma_node_revoke only once and
so the structure leaks.
Secondary effect from this, which is also different than what we had
before 786555987207 is that it is now possible to mmap an offset belonging
to a closed object.
Fix here is to partially revert to behaviour before 786555987207 - that is
to disallow mmap of closed objects and to only increment the mmap offset
ref count once per object-type.
Signed-off-by: Tvrtko Ursulin
Co-developed-by: Chuansheng Liu
Fixes: 786555987207 ("drm/i915/gem: Store mmap_offsets in an rbtree rather than
a plain list")
Reported-by: Mirsad Todorovac
Tested-by: Mirsad Todorovac
Testcase: igt@gem_mmap_gtt@mmap-closed-bo
Cc: Matthew Auld
Cc: "Thomas Hellström"
Cc: # v5.7+
Reviewed-by: Tvrtko Ursulin
---
Test-with: 20221222100403.256775-1-tvrtko.ursu...@linux.intel.com
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index d73ba0f5c4c5..1ceff19a0ac0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -695,9 +695,10 @@ mmap_offset_attach(struct drm_i915_gem_object *obj,
insert:
mmo = insert_mmo(obj, mmo);
GEM_BUG_ON(lookup_mmo(obj, mmap_type) != mmo);
-out:
+
if (file)
drm_vma_node_allow(&mmo->vma_node, file);
+out:
return mmo;
err:
--
2.34.1
[PATCH 00/19] Introduce __xchg, non-atomic xchg
Hi all, I hope there will be place for such tiny helper in kernel. Quick cocci analyze shows there is probably few thousands places where it could be useful. I am not sure who is good person to review/ack such patches, so I've used my intuition to construct to/cc lists, sorry for mistakes. This is the 2nd approach of the same idea, with comments addressed[0]. The helper is tiny and there are advices we can leave without it, so I want to present few arguments why it would be good to have it: 1. Code readability/simplification/number of lines: Real example from drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c: - previous_min_rate = evport->qos.min_rate; - evport->qos.min_rate = min_rate; + previous_min_rate = __xchg(evport->qos.min_rate, min_rate); For sure the code is more compact, and IMHO more readable. 2. Presence of similar helpers in other somehow related languages/libs: a) Rust[1]: 'replace' from std::mem module, there is also 'take' helper (__xchg(&x, 0)), which is the same as private helper in i915 - fetch_and_zero, see latest patch. b) C++ [2]: 'exchange' from utility header. If the idea is OK there are still 2 qestions to answer: 1. Name of the helper, __xchg follows kernel conventions, but for me Rust names are also OK. 2. Where to put the helper: a) as in this patchset include/linux/non-atomic/xchg.h, proposed by Andy Shevchenko, b) include/linux/utils.h ? any better name? Some kind of container for simple helpers. Structure of the patchset: 17 patches releasing __xchg name from arch files 1 patch adding __xchg 1 patch adding users of __xchg Arnd thanks for convienient set of cross compilers, it was very helpful. So many words for so small helper :) [0]: https://lore.kernel.org/lkml/y5ofsvaybv4xc...@smile.fi.intel.com/T/ [1]: https://doc.rust-lang.org/std/mem/index.html [2]: https://en.cppreference.com/w/cpp/header/utility Regards Andrzej Andrzej Hajda (19): arch/alpha: rename internal name __xchg to __arch_xchg arch/arc: rename internal name __xchg to __arch_xchg arch/arm: rename internal name __xchg to __arch_xchg arch/arm64: rename internal name __xchg to __arch_xchg arch/hexagon: rename internal name __xchg to __arch_xchg arch/ia64: rename internal name __xchg to __arch_xchg arch/loongarch: rename internal name __xchg to __arch_xchg arch/m68k: rename internal name __xchg to __arch_xchg arch/mips: rename internal name __xchg to __arch_xchg arch/openrisc: rename internal name __xchg to __arch_xchg arch/parisc: rename internal name __xchg to __arch_xchg arch/powerpc: correct logged function names in xchg helpers arch/riscv: rename internal name __xchg to __arch_xchg arch/s390: rename internal name __xchg to __arch_xchg arch/sh: rename internal name __xchg to __arch_xchg arch/sparc: rename internal name __xchg to __arch_xchg arch/xtensa: rename internal name __xchg to __arch_xchg linux/include: add non-atomic version of xchg drm/i915/gt: use __xchg instead of internal helper arch/alpha/include/asm/cmpxchg.h | 6 +++--- arch/arc/include/asm/cmpxchg.h| 4 ++-- arch/arm/include/asm/cmpxchg.h| 4 ++-- arch/arm64/include/asm/cmpxchg.h | 4 ++-- arch/hexagon/include/asm/cmpxchg.h| 6 +++--- arch/ia64/include/asm/cmpxchg.h | 2 +- arch/ia64/include/uapi/asm/cmpxchg.h | 4 ++-- arch/loongarch/include/asm/cmpxchg.h | 4 ++-- arch/m68k/include/asm/cmpxchg.h | 6 +++--- arch/mips/include/asm/cmpxchg.h | 4 ++-- arch/openrisc/include/asm/cmpxchg.h | 4 ++-- arch/parisc/include/asm/cmpxchg.h | 4 ++-- arch/powerpc/include/asm/cmpxchg.h| 4 ++-- arch/riscv/include/asm/atomic.h | 2 +- arch/riscv/include/asm/cmpxchg.h | 4 ++-- arch/s390/include/asm/cmpxchg.h | 4 ++-- arch/sh/include/asm/cmpxchg.h | 4 ++-- arch/sparc/include/asm/cmpxchg_32.h | 4 ++-- arch/sparc/include/asm/cmpxchg_64.h | 4 ++-- arch/xtensa/include/asm/cmpxchg.h | 4 ++-- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 4 ++-- .../drm/i915/gt/intel_execlists_submission.c | 4 ++-- drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 ++-- drivers/gpu/drm/i915/gt/intel_gsc.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt.c| 4 ++-- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +++--- drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +- drivers/gpu/drm/i915/gt/intel_rps.c | 2 +- drivers/gpu/drm/i915/gt/selftest_context.c| 2 +- .../drm/i915/gt/selftest_ring_submission.c| 2 +- drivers/gpu/drm/i915/gt/selftest_timeline.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
Re: [PATCH v5 04/21] dt-bindings: msm: dsi-controller-main: Add compatible strings for every current SoC
On 20/12/2022 13:36, Bryan O'Donoghue wrote: > Currently we do not differentiate between the various users of the > qcom,mdss-dsi-ctrl. The driver is flexible enough to operate from one > compatible string but, the hardware does have some significant differences > in the number of clocks. > > To facilitate documenting the clocks add the following compatible strings > > - qcom,apq8064-dsi-ctrl > - qcom,msm8916-dsi-ctrl > - qcom,msm8953-dsi-ctrl > - qcom,msm8974-dsi-ctrl > - qcom,msm8996-dsi-ctrl > - qcom,msm8998-dsi-ctrl > - qcom,sc7180-dsi-ctrl > - qcom,sc7280-dsi-ctrl > - qcom,sdm660-dsi-ctrl > - qcom,sdm845-dsi-ctrl > - qcom,sm8250-dsi-ctrl > > Each SoC dtsi should declare "qcom,socname-dsi-ctrl", "qcom,mdss-dsi-ctrl"; > > Signed-off-by: Bryan O'Donoghue > --- > .../display/msm/dsi-controller-main.yaml | 20 +++ > 1 file changed, 16 insertions(+), 4 deletions(-) > > diff --git > a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > index 6e2fd6e9fa7f0..01afa9e9c4b3c 100644 > --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > @@ -14,9 +14,21 @@ allOf: > > properties: >compatible: > -enum: > - - qcom,mdss-dsi-ctrl > - - qcom,dsi-ctrl-6g-qcm2290 > +items: > + - enum: > + - qcom,apq8064-dsi-ctrl > + - qcom,msm8916-dsi-ctrl > + - qcom,msm8953-dsi-ctrl > + - qcom,msm8974-dsi-ctrl > + - qcom,msm8996-dsi-ctrl > + - qcom,msm8998-dsi-ctrl > + - qcom,dsi-ctrl-6g-qcm2290 > + - qcom,sc7180-dsi-ctrl > + - qcom,sc7280-dsi-ctrl > + - qcom,sdm660-dsi-ctrl > + - qcom,sdm845-dsi-ctrl > + - qcom,sm8250-dsi-ctrl Usual comment: can we keep the list sorted? Best regards, Krzysztof
[PATCH 01/19] arch/alpha: rename internal name __xchg to __arch_xchg
__xchg will be used for non-atomic xchg macro. Signed-off-by: Andrzej Hajda --- arch/alpha/include/asm/cmpxchg.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/alpha/include/asm/cmpxchg.h b/arch/alpha/include/asm/cmpxchg.h index 6e0a850aa9d38c..40e8159ef6e794 100644 --- a/arch/alpha/include/asm/cmpxchg.h +++ b/arch/alpha/include/asm/cmpxchg.h @@ -6,7 +6,7 @@ * Atomic exchange routines. */ -#define xchg(type, args...)__xchg ## type ## _local(args) +#define xchg(type, args...)__arch_xchg ## type ## _local(args) #define cmpxchg(type, args...) __cmpxchg ## type ## _local(args) #include @@ -34,7 +34,7 @@ #undef xchg #undef cmpxchg -#define xchg(type, args...)__xchg ##type(args) +#define xchg(type, args...)__arch_xchg ##type(args) #define cmpxchg(type, args...) __cmpxchg ##type(args) #include @@ -48,7 +48,7 @@ __typeof__(*(ptr)) _x_ = (x); \ smp_mb(); \ __ret = (__typeof__(*(ptr)))\ - __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \ + __arch_xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \ smp_mb(); \ __ret; \ }) -- 2.34.1
[PATCH 03/19] arch/arm: rename internal name __xchg to __arch_xchg
__xchg will be used for non-atomic xchg macro.
Signed-off-by: Andrzej Hajda
---
arch/arm/include/asm/cmpxchg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
index 4dfe538dfc689b..6953fc05a97886 100644
--- a/arch/arm/include/asm/cmpxchg.h
+++ b/arch/arm/include/asm/cmpxchg.h
@@ -25,7 +25,7 @@
#define swp_is_buggy
#endif
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int
size)
+static inline unsigned long __arch_xchg(unsigned long x, volatile void *ptr,
int size)
{
extern void __bad_xchg(volatile void *, int);
unsigned long ret;
@@ -115,7 +115,7 @@ static inline unsigned long __xchg(unsigned long x,
volatile void *ptr, int size
}
#define arch_xchg_relaxed(ptr, x) ({ \
- (__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), \
+ (__typeof__(*(ptr)))__arch_xchg((unsigned long)(x), (ptr),
\
sizeof(*(ptr))); \
})
--
2.34.1
[PATCH 02/19] arch/arc: rename internal name __xchg to __arch_xchg
__xchg will be used for non-atomic xchg macro.
Signed-off-by: Andrzej Hajda
---
arch/arc/include/asm/cmpxchg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arc/include/asm/cmpxchg.h b/arch/arc/include/asm/cmpxchg.h
index c5b544a5fe8106..e138fde067dea5 100644
--- a/arch/arc/include/asm/cmpxchg.h
+++ b/arch/arc/include/asm/cmpxchg.h
@@ -85,7 +85,7 @@
*/
#ifdef CONFIG_ARC_HAS_LLSC
-#define __xchg(ptr, val) \
+#define __arch_xchg(ptr, val) \
({ \
__asm__ __volatile__( \
" ex %0, [%1]\n" /* set new value */ \
@@ -102,7 +102,7 @@
\
switch(sizeof(*(_p_))) {\
case 4: \
- _val_ = __xchg(_p_, _val_); \
+ _val_ = __arch_xchg(_p_, _val_);\
break; \
default:\
BUILD_BUG();\
--
2.34.1
[PATCH 05/19] arch/hexagon: rename internal name __xchg to __arch_xchg
__xchg will be used for non-atomic xchg macro.
Signed-off-by: Andrzej Hajda
---
arch/hexagon/include/asm/cmpxchg.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/hexagon/include/asm/cmpxchg.h
b/arch/hexagon/include/asm/cmpxchg.h
index cdb705e1496af8..92dc5e5f836f3b 100644
--- a/arch/hexagon/include/asm/cmpxchg.h
+++ b/arch/hexagon/include/asm/cmpxchg.h
@@ -9,7 +9,7 @@
#define _ASM_CMPXCHG_H
/*
- * __xchg - atomically exchange a register and a memory location
+ * __arch_xchg - atomically exchange a register and a memory location
* @x: value to swap
* @ptr: pointer to memory
* @size: size of the value
@@ -19,7 +19,7 @@
* Note: there was an errata for V2 about .new's and memw_locked.
*
*/
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
+static inline unsigned long __arch_xchg(unsigned long x, volatile void *ptr,
int size)
{
unsigned long retval;
@@ -42,7 +42,7 @@ static inline unsigned long __xchg(unsigned long x, volatile
void *ptr,
* Atomically swap the contents of a register with memory. Should be atomic
* between multiple CPU's and within interrupts on the same CPU.
*/
-#define arch_xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),
(ptr), \
+#define arch_xchg(ptr, v) ((__typeof__(*(ptr)))__arch_xchg((unsigned long)(v),
(ptr), \
sizeof(*(ptr
/*
--
2.34.1
[PATCH 04/19] arch/arm64: rename internal name __xchg to __arch_xchg
__xchg will be used for non-atomic xchg macro.
Signed-off-by: Andrzej Hajda
---
arch/arm64/include/asm/cmpxchg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/cmpxchg.h b/arch/arm64/include/asm/cmpxchg.h
index 497acf134d9923..3a36ba58e8c2ef 100644
--- a/arch/arm64/include/asm/cmpxchg.h
+++ b/arch/arm64/include/asm/cmpxchg.h
@@ -62,7 +62,7 @@ __XCHG_CASE( , , mb_, 64, dmb ish, nop, , a, l, "memory")
#undef __XCHG_CASE
#define __XCHG_GEN(sfx)
\
-static __always_inline unsigned long __xchg##sfx(unsigned long x, \
+static __always_inline unsigned long __arch_xchg##sfx(unsigned long x,
\
volatile void *ptr, \
int size) \
{ \
@@ -93,7 +93,7 @@ __XCHG_GEN(_mb)
({ \
__typeof__(*(ptr)) __ret; \
__ret = (__typeof__(*(ptr)))\
- __xchg##sfx((unsigned long)(x), (ptr), sizeof(*(ptr))); \
+ __arch_xchg##sfx((unsigned long)(x), (ptr), sizeof(*(ptr))); \
__ret; \
})
--
2.34.1
[PATCH 07/19] arch/loongarch: rename internal name __xchg to __arch_xchg
__xchg will be used for non-atomic xchg macro.
Signed-off-by: Andrzej Hajda
---
arch/loongarch/include/asm/cmpxchg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/loongarch/include/asm/cmpxchg.h
b/arch/loongarch/include/asm/cmpxchg.h
index ecfa6cf79806e6..979fde61bba8a4 100644
--- a/arch/loongarch/include/asm/cmpxchg.h
+++ b/arch/loongarch/include/asm/cmpxchg.h
@@ -62,7 +62,7 @@ static inline unsigned int __xchg_small(volatile void *ptr,
unsigned int val,
}
static __always_inline unsigned long
-__xchg(volatile void *ptr, unsigned long x, int size)
+__arch_xchg(volatile void *ptr, unsigned long x, int size)
{
switch (size) {
case 1:
@@ -87,7 +87,7 @@ __xchg(volatile void *ptr, unsigned long x, int size)
__typeof__(*(ptr)) __res; \
\
__res = (__typeof__(*(ptr)))\
- __xchg((ptr), (unsigned long)(x), sizeof(*(ptr))); \
+ __arch_xchg((ptr), (unsigned long)(x), sizeof(*(ptr))); \
\
__res; \
})
--
2.34.1
[PATCH 08/19] arch/m68k: rename internal name __xchg to __arch_xchg
__xchg will be used for non-atomic xchg macro.
Signed-off-by: Andrzej Hajda
---
arch/m68k/include/asm/cmpxchg.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/m68k/include/asm/cmpxchg.h b/arch/m68k/include/asm/cmpxchg.h
index 6cf464cdab067e..d7f3de9c5d6f79 100644
--- a/arch/m68k/include/asm/cmpxchg.h
+++ b/arch/m68k/include/asm/cmpxchg.h
@@ -9,7 +9,7 @@
extern unsigned long __invalid_xchg_size(unsigned long, volatile void *, int);
#ifndef CONFIG_RMW_INSNS
-static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int
size)
+static inline unsigned long __arch_xchg(unsigned long x, volatile void * ptr,
int size)
{
unsigned long flags, tmp;
@@ -40,7 +40,7 @@ static inline unsigned long __xchg(unsigned long x, volatile
void * ptr, int siz
return x;
}
#else
-static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int
size)
+static inline unsigned long __arch_xchg(unsigned long x, volatile void * ptr,
int size)
{
switch (size) {
case 1:
@@ -75,7 +75,7 @@ static inline unsigned long __xchg(unsigned long x, volatile
void * ptr, int siz
}
#endif
-#define arch_xchg(ptr,x) ({(__typeof__(*(ptr)))__xchg((unsigned
long)(x),(ptr),sizeof(*(ptr)));})
+#define arch_xchg(ptr,x) ({(__typeof__(*(ptr)))__arch_xchg((unsigned
long)(x),(ptr),sizeof(*(ptr)));})
#include
--
2.34.1
[PATCH 06/19] arch/ia64: rename internal name __xchg to __arch_xchg
__xchg will be used for non-atomic xchg macro.
Signed-off-by: Andrzej Hajda
---
arch/ia64/include/asm/cmpxchg.h | 2 +-
arch/ia64/include/uapi/asm/cmpxchg.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/ia64/include/asm/cmpxchg.h b/arch/ia64/include/asm/cmpxchg.h
index 94ef844298431a..8b2e644ef6a14e 100644
--- a/arch/ia64/include/asm/cmpxchg.h
+++ b/arch/ia64/include/asm/cmpxchg.h
@@ -5,7 +5,7 @@
#include
#define arch_xchg(ptr, x) \
-({(__typeof__(*(ptr))) __xchg((unsigned long) (x), (ptr), sizeof(*(ptr)));})
+({(__typeof__(*(ptr))) __arch_xchg((unsigned long) (x), (ptr),
sizeof(*(ptr)));})
#define arch_cmpxchg(ptr, o, n)cmpxchg_acq((ptr), (o), (n))
#define arch_cmpxchg64(ptr, o, n) cmpxchg_acq((ptr), (o), (n))
diff --git a/arch/ia64/include/uapi/asm/cmpxchg.h
b/arch/ia64/include/uapi/asm/cmpxchg.h
index ca2e0268534384..3fec9b037051bb 100644
--- a/arch/ia64/include/uapi/asm/cmpxchg.h
+++ b/arch/ia64/include/uapi/asm/cmpxchg.h
@@ -27,7 +27,7 @@
*/
extern void ia64_xchg_called_with_bad_pointer(void);
-#define __xchg(x, ptr, size) \
+#define __arch_xchg(x, ptr, size) \
({ \
unsigned long __xchg_result;\
\
@@ -55,7 +55,7 @@ extern void ia64_xchg_called_with_bad_pointer(void);
#ifndef __KERNEL__
#define xchg(ptr, x) \
-({(__typeof__(*(ptr))) __xchg((unsigned long) (x), (ptr), sizeof(*(ptr)));})
+({(__typeof__(*(ptr))) __arch_xchg((unsigned long) (x), (ptr),
sizeof(*(ptr)));})
#endif
/*
--
2.34.1
[PATCH 09/19] arch/mips: rename internal name __xchg to __arch_xchg
__xchg will be used for non-atomic xchg macro.
Signed-off-by: Andrzej Hajda
---
arch/mips/include/asm/cmpxchg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index 7ec9493b28614f..feed343ad483a9 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -68,7 +68,7 @@ extern unsigned long __xchg_small(volatile void *ptr,
unsigned long val,
unsigned int size);
static __always_inline
-unsigned long __xchg(volatile void *ptr, unsigned long x, int size)
+unsigned long __arch_xchg(volatile void *ptr, unsigned long x, int size)
{
switch (size) {
case 1:
@@ -102,7 +102,7 @@ unsigned long __xchg(volatile void *ptr, unsigned long x,
int size)
smp_mb__before_llsc(); \
\
__res = (__typeof__(*(ptr)))\
- __xchg((ptr), (unsigned long)(x), sizeof(*(ptr))); \
+ __arch_xchg((ptr), (unsigned long)(x), sizeof(*(ptr))); \
\
smp_llsc_mb(); \
\
--
2.34.1
Re: [PATCH v5 04/21] dt-bindings: msm: dsi-controller-main: Add compatible strings for every current SoC
On 22/12/2022 12:47, Krzysztof Kozlowski wrote: > On 20/12/2022 13:36, Bryan O'Donoghue wrote: >> Currently we do not differentiate between the various users of the >> qcom,mdss-dsi-ctrl. The driver is flexible enough to operate from one >> compatible string but, the hardware does have some significant differences >> in the number of clocks. >> >> To facilitate documenting the clocks add the following compatible strings >> >> - qcom,apq8064-dsi-ctrl >> - qcom,msm8916-dsi-ctrl >> - qcom,msm8953-dsi-ctrl >> - qcom,msm8974-dsi-ctrl >> - qcom,msm8996-dsi-ctrl >> - qcom,msm8998-dsi-ctrl >> - qcom,sc7180-dsi-ctrl >> - qcom,sc7280-dsi-ctrl >> - qcom,sdm660-dsi-ctrl >> - qcom,sdm845-dsi-ctrl >> - qcom,sm8250-dsi-ctrl >> >> Each SoC dtsi should declare "qcom,socname-dsi-ctrl", "qcom,mdss-dsi-ctrl"; >> >> Signed-off-by: Bryan O'Donoghue >> --- >> .../display/msm/dsi-controller-main.yaml | 20 +++ >> 1 file changed, 16 insertions(+), 4 deletions(-) >> >> diff --git >> a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml >> b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml >> index 6e2fd6e9fa7f0..01afa9e9c4b3c 100644 >> --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml >> +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml >> @@ -14,9 +14,21 @@ allOf: >> >> properties: >>compatible: >> -enum: >> - - qcom,mdss-dsi-ctrl >> - - qcom,dsi-ctrl-6g-qcm2290 >> +items: >> + - enum: >> + - qcom,apq8064-dsi-ctrl >> + - qcom,msm8916-dsi-ctrl >> + - qcom,msm8953-dsi-ctrl >> + - qcom,msm8974-dsi-ctrl >> + - qcom,msm8996-dsi-ctrl >> + - qcom,msm8998-dsi-ctrl >> + - qcom,dsi-ctrl-6g-qcm2290 >> + - qcom,sc7180-dsi-ctrl >> + - qcom,sc7280-dsi-ctrl >> + - qcom,sdm660-dsi-ctrl >> + - qcom,sdm845-dsi-ctrl >> + - qcom,sm8250-dsi-ctrl > > Usual comment: can we keep the list sorted? Actually it is sorted, except the qcom,dsi-ctrl-6g-qcm2290. Please move it after apq. Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof
[PATCH 11/19] arch/parisc: rename internal name __xchg to __arch_xchg
__xchg will be used for non-atomic xchg macro.
Signed-off-by: Andrzej Hajda
---
arch/parisc/include/asm/cmpxchg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/parisc/include/asm/cmpxchg.h
b/arch/parisc/include/asm/cmpxchg.h
index 5f274be105671e..c1d776bb16b4ed 100644
--- a/arch/parisc/include/asm/cmpxchg.h
+++ b/arch/parisc/include/asm/cmpxchg.h
@@ -22,7 +22,7 @@ extern unsigned long __xchg64(unsigned long, volatile
unsigned long *);
/* optimizer better get rid of switch since size is a constant */
static inline unsigned long
-__xchg(unsigned long x, volatile void *ptr, int size)
+__arch_xchg(unsigned long x, volatile void *ptr, int size)
{
switch (size) {
#ifdef CONFIG_64BIT
@@ -49,7 +49,7 @@ __xchg(unsigned long x, volatile void *ptr, int size)
__typeof__(*(ptr)) __ret; \
__typeof__(*(ptr)) _x_ = (x); \
__ret = (__typeof__(*(ptr)))\
- __xchg((unsigned long)_x_, (ptr), sizeof(*(ptr))); \
+ __arch_xchg((unsigned long)_x_, (ptr), sizeof(*(ptr))); \
__ret; \
})
--
2.34.1
[PATCH 10/19] arch/openrisc: rename internal name __xchg to __arch_xchg
__xchg will be used for non-atomic xchg macro.
Signed-off-by: Andrzej Hajda
---
arch/openrisc/include/asm/cmpxchg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/openrisc/include/asm/cmpxchg.h
b/arch/openrisc/include/asm/cmpxchg.h
index 79fd16162ccb6d..5725e22e10683b 100644
--- a/arch/openrisc/include/asm/cmpxchg.h
+++ b/arch/openrisc/include/asm/cmpxchg.h
@@ -147,7 +147,7 @@ static inline unsigned long __cmpxchg(volatile void *ptr,
unsigned long old,
extern unsigned long __xchg_called_with_bad_pointer(void)
__compiletime_error("Bad argument size for xchg");
-static inline unsigned long __xchg(volatile void *ptr, unsigned long with,
+static inline unsigned long __arch_xchg(volatile void *ptr, unsigned long with,
int size)
{
switch (size) {
@@ -163,7 +163,7 @@ static inline unsigned long __xchg(volatile void *ptr,
unsigned long with,
#define arch_xchg(ptr, with) \
({ \
- (__typeof__(*(ptr))) __xchg((ptr), \
+ (__typeof__(*(ptr))) __arch_xchg((ptr), \
(unsigned long)(with), \
sizeof(*(ptr)));\
})
--
2.34.1
[PATCH 12/19] arch/powerpc: correct logged function names in xchg helpers
__xchg will be used for non-atomic xchg macro. Signed-off-by: Andrzej Hajda --- arch/powerpc/include/asm/cmpxchg.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/cmpxchg.h b/arch/powerpc/include/asm/cmpxchg.h index 05f246c0e36eb3..b5624c9fe09bf7 100644 --- a/arch/powerpc/include/asm/cmpxchg.h +++ b/arch/powerpc/include/asm/cmpxchg.h @@ -163,7 +163,7 @@ __xchg_local(void *ptr, unsigned long x, unsigned int size) return __xchg_u64_local(ptr, x); #endif } - BUILD_BUG_ON_MSG(1, "Unsupported size for __xchg"); + BUILD_BUG_ON_MSG(1, "Unsupported size for __xchg_local"); return x; } @@ -182,7 +182,7 @@ __xchg_relaxed(void *ptr, unsigned long x, unsigned int size) return __xchg_u64_relaxed(ptr, x); #endif } - BUILD_BUG_ON_MSG(1, "Unsupported size for __xchg_local"); + BUILD_BUG_ON_MSG(1, "Unsupported size for __xchg_relaxed"); return x; } #define arch_xchg_local(ptr,x) \ -- 2.34.1
[PATCH 13/19] arch/riscv: rename internal name __xchg to __arch_xchg
__xchg will be used for non-atomic xchg macro.
Signed-off-by: Andrzej Hajda
---
arch/riscv/include/asm/atomic.h | 2 +-
arch/riscv/include/asm/cmpxchg.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h
index 0dfe9d857a762b..bba472928b5393 100644
--- a/arch/riscv/include/asm/atomic.h
+++ b/arch/riscv/include/asm/atomic.h
@@ -261,7 +261,7 @@ c_t arch_atomic##prefix##_xchg_release(atomic##prefix##_t
*v, c_t n)\
static __always_inline \
c_t arch_atomic##prefix##_xchg(atomic##prefix##_t *v, c_t n) \
{ \
- return __xchg(&(v->counter), n, size); \
+ return __arch_xchg(&(v->counter), n, size); \
} \
static __always_inline \
c_t arch_atomic##prefix##_cmpxchg_relaxed(atomic##prefix##_t *v, \
diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
index 12debce235e52d..2f4726d3cfcc25 100644
--- a/arch/riscv/include/asm/cmpxchg.h
+++ b/arch/riscv/include/asm/cmpxchg.h
@@ -114,7 +114,7 @@
_x_, sizeof(*(ptr))); \
})
-#define __xchg(ptr, new, size) \
+#define __arch_xchg(ptr, new, size)\
({ \
__typeof__(ptr) __ptr = (ptr); \
__typeof__(new) __new = (new); \
@@ -143,7 +143,7 @@
#define arch_xchg(ptr, x) \
({ \
__typeof__(*(ptr)) _x_ = (x); \
- (__typeof__(*(ptr))) __xchg((ptr), _x_, sizeof(*(ptr)));\
+ (__typeof__(*(ptr))) __arch_xchg((ptr), _x_, sizeof(*(ptr))); \
})
#define xchg32(ptr, x) \
--
2.34.1
[PATCH 14/19] arch/s390: rename internal name __xchg to __arch_xchg
__xchg will be used for non-atomic xchg macro.
Signed-off-by: Andrzej Hajda
---
arch/s390/include/asm/cmpxchg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/s390/include/asm/cmpxchg.h b/arch/s390/include/asm/cmpxchg.h
index 84c3f0d576c5b1..efc16f4aac8643 100644
--- a/arch/s390/include/asm/cmpxchg.h
+++ b/arch/s390/include/asm/cmpxchg.h
@@ -14,7 +14,7 @@
void __xchg_called_with_bad_pointer(void);
-static __always_inline unsigned long __xchg(unsigned long x,
+static __always_inline unsigned long __arch_xchg(unsigned long x,
unsigned long address, int size)
{
unsigned long old;
@@ -77,7 +77,7 @@ static __always_inline unsigned long __xchg(unsigned long x,
__typeof__(*(ptr)) __ret; \
\
__ret = (__typeof__(*(ptr)))\
- __xchg((unsigned long)(x), (unsigned long)(ptr),\
+ __arch_xchg((unsigned long)(x), (unsigned long)(ptr), \
sizeof(*(ptr))); \
__ret; \
})
--
2.34.1
[PATCH 15/19] arch/sh: rename internal name __xchg to __arch_xchg
__xchg will be used for non-atomic xchg macro.
Signed-off-by: Andrzej Hajda
---
arch/sh/include/asm/cmpxchg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/sh/include/asm/cmpxchg.h b/arch/sh/include/asm/cmpxchg.h
index 0ed9b3f4a57796..288f6f38d98fb4 100644
--- a/arch/sh/include/asm/cmpxchg.h
+++ b/arch/sh/include/asm/cmpxchg.h
@@ -22,7 +22,7 @@
extern void __xchg_called_with_bad_pointer(void);
-#define __xchg(ptr, x, size) \
+#define __arch_xchg(ptr, x, size) \
({ \
unsigned long __xchg__res; \
volatile void *__xchg_ptr = (ptr); \
@@ -46,7 +46,7 @@ extern void __xchg_called_with_bad_pointer(void);
})
#define arch_xchg(ptr,x) \
- ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr
+ ((__typeof__(*(ptr)))__arch_xchg((ptr),(unsigned long)(x),
sizeof(*(ptr
/* This function doesn't exist, so you'll get a linker error
* if something tries to do an invalid cmpxchg(). */
--
2.34.1
[PATCH 16/19] arch/sparc: rename internal name __xchg to __arch_xchg
__xchg will be used for non-atomic xchg macro.
Signed-off-by: Andrzej Hajda
---
arch/sparc/include/asm/cmpxchg_32.h | 4 ++--
arch/sparc/include/asm/cmpxchg_64.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/sparc/include/asm/cmpxchg_32.h
b/arch/sparc/include/asm/cmpxchg_32.h
index 27a57a3a7597eb..7a1339533d1d7e 100644
--- a/arch/sparc/include/asm/cmpxchg_32.h
+++ b/arch/sparc/include/asm/cmpxchg_32.h
@@ -15,7 +15,7 @@
unsigned long __xchg_u32(volatile u32 *m, u32 new);
void __xchg_called_with_bad_pointer(void);
-static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
int size)
+static inline unsigned long __arch_xchg(unsigned long x, __volatile__ void *
ptr, int size)
{
switch (size) {
case 4:
@@ -25,7 +25,7 @@ static inline unsigned long __xchg(unsigned long x,
__volatile__ void * ptr, int
return x;
}
-#define arch_xchg(ptr,x) ({(__typeof__(*(ptr)))__xchg((unsigned
long)(x),(ptr),sizeof(*(ptr)));})
+#define arch_xchg(ptr,x) ({(__typeof__(*(ptr)))__arch_xchg((unsigned
long)(x),(ptr),sizeof(*(ptr)));})
/* Emulate cmpxchg() the same way we emulate atomics,
* by hashing the object address and indexing into an array
diff --git a/arch/sparc/include/asm/cmpxchg_64.h
b/arch/sparc/include/asm/cmpxchg_64.h
index 12d00a42c0a3ed..4c22fd9110c945 100644
--- a/arch/sparc/include/asm/cmpxchg_64.h
+++ b/arch/sparc/include/asm/cmpxchg_64.h
@@ -55,7 +55,7 @@ static inline unsigned long xchg64(__volatile__ unsigned long
*m, unsigned long
#define arch_xchg(ptr,x)
\
({ __typeof__(*(ptr)) __ret; \
__ret = (__typeof__(*(ptr)))\
- __xchg((unsigned long)(x), (ptr), sizeof(*(ptr))); \
+ __arch_xchg((unsigned long)(x), (ptr), sizeof(*(ptr))); \
__ret; \
})
@@ -87,7 +87,7 @@ xchg16(__volatile__ unsigned short *m, unsigned short val)
return (load32 & mask) >> bit_shift;
}
-static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
+static inline unsigned long __arch_xchg(unsigned long x, __volatile__ void *
ptr,
int size)
{
switch (size) {
--
2.34.1
[PATCH 17/19] arch/xtensa: rename internal name __xchg to __arch_xchg
__xchg will be used for non-atomic xchg macro.
Signed-off-by: Andrzej Hajda
---
arch/xtensa/include/asm/cmpxchg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/xtensa/include/asm/cmpxchg.h
b/arch/xtensa/include/asm/cmpxchg.h
index eb87810357ad88..675a11ea8de76b 100644
--- a/arch/xtensa/include/asm/cmpxchg.h
+++ b/arch/xtensa/include/asm/cmpxchg.h
@@ -170,7 +170,7 @@ static inline unsigned long xchg_u32(volatile int * m,
unsigned long val)
}
#define arch_xchg(ptr,x) \
- ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr
+ ((__typeof__(*(ptr)))__arch_xchg((unsigned
long)(x),(ptr),sizeof(*(ptr
static inline u32 xchg_small(volatile void *ptr, u32 x, int size)
{
@@ -203,7 +203,7 @@ static inline u32 xchg_small(volatile void *ptr, u32 x, int
size)
extern void __xchg_called_with_bad_pointer(void);
static __inline__ unsigned long
-__xchg(unsigned long x, volatile void * ptr, int size)
+__arch_xchg(unsigned long x, volatile void * ptr, int size)
{
switch (size) {
case 1:
--
2.34.1
[PATCH 18/19] linux/include: add non-atomic version of xchg
The pattern of setting variable with new value and returning old
one is very common in kernel. Usually atomicity of the operation
is not required, so xchg seems to be suboptimal and confusing in
such cases.
Signed-off-by: Andrzej Hajda
---
include/linux/non-atomic/xchg.h | 19 +++
1 file changed, 19 insertions(+)
create mode 100644 include/linux/non-atomic/xchg.h
diff --git a/include/linux/non-atomic/xchg.h b/include/linux/non-atomic/xchg.h
new file mode 100644
index 00..f7fa5dd746f37d
--- /dev/null
+++ b/include/linux/non-atomic/xchg.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _LINUX_NON_ATOMIC_XCHG_H
+#define _LINUX_NON_ATOMIC_XCHG_H
+
+/**
+ * __xchg - set variable pointed by @ptr to @val, return old value
+ * @ptr: pointer to affected variable
+ * @val: value to be written
+ *
+ * This is non-atomic variant of xchg.
+ */
+#define __xchg(ptr, val) ({\
+ __auto_type __ptr = ptr;\
+ __auto_type __t = *__ptr; \
+ *__ptr = (val); \
+ __t;\
+})
+
+#endif
--
2.34.1
[PATCH 19/19] drm/i915/gt: use __xchg instead of internal helper
Prefer core helper if available.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 2 +-
drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_gsc.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt_pm.c| 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_context.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_timeline.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
drivers/gpu/drm/i915/i915_utils.h| 1 +
18 files changed, 24 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 99c4b866adddfa..aa548bd0b83687 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1042,7 +1042,7 @@ static void cleanup_status_page(struct intel_engine_cs
*engine)
/* Prevent writes into HWSP after returning the page to the system */
intel_engine_set_hwsp_writemask(engine, ~0u);
- vma = fetch_and_zero(&engine->status_page.vma);
+ vma = __xchg(&engine->status_page.vma, 0);
if (!vma)
return;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index 9a527e1f5be655..09befcc6a84fa1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -229,7 +229,7 @@ static void heartbeat(struct work_struct *wrk)
mutex_unlock(&ce->timeline->mutex);
out:
if (!engine->i915->params.enable_hangcheck || !next_heartbeat(engine))
- i915_request_put(fetch_and_zero(&engine->heartbeat.systole));
+ i915_request_put(__xchg(&engine->heartbeat.systole, 0));
intel_engine_pm_put(engine);
}
@@ -244,7 +244,7 @@ void intel_engine_unpark_heartbeat(struct intel_engine_cs
*engine)
void intel_engine_park_heartbeat(struct intel_engine_cs *engine)
{
if (cancel_delayed_work(&engine->heartbeat.work))
- i915_request_put(fetch_and_zero(&engine->heartbeat.systole));
+ i915_request_put(__xchg(&engine->heartbeat.systole, 0));
}
void intel_gt_unpark_heartbeats(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 49a8f10d76c77b..692f18e5a10ef3 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3197,7 +3197,7 @@ static void execlists_reset_cancel(struct intel_engine_cs
*engine)
RB_CLEAR_NODE(rb);
spin_lock(&ve->base.sched_engine->lock);
- rq = fetch_and_zero(&ve->request);
+ rq = __xchg(&ve->request, NULL);
if (rq) {
if (i915_request_mark_eio(rq)) {
rq->engine = engine;
@@ -3602,7 +3602,7 @@ static void rcu_virtual_context_destroy(struct
work_struct *wrk)
spin_lock_irq(&ve->base.sched_engine->lock);
- old = fetch_and_zero(&ve->request);
+ old = __xchg(&ve->request, NULL);
if (old) {
GEM_BUG_ON(!__i915_request_is_complete(old));
__i915_request_submit(old);
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 0c7fe360f87331..81317187d0c5c6 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -684,7 +684,7 @@ static void fini_aliasing_ppgtt(struct i915_ggtt *ggtt)
{
struct i915_ppgtt *ppgtt;
- ppgtt = fetch_and_zero(&ggtt->alias);
+ ppgtt = __xchg(&ggtt->alias, NULL);
if (!ppgtt)
return;
@@ -1238,7 +1238,7 @@ bool i915_ggtt_resume_vm(struct i915_address_space *vm)
was_bound);
if (obj) { /* only used during resume => exclusive access */
- write_domain_objs |= fetch_and_zero(&obj->write_domain);
+ write_domain_objs |= __xchg(&obj->write_domain, 0);
obj->read_domains |= I915_GEM_DOMAIN_GTT;
}
}
diff --git a/drivers/gpu/drm/i915/gt/int
Re: [PATCH v5 05/21] dt-bindings: msm: dsi-controller-main: Deprecate qcom,dsi-ctrl-6g-qcm2290 in favour of qcom,qcm2290-dsi-ctrl
On 20/12/2022 13:36, Bryan O'Donoghue wrote: > Deprecate qcom,dsi-ctrl-6g-qcm2290 in favour of the desired format > qcom,qcm2290-dsi-ctrl. > > Signed-off-by: Bryan O'Donoghue > --- > .../display/msm/dsi-controller-main.yaml | 36 +++ > 1 file changed, 21 insertions(+), 15 deletions(-) > > diff --git > a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > index 01afa9e9c4b3c..98d54a7ee28d4 100644 > --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > @@ -14,21 +14,27 @@ allOf: > > properties: >compatible: > -items: > - - enum: > - - qcom,apq8064-dsi-ctrl > - - qcom,msm8916-dsi-ctrl > - - qcom,msm8953-dsi-ctrl > - - qcom,msm8974-dsi-ctrl > - - qcom,msm8996-dsi-ctrl > - - qcom,msm8998-dsi-ctrl > - - qcom,dsi-ctrl-6g-qcm2290 > - - qcom,sc7180-dsi-ctrl > - - qcom,sc7280-dsi-ctrl > - - qcom,sdm660-dsi-ctrl > - - qcom,sdm845-dsi-ctrl > - - qcom,sm8250-dsi-ctrl > - - const: qcom,mdss-dsi-ctrl > +oneOf: > + - items: > + - enum: > + - qcom,apq8064-dsi-ctrl > + - qcom,msm8916-dsi-ctrl > + - qcom,msm8953-dsi-ctrl > + - qcom,msm8974-dsi-ctrl > + - qcom,msm8996-dsi-ctrl > + - qcom,msm8998-dsi-ctrl > + - qcom,qcm2290-dsi-ctrl > + - qcom,sc7180-dsi-ctrl > + - qcom,sc7280-dsi-ctrl > + - qcom,sdm660-dsi-ctrl > + - qcom,sdm845-dsi-ctrl > + - qcom,sm8250-dsi-ctrl > + - const: qcom,mdss-dsi-ctrl > + - items: I would just squash it with previous. You are adding some code and in next patch immediately: 1. re-indent it, 2. remove it (qcom,dsi-ctrl-6g-qcm2290) Best regards, Krzysztof
Re: [PATCH v5 06/21] dt-bindings: msm: dsi-controller-main: Document clocks on a per compatible basis
On 20/12/2022 13:36, Bryan O'Donoghue wrote: > Each compatible has a different set of clocks which are associated with it. > Add in the list of clocks for each compatible. > > Signed-off-by: Bryan O'Donoghue > --- > .../display/msm/dsi-controller-main.yaml | 189 +- > 1 file changed, 179 insertions(+), 10 deletions(-) > > diff --git > a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > index 98d54a7ee28d4..ce103e3ec4db3 100644 > --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml > @@ -9,9 +9,6 @@ title: Qualcomm Display DSI controller > maintainers: >- Krishna Manikandan > > -allOf: > - - $ref: "../dsi-controller.yaml#" > - > properties: >compatible: > oneOf: > @@ -55,13 +52,8 @@ properties: >- description: Display AXI clock > >clock-names: > -items: > - - const: byte > - - const: byte_intf > - - const: pixel > - - const: core > - - const: iface > - - const: bus > +minItems: 3 > +maxItems: 9 > >phys: > maxItems: 1 > @@ -157,6 +149,183 @@ required: >- assigned-clock-parents >- ports > > +allOf: > + - $ref: "../dsi-controller.yaml#" Drop the quotes. Add missing Ack. Acked-by: Krzysztof Kozlowski Best regards, Krzysztof
Re: [PATCH v5 07/21] dt-bindings: msm: dsi-controller-main: Fix clock declarations
On 20/12/2022 13:36, Bryan O'Donoghue wrote:
> When converting from .txt to .yaml dt-binding descriptions we appear to
> have missed some of the previous detail on the number and names of
> permissible clocks.
>
> Fix this by listing the clock descriptions against the clock names at a
> high level.
>
> Fixes: 4dbe55c97741 ("dt-bindings: msm: dsi: add yaml schemas for DSI
> bindings")
> Signed-off-by: Bryan O'Donoghue
> ---
I don't think this can be on its own. Clocks and clock-names go together
and your previous patch already changed from 6 to 3-9 entries. Splitting
these make them non-bisectable and confusing.
Best regards,
Krzysztof
Re: [PATCH v5 08/21] dt-bindings: msm: dsi-controller-main: Add vdd* descriptions back in
On 20/12/2022 13:36, Bryan O'Donoghue wrote:
> When converting from .txt to .yaml we didn't include descriptions for the
> existing regulator supplies.
>
> - vdd
> - vdda
> - vddio
>
> Add those descriptions into the yaml now as they were prior to the
> conversion. In the .txt description we marked these regulators as required,
> however, that requirement appears to have been in error.
>
> Taking the example of sc7180-trogdor-wormdingler.dtsi. The avdd and avee
> come from GPIO controlled external regulators, not the SoC and in this case
> there's no need for vddio to power an I/O bus. Similarly the regulators for
> the LCD are controlled by the panel driver not by the dsi-ctrl driver.
>
> It would be possible to connect a different type of panel to the DSI bus
> here in which case we may or may not want to make use of vdd, vdda or
> vddio.
>
> This is also the case for older chipsets like apq8064, msm8916 etc the vdd*
> regulators in the dsi-ctrl block are helpers not dependencies.
>
> Add the description of vdd, vdda and vddio back in for the existing
> upstream dts where vdd, vdda or vddio are already declared but, don't
> declare those regulators required - they are not SoC requirements.
>
> Fixes: 4dbe55c97741 ("dt-bindings: msm: dsi: add yaml schemas for DSI
> bindings")
> Signed-off-by: Bryan O'Donoghue
You got here ack, didn't you?
Best regards,
Krzysztof
Re: [PATCH v5 09/21] dt-bindings: display/msm: Add list of mdss-dsi-ctrl compats
On 20/12/2022 13:36, Bryan O'Donoghue wrote: > Add the list of current compats absent the deprecated qcm2290 to the list > of dsi compats listed here. > > Signed-off-by: Bryan O'Donoghue > --- > .../bindings/display/msm/qcom,mdss.yaml | 16 +++- > 1 file changed, 15 insertions(+), 1 deletion(-) > Is your patchset bisectable? That's second place where it looks like not. Best regards, Krzysztof
Re: [PATCH v5 10/21] dt-bindings: display/msm: Update MDSS dsi compat strings
On 20/12/2022 13:36, Bryan O'Donoghue wrote: > Several MDSS yaml files exist which document the dsi sub-node. > For each existing SoC MDSS yaml, provide the right dsi compat string. > > Signed-off-by: Bryan O'Donoghue Same concerns about bisectability. Best regards, Krzysztof
Re: [6.2][regression] looks like commit aab9cf7b6954136f4339136a1a7fc0602a2c4d8b leads to use-after-free and random computer hangs
Hi, this is your Linux kernel regression tracker. On 18.12.22 14:28, Mikhail Gavrilov wrote: > > The kernel 6.2 preparation cycle has begun. > And after the kernel was updated on my Fedora Rawhide I started > receiving use-after-free errors with complete computer hangs. > At least a good reproducer of this behaviour is launch of the game > "Marvel's Avengers". > > The backtrace of the issue looks like: > [...] Thx for your report. I'm not one of the developers for this area of the kernel, but to my untrained eyes it looks like this patch might fix your problem: https://lore.kernel.org/all/20221219104718.21677-1-christian.koe...@amd.com/ Anyway, to be sure the issue doesn't fall through the cracks unnoticed, I'm adding it to regzbot, my Linux kernel regression tracking bot: #regzbot ^introduced aab9cf7b695413 #regzbot title drm: amdgpu: use-after-free and random computer hangs #regzbot monitor: https://lore.kernel.org/all/20221219104718.21677-1-christian.koe...@amd.com/ #regzbot fix: drm/amdgpu: grab extra fence reference for drm_sched_job_add_dependency #regzbot ignore-activity Ciao, Thorsten (wearing his 'the Linux kernel's regression tracker' hat) P.S.: As the Linux kernel's regression tracker I deal with a lot of reports and sometimes miss something important when writing mails like this. If that's the case here, don't hesitate to tell me in a public reply, it's in everyone's interest to set the public record straight.
Re: [PATCH v5 05/21] dt-bindings: msm: dsi-controller-main: Deprecate qcom,dsi-ctrl-6g-qcm2290 in favour of qcom,qcm2290-dsi-ctrl
On 22/12/2022 11:50, Krzysztof Kozlowski wrote: On 20/12/2022 13:36, Bryan O'Donoghue wrote: Deprecate qcom,dsi-ctrl-6g-qcm2290 in favour of the desired format qcom,qcm2290-dsi-ctrl. Signed-off-by: Bryan O'Donoghue --- .../display/msm/dsi-controller-main.yaml | 36 +++ 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 01afa9e9c4b3c..98d54a7ee28d4 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -14,21 +14,27 @@ allOf: properties: compatible: -items: - - enum: - - qcom,apq8064-dsi-ctrl - - qcom,msm8916-dsi-ctrl - - qcom,msm8953-dsi-ctrl - - qcom,msm8974-dsi-ctrl - - qcom,msm8996-dsi-ctrl - - qcom,msm8998-dsi-ctrl - - qcom,dsi-ctrl-6g-qcm2290 - - qcom,sc7180-dsi-ctrl - - qcom,sc7280-dsi-ctrl - - qcom,sdm660-dsi-ctrl - - qcom,sdm845-dsi-ctrl - - qcom,sm8250-dsi-ctrl - - const: qcom,mdss-dsi-ctrl +oneOf: + - items: + - enum: + - qcom,apq8064-dsi-ctrl + - qcom,msm8916-dsi-ctrl + - qcom,msm8953-dsi-ctrl + - qcom,msm8974-dsi-ctrl + - qcom,msm8996-dsi-ctrl + - qcom,msm8998-dsi-ctrl + - qcom,qcm2290-dsi-ctrl + - qcom,sc7180-dsi-ctrl + - qcom,sc7280-dsi-ctrl + - qcom,sdm660-dsi-ctrl + - qcom,sdm845-dsi-ctrl + - qcom,sm8250-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + - items: I would just squash it with previous. You are adding some code and in next patch immediately: 1. re-indent it, 2. remove it (qcom,dsi-ctrl-6g-qcm2290) Best regards, Krzysztof Just to make sure. I'll squash this patch down in the previous and include your RB.
Re: [PATCH 18/19] linux/include: add non-atomic version of xchg
On Thu, Dec 22, 2022 at 12:46:34PM +0100, Andrzej Hajda wrote:
> The pattern of setting variable with new value and returning old
> one is very common in kernel. Usually atomicity of the operation
> is not required, so xchg seems to be suboptimal and confusing in
> such cases.
FWIW,
Reviewed-by: Andy Shevchenko
> Signed-off-by: Andrzej Hajda
> ---
> include/linux/non-atomic/xchg.h | 19 +++
> 1 file changed, 19 insertions(+)
> create mode 100644 include/linux/non-atomic/xchg.h
>
> diff --git a/include/linux/non-atomic/xchg.h b/include/linux/non-atomic/xchg.h
> new file mode 100644
> index 00..f7fa5dd746f37d
> --- /dev/null
> +++ b/include/linux/non-atomic/xchg.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef _LINUX_NON_ATOMIC_XCHG_H
> +#define _LINUX_NON_ATOMIC_XCHG_H
> +
> +/**
> + * __xchg - set variable pointed by @ptr to @val, return old value
> + * @ptr: pointer to affected variable
> + * @val: value to be written
> + *
> + * This is non-atomic variant of xchg.
> + */
> +#define __xchg(ptr, val) ({ \
> + __auto_type __ptr = ptr;\
> + __auto_type __t = *__ptr; \
> + *__ptr = (val); \
> + __t;\
> +})
> +
> +#endif
> --
> 2.34.1
>
--
With Best Regards,
Andy Shevchenko
Re: [Intel-gfx] [PATCH 1/3] drm/i915/guc: Fix missing return code checks in submission init
On 12/21/2022 8:30 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The CI results for the 'fast request' patch set (enables error return
codes for fire-and-forget H2G messages) hit an issue with the KMD
sending context submission requests on an invalid context. That was
caused by a fault injection probe failing the context creation of a
kernel context. However, there was no return code checking on any of
the kernel context registration paths. So the driver kept going and
tried to use the kernel context for the record defaults process.
Fix that by checking for errors and aborting as appropriate when
creating kernel contexts. While at it, clean up some other submission
init related failure cleanup paths. Also, rename guc_init_lrc_mapping
to guc_init_submission as the former name hasn't been valid in a long
time.
IMO we should specify that this isn't a bug in the current code. The
only way this can fail if we don't inject the failure is if the GuC is
dead and/or is not seeing our messages, in which case we'll eventually
correctly wedge. We only need this to get ready to switch to fast
request messages.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 74 ++-
.../gpu/drm/i915/gt/uc/intel_guc_submission.h | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 7 +-
3 files changed, 62 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 53f7f599cde3a..4682ec1dbd9c0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1431,21 +1431,25 @@ static int guc_action_enable_usage_stats(struct
intel_guc *guc)
return intel_guc_send(guc, action, ARRAY_SIZE(action));
}
-static void guc_init_engine_stats(struct intel_guc *guc)
+static int guc_init_engine_stats(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
intel_wakeref_t wakeref;
+ int ret;
mod_delayed_work(system_highpri_wq, &guc->timestamp.work,
guc->timestamp.ping_delay);
with_intel_runtime_pm(>->i915->runtime_pm, wakeref) {
- int ret = guc_action_enable_usage_stats(guc);
+ ret = guc_action_enable_usage_stats(guc);
- if (ret)
- drm_err(>->i915->drm,
- "Failed to enable usage stats: %d!\n", ret);
+ if (ret) {
+ cancel_delayed_work_sync(&guc->timestamp.work);
+ drm_err(>->i915->drm, "Failed to enable usage stats:
%d!\n", ret);
+ }
}
+
+ return ret;
}
void intel_guc_busyness_park(struct intel_gt *gt)
@@ -4101,9 +4105,11 @@ static void guc_set_default_submission(struct
intel_engine_cs *engine)
engine->submit_request = guc_submit_request;
}
-static inline void guc_kernel_context_pin(struct intel_guc *guc,
- struct intel_context *ce)
+static inline int guc_kernel_context_pin(struct intel_guc *guc,
+struct intel_context *ce)
{
+ int ret;
+
/*
* Note: we purposefully do not check the returns below because
* the registration can only fail if a reset is just starting.
@@ -4111,16 +4117,24 @@ static inline void guc_kernel_context_pin(struct
intel_guc *guc,
* isn't happening and even it did this code would be run again.
*/
- if (context_guc_id_invalid(ce))
- pin_guc_id(guc, ce);
+ if (context_guc_id_invalid(ce)) {
+ int ret = pin_guc_id(guc, ce);
+
+ if (ret < 0)
+ return ret;
+ }
if (!test_bit(CONTEXT_GUC_INIT, &ce->flags))
guc_context_init(ce);
- try_context_registration(ce, true);
+ ret = try_context_registration(ce, true);
+ if (ret)
+ unpin_guc_id(guc, ce);
+
+ return ret;
}
-static inline void guc_init_lrc_mapping(struct intel_guc *guc)
+static inline int guc_init_submission(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
struct intel_engine_cs *engine;
@@ -4147,9 +4161,17 @@ static inline void guc_init_lrc_mapping(struct intel_guc
*guc)
struct intel_context *ce;
list_for_each_entry(ce, &engine->pinned_contexts_list,
- pinned_contexts_link)
- guc_kernel_context_pin(guc, ce);
+ pinned_contexts_link) {
+ int ret = guc_kernel_context_pin(guc, ce);
+
+ if (ret) {
+ /* No point in trying to clean up as i915 will
wedge on failure */
+ return ret;
+ }
nit: no need for {} here
+ }
}
Re: [PATCH 2/3] drm/i915/guc: Fix a static analysis warning
Reviewed-by: Daniele Ceraolo Spurio Daniele On 12/21/2022 8:30 PM, john.c.harri...@intel.com wrote: From: John Harrison A static analyser was complaining about not checking for null pointers. However, the location of the complaint can only be reached in the first place if said pointer is non-null. Basically, if we are using a v69 GuC then the descriptor pool is guaranteed to be alocated at start of day or submission will be disabled with an ENOMEM error. And if we are using a later GuC that does not use a descriptor pool then the v69 submission function would not be called. So, not a possible null at that point in the code. Hence adding a GEM_BUG_ON(!ptr) to keep the tool happy. Signed-off-by: John Harrison --- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 4682ec1dbd9c0..c93d0594bfd5e 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -2538,6 +2538,7 @@ static void prepare_context_registration_info_v69(struct intel_context *ce) i915_gem_object_is_lmem(ce->ring->vma->obj)); desc = __get_lrc_desc_v69(guc, ctx_id); + GEM_BUG_ON(!desc); desc->engine_class = engine_class_to_guc_class(engine->class); desc->engine_submit_mask = engine->logical_mask; desc->hw_context_desc = ce->lrc.lrca;
Re: [Intel-gfx] [PATCH] drm/i915/gt: Reset twice
Hi GG,
> > > > > > > drivers/gpu/drm/i915/gt/intel_reset.c | 34
> > > > > > > ++-
> > > > > > > 1 file changed, 28 insertions(+), 6 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> > > > > > > b/drivers/gpu/drm/i915/gt/intel_reset.c
> > > > > > > index ffde89c5835a4..88dfc0c5316ff 100644
> > > > > > > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> > > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> > > > > > > @@ -268,6 +268,7 @@ static int ilk_do_reset(struct intel_gt *gt,
> > > > > > > intel_engine_mask_t engine_mask,
> > > > > > > static int gen6_hw_domain_reset(struct intel_gt *gt, u32
> > > > > > > hw_domain_mask)
> > > > > > > {
> > > > > > > struct intel_uncore *uncore = gt->uncore;
> > > > > > > + int loops = 2;
> > > > > > > int err;
> > > > > > > /*
> > > > > > > @@ -275,18 +276,39 @@ static int gen6_hw_domain_reset(struct
> > > > > > > intel_gt *gt, u32 hw_domain_mask)
> > > > > > > * for fifo space for the write or forcewake the chip for
> > > > > > > * the read
> > > > > > > */
> > > > > > > - intel_uncore_write_fw(uncore, GEN6_GDRST,
> > > > > > > hw_domain_mask);
> > > > > > > + do {
> > > > > > > + intel_uncore_write_fw(uncore, GEN6_GDRST,
> > > > > > > hw_domain_mask);
> > > > > > > - /* Wait for the device to ack the reset requests */
> > > > > > > - err = __intel_wait_for_register_fw(uncore,
> > > > > > > - GEN6_GDRST,
> > > > > > > hw_domain_mask, 0,
> > > > > > > - 500, 0,
> > > > > > > - NULL);
> > > > > > > + /*
> > > > > > > + * Wait for the device to ack the reset requests.
> > > > > > > + *
> > > > > > > + * On some platforms, e.g. Jasperlake, we see see
> > > > > > > that the
> > > > > > > + * engine register state is not cleared until
> > > > > > > shortly after
> > > > > > > + * GDRST reports completion, causing a failure as
> > > > > > > we try
> > > > > > > + * to immediately resume while the internal state
> > > > > > > is still
> > > > > > > + * in flux. If we immediately repeat the reset,
> > > > > > > the second
> > > > > > > + * reset appears to serialise with the first, and
> > > > > > > since
> > > > > > > + * it is a no-op, the registers should retain
> > > > > > > their reset
> > > > > > > + * value. However, there is still a concern that
> > > > > > > upon
> > > > > > > + * leaving the second reset, the internal engine
> > > > > > > state
> > > > > > > + * is still in flux and not ready for resuming.
> > > > > > > + */
> > > > > > > + err = __intel_wait_for_register_fw(uncore,
> > > > > > > GEN6_GDRST,
> > > > > > > +
> > > > > > > hw_domain_mask, 0,
> > > > > > > + 2000, 0,
> > > > > > > + NULL);
> Andi, fast_timeout_us is increased from 500 to 2000, and if it fails, it
> tries to reset it once more. How was this value of 2000 calculated?
No real reason, it's just an empiric choice to make the call a
bit more robust and suffer less from delayed feedback.
> > > > > > > + } while (err == 0 && --loops);
> > > > > > > if (err)
> > > > > > > GT_TRACE(gt,
> > > > > > > "Wait for 0x%08x engines reset
> > > > > > > failed\n",
> > > > > > > hw_domain_mask);
> Did GT_TRACE report an error in a situation where the problem was reported?
I guess so, in Jasperlake.
> > > > > > > + /*
> > > > > > > + * As we have observed that the engine state is still
> > > > > > > volatile
> > > > > > > + * after GDRST is acked, impose a small delay to let
> > > > > > > everything settle.
> > > > > > > + */
> > > > > > > + udelay(50);
> udelay(50) affects all platforms that can call gen6_hw_domain_reset(), is
> that intended?
Yes, that's intended as apparently we need to give it a bit more
time for the engines to recover from the reset. We are here in
atomic context and we need udelay to wait atomically, thus
udelay().
Thank you,
Andi
Re: [PATCH 00/19] Introduce __xchg, non-atomic xchg
Hi Andrzej,
Thanks for your series!
On Thu, Dec 22, 2022 at 12:49 PM Andrzej Hajda wrote:
> I hope there will be place for such tiny helper in kernel.
> Quick cocci analyze shows there is probably few thousands places
> where it could be useful.
> I am not sure who is good person to review/ack such patches,
> so I've used my intuition to construct to/cc lists, sorry for mistakes.
> This is the 2nd approach of the same idea, with comments addressed[0].
>
> The helper is tiny and there are advices we can leave without it, so
> I want to present few arguments why it would be good to have it:
>
> 1. Code readability/simplification/number of lines:
>
> Real example from drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c:
> - previous_min_rate = evport->qos.min_rate;
> - evport->qos.min_rate = min_rate;
> + previous_min_rate = __xchg(evport->qos.min_rate, min_rate);
Upon closer look, shouldn't that be
previous_min_rate = __xchg(&evport->qos.min_rate, min_rate);
?
> For sure the code is more compact, and IMHO more readable.
>
> 2. Presence of similar helpers in other somehow related languages/libs:
>
> a) Rust[1]: 'replace' from std::mem module, there is also 'take'
> helper (__xchg(&x, 0)), which is the same as private helper in
> i915 - fetch_and_zero, see latest patch.
> b) C++ [2]: 'exchange' from utility header.
>
> If the idea is OK there are still 2 qestions to answer:
>
> 1. Name of the helper, __xchg follows kernel conventions,
> but for me Rust names are also OK.
Before I realized the missing "&", I wondered how this is different
from swap(), so naming is important.
https://elixir.bootlin.com/linux/latest/source/include/linux/minmax.h#L139
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 00/19] Introduce __xchg, non-atomic xchg
On 22.12.2022 15:12, Geert Uytterhoeven wrote:
Hi Andrzej,
Thanks for your series!
On Thu, Dec 22, 2022 at 12:49 PM Andrzej Hajda wrote:
I hope there will be place for such tiny helper in kernel.
Quick cocci analyze shows there is probably few thousands places
where it could be useful.
I am not sure who is good person to review/ack such patches,
so I've used my intuition to construct to/cc lists, sorry for mistakes.
This is the 2nd approach of the same idea, with comments addressed[0].
The helper is tiny and there are advices we can leave without it, so
I want to present few arguments why it would be good to have it:
1. Code readability/simplification/number of lines:
Real example from drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c:
- previous_min_rate = evport->qos.min_rate;
- evport->qos.min_rate = min_rate;
+ previous_min_rate = __xchg(evport->qos.min_rate, min_rate);
Upon closer look, shouldn't that be
previous_min_rate = __xchg(&evport->qos.min_rate, min_rate);
?
Yes, you are right, the first argument is a pointer.
Regards
Andrzej
For sure the code is more compact, and IMHO more readable.
2. Presence of similar helpers in other somehow related languages/libs:
a) Rust[1]: 'replace' from std::mem module, there is also 'take'
helper (__xchg(&x, 0)), which is the same as private helper in
i915 - fetch_and_zero, see latest patch.
b) C++ [2]: 'exchange' from utility header.
If the idea is OK there are still 2 qestions to answer:
1. Name of the helper, __xchg follows kernel conventions,
but for me Rust names are also OK.
Before I realized the missing "&", I wondered how this is different
from swap(), so naming is important.
https://elixir.bootlin.com/linux/latest/source/include/linux/minmax.h#L139
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH v6 01/17] dt-bindings: display: rockchip: convert rockchip-lvds.txt to YAML
Convert rockchip-lvds.txt to YAML.
Changed:
Add power-domains property.
Requirements between PX30 and RK3288
Signed-off-by: Johan Jonker
Reviewed-by: Rob Herring
---
Changed V3:
Filename matching compatible style
Drop "Regulator phandle for "
Specify properties and requirements per SoC
Sort order and restyle
Changed V2:
Fix title
---
.../display/rockchip/rockchip,lvds.yaml | 170 ++
.../display/rockchip/rockchip-lvds.txt| 92 --
2 files changed, 170 insertions(+), 92 deletions(-)
create mode 100644
Documentation/devicetree/bindings/display/rockchip/rockchip,lvds.yaml
delete mode 100644
Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
diff --git
a/Documentation/devicetree/bindings/display/rockchip/rockchip,lvds.yaml
b/Documentation/devicetree/bindings/display/rockchip/rockchip,lvds.yaml
new file mode 100644
index 0..03b002a05
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,lvds.yaml
@@ -0,0 +1,170 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/rockchip/rockchip,lvds.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip low-voltage differential signal (LVDS) transmitter
+
+maintainers:
+ - Sandy Huang
+ - Heiko Stuebner
+
+properties:
+ compatible:
+enum:
+ - rockchip,px30-lvds
+ - rockchip,rk3288-lvds
+
+ reg:
+maxItems: 1
+
+ clocks:
+maxItems: 1
+
+ clock-names:
+const: pclk_lvds
+
+ avdd1v0-supply:
+description: 1.0V analog power.
+
+ avdd1v8-supply:
+description: 1.8V analog power.
+
+ avdd3v3-supply:
+description: 3.3V analog power.
+
+ rockchip,grf:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: Phandle to the general register files syscon.
+
+ rockchip,output:
+$ref: /schemas/types.yaml#/definitions/string
+enum: [rgb, lvds, duallvds]
+description: This describes the output interface.
+
+ phys:
+maxItems: 1
+
+ phy-names:
+const: dphy
+
+ pinctrl-names:
+const: lcdc
+
+ pinctrl-0: true
+
+ power-domains:
+maxItems: 1
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+ port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ Video port 0 for the VOP input.
+ The remote endpoint maybe vopb or vopl.
+
+ port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ Video port 1 for either a panel or subsequent encoder.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - rockchip,grf
+ - rockchip,output
+ - ports
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+const: rockchip,px30-lvds
+
+then:
+ properties:
+reg: false
+clocks: false
+clock-names: false
+avdd1v0-supply: false
+avdd1v8-supply: false
+avdd3v3-supply: false
+
+ required:
+- phys
+- phy-names
+
+ - if:
+ properties:
+compatible:
+ contains:
+const: rockchip,rk3288-lvds
+
+then:
+ properties:
+phys: false
+phy-names: false
+
+ required:
+- reg
+- clocks
+- clock-names
+- avdd1v0-supply
+- avdd1v8-supply
+- avdd3v3-supply
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+lvds: lvds@ff96c000 {
+ compatible = "rockchip,rk3288-lvds";
+ reg = <0xff96c000 0x4000>;
+ clocks = <&cru PCLK_LVDS_PHY>;
+ clock-names = "pclk_lvds";
+ avdd1v0-supply = <&vdd10_lcd>;
+ avdd1v8-supply = <&vcc18_lcd>;
+ avdd3v3-supply = <&vcca_33>;
+ pinctrl-names = "lcdc";
+ pinctrl-0 = <&lcdc_ctl>;
+ rockchip,grf = <&grf>;
+ rockchip,output = "rgb";
+
+ ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+lvds_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lvds_in_vopb: endpoint@0 {
+reg = <0>;
+remote-endpoint = <&vopb_out_lvds>;
+ };
+ lvds_in_vopl: endpoint@1 {
+reg = <1>;
+remote-endpoint = <&vopl_out_lvds>;
+ };
+};
+
+lvds_out: port@1 {
+ reg = <1>;
+
+ lvds_out_panel: endpoint {
+remote-endpoint = <&panel_in_lvds>;
+ };
+};
+ };
+};
diff --git
a/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
b/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
deleted file mode 100644
index aaf8c44cf..0
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
+++ /dev/null
@@ -1,92 +0,0 @@
-Rockchip RK3288 LVDS interface
-
-
-Required properties:
-- compatible: matching the soc type, one o
[PATCH v6 02/17] dt-bindings: soc: rockchip: grf: add rockchip,lvds.yaml
Add new converted rockchip,lvds.yaml to grf.yaml file. Prepare for more SoCs with lvds output. Signed-off-by: Johan Jonker Reviewed-by: Rob Herring --- Changed V5: Drop the quotes --- .../devicetree/bindings/soc/rockchip/grf.yaml | 24 +++ 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 2ed8cca79..7ac9aa5fa 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -75,13 +75,17 @@ allOf: properties: compatible: contains: -const: rockchip,px30-grf +enum: + - rockchip,px30-grf then: properties: lvds: - description: - Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt + type: object + + $ref: /schemas/display/rockchip/rockchip,lvds.yaml# + + unevaluatedProperties: false - if: properties: @@ -109,7 +113,7 @@ allOf: usbphy: type: object - $ref: "/schemas/phy/rockchip-usb-phy.yaml#" + $ref: /schemas/phy/rockchip-usb-phy.yaml# unevaluatedProperties: false @@ -124,14 +128,14 @@ allOf: gpio: type: object - $ref: "/schemas/gpio/rockchip,rk3328-grf-gpio.yaml#" + $ref: /schemas/gpio/rockchip,rk3328-grf-gpio.yaml# unevaluatedProperties: false power-controller: type: object - $ref: "/schemas/power/rockchip,power-controller.yaml#" + $ref: /schemas/power/rockchip,power-controller.yaml# unevaluatedProperties: false @@ -146,7 +150,7 @@ allOf: mipi-dphy-rx0: type: object - $ref: "/schemas/phy/rockchip-mipi-dphy-rx0.yaml#" + $ref: /schemas/phy/rockchip-mipi-dphy-rx0.yaml# unevaluatedProperties: false @@ -174,7 +178,7 @@ allOf: reboot-mode: type: object - $ref: "/schemas/power/reset/syscon-reboot-mode.yaml#" + $ref: /schemas/power/reset/syscon-reboot-mode.yaml# unevaluatedProperties: false @@ -200,7 +204,7 @@ allOf: "usb2phy@[0-9a-f]+$": type: object - $ref: "/schemas/phy/phy-rockchip-inno-usb2.yaml#" + $ref: /schemas/phy/phy-rockchip-inno-usb2.yaml# unevaluatedProperties: false @@ -228,7 +232,7 @@ allOf: io-domains: type: object - $ref: "/schemas/power/rockchip-io-domain.yaml#" + $ref: /schemas/power/rockchip-io-domain.yaml# unevaluatedProperties: false -- 2.20.1
[PATCH v6 03/17] dt-bindings: display: dsi-controller: move clock-master property
The clock-master property is used for the controller and not in the panel, so move it there. Signed-off-by: Johan Jonker --- .../bindings/display/dsi-controller.yaml | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/display/dsi-controller.yaml b/Documentation/devicetree/bindings/display/dsi-controller.yaml index ca21671f6..67ce10307 100644 --- a/Documentation/devicetree/bindings/display/dsi-controller.yaml +++ b/Documentation/devicetree/bindings/display/dsi-controller.yaml @@ -30,6 +30,15 @@ properties: $nodename: pattern: "^dsi(@.*)?$" + clock-master: +type: boolean +description: + Should be enabled if the host is being used in conjunction with + another DSI host to drive the same peripheral. Hardware supporting + such a configuration generally requires the data on both the busses + to be driven by the same clock. Only the DSI host instance + controlling this clock should contain this property. + "#address-cells": const: 1 @@ -52,15 +61,6 @@ patternProperties: case the reg property can take multiple entries, one for each virtual channel that the peripheral responds to. - clock-master: -type: boolean -description: - Should be enabled if the host is being used in conjunction with - another DSI host to drive the same peripheral. Hardware supporting - such a configuration generally requires the data on both the busses - to be driven by the same clock. Only the DSI host instance - controlling this clock should contain this property. - enforce-video-mode: type: boolean description: -- 2.20.1
[PATCH v6 04/17] dt-bindings: display: bridge: snps, dw-mipi-dsi: fix clock properties
Fix clock properties from the common snps,dw-mipi-dsi.yaml file, as they don't match with what is used on the SoCs. Signed-off-by: Johan Jonker Reviewed-by: Rob Herring --- .../display/bridge/snps,dw-mipi-dsi.yaml | 16 +++- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml index 11fd68a70..0b51c64f1 100644 --- a/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml @@ -26,19 +26,9 @@ properties: reg: maxItems: 1 - clocks: -items: - - description: Module clock - - description: DSI bus clock for either AHB and APB - - description: Pixel clock for the DPI/RGB input -minItems: 2 - - clock-names: -items: - - const: ref - - const: pclk - - const: px_clk -minItems: 2 + clocks: true + + clock-names: true resets: maxItems: 1 -- 2.20.1
[PATCH v6 05/17] dt-bindings: display: rockchip: convert dw_mipi_dsi_rockchip.txt to yaml
Convert dw_mipi_dsi_rockchip.txt to yaml.
Changed:
file name
requirements
Signed-off-by: Johan Jonker
---
Changed V6:
Remove clock-master property
Fix $ref
---
.../display/rockchip/dw_mipi_dsi_rockchip.txt | 94 --
.../rockchip/rockchip,dw-mipi-dsi.yaml| 166 ++
2 files changed, 166 insertions(+), 94 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
create mode 100644
Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml
diff --git
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
deleted file mode 100644
index 9a223df85..0
---
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ /dev/null
@@ -1,94 +0,0 @@
-Rockchip specific extensions to the Synopsys Designware MIPI DSI
-
-
-Required properties:
-- #address-cells: Should be <1>.
-- #size-cells: Should be <0>.
-- compatible: one of
- "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
- "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
- "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
- "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"
-- reg: Represent the physical address range of the controller.
-- interrupts: Represent the controller's interrupt to the CPU(s).
-- clocks, clock-names: Phandles to the controller's pll reference
- clock(ref) when using an internal dphy and APB clock(pclk).
- For RK3399, a phy config clock (phy_cfg) and a grf clock(grf)
- are required. As described in [1].
-- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
-- ports: contain a port node with endpoint definitions as defined in [2].
- For vopb,set the reg = <0> and set the reg = <1> for vopl.
-- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
-- video port 1 for either a panel or subsequent encoder
-
-Optional properties:
-- phys: from general PHY binding: the phandle for the PHY device.
-- phy-names: Should be "dphy" if phys references an external phy.
-- #phy-cells: Defined when used as ISP phy, should be 0.
-- power-domains: a phandle to mipi dsi power domain node.
-- resets: list of phandle + reset specifier pairs, as described in [3].
-- reset-names: string reset name, must be "apb".
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/media/video-interfaces.txt
-[3] Documentation/devicetree/bindings/reset/reset.txt
-
-Example:
- mipi_dsi: mipi@ff96 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
- reg = <0xff96 0x4000>;
- interrupts = ;
- clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
- clock-names = "ref", "pclk";
- resets = <&cru SRST_MIPIDSI0>;
- reset-names = "apb";
- rockchip,grf = <&grf>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi_in: port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi_in_vopb: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vopb_out_mipi>;
- };
- mipi_in_vopl: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vopl_out_mipi>;
- };
- };
-
- mipi_out: port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi_out_panel: endpoint {
- remote-endpoint = <&panel_in_mipi>;
- };
- };
- };
-
- panel {
- compatible ="boe,tv080wum-nl0";
- reg = <0>;
-
- enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&lcd_en>;
- backlight = <&backlight>;
-
- port {
- panel_in_mipi: endpoint {
- remote-endpoint = <&mipi_out_panel>;
- };
- };
- };
- };
diff --git
a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml
b/Documentati
[PATCH v6 06/17] dt-bindings: display: bridge: convert analogix_dp.txt to yaml
Convert analogix_dp.txt to yaml for use as common document.
Changed:
Relexed requirements
Signed-off-by: Johan Jonker
---
.../bindings/display/bridge/analogix,dp.yaml | 63 +++
.../bindings/display/bridge/analogix_dp.txt | 51 ---
.../bindings/display/exynos/exynos_dp.txt | 2 +-
3 files changed, 64 insertions(+), 52 deletions(-)
create mode 100644
Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml
delete mode 100644
Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml
b/Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml
new file mode 100644
index 0..c9b06885c
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/analogix,dp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analogix Display Port bridge
+
+maintainers:
+ - Rob Herring
+
+properties:
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks: true
+
+ clock-names: true
+
+ phys: true
+
+ phy-names:
+const: dp
+
+ force-hpd:
+description:
+ Indicate driver need force hpd when hpd detect failed, this
+ is used for some eDP screen which don not have a hpd signal.
+
+ hpd-gpios:
+description:
+ Hotplug detect GPIO.
+ Indicates which GPIO should be used for hotplug detection
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+ port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ Input node to receive pixel data.
+
+ port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ Port node with one endpoint connected to a dp-connector node.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - reg
+ - interrupts
+ - clock-names
+ - clocks
+ - ports
+
+additionalProperties: true
diff --git a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
deleted file mode 100644
index 027d76c27..0
--- a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
+++ /dev/null
@@ -1,51 +0,0 @@
-Analogix Display Port bridge bindings
-
-Required properties for dp-controller:
- -compatible:
- platform specific such as:
-* "samsung,exynos5-dp"
-* "rockchip,rk3288-dp"
-* "rockchip,rk3399-edp"
- -reg:
- physical base address of the controller and length
- of memory mapped region.
- -interrupts:
- interrupt combiner values.
- -clocks:
- from common clock binding: handle to dp clock.
- -clock-names:
- from common clock binding: Shall be "dp".
- -phys:
- from general PHY binding: the phandle for the PHY device.
- -phy-names:
- from general PHY binding: Should be "dp".
-
-Optional properties for dp-controller:
- -force-hpd:
- Indicate driver need force hpd when hpd detect failed, this
- is used for some eDP screen which don't have hpd signal.
- -hpd-gpios:
- Hotplug detect GPIO.
- Indicates which GPIO should be used for hotplug detection
- -port@[X]: SoC specific port nodes with endpoint definitions as defined
- in Documentation/devicetree/bindings/media/video-interfaces.txt,
- please refer to the SoC specific binding document:
- * Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
- *
Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
-
-[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
-
-Example:
-
- dp-controller {
- compatible = "samsung,exynos5-dp";
- reg = <0x145b 0x1>;
- interrupts = <10 3>;
- interrupt-parent = <&combiner>;
- clocks = <&clock 342>;
- clock-names = "dp";
-
- phys = <&dp_phy>;
- phy-names = "dp";
- };
diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
index 9b6cba3f8..3a4015903 100644
--- a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
@@ -50,7 +50,7 @@ Optional properties for dp-controller:
Documentation/devicetree/bindings/display/panel/display-timing.txt
For the below properties, please refer to Analogix DP binding document:
- * Documentation/devicetree/bi
[PATCH v6 07/17] dt-bindings: display: rockchip: convert analogix_dp-rockchip.txt to yaml
Convert analogix_dp-rockchip.txt to yaml.
Changed:
Add power-domains property
File name
Signed-off-by: Johan Jonker
---
.../display/rockchip/analogix_dp-rockchip.txt | 98 -
.../rockchip/rockchip,analogix-dp.yaml| 103 ++
2 files changed, 103 insertions(+), 98 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
create mode 100644
Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
diff --git
a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
deleted file mode 100644
index 43561584c..0
---
a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
+++ /dev/null
@@ -1,98 +0,0 @@
-Rockchip RK3288 specific extensions to the Analogix Display Port
-
-
-Required properties:
-- compatible: "rockchip,rk3288-dp",
- "rockchip,rk3399-edp";
-
-- reg: physical base address of the controller and length
-
-- clocks: from common clock binding: handle to dp clock.
- of memory mapped region.
-
-- clock-names: from common clock binding:
- Required elements: "dp" "pclk"
-
-- resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-
-- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
-- pinctrl-0: pin-control mode. should be <&edp_hpd>
-
-- reset-names: Must include the name "dp"
-
-- rockchip,grf: this soc should set GRF regs, so need get grf here.
-
-- ports: there are 2 port nodes with endpoint definitions as defined in
- Documentation/devicetree/bindings/media/video-interfaces.txt.
-Port 0: contained 2 endpoints, connecting to the output of vop.
-Port 1: contained 1 endpoint, connecting to the input of panel.
-
-Optional property for different chips:
-- clocks: from common clock binding: handle to grf_vio clock.
-
-- clock-names: from common clock binding:
- Required elements: "grf"
-
-For the below properties, please refer to Analogix DP binding document:
- * Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
-- phys (required)
-- phy-names (required)
-- hpd-gpios (optional)
-- force-hpd (optional)
-
-Example:
- dp-controller: dp@ff97 {
- compatible = "rockchip,rk3288-dp";
- reg = <0xff97 0x4000>;
- interrupts = ;
- clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
- clock-names = "dp", "pclk";
- phys = <&dp_phy>;
- phy-names = "dp";
-
- rockchip,grf = <&grf>;
- resets = <&cru 111>;
- reset-names = "dp";
-
- pinctrl-names = "default";
- pinctrl-0 = <&edp_hpd>;
-
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- edp_in: port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- edp_in_vopb: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vopb_out_edp>;
- };
- edp_in_vopl: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&vopl_out_edp>;
- };
- };
-
- edp_out: port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- edp_out_panel: endpoint {
- reg = <0>;
- remote-endpoint = <&panel_in_edp>
- };
- };
- };
- };
-
- pinctrl {
- edp {
- edp_hpd: edp-hpd {
- rockchip,pins = <7 11 RK_FUNC_2
&pcfg_pull_none>;
- };
- };
- };
diff --git
a/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
new file mode 100644
index 0..60dedf9b2
--- /dev/null
+++
b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/rockchip/rockchip,analogix-dp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip speci
[PATCH v6 08/17] dt-bindings: usb: convert fcs,fusb302.txt to yaml
Convert fcs,fusb302.txt to yaml.
Changed:
Add vbus-supply property
Signed-off-by: Johan Jonker
---
Changed V6:
Add unevaluatedProperties
Drop unused labels
---
.../devicetree/bindings/usb/fcs,fusb302.txt | 34 --
.../devicetree/bindings/usb/fcs,fusb302.yaml | 67 +++
2 files changed, 67 insertions(+), 34 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/usb/fcs,fusb302.txt
create mode 100644 Documentation/devicetree/bindings/usb/fcs,fusb302.yaml
diff --git a/Documentation/devicetree/bindings/usb/fcs,fusb302.txt
b/Documentation/devicetree/bindings/usb/fcs,fusb302.txt
deleted file mode 100644
index 60e465429..0
--- a/Documentation/devicetree/bindings/usb/fcs,fusb302.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-Fairchild FUSB302 Type-C Port controllers
-
-Required properties :
-- compatible : "fcs,fusb302"
-- reg: I2C slave address
-- interrupts : Interrupt specifier
-
-Required sub-node:
-- connector : The "usb-c-connector" attached to the FUSB302 IC. The bindings
- of the connector node are specified in:
-
- Documentation/devicetree/bindings/connector/usb-connector.yaml
-
-
-Example:
-
-fusb302: typec-portc@54 {
- compatible = "fcs,fusb302";
- reg = <0x54>;
- interrupt-parent = <&nmi_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-
- usb_con: connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- power-role = "dual";
- try-power-role = "sink";
- source-pdos = ;
- sink-pdos = ;
- op-sink-microwatt = <1000>;
- };
-};
diff --git a/Documentation/devicetree/bindings/usb/fcs,fusb302.yaml
b/Documentation/devicetree/bindings/usb/fcs,fusb302.yaml
new file mode 100644
index 0..b396ea0ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/fcs,fusb302.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/fcs,fusb302.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Fairchild FUSB302 Type-C Port controller
+
+maintainers:
+ - Rob Herring
+
+properties:
+ compatible:
+const: fcs,fusb302
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ vbus-supply:
+description: VBUS power supply
+
+ connector:
+type: object
+$ref: /schemas/connector/usb-connector.yaml#
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - vbus-supply
+ - connector
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ typec-portc@54 {
+compatible = "fcs,fusb302";
+reg = <0x54>;
+interrupt-parent = <&nmi_intc>;
+interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+vbus-supply = <&vbus_typec>;
+
+connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ try-power-role = "sink";
+ source-pdos = ;
+ sink-pdos = ;
+ op-sink-microwatt = <1000>;
+};
+ };
+};
--
2.20.1
[PATCH v6 09/17] ARM: dts: rockchip: rk3288: fix dsi node
Use generic node name for rk3288.dtsi dsi node.
With the conversion of rockchip,dw-mipi-dsi.yaml a port@1 node
is required, so add a node with label mipi_out.
Also restyle.
Signed-off-by: Johan Jonker
---
Changed V6:
Restyle
---
arch/arm/boot/dts/rk3288.dtsi | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 487b0e03d..fbb174729 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -1114,7 +1114,7 @@
status = "disabled";
};
- mipi_dsi: mipi@ff96 {
+ mipi_dsi: dsi@ff96 {
compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff96 0x0 0x4000>;
interrupts = ;
@@ -1125,18 +1125,28 @@
status = "disabled";
ports {
- mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_in: port@0 {
+ reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
+
mipi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_mipi>;
};
+
mipi_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_mipi>;
};
};
+
+ mipi_out: port@1 {
+ reg = <1>;
+ };
};
};
--
2.20.1
[PATCH v6 10/17] ARM: dts: rockchip: rk3288: fix lvds node
With the conversion of rockchip,lvds.yaml a port@1 node
is required, so add a node with label lvds_out.
Also restyle.
Signed-off-by: Johan Jonker
---
Changed V6:
Restyle
Changed V5:
Rename title
---
arch/arm/boot/dts/rk3288.dtsi | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index fbb174729..9def3988e 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -1167,7 +1167,6 @@
lvds_in: port@0 {
reg = <0>;
-
#address-cells = <1>;
#size-cells = <0>;
@@ -1175,11 +1174,16 @@
reg = <0>;
remote-endpoint = <&vopb_out_lvds>;
};
+
lvds_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_lvds>;
};
};
+
+ lvds_out: port@1 {
+ reg = <1>;
+ };
};
};
--
2.20.1
[PATCH v6 11/17] ARM: dts: rockchip: rk3288: fix dp node
With the conversion of rockchip,analogix-dp.yaml a port@1 node
is required, so add a node with label edp_out.
Also restyle.
Signed-off-by: Johan Jonker
---
arch/arm/boot/dts/rk3288.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 9def3988e..4d1bc6784 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -1203,19 +1203,26 @@
ports {
#address-cells = <1>;
#size-cells = <0>;
+
edp_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
+
edp_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_edp>;
};
+
edp_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_edp>;
};
};
+
+ edp_out: port@1 {
+ reg = <1>;
+ };
};
};
--
2.20.1
[PATCH v6 12/17] arm64: dts: rockchip: px30: fix lvds node
With the conversion of rockchip,lvds.yaml a port@1 node
is required, so add a node with label lvds_out.
Also add label lvds_in to port@0.
Signed-off-by: Johan Jonker
---
Changed V5:
rename title
add label lvds_in
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi
b/arch/arm64/boot/dts/rockchip/px30.dtsi
index bfa358042..e34d81f29 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -453,7 +453,7 @@
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
+ lvds_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
@@ -468,6 +468,10 @@
remote-endpoint =
<&vopl_out_lvds>;
};
};
+
+ lvds_out: port@1 {
+ reg = <1>;
+ };
};
};
};
--
2.20.1
[PATCH v6 13/17] arm64: dts: rockchip: px30: fix dsi node
With the conversion of rockchip,dw-mipi-dsi.yaml a port@1 node
is required, so add a node with label dsi_out.
Also add label dsi_in to port@0.
Signed-off-by: Johan Jonker
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi
b/arch/arm64/boot/dts/rockchip/px30.dtsi
index e34d81f29..272b01154 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -1117,7 +1117,7 @@
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
+ dsi_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1132,6 +1132,10 @@
remote-endpoint = <&vopl_out_dsi>;
};
};
+
+ dsi_out: port@1 {
+ reg = <1>;
+ };
};
};
--
2.20.1
[PATCH v6 14/17] arm64: dts: rockchip: rk3399: fix dsi node
Use generic node name for rk3399.dtsi dsi node.
With the conversion of rockchip,dw-mipi-dsi.yaml a port@1 node
is required, so add a node with label mipi_out.
Also restyle.
Signed-off-by: Johan Jonker
---
Changed V6:
Restyle
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 834d16acb..2250533cf 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1954,7 +1954,7 @@
};
};
- mipi_dsi: mipi@ff96 {
+ mipi_dsi: dsi@ff96 {
compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff96 0x0 0x8000>;
interrupts = ;
@@ -1982,15 +1982,20 @@
reg = <0>;
remote-endpoint = <&vopb_out_mipi>;
};
+
mipi_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_mipi>;
};
};
+
+ mipi_out: port@1 {
+ reg = <1>;
+ };
};
};
- mipi_dsi1: mipi@ff968000 {
+ mipi_dsi1: dsi@ff968000 {
compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff968000 0x0 0x8000>;
interrupts = ;
@@ -2025,6 +2030,10 @@
remote-endpoint = <&vopl_out_mipi1>;
};
};
+
+ mipi1_out: port@1 {
+ reg = <1>;
+ };
};
};
--
2.20.1
[PATCH v6 15/17] arm64: dts: rockchip: rk3399: fix dp node
Use generic node name for rk3399.dtsi dp node.
With the conversion of rockchip,analogix-dp.yaml a port@1 node
is required, so add a node with label edp_out.
Also restyle.
Signed-off-by: Johan Jonker
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 2250533cf..e02483b72 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -2037,7 +2037,7 @@
};
};
- edp: edp@ff97 {
+ edp: dp@ff97 {
compatible = "rockchip,rk3399-edp";
reg = <0x0 0xff97 0x0 0x8000>;
interrupts = ;
@@ -2054,6 +2054,7 @@
ports {
#address-cells = <1>;
#size-cells = <0>;
+
edp_in: port@0 {
reg = <0>;
#address-cells = <1>;
@@ -2069,6 +2070,10 @@
remote-endpoint = <&vopl_out_edp>;
};
};
+
+ edp_out: port@1 {
+ reg = <1>;
+ };
};
};
--
2.20.1
[PATCH v6 16/17] arm64: dts: rockchip: rename vbus-supply to phy-supply in rk3566-box-demo.dts
'vbus-supply' does not match any of the regexes in rk3566-box-demo.dts
in the usb2phy0_otg node, so rename vbus-supply to phy-supply.
Signed-off-by: Johan Jonker
---
arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
b/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
index 4c7f9abd5..4dc9b7623 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
@@ -464,7 +464,7 @@
};
&usb2phy0_otg {
- vbus-supply = <&vcc5v0_usb2_otg>;
+ phy-supply = <&vcc5v0_usb2_otg>;
status = "okay";
};
--
2.20.1
[PATCH v6 17/17] arm64: dts: rockchip: rk356x: remove hclk from dsi node
The hclk is not used in the dw-mipi-dsi-rockchip.c driver, so remove hclk from the rk356x.dtsi dsi node. Signed-off-by: Johan Jonker --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 5706c3e24..2cb61a783 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -743,8 +743,8 @@ compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x00 0xfe06 0x00 0x1>; interrupts = ; - clock-names = "pclk", "hclk"; - clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>; + clock-names = "pclk"; + clocks = <&cru PCLK_DSITX_0>; phy-names = "dphy"; phys = <&dsi_dphy0>; power-domains = <&power RK3568_PD_VO>; @@ -771,8 +771,8 @@ compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xfe07 0x0 0x1>; interrupts = ; - clock-names = "pclk", "hclk"; - clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>; + clock-names = "pclk"; + clocks = <&cru PCLK_DSITX_1>; phy-names = "dphy"; phys = <&dsi_dphy1>; power-domains = <&power RK3568_PD_VO>; -- 2.20.1
[PATCH v10 00/15] Add PSR support for eDP
Changes in v2: - Use dp bridge to set psr entry/exit instead of dpu_enocder. - Don't modify whitespaces. - Set self refresh aware from atomic_check. - Set self refresh aware only if psr is supported. - Provide a stub for msm_dp_display_set_psr. - Move dp functions to bridge code. Changes in v3: - Change callback names to reflect atomic interfaces. - Move bridge callback change to separate patch as suggested by Dmitry. - Remove psr function declaration from msm_drv.h. - Set self_refresh_aware flag only if psr is supported. - Modify the variable names to simpler form. - Define bit fields for PSR settings. - Add comments explaining the steps to enter/exit psr. - Change DRM_INFO to drm_dbg_db. Changes in v4: - Move the get crtc functions to drm_atomic. - Add atomic functions for DP bridge too. - Add ternary operator to choose eDP or DP ops. - Return true/false instead of 1/0. - mode_valid missing in the eDP bridge ops. - Move the functions to get crtc into drm_atomic.c. - Fix compilation issues. - Remove dpu_assign_crtc and get crtc from drm_enc instead of dpu_enc. - Check for crtc state enable while reserving resources. Changes in v5: - Move the mode_valid changes into a different patch. - Complete psr_op_comp only when isr is set. - Move the DP atomic callback changes to a different patch. - Get crtc from drm connector state crtc. - Move to separate patch for check for crtc state enable while reserving resources. Changes in v6: - Remove crtc from dpu_encoder_virt struct. - fix crtc check during vblank toggle crtc. - Misc changes. Changes in v7: - Add fix for underrun issue on kasan build. Changes in v8: - Drop the enc spinlock as it won't serve any purpose in protetcing conn state.(Dmitry/Doug) Changes in v9: - Update commit message and fix alignment using spaces.(Marijn) - Misc changes.(Marijn) Changes in v10: - get crtc cached in dpu_enc during obj init.(Dmitry) Sankeerth Billakanti (1): drm/msm/dp: disable self_refresh_aware after entering psr Vinod Polimera (14): drm/msm/disp/dpu: cache crtc obj in the dpu_encoder during initialization drm: add helper functions to retrieve old and new crtc drm/msm/dp: use atomic callbacks for DP bridge ops drm/msm/dp: Add basic PSR support for eDP drm/msm/dp: use the eDP bridge ops to validate eDP modes drm/bridge: use atomic enable/disable callbacks for panel bridge drm/bridge: add psr support for panel bridge callbacks drm/msm/disp/dpu: use atomic enable/disable callbacks for encoder functions drm/msm/disp/dpu: check for crtc enable rather than crtc active to release shared resources drm/msm/disp/dpu: add PSR support for eDP interface in dpu driver drm/msm/disp/dpu: get timing engine status from intf status register drm/msm/disp/dpu: wait for extra vsync till timing engine status is disabled drm/msm/disp/dpu: reset the datapath after timing engine disable drm/msm/disp/dpu: clear active interface in the datapath cleanup drivers/gpu/drm/bridge/panel.c | 68 ++- drivers/gpu/drm/drm_atomic.c | 60 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 17 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 45 +++-- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 22 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 12 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 8 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 3 +- drivers/gpu/drm/msm/dp/dp_catalog.c| 80 drivers/gpu/drm/msm/dp/dp_catalog.h| 4 + drivers/gpu/drm/msm/dp/dp_ctrl.c | 80 drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 + drivers/gpu/drm/msm/dp/dp_display.c| 36 ++-- drivers/gpu/drm/msm/dp/dp_display.h| 2 + drivers/gpu/drm/msm/dp/dp_drm.c| 206 - drivers/gpu/drm/msm/dp/dp_drm.h| 9 +- drivers/gpu/drm/msm/dp/dp_link.c | 36 drivers/gpu/drm/msm/dp/dp_panel.c | 22 +++ drivers/gpu/drm/msm/dp/dp_panel.h | 6 + drivers/gpu/drm/msm/dp/dp_reg.h| 27 +++ include/drm/drm_atomic.h | 7 + 22 files changed, 696 insertions(+), 60 deletions(-) -- 2.7.4
[PATCH v10 01/15] drm/msm/disp/dpu: cache crtc obj in the dpu_encoder during initialization
Cache crtc obj in the dpu encoder during initialization.
This will avoid extracting crtc from connector state there by
simplifying the obj access whenever it is required.
This patch is dependent on the series:
https://patchwork.freedesktop.org/series/110969/
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 4
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 16 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
3 files changed, 6 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 3f72d38..289d51e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1029,7 +1029,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc,
*/
if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
release_bandwidth = true;
- dpu_encoder_assign_crtc(encoder, NULL);
}
/* wait for frame_event_done completion */
@@ -1099,9 +1098,6 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc);
dpu_crtc->enabled = true;
- drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
- dpu_encoder_assign_crtc(encoder, crtc);
-
/* Enable/restore vblank irq handling */
drm_crtc_vblank_on(crtc);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index a585036..5055d56 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1317,7 +1317,6 @@ static void dpu_encoder_vblank_callback(struct
drm_encoder *drm_enc,
struct dpu_encoder_phys *phy_enc)
{
struct dpu_encoder_virt *dpu_enc = NULL;
- unsigned long lock_flags;
if (!drm_enc || !phy_enc)
return;
@@ -1325,12 +1324,11 @@ static void dpu_encoder_vblank_callback(struct
drm_encoder *drm_enc,
DPU_ATRACE_BEGIN("encoder_vblank_callback");
dpu_enc = to_dpu_encoder_virt(drm_enc);
- atomic_inc(&phy_enc->vsync_cnt);
+ if (!dpu_enc->crtc)
+ return;
- spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
- if (dpu_enc->crtc)
- dpu_crtc_vblank_callback(dpu_enc->crtc);
- spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
+ atomic_inc(&phy_enc->vsync_cnt);
+ dpu_crtc_vblank_callback(dpu_enc->crtc);
DPU_ATRACE_END("encoder_vblank_callback");
}
@@ -1369,17 +1367,13 @@ void dpu_encoder_toggle_vblank_for_crtc(struct
drm_encoder *drm_enc,
struct drm_crtc *crtc, bool enable)
{
struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
- unsigned long lock_flags;
int i;
trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
- spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
- if (dpu_enc->crtc != crtc) {
- spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
+ if (!dpu_enc->crtc || dpu_enc->crtc != crtc) {
return;
}
- spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 93221a2..264d571 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -801,6 +801,7 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
}
priv->crtcs[priv->num_crtcs++] = crtc;
encoder->possible_crtcs = 1 << drm_crtc_index(crtc);
+ dpu_encoder_assign_crtc(encoder, crtc);
i++;
}
--
2.7.4
[PATCH v10 02/15] drm: add helper functions to retrieve old and new crtc
Add new helper functions, drm_atomic_get_old_crtc_for_encoder
and drm_atomic_get_new_crtc_for_encoder to retrieve the
corresponding crtc for the encoder.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Douglas Anderson
---
drivers/gpu/drm/drm_atomic.c | 60
include/drm/drm_atomic.h | 7 ++
2 files changed, 67 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index f197f59..941fd6d 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -985,6 +985,66 @@ drm_atomic_get_new_connector_for_encoder(struct
drm_atomic_state *state,
EXPORT_SYMBOL(drm_atomic_get_new_connector_for_encoder);
/**
+ * drm_atomic_get_old_crtc_for_encoder - Get old crtc for an encoder
+ * @state: Atomic state
+ * @encoder: The encoder to fetch the crtc state for
+ *
+ * This function finds and returns the crtc that was connected to @encoder
+ * as specified by the @state.
+ *
+ * Returns: The old crtc connected to @encoder, or NULL if the encoder is
+ * not connected.
+ */
+struct drm_crtc *
+drm_atomic_get_old_crtc_for_encoder(struct drm_atomic_state *state,
+ struct drm_encoder *encoder)
+{
+ struct drm_connector *connector;
+ struct drm_connector_state *conn_state;
+
+ connector = drm_atomic_get_old_connector_for_encoder(state, encoder);
+ if (!connector)
+ return NULL;
+
+ conn_state = drm_atomic_get_old_connector_state(state, connector);
+ if (!conn_state)
+ return NULL;
+
+ return conn_state->crtc;
+}
+EXPORT_SYMBOL(drm_atomic_get_old_crtc_for_encoder);
+
+/**
+ * drm_atomic_get_new_crtc_for_encoder - Get new crtc for an encoder
+ * @state: Atomic state
+ * @encoder: The encoder to fetch the crtc state for
+ *
+ * This function finds and returns the crtc that will be connected to @encoder
+ * as specified by the @state.
+ *
+ * Returns: The new crtc connected to @encoder, or NULL if the encoder is
+ * not connected.
+ */
+struct drm_crtc *
+drm_atomic_get_new_crtc_for_encoder(struct drm_atomic_state *state,
+ struct drm_encoder *encoder)
+{
+ struct drm_connector *connector;
+ struct drm_connector_state *conn_state;
+
+ connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
+ if (!connector)
+ return NULL;
+
+ conn_state = drm_atomic_get_new_connector_state(state, connector);
+ if (!conn_state)
+ return NULL;
+
+ return conn_state->crtc;
+}
+EXPORT_SYMBOL(drm_atomic_get_new_crtc_for_encoder);
+
+/**
* drm_atomic_get_connector_state - get connector state
* @state: global atomic state object
* @connector: connector to get state object for
diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
index 10b1990..fdbd656 100644
--- a/include/drm/drm_atomic.h
+++ b/include/drm/drm_atomic.h
@@ -528,6 +528,13 @@ struct drm_connector *
drm_atomic_get_new_connector_for_encoder(struct drm_atomic_state *state,
struct drm_encoder *encoder);
+struct drm_crtc *
+drm_atomic_get_old_crtc_for_encoder(struct drm_atomic_state *state,
+struct drm_encoder *encoder);
+struct drm_crtc *
+drm_atomic_get_new_crtc_for_encoder(struct drm_atomic_state *state,
+struct drm_encoder *encoder);
+
/**
* drm_atomic_get_existing_crtc_state - get CRTC state, if it exists
* @state: global atomic state object
--
2.7.4
[PATCH v10 04/15] drm/msm/dp: Add basic PSR support for eDP
Add support for basic panel self refresh (PSR) feature for eDP.
Add a new interface to set PSR state in the sink from DPU.
Program the eDP controller to issue PSR enter and exit SDP to
the sink.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 80 ++
drivers/gpu/drm/msm/dp/dp_catalog.h | 4 ++
drivers/gpu/drm/msm/dp/dp_ctrl.c| 80 ++
drivers/gpu/drm/msm/dp/dp_ctrl.h| 3 +
drivers/gpu/drm/msm/dp/dp_display.c | 19 ++
drivers/gpu/drm/msm/dp/dp_display.h | 2 +
drivers/gpu/drm/msm/dp/dp_drm.c | 133 +++-
drivers/gpu/drm/msm/dp/dp_link.c| 36 ++
drivers/gpu/drm/msm/dp/dp_panel.c | 22 ++
drivers/gpu/drm/msm/dp/dp_panel.h | 6 ++
drivers/gpu/drm/msm/dp/dp_reg.h | 27
11 files changed, 411 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c
b/drivers/gpu/drm/msm/dp/dp_catalog.c
index 676279d..c12a5d9 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
@@ -47,6 +47,14 @@
#define DP_INTERRUPT_STATUS2_MASK \
(DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_MASK_SHIFT)
+#define DP_INTERRUPT_STATUS4 \
+ (PSR_UPDATE_INT | PSR_CAPTURE_INT | PSR_EXIT_INT | \
+ PSR_UPDATE_ERROR_INT | PSR_WAKE_ERROR_INT)
+
+#define DP_INTERRUPT_MASK4 \
+ (PSR_UPDATE_MASK | PSR_CAPTURE_MASK | PSR_EXIT_MASK | \
+ PSR_UPDATE_ERROR_MASK | PSR_WAKE_ERROR_MASK)
+
struct dp_catalog_private {
struct device *dev;
struct drm_device *drm_dev;
@@ -359,6 +367,23 @@ void dp_catalog_ctrl_lane_mapping(struct dp_catalog
*dp_catalog)
ln_mapping);
}
+void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog,
+ bool enable)
+{
+ u32 val;
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+
+ val = dp_read_link(catalog, REG_DP_MAINLINK_CTRL);
+
+ if (enable)
+ val |= DP_MAINLINK_CTRL_ENABLE;
+ else
+ val &= ~DP_MAINLINK_CTRL_ENABLE;
+
+ dp_write_link(catalog, REG_DP_MAINLINK_CTRL, val);
+}
+
void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog,
bool enable)
{
@@ -610,6 +635,47 @@ void dp_catalog_ctrl_hpd_config(struct dp_catalog
*dp_catalog)
dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN);
}
+static void dp_catalog_enable_sdp(struct dp_catalog_private *catalog)
+{
+ /* trigger sdp */
+ dp_write_link(catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP);
+ dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x0);
+}
+
+void dp_catalog_ctrl_config_psr(struct dp_catalog *dp_catalog)
+{
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+ u32 config;
+
+ /* enable PSR1 function */
+ config = dp_read_link(catalog, REG_PSR_CONFIG);
+ config |= PSR1_SUPPORTED;
+ dp_write_link(catalog, REG_PSR_CONFIG, config);
+
+ dp_write_ahb(catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4);
+ dp_catalog_enable_sdp(catalog);
+}
+
+void dp_catalog_ctrl_set_psr(struct dp_catalog *dp_catalog, bool enter)
+{
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+ u32 cmd;
+
+ cmd = dp_read_link(catalog, REG_PSR_CMD);
+
+ cmd &= ~(PSR_ENTER | PSR_EXIT);
+
+ if (enter)
+ cmd |= PSR_ENTER;
+ else
+ cmd |= PSR_EXIT;
+
+ dp_catalog_enable_sdp(catalog);
+ dp_write_link(catalog, REG_PSR_CMD, cmd);
+}
+
u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
@@ -645,6 +711,20 @@ u32 dp_catalog_hpd_get_intr_status(struct dp_catalog
*dp_catalog)
return isr & (mask | ~DP_DP_HPD_INT_MASK);
}
+u32 dp_catalog_ctrl_read_psr_interrupt_status(struct dp_catalog *dp_catalog)
+{
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+ u32 intr, intr_ack;
+
+ intr = dp_read_ahb(catalog, REG_DP_INTR_STATUS4);
+ intr_ack = (intr & DP_INTERRUPT_STATUS4)
+ << DP_INTERRUPT_STATUS_ACK_SHIFT;
+ dp_write_ahb(catalog, REG_DP_INTR_STATUS4, intr_ack);
+
+ return intr;
+}
+
int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h
b/drivers/gpu/drm/msm/dp/dp_catalog.h
index 1f717f4..2174bb5 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalo
[PATCH v10 05/15] drm/msm/dp: use the eDP bridge ops to validate eDP modes
The eDP and DP interfaces shared the bridge operations and
the eDP specific changes were implemented under is_edp check.
To add psr support for eDP, we started using a new set of eDP
bridge ops. We are moving the eDP specific code in the
dp_bridge_mode_valid function to a new eDP function,
edp_bridge_mode_valid under the eDP bridge ops.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_display.c | 8
drivers/gpu/drm/msm/dp/dp_drm.c | 34 +-
2 files changed, 33 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index 7ec81b8..91642a0 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -984,14 +984,6 @@ enum drm_mode_status dp_bridge_mode_valid(struct
drm_bridge *bridge,
return -EINVAL;
}
- /*
-* The eDP controller currently does not have a reliable way of
-* enabling panel power to read sink capabilities. So, we rely
-* on the panel driver to populate only supported modes for now.
-*/
- if (dp->is_edp)
- return MODE_OK;
-
if (mode->clock > DP_MAX_PIXEL_CLK_KHZ)
return MODE_CLOCK_HIGH;
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
index df66df0..d3e9010 100644
--- a/drivers/gpu/drm/msm/dp/dp_drm.c
+++ b/drivers/gpu/drm/msm/dp/dp_drm.c
@@ -223,12 +223,44 @@ static void edp_bridge_atomic_post_disable(struct
drm_bridge *drm_bridge,
dp_bridge_atomic_post_disable(drm_bridge, old_bridge_state);
}
+/**
+ * edp_bridge_mode_valid - callback to determine if specified mode is valid
+ * @bridge: Pointer to drm bridge structure
+ * @info: display info
+ * @mode: Pointer to drm mode structure
+ * Returns: Validity status for specified mode
+ */
+static enum drm_mode_status edp_bridge_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode)
+{
+ struct msm_dp *dp;
+ int mode_pclk_khz = mode->clock;
+
+ dp = to_dp_bridge(bridge)->dp_display;
+
+ if (!dp || !mode_pclk_khz || !dp->connector) {
+ DRM_ERROR("invalid params\n");
+ return -EINVAL;
+ }
+
+ if (mode->clock > DP_MAX_PIXEL_CLK_KHZ)
+ return MODE_CLOCK_HIGH;
+
+ /*
+* The eDP controller currently does not have a reliable way of
+* enabling panel power to read sink capabilities. So, we rely
+* on the panel driver to populate only supported modes for now.
+*/
+ return MODE_OK;
+}
+
static const struct drm_bridge_funcs edp_bridge_ops = {
.atomic_enable = edp_bridge_atomic_enable,
.atomic_disable = edp_bridge_atomic_disable,
.atomic_post_disable = edp_bridge_atomic_post_disable,
.mode_set = dp_bridge_mode_set,
- .mode_valid = dp_bridge_mode_valid,
+ .mode_valid = edp_bridge_mode_valid,
.atomic_reset = drm_atomic_helper_bridge_reset,
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
--
2.7.4
[PATCH v10 00/15] Add PSR support for eDP
Changes in v2: - Use dp bridge to set psr entry/exit instead of dpu_enocder. - Don't modify whitespaces. - Set self refresh aware from atomic_check. - Set self refresh aware only if psr is supported. - Provide a stub for msm_dp_display_set_psr. - Move dp functions to bridge code. Changes in v3: - Change callback names to reflect atomic interfaces. - Move bridge callback change to separate patch as suggested by Dmitry. - Remove psr function declaration from msm_drv.h. - Set self_refresh_aware flag only if psr is supported. - Modify the variable names to simpler form. - Define bit fields for PSR settings. - Add comments explaining the steps to enter/exit psr. - Change DRM_INFO to drm_dbg_db. Changes in v4: - Move the get crtc functions to drm_atomic. - Add atomic functions for DP bridge too. - Add ternary operator to choose eDP or DP ops. - Return true/false instead of 1/0. - mode_valid missing in the eDP bridge ops. - Move the functions to get crtc into drm_atomic.c. - Fix compilation issues. - Remove dpu_assign_crtc and get crtc from drm_enc instead of dpu_enc. - Check for crtc state enable while reserving resources. Changes in v5: - Move the mode_valid changes into a different patch. - Complete psr_op_comp only when isr is set. - Move the DP atomic callback changes to a different patch. - Get crtc from drm connector state crtc. - Move to separate patch for check for crtc state enable while reserving resources. Changes in v6: - Remove crtc from dpu_encoder_virt struct. - fix crtc check during vblank toggle crtc. - Misc changes. Changes in v7: - Add fix for underrun issue on kasan build. Changes in v8: - Drop the enc spinlock as it won't serve any purpose in protetcing conn state.(Dmitry/Doug) Changes in v9: - Update commit message and fix alignment using spaces.(Marijn) - Misc changes.(Marijn) Changes in v10: - get crtc cached in dpu_enc during obj init.(Dmitry) Sankeerth Billakanti (1): drm/msm/dp: disable self_refresh_aware after entering psr Vinod Polimera (14): drm/msm/disp/dpu: cache crtc obj in the dpu_encoder during initialization drm: add helper functions to retrieve old and new crtc drm/msm/dp: use atomic callbacks for DP bridge ops drm/msm/dp: Add basic PSR support for eDP drm/msm/dp: use the eDP bridge ops to validate eDP modes drm/bridge: use atomic enable/disable callbacks for panel bridge drm/bridge: add psr support for panel bridge callbacks drm/msm/disp/dpu: use atomic enable/disable callbacks for encoder functions drm/msm/disp/dpu: check for crtc enable rather than crtc active to release shared resources drm/msm/disp/dpu: add PSR support for eDP interface in dpu driver drm/msm/disp/dpu: get timing engine status from intf status register drm/msm/disp/dpu: wait for extra vsync till timing engine status is disabled drm/msm/disp/dpu: reset the datapath after timing engine disable drm/msm/disp/dpu: clear active interface in the datapath cleanup drivers/gpu/drm/bridge/panel.c | 68 ++- drivers/gpu/drm/drm_atomic.c | 60 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 17 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 45 +++-- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 22 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 12 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 8 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 3 +- drivers/gpu/drm/msm/dp/dp_catalog.c| 80 drivers/gpu/drm/msm/dp/dp_catalog.h| 4 + drivers/gpu/drm/msm/dp/dp_ctrl.c | 80 drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 + drivers/gpu/drm/msm/dp/dp_display.c| 36 ++-- drivers/gpu/drm/msm/dp/dp_display.h| 2 + drivers/gpu/drm/msm/dp/dp_drm.c| 206 - drivers/gpu/drm/msm/dp/dp_drm.h| 9 +- drivers/gpu/drm/msm/dp/dp_link.c | 36 drivers/gpu/drm/msm/dp/dp_panel.c | 22 +++ drivers/gpu/drm/msm/dp/dp_panel.h | 6 + drivers/gpu/drm/msm/dp/dp_reg.h| 27 +++ include/drm/drm_atomic.h | 7 + 22 files changed, 696 insertions(+), 60 deletions(-) -- 2.7.4
[PATCH v10 03/15] drm/msm/dp: use atomic callbacks for DP bridge ops
Use atomic variants for DP bridge callback functions so that
the atomic state can be accessed in the interface drivers.
The atomic state will help the driver find out if the display
is in self refresh state.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
Reviewed-by: Douglas Anderson
---
drivers/gpu/drm/msm/dp/dp_display.c | 9 ++---
drivers/gpu/drm/msm/dp/dp_drm.c | 16
drivers/gpu/drm/msm/dp/dp_drm.h | 9 ++---
3 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index 7ff60e5..c04a02b 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -1643,7 +1643,8 @@ int msm_dp_modeset_init(struct msm_dp *dp_display, struct
drm_device *dev,
return 0;
}
-void dp_bridge_enable(struct drm_bridge *drm_bridge)
+void dp_bridge_atomic_enable(struct drm_bridge *drm_bridge,
+struct drm_bridge_state *old_bridge_state)
{
struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge);
struct msm_dp *dp = dp_bridge->dp_display;
@@ -1698,7 +1699,8 @@ void dp_bridge_enable(struct drm_bridge *drm_bridge)
mutex_unlock(&dp_display->event_mutex);
}
-void dp_bridge_disable(struct drm_bridge *drm_bridge)
+void dp_bridge_atomic_disable(struct drm_bridge *drm_bridge,
+ struct drm_bridge_state *old_bridge_state)
{
struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge);
struct msm_dp *dp = dp_bridge->dp_display;
@@ -1709,7 +1711,8 @@ void dp_bridge_disable(struct drm_bridge *drm_bridge)
dp_ctrl_push_idle(dp_display->ctrl);
}
-void dp_bridge_post_disable(struct drm_bridge *drm_bridge)
+void dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge,
+ struct drm_bridge_state *old_bridge_state)
{
struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge);
struct msm_dp *dp = dp_bridge->dp_display;
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
index 6db82f9..77c34cb 100644
--- a/drivers/gpu/drm/msm/dp/dp_drm.c
+++ b/drivers/gpu/drm/msm/dp/dp_drm.c
@@ -94,14 +94,14 @@ static const struct drm_bridge_funcs dp_bridge_ops = {
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
.atomic_reset = drm_atomic_helper_bridge_reset,
- .enable = dp_bridge_enable,
- .disable = dp_bridge_disable,
- .post_disable = dp_bridge_post_disable,
- .mode_set = dp_bridge_mode_set,
- .mode_valid = dp_bridge_mode_valid,
- .get_modes= dp_bridge_get_modes,
- .detect = dp_bridge_detect,
- .atomic_check = dp_bridge_atomic_check,
+ .atomic_enable = dp_bridge_atomic_enable,
+ .atomic_disable = dp_bridge_atomic_disable,
+ .atomic_post_disable= dp_bridge_atomic_post_disable,
+ .mode_set = dp_bridge_mode_set,
+ .mode_valid = dp_bridge_mode_valid,
+ .get_modes = dp_bridge_get_modes,
+ .detect = dp_bridge_detect,
+ .atomic_check = dp_bridge_atomic_check,
};
struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device
*dev,
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_drm.h
index 82035db..e69c0b9 100644
--- a/drivers/gpu/drm/msm/dp/dp_drm.h
+++ b/drivers/gpu/drm/msm/dp/dp_drm.h
@@ -23,9 +23,12 @@ struct drm_connector *dp_drm_connector_init(struct msm_dp
*dp_display, struct dr
struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device
*dev,
struct drm_encoder *encoder);
-void dp_bridge_enable(struct drm_bridge *drm_bridge);
-void dp_bridge_disable(struct drm_bridge *drm_bridge);
-void dp_bridge_post_disable(struct drm_bridge *drm_bridge);
+void dp_bridge_atomic_enable(struct drm_bridge *drm_bridge,
+struct drm_bridge_state *old_bridge_state);
+void dp_bridge_atomic_disable(struct drm_bridge *drm_bridge,
+ struct drm_bridge_state *old_bridge_state);
+void dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge,
+ struct drm_bridge_state *old_bridge_state);
enum drm_mode_status dp_bridge_mode_valid(struct drm_bridge *bridge,
const struct drm_display_info *info,
const struct drm_display_mode *mode);
--
2.7.4
[PATCH v10 09/15] drm/msm/disp/dpu: use atomic enable/disable callbacks for encoder functions
Use atomic variants for encoder callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 5055d56..98f38d6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1202,7 +1202,8 @@ void dpu_encoder_virt_runtime_resume(struct drm_encoder
*drm_enc)
mutex_unlock(&dpu_enc->enc_lock);
}
-static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
+static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc,
+ struct drm_atomic_state *state)
{
struct dpu_encoder_virt *dpu_enc = NULL;
int ret = 0;
@@ -1238,7 +1239,8 @@ static void dpu_encoder_virt_enable(struct drm_encoder
*drm_enc)
mutex_unlock(&dpu_enc->enc_lock);
}
-static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
+static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc,
+ struct drm_atomic_state *state)
{
struct dpu_encoder_virt *dpu_enc = NULL;
int i = 0;
@@ -2417,8 +2419,8 @@ static void dpu_encoder_frame_done_timeout(struct
timer_list *t)
static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
.atomic_mode_set = dpu_encoder_virt_atomic_mode_set,
- .disable = dpu_encoder_virt_disable,
- .enable = dpu_encoder_virt_enable,
+ .atomic_disable = dpu_encoder_virt_atomic_disable,
+ .atomic_enable = dpu_encoder_virt_atomic_enable,
.atomic_check = dpu_encoder_virt_atomic_check,
};
--
2.7.4
[PATCH v10 08/15] drm/bridge: add psr support for panel bridge callbacks
This change will handle the psr entry exit cases in the panel
bridge atomic callback functions. For example, the panel power
should not turn off if the panel is entering psr.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/bridge/panel.c | 48 ++
1 file changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c
index 3558cbf..5e77e38 100644
--- a/drivers/gpu/drm/bridge/panel.c
+++ b/drivers/gpu/drm/bridge/panel.c
@@ -113,6 +113,18 @@ static void panel_bridge_atomic_pre_enable(struct
drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
+ struct drm_atomic_state *atomic_state = old_bridge_state->base.state;
+ struct drm_encoder *encoder = bridge->encoder;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *old_crtc_state;
+
+ crtc = drm_atomic_get_new_crtc_for_encoder(atomic_state, encoder);
+ if (!crtc)
+ return;
+
+ old_crtc_state = drm_atomic_get_old_crtc_state(atomic_state, crtc);
+ if (old_crtc_state && old_crtc_state->self_refresh_active)
+ return;
drm_panel_prepare(panel_bridge->panel);
}
@@ -121,6 +133,18 @@ static void panel_bridge_atomic_enable(struct drm_bridge
*bridge,
struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
+ struct drm_atomic_state *atomic_state = old_bridge_state->base.state;
+ struct drm_encoder *encoder = bridge->encoder;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *old_crtc_state;
+
+ crtc = drm_atomic_get_new_crtc_for_encoder(atomic_state, encoder);
+ if (!crtc)
+ return;
+
+ old_crtc_state = drm_atomic_get_old_crtc_state(atomic_state, crtc);
+ if (old_crtc_state && old_crtc_state->self_refresh_active)
+ return;
drm_panel_enable(panel_bridge->panel);
}
@@ -129,6 +153,18 @@ static void panel_bridge_atomic_disable(struct drm_bridge
*bridge,
struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
+ struct drm_atomic_state *atomic_state = old_bridge_state->base.state;
+ struct drm_encoder *encoder = bridge->encoder;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *new_crtc_state;
+
+ crtc = drm_atomic_get_old_crtc_for_encoder(atomic_state, encoder);
+ if (!crtc)
+ return;
+
+ new_crtc_state = drm_atomic_get_new_crtc_state(atomic_state, crtc);
+ if (new_crtc_state && new_crtc_state->self_refresh_active)
+ return;
drm_panel_disable(panel_bridge->panel);
}
@@ -137,6 +173,18 @@ static void panel_bridge_atomic_post_disable(struct
drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
+ struct drm_atomic_state *atomic_state = old_bridge_state->base.state;
+ struct drm_encoder *encoder = bridge->encoder;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *new_crtc_state;
+
+ crtc = drm_atomic_get_old_crtc_for_encoder(atomic_state, encoder);
+ if (!crtc)
+ return;
+
+ new_crtc_state = drm_atomic_get_new_crtc_state(atomic_state, crtc);
+ if (new_crtc_state && new_crtc_state->self_refresh_active)
+ return;
drm_panel_unprepare(panel_bridge->panel);
}
--
2.7.4
[PATCH v10 06/15] drm/msm/dp: disable self_refresh_aware after entering psr
From: Sankeerth Billakanti
Updated frames get queued if self_refresh_aware is set when the
sink is in psr. To support bridge enable and avoid queuing of update
frames, reset the self_refresh_aware state after entering psr.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/dp/dp_drm.c | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
index d3e9010..0f262a6 100644
--- a/drivers/gpu/drm/msm/dp/dp_drm.c
+++ b/drivers/gpu/drm/msm/dp/dp_drm.c
@@ -131,6 +131,8 @@ static void edp_bridge_atomic_enable(struct drm_bridge
*drm_bridge,
struct drm_crtc_state *old_crtc_state;
struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge);
struct msm_dp *dp = dp_bridge->dp_display;
+ struct drm_connector *connector;
+ struct drm_connector_state *conn_state = NULL;
/*
* Check the old state of the crtc to determine if the panel
@@ -147,10 +149,22 @@ static void edp_bridge_atomic_enable(struct drm_bridge
*drm_bridge,
if (old_crtc_state && old_crtc_state->self_refresh_active) {
dp_display_set_psr(dp, false);
- return;
+ goto psr_aware;
}
dp_bridge_atomic_enable(drm_bridge, old_bridge_state);
+
+psr_aware:
+ connector = drm_atomic_get_new_connector_for_encoder(atomic_state,
+ drm_bridge->encoder);
+ if (connector)
+ conn_state = drm_atomic_get_new_connector_state(atomic_state,
+ connector);
+
+ if (conn_state) {
+ conn_state->self_refresh_aware = dp->psr_supported;
+ }
+
}
static void edp_bridge_atomic_disable(struct drm_bridge *drm_bridge,
@@ -161,6 +175,14 @@ static void edp_bridge_atomic_disable(struct drm_bridge
*drm_bridge,
struct drm_crtc_state *new_crtc_state = NULL, *old_crtc_state = NULL;
struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge);
struct msm_dp *dp = dp_bridge->dp_display;
+ struct drm_connector *connector;
+ struct drm_connector_state *conn_state = NULL;
+
+ connector = drm_atomic_get_old_connector_for_encoder(atomic_state,
+ drm_bridge->encoder);
+ if (connector)
+ conn_state = drm_atomic_get_new_connector_state(atomic_state,
+ connector);
crtc = drm_atomic_get_old_crtc_for_encoder(atomic_state,
drm_bridge->encoder);
@@ -187,6 +209,9 @@ static void edp_bridge_atomic_disable(struct drm_bridge
*drm_bridge,
* when display disable occurs while the sink is in psr state.
*/
if (new_crtc_state->self_refresh_active) {
+ if (conn_state)
+ conn_state->self_refresh_aware = false;
+
dp_display_set_psr(dp, true);
return;
} else if (old_crtc_state->self_refresh_active) {
--
2.7.4
[PATCH v10 10/15] drm/msm/disp/dpu: check for crtc enable rather than crtc active to release shared resources
According to KMS documentation, The driver must not release any shared
resources if active is set to false but enable still true.
Fixes: ccc862b957c6 ("drm/msm/dpu: Fix reservation failures in modeset")
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 98f38d6..f454964 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -683,7 +683,7 @@ static int dpu_encoder_virt_atomic_check(
if (drm_atomic_crtc_needs_modeset(crtc_state)) {
dpu_rm_release(global_state, drm_enc);
- if (!crtc_state->active_changed || crtc_state->active)
+ if (!crtc_state->active_changed || crtc_state->enable)
ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
drm_enc, crtc_state, topology);
}
--
2.7.4
[PATCH v10 07/15] drm/bridge: use atomic enable/disable callbacks for panel bridge
Use atomic variants for panel bridge callback functions such that
certain states like self-refresh can be accessed as part of
enable/disable sequence.
Signed-off-by: Sankeerth Billakanti
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/panel.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c
index 216af76..3558cbf 100644
--- a/drivers/gpu/drm/bridge/panel.c
+++ b/drivers/gpu/drm/bridge/panel.c
@@ -109,28 +109,32 @@ static void panel_bridge_detach(struct drm_bridge *bridge)
drm_connector_cleanup(connector);
}
-static void panel_bridge_pre_enable(struct drm_bridge *bridge)
+static void panel_bridge_atomic_pre_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
drm_panel_prepare(panel_bridge->panel);
}
-static void panel_bridge_enable(struct drm_bridge *bridge)
+static void panel_bridge_atomic_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
drm_panel_enable(panel_bridge->panel);
}
-static void panel_bridge_disable(struct drm_bridge *bridge)
+static void panel_bridge_atomic_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
drm_panel_disable(panel_bridge->panel);
}
-static void panel_bridge_post_disable(struct drm_bridge *bridge)
+static void panel_bridge_atomic_post_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
@@ -159,10 +163,10 @@ static void panel_bridge_debugfs_init(struct drm_bridge
*bridge,
static const struct drm_bridge_funcs panel_bridge_bridge_funcs = {
.attach = panel_bridge_attach,
.detach = panel_bridge_detach,
- .pre_enable = panel_bridge_pre_enable,
- .enable = panel_bridge_enable,
- .disable = panel_bridge_disable,
- .post_disable = panel_bridge_post_disable,
+ .atomic_pre_enable = panel_bridge_atomic_pre_enable,
+ .atomic_enable = panel_bridge_atomic_enable,
+ .atomic_disable = panel_bridge_atomic_disable,
+ .atomic_post_disable = panel_bridge_atomic_post_disable,
.get_modes = panel_bridge_get_modes,
.atomic_reset = drm_atomic_helper_bridge_reset,
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
--
2.7.4
[PATCH v10 11/15] drm/msm/disp/dpu: add PSR support for eDP interface in dpu driver
Enable PSR on eDP interface using drm self-refresh librabry.
This patch uses a trigger from self-refresh library to enter/exit
into PSR, when there are no updates from framework.
Signed-off-by: Kalyan Thota
Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 13 -
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 14 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
3 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 289d51e..386b037 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
#include "dpu_kms.h"
#include "dpu_hw_lm.h"
@@ -1018,6 +1019,9 @@ static void dpu_crtc_disable(struct drm_crtc *crtc,
DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
+ if (old_crtc_state->self_refresh_active)
+ return;
+
/* Disable/save vblank irq handling */
drm_crtc_vblank_off(crtc);
@@ -1572,7 +1576,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev,
struct drm_plane *plane,
{
struct drm_crtc *crtc = NULL;
struct dpu_crtc *dpu_crtc = NULL;
- int i;
+ int i, ret;
dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL);
if (!dpu_crtc)
@@ -1610,6 +1614,13 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev,
struct drm_plane *plane,
/* initialize event handling */
spin_lock_init(&dpu_crtc->event_lock);
+ ret = drm_self_refresh_helper_init(crtc);
+ if (ret) {
+ DPU_ERROR("Failed to initialize %s with self-refresh helpers
%d\n",
+ crtc->name, ret);
+ return ERR_PTR(ret);
+ }
+
DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc->name);
return crtc;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index f454964..e13a309 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -12,6 +12,7 @@
#include
#include
+#include
#include
#include
#include
@@ -1243,11 +1244,24 @@ static void dpu_encoder_virt_atomic_disable(struct
drm_encoder *drm_enc,
struct drm_atomic_state *state)
{
struct dpu_encoder_virt *dpu_enc = NULL;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *old_state = NULL;
int i = 0;
dpu_enc = to_dpu_encoder_virt(drm_enc);
DPU_DEBUG_ENC(dpu_enc, "\n");
+ crtc = drm_atomic_get_old_crtc_for_encoder(state, drm_enc);
+ if (crtc)
+ old_state = drm_atomic_get_old_crtc_state(state, crtc);
+
+ /*
+* The encoder is already disabled if self refresh mode was set earlier,
+* in the old_state for the corresponding crtc.
+*/
+ if (old_state && old_state->self_refresh_active)
+ return;
+
mutex_lock(&dpu_enc->enc_lock);
dpu_enc->enabled = false;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 264d571..3ab12f0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -491,7 +491,7 @@ static void dpu_kms_wait_for_commit_done(struct msm_kms
*kms,
return;
}
- if (!crtc->state->active) {
+ if (!drm_atomic_crtc_effectively_active(crtc->state)) {
DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id);
return;
}
--
2.7.4
[PATCH v10 13/15] drm/msm/disp/dpu: wait for extra vsync till timing engine status is disabled
There can be a race between timing gen disable and vblank irq. The
wait post timing gen disable may return early but intf disable sequence
might not be completed. Ensure that, intf status is disabled before
we retire the function.
Signed-off-by: Vinod Polimera
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c| 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 0f71e8f..685cb44 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -526,6 +526,7 @@ static void dpu_encoder_phys_vid_disable(struct
dpu_encoder_phys *phys_enc)
{
unsigned long lock_flags;
int ret;
+ struct intf_status intf_status = {0};
if (!phys_enc->parent || !phys_enc->parent->dev) {
DPU_ERROR("invalid encoder/device\n");
@@ -570,6 +571,26 @@ static void dpu_encoder_phys_vid_disable(struct
dpu_encoder_phys *phys_enc)
}
}
+ if (phys_enc->hw_intf && phys_enc->hw_intf->ops.get_status)
+ phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf,
&intf_status);
+
+ /*
+* Wait for a vsync if timing en status is on after timing engine
+* is disabled.
+*/
+ if (intf_status.is_en && dpu_encoder_phys_vid_is_master(phys_enc)) {
+ spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
+ dpu_encoder_phys_inc_pending(phys_enc);
+ spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
+ ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc);
+ if (ret) {
+ atomic_set(&phys_enc->pending_kickoff_cnt, 0);
+ DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
+ DRMID(phys_enc->parent),
+ phys_enc->hw_intf->idx - INTF_0, ret);
+ }
+ }
+
phys_enc->enable_state = DPU_ENC_DISABLED;
}
--
2.7.4
[PATCH v10 12/15] drm/msm/disp/dpu: get timing engine status from intf status register
Recommended way of reading the interface timing gen status is via
status register. Timing gen status register will give a reliable status
of the interface especially during ON/OFF transitions. This support was
added from DPU version 5.0.0.
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 12 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 8 +++-
3 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 2196e20..0e410cd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -77,7 +77,8 @@
#define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE)
-#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
+#define INTF_SC7280_MASK \
+ (INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) |
BIT(DPU_INTF_STATUS_SUPPORTED))
#define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 3b645d5..b16b428 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -204,17 +204,19 @@ enum {
/**
* INTF sub-blocks
- * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
- * pixel data arrives to this INTF
- * @DPU_INTF_TE INTF block has TE configuration support
- * @DPU_DATA_HCTL_ENAllows data to be transferred at different rate
-than video timing
+ * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
+ * pixel data arrives to this INTF
+ * @DPU_INTF_TE INTF block has TE configuration support
+ * @DPU_DATA_HCTL_ENAllows data to be transferred at different
rate
+ * than video timing
+ * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register
* @DPU_INTF_MAX
*/
enum {
DPU_INTF_INPUT_CTRL = 0x1,
DPU_INTF_TE,
DPU_DATA_HCTL_EN,
+ DPU_INTF_STATUS_SUPPORTED,
DPU_INTF_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 7ce66bf..84ee2ef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -62,6 +62,7 @@
#define INTF_LINE_COUNT 0x0B0
#define INTF_MUX 0x25C
+#define INTF_STATUS 0x26C
#define INTF_CFG_ACTIVE_H_EN BIT(29)
#define INTF_CFG_ACTIVE_V_EN BIT(30)
@@ -297,8 +298,13 @@ static void dpu_hw_intf_get_status(
struct intf_status *s)
{
struct dpu_hw_blk_reg_map *c = &intf->hw;
+ unsigned long cap = intf->cap->features;
+
+ if (cap & BIT(DPU_INTF_STATUS_SUPPORTED))
+ s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0);
+ else
+ s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);
- s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);
s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31));
if (s->is_en) {
s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT);
--
2.7.4
[PATCH v10 15/15] drm/msm/disp/dpu: clear active interface in the datapath cleanup
Clear interface active register from the datapath for a clean shutdown of the datapath. Signed-off-by: Vinod Polimera --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index e13a309..b49c8dc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2108,6 +2108,9 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) if (phys_enc->hw_pp->merge_3d) intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; + if (phys_enc->hw_intf) + intf_cfg.intf = phys_enc->hw_intf->idx; + if (ctl->ops.reset_intf_cfg) ctl->ops.reset_intf_cfg(ctl, &intf_cfg); -- 2.7.4
[PATCH v10 14/15] drm/msm/disp/dpu: reset the datapath after timing engine disable
Reset the datapath after disabling the timing gen, such that it can start on a clean slate when the intf is enabled back. This was a recommended sequence from the DPU HW programming guide. Signed-off-by: Vinod Polimera --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 685cb44..a597cca 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -591,6 +591,7 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc) } } + dpu_encoder_helper_phys_cleanup(phys_enc); phys_enc->enable_state = DPU_ENC_DISABLED; } -- 2.7.4
Re: [PATCH v2 7/9] drm: Remove usage of deprecated DRM_DEBUG_PRIME
This patch is: Reviewed-by: Simon Ser
Re: [PATCH 1/4] drm/i915/gt: Remove platform comments from workarounds
On Thu, Dec 22, 2022 at 10:27:00AM +, Tvrtko Ursulin wrote:
On 22/12/2022 08:25, Lucas De Marchi wrote:
The comments are redundant to the checks being done to apply the
workarounds and very often get outdated as workarounds need to be
extended to new platforms or steppings. Remove them altogether with
the following matches (platforms extracted from intel_workarounds.c):
find drivers/gpu/drm/i915/gt/ -name '*.c' | xargs sed -i -E \
's/(Wa.*):(bdw|chv|bxt|glk|skl|kbl|cfl|cfl|whl|cml|aml|chv|cl|bw|ctg|elk|ilk|snb|dg|pvc|g4x|ilk|gen|glk|kbl|cml|glk|kbl|cml|hsw|icl|ehl|ivb|hsw|ivb|vlv|kbl|pvc|rkl|dg|adl|skl|skl|bxt|blk|cfl|cnl|glk|snb|tgl|vlv|xehpsdv).*/\1/'
find drivers/gpu/drm/i915/gt/ -name '*.c' | xargs sed -i -E \
's/(Wa.*):(bdw|chv|bxt|glk|skl|kbl|cfl|cfl|whl|cml|aml|chv|cl|bw|ctg|elk|ilk|snb|dg|pvc|g4x|ilk|gen|glk|kbl|cml|glk|kbl|cml|hsw|icl|ehl|ivb|hsw|ivb|vlv|kbl|pvc|rkl|dg|adl|skl|skl|bxt|blk|cfl|cnl|glk|snb|tgl|vlv|xehpsdv).*\*\//\1
Same things was executed in the gem directory, omitted here for brevity.
There were a few false positives that included the workaround
description. Those were manually patched.
sed -E 's/(Wa[a-zA-Z0-9_]+)[:,]([a-zA-Z0-9,-_\+\[]{2,})/\1/'
then there are false negatives. We have Was in the form
"Wa_xxx:tgl,dg2, mtl". False positives we can fixup, false negatives
we simply don't see. After running that in gt/:
$ git grep ": mtl" -- drivers/gpu/drm/i915/
drivers/gpu/drm/i915/gt/intel_gt_pm.c: /* Wa_14017073508: mtl */
drivers/gpu/drm/i915/gt/intel_gt_pm.c: /* Wa_14017073508: mtl */
drivers/gpu/drm/i915/gt/intel_gt_pm.c: /* Wa_14017073508: mtl */
drivers/gpu/drm/i915/gt/intel_gt_pm.c: /* Wa_14017073508: mtl */
drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c: * Wa_14017073508: mtl
drivers/gpu/drm/i915/i915_reg.h:/* Wa_14017210380: mtl */
I was going with the platform names to avoid the false
negatives and because I was entertaining the idea of only doing this for
latest platforms where we do have the "Wa_[[:number:]]" form
Maybe..
Matt recently said he has this worked planned, but more importantly -
I gather then that the WA lookup tool definitely does not output these
strings?
Whatever it does it's true only at the time it's called. It simply tells what
are the platforms and steppings the Wa applies to. We can change the
output to whatever we want, but that is not the point.
Those comments get stale and bring no real value as they match 1:1
what the code is supposed to be doing. Several times a patch has to
update just that comment to "extend a workaround" to a next platform.
This is not always done, so we get a comment that doesn't match what is
supposed to be there.
Lucas De Marchi
Regards,
Tvrtko
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 2 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 12 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
.../drm/i915/gt/intel_execlists_submission.c | 6 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 20 +-
drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 4 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 4 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 10 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 440 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 16 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
16 files changed, 266 insertions(+), 266 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index bc9521078807..a2a49cc25ca3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -46,7 +46,7 @@ int i915_gem_stolen_insert_node_in_range(struct
drm_i915_private *i915,
if (!drm_mm_initialized(&i915->mm.stolen))
return -ENODEV;
- /* WaSkipStolenMemoryFirstPage:bdw+ */
+ /* WaSkipStolenMemoryFirstPage */
if (GRAPHICS_VER(i915) >= 8 && start < 4096)
start = 4096;
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index e1c76e5bfa82..d7a40ed66d9e 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -42,7 +42,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
if (GRAPHICS_VER(rq->engine->i915) == 9)
vf_flush_wa = true;
- /* WaForGAMHang:kbl */
+ /* WaForGAMHang */
if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
dc_flush_wa = true;
}
@@ -189,7 +189,7 @@ int gen12_em
Re: [PATCH v4 2/5] clk: qcom: gdsc: Support 'synced_poweroff' genpd flag
On Wed, 21 Dec 2022 at 18:14, Akhil P Oommen wrote:
>
> Add support for the newly added 'synced_poweroff' genpd flag. This allows
> some clients (like adreno gpu driver) to request gdsc driver to ensure
> a votable gdsc (like gpucc cx gdsc) has collapsed at hardware.
>
> Signed-off-by: Akhil P Oommen
Reviewed-by: Ulf Hansson
Kind regards
Uffe
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - Rename the var 'force_sync' to 'wait (Stephen)
>
> drivers/clk/qcom/gdsc.c | 11 ++-
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
> index 9e4d6ce891aa..5358e28122ab 100644
> --- a/drivers/clk/qcom/gdsc.c
> +++ b/drivers/clk/qcom/gdsc.c
> @@ -136,7 +136,8 @@ static int gdsc_update_collapse_bit(struct gdsc *sc, bool
> val)
> return 0;
> }
>
> -static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
> +static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status,
> + bool wait)
> {
> int ret;
>
> @@ -149,7 +150,7 @@ static int gdsc_toggle_logic(struct gdsc *sc, enum
> gdsc_status status)
> ret = gdsc_update_collapse_bit(sc, status == GDSC_OFF);
>
> /* If disabling votable gdscs, don't poll on status */
> - if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
> + if ((sc->flags & VOTABLE) && status == GDSC_OFF && !wait) {
> /*
> * Add a short delay here to ensure that an enable
> * right after it was disabled does not put it in an
> @@ -275,7 +276,7 @@ static int gdsc_enable(struct generic_pm_domain *domain)
> gdsc_deassert_clamp_io(sc);
> }
>
> - ret = gdsc_toggle_logic(sc, GDSC_ON);
> + ret = gdsc_toggle_logic(sc, GDSC_ON, false);
> if (ret)
> return ret;
>
> @@ -352,7 +353,7 @@ static int gdsc_disable(struct generic_pm_domain *domain)
> if (sc->pwrsts == PWRSTS_RET_ON)
> return 0;
>
> - ret = gdsc_toggle_logic(sc, GDSC_OFF);
> + ret = gdsc_toggle_logic(sc, GDSC_OFF, domain->synced_poweroff);
> if (ret)
> return ret;
>
> @@ -392,7 +393,7 @@ static int gdsc_init(struct gdsc *sc)
>
> /* Force gdsc ON if only ON state is supported */
> if (sc->pwrsts == PWRSTS_ON) {
> - ret = gdsc_toggle_logic(sc, GDSC_ON);
> + ret = gdsc_toggle_logic(sc, GDSC_ON, false);
> if (ret)
> return ret;
> }
> --
> 2.7.4
>
Re: [PATCH v4 4/5] drm/msm/a6xx: Remove cx gdsc polling using 'reset'
On Wed, 21 Dec 2022 at 18:14, Akhil P Oommen wrote:
>
> Remove the unused 'reset' interface which was supposed to help to ensure
> that cx gdsc has collapsed during gpu recovery. This is was not enabled
> so far due to missing gpucc driver support. Similar functionality using
> genpd framework will be implemented in the upcoming patch.
>
> This effectively reverts commit 1f6cca404918
> ("drm/msm/a6xx: Ensure CX collapse during gpu recovery").
>
> Signed-off-by: Akhil P Oommen
Reviewed-by: Ulf Hansson
Kind regards
Uffe
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - Updated commit msg (Philipp)
>
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4
> drivers/gpu/drm/msm/msm_gpu.c | 4
> drivers/gpu/drm/msm/msm_gpu.h | 4
> 3 files changed, 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 36c8fb699b56..4b16e75dfa50 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -10,7 +10,6 @@
>
> #include
> #include
> -#include
> #include
>
> #define GPU_PAS_ID 13
> @@ -1298,9 +1297,6 @@ static void a6xx_recover(struct msm_gpu *gpu)
> /* And the final one from recover worker */
> pm_runtime_put_sync(&gpu->pdev->dev);
>
> - /* Call into gpucc driver to poll for cx gdsc collapse */
> - reset_control_reset(gpu->cx_collapse);
> -
> pm_runtime_use_autosuspend(&gpu->pdev->dev);
>
> if (active_submits)
> diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
> index 30ed45af76ad..97e1319d4577 100644
> --- a/drivers/gpu/drm/msm/msm_gpu.c
> +++ b/drivers/gpu/drm/msm/msm_gpu.c
> @@ -16,7 +16,6 @@
> #include
> #include
> #include
> -#include
> #include
>
> /*
> @@ -933,9 +932,6 @@ int msm_gpu_init(struct drm_device *drm, struct
> platform_device *pdev,
> if (IS_ERR(gpu->gpu_cx))
> gpu->gpu_cx = NULL;
>
> - gpu->cx_collapse =
> devm_reset_control_get_optional_exclusive(&pdev->dev,
> - "cx_collapse");
> -
> gpu->pdev = pdev;
> platform_set_drvdata(pdev, &gpu->adreno_smmu);
>
> diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
> index 651786bc55e5..fa9e34d02c91 100644
> --- a/drivers/gpu/drm/msm/msm_gpu.h
> +++ b/drivers/gpu/drm/msm/msm_gpu.h
> @@ -13,7 +13,6 @@
> #include
> #include
> #include
> -#include
>
> #include "msm_drv.h"
> #include "msm_fence.h"
> @@ -282,9 +281,6 @@ struct msm_gpu {
> bool hw_apriv;
>
> struct thermal_cooling_device *cooling;
> -
> - /* To poll for cx gdsc collapse during gpu recovery */
> - struct reset_control *cx_collapse;
> };
>
> static inline struct msm_gpu *dev_to_gpu(struct device *dev)
> --
> 2.7.4
>
Re: [PATCH v4 5/5] drm/msm/a6xx: Use genpd notifier to ensure cx-gdsc collapse
On Wed, 21 Dec 2022 at 18:14, Akhil P Oommen wrote:
>
> As per the recommended recovery sequence of adreno gpu, cx gdsc should
> collapse at hardware before it is turned back ON. This helps to clear
> out the stale states in hardware before it is reinitialized. Use the
> genpd notifier along with the newly introduced
> dev_pm_genpd_synced_poweroff() api to ensure that cx gdsc has collapsed
> before we turn it back ON.
>
> Signed-off-by: Akhil P Oommen
Reviewed-by: Ulf Hansson
Kind regards
Uffe
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - Select PM_GENERIC_DOMAINS from Kconfig
>
> drivers/gpu/drm/msm/Kconfig | 1 +
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 15 +++
> drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 6 ++
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 +++
> 4 files changed, 33 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
> index 3c9dfdb0b328..74f5916f5ca5 100644
> --- a/drivers/gpu/drm/msm/Kconfig
> +++ b/drivers/gpu/drm/msm/Kconfig
> @@ -28,6 +28,7 @@ config DRM_MSM
> select SYNC_FILE
> select PM_OPP
> select NVMEM
> + select PM_GENERIC_DOMAINS
> help
> DRM/KMS driver for MSM/snapdragon.
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index 1580d0090f35..c03830957c26 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> @@ -1507,6 +1507,17 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
> gmu->initialized = false;
> }
>
> +static int cxpd_notifier_cb(struct notifier_block *nb,
> + unsigned long action, void *data)
> +{
> + struct a6xx_gmu *gmu = container_of(nb, struct a6xx_gmu, pd_nb);
> +
> + if (action == GENPD_NOTIFY_OFF)
> + complete_all(&gmu->pd_gate);
> +
> + return 0;
> +}
> +
> int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
> {
> struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
> @@ -1640,6 +1651,10 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct
> device_node *node)
> goto detach_cxpd;
> }
>
> + init_completion(&gmu->pd_gate);
> + complete_all(&gmu->pd_gate);
> + gmu->pd_nb.notifier_call = cxpd_notifier_cb;
> +
> /*
> * Get a link to the GX power domain to reset the GPU in case of GMU
> * crash
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
> index 5a42dd4dd31f..0bc3eb443fec 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
> @@ -4,8 +4,10 @@
> #ifndef _A6XX_GMU_H_
> #define _A6XX_GMU_H_
>
> +#include
> #include
> #include
> +#include
> #include "msm_drv.h"
> #include "a6xx_hfi.h"
>
> @@ -90,6 +92,10 @@ struct a6xx_gmu {
> bool initialized;
> bool hung;
> bool legacy; /* a618 or a630 */
> +
> + /* For power domain callback */
> + struct notifier_block pd_nb;
> + struct completion pd_gate;
> };
>
> static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 4b16e75dfa50..dd618b099110 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -10,6 +10,7 @@
>
> #include
> #include
> +#include
> #include
>
> #define GPU_PAS_ID 13
> @@ -1258,6 +1259,7 @@ static void a6xx_recover(struct msm_gpu *gpu)
> {
> struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
> + struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
> int i, active_submits;
>
> adreno_dump_info(gpu);
> @@ -1290,6 +1292,10 @@ static void a6xx_recover(struct msm_gpu *gpu)
> */
> gpu->active_submits = 0;
>
> + reinit_completion(&gmu->pd_gate);
> + dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb);
> + dev_pm_genpd_synced_poweroff(gmu->cxpd);
> +
> /* Drop the rpm refcount from active submits */
> if (active_submits)
> pm_runtime_put(&gpu->pdev->dev);
> @@ -1297,6 +1303,11 @@ static void a6xx_recover(struct msm_gpu *gpu)
> /* And the final one from recover worker */
> pm_runtime_put_sync(&gpu->pdev->dev);
>
> + if (!wait_for_completion_timeout(&gmu->pd_gate,
> msecs_to_jiffies(1000)))
> + DRM_DEV_ERROR(&gpu->pdev->dev, "cx gdsc didn't collapse\n");
> +
> + dev_pm_genpd_remove_notifier(gmu->cxpd);
> +
> pm_runtime_use_autosuspend(&gpu->pdev->dev);
>
> if (active_submits)
> --
> 2.7.4
>
Re: [PATCH v4 3/5] drm/msm/a6xx: Vote for cx gdsc from gpu driver
On Wed, 21 Dec 2022 at 18:14, Akhil P Oommen wrote:
>
> When a device has multiple power domains, dev->power_domain is left
> empty during probe. That didn't cause any issue so far because we are
> freeloading on smmu driver's vote on cx gdsc. Instead of that, create
> a device_link between cx genpd device and gmu device to keep a vote from
> gpu driver.
>
> Before this patch:
> localhost ~ # cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
> gx_gdsc on 0
> /devices/genpd:1:3d6a000.gmuactive 0
> cx_gdsc on 0
> /devices/platform/soc@0/3da.iommu active 0
>
> After this patch:
> localhost ~ # cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
> gx_gdsc on 0
> /devices/genpd:1:3d6a000.gmuactive 0
> cx_gdsc on 0
> /devices/platform/soc@0/3da.iommu active 0
> /devices/genpd:0:3d6a000.gmuactive 0
>
> Signed-off-by: Akhil P Oommen
Reviewed-by: Ulf Hansson
Kind regards
Uffe
> ---
>
> (no changes since v1)
>
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 31 +++
> drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 +
> 2 files changed, 28 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index 6484b97c5344..1580d0090f35 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> @@ -1479,6 +1479,12 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
>
> pm_runtime_force_suspend(gmu->dev);
>
> + /*
> +* Since cxpd is a virt device, the devlink with gmu-dev will be
> removed
> +* automatically when we do detach
> +*/
> + dev_pm_domain_detach(gmu->cxpd, false);
> +
> if (!IS_ERR_OR_NULL(gmu->gxpd)) {
> pm_runtime_disable(gmu->gxpd);
> dev_pm_domain_detach(gmu->gxpd, false);
> @@ -1605,8 +1611,10 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct
> device_node *node)
>
> if (adreno_is_a650_family(adreno_gpu)) {
> gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
> - if (IS_ERR(gmu->rscc))
> + if (IS_ERR(gmu->rscc)) {
> + ret = -ENODEV;
> goto err_mmio;
> + }
> } else {
> gmu->rscc = gmu->mmio + 0x23000;
> }
> @@ -1615,8 +1623,22 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct
> device_node *node)
> gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq);
> gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq);
>
> - if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0)
> + if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) {
> + ret = -ENODEV;
> + goto err_mmio;
> + }
> +
> + gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx");
> + if (IS_ERR(gmu->cxpd)) {
> + ret = PTR_ERR(gmu->cxpd);
> goto err_mmio;
> + }
> +
> + if (!device_link_add(gmu->dev, gmu->cxpd,
> + DL_FLAG_PM_RUNTIME)) {
> + ret = -ENODEV;
> + goto detach_cxpd;
> + }
>
> /*
> * Get a link to the GX power domain to reset the GPU in case of GMU
> @@ -1634,6 +1656,9 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct
> device_node *node)
>
> return 0;
>
> +detach_cxpd:
> + dev_pm_domain_detach(gmu->cxpd, false);
> +
> err_mmio:
> iounmap(gmu->mmio);
> if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
> @@ -1641,8 +1666,6 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct
> device_node *node)
> free_irq(gmu->gmu_irq, gmu);
> free_irq(gmu->hfi_irq, gmu);
>
> - ret = -ENODEV;
> -
> err_memory:
> a6xx_gmu_memory_free(gmu);
> err_put_device:
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
> index e034935b3986..5a42dd4dd31f 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
> @@ -56,6 +56,7 @@ struct a6xx_gmu {
> int gmu_irq;
>
> struct device *gxpd;
> + struct device *cxpd;
>
> int idle_level;
>
> --
> 2.7.4
>
Re: [PATCH v14 1/5] arm64: dts: qcom: add data-lanes and link-freuencies into dp_out endpoint
On 12/22/2022 2:47 AM, Krzysztof Kozlowski wrote:
On 16/12/2022 20:11, Kuogee Hsieh wrote:
Move data-lanes property from mdss_dp node to dp_out endpoint. Also
add link-frequencies property into dp_out endpoint as well. The last
frequency specified at link-frequencies will be the max link rate
supported by DP.
Changes in v5:
-- revert changes at sc7180.dtsi and sc7280.dtsi
-- add &dp_out to sc7180-trogdor.dtsi and sc7280-herobrine.dtsi
Changes in v6:
-- add data-lanes and link-frequencies to yaml
Changes in v7:
-- change 16000 to 162000
-- separate yaml to different patch
Changes in v8:
-- correct Bjorn mail address to kernel.org
Changes in v9:
-- use symbol rate (hz) for link-frequencies at dp_out at sc7180_trogdor.dtsi
Changes in v13:
-- delete an extra space at data-lanes
Signed-off-by: Kuogee Hsieh
---
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 6 +-
arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 4
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
index eae22e6..e2783dd 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
@@ -814,7 +814,11 @@ hp_i2c: &i2c9 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dp_hot_plug_det>;
- data-lanes = <0 1>;
+};
+
+&dp_out {
+data-lanes = <0 1>;
+link-frequencies = /bits/ 64 <162000 27 54>;
Messed order of nodes.
can you please give me more details and how should i fixed it?
Thanks,
};
&pm6150_adc {
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
index c11e371..3f363f8 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
@@ -442,7 +442,11 @@ ap_i2c_tpm: &i2c14 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dp_hot_plug_det>;
+};
+
+&dp_out {
Same problem here.
Best regards,
Krzysztof
Re: [PATCH v3 1/2] backlight: ktz8866: Add support for Kinetic KTZ8866 backlight
On Thu, Dec 22, 2022 at 08:54:40PM +0800, Jianhua Lu wrote:
> Add support for Kinetic KTZ8866 backlight, which is used in
> Xiaomi tablet, Mi Pad 5 series. This driver lightly based on
> downstream implementation [1].
> [1]
> https://github.com/MiCode/Xiaomi_Kernel_OpenSource/blob/elish-r-oss/drivers/video/backlight/ktz8866.c
>
> Signed-off-by: Jianhua Lu
> ---
> Changes in v2:
> - Add missing staitc modifier to ktz8866_write function.
>
> Changes in v3:
> - Add 2022 to Copyright line.
> - Sort headers
> - Remove meaningless comment
> - Use definitions instead of hardcoding.
> - Add missing maintainer info
>
> MAINTAINERS | 6 +
> drivers/video/backlight/Kconfig | 8 ++
> drivers/video/backlight/Makefile | 1 +
> drivers/video/backlight/ktz8866.c | 180 ++
> drivers/video/backlight/ktz8866.h | 31 +
> 5 files changed, 226 insertions(+)
> create mode 100644 drivers/video/backlight/ktz8866.c
> create mode 100644 drivers/video/backlight/ktz8866.h
>
> diff --git a/drivers/video/backlight/ktz8866.c
> b/drivers/video/backlight/ktz8866.c
> new file mode 100644
> index ..ea641bdfc4d2
> --- /dev/null
> +++ b/drivers/video/backlight/ktz8866.c
> @@ -0,0 +1,180 @@
> +
> +#define BL_EN_BIT BIT(6)
> +#define BL_CURRENT_SINKS 0x1F
> +#define BL_OVP_LIMIT 0x33
> +#define LED_CURRENT_RAMPING_TIME 0xBD
> +#define LED_DIMMING_TIME 0x11
> +#define LCD_BIAS_EN 0x9F
> +#define LED_CURRENT 0xF9
> +
> +#define low_3_bit(x) ((x)&0x7)
> +#define high_8_bit(x) ((x >> 3) & 0xFF)
These don't seem to be particularly useful. They are used exactly once
so I think it is better just to implement the shifts directly
in ktz8866_backlight_update_status().
> +struct ktz8866 {
> + struct i2c_client *client;
> + struct regmap *regmap;
> + bool state;
> +};
> +
> +enum {
> + LED_OFF,
> + LED_ON,
> +};
Let's remove this emum. It is better to rename state to
led_on in order to make the code read well:
if (ktz->led_on) ...
ktz->led_on = true;
ktz->led_on = false;
> +static void ktz8866_init(struct ktz8866 *ktz)
> +{
> + /* Enable 1~5 current sinks */
> + ktz8866_write(ktz, BL_EN, BL_CURRENT_SINKS);
> + /* Backlight OVP 26.4V */
> + ktz8866_write(ktz, BL_CFG1, BL_OVP_LIMIT);
> + /* LED current ramping time 128ms */
> + ktz8866_write(ktz, BL_CFG2, LED_CURRENT_RAMPING_TIME);
> + /* LED on/off ramping time 1ms */
> + ktz8866_write(ktz, BL_DIMMING, LED_DIMMING_TIME);
> + /* Enable OUTP and OUTN via pin ENP and ENN */
> + ktz8866_write(ktz, LCD_BIAS_CFG1, LCD_BIAS_EN);
> + /* Backlight Full-scale LED Current 30.0mA */
> + ktz8866_write(ktz, FULL_SCALE_CURRENT, LED_CURRENT);
> +}
Are these settings specific to the mipad 5 m/board? Many of these look
like they should be described in the devicetree rather than hardcoded
in the driver.
> +static int ktz8866_probe(struct i2c_client *client,
> + const struct i2c_device_id *id)
> +{
> + struct backlight_device *backlight_dev;
> + struct backlight_properties props;
> + struct ktz8866 *ktz;
> +
> + ktz = devm_kzalloc(&client->dev, sizeof(*ktz), GFP_KERNEL);
> + if (!ktz)
> + return -ENOMEM;
> +
> + ktz->client = client;
> + ktz->regmap = devm_regmap_init_i2c(client, &ktz8866_regmap_config);
> +
> + if (IS_ERR(ktz->regmap)) {
> + dev_err(&client->dev, "failed to init regmap\n");
> + return PTR_ERR(ktz->regmap);
> + }
> +
> + memset(&props, 0, sizeof(props));
> + props.type = BACKLIGHT_RAW;
> + props.max_brightness = MAX_BRIGHTNESS;
> + props.brightness = clamp_t(unsigned int, DEFAULT_BRIGHTNESS, 0,
> +props.max_brightness);
Please set the scale property correctly. "Unknown" is never correct for
new drivers.
> + backlight_dev = devm_backlight_device_register(
> + &client->dev, "ktz8866-backlight", &client->dev, ktz,
> + &ktz8866_backlight_ops, &props);
> +
> + if (IS_ERR(backlight_dev)) {
> + dev_err(&client->dev, "failed to register backlight device\n");
> + return PTR_ERR(backlight_dev);
> + }
> +
> + ktz8866_init(ktz);
> +
> + i2c_set_clientdata(client, backlight_dev);
> + backlight_update_status(backlight_dev);
> +
> + return 0;
> +}
> diff --git a/drivers/video/backlight/ktz8866.h
> b/drivers/video/backlight/ktz8866.h
> new file mode 100644
> index ..b0ed8cbee608
> --- /dev/null
> +++ b/drivers/video/backlight/ktz8866.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Register definitions for Kinetic KTZ8866 backlight
> + *
> + * Copyright (C) 2022 Jianhua Lu
> + */
> +
> +#ifndef KTZ8866_H
> +#define KTZ8866_H
> +
> +#define DEVICE_ID 0x01
> +#define BL_CFG1 0x02
> +#define BL_CFG2 0x03
> +#define BL_BRT_LSB 0x04
> +#define BL_BRT_MSB 0x05
> +#define BL_EN 0x08
> +#define LCD_BIA
Re: [PATCH v4 0/7] Introduce debugfs device-centered functions
On Mon, Dec 19, 2022 at 11:49:47AM -0100, Melissa Wen wrote: > On 12/19, Maíra Canal wrote: > > This series introduces the initial structure to make DRM debugfs more > > device-centered and it is the first step to drop the > > drm_driver->debugfs_init hooks in the future [1]. > > > > Currently, DRM debugfs files are created using drm_debugfs_create_files() > > on request. The first patch of this series makes it possible for DRM devices > > for creating debugfs files during drm_dev_register(). For it, it introduces > > two new functions that can be used by the drivers: drm_debugfs_add_files() > > and drm_debugfs_add_file(). The requests are added to a list and are created > > all at once during drm_dev_register(). Moreover, the first patch was based > > on > > this RFC series [2]. > > > > The main difference between the RFC series and the current series is the > > creation of a new fops structure to accommodate the new structs and, also, > > the creation of a new drm_debugfs_open. Moreover, the new series uses > > device-managed allocation, returns memory allocation errors, and converts > > more drivers to the new structure. > > > > Moreover, since v3, the ability to create debugfs files at late_register > > hooks was > > added. In previous versions, modeset components weren't able to create > > debugfs > > files at late_register hooks as the registration of drm_minor happens > > before the > > registration of the modeset abstractions. So, the third patch fixes this > > problem > > by adding a drm_debugfs_late_register() function. Thanks to Melissa Wen for > > catching this problem! > > > > Apart from the third patch, the series looks similiar from its last version. > > > > [1] > > https://cgit.freedesktop.org/drm/drm/tree/Documentation/gpu/todo.rst#n506 > > [2] > > https://lore.kernel.org/dri-devel/20200513114130.28641-2-wambui.karu...@gmail.com/ > > > > Best Regards, > > - Maíra Canal > > > > --- > > > > v1 -> v2: > > https://lore.kernel.org/dri-devel/20221122190314.185015-1-mca...@igalia.com/T/#t > > > > - Fix compilation errors in the second patch (kernel test robot). > > - Drop debugfs_init hook from vkms (Maíra Canal). > > - Remove return values and error handling to debugfs related > > functions (Jani Nikula). > > - Remove entry from list after the file is created, so that drm_debugfs_init > > can be called more than once (Maíra Canal). > > > > v2 -> v3: > > https://lore.kernel.org/dri-devel/20221123220725.1272155-1-mca...@igalia.com/ > > > > - Rebase on top of drm-misc-next > > > > v3 -> v4: > > https://lore.kernel.org/dri-devel/20221207132325.140393-1-mca...@igalia.com/ > > > > - Add Maxime's Reviewed-by tags > > - Add the ability to create debugfs files at late_register hooks (Melissa > > Wen). > > Hi Maíra, > > Thanks for addressing all comments. > > Maybe Danvet has some inputs for the late_register approach. I think as a stop-gap (really need to get this stuff landed so people can start to use it) this is ok, but long term I think the right fix is to roll out the same pre-register infrastructure for connector and crtc too. That way drivers don't need to split their setup code into init and register anymore, which is the point of this entire rework. If you want, you can adjust the todo accordingly, but we do already have the paragraph about connector/crtc. But we can do that later on, because this is definitely a great way forward. Thanks a lot for pushing this forward! > Anyway, LGTM and the entire series is: > > Reviewed-by: Melissa Wen On the series: Acked-by: Daniel Vetter > > > > > --- > > > > Maíra Canal (7): > > drm/debugfs: create device-centered debugfs functions > > drm: use new debugfs device-centered functions on DRM core files > > drm/debugfs: create debugfs late register functions > > drm/vc4: use new debugfs device-centered functions > > drm/v3d: use new debugfs device-centered functions > > drm/vkms: use new debugfs device-centered functions > > drm/todo: update the debugfs clean up task > > > > Documentation/gpu/todo.rst| 9 +-- > > drivers/gpu/drm/drm_atomic.c | 11 ++- > > drivers/gpu/drm/drm_client.c | 11 ++- > > drivers/gpu/drm/drm_debugfs.c | 102 +++--- > > drivers/gpu/drm/drm_drv.c | 3 + > > drivers/gpu/drm/drm_framebuffer.c | 11 ++- > > drivers/gpu/drm/drm_gem_vram_helper.c | 11 ++- > > drivers/gpu/drm/drm_internal.h| 5 ++ > > drivers/gpu/drm/drm_mode_config.c | 2 + > > drivers/gpu/drm/v3d/v3d_debugfs.c | 22 +++--- > > drivers/gpu/drm/vc4/vc4_bo.c | 10 +-- > > drivers/gpu/drm/vc4/vc4_crtc.c| 7 +- > > drivers/gpu/drm/vc4/vc4_debugfs.c | 36 ++--- > > drivers/gpu/drm/vc4/vc4_dpi.c | 5 +- > > drivers/gpu/drm/vc4/vc4_drv.c | 1 - > > drivers/gpu/drm/vc4/vc4_drv.h | 32 ++-- > > drivers/gpu/drm/vc4/vc4_dsi.c | 6 +- > > drivers/gpu/drm/vc4/v
Re: [PATCH 00/19] Introduce __xchg, non-atomic xchg
On Thu, 22 Dec 2022 12:46:16 +0100 Andrzej Hajda wrote: > Hi all, > > I hope there will be place for such tiny helper in kernel. > Quick cocci analyze shows there is probably few thousands places > where it could be useful. So to clarify, the intent here is a simple readability cleanup for existing open-coded exchange operations. The intent is *not* to identify existing xchg() sites which are unnecessarily atomic and to optimize them by using the non-atomic version. Have you considered the latter? > I am not sure who is good person to review/ack such patches, I can take 'em. > so I've used my intuition to construct to/cc lists, sorry for mistakes. > This is the 2nd approach of the same idea, with comments addressed[0]. > > The helper is tiny and there are advices we can leave without it, so > I want to present few arguments why it would be good to have it: > > 1. Code readability/simplification/number of lines: > > Real example from drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c: > - previous_min_rate = evport->qos.min_rate; > - evport->qos.min_rate = min_rate; > + previous_min_rate = __xchg(evport->qos.min_rate, min_rate); > > For sure the code is more compact, and IMHO more readable. > > 2. Presence of similar helpers in other somehow related languages/libs: > > a) Rust[1]: 'replace' from std::mem module, there is also 'take' > helper (__xchg(&x, 0)), which is the same as private helper in > i915 - fetch_and_zero, see latest patch. > b) C++ [2]: 'exchange' from utility header. > > If the idea is OK there are still 2 qestions to answer: > > 1. Name of the helper, __xchg follows kernel conventions, > but for me Rust names are also OK. I like replace(), or, shockingly, exchange(). But... Can we simply make swap() return the previous value? previous_min_rate = swap(&evport->qos.min_rate, min_rate);
Re: [PATCH] drm: override detected status for connectors which are forced on
Hi,
On Thu, Dec 15, 2022 at 06:03:59PM +0100, Michael Rodin wrote:
> The detected status of a connector should be ignored when a connector is
> forced as hinted in the commit d50ba256b5f1 ("drm/kms: start
> adding command line interface using fb."). One negative side effect of
> not ignoring this is observed on the RCar3 SoCs which use the dw-hdmi
> driver. It continues executing drm_helper_hpd_irq_event even if its
> connector is forced to ON. As consequence drm_helper_hpd_irq_event calls
> "detect" so the connector status is updated to "disconnected":
>
> [ 420.201527] [drm:drm_helper_hpd_irq_event] [CONNECTOR:76:HDMI-A-1] status
> updated from connected to disconnected
>
> This status is corrected by drm_helper_probe_single_connector_modes shortly
> after this because this function checks if a connector is forced:
>
> [ 420.218703] [drm:drm_helper_probe_single_connector_modes]
> [CONNECTOR:76:HDMI-A-1] status updated from disconnected to connected
>
> To avoid similar issues this commit adapts functions which call "detect"
> so they check additionally if a connector is forced and override the status
> returned by "detect".
>
> Fixes: 816da85a0990 ("drm: handle HPD and polled connectors separately")
> Signed-off-by: Michael Rodin
As reported here, this breaks vc4, and probably i915:
https://lore.kernel.org/dri-devel/20221107123657.24vbgep3jqeklb2s@houat/
Maxime
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