[PATCH] drm/modes: Fix outdated drm_mode_vrefresh return value documentation
The vrefresh field in drm_display_mode struct was removed so the
function no longer checks if it is set before calculating it.
Fixes: 0425662fdf05 ("drm: Nuke mode->vrefresh")
Signed-off-by: Jonathan Liu
---
drivers/gpu/drm/drm_modes.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 3c8034a8c27b..2d51ab2734a0 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -803,8 +803,7 @@ EXPORT_SYMBOL(drm_mode_set_name);
* @mode: mode
*
* Returns:
- * @modes's vrefresh rate in Hz, rounded to the nearest integer. Calculates the
- * value first if it is not yet set.
+ * @modes's vrefresh rate in Hz, rounded to the nearest integer.
*/
int drm_mode_vrefresh(const struct drm_display_mode *mode)
{
--
2.38.1
Re: [PATCH 1/2] dt-bindings: display/msm: add support for the display
On Sun, 20 Nov 2022 14:37:36 +0100, Adam Skladowski wrote:
> Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm
> SM6115 platform.
> Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused.
> Lack of dsi phy supply in example is intended
> due to fact on qcm2290, sm6115 and sm6125
> this phy is supplied via power domain, not regulator.
>
> Signed-off-by: Adam Skladowski
> ---
> .../bindings/display/msm/qcom,sm6115-dpu.yaml | 87
> .../display/msm/qcom,sm6115-mdss.yaml | 187 ++
> 2 files changed, 274 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml
> create mode 100644
> Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
./Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml: Unable to
find schema file matching $id:
http://devicetree.org/schemas/display/msm/dpu-common.yaml
./Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml: Unable
to find schema file matching $id:
http://devicetree.org/schemas/display/msm/mdss-common.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.example.dtb:
display-controller@5e01000: False schema does not allow {'compatible':
['qcom,sm6115-dpu'], 'reg': [[98570240, 585728], [99287040, 8200]],
'reg-names': ['mdp', 'vbif'], 'clocks': [[4294967295, 63], [4294967295, 2],
[4294967295, 10], [4294967295, 12], [4294967295, 16], [4294967295, 18]],
'clock-names': ['bus', 'iface', 'core', 'lut', 'rot', 'vsync'],
'operating-points-v2': [[4294967295]], 'power-domains': [[4294967295, 0]],
'interrupts': [[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]],
'port@0': {'reg': [[0]], 'endpoint': {'remote-endpoint': [[4294967295]]}}},
'$nodename': ['display-controller@5e01000']}
From schema:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.example.dtb:
display-controller@5e01000: Unevaluated properties are not allowed
('interrupts', 'operating-points-v2', 'ports', 'power-domains' were unexpected)
From schema:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.example.dtb:
mdss@5e0: False schema does not allow {'#address-cells': [[1]],
'#size-cells': [[1]], 'compatible': ['qcom,sm6115-mdss'], 'reg': [[98566144,
4096]], 'reg-names': ['mdss'], 'power-domains': [[4294967295, 0]], 'clocks':
[[4294967295, 61], [4294967295, 63], [4294967295, 10]], 'clock-names':
['iface', 'bus', 'core'], 'interrupts': [[0, 186, 4]], 'interrupt-controller':
True, '#interrupt-cells': [[1]], 'iommus': [[4294967295, 1056, 2], [4294967295,
1057, 0]], 'ranges': True, 'display-controller@5e01000': {'compatible':
['qcom,sm6115-dpu'], 'reg': [[98570240, 585728], [99287040, 8200]],
'reg-names': ['mdp', 'vbif'], 'clocks': [[4294967295, 63], [4294967295, 2],
[4294967295, 10], [4294967295, 12], [4294967295, 16], [4294967295, 18]],
'clock-names': ['bus', 'iface', 'core', 'lut', 'rot', 'vsync'],
'operating-points-v2': [[4294967295]], 'power-domains': [[4294967295, 0]], 'int
errupts': [[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]],
'port@0': {'reg': [[0]], 'endpoint': {'remote-endpoint': [[1]], 'phandle':
[[3]], 'dsi@5e94000': {'compatible': ['qcom,dsi-ctrl-6g-qcm2290'], 'reg':
[[99172352, 1024]], 'reg-names': ['dsi_ctrl'], 'interrupts': [[4]], 'clocks':
[[4294967295, 4], [4294967295, 7], [4294967295, 14], [4294967295, 8],
[4294967295, 2], [4294967295, 63]], 'clock-names': ['byte', 'byte_intf',
'pixel', 'core', 'iface', 'bus'], 'assigned-clocks': [[4294967295, 5],
[4294967295, 15]], 'assigned-clock-parents': [[2, 0], [2, 1]],
'operating-points-v2': [[4294967295]], 'power-domains': [[4294967295, 0]],
'phys': [[2]], 'phy-names': ['dsi'], '#address-cells': [[1]], '#size-cells':
[[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0':
{'reg': [[0]], 'endpoint': {'remote-endpoint': [[3]], 'phandle': [[1]]}},
'port@1': {'reg': [[1]], 'endpoint': {, 'phy@5e94400': {'compatible':
['qcom,dsi-phy-14nm-2290'], 'reg': [[9917
3376, 256], [99173632, 768], [99174400, 392]], 'reg-names': ['dsi_phy',
'dsi_phy_lane', 'dsi_pll'], '#clock-cells': [[1]], '#phy-cells': [[0]],
'clocks': [[4294967295, 2], [4294967295, 0]], 'clock-names': ['iface', 'ref'],
'phandle': [[2]]}, '$nodename': ['mdss@5e0']}
From schema:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss
[PATCH 1/2] dt-bindings: display/msm: add support for the display
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm
SM6115 platform.
Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused.
Lack of dsi phy supply in example is intended
due to fact on qcm2290, sm6115 and sm6125
this phy is supplied via power domain, not regulator.
Signed-off-by: Adam Skladowski
---
.../bindings/display/msm/qcom,sm6115-dpu.yaml | 87
.../display/msm/qcom,sm6115-mdss.yaml | 187 ++
2 files changed, 274 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml
new file mode 100644
index ..cc77675ec4f6
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DPU dt properties for SM6115 target
+
+maintainers:
+ - Dmitry Baryshkov
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+items:
+ - const: qcom,sm6115-dpu
+
+ reg:
+items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+items:
+ - description: Display AXI clock from gcc
+ - description: Display AHB clock from dispcc
+ - description: Display core clock from dispcc
+ - description: Display lut clock from dispcc
+ - description: Display rotator clock from dispcc
+ - description: Display vsync clock from dispcc
+
+ clock-names:
+items:
+ - const: bus
+ - const: iface
+ - const: core
+ - const: lut
+ - const: rot
+ - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+display-controller@5e01000 {
+compatible = "qcom,sm6115-dpu";
+reg = <0x05e01000 0x8f000>,
+ <0x05eb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
+
+operating-points-v2 = <&mdp_opp_table>;
+power-domains = <&rpmpd SM6115_VDDCX>;
+
+interrupt-parent = <&mdss>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+endpoint {
+remote-endpoint = <&dsi0_in>;
+};
+};
+};
+};
+...
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
new file mode 100644
index ..af721aa05b22
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
@@ -0,0 +1,187 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6115 Display MDSS
+
+maintainers:
+ - Dmitry Baryshkov
+
+description:
+ Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
+ sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
+ are mentioned for SM6115 target.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+items:
+ - const: qcom,sm6115-mdss
+
+ clocks:
+items:
+ - description: Display AHB clock from gcc
+ - description: Display AXI clock
+ - description: Display core clock
+
+ clock-names:
+items:
+ - const: iface
+ - const: bus
+ - const: core
+
+ iommus:
+maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,sm6115-dpu
+
+ "^dsi@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,dsi-ctrl-6g-qcm2290
+
+ "^phy@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,dsi-phy-14nm-2290
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+
+mdss@5e0 {
+#address-c
[PATCH 2/2] drm/msm/disp/dpu1: add support for display on SM6115
Add required display hw catalog changes for SM6115.
Signed-off-by: Adam Skladowski
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 87 +++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
drivers/gpu/drm/msm/msm_mdss.c| 5 ++
4 files changed, 94 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 1ce237e18506..4fed544c1356 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -321,6 +321,18 @@ static const struct dpu_caps sc7180_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
+static const struct dpu_caps sm6115_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0x4,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_20,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = 2160,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
static const struct dpu_caps sm8150_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
@@ -475,6 +487,19 @@ static const struct dpu_mdp_cfg sc8180x_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sm6115_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .highest_bank_bit = 0x1,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x2AC, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x2AC, .bit_off = 8},
+ },
+};
+
static const struct dpu_mdp_cfg sm8250_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -852,6 +877,16 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
};
+static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
+ _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED3LITE);
+
+static const struct dpu_sspp_cfg sm6115_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
+ sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+};
+
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
_VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
@@ -1590,6 +1625,35 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
.bw_inefficiency_factor = 120,
};
+static const struct dpu_perf_cfg sm6115_perf_data = {
+ .max_bw_low = 310,
+ .max_bw_high = 400,
+ .min_core_ib = 240,
+ .min_llcc_ib = 80,
+ .min_dram_ib = 80,
+ .min_prefill_lines = 24,
+ .danger_lut_tbl = {0xff, 0x, 0x0},
+ .safe_lut_tbl = {0xfff0, 0xff00, 0x},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sc7180_qos_linear),
+ .entries = sc7180_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+ .entries = sc7180_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ /* TODO: macrotile-qseed is different from macrotile */
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
static const struct dpu_perf_cfg sm8150_perf_data = {
.max_bw_low = 1280,
.max_bw_high = 1280,
@@ -1801,6 +1865,28 @@ static const struct dpu_mdss_cfg sc7180_dpu_cfg = {
.mdss_irqs = IRQ_SC7180_MASK,
};
+static const struct dpu_mdss_cfg sm6115_dpu_cfg = {
+ .caps = &sm6115_dpu_caps,
+ .mdp_count = ARRAY_SIZE(sm6115_mdp),
+ .mdp = sm6115_mdp,
+ .ctl_count = ARRAY_SIZE(qcm2290_ctl),
+ .ctl = qcm2290_ctl,
+ .sspp_count = ARRAY_SIZE(sm6115_sspp),
+ .sspp = sm6115_sspp,
+ .mixer_count = ARRAY_SIZE(qcm2290_lm),
+ .mixer = qcm2290_lm,
+ .dspp_count = ARRAY_SIZE(qcm2290_dspp),
+ .dspp = qcm2290_dspp,
+ .pingpong_count = ARRAY_SIZE(qcm2290_pp),
+ .pingpong = qcm2290_pp,
+ .intf_count = ARRAY_SIZE(qcm2290_intf),
+ .intf = qcm2290_intf,
+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
+ .vbif = sdm845_vbif,
+ .perf = &sm6115_perf_data,
+ .mdss_irqs = IRQ_SC7180_MASK,
+};
+
static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
.caps = &sm8150_dpu_caps,
[PATCH] drm/vc4: Fix NULL pointer access in vc4_platform_drm_probe()
From: Lino Sanfilippo
In vc4_platform_drm_probe() function vc4_match_add_drivers() is called to
find component matches for the component drivers. If no such match is found
the passed variable "match" is still NULL after the function returns.
Do not pass "match" to component_master_add_with_match() in this case since
this results in a NULL pointer access as soon as match->num is used to
allocate a component_match array. Instead return with -ENODEV from the
drivers probe function.
Fixes: c8b75bca92cb ("drm/vc4: Add KMS support for Raspberry Pi.")
Cc: sta...@vger.kernel.org
Signed-off-by: Lino Sanfilippo
---
drivers/gpu/drm/vc4/vc4_drv.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
index 2027063fdc30..2e53d7f8ad44 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.c
+++ b/drivers/gpu/drm/vc4/vc4_drv.c
@@ -437,6 +437,9 @@ static int vc4_platform_drm_probe(struct platform_device
*pdev)
vc4_match_add_drivers(dev, &match,
component_drivers, ARRAY_SIZE(component_drivers));
+ if (!match)
+ return -ENODEV;
+
return component_master_add_with_match(dev, &vc4_drm_ops, match);
}
base-commit: 30a0b95b1335e12efef89dd78518ed3e4a71a763
--
2.36.1
[PATCH 0/2] Add SM6115 MDSS/DPU support
This patch series add support for MDSS and DPU block found on SM6115. These patches were tested on Xiaomi Redmi 9T smartphone. Adam Skladowski (2): dt-bindings: display/msm: add support for the display on SM6115 drm/msm/disp/dpu1: add support for display on SM6115 .../bindings/display/msm/qcom,sm6115-dpu.yaml | 87 .../display/msm/qcom,sm6115-mdss.yaml | 187 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 87 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_mdss.c| 5 + 6 files changed, 368 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml -- 2.25.1
Re: [PATCH v4 0/4] new subsystem for compute accelerator devices
On Sat, Nov 19, 2022 at 10:44:31PM +0200, Oded Gabbay wrote: > This is the fourth (and hopefully last) version of the patch-set to add the > new subsystem for compute accelerators. I removed the RFC headline as > I believe it is now ready for merging. > > Compare to v3, this patch-set contains one additional patch that adds > documentation regarding the accel subsystem. I hope it's good enough for > this stage. In addition, there were few very minor fixes according to > comments received on v3. > > The patches are in the following repo: > https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/accel.git/log/?h=accel_v4 > > As in v3, The HEAD of that branch is a commit adding a dummy driver that > registers an accel device using the new framework. This can be served > as a simple reference. Looks good, thanks for doing this: Reviewed-by: Greg Kroah-Hartman
Re: [PATCH 1/2] dt-bindings: display/msm: add support for the display
On Sun, Nov 20, 2022 at 02:37:36PM +0100, Adam Skladowski wrote:
> Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm
> SM6115 platform.
> Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused.
> Lack of dsi phy supply in example is intended
> due to fact on qcm2290, sm6115 and sm6125
> this phy is supplied via power domain, not regulator.
The subject needs 'sm6115' somewhere.
>
> Signed-off-by: Adam Skladowski
> ---
> .../bindings/display/msm/qcom,sm6115-dpu.yaml | 87
> .../display/msm/qcom,sm6115-mdss.yaml | 187 ++
> 2 files changed, 274 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml
> create mode 100644
> Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml
> b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml
> new file mode 100644
> index ..cc77675ec4f6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml
> @@ -0,0 +1,87 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Display DPU dt properties for SM6115 target
> +
> +maintainers:
> + - Dmitry Baryshkov
> +
> +$ref: /schemas/display/msm/dpu-common.yaml#
> +
> +properties:
> + compatible:
> +items:
> + - const: qcom,sm6115-dpu
> +
> + reg:
> +items:
> + - description: Address offset and size for mdp register set
> + - description: Address offset and size for vbif register set
Drop 'Address offset and size for'.
s/mdp/MDP/ ?
s/vbif/VBIF/ ?
> +
> + reg-names:
> +items:
> + - const: mdp
> + - const: vbif
> +
> + clocks:
> +items:
> + - description: Display AXI clock from gcc
> + - description: Display AHB clock from dispcc
> + - description: Display core clock from dispcc
> + - description: Display lut clock from dispcc
> + - description: Display rotator clock from dispcc
> + - description: Display vsync clock from dispcc
Source of the clock is outside the scope of the binding.
> +
> + clock-names:
> +items:
> + - const: bus
> + - const: iface
> + - const: core
> + - const: lut
> + - const: rot
> + - const: vsync
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> +#include
> +#include
> +#include
> +
> +display-controller@5e01000 {
> +compatible = "qcom,sm6115-dpu";
> +reg = <0x05e01000 0x8f000>,
> + <0x05eb 0x2008>;
> +reg-names = "mdp", "vbif";
> +
> +clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc DISP_CC_MDSS_ROT_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> +clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
> +
> +operating-points-v2 = <&mdp_opp_table>;
> +power-domains = <&rpmpd SM6115_VDDCX>;
> +
> +interrupt-parent = <&mdss>;
> +interrupts = <0>;
> +
> +ports {
> +#address-cells = <1>;
> +#size-cells = <0>;
> +
> +port@0 {
> +reg = <0>;
> +endpoint {
> +remote-endpoint = <&dsi0_in>;
> +};
> +};
> +};
> +};
> +...
> diff --git
> a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
> b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
> new file mode 100644
> index ..af721aa05b22
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
> @@ -0,0 +1,187 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM6115 Display MDSS
> +
> +maintainers:
> + - Dmitry Baryshkov
> +
> +description:
> + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that
> encapsulates
> + sub-blocks like DPU display controller and DSI. Device tree bindings of
> MDSS
> + are mentioned for SM6115 target.
> +
> +$ref: /schemas/display/msm/mdss-common.yaml#
> +
> +properties:
> + compatible:
> +items:
> + - const: qcom,sm6115-mdss
> +
> + clocks:
> +items:
> + - description: Display AHB clock from gcc
> + - description: Display AXI clock
> + - description: Display core clock
> +
> + clock-names:
> +items:
> + - const: iface
> + - const: bus
> + - const: core
> +
> + iommus:
> +maxItems:
Re: [PATCH] dt-bindings: msm/dsi: Don't require vdds-supply on 10nm PHY
On Wed, 16 Nov 2022 17:32:18 +0100, Konrad Dybcio wrote: > On some SoCs (hello SM6350) vdds-supply is not wired to any smd-rpm > or rpmh regulator, but instead powered by the VDD_MX/mx.lvl line, > which is voted for in the DSI ctrl node. > > Signed-off-by: Konrad Dybcio > --- > Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml | 1 - > 1 file changed, 1 deletion(-) > Acked-by: Rob Herring
Re: [6.1][regression] after commit dd80d9c8eecac8c516da5b240d01a35660ba6cb6 some games (Cyberpunk 2077, Forza Horizon 4/5) hang at start #forregzbot
[Note: this mail is primarily send for documentation purposes and/or for regzbot, my Linux kernel regression tracking bot. That's why I removed most or all folks from the list of recipients, but left any that looked like a mailing lists. These mails usually contain '#forregzbot' in the subject, to make them easy to spot and filter out.] On 14.11.22 14:22, Christian König wrote: > > I've found and fixed a few problems around the userptr handling which > might explain what you see here. > > A series of four patches starting with "drm/amdgpu: always register an > MMU notifier for userptr" is under review now. #regzbot monitor: https://lore.kernel.org/all/20221115133853.7950-1-christian.koe...@amd.com/ #regzbot fixed-by: fec8fdb54e8f
Re: [syzbot] inconsistent lock state in sync_info_debugfs_show
syzbot has bisected this issue to:
commit 997acaf6b4b59c6a9c259740312a69ea549cc684
Author: Mark Rutland
Date: Mon Jan 11 15:37:07 2021 +
lockdep: report broken irq restoration
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=115b350d88
start commit: 84368d882b96 Merge tag 'soc-fixes-6.1-3' of git://git.kern..
git tree: upstream
final oops: https://syzkaller.appspot.com/x/report.txt?x=135b350d88
console output: https://syzkaller.appspot.com/x/log.txt?x=155b350d88
kernel config: https://syzkaller.appspot.com/x/.config?x=6f4e5e9899396248
dashboard link: https://syzkaller.appspot.com/bug?extid=007bfe0f3330f6e1e7d1
syz repro: https://syzkaller.appspot.com/x/repro.syz?x=164376f988
C reproducer: https://syzkaller.appspot.com/x/repro.c?x=16cf096588
Reported-by: syzbot+007bfe0f3330f6e1e...@syzkaller.appspotmail.com
Fixes: 997acaf6b4b5 ("lockdep: report broken irq restoration")
For information about bisection process see: https://goo.gl/tpsmEJ#bisection
Re: [PATCH v4 2/4] accel: add dedicated minor for accelerator devices
On 11/19/2022 1:44 PM, Oded Gabbay wrote: diff --git a/drivers/accel/drm_accel.c b/drivers/accel/drm_accel.c index fac6ad6ac28e..703d40c4ff45 100644 --- a/drivers/accel/drm_accel.c +++ b/drivers/accel/drm_accel.c @@ -8,14 +8,25 @@ #include #include +#include Including xarray, but using idr This should be linux/idr.h This seems so minor, I don't think I advise spinning a v5 for it. If a v5 is warranted elsewhere, obviously fix this. If not, hopefully this can be fixed up by whoever applies it, or someone submits a follow up patch. Hopefully this is the only nit. I would like to see this merged. -Jeff
[Bug 213145] AMDGPU resets, timesout and crashes after "*ERROR* Waiting for fences timed out!"
https://bugzilla.kernel.org/show_bug.cgi?id=213145 Viktor (sgas...@gmail.com) changed: What|Removed |Added CC||sgas...@gmail.com --- Comment #29 from Viktor (sgas...@gmail.com) --- Same problem on Lenovo Thinkpad T14 Gen3 with Ryzen 7 and Radeon 680M. Spontaneous freezes on kernels 5.17.* and 6.0.*. Here is the log: Nov 20 22:31:39 calculate kernel: [drm:amdgpu_dm_commit_planes [amdgpu]] *ERROR* Waiting for fences timed out! Nov 20 22:31:39 calculate kernel: [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring sdma0 timeout, signaled seq=146659, emitted seq=146661 Nov 20 22:31:39 calculate kernel: [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process information: process pid 0 thread pid 0 Nov 20 22:31:39 calculate kernel: amdgpu :04:00.0: amdgpu: GPU reset begin! Nov 20 22:31:39 calculate kernel: [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx_0.0.0 timeout, signaled seq=986766, emitted seq=986766 Nov 20 22:31:39 calculate kernel: [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process information: process X pid 4963 thread X:cs0 pid 5224 Nov 20 22:31:39 calculate kernel: amdgpu :04:00.0: amdgpu: GPU reset begin! Nov 20 22:31:39 calculate kernel: amdgpu :04:00.0: amdgpu: Bailing on TDR for s_job:df2df, as another already in progress Nov 20 22:31:40 calculate kernel: amdgpu :04:00.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring kiq_2.1.0 test failed (-110) Nov 20 22:31:40 calculate kernel: [drm:gfx_v10_0_hw_fini [amdgpu]] *ERROR* KGQ disable failed Nov 20 22:31:40 calculate kernel: amdgpu :04:00.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring kiq_2.1.0 test failed (-110) Nov 20 22:31:40 calculate kernel: [drm:gfx_v10_0_hw_fini [amdgpu]] *ERROR* KCQ disable failed Nov 20 22:31:40 calculate kernel: [drm:gfx_v10_0_hw_fini [amdgpu]] *ERROR* failed to halt cp gfx Nov 20 22:31:40 calculate kernel: [drm] free PSP TMR buffer Nov 20 22:31:40 calculate kernel: amdgpu :04:00.0: amdgpu: MODE2 reset Nov 20 22:31:40 calculate kernel: amdgpu :04:00.0: amdgpu: GPU reset succeeded, trying to resume Nov 20 22:31:40 calculate kernel: [drm] PCIE GART of 512M enabled (table at 0x00F4008C9000). Nov 20 22:31:40 calculate kernel: [drm] PSP is resuming... Nov 20 22:31:40 calculate kernel: [drm] reserve 0xa0 from 0xf43f40 for PSP TMR Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: RAS: optional ras ta ucode is not available Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: RAP: optional rap ta ucode is not available Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: SECUREDISPLAY: securedisplay ta ucode is not available Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: SMU is resuming... Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: SMU is resumed successfully! Nov 20 22:31:41 calculate kernel: [drm] DMUB hardware initialized: version=0x041A Nov 20 22:31:41 calculate kernel: [drm] kiq ring mec 2 pipe 1 q 0 Nov 20 22:31:41 calculate kernel: [drm] VCN decode and encode initialized successfully(under DPG Mode). Nov 20 22:31:41 calculate kernel: [drm] JPEG decode initialized successfully. Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: ring gfx_0.0.0 uses VM inv eng 0 on hub 0 Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: ring comp_1.0.0 uses VM inv eng 1 on hub 0 Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: ring comp_1.1.0 uses VM inv eng 4 on hub 0 Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: ring comp_1.2.0 uses VM inv eng 5 on hub 0 Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: ring comp_1.3.0 uses VM inv eng 6 on hub 0 Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: ring comp_1.0.1 uses VM inv eng 7 on hub 0 Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: ring comp_1.1.1 uses VM inv eng 8 on hub 0 Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: ring comp_1.2.1 uses VM inv eng 9 on hub 0 Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: ring comp_1.3.1 uses VM inv eng 10 on hub 0 Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: ring kiq_2.1.0 uses VM inv eng 11 on hub 0 Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: ring sdma0 uses VM inv eng 12 on hub 0 Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: ring vcn_dec_0 uses VM inv eng 0 on hub 1 Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: ring vcn_enc_0.0 uses VM inv eng 1 on hub 1 Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: ring vcn_enc_0.1 uses VM inv eng 4 on hub 1 Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: ring jpeg_dec uses VM inv eng 5 on hub 1 Nov 20 22:31:41 calculate kernel: amdgpu :04:00.0: amdgpu: recover vram bo from shadow start Nov 20 22:31:41 calcu
Re: [PATCH v4 4/4] doc: add documentation for accel subsystem
On 11/19/2022 1:44 PM, Oded Gabbay wrote: Add an introduction section for the accel subsystem. Most of the relevant data is in the DRM documentation, so the introduction only presents the why of the new subsystem, how are the compute accelerators exposed to user-space and what changes need to be done in a standard DRM driver to register it to the new accel subsystem. Signed-off-by: Oded Gabbay --- Documentation/accel/index.rst| 17 + Documentation/accel/introduction.rst | 109 +++ Documentation/subsystem-apis.rst | 1 + MAINTAINERS | 1 + 4 files changed, 128 insertions(+) create mode 100644 Documentation/accel/index.rst create mode 100644 Documentation/accel/introduction.rst diff --git a/Documentation/accel/index.rst b/Documentation/accel/index.rst new file mode 100644 index ..2b43c9a7f67b --- /dev/null +++ b/Documentation/accel/index.rst @@ -0,0 +1,17 @@ +.. SPDX-License-Identifier: GPL-2.0 + + +Compute Accelerators + + +.. toctree:: + :maxdepth: 1 + + introduction + +.. only:: subproject and html + + Indices + === + + * :ref:`genindex` diff --git a/Documentation/accel/introduction.rst b/Documentation/accel/introduction.rst new file mode 100644 index ..5a3963eae973 --- /dev/null +++ b/Documentation/accel/introduction.rst @@ -0,0 +1,109 @@ +.. SPDX-License-Identifier: GPL-2.0 + + +Introduction + + +The Linux compute accelerators subsystem is designed to expose compute +accelerators in a common way to user-space and provide a common set of +functionality. + +These devices can be either stand-alone ASICs or IP blocks inside an SoC/GPU. +Although these devices are typically designed to accelerate Machine-Learning +and/or Deep-Learning computations, the accel layer is not limited to handling You use "DL" later on as a short form for Deep-Learning. It would be good to introduce that here. +these types of accelerators. + +typically, a compute accelerator will belong to one of the following Typically +categories: + +- Edge AI - doing inference at an edge device. It can be an embedded ASIC/FPGA, + or an IP inside a SoC (e.g. laptop web camera). These devices + are typically configured using registers and can work with or without DMA. + +- Inference data-center - single/multi user devices in a large server. This + type of device can be stand-alone or an IP inside a SoC or a GPU. It will + have on-board DRAM (to hold the DL topology), DMA engines and + command submission queues (either kernel or user-space queues). + It might also have an MMU to manage multiple users and might also enable + virtualization (SR-IOV) to support multiple VMs on the same device. In + addition, these devices will usually have some tools, such as profiler and + debugger. + +- Training data-center - Similar to Inference data-center cards, but typically + have more computational power and memory b/w (e.g. HBM) and will likely have + a method of scaling-up/out, i.e. connecting to other training cards inside + the server or in other servers, respectively. + +All these devices typically have different runtime user-space software stacks, +that are tailored-made to their h/w. In addition, they will also probably +include a compiler to generate programs to their custom-made computational +engines. Typically, the common layer in user-space will be the DL frameworks, +such as PyTorch and TensorFlow. + +Sharing code with DRM += + +Because this type of devices can be an IP inside GPUs or have similar +characteristics as those of GPUs, the accel subsystem will use the +DRM subsystem's code and functionality. i.e. the accel core code will +be part of the DRM subsystem and an accel device will be a new type of DRM +device. + +This will allow us to leverage the extensive DRM code-base and +collaborate with DRM developers that have experience with this type of +devices. In addition, new features that will be added for the accelerator +drivers can be of use to GPU drivers as well. + +Differentiation from GPUs += + +Because we want to prevent the extensive user-space graphic software stack +from trying to use an accelerator as a GPU, the compute accelerators will be +differentiated from GPUs by using a new major number and new device char files. + +Furthermore, the drivers will be located in a separate place in the kernel +tree - drivers/accel/. + +The accelerator devices will be exposed to the user space with the dedicated +261 major number and will have the following convention: + +- device char files - /dev/accel/accel* +- sysfs - /sys/class/accel/accel*/ +- debugfs - /sys/kernel/debug/accel/accel*/ + +Getting Started +=== + +First, read the DRM documentation. Not only it will explain how to write a new How about a link to the DRM documentation? +DRM driver but it w
Re: [PATCH v4 0/4] new subsystem for compute accelerator devices
On 11/19/2022 1:44 PM, Oded Gabbay wrote: This is the fourth (and hopefully last) version of the patch-set to add the new subsystem for compute accelerators. I removed the RFC headline as I believe it is now ready for merging. Compare to v3, this patch-set contains one additional patch that adds documentation regarding the accel subsystem. I hope it's good enough for this stage. In addition, there were few very minor fixes according to comments received on v3. The patches are in the following repo: https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/accel.git/log/?h=accel_v4 As in v3, The HEAD of that branch is a commit adding a dummy driver that registers an accel device using the new framework. This can be served as a simple reference. v1 cover letter: https://lkml.org/lkml/2022/10/22/544 v2 cover letter: https://lore.kernel.org/lkml/20221102203405.1797491-1-ogab...@kernel.org/T/ v3 cover letter: https://lore.kernel.org/lkml/20221106210225.2065371-1-ogab...@kernel.org/T/ Thanks, Oded. Reviewed-by: Jeffrey Hugo I have some nits. Nothing that I think should be a blocker for this series.
linux-next: manual merge of the drm tree with the drm-misc-fixes tree
Hi all,
Today's linux-next merge of the drm tree got a conflict in:
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
between commit:
b09d6acba1d9 ("drm/amdgpu: handle gang submit before VMID")
from the drm-misc-fixes tree and commits:
c5093cddf56b ("drm/amdgpu: drop the fence argument from amdgpu_vmid_grab")
940ca22b7ea9 ("drm/amdgpu: drop amdgpu_sync from amdgpu_vmid_grab v2")
1b2d5eda5ad7 ("drm/amdgpu: move explicit sync check into the CS")
1728baa7e4e6 ("drm/amdgpu: use scheduler dependencies for CS")
from the drm tree.
I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index abb99cff8b4b,032651a655f0..
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@@ -243,30 -242,18 +242,18 @@@ amdgpu_job_prepare_job(struct drm_sched
{
struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched);
struct amdgpu_job *job = to_amdgpu_job(sched_job);
- struct amdgpu_vm *vm = job->vm;
- struct dma_fence *fence;
+ struct dma_fence *fence = NULL;
int r;
- fence = amdgpu_sync_get_fence(&job->sync);
- if (fence && drm_sched_dependency_optimized(fence, s_entity)) {
- r = amdgpu_sync_fence(&job->sched_sync, fence);
- if (r)
- DRM_ERROR("Error adding fence (%d)\n", r);
- }
-
- if (!fence && job->gang_submit)
++ if (job->gang_submit)
+ fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit);
+
- while (fence == NULL && vm && !job->vmid) {
- r = amdgpu_vmid_grab(vm, ring, &job->sync,
-&job->base.s_fence->finished,
-job);
+ while (!fence && job->vm && !job->vmid) {
+ r = amdgpu_vmid_grab(job->vm, ring, job, &fence);
if (r)
DRM_ERROR("Error getting VM ID (%d)\n", r);
-
- fence = amdgpu_sync_get_fence(&job->sync);
}
- if (!fence && job->gang_submit)
- fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit);
-
return fence;
}
pgpohYmAgPHfl.pgp
Description: OpenPGP digital signature
Re: [PATCH 09/26] drm: exynos: Remove #ifdef guards for PM related functions
Hi,
2022년 11월 8일 (화) 오전 2:52, Paul Cercueil 님이 작성:
>
> Use the DEFINE_RUNTIME_DEV_PM_OPS(), SYSTEM_SLEEP_PM_OPS(),
> RUNTIME_PM_OPS() and pm_ptr() macros to handle the runtime and suspend
> PM callbacks.
>
> These macros allow the suspend and resume functions to be automatically
> dropped by the compiler when CONFIG_PM is disabled, without having
> to use #ifdef guards.
>
> This has the advantage of always compiling these functions in,
> independently of any Kconfig option. Thanks to that, bugs and other
> regressions are subsequently easier to catch.
>
> Signed-off-by: Paul Cercueil
Acked-by : Inki Dae
Thanks for cleanup,
Inki Dae
> ---
> Cc: Inki Dae
> Cc: Seung-Woo Kim
> Cc: Kyungmin Park
> Cc: Krzysztof Kozlowski
> Cc: Alim Akhtar
> Cc: Jingoo Han
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-samsung-...@vger.kernel.org
> ---
> drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 13 -
> drivers/gpu/drm/exynos/exynos7_drm_decon.c| 12 +++-
> drivers/gpu/drm/exynos/exynos_dp.c| 11 +++
> drivers/gpu/drm/exynos/exynos_drm_fimc.c | 11 +++
> drivers/gpu/drm/exynos/exynos_drm_fimd.c | 11 +++
> drivers/gpu/drm/exynos/exynos_drm_g2d.c | 10 +++---
> drivers/gpu/drm/exynos/exynos_drm_mic.c | 11 +++
> drivers/gpu/drm/exynos/exynos_drm_rotator.c | 12 +++-
> drivers/gpu/drm/exynos/exynos_drm_scaler.c| 12 +++-
> 9 files changed, 28 insertions(+), 75 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> index 8155d7e650f1..2867b39fa35e 100644
> --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> @@ -710,7 +710,6 @@ static irqreturn_t decon_irq_handler(int irq, void
> *dev_id)
> return IRQ_HANDLED;
> }
>
> -#ifdef CONFIG_PM
> static int exynos5433_decon_suspend(struct device *dev)
> {
> struct decon_context *ctx = dev_get_drvdata(dev);
> @@ -741,14 +740,10 @@ static int exynos5433_decon_resume(struct device *dev)
>
> return ret;
> }
> -#endif
>
> -static const struct dev_pm_ops exynos5433_decon_pm_ops = {
> - SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
> - NULL)
> - SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
> -pm_runtime_force_resume)
> -};
> +static DEFINE_RUNTIME_DEV_PM_OPS(exynos5433_decon_pm_ops,
> +exynos5433_decon_suspend,
> +exynos5433_decon_resume, NULL);
>
> static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
> {
> @@ -881,7 +876,7 @@ struct platform_driver exynos5433_decon_driver = {
> .remove = exynos5433_decon_remove,
> .driver = {
> .name = "exynos5433-decon",
> - .pm = &exynos5433_decon_pm_ops,
> + .pm = pm_ptr(&exynos5433_decon_pm_ops),
> .of_match_table = exynos5433_decon_driver_dt_match,
> },
> };
> diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c
> b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
> index 7080cf7952ec..3126f735dedc 100644
> --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c
> +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
> @@ -779,7 +779,6 @@ static int decon_remove(struct platform_device *pdev)
> return 0;
> }
>
> -#ifdef CONFIG_PM
> static int exynos7_decon_suspend(struct device *dev)
> {
> struct decon_context *ctx = dev_get_drvdata(dev);
> @@ -836,21 +835,16 @@ static int exynos7_decon_resume(struct device *dev)
> err_pclk_enable:
> return ret;
> }
> -#endif
>
> -static const struct dev_pm_ops exynos7_decon_pm_ops = {
> - SET_RUNTIME_PM_OPS(exynos7_decon_suspend, exynos7_decon_resume,
> - NULL)
> - SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
> - pm_runtime_force_resume)
> -};
> +static DEFINE_RUNTIME_DEV_PM_OPS(exynos7_decon_pm_ops, exynos7_decon_suspend,
> +exynos7_decon_resume, NULL);
>
> struct platform_driver decon_driver = {
> .probe = decon_probe,
> .remove = decon_remove,
> .driver = {
> .name = "exynos-decon",
> - .pm = &exynos7_decon_pm_ops,
> + .pm = pm_ptr(&exynos7_decon_pm_ops),
> .of_match_table = decon_driver_dt_match,
> },
> };
> diff --git a/drivers/gpu/drm/exynos/exynos_dp.c
> b/drivers/gpu/drm/exynos/exynos_dp.c
> index 4e3d3d5f6866..3404ec1367fb 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp.c
> +++ b/drivers/gpu/drm/exynos/exynos_dp.c
> @@ -260,7 +260,6 @@ static int exynos_dp_remove(struct platform_device *pdev)
> return 0;
> }
>
> -#ifdef CONFIG_PM
> static int exynos_dp_suspend(struct
Re: [PATCH v7 2/2] drm/bridge: add it6505 driver to read data-lanes and link-frequencies from dt
Hi all,
Friendly ping on this patch.
Regards,
Pin-yen
On Thu, Nov 3, 2022 at 5:13 PM allen wrote:
>
> From: allen chen
>
> Add driver to read data-lanes and link-frequencies from dt property to
> restrict output bandwidth.
>
> Signed-off-by: Allen chen
> Signed-off-by: Pin-yen Lin
> ---
> drivers/gpu/drm/bridge/ite-it6505.c | 80 +++--
> 1 file changed, 77 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/ite-it6505.c
> b/drivers/gpu/drm/bridge/ite-it6505.c
> index a4302492cf8df..ed4536cde3140 100644
> --- a/drivers/gpu/drm/bridge/ite-it6505.c
> +++ b/drivers/gpu/drm/bridge/ite-it6505.c
> @@ -437,6 +437,8 @@ struct it6505 {
> bool powered;
> bool hpd_state;
> u32 afe_setting;
> + u32 max_dpi_pixel_clock;
> + u32 max_lane_count;
> enum hdcp_state hdcp_status;
> struct delayed_work hdcp_work;
> struct work_struct hdcp_wait_ksv_list;
> @@ -1476,7 +1478,8 @@ static void it6505_parse_link_capabilities(struct
> it6505 *it6505)
> it6505->lane_count = link->num_lanes;
> DRM_DEV_DEBUG_DRIVER(dev, "Sink support %d lanes training",
> it6505->lane_count);
> - it6505->lane_count = min_t(int, it6505->lane_count, MAX_LANE_COUNT);
> + it6505->lane_count = min_t(int, it6505->lane_count,
> + it6505->max_lane_count);
>
> it6505->branch_device = drm_dp_is_branch(it6505->dpcd);
> DRM_DEV_DEBUG_DRIVER(dev, "Sink %sbranch device",
> @@ -2912,7 +2915,7 @@ it6505_bridge_mode_valid(struct drm_bridge *bridge,
> if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> return MODE_NO_INTERLACE;
>
> - if (mode->clock > DPI_PIXEL_CLK_MAX)
> + if (mode->clock > it6505->max_dpi_pixel_clock)
> return MODE_CLOCK_HIGH;
>
> it6505->video_info.clock = mode->clock;
> @@ -3099,10 +3102,32 @@ static int it6505_init_pdata(struct it6505 *it6505)
> return 0;
> }
>
> +static int it6505_get_data_lanes_count(const struct device_node *endpoint,
> + const unsigned int min,
> + const unsigned int max)
> +{
> + int ret;
> +
> + ret = of_property_count_u32_elems(endpoint, "data-lanes");
> + if (ret < 0)
> + return ret;
> +
> + if (ret < min || ret > max)
> + return -EINVAL;
> +
> + return ret;
> +}
> +
> static void it6505_parse_dt(struct it6505 *it6505)
> {
> struct device *dev = &it6505->client->dev;
> + struct device_node *np = dev->of_node, *ep = NULL;
> + int len;
> + u64 link_frequencies;
> + u32 data_lanes[4];
> u32 *afe_setting = &it6505->afe_setting;
> + u32 *max_lane_count = &it6505->max_lane_count;
> + u32 *max_dpi_pixel_clock = &it6505->max_dpi_pixel_clock;
>
> it6505->lane_swap_disabled =
> device_property_read_bool(dev, "no-laneswap");
> @@ -3118,7 +3143,56 @@ static void it6505_parse_dt(struct it6505 *it6505)
> } else {
> *afe_setting = 0;
> }
> - DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %d", *afe_setting);
> +
> + ep = of_graph_get_endpoint_by_regs(np, 1, 0);
> + of_node_put(ep);
> +
> + if (ep) {
> + len = it6505_get_data_lanes_count(ep, 1, 4);
> +
> + if (len > 0 && len != 3) {
> + of_property_read_u32_array(ep, "data-lanes",
> + data_lanes, len);
> + *max_lane_count = len;
> + } else {
> + *max_lane_count = MAX_LANE_COUNT;
> + dev_err(dev, "error data-lanes, use default");
> + }
> + } else {
> + *max_lane_count = MAX_LANE_COUNT;
> + dev_err(dev, "error endpoint, use default");
> + }
> +
> + ep = of_graph_get_endpoint_by_regs(np, 0, 0);
> + of_node_put(ep);
> +
> + if (ep) {
> + len = of_property_read_variable_u64_array(ep,
> + "link-frequencies",
> + &link_frequencies,
> 0,
> + 1);
> + if (len >= 0) {
> + do_div(link_frequencies, 1000);
> + if (link_frequencies > 297000) {
> + dev_err(dev,
> + "max pixel clock error, use default");
> + *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
> + } else {
> + *max_dpi_pixel_clock = link_frequencies;
> + }
> + } else {
> + dev_err(dev, "error link frequencies, use default");
> +
Re: [PATCH v4 0/4] new subsystem for compute accelerator devices
On Sun, 20 Nov 2022 at 06:44, Oded Gabbay wrote: > > This is the fourth (and hopefully last) version of the patch-set to add the > new subsystem for compute accelerators. I removed the RFC headline as > I believe it is now ready for merging. > > Compare to v3, this patch-set contains one additional patch that adds > documentation regarding the accel subsystem. I hope it's good enough for > this stage. In addition, there were few very minor fixes according to > comments received on v3. > > The patches are in the following repo: > https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/accel.git/log/?h=accel_v4 > > As in v3, The HEAD of that branch is a commit adding a dummy driver that > registers an accel device using the new framework. This can be served > as a simple reference. > FIx the nits Jeffery raised and the one I brought up and I think we should be good for this to be in a PR. Reviewed-by: Dave Airlie
[drm:drm-next 741/803] drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c: chid.h is included more than once.
tree: git://anongit.freedesktop.org/drm/drm drm-next head: a143bc517bf31c4575191efbaac216a11ec016e0 commit: 67059b9fb8997f3d4515d72052c331503b00274b [741/803] drm/nouveau/fifo: add chan start()/stop() compiler: gcc-11 (Debian 11.3.0-8) 11.3.0 includecheck warnings: (new ones prefixed by >>) >> drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c: chid.h is included more than once. $ git blame drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c 9a65a38c456eb (Ben Skeggs 2015-08-20 14:54:19 +1000 24) #include "chan.h" 468fae7bb0a31 (Ben Skeggs 2022-06-01 20:47:26 +1000 @25) #include "chid.h" 468fae7bb0a31 (Ben Skeggs 2022-06-01 20:47:26 +1000 26) #include "cgrp.h" 67059b9fb8997 (Ben Skeggs 2022-06-01 20:47:32 +1000 @27) #include "chid.h" 468fae7bb0a31 (Ben Skeggs 2022-06-01 20:47:26 +1000 28) #include "runl.h" f5e4568991f60 (Ben Skeggs 2022-06-01 20:47:21 +1000 29) #include "priv.h" If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot -- 0-DAY CI Kernel Test Service https://01.org/lkp
[PATCH] [next] drm/amdgpu: Replace remaining 1-element array with flex-array
One-element arrays are deprecated, and we are replacing them with
flexible array members instead. So, replace one-element array with
flexible-array member in struct GOP_VBIOS_CONTENT and refactor the
rest of the code accordingly.
Important to mention is that doing a build before/after this patch
results in no functional binary output differences.
This helps with the ongoing efforts to tighten the FORTIFY_SOURCE
routines on memcpy() and help us make progress towards globally
enabling -fstrict-flex-arrays=3 [1].
Link: https://github.com/KSPP/linux/issues/79
Link: https://github.com/KSPP/linux/issues/238
Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101836 [1]
Signed-off-by: Paulo Miguel Almeida
---
This should be the last one-element array that had references in source
code. Given the way it was used, no *.c code change was required.
I will move on to the atombios.h in the radeon driver.
---
drivers/gpu/drm/amd/include/atombios.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/include/atombios.h
b/drivers/gpu/drm/amd/include/atombios.h
index 4dc738c51771..b78360a71bc9 100644
--- a/drivers/gpu/drm/amd/include/atombios.h
+++ b/drivers/gpu/drm/amd/include/atombios.h
@@ -9292,7 +9292,7 @@ typedef struct {
typedef struct {
VFCT_IMAGE_HEADER VbiosHeader;
- UCHAR VbiosContent[1];
+ UCHAR VbiosContent[];
}GOP_VBIOS_CONTENT;
typedef struct {
--
2.37.3
[PATCH v4 00/10] Initial support for Cadence MHDP(HDMI/DP) for i.MX8MQ
The patch set initial support for Cadence MHDP(HDMI/DP) DRM bridge drivers and Cadence HDP-TX PHY(HDMI/DP) drivers for iMX8MQ. The patch set compose of DRM bridge drivers and PHY drivers. Both of them need the followed two patches to pass build. drm: bridge: cadence: convert mailbox functions to macro functions phy: Add HDMI configuration options DRM bridges driver patches: dts-bingings: display: bridge: Add MHDP HDMI bindings for i.MX8MQ drm: bridge: cadence: Add MHDP DP driver for i.MX8MQ dts-bindings: display: bridge: Add MHDP DP bindings for i.MX8MQ drm: bridge: cadence: Add MHDP HDMI driver for i.MX8MQ PHY driver patches: dts-bindings: phy: Add Cadence HDP-TX DP PHY bindings phy: cadence: Add driver for HDP-TX DisplyPort PHY dts-bindings: phy: Add Cadence HDP-TX HDMI PHY bindings phy: cadence: Add driver for HDP-TX HDMI PHY v3->v4: dt-bindings: - Correct dt-bindings coding style and address review comments. - Add apb_clk description. - Add output port for HDMI/DP connector PHY: - Alphabetically sorted in Kconfig and Makefile for DP and HDMI PHY - Remove unused registers define from HDMI and DP PHY drivers. - More description in phy_hdmi.h. - Add apb_clk to HDMI and DP phy driver. HDMI/DP: - Use get_unaligned_le32() to replace hardcode type conversion in HDMI AVI infoframe data fill function. - Add mailbox mutex lock in HDMI/DP driver for phy functions to reslove race conditions between HDMI/DP and PHY drivers. - Add apb_clk to both HDMI and DP driver. - Rename some function names and add prefix with "cdns_hdmi/cdns_dp". - Remove bpc 12 and 16 optional that not supported. v2->v3: Address comments for dt-bindings files. - Correct dts-bindings file names Rename phy-cadence-hdptx-dp.yaml to cdns,mhdp-imx8mq-dp.yaml Rename phy-cadence-hdptx-hdmi.yaml to cdns,mhdp-imx8mq-hdmi.yaml - Drop redundant words and descriptions. - Correct hdmi/dp node name. v2 is a completely different version compared to v1. Previous v1 can be available here [1]. v1->v2: - Reuse Cadence mailbox access functions from mhdp8546 instead of rockchip DP. - Mailbox access functions be convert to marco functions that will be referenced by HDP-TX PHY(HDMI/DP) driver too. - Plain bridge instead of component driver. - Standalone Cadence HDP-TX PHY(HDMI/DP) driver. - Audio driver are removed from the patch set, it will be add in another patch set later. [1] https://patchwork.kernel.org/project/linux-rockchip/cover/cover.1590982881.git.sandor...@nxp.com/ Sandor Yu (10): drm: bridge: cadence: convert mailbox functions to macro functions dt-bindings: display: bridge: Add MHDP DP for i.MX8MQ drm: bridge: cadence: Add MHDP DP driver for i.MX8MQ phy: Add HDMI configuration options dt-bindings: display: bridge: Add MHDP HDMI for i.MX8MQ drm: bridge: cadence: Add MHDP HDMI driver for i.MX8MQ dt-bindings: phy: Add Cadence HDP-TX DP PHY phy: cadence: Add driver for HDP-TX DisplyPort PHY dt-bindings: phy: Add Cadence HDP-TX HDMI PHY phy: cadence: Add driver for HDP-TX HDMI PHY .../display/bridge/cdns,mhdp-imx8mq-dp.yaml | 93 ++ .../display/bridge/cdns,mhdp-imx8mq-hdmi.yaml | 93 ++ .../bindings/phy/cdns,hdptx-dp-phy.yaml | 68 ++ .../bindings/phy/cdns,hdptx-hdmi-phy.yaml | 52 + drivers/gpu/drm/bridge/cadence/Kconfig| 25 + drivers/gpu/drm/bridge/cadence/Makefile |3 + drivers/gpu/drm/bridge/cadence/cdns-dp-core.c | 1071 + .../gpu/drm/bridge/cadence/cdns-hdmi-core.c | 1018 .../gpu/drm/bridge/cadence/cdns-mhdp-common.h | 400 ++ .../drm/bridge/cadence/cdns-mhdp8546-core.c | 197 +-- .../drm/bridge/cadence/cdns-mhdp8546-core.h |1 - drivers/phy/cadence/Kconfig | 16 + drivers/phy/cadence/Makefile |2 + drivers/phy/cadence/phy-cadence-hdptx-dp.c| 737 drivers/phy/cadence/phy-cadence-hdptx-hdmi.c | 891 ++ include/drm/bridge/cdns-mhdp-mailbox.h| 240 include/linux/phy/phy-hdmi.h | 38 + include/linux/phy/phy.h |7 +- 18 files changed, 4755 insertions(+), 197 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml create mode 100644 Documentation/devicetree/bindings/phy/cdns,hdptx-dp-phy.yaml create mode 100644 Documentation/devicetree/bindings/phy/cdns,hdptx-hdmi-phy.yaml create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dp-core.c create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.h create mode 100644 drivers/phy/cadence/phy-cadence-hdptx-dp.c create mode 100644 drivers/phy/cadence/phy-cadence-hdptx-hdmi.c create mode 100644 include/drm/bridge/cdns-mhdp-mailbox.h create mode 100644 include/linux/phy/phy-hdmi.h -- 2.34.1
[PATCH v4 01/10] drm: bridge: cadence: convert mailbox functions to macro functions
Mailbox access functions could be share to other mhdp driver and
HDP-TX HDMI/DP PHY drivers, move those functions to head file
include/drm/bridge/cdns-mhdp-mailbox.h and convert them to
macro functions.
Signed-off-by: Sandor Yu
---
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 197 +-
.../drm/bridge/cadence/cdns-mhdp8546-core.h | 1 -
include/drm/bridge/cdns-mhdp-mailbox.h| 240 ++
3 files changed, 242 insertions(+), 196 deletions(-)
create mode 100644 include/drm/bridge/cdns-mhdp-mailbox.h
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index 31442a922502..b77b0ddcc9b3 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -36,6 +36,7 @@
#include
#include
+#include
#include
#include
#include
@@ -55,200 +56,6 @@
#include "cdns-mhdp8546-hdcp.h"
#include "cdns-mhdp8546-j721e.h"
-static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
-{
- int ret, empty;
-
- WARN_ON(!mutex_is_locked(&mhdp->mbox_mutex));
-
- ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_EMPTY,
-empty, !empty, MAILBOX_RETRY_US,
-MAILBOX_TIMEOUT_US);
- if (ret < 0)
- return ret;
-
- return readl(mhdp->regs + CDNS_MAILBOX_RX_DATA) & 0xff;
-}
-
-static int cdns_mhdp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val)
-{
- int ret, full;
-
- WARN_ON(!mutex_is_locked(&mhdp->mbox_mutex));
-
- ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_FULL,
-full, !full, MAILBOX_RETRY_US,
-MAILBOX_TIMEOUT_US);
- if (ret < 0)
- return ret;
-
- writel(val, mhdp->regs + CDNS_MAILBOX_TX_DATA);
-
- return 0;
-}
-
-static int cdns_mhdp_mailbox_recv_header(struct cdns_mhdp_device *mhdp,
-u8 module_id, u8 opcode,
-u16 req_size)
-{
- u32 mbox_size, i;
- u8 header[4];
- int ret;
-
- /* read the header of the message */
- for (i = 0; i < sizeof(header); i++) {
- ret = cdns_mhdp_mailbox_read(mhdp);
- if (ret < 0)
- return ret;
-
- header[i] = ret;
- }
-
- mbox_size = get_unaligned_be16(header + 2);
-
- if (opcode != header[0] || module_id != header[1] ||
- req_size != mbox_size) {
- /*
-* If the message in mailbox is not what we want, we need to
-* clear the mailbox by reading its contents.
-*/
- for (i = 0; i < mbox_size; i++)
- if (cdns_mhdp_mailbox_read(mhdp) < 0)
- break;
-
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int cdns_mhdp_mailbox_recv_data(struct cdns_mhdp_device *mhdp,
- u8 *buff, u16 buff_size)
-{
- u32 i;
- int ret;
-
- for (i = 0; i < buff_size; i++) {
- ret = cdns_mhdp_mailbox_read(mhdp);
- if (ret < 0)
- return ret;
-
- buff[i] = ret;
- }
-
- return 0;
-}
-
-static int cdns_mhdp_mailbox_send(struct cdns_mhdp_device *mhdp, u8 module_id,
- u8 opcode, u16 size, u8 *message)
-{
- u8 header[4];
- int ret, i;
-
- header[0] = opcode;
- header[1] = module_id;
- put_unaligned_be16(size, header + 2);
-
- for (i = 0; i < sizeof(header); i++) {
- ret = cdns_mhdp_mailbox_write(mhdp, header[i]);
- if (ret)
- return ret;
- }
-
- for (i = 0; i < size; i++) {
- ret = cdns_mhdp_mailbox_write(mhdp, message[i]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
-static
-int cdns_mhdp_reg_read(struct cdns_mhdp_device *mhdp, u32 addr, u32 *value)
-{
- u8 msg[4], resp[8];
- int ret;
-
- put_unaligned_be32(addr, msg);
-
- mutex_lock(&mhdp->mbox_mutex);
-
- ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL,
-GENERAL_REGISTER_READ,
-sizeof(msg), msg);
- if (ret)
- goto out;
-
- ret = cdns_mhdp_mailbox_recv_header(mhdp, MB_MODULE_ID_GENERAL,
- GENERAL_REGISTER_READ,
- sizeof(resp));
- if (ret)
- goto out;
-
- ret = cdns_mhdp_mailbox_recv_data(mhdp, resp, sizeof(resp));
- if (ret)
- goto out;
-
- /* Returned address value should be the same as requested */
- if (memcmp(msg, resp, sizeof(msg
[PATCH v4 03/10] drm: bridge: cadence: Add MHDP DP driver for i.MX8MQ
Add a new DRM DisplayPort bridge driver for Candence MHDP
used in i.MX8MQ SOC. MHDP IP could support HDMI or DisplayPort
standards according embedded Firmware running in the uCPU.
For iMX8MQ SOC, the DisplayPort FW was loaded and activated by SOC
ROM code. Bootload binary included HDMI FW was required for the driver.
Signed-off-by: Sandor Yu
---
drivers/gpu/drm/bridge/cadence/Kconfig| 13 +
drivers/gpu/drm/bridge/cadence/Makefile |3 +
drivers/gpu/drm/bridge/cadence/cdns-dp-core.c | 1071 +
.../gpu/drm/bridge/cadence/cdns-mhdp-common.h | 400 ++
4 files changed, 1487 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.h
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
index 1d06182bea71..e79ae1af3765 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -25,3 +25,16 @@ config DRM_CDNS_MHDP8546_J721E
initializes the J721E Display Port and sets up the
clock and data muxes.
endif
+
+config DRM_CDNS_DP
+ tristate "Cadence DP DRM driver"
+ select DRM_KMS_HELPER
+ select DRM_PANEL_BRIDGE
+ select DRM_DISPLAY_DP_HELPER
+ select DRM_DISPLAY_HELPER
+ select DRM_CDNS_AUDIO
+ depends on OF
+ help
+ Support Cadence MHDP DisplayPort driver.
+ Cadence MHDP Controller support one or more protocols,
+ DisplayPort firmware is required for this driver.
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
b/drivers/gpu/drm/bridge/cadence/Makefile
index 4d2db8df1bc6..269ef500c29d 100644
--- a/drivers/gpu/drm/bridge/cadence/Makefile
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -2,3 +2,6 @@
obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
+
+obj-$(CONFIG_DRM_CDNS_DP) += cdns-dp-core.o
+obj-$(CONFIG_DRM_CDNS_HDMI) += cdns-hdmi-core.o
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
new file mode 100644
index ..b1062e8015f9
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
@@ -0,0 +1,1071 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Cadence Display Port Interface (DP) driver
+ *
+ * Copyright (C) 2019-2022 NXP Semiconductor, Inc.
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "cdns-mhdp-common.h"
+
+#define LINK_TRAINING_TIMEOUT_MS 500
+#define LINK_TRAINING_RETRY_MS 20
+
+/*
+ * This function only implements native DPDC reads and writes
+ */
+static int cdns_dp_dpcd_read(struct cdns_mhdp_device *mhdp,
+ u32 addr, u8 *data, u16 len)
+{
+ u8 msg[5], reg[5];
+ int ret;
+
+ put_unaligned_be16(len, msg);
+ put_unaligned_be24(addr, msg + 2);
+
+ mutex_lock(&mhdp->mbox_mutex);
+
+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
+DPTX_READ_DPCD, sizeof(msg), msg);
+ if (ret)
+ goto out;
+
+ ret = cdns_mhdp_mailbox_recv_header(mhdp, MB_MODULE_ID_DP_TX,
+ DPTX_READ_DPCD,
+ sizeof(reg) + len);
+ if (ret)
+ goto out;
+
+ ret = cdns_mhdp_mailbox_recv_data(mhdp, reg, sizeof(reg));
+ if (ret)
+ goto out;
+
+ ret = cdns_mhdp_mailbox_recv_data(mhdp, data, len);
+
+out:
+ mutex_unlock(&mhdp->mbox_mutex);
+
+ return ret;
+}
+
+static int cdns_dp_dpcd_write(struct cdns_mhdp_device *mhdp, u32 addr, u8
value)
+{
+ u8 msg[6], reg[5];
+ int ret;
+
+ put_unaligned_be16(1, msg);
+ put_unaligned_be24(addr, msg + 2);
+ msg[5] = value;
+
+ mutex_lock(&mhdp->mbox_mutex);
+
+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
+DPTX_WRITE_DPCD, sizeof(msg), msg);
+ if (ret)
+ goto out;
+
+ ret = cdns_mhdp_mailbox_recv_header(mhdp, MB_MODULE_ID_DP_TX,
+ DPTX_WRITE_DPCD, sizeof(reg));
+ if (ret)
+ goto out;
+
+ ret = cdns_mhdp_mailbox_recv_data(mhdp, reg, sizeof(reg));
+ if (ret)
+ goto out;
+
+ if (addr != get_unaligned_be24(reg + 2))
+ ret = -EINVAL;
+
+out:
+ mutex_unlock(&mhdp->mbox_mutex);
+
+ if (ret)
+ dev_err(mhdp->dev, "dpcd write failed: %d\n", ret);
+ return ret;
+}
+
+static ssize_t cdns_dp_aux_transfer(struct drm_dp_aux *aux,
+ struct drm_dp_aux_msg *msg)
+{
+ struct
[PATCH v4 04/10] phy: Add HDMI configuration options
Allow HDMI PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The parameters added here are based on HDMI PHY
implementation practices. The current set of parameters
should cover the potential users.
Signed-off-by: Sandor Yu
---
include/linux/phy/phy-hdmi.h | 38
include/linux/phy/phy.h | 7 ++-
2 files changed, 44 insertions(+), 1 deletion(-)
create mode 100644 include/linux/phy/phy-hdmi.h
diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h
new file mode 100644
index ..5765aa5bc175
--- /dev/null
+++ b/include/linux/phy/phy-hdmi.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __PHY_HDMI_H_
+#define __PHY_HDMI_H_
+
+/**
+ * Pixel Encoding as HDMI Specification
+ * RGB, YUV422, YUV444:HDMI Specification 1.4a Section 6.5
+ * YUV420: HDMI Specification 2.a Section 7.1
+ */
+enum hdmi_phy_colorspace {
+ HDMI_PHY_COLORSPACE_RGB,/* RGB 4:4:4 */
+ HDMI_PHY_COLORSPACE_YUV422, /* YCbCr 4:2:2 */
+ HDMI_PHY_COLORSPACE_YUV444, /* YCbCr 4:4:4 */
+ HDMI_PHY_COLORSPACE_YUV420, /* YCbCr 4:2:0 */
+ HDMI_PHY_COLORSPACE_RESERVED4,
+ HDMI_PHY_COLORSPACE_RESERVED5,
+ HDMI_PHY_COLORSPACE_RESERVED6,
+};
+
+/**
+ * struct phy_configure_opts_hdmi - HDMI configuration set
+ * @pixel_clk_rate:Pixel clock of video modes in KHz.
+ * @bpc: Maximum bits per color channel.
+ * @color_space: Colorspace in enum hdmi_phy_colorspace.
+ *
+ * This structure is used to represent the configuration state of a HDMI phy.
+ */
+struct phy_configure_opts_hdmi {
+ unsigned int pixel_clk_rate;
+ unsigned int bpc;
+ enum hdmi_phy_colorspace color_space;
+};
+
+#endif /* __PHY_HDMI_H_ */
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index b1413757fcc3..6f6873ea7270 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -17,6 +17,7 @@
#include
#include
+#include
#include
#include
@@ -42,7 +43,8 @@ enum phy_mode {
PHY_MODE_MIPI_DPHY,
PHY_MODE_SATA,
PHY_MODE_LVDS,
- PHY_MODE_DP
+ PHY_MODE_DP,
+ PHY_MODE_HDMI,
};
enum phy_media {
@@ -60,11 +62,14 @@ enum phy_media {
* the DisplayPort protocol.
* @lvds: Configuration set applicable for phys supporting
* the LVDS phy mode.
+ * @hdmi: Configuration set applicable for phys supporting
+ * the HDMI phy mode.
*/
union phy_configure_opts {
struct phy_configure_opts_mipi_dphy mipi_dphy;
struct phy_configure_opts_dpdp;
struct phy_configure_opts_lvds lvds;
+ struct phy_configure_opts_hdmi hdmi;
};
/**
--
2.34.1
[PATCH v4 02/10] dt-bindings: display: bridge: Add MHDP DP for i.MX8MQ
Add bindings for i.MX8MQ MHDP DisplayPort.
Signed-off-by: Sandor Yu
---
.../display/bridge/cdns,mhdp-imx8mq-dp.yaml | 93 +++
1 file changed, 93 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml
diff --git
a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml
b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml
new file mode 100644
index ..d82f3ceddaa8
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-dp.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp-imx8mq-dp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence MHDP Displayport bridge
+
+maintainers:
+ - Sandor Yu
+
+description:
+ The Cadence MHDP Displayport TX interface.
+
+properties:
+ compatible:
+enum:
+ - cdns,mhdp-imx8mq-dp
+
+ reg:
+maxItems: 1
+
+ clocks:
+maxItems: 1
+description: MHDP DP APB clock.
+
+ phys:
+maxItems: 1
+
+ interrupts:
+items:
+ - description: Hotplug cable plugin.
+ - description: Hotplug cable plugout.
+
+ interrupt-names:
+items:
+ - const: plug_in
+ - const: plug_out
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+ port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ Input port from display controller output.
+ port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ Output port to DP connector.
+
+required:
+ - port@0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+ - interrupt-names
+ - phys
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+mhdp_dp: dp-bridge@32c0 {
+compatible = "cdns,mhdp-imx8mq-dp";
+reg = <0x32c0 0x10>;
+interrupts = ,
+ ;
+interrupt-names = "plug_in", "plug_out";
+clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+phys = <&dp_phy>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+
+mhdp_in: endpoint {
+remote-endpoint = <&dcss_out>;
+};
+};
+};
+};
--
2.34.1
[PATCH v4 05/10] dt-bindings: display: bridge: Add MHDP HDMI for i.MX8MQ
Add bindings for i.MX8MQ MHDP HDMI.
Signed-off-by: Sandor Yu
---
.../display/bridge/cdns,mhdp-imx8mq-hdmi.yaml | 93 +++
1 file changed, 93 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml
diff --git
a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml
b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml
new file mode 100644
index ..dad5b12d8ef0
--- /dev/null
+++
b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp-imx8mq-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence MHDP HDMI bridge
+
+maintainers:
+ - Sandor Yu
+
+description:
+ The Cadence MHDP TX HDMI interface.
+
+properties:
+ compatible:
+enum:
+ - cdns,mhdp-imx8mq-hdmi
+
+ reg:
+maxItems: 1
+
+ clocks:
+maxItems: 1
+description: MHDP HDMI APB clock.
+
+ phys:
+maxItems: 1
+
+ interrupts:
+items:
+ - description: Hotplug cable plugin.
+ - description: Hotplug cable plugout.
+
+ interrupt-names:
+items:
+ - const: plug_in
+ - const: plug_out
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+ port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ Input port from display controller output.
+
+ port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ Output port to HDMI connector.
+
+required:
+ - port@0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+ - interrupt-names
+ - phys
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+mhdp_hdmi: hdmi-bridge@32c0 {
+compatible = "cdns,mhdp-imx8mq-hdmi";
+reg = <0x32c0 0x10>;
+interrupts = ,
+ ;
+interrupt-names = "plug_in", "plug_out";
+clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+phys = <&hdmi_phy>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+
+mhdp_in: endpoint {
+remote-endpoint = <&dcss_out>;
+};
+};
+};
+};
--
2.34.1
[PATCH v4 07/10] dt-bindings: phy: Add Cadence HDP-TX DP PHY
Add bindings for Cadence HDP-TX DisplayPort PHY.
Signed-off-by: Sandor Yu
---
.../bindings/phy/cdns,hdptx-dp-phy.yaml | 68 +++
1 file changed, 68 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/cdns,hdptx-dp-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/cdns,hdptx-dp-phy.yaml
b/Documentation/devicetree/bindings/phy/cdns,hdptx-dp-phy.yaml
new file mode 100644
index ..b997c15ff0bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/cdns,hdptx-dp-phy.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/cdns,hdptx-dp-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence HDP-TX(HDMI/DisplayPort) PHY for DisplayPort protocol
+
+maintainers:
+ - Sandor Yu
+
+properties:
+ compatible:
+enum:
+ - cdns,hdptx-dp-phy
+
+ reg:
+maxItems: 1
+
+ clocks:
+items:
+ - description: PHY reference clock.
+ - description: APB clock.
+
+ clock-names:
+items:
+ - const: refclk
+ - const: apbclk
+
+ "#phy-cells":
+const: 0
+
+ cdns,num-lanes:
+description:
+ Number of lanes.
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [1, 2, 3, 4]
+default: 4
+
+ cdns,max-bit-rate:
+description:
+ Maximum DisplayPort link bit rate to use, in Mbps
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [2160, 2430, 2700, 3240, 4320, 5400]
+default: 5400
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+dp_phy: phy@32c0 {
+compatible = "cdns,hdptx-dp-phy";
+reg = <0x32c0 0x10>;
+#phy-cells = <0>;
+clocks = <&hdmi_phy_27m>, <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+clock-names = "refclk", "apbclk";
+cdns,num-lanes = <4>;
+cdns,max-bit-rate = <5400>;
+};
--
2.34.1
[PATCH v4 06/10] drm: bridge: cadence: Add MHDP HDMI driver for i.MX8MQ
Add a new DRM HDMI bridge driver for Candence MHDP used in i.MX8MQ
SOC. MHDP IP could support HDMI or DisplayPort standards according
embedded Firmware running in the uCPU.
For iMX8MQ SOC, the HDMI FW was loaded and activated by SOC ROM code.
Bootload binary included HDMI FW was required for the driver.
Signed-off-by: Sandor Yu
---
drivers/gpu/drm/bridge/cadence/Kconfig| 12 +
.../gpu/drm/bridge/cadence/cdns-hdmi-core.c | 1018 +
2 files changed, 1030 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
index e79ae1af3765..377452d09992 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -26,6 +26,18 @@ config DRM_CDNS_MHDP8546_J721E
clock and data muxes.
endif
+config DRM_CDNS_HDMI
+ tristate "Cadence HDMI DRM driver"
+ select DRM_KMS_HELPER
+ select DRM_PANEL_BRIDGE
+ select DRM_DISPLAY_HELPER
+ select DRM_CDNS_AUDIO
+ depends on OF
+ help
+ Support Cadence MHDP HDMI driver.
+ Cadence MHDP Controller support one or more protocols,
+ HDMI firmware is required for this driver.
+
config DRM_CDNS_DP
tristate "Cadence DP DRM driver"
select DRM_KMS_HELPER
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
new file mode 100644
index ..10cb30a66947
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
@@ -0,0 +1,1018 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Cadence High-Definition Multimedia Interface (HDMI) driver
+ *
+ * Copyright (C) 2019-2022 NXP Semiconductor, Inc.
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "cdns-mhdp-common.h"
+
+/**
+ * cdns_hdmi_infoframe_set() - fill the HDMI AVI infoframe
+ * @mhdp: phandle to mhdp device.
+ * @entry_id: The packet memory address in which the data is written.
+ * @packet_len: 32, only 32 bytes now.
+ * @packet: point to InfoFrame Packet.
+ * packet[0] = 0
+ * packet[1-3] = HB[0-2] InfoFrame Packet Header
+ * packet[4-31 = PB[0-27] InfoFrame Packet Contents
+ * @packet_type: Packet Type of InfoFrame in HDMI Specification.
+ *
+ */
+static void cdns_hdmi_infoframe_set(struct cdns_mhdp_device *mhdp,
+ u8 entry_id, u8 packet_len, u8 *packet,
u8 packet_type)
+{
+ u32 packet32, len32;
+ u32 val, i;
+
+ /* only support 32 bytes now */
+ if (packet_len != 32)
+ return;
+
+ /* invalidate entry */
+ val = F_ACTIVE_IDLE_TYPE(1) | F_PKT_ALLOC_ADDRESS(entry_id);
+ writel(val, mhdp->regs + SOURCE_PIF_PKT_ALLOC_REG);
+ writel(F_PKT_ALLOC_WR_EN(1), mhdp->regs + SOURCE_PIF_PKT_ALLOC_WR_EN);
+
+ /* flush fifo 1 */
+ writel(F_FIFO1_FLUSH(1), mhdp->regs + SOURCE_PIF_FIFO1_FLUSH);
+
+ /* write packet into memory */
+ len32 = packet_len / 4;
+ for (i = 0; i < len32; i++) {
+ packet32 = get_unaligned_le32(packet + 4 * i);
+ writel(F_DATA_WR(packet32), mhdp->regs + SOURCE_PIF_DATA_WR);
+ }
+
+ /* write entry id */
+ writel(F_WR_ADDR(entry_id), mhdp->regs + SOURCE_PIF_WR_ADDR);
+
+ /* write request */
+ writel(F_HOST_WR(1), mhdp->regs + SOURCE_PIF_WR_REQ);
+
+ /* update entry */
+ val = F_ACTIVE_IDLE_TYPE(1) | F_TYPE_VALID(1) |
+ F_PACKET_TYPE(packet_type) |
F_PKT_ALLOC_ADDRESS(entry_id);
+ writel(val, mhdp->regs + SOURCE_PIF_PKT_ALLOC_REG);
+
+ writel(F_PKT_ALLOC_WR_EN(1), mhdp->regs + SOURCE_PIF_PKT_ALLOC_WR_EN);
+}
+
+static int cdns_hdmi_get_edid_block(void *data, u8 *edid,
+ u32 block, size_t length)
+{
+ struct cdns_mhdp_device *mhdp = data;
+ u8 msg[2], reg[5], i;
+ int ret;
+
+ mutex_lock(&mhdp->mbox_mutex);
+
+ for (i = 0; i < 4; i++) {
+ msg[0] = block / 2;
+ msg[1] = block % 2;
+
+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_HDMI_TX,
HDMI_TX_EDID,
+ sizeof(msg), msg);
+ if (ret)
+ continue;
+
+ ret = cdns_mhdp_mailbox_recv_header(mhdp, MB_MODULE_ID_HDMI_TX,
+ HDMI_TX_EDID, sizeof(reg)
+ length);
+ if (ret)
+ continue;
+
+ ret = cdns_mhdp_mailbox_recv_data(mhdp, reg, sizeof(reg));
+ if (ret)
+ continue;
+
+ ret = cdns_mhdp_mailbox_recv_data(mhdp, edid, length);
+ if (ret)
+
[PATCH v4 08/10] phy: cadence: Add driver for HDP-TX DisplyPort PHY
Add Cadence HDP-TX DisplayPort PHY driver. Cadence HDP-TX PHY could be put in either DP mode or HDMI mode base on the configuration chosen. DisplayPort PHY mode is configurated in the driver. Signed-off-by: Sandor Yu --- drivers/phy/cadence/Kconfig| 8 + drivers/phy/cadence/Makefile | 1 + drivers/phy/cadence/phy-cadence-hdptx-dp.c | 737 + 3 files changed, 746 insertions(+) create mode 100644 drivers/phy/cadence/phy-cadence-hdptx-dp.c diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig index 1adde2d99ae7..7c662a57b812 100644 --- a/drivers/phy/cadence/Kconfig +++ b/drivers/phy/cadence/Kconfig @@ -30,6 +30,14 @@ config PHY_CADENCE_DPHY_RX help Support for Cadence D-PHY in Rx configuration. +config PHY_CADENCE_HDPTX_DP + tristate "Cadence HDPTX DP PHY Driver" + depends on OF && HAS_IOMEM + depends on COMMON_CLK + select GENERIC_PHY + help + Enable this to support the Cadence HDPTX DP PHY driver + config PHY_CADENCE_SIERRA tristate "Cadence Sierra PHY Driver" depends on OF && HAS_IOMEM && RESET_CONTROLLER diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile index e17f035ddece..5e7d92a4c9aa 100644 --- a/drivers/phy/cadence/Makefile +++ b/drivers/phy/cadence/Makefile @@ -2,5 +2,6 @@ obj-$(CONFIG_PHY_CADENCE_TORRENT) += phy-cadence-torrent.o obj-$(CONFIG_PHY_CADENCE_DPHY) += cdns-dphy.o obj-$(CONFIG_PHY_CADENCE_DPHY_RX) += cdns-dphy-rx.o +obj-$(CONFIG_PHY_CADENCE_HDPTX_DP) += phy-cadence-hdptx-dp.o obj-$(CONFIG_PHY_CADENCE_SIERRA) += phy-cadence-sierra.o obj-$(CONFIG_PHY_CADENCE_SALVO)+= phy-cadence-salvo.o diff --git a/drivers/phy/cadence/phy-cadence-hdptx-dp.c b/drivers/phy/cadence/phy-cadence-hdptx-dp.c new file mode 100644 index ..144292288dd6 --- /dev/null +++ b/drivers/phy/cadence/phy-cadence-hdptx-dp.c @@ -0,0 +1,737 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cadence HDP-TX Display Port Interface (DP) PHY driver + * + * Copyright (C) 2022 NXP Semiconductor, Inc. + */ +#include +#include +#include +#include +#include +#include +#include + +#include + +#define ADDR_PHY_AFE 0x8 + +/* PHY registers */ +#define CMN_SSM_BIAS_TMR0x0022 +#define CMN_PLLSM0_PLLEN_TMR0x0029 +#define CMN_PLLSM0_PLLPRE_TMR 0x002A +#define CMN_PLLSM0_PLLVREF_TMR 0x002B +#define CMN_PLLSM0_PLLLOCK_TMR 0x002C +#define CMN_PLLSM0_USER_DEF_CTRL0x002F +#define CMN_PSM_CLK_CTRL0x0061 +#define CMN_PLL0_VCOCAL_START 0x0081 +#define CMN_PLL0_VCOCAL_INIT_TMR0x0084 +#define CMN_PLL0_VCOCAL_ITER_TMR0x0085 +#define CMN_PLL0_INTDIV 0x0094 +#define CMN_PLL0_FRACDIV0x0095 +#define CMN_PLL0_HIGH_THR 0x0096 +#define CMN_PLL0_DSM_DIAG 0x0097 +#define CMN_PLL0_SS_CTRL2 0x0099 +#define CMN_ICAL_INIT_TMR 0x00C4 +#define CMN_ICAL_ITER_TMR 0x00C5 +#define CMN_RXCAL_INIT_TMR 0x00D4 +#define CMN_RXCAL_ITER_TMR 0x00D5 +#define CMN_TXPUCAL_INIT_TMR0x00E4 +#define CMN_TXPUCAL_ITER_TMR0x00E5 +#define CMN_TXPDCAL_INIT_TMR0x00F4 +#define CMN_TXPDCAL_ITER_TMR0x00F5 +#define CMN_ICAL_ADJ_INIT_TMR 0x0102 +#define CMN_ICAL_ADJ_ITER_TMR 0x0103 +#define CMN_RX_ADJ_INIT_TMR 0x0106 +#define CMN_RX_ADJ_ITER_TMR 0x0107 +#define CMN_TXPU_ADJ_INIT_TMR 0x010A +#define CMN_TXPU_ADJ_ITER_TMR 0x010B +#define CMN_TXPD_ADJ_INIT_TMR 0x010E +#define CMN_TXPD_ADJ_ITER_TMR 0x010F +#define CMN_DIAG_PLL0_FBH_OVRD 0x01C0 +#define CMN_DIAG_PLL0_FBL_OVRD 0x01C1 +#define CMN_DIAG_PLL0_OVRD 0x01C2 +#define CMN_DIAG_PLL0_TEST_MODE 0x01C4 +#define CMN_DIAG_PLL0_V2I_TUNE 0x01C5 +#define CMN_DIAG_PLL0_CP_TUNE 0x01C6 +#define CMN_DIAG_PLL0_LF_PROG 0x01C7 +#define CMN_DIAG_PLL0_PTATIS_TUNE1 0x01C8 +#define CMN_DIAG_PLL0_PTATIS_TUNE2 0x01C9 +#define CMN_DIAG_HSCLK_SEL 0x01E0 +#define CMN_DIAG_PER_CAL_ADJ0x01EC +#define CMN_DIAG_CAL_CTRL 0x01ED +#define CMN_DIAG_ACYA 0x01FF +#define XCVR_PSM_RCTRL 0x4001 +#define XCVR_PSM_CAL_TMR0x4002 +#define XCVR_PSM_A0IN_TMR 0x4003 +#define TX_TXCC_CAL_SCLR_MULT_0 0x4047 +#define TX_TXCC_CPOST_MULT_00_0 0x404C +#define XCVR_DIAG_PLLDRC_CTRL 0x40E0 +#define XCVR_DIAG_PLLDRC_CTRL 0x40E0 +#define XCVR_DIAG_HSCLK_SEL 0x40E1 +#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR 0x40F2 +#define TX_PSC_A0 0x4100 +#define TX_PSC_A1 0x4101 +#define TX_PSC_A2 0x4102 +#define TX_PSC_A3
[PATCH v4 10/10] phy: cadence: Add driver for HDP-TX HDMI PHY
Add Cadence HDP-TX HDMI PHY driver. Cadence HDP-TX PHY could be put in either DP mode or HDMI mode base on the configuration chosen. HDMI PHY mode is configurated in the driver. Signed-off-by: Sandor Yu --- drivers/phy/cadence/Kconfig | 8 + drivers/phy/cadence/Makefile | 1 + drivers/phy/cadence/phy-cadence-hdptx-hdmi.c | 891 +++ 3 files changed, 900 insertions(+) create mode 100644 drivers/phy/cadence/phy-cadence-hdptx-hdmi.c diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig index 7c662a57b812..84e81c473a51 100644 --- a/drivers/phy/cadence/Kconfig +++ b/drivers/phy/cadence/Kconfig @@ -38,6 +38,14 @@ config PHY_CADENCE_HDPTX_DP help Enable this to support the Cadence HDPTX DP PHY driver +config PHY_CADENCE_HDPTX_HDMI + tristate "Cadence HDPTX HDMI PHY Driver" + depends on OF && HAS_IOMEM + depends on COMMON_CLK + select GENERIC_PHY + help + Enable this to support the Cadence HDPTX HDMI PHY driver. + config PHY_CADENCE_SIERRA tristate "Cadence Sierra PHY Driver" depends on OF && HAS_IOMEM && RESET_CONTROLLER diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile index 5e7d92a4c9aa..98702b7d2903 100644 --- a/drivers/phy/cadence/Makefile +++ b/drivers/phy/cadence/Makefile @@ -3,5 +3,6 @@ obj-$(CONFIG_PHY_CADENCE_TORRENT) += phy-cadence-torrent.o obj-$(CONFIG_PHY_CADENCE_DPHY) += cdns-dphy.o obj-$(CONFIG_PHY_CADENCE_DPHY_RX) += cdns-dphy-rx.o obj-$(CONFIG_PHY_CADENCE_HDPTX_DP) += phy-cadence-hdptx-dp.o +obj-$(CONFIG_PHY_CADENCE_HDPTX_HDMI) += phy-cadence-hdptx-hdmi.o obj-$(CONFIG_PHY_CADENCE_SIERRA) += phy-cadence-sierra.o obj-$(CONFIG_PHY_CADENCE_SALVO)+= phy-cadence-salvo.o diff --git a/drivers/phy/cadence/phy-cadence-hdptx-hdmi.c b/drivers/phy/cadence/phy-cadence-hdptx-hdmi.c new file mode 100644 index ..e7b1633846bb --- /dev/null +++ b/drivers/phy/cadence/phy-cadence-hdptx-hdmi.c @@ -0,0 +1,891 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cadence High-Definition Multimedia Interface (HDMI) PHY driver + * + * Copyright (C) 2022 NXP Semiconductor, Inc. + */ +#include +#include +#include +#include +#include +#include + +#include + +#define ADDR_PHY_AFE 0x8 +/* PHY registers */ +#define CMN_SSM_BIAS_TMR0x0022 +#define CMN_PLLSM0_USER_DEF_CTRL0x002F +#define CMN_PSM_CLK_CTRL0x0061 +#define CMN_CDIAG_REFCLK_CTRL 0x0062 +#define CMN_PLL0_VCOCAL_START 0x0081 +#define CMN_PLL0_VCOCAL_INIT_TMR0x0084 +#define CMN_PLL0_VCOCAL_ITER_TMR0x0085 +#define CMN_TXPUCAL_CTRL0x00E0 +#define CMN_TXPDCAL_CTRL0x00F0 +#define CMN_TXPU_ADJ_CTRL 0x0108 +#define CMN_TXPD_ADJ_CTRL 0x010c +#define CMN_DIAG_PLL0_FBH_OVRD 0x01C0 +#define CMN_DIAG_PLL0_FBL_OVRD 0x01C1 +#define CMN_DIAG_PLL0_OVRD 0x01C2 +#define CMN_DIAG_PLL0_TEST_MODE 0x01C4 +#define CMN_DIAG_PLL0_V2I_TUNE 0x01C5 +#define CMN_DIAG_PLL0_CP_TUNE 0x01C6 +#define CMN_DIAG_PLL0_LF_PROG 0x01C7 +#define CMN_DIAG_PLL0_PTATIS_TUNE1 0x01C8 +#define CMN_DIAG_PLL0_PTATIS_TUNE2 0x01C9 +#define CMN_DIAG_PLL0_INCLK_CTRL0x01CA +#define CMN_DIAG_PLL0_PXL_DIVH 0x01CB +#define CMN_DIAG_PLL0_PXL_DIVL 0x01CC +#define CMN_DIAG_HSCLK_SEL 0x01E0 +#define XCVR_PSM_RCTRL 0x4001 +#define TX_TXCC_CAL_SCLR_MULT_0 0x4047 +#define TX_TXCC_CPOST_MULT_00_0 0x404C +#define XCVR_DIAG_PLLDRC_CTRL 0x40E0 +#define XCVR_DIAG_PLLDRC_CTRL 0x40E0 +#define XCVR_DIAG_HSCLK_SEL 0x40E1 +#define XCVR_DIAG_BIDI_CTRL 0x40E8 +#define TX_PSC_A0 0x4100 +#define TX_PSC_A1 0x4101 +#define TX_PSC_A2 0x4102 +#define TX_PSC_A3 0x4103 +#define TX_DIAG_TX_CTRL 0x41E0 +#define TX_DIAG_TX_DRV 0x41E1 +#define TX_DIAG_BGREF_PREDRV_DELAY 0x41E7 +#define TX_DIAG_ACYA_0 0x41FF +#define TX_DIAG_ACYA_1 0x43FF +#define TX_DIAG_ACYA_2 0x45FF +#define TX_DIAG_ACYA_3 0x47FF +#define TX_ANA_CTRL_REG_1 0x5020 +#define TX_ANA_CTRL_REG_2 0x5021 +#define TX_DIG_CTRL_REG_2 0x5024 +#define TXDA_CYA_AUXDA_CYA 0x5025 +#define TX_ANA_CTRL_REG_3 0x5026 +#define TX_ANA_CTRL_REG_4 0x5027 +#define TX_ANA_CTRL_REG_5 0x5029 +#define RX_PSC_A0 0x8000 +#define RX_PSC_CAL 0x8006 +#define PHY_HDP_MODE_CTRL 0xC008 +#define PHY_HDP_CLK_CTL 0xC009 +#define PHY_ISO_CMN_CTRL0xC010 +#define PHY_PMA_CMN_CTRL1 0xC800 +#def
[PATCH v4 09/10] dt-bindings: phy: Add Cadence HDP-TX HDMI PHY
Add bindings for Cadence HDP-TX HDMI PHY.
Signed-off-by: Sandor Yu
---
.../bindings/phy/cdns,hdptx-hdmi-phy.yaml | 52 +++
1 file changed, 52 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/cdns,hdptx-hdmi-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/cdns,hdptx-hdmi-phy.yaml
b/Documentation/devicetree/bindings/phy/cdns,hdptx-hdmi-phy.yaml
new file mode 100644
index ..99352e655eec
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/cdns,hdptx-hdmi-phy.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/cdns,hdptx-hdmi-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence HDP-TX(HDMI/DisplayPort) PHY for HDMI protocol
+
+maintainers:
+ - Sandor Yu
+
+properties:
+ compatible:
+enum:
+ - cdns,hdptx-hdmi-phy
+
+ reg:
+maxItems: 1
+
+ clocks:
+items:
+ - description: PHY reference clock.
+ - description: APB clock.
+
+ clock-names:
+items:
+ - const: refclk
+ - const: apbclk
+
+ "#phy-cells":
+const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+hdmi_phy: phy@32c0 {
+compatible = "cdns,hdptx-hdmi-phy";
+reg = <0x32c0 0x10>;
+#phy-cells = <0>;
+clocks = <&hdmi_phy_27m>, <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+clock-names = "refclk", "apbclk";
+};
--
2.34.1
[Bug 216716] New: [drm:psp_resume [amdgpu]] *ERROR* PSP resume failed on r9 7950x igpu
https://bugzilla.kernel.org/show_bug.cgi?id=216716 Bug ID: 216716 Summary: [drm:psp_resume [amdgpu]] *ERROR* PSP resume failed on r9 7950x igpu Product: Drivers Version: 2.5 Kernel Version: 6.0.9 Hardware: All OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-...@kernel-bugs.osdl.org Reporter: ker...@januszmk.pl Regression: No Created attachment 303246 --> https://bugzilla.kernel.org/attachment.cgi?id=303246&action=edit dmesg Sometimes when I put my pc to sleep through "echo mem > /sys/power/state", resuming fails. I am able to ssh into machine. Attaching dmesg, on this session I was able to sleep/resume properly once, and after putting it to sleep for the night, it didn't resume. I had this problem on 6.0.5, 6.0.7 and 6.0.9. Its integrated gpu on r9 7950x. -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.
