Re: [PATCH V3 5/13] hid: use time_is_after_jiffies() instead of open coding it
On Tue, Feb 15, 2022 at 2:56 AM Qing Wang wrote:
>
> From: Wang Qing
>
> Use the helper function time_is_{before,after}_jiffies() to improve
> code readability.
>
> Signed-off-by: Wang Qing
> Acked-by: Srinivas Pandruvada
FWIW, this one is
Acked-by: Benjamin Tissoires
Wang, is there any plan to take this series through the trivial tree
or should each maintainer take the matching patches?
Cheers,
Benjamin
> ---
> drivers/hid/intel-ish-hid/ipc/ipc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/hid/intel-ish-hid/ipc/ipc.c
> b/drivers/hid/intel-ish-hid/ipc/ipc.c
> index 8ccb246..15e1423
> --- a/drivers/hid/intel-ish-hid/ipc/ipc.c
> +++ b/drivers/hid/intel-ish-hid/ipc/ipc.c
> @@ -578,7 +578,7 @@ static void _ish_sync_fw_clock(struct ishtp_device *dev)
> static unsigned longprev_sync;
> uint64_tusec;
>
> - if (prev_sync && jiffies - prev_sync < 20 * HZ)
> + if (prev_sync && time_is_after_jiffies(prev_sync + 20 * HZ))
> return;
>
> prev_sync = jiffies;
> --
> 2.7.4
>
Re: [PATCH V3 6/13] input: serio: use time_is_before_jiffies() instead of open coding it
On Tue, Feb 15, 2022 at 2:57 AM Qing Wang wrote:
>
> From: Wang Qing
>
> Use the helper function time_is_{before,after}_jiffies() to improve
> code readability.
>
> Signed-off-by: Wang Qing
> ---
Reviewed-by: Benjamin Tissoires
Cheers,
Benjamin
> drivers/input/serio/ps2-gpio.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/input/serio/ps2-gpio.c b/drivers/input/serio/ps2-gpio.c
> index 8970b49..7834296
> --- a/drivers/input/serio/ps2-gpio.c
> +++ b/drivers/input/serio/ps2-gpio.c
> @@ -136,7 +136,7 @@ static irqreturn_t ps2_gpio_irq_rx(struct ps2_gpio_data
> *drvdata)
> if (old_jiffies == 0)
> old_jiffies = jiffies;
>
> - if ((jiffies - old_jiffies) > usecs_to_jiffies(100)) {
> + if (time_is_before_jiffies(old_jiffies + usecs_to_jiffies(100))) {
> dev_err(drvdata->dev,
> "RX: timeout, probably we missed an interrupt\n");
> goto err;
> @@ -237,7 +237,7 @@ static irqreturn_t ps2_gpio_irq_tx(struct ps2_gpio_data
> *drvdata)
> if (old_jiffies == 0)
> old_jiffies = jiffies;
>
> - if ((jiffies - old_jiffies) > usecs_to_jiffies(100)) {
> + if (time_is_before_jiffies(old_jiffies + usecs_to_jiffies(100))) {
> dev_err(drvdata->dev,
> "TX: timeout, probably we missed an interrupt\n");
> goto err;
> --
> 2.7.4
>
Re: [PATCH] amdgpu: assign adev after null check
Am 15.02.22 um 02:59 schrieb Qing Wang:
From: Wang Qing
adev should be assigned after a null check
I would rather remove the NULL check altogether.
The caller is supposed to make sure that the context is valid and even
if it isn't that's not a recoverable error here.
Regards,
Christian.
Signed-off-by: Wang Qing
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 2c929fa..da114f7
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -259,12 +259,13 @@ static void amdgpu_ctx_fini_entity(struct
amdgpu_ctx_entity *entity)
static int amdgpu_ctx_get_stable_pstate(struct amdgpu_ctx *ctx,
u32 *stable_pstate)
{
- struct amdgpu_device *adev = ctx->adev;
+ struct amdgpu_device *adev;
enum amd_dpm_forced_level current_level;
if (!ctx)
return -EINVAL;
+ adev = ctx->adev;
current_level = amdgpu_dpm_get_performance_level(adev);
switch (current_level) {
@@ -290,13 +291,14 @@ static int amdgpu_ctx_get_stable_pstate(struct amdgpu_ctx
*ctx,
static int amdgpu_ctx_set_stable_pstate(struct amdgpu_ctx *ctx,
u32 stable_pstate)
{
- struct amdgpu_device *adev = ctx->adev;
+ struct amdgpu_device *adev;
enum amd_dpm_forced_level level;
int r;
if (!ctx)
return -EINVAL;
+ adev = ctx->adev;
mutex_lock(&adev->pm.stable_pstate_ctx_lock);
if (adev->pm.stable_pstate_ctx && adev->pm.stable_pstate_ctx != ctx) {
r = -EBUSY;
Re: [PATCH v3 0/3] Add connector_type to debug info to differentiate between eDP and DP
On Wed, 02 Feb 2022, Kuogee Hsieh wrote: > 1) Add connector_type to debug info to differentiate between eDP and DP > 2) add more debug info to cover dp Phy > 3) repalce DRM_DEBUG_DP with drm_debug_dp In the future, please include the drm/msm/dp prefix also in the cover letter. Thanks. BR, Jani. > > Kuogee Hsieh (3): > drm/msm/dp: add connector type to enhance debug messages > drm/msm/dp: enhance debug info related to dp phy > drm/msm/dp: replace DRM_DEBUG_DP marco with drm_dbg_dp > > drivers/gpu/drm/msm/dp/dp_audio.c | 49 +-- > drivers/gpu/drm/msm/dp/dp_catalog.c | 34 ++- > drivers/gpu/drm/msm/dp/dp_ctrl.c| 116 > +++- > drivers/gpu/drm/msm/dp/dp_display.c | 103 ++-- > drivers/gpu/drm/msm/dp/dp_drm.c | 4 +- > drivers/gpu/drm/msm/dp/dp_link.c| 99 +- > drivers/gpu/drm/msm/dp/dp_panel.c | 43 +++-- > drivers/gpu/drm/msm/dp/dp_parser.c | 2 +- > drivers/gpu/drm/msm/dp/dp_power.c | 20 --- > 9 files changed, 283 insertions(+), 187 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center
RE: [PATCH V3 5/13] hid: use time_is_after_jiffies() instead of open coding it
>>On Tue, Feb 15, 2022 at 2:56 AM Qing Wang wrote:
>>
>> From: Wang Qing
>>
>> Use the helper function time_is_{before,after}_jiffies() to improve
>> code readability.
>>
>> Signed-off-by: Wang Qing
>> Acked-by: Srinivas Pandruvada
>
>FWIW, this one is
>Acked-by: Benjamin Tissoires
>
>Wang, is there any plan to take this series through the trivial tree
That's why I batch them in a series, but I don't know how to take
this series through the trivial tree directly.
I would appreciate if you could help.
Thanks,
Wang
>or should each maintainer take the matching patches?
>
>Cheers,
>Benjamin
>
>> ---
>> drivers/hid/intel-ish-hid/ipc/ipc.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/hid/intel-ish-hid/ipc/ipc.c
>> b/drivers/hid/intel-ish-hid/ipc/ipc.c
>> index 8ccb246..15e1423
>> --- a/drivers/hid/intel-ish-hid/ipc/ipc.c
>> +++ b/drivers/hid/intel-ish-hid/ipc/ipc.c
>> @@ -578,7 +578,7 @@ static void _ish_sync_fw_clock(struct ishtp_device *dev)
>> static unsigned long prev_sync;
>> uint64_t usec;
>>
>> - if (prev_sync && jiffies - prev_sync < 20 * HZ)
>> + if (prev_sync && time_is_after_jiffies(prev_sync + 20 * HZ))
>> return;
>>
>> prev_sync = jiffies;
>> --
>> 2.7.4
>>
Re: [Intel-gfx] [PATCH] drm/i915/guc: Initialize GuC submission locks and queues early
On 15/02/2022 01:11, Daniele Ceraolo Spurio wrote:
Move initialization of submission-related spinlock, lists and workers to
init_early. This fixes an issue where if the GuC init fails we might
still try to get the lock in the context cleanup code. Note that it is
What's the worst case impact on non-debug builds aka is Fixes: required?
Regards,
Tvrtko
safe to call the GuC context cleanup code even if the init failed
because all contexts are initialized with an invalid GuC ID, which will
cause the GuC side of the cleanup to be skipped, so it is easier to just
make sure the variables are initialized than to special case the cleanup
to handle the case when they're not.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/4932
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matthew Brost
Cc: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b3a429a92c0da..2160da2c83cbf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1818,24 +1818,11 @@ int intel_guc_submission_init(struct intel_guc *guc)
*/
GEM_BUG_ON(!guc->lrc_desc_pool);
- xa_init_flags(&guc->context_lookup, XA_FLAGS_LOCK_IRQ);
-
- spin_lock_init(&guc->submission_state.lock);
- INIT_LIST_HEAD(&guc->submission_state.guc_id_list);
- ida_init(&guc->submission_state.guc_ids);
- INIT_LIST_HEAD(&guc->submission_state.destroyed_contexts);
- INIT_WORK(&guc->submission_state.destroyed_worker,
- destroyed_worker_func);
- INIT_WORK(&guc->submission_state.reset_fail_worker,
- reset_fail_worker_func);
-
guc->submission_state.guc_ids_bitmap =
bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
if (!guc->submission_state.guc_ids_bitmap)
return -ENOMEM;
- spin_lock_init(&guc->timestamp.lock);
- INIT_DELAYED_WORK(&guc->timestamp.work, guc_timestamp_ping);
guc->timestamp.ping_delay = (POLL_TIME_CLKS / gt->clock_frequency + 1)
* HZ;
guc->timestamp.shift = gpm_timestamp_shift(gt);
@@ -3831,6 +3818,20 @@ static bool __guc_submission_selected(struct intel_guc *guc)
void intel_guc_submission_init_early(struct intel_guc *guc)
{
+ xa_init_flags(&guc->context_lookup, XA_FLAGS_LOCK_IRQ);
+
+ spin_lock_init(&guc->submission_state.lock);
+ INIT_LIST_HEAD(&guc->submission_state.guc_id_list);
+ ida_init(&guc->submission_state.guc_ids);
+ INIT_LIST_HEAD(&guc->submission_state.destroyed_contexts);
+ INIT_WORK(&guc->submission_state.destroyed_worker,
+ destroyed_worker_func);
+ INIT_WORK(&guc->submission_state.reset_fail_worker,
+ reset_fail_worker_func);
+
+ spin_lock_init(&guc->timestamp.lock);
+ INIT_DELAYED_WORK(&guc->timestamp.work, guc_timestamp_ping);
+
guc->submission_state.num_guc_ids = GUC_MAX_LRC_DESCRIPTORS;
guc->submission_supported = __guc_submission_supported(guc);
guc->submission_selected = __guc_submission_selected(guc);
[PATCH] drm/amdkfd: Replace zero-length array with flexible-array member
From: Changcheng Deng
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use "flexible array members" for these cases. The older
style of one-element or zero-length arrays should no longer be used.
Reference:
https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arrays
Reported-by: Zeal Robot
Signed-off-by: Changcheng Deng
---
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index e54a52785690..7d39191d13f6 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -1084,7 +1084,7 @@ struct kfd_criu_svm_range_priv_data {
uint64_t start_addr;
uint64_t size;
/* Variable length array of attributes */
- struct kfd_ioctl_svm_attribute attrs[0];
+ struct kfd_ioctl_svm_attribute attrs[];
};
struct kfd_criu_queue_priv_data {
--
2.25.1
Re: [PATCH] drm/amdkfd: Replace zero-length array with flexible-array member
Am 15.02.22 um 10:11 schrieb cgel@gmail.com:
From: Changcheng Deng
There is a regular need in the kernel to provide a way to declare having
a dynamically sized set of trailing elements in a structure. Kernel code
should always use "flexible array members" for these cases. The older
style of one-element or zero-length arrays should no longer be used.
Reference:
https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arrays
I think you should harden the wording here into "must" no longer be used.
We had so many problems with that and certain gcc versions that we
should have this automatically checked somehow.
Reported-by: Zeal Robot
Signed-off-by: Changcheng Deng
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index e54a52785690..7d39191d13f6 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -1084,7 +1084,7 @@ struct kfd_criu_svm_range_priv_data {
uint64_t start_addr;
uint64_t size;
/* Variable length array of attributes */
- struct kfd_ioctl_svm_attribute attrs[0];
+ struct kfd_ioctl_svm_attribute attrs[];
};
struct kfd_criu_queue_priv_data {
Re: [PATCH] drm/panfrost: Dynamically allocate pm_domains
Il 14/02/22 21:55, Alyssa Rosenzweig ha scritto:
mali_kbase hardcodes MAX_PM_DOMAINS (=5 for the mt8192 kernel). I have
no real objection to it but Angelo did. Maybe should've marked this RFC.
Clarifying, the suggested patch was not a big objection, but I think that it
would be a nice preventive cleanup that is useful for the power tree that has
to be managed on MT8192 and possibly on other SoCs.
I would expect to see a variable amount of PM domains to take care of as time
goes by (with new SoCs, not necessarily only MediaTek) due to granular power
optimizations but, at the same time, dynamically allocating the pm_domain_devs
and links structures makes this driver to also be nice with older platforms,
where memory is a little more constrained, allowing Linux to have a lighter
footprint, even if not by much.
Logic for this footprint saving is "a little here, a little there, becomes a
bit more considerable" (of course, being aware of both upsides and downsides
in dynamically allocating things, and avoiding to write gigabytes of text to
explain common knowledge).
P.S.: Thank you all!
Regards,
Angelo
On Mon, Feb 14, 2022 at 03:31:32PM -0500, Alyssa Rosenzweig wrote:
MT8192 requires 5 power domains. Rather than bump MAX_PM_DOMAINS and
waste memory on every supported Panfrost chip, instead dynamically
allocate pm_domain_devs and pm_domain_links. This adds some flexibility;
it seems inevitable a new MediaTek device will require more than 5
domains.
On non-MediaTek devices, this saves a small amount of memory.
Suggested-by: AngeloGioacchino Del Regno
Signed-off-by: Alyssa Rosenzweig
---
drivers/gpu/drm/panfrost/panfrost_device.c | 14 ++
drivers/gpu/drm/panfrost/panfrost_device.h | 5 ++---
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c
b/drivers/gpu/drm/panfrost/panfrost_device.c
index ee612303f076..661cdec320af 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.c
+++ b/drivers/gpu/drm/panfrost/panfrost_device.c
@@ -127,7 +127,10 @@ static void panfrost_pm_domain_fini(struct panfrost_device
*pfdev)
{
int i;
- for (i = 0; i < ARRAY_SIZE(pfdev->pm_domain_devs); i++) {
+ if (!pfdev->pm_domain_devs || !pfdev->pm_domain_links)
+ return;
+
+ for (i = 0; i < pfdev->comp->num_pm_domains; i++) {
if (!pfdev->pm_domain_devs[i])
break;
@@ -161,9 +164,12 @@ static int panfrost_pm_domain_init(struct panfrost_device *pfdev)
return -EINVAL;
}
- if (WARN(num_domains > ARRAY_SIZE(pfdev->pm_domain_devs),
- "Too many supplies in compatible structure.\n"))
- return -EINVAL;
+ pfdev->pm_domain_devs = devm_kcalloc(pfdev->dev, num_domains,
+sizeof(*pfdev->pm_domain_devs),
+GFP_KERNEL);
+ pfdev->pm_domain_links = devm_kcalloc(pfdev->dev, num_domains,
+ sizeof(*pfdev->pm_domain_links),
+ GFP_KERNEL);
for (i = 0; i < num_domains; i++) {
pfdev->pm_domain_devs[i] =
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h
b/drivers/gpu/drm/panfrost/panfrost_device.h
index 8b25278f34c8..98e3039696f9 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.h
+++ b/drivers/gpu/drm/panfrost/panfrost_device.h
@@ -22,7 +22,6 @@ struct panfrost_job;
struct panfrost_perfcnt;
#define NUM_JOB_SLOTS 3
-#define MAX_PM_DOMAINS 3
struct panfrost_features {
u16 id;
@@ -87,8 +86,8 @@ struct panfrost_device {
struct regulator_bulk_data *regulators;
struct reset_control *rstc;
/* pm_domains for devices with more than one. */
- struct device *pm_domain_devs[MAX_PM_DOMAINS];
- struct device_link *pm_domain_links[MAX_PM_DOMAINS];
+ struct device **pm_domain_devs;
+ struct device_link **pm_domain_links;
bool coherent;
struct panfrost_features features;
--
2.34.1
RE: [2/2] drm/amd: use fixed dsc bits-per-pixel from edid
[Public]
Hi,
Thanks for the patch and it LGTM.
Feel free to add
Reviewed-by: Wayne Lin
> -Original Message-
> From: Yaroslav Bolyukin
> Sent: Sunday, February 13, 2022 9:31 PM
> To: linux-ker...@vger.kernel.org; dri-devel@lists.freedesktop.org;
> amd-...@lists.freedesktop.org
> Cc: Thomas Zimmermann ; David Airlie ;
> Rodrigo Siqueira ; Pan,
> Xinhui ; Leo Li ; Alex Deucher
> ; Christian K?nig
> ; Yaroslav Bolyukin
> Subject: [2/2] drm/amd: use fixed dsc bits-per-pixel from edid
>
> VESA vendor header from DisplayID spec may contain fixed bit per pixel rate,
> it should be respected by drm driver
>
> Signed-off-by: Yaroslav Bolyukin
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 ++
> drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 3 ++-
> drivers/gpu/drm/amd/display/dc/dc_types.h | 3 +++
> 3 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> index 29f07c26d..b34dd89ae 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> @@ -118,6 +118,8 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
>
> edid_caps->edid_hdmi = connector->display_info.is_hdmi;
>
> + edid_caps->dsc_fixed_bits_per_pixel_x16 =
> +connector->display_info.dp_dsc_bpp;
> +
> sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
> if (sad_count <= 0)
> return result;
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
> index 57cf4cb82..f8516ec70 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
> @@ -105,6 +105,8 @@ static bool dc_stream_construct(struct dc_stream_state
> *stream,
>
> /* EDID CAP translation for HDMI 2.0 */
> stream->timing.flags.LTE_340MCSC_SCRAMBLE =
> dc_sink_data->edid_caps.lte_340mcsc_scramble;
> + stream->timing.dsc_fixed_bits_per_pixel_x16 =
> + dc_sink_data->edid_caps.dsc_fixed_bits_per_pixel_x16;
>
> memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg));
> stream->timing.dsc_cfg.num_slices_h = 0; @@ -738,4 +740,3 @@ void
> dc_stream_log(const struct dc *dc, const struct
> dc_stream_state *stream)
> "\tlink: %d\n",
> stream->link->link_index);
> }
> -
> diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
> b/drivers/gpu/drm/amd/display/dc/dc_types.h
> index 0285a4b38..ce2e11d70 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
> @@ -227,6 +227,9 @@ struct dc_edid_caps {
> bool edid_hdmi;
> bool hdr_supported;
>
> + /* DisplayPort caps */
> + uint32_t dsc_fixed_bits_per_pixel_x16;
> +
> struct dc_panel_patch panel_patch;
> };
>
--
Regards,
Wayne Lin
[PATCH 1/3] video: fbdev: atari: Fix TT High video mode
The horizontal resolution (640) for the TT High video mode (1280x960) is
definitely bogus. While fixing that, correct the timings to match the
TTM195 service manual.
Signed-off-by: Geert Uytterhoeven
---
Untested on actual hardware.
v3:
- Adjust pixclock from 7761 to 7760 to match 4 * 32.215905 MHz
crystal oscillator frequency,
- Make it part of a series.
v2[1]:
- Use correct base.
[1] https://lore.kernel.org/r/20201101102759.2890612-1-ge...@linux-m68k.org/
---
drivers/video/fbdev/atafb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/fbdev/atafb.c b/drivers/video/fbdev/atafb.c
index e3812a8ff55a4fb8..a9f25cab4a1e6737 100644
--- a/drivers/video/fbdev/atafb.c
+++ b/drivers/video/fbdev/atafb.c
@@ -487,8 +487,8 @@ static struct fb_videomode atafb_modedb[] __initdata = {
"tt-mid", 60, 640, 480, 31041, 120, 100, 8, 16, 140, 30,
0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
}, {
- /* 1280x960, 29 kHz, 60 Hz (TT high) */
- "tt-high", 57, 640, 960, 31041, 120, 100, 8, 16, 140, 30,
+ /* 1280x960, 72 kHz, 72 Hz (TT high) */
+ "tt-high", 57, 1280, 960, 7760, 260, 60, 36, 4, 192, 4,
0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
},
--
2.25.1
[PATCH 0/3] video: fbdev: atari: Miscellaneous fixes
Hi Helge,
This is a small series of miscellaneous fixes for the Atari frame buffer
device driver.
The first patch has been sent before, and is untested, as I have no
access to the hardware.
The other patches have been tested on ARAnyM.
Thanks!
Geert Uytterhoeven (3):
video: fbdev: atari: Fix TT High video mode
video: fbdev: atari: Convert to standard round_up() helper
video: fbdev: atari: Remove unused atafb_setcolreg()
drivers/video/fbdev/atafb.c | 23 +--
1 file changed, 5 insertions(+), 18 deletions(-)
--
2.25.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH 3/3] video: fbdev: atari: Remove unused atafb_setcolreg()
atafb_probe() overrides the atafb_ops.fb_setcolreg() method to match the
actual graphics hardware. Besides, the shifts by 8 were bogus, as the
individual .fb_setcolreg() implementations already take care of that.
Signed-off-by: Geert Uytterhoeven
---
drivers/video/fbdev/atafb.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/drivers/video/fbdev/atafb.c b/drivers/video/fbdev/atafb.c
index b9d6aaaeae43f2f1..e95333e004744bf5 100644
--- a/drivers/video/fbdev/atafb.c
+++ b/drivers/video/fbdev/atafb.c
@@ -2404,16 +2404,6 @@ static void atafb_set_disp(struct fb_info *info)
atari_stram_to_virt(info->fix.smem_start));
}
-static int atafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
- u_int transp, struct fb_info *info)
-{
- red >>= 8;
- green >>= 8;
- blue >>= 8;
-
- return info->fbops->fb_setcolreg(regno, red, green, blue, transp, info);
-}
-
static int
atafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
@@ -2724,7 +2714,6 @@ static struct fb_ops atafb_ops = {
.owner =THIS_MODULE,
.fb_check_var = atafb_check_var,
.fb_set_par = atafb_set_par,
- .fb_setcolreg = atafb_setcolreg,
.fb_blank = atafb_blank,
.fb_pan_display = atafb_pan_display,
.fb_fillrect= atafb_fillrect,
--
2.25.1
[PATCH 2/3] video: fbdev: atari: Convert to standard round_up() helper
Remove the custom macro up(), and convert the code to use the standard
round_up() helper instead.
Signed-off-by: Geert Uytterhoeven
---
drivers/video/fbdev/atafb.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/video/fbdev/atafb.c b/drivers/video/fbdev/atafb.c
index a9f25cab4a1e6737..b9d6aaaeae43f2f1 100644
--- a/drivers/video/fbdev/atafb.c
+++ b/drivers/video/fbdev/atafb.c
@@ -76,8 +76,6 @@
#define SWITCH_SND7 0x80
#define SWITCH_NONE 0x00
-#define up(x, r) (((x) + (r) - 1) & ~((r)-1))
-
static int default_par;/* default resolution (0=none) */
@@ -1649,12 +1647,12 @@ static int falcon_pan_display(struct fb_var_screeninfo
*var,
int bpp = info->var.bits_per_pixel;
if (bpp == 1)
- var->xoffset = up(var->xoffset, 32);
+ var->xoffset = round_up(var->xoffset, 32);
if (bpp != 16)
par->hw.falcon.xoffset = var->xoffset & 15;
else {
par->hw.falcon.xoffset = 0;
- var->xoffset = up(var->xoffset, 2);
+ var->xoffset = round_up(var->xoffset, 2);
}
par->hw.falcon.line_offset = bpp *
(info->var.xres_virtual - info->var.xres) / 16;
@@ -2268,7 +2266,7 @@ static int pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
if (!fbhw->set_screen_base ||
(!ATARIHW_PRESENT(EXTD_SHIFTER) && var->xoffset))
return -EINVAL;
- var->xoffset = up(var->xoffset, 16);
+ var->xoffset = round_up(var->xoffset, 16);
par->screen_base = screen_base +
(var->yoffset * info->var.xres_virtual + var->xoffset)
* info->var.bits_per_pixel / 8;
--
2.25.1
Re: [PATCH v2 2/3] mm/gup.c: Migrate device coherent pages when pinning instead of failing
On 11.02.22 00:41, Alistair Popple wrote:
> On Thursday, 10 February 2022 10:47:35 PM AEDT David Hildenbrand wrote:
>> On 10.02.22 12:39, Alistair Popple wrote:
>>> On Thursday, 10 February 2022 9:53:38 PM AEDT David Hildenbrand wrote:
On 07.02.22 05:26, Alistair Popple wrote:
> Currently any attempts to pin a device coherent page will fail. This is
> because device coherent pages need to be managed by a device driver, and
> pinning them would prevent a driver from migrating them off the device.
>
> However this is no reason to fail pinning of these pages. These are
> coherent and accessible from the CPU so can be migrated just like
> pinning ZONE_MOVABLE pages. So instead of failing all attempts to pin
> them first try migrating them out of ZONE_DEVICE.
>
> Signed-off-by: Alistair Popple
> Acked-by: Felix Kuehling
> ---
>
> Changes for v2:
>
> - Added Felix's Acked-by
> - Fixed missing check for dpage == NULL
>
> mm/gup.c | 105 ++--
> 1 file changed, 95 insertions(+), 10 deletions(-)
>
> diff --git a/mm/gup.c b/mm/gup.c
> index 56d9577..5e826db 100644
> --- a/mm/gup.c
> +++ b/mm/gup.c
> @@ -1861,6 +1861,60 @@ struct page *get_dump_page(unsigned long addr)
>
> #ifdef CONFIG_MIGRATION
> /*
> + * Migrates a device coherent page back to normal memory. Caller should
> have a
> + * reference on page which will be copied to the new page if migration is
> + * successful or dropped on failure.
> + */
> +static struct page *migrate_device_page(struct page *page,
> + unsigned int gup_flags)
> +{
> + struct page *dpage;
> + struct migrate_vma args;
> + unsigned long src_pfn, dst_pfn = 0;
> +
> + lock_page(page);
> + src_pfn = migrate_pfn(page_to_pfn(page)) | MIGRATE_PFN_MIGRATE;
> + args.src = &src_pfn;
> + args.dst = &dst_pfn;
> + args.cpages = 1;
> + args.npages = 1;
> + args.vma = NULL;
> + migrate_vma_setup(&args);
> + if (!(src_pfn & MIGRATE_PFN_MIGRATE))
> + return NULL;
> +
> + dpage = alloc_pages(GFP_USER | __GFP_NOWARN, 0);
> +
> + /*
> + * get/pin the new page now so we don't have to retry gup after
> + * migrating. We already have a reference so this should never fail.
> + */
> + if (dpage && WARN_ON_ONCE(!try_grab_page(dpage, gup_flags))) {
> + __free_pages(dpage, 0);
> + dpage = NULL;
> + }
> +
> + if (dpage) {
> + lock_page(dpage);
> + dst_pfn = migrate_pfn(page_to_pfn(dpage));
> + }
> +
> + migrate_vma_pages(&args);
> + if (src_pfn & MIGRATE_PFN_MIGRATE)
> + copy_highpage(dpage, page);
> + migrate_vma_finalize(&args);
> + if (dpage && !(src_pfn & MIGRATE_PFN_MIGRATE)) {
> + if (gup_flags & FOLL_PIN)
> + unpin_user_page(dpage);
> + else
> + put_page(dpage);
> + dpage = NULL;
> + }
> +
> + return dpage;
> +}
> +
> +/*
> * Check whether all pages are pinnable, if so return number of pages.
> If some
> * pages are not pinnable, migrate them, and unpin all pages. Return
> zero if
> * pages were migrated, or if some pages were not successfully isolated.
> @@ -1888,15 +1942,40 @@ static long
> check_and_migrate_movable_pages(unsigned long nr_pages,
> continue;
> prev_head = head;
> /*
> - * If we get a movable page, since we are going to be pinning
> - * these entries, try to move them out if possible.
> + * Device coherent pages are managed by a driver and should not
> + * be pinned indefinitely as it prevents the driver moving the
> + * page. So when trying to pin with FOLL_LONGTERM instead try
> + * migrating page out of device memory.
>*/
> if (is_dev_private_or_coherent_page(head)) {
> + /*
> + * device private pages will get faulted in during gup
> + * so it shouldn't be possible to see one here.
> + */
> WARN_ON_ONCE(is_device_private_page(head));
> - ret = -EFAULT;
> - goto unpin_pages;
> + WARN_ON_ONCE(PageCompound(head));
> +
> + /*
> + * migration will fail if the page is pinned, so convert
> + * the pin on the source page to a normal reference.
> + */
> + if (gup_flags & FOLL_PIN) {
> + get_page(head);
> + unpin_user_page(head);
> +
Re: [Intel-gfx] [PATCH v8 1/3] gpu: drm: separate panel orientation property creating and value setting
Greetings everyone, Padron for joining in so late o/ On Tue, 8 Feb 2022 at 08:42, Hsin-Yi Wang wrote: > > drm_dev_register() sets connector->registration_state to > DRM_CONNECTOR_REGISTERED and dev->registered to true. If > drm_connector_set_panel_orientation() is first called after > drm_dev_register(), it will fail several checks and results in following > warning. > > Add a function to create panel orientation property and set default value > to UNKNOWN, so drivers can call this function to init the property earlier > , and let the panel set the real value later. > The warning illustrates a genuine race condition, where userspace will read the old/invalid property value/state. So this patch masks away the WARNING without addressing the actual issue. Instead can we fix the respective drivers, so that no properties are created after drm_dev_register()? Longer version: As we look into drm_dev_register() it's in charge of creating the dev/sysfs nodes (et al). Note that connectors cannot disappear at runtime. For panel orientation, we are creating an immutable connector properly, meaning that as soon as drm_dev_register() is called we must ensure that the property is available (if applicable) and set to the correct value. For illustration, consider the following scenario: - DRM modules are loaded late - are not built-in and not part of initrd (or there's no initrd) - kernel boots - plymouth/similar user-space component kicks in before the driver/module is loaded - module gets loaded, drm_dev_register() kicks in populating /dev/dri/card0 - plymouth opens the dev node and reads DRM_MODE_PANEL_ORIENTATION_UNKNOWN - module updates the orientation property Thanks Emil
Re: [PATCH] drm/panfrost: Dynamically allocate pm_domains
On 2022-02-14 20:31, Alyssa Rosenzweig wrote:
MT8192 requires 5 power domains. Rather than bump MAX_PM_DOMAINS and
waste memory on every supported Panfrost chip, instead dynamically
allocate pm_domain_devs and pm_domain_links. This adds some flexibility;
it seems inevitable a new MediaTek device will require more than 5
domains.
On non-MediaTek devices, this saves a small amount of memory.
Suggested-by: AngeloGioacchino Del Regno
Signed-off-by: Alyssa Rosenzweig
---
drivers/gpu/drm/panfrost/panfrost_device.c | 14 ++
drivers/gpu/drm/panfrost/panfrost_device.h | 5 ++---
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c
b/drivers/gpu/drm/panfrost/panfrost_device.c
index ee612303f076..661cdec320af 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.c
+++ b/drivers/gpu/drm/panfrost/panfrost_device.c
@@ -127,7 +127,10 @@ static void panfrost_pm_domain_fini(struct panfrost_device
*pfdev)
{
int i;
- for (i = 0; i < ARRAY_SIZE(pfdev->pm_domain_devs); i++) {
+ if (!pfdev->pm_domain_devs || !pfdev->pm_domain_links)
+ return;
+
+ for (i = 0; i < pfdev->comp->num_pm_domains; i++) {
if (!pfdev->pm_domain_devs[i])
break;
@@ -161,9 +164,12 @@ static int panfrost_pm_domain_init(struct panfrost_device *pfdev)
return -EINVAL;
}
- if (WARN(num_domains > ARRAY_SIZE(pfdev->pm_domain_devs),
- "Too many supplies in compatible structure.\n"))
- return -EINVAL;
+ pfdev->pm_domain_devs = devm_kcalloc(pfdev->dev, num_domains,
+sizeof(*pfdev->pm_domain_devs),
+GFP_KERNEL);
+ pfdev->pm_domain_links = devm_kcalloc(pfdev->dev, num_domains,
+ sizeof(*pfdev->pm_domain_links),
+ GFP_KERNEL);
Since we're not really doing any detailed management of our device
links, could we get away with using AUTOREMOVE_CONSUMER instead of
STATELESS to avoid having to explicitly keep track of them ourselves?
Robin.
for (i = 0; i < num_domains; i++) {
pfdev->pm_domain_devs[i] =
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h
b/drivers/gpu/drm/panfrost/panfrost_device.h
index 8b25278f34c8..98e3039696f9 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.h
+++ b/drivers/gpu/drm/panfrost/panfrost_device.h
@@ -22,7 +22,6 @@ struct panfrost_job;
struct panfrost_perfcnt;
#define NUM_JOB_SLOTS 3
-#define MAX_PM_DOMAINS 3
struct panfrost_features {
u16 id;
@@ -87,8 +86,8 @@ struct panfrost_device {
struct regulator_bulk_data *regulators;
struct reset_control *rstc;
/* pm_domains for devices with more than one. */
- struct device *pm_domain_devs[MAX_PM_DOMAINS];
- struct device_link *pm_domain_links[MAX_PM_DOMAINS];
+ struct device **pm_domain_devs;
+ struct device_link **pm_domain_links;
bool coherent;
struct panfrost_features features;
Re: linux-next: build failure after merge of the drm-intel tree
On Tue, 15 Feb 2022, Stephen Rothwell wrote:
> Hi all,
>
> After merging the drm-intel tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> drivers/gpu/drm/i915/gvt/kvmgt.c: In function 'handle_edid_regs':
> drivers/gpu/drm/i915/gvt/kvmgt.c:595:38: error: implicit declaration of
> function 'drm_edid_block_valid' [-Werror=implicit-function-declaration]
> 595 | if (!drm_edid_block_valid(
> | ^~~~
>
> Presumably caused by commit
>
> 14da21cc4671 ("drm/i915: axe lots of unnecessary includes from i915_drv.h")
>
> I am beginning to wonder if you guys run stuff through your CI before
> relasing to linux-next. Especially important when removing #include
> statements from include files :-)
Thanks for the report. Apparently CI (and I) have VFIO=n, VFIO_MDEV=n,
and DRM_I915_GVT_KVMGT=n.
BR,
Jani.
>
> I have used the drm-intel tree from next-20220214 for today.
--
Jani Nikula, Intel Open Source Graphics Center
Re: [PATCH v6 01/10] mm: add zone device coherent type memory support
On 11.02.22 17:56, Jason Gunthorpe wrote: > On Fri, Feb 11, 2022 at 05:49:08PM +0100, David Hildenbrand wrote: >> On 11.02.22 17:45, Jason Gunthorpe wrote: >>> On Fri, Feb 11, 2022 at 05:15:25PM +0100, David Hildenbrand wrote: >>> ... I'm pretty sure we cannot FOLL_PIN DEVICE_PRIVATE pages >>> >>> Currently the only way to get a DEVICE_PRIVATE page out of the page >>> tables is via hmm_range_fault() and that doesn't manipulate any ref >>> counts. >> >> Thanks for clarifying Jason! ... and AFAIU, device exclusive entries are >> essentially just pointers at ordinary PageAnon() pages. So with DEVICE >> COHERENT we'll have the first PageAnon() ZONE_DEVICE pages mapped as >> present in the page tables where GUP could FOLL_PIN them. > > This is my understanding > > Though you probably understand what PageAnon means alot better than I > do.. I wonder if it really makes sense to talk about that together > with ZONE_DEVICE which has alot in common with filesystem originated > pages too. For me, PageAnon() means that modifications are visible only to the modifying process. On actual CoW, the underlying page will get replaced -- in the world of DEVICE_COHERENT that would mean that once you write to a DEVICE_COHERENT you could suddenly have a !DEVICE_COHERENT page. PageAnon() pages don't have a mapping, thus they can only be found in MAP_ANON VMAs or in MAP_SHARED VMAs with MAP_PRIVATE. They can only be found via a page table, and not looked up via the page cache (excluding the swap cache). So if we have PageAnon() pages on ZONE_DEVICE, they generally have the exact same semantics as !ZONE_DEVICE pages, but the way they "appear" in the page tables the allocation/freeing path differs -- I guess :) ... and as we want pinning semantics to be different we have to touch GUP. > > I'm not sure what AMDs plan is here, is there an expecation that a GPU > driver will somehow stuff these pages into an existing anonymous > memory VMA or do they always come from a driver originated VMA? My understanding is that a driver can just decide to replace "ordinary" PageAnon() pages e.g., in a MAP_ANON VMA by these pages. Hopefully AMD can clarify. -- Thanks, David / dhildenb
Re: [PATCH v6 01/10] mm: add zone device coherent type memory support
On 11.02.22 18:07, Felix Kuehling wrote: > > Am 2022-02-11 um 11:39 schrieb David Hildenbrand: >> On 11.02.22 17:15, David Hildenbrand wrote: >>> On 01.02.22 16:48, Alex Sierra wrote: Device memory that is cache coherent from device and CPU point of view. This is used on platforms that have an advanced system bus (like CAPI or CXL). Any page of a process can be migrated to such memory. However, no one should be allowed to pin such memory so that it can always be evicted. Signed-off-by: Alex Sierra Acked-by: Felix Kuehling Reviewed-by: Alistair Popple >>> So, I'm currently messing with PageAnon() pages and CoW semantics ... >>> all these PageAnon() ZONE_DEVICE variants don't necessarily make my life >>> easier but I'm not sure yet if they make my life harder. I hope you can >>> help me understand some of that stuff. >>> >>> 1) What are expected CoW semantics for DEVICE_COHERENT? >>> >>> I assume we'll share them just like other PageAnon() pages during fork() >>> readable, and the first sharer writing to them receives an "ordinary" >>> !ZONE_DEVICE copy. >>> >>> So this would be just like DEVICE_EXCLUSIVE CoW handling I assume, just >>> that we don't have to go through the loop of restoring a device >>> exclusive entry? >>> >>> 2) How are these pages freed to clear/invalidate PageAnon() ? >>> >>> I assume for PageAnon() ZONE_DEVICE pages we'll always for via >>> free_devmap_managed_page(), correct? >>> >>> >>> 3) FOLL_PIN >>> >>> While you write "no one should be allowed to pin such memory", patch #2 >>> only blocks FOLL_LONGTERM. So I assume we allow ordinary FOLL_PIN and >>> you might want to be a bit more precise? >>> >>> >>> ... I'm pretty sure we cannot FOLL_PIN DEVICE_PRIVATE pages, but can we >>> FILL_PIN DEVICE_EXCLUSIVE pages? I strongly assume so? >>> >>> >>> Thanks for any information. >>> >> (digging a bit more, I realized that device exclusive pages are not >> actually/necessarily ZONE_DEVICE pages -- so I assume DEVICE_COHERENT >> will be the actual first PageAnon() ZONE_DEVICE pages that can be >> present in a page table.) > > I think DEVICE_GENERIC pages can also be mapped in the page table. In > fact, the first version of our patches attempted to add migration > support to DEVICE_GENERIC. But we were convinced to create a new > ZONE_DEVICE page type for our use case instead. Do you know if DEVICE_GENERIC pages would end up as PageAnon()? My assumption was that they would be part of a special mapping. -- Thanks, David / dhildenb
Re: [PATCH 1/9] dt-bindings: Add arm,mali-valhall compatible
On 2022-02-11 20:27, alyssa.rosenzw...@collabora.com wrote: From: Alyssa Rosenzweig From the kernel's perspective, pre-CSF Valhall is more or less compatible with Bifrost, although they differ to userspace. Add a compatible for Valhall to the existing Bifrost bindings documentation. Signed-off-by: Alyssa Rosenzweig Cc: devicet...@vger.kernel.org --- Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 63a08f3f321d..48aeabd2ed68 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -23,6 +23,7 @@ properties: - rockchip,px30-mali - rockchip,rk3568-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable + - const: arm,mali-valhall # Mali Valhall GPU model/revision is fully discoverable This requires all existing Bifrost users to add the Valhall compatible as well - I don't think that's what you want. From what we tossed about on IRC the other week, I'd imagined something more in the shape of: compatible: oneOf: - items: - enum: - vendor,soc-mali - ... - const: arm,mali-bifrost - items: - enum: - vendor,soc-mali - ... - const: arm,mali-valhall - const: arm,mali-bifrost #or not, depending on forward-compatibility preferences Cheers, Robin.
Re: [PATCH] drm/i915/perf: Skip the i915_perf_init for dg2
On 15/02/2022 05:31, Ramalingam C wrote:
i915_perf is not enabled for dg2 yet, hence skip the feature
initialization.
Signed-off-by: Ramalingam C
cc: Umesh Nerlige Ramappa
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_perf.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 36f1325baa7d..5ac9604d07b3 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4373,6 +4373,10 @@ void i915_perf_init(struct drm_i915_private *i915)
/* XXX const struct i915_perf_ops! */
+ /* i915_perf is not enabled for DG2 yet */
+ if (IS_DG2(i915))
+ return;
+
perf->oa_formats = oa_formats;
if (IS_HASWELL(i915)) {
perf->ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr;
Re: [Intel-gfx] [PATCH v8 1/3] gpu: drm: separate panel orientation property creating and value setting
On Tue, Feb 15, 2022 at 8:04 PM Emil Velikov wrote: > > Greetings everyone, > > Padron for joining in so late o/ > > On Tue, 8 Feb 2022 at 08:42, Hsin-Yi Wang wrote: > > > > drm_dev_register() sets connector->registration_state to > > DRM_CONNECTOR_REGISTERED and dev->registered to true. If > > drm_connector_set_panel_orientation() is first called after > > drm_dev_register(), it will fail several checks and results in following > > warning. > > > > Add a function to create panel orientation property and set default value > > to UNKNOWN, so drivers can call this function to init the property earlier > > , and let the panel set the real value later. > > > > The warning illustrates a genuine race condition, where userspace will > read the old/invalid property value/state. So this patch masks away > the WARNING without addressing the actual issue. > Instead can we fix the respective drivers, so that no properties are > created after drm_dev_register()? > 1. How about the proposal in previous version: v7 https://patchwork.kernel.org/project/linux-mediatek/patch/20220208073714.1540390-1-hsi...@chromium.org/ we separate property creation (drm_connector_init_panel_orientation_property) and value setting (drm_connector_set_panel_orientation). This is also similar to some of other optional properties are created, eg. vrr_capable. And drm drivers have to make sure that if they want to use this property, they have to create it before drm_dev_register(). For example, in the 2nd patch, mtk_drm sets the property before calling drm_dev_register(). 2. I'm not sure how to handle the case that if user space tries to read the property before the proper value is set. Currently drm creates this property and the panels[1] will set the correct value parsed from DT. If userspace calls before the panel sets the correct value, it will get unknown (similar to the illustration you mentioned below). Do you think that the drm should be responsible for parsing the value if the panel provides it? In this way it's guaranteed that the value is set when the property is created. [1] https://elixir.bootlin.com/linux/latest/A/ident/drm_connector_set_panel_orientation > Longer version: > As we look into drm_dev_register() it's in charge of creating the > dev/sysfs nodes (et al). Note that connectors cannot disappear at > runtime. > For panel orientation, we are creating an immutable connector > properly, meaning that as soon as drm_dev_register() is called we must > ensure that the property is available (if applicable) and set to the > correct value. > > For illustration, consider the following scenario: > - DRM modules are loaded late - are not built-in and not part of > initrd (or there's no initrd) > - kernel boots > - plymouth/similar user-space component kicks in before the > driver/module is loaded > - module gets loaded, drm_dev_register() kicks in populating /dev/dri/card0 > - plymouth opens the dev node and reads DRM_MODE_PANEL_ORIENTATION_UNKNOWN > - module updates the orientation property > > Thanks > Emil
Re: [PATCH v8 1/3] gpu: drm: separate panel orientation property creating and value setting
On Tue, Feb 15, 2022 at 12:03 PM Gabriel Krisman Bertazi
wrote:
>
> Hsin-Yi Wang writes:
>
> > On Tue, Feb 15, 2022 at 9:17 AM Gabriel Krisman Bertazi
> > wrote:
> >>
> >> Hsin-Yi Wang writes:
> >>
> >> > drm_dev_register() sets connector->registration_state to
> >> > DRM_CONNECTOR_REGISTERED and dev->registered to true. If
> >> > drm_connector_set_panel_orientation() is first called after
> >> > drm_dev_register(), it will fail several checks and results in following
> >> > warning.
> >>
> >> Hi,
> >>
> >> I stumbled upon this when investigating the same WARN_ON on amdgpu.
> >> Thanks for the patch :)
> >>
> >> > diff --git a/drivers/gpu/drm/drm_connector.c
> >> > b/drivers/gpu/drm/drm_connector.c
> >> > index a50c82bc2b2fec..572ead7ac10690 100644
> >> > --- a/drivers/gpu/drm/drm_connector.c
> >> > +++ b/drivers/gpu/drm/drm_connector.c
> >> > @@ -1252,7 +1252,7 @@ static const struct drm_prop_enum_list
> >> > dp_colorspaces[] = {
> >> > * INPUT_PROP_DIRECT) will still map 1:1 to the actual LCD panel
> >> > * coordinates, so if userspace rotates the picture to adjust for
> >> > * the orientation it must also apply the same transformation to the
> >> > - * touchscreen input coordinates. This property is initialized by
> >> > calling
> >> > + * touchscreen input coordinates. This property value is set by
> >> > calling
> >> > * drm_connector_set_panel_orientation() or
> >> > * drm_connector_set_panel_orientation_with_quirk()
> >> > *
> >> > @@ -2341,8 +2341,8 @@
> >> > EXPORT_SYMBOL(drm_connector_set_vrr_capable_property);
> >> > * @connector: connector for which to set the panel-orientation
> >> > property.
> >> > * @panel_orientation: drm_panel_orientation value to set
> >> > *
> >> > - * This function sets the connector's panel_orientation and attaches
> >> > - * a "panel orientation" property to the connector.
> >> > + * This function sets the connector's panel_orientation value. If the
> >> > property
> >> > + * doesn't exist, it will try to create one.
> >> > *
> >> > * Calling this function on a connector where the panel_orientation has
> >> > * already been set is a no-op (e.g. the orientation has been
> >> > overridden with
> >> > @@ -2373,19 +2373,12 @@ int drm_connector_set_panel_orientation(
> >> > info->panel_orientation = panel_orientation;
> >> >
> >> > prop = dev->mode_config.panel_orientation_property;
> >> > - if (!prop) {
> >> > - prop = drm_property_create_enum(dev,
> >> > DRM_MODE_PROP_IMMUTABLE,
> >> > - "panel orientation",
> >> > - drm_panel_orientation_enum_list,
> >> > -
> >> > ARRAY_SIZE(drm_panel_orientation_enum_list));
> >> > - if (!prop)
> >> > - return -ENOMEM;
> >> > -
> >> > - dev->mode_config.panel_orientation_property = prop;
> >> > - }
> >> > + if (!prop &&
> >> > + drm_connector_init_panel_orientation_property(connector) < 0)
> >> > + return -ENOMEM;
> >> >
> >>
> >> In the case where the property has not been created beforehand, you
> >> forgot to reinitialize prop here, after calling
> >> drm_connector_init_panel_orientation_property(). This means
> > hi Gabriel,
> >
> > drm_connector_init_panel_orientation_property() will create prop if
> > it's null. If prop fails to be created there, it will return -ENOMEM.
>
> Yes. But *after the property is successfully created*, the prop variable is
> still
> NULL. And then you call the following, using prop, which is still NULL:
>
> >> > + drm_object_property_set_value(&connector->base, prop,
> >> > + info->panel_orientation);
>
> This will do property->dev right on the first line of code, and dereference
> the
> null prop pointer.
Ah, right. Sorry that I totally missed this.
I'll fix it in the next version if the idea of this patch is accepted.
There might be another preferred solution for this.
>
> You must do
>
> prop = dev->mode_config.panel_orientation_property;
>
> again after drm_connector_init_panel_orientation_property successfully
> returns, or call drm_object_property_set_value using
> dev->mode_config.panel_orientation_property directly:
>
> drm_object_property_set_value(&connector->base,
> dev->mode_config.panel_orientation_property
> info->panel_orientation);
>
> --
> Gabriel Krisman Bertazi
Re: [PATCH v4 2/2] drm/msm/dp: enable widebus feature for display port
On 15/02/2022 01:39, Kuogee Hsieh wrote:
Widebus feature will transmit two pixel data per pixel clock to interface.
This feature now is required to be enabled to easy migrant to higher
resolution applications in future. However since some legacy chipsets
does not support this feature, this feature is enabled base on chip's
hardware revision.
changes in v2:
-- remove compression related code from timing
-- remove op_info from struct msm_drm_private
-- remove unnecessary wide_bus_en variables
-- pass wide_bus_en into timing configuration by struct msm_dp
Changes in v3:
-- split patch into 3 patches
-- enable widebus feature base on chip hardware revision
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 +++-
drivers/gpu/drm/msm/dp/dp_catalog.c | 36 +++--
drivers/gpu/drm/msm/dp/dp_catalog.h | 3 ++-
drivers/gpu/drm/msm/dp/dp_ctrl.c| 13 +++
drivers/gpu/drm/msm/dp/dp_ctrl.h| 1 +
drivers/gpu/drm/msm/dp/dp_display.c | 30
drivers/gpu/drm/msm/dp/dp_display.h | 2 ++
drivers/gpu/drm/msm/dp/dp_panel.c | 4 ++--
drivers/gpu/drm/msm/dp/dp_panel.h | 2 +-
drivers/gpu/drm/msm/msm_drv.h | 6 +
10 files changed, 90 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 0c22839..b2d23c2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2167,8 +2167,10 @@ int dpu_encoder_setup(struct drm_device *dev, struct
drm_encoder *enc,
timer_setup(&dpu_enc->vsync_event_timer,
dpu_encoder_vsync_event_handler,
0);
- else if (disp_info->intf_type == DRM_MODE_ENCODER_TMDS)
+ else if (disp_info->intf_type == DRM_MODE_ENCODER_TMDS) {
dpu_enc->dp = priv->dp[disp_info->h_tile_instance[0]];
+ dpu_enc->wide_bus_en = msm_dp_wide_bus_enable(dpu_enc->dp);
+ }
Please revert the order of the patches and move this chunk into the DPU
patch.
INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
dpu_encoder_off_work);
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c
b/drivers/gpu/drm/msm/dp/dp_catalog.c
index 64f0b26..99d087e 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
@@ -483,6 +483,27 @@ int dp_catalog_ctrl_set_pattern_state_bit(struct
dp_catalog *dp_catalog,
}
/**
+ * dp_catalog_hw_revision() - retrieve DP hw revision
+ *
+ * @dp_catalog: DP catalog structure
+ *
+ * return: u32
+ *
+ * This function return the DP controller hw revision
+ *
+ */
+u32 dp_catalog_hw_revision(struct dp_catalog *dp_catalog)
+{
+ u32 revision;
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+
+ revision = dp_read_ahb(catalog, REG_DP_HW_VERSION);
+
+ return revision;
+}
+
+/**
* dp_catalog_ctrl_reset() - reset DP controller
*
* @dp_catalog: DP catalog structure
@@ -739,10 +760,11 @@ u32 dp_catalog_ctrl_read_phy_pattern(struct dp_catalog
*dp_catalog)
}
/* panel related catalog functions */
-int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog)
+int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog, bool
wide_bus_en)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
+ u32 reg;
dp_write_link(catalog, REG_DP_TOTAL_HOR_VER,
dp_catalog->total);
@@ -751,7 +773,17 @@ int dp_catalog_panel_timing_cfg(struct dp_catalog
*dp_catalog)
dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY,
dp_catalog->width_blanking);
dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, dp_catalog->dp_active);
- dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, 0);
+
+ reg = dp_read_p0(catalog, MMSS_DP_INTF_CONFIG);
+
+ if (wide_bus_en)
+ reg |= BIT(4); /* DATABUS_WIDEN */
+ else
+ reg &= ~BIT(4);
+
+ DRM_DEBUG_DP("wide_bus_en=%d reg=%x\n", wide_bus_en, reg);
+
+ dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, reg);
return 0;
}
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h
index 7dea101..a3a0129 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.h
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.h
@@ -95,6 +95,7 @@ void dp_catalog_ctrl_config_misc(struct dp_catalog
*dp_catalog, u32 cc, u32 tb);
void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate,
u32 stream_rate_khz, bool fixed_nvid);
int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, u32
patter
Re: [PATCH v4 1/2] drm/msm/dp: revise timing engine programming to support widebus feature
On 15/02/2022 07:12, Bjorn Andersson wrote:
On Mon 14 Feb 16:39 CST 2022, Kuogee Hsieh wrote:
Widebus feature will transmit two pixel data per pixel clock to interface.
Timing engine provides driving force for this purpose. This patch base
on HPG (Hardware Programming Guide) to revise timing engine register
setting to accommodate both widebus and non widebus application. Also
horizontal width parameters need to be reduced by half since two pixel
data are clocked out per pixel clock when widebus feature enabled.
Widebus can be enabled individually at DP. However at DSI, widebus have
to be enabled along with DSC enabled to achieve pixel clock rate be
scaled down with same ratio as compression ratio when 10 bits per source
component. Therefore this patch have both widebus and compression covered
together so tat less efforts will be required when DSC enabled later.
Please split compression away. It's has hanging loose ends, which are
not tied anywhere. It can be sent as a part of this patch series, but
will be merged later, together with the DP DSC support.
In general, sending a patch that does several items at once is not the
best idea. Usually it's better to send two separate patches.
Changes in v2:
-- remove compression related code from timing
-- remove op_info from struct msm_drm_private
-- remove unnecessary wide_bus_en variables
-- pass wide_bus_en into timing configuration by struct msm_dp
Changes in v3:
-- split patch into 3 patches
Changes in v4:
-- rework timing engine to not interfere with dsi/hdmi
Thanks a lot, this is much cleaner now!
-- cover both widebus and compression
Even though the change relates to DP, I think it would be appropriate to
change the $subject prefix to "drm/msm/dpu".
When booting sc8180x the bootloader leaves widebus enabled in the eDP
controller, and the two patches takes care of this problem for me. I
also checked the DP still works.
Tested-by: Bjorn Andersson
Thanks,
Bjorn
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 10 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h| 2 +
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 14 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 99 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h| 6 ++
5 files changed, 115 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 0d315b4..0c22839 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -208,6 +208,8 @@ struct dpu_encoder_virt {
u32 idle_timeout;
+ bool wide_bus_en;
+
struct msm_dp *dp;
};
@@ -217,6 +219,14 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
};
+
+bool dpu_encoder_is_widebus_enabled(struct drm_encoder *drm_enc)
+{
+ struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
+
+ return dpu_enc->wide_bus_en;
+}
+
static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned
bpc)
{
struct dpu_hw_dither_cfg dither_cfg = { 0 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 99a5d73..893d74d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -168,4 +168,6 @@ int dpu_encoder_get_linecount(struct drm_encoder *drm_enc);
*/
int dpu_encoder_get_frame_count(struct drm_encoder *drm_enc);
+bool dpu_encoder_is_widebus_enabled(struct drm_encoder *drm_enc);
+
#endif /* __DPU_ENCODER_H__ */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 185379b..2af2bb7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -110,6 +110,20 @@ static void drm_mode_to_intf_timing_params(
timing->v_back_porch += timing->v_front_porch;
timing->v_front_porch = 0;
}
+
+ timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);
+
+ /*
+* for DP, divide the horizonal parameters by 2 when
+* widebus is enabled
+*/
+ if (phys_enc->hw_intf->cap->type == INTF_DP && timing->wide_bus_en) {
+ timing->width = timing->width >> 1;
+ timing->xres = timing->xres >> 1;
+ timing->h_back_porch = timing->h_back_porch >> 1;
+ timing->h_front_porch = timing->h_front_porch >> 1;
+ timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
+ }
}
static u32 get_horizontal_total(const struct intf_timing_params *timing)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 116e2b5..3b9273e 100644
--- a/drivers/gpu/drm
Re: [PATCH v2 1/2] drm/msm/dpu: Add INTF_5 interrupts
On 15/02/2022 07:33, Bjorn Andersson wrote:
SC8180x has the eDP controller wired up to INTF_5, so add the interrupt
register block for this interface to the list.
Signed-off-by: Bjorn Andersson
Reviewed-by: Dmitry Baryshkov
---
Changes since v1:
- None
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 6 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index a77a5eaa78ad..dd2161e7bdb6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -23,6 +23,7 @@
#define MDP_INTF_2_OFF0x6B000
#define MDP_INTF_3_OFF0x6B800
#define MDP_INTF_4_OFF0x6C000
+#define MDP_INTF_5_OFF 0x6C800
#define MDP_AD4_0_OFF 0x7C000
#define MDP_AD4_1_OFF 0x7D000
#define MDP_AD4_INTR_EN_OFF 0x41c
@@ -93,6 +94,11 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
MDP_INTF_4_OFF+INTF_INTR_EN,
MDP_INTF_4_OFF+INTF_INTR_STATUS
},
+ {
+ MDP_INTF_5_OFF+INTF_INTR_CLEAR,
+ MDP_INTF_5_OFF+INTF_INTR_EN,
+ MDP_INTF_5_OFF+INTF_INTR_STATUS
+ },
{
MDP_AD4_0_OFF + MDP_AD4_INTR_CLEAR_OFF,
MDP_AD4_0_OFF + MDP_AD4_INTR_EN_OFF,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index 1ab75cccd145..37379966d8ec 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -22,6 +22,7 @@ enum dpu_hw_intr_reg {
MDP_INTF2_INTR,
MDP_INTF3_INTR,
MDP_INTF4_INTR,
+ MDP_INTF5_INTR,
MDP_AD4_0_INTR,
MDP_AD4_1_INTR,
MDP_INTF0_7xxx_INTR,
--
With best wishes
Dmitry
Re: [PATCH v2 2/2] drm/msm/dpu: Add SC8180x to hw catalog
On 15/02/2022 07:33, Bjorn Andersson wrote:
From: Rob Clark
Add SC8180x to the hardware catalog, for initial support for the
platform. Due to limitations in the DP driver only one of the four DP
interfaces is left enabled.
The SC8180x platform supports the newly added DPU_INTF_WIDEBUS flag and
the Windows-on-Snapdragon bootloader leaves the widebus bit set, so this
is flagged appropriately to ensure widebus is disabled - for now.
Signed-off-by: Rob Clark
[bjorn: Reworked intf and irq definitions]
Signed-off-by: Bjorn Andersson
Reviewed-by: Dmitry Baryshkov
Nit: missing dt bindings change.
---
Changes since v1:
- Dropped widebus flag
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 129 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
drivers/gpu/drm/msm/msm_drv.c | 1 +
4 files changed, 132 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index aa75991903a6..7ac0fe32df49 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -90,6 +90,17 @@
BIT(MDP_INTF3_INTR) | \
BIT(MDP_INTF4_INTR))
+#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+ BIT(MDP_SSPP_TOP0_INTR2) | \
+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+ BIT(MDP_INTF0_INTR) | \
+ BIT(MDP_INTF1_INTR) | \
+ BIT(MDP_INTF2_INTR) | \
+ BIT(MDP_INTF3_INTR) | \
+ BIT(MDP_INTF4_INTR) | \
+ BIT(MDP_INTF5_INTR) | \
+ BIT(MDP_AD4_0_INTR) | \
+ BIT(MDP_AD4_1_INTR))
#define DEFAULT_PIXEL_RAM_SIZE (50 * 1024)
#define DEFAULT_DPU_LINE_WIDTH2048
@@ -225,6 +236,22 @@ static const struct dpu_caps sm8150_dpu_caps = {
.max_vdeci_exp = MAX_VERT_DECIMATION,
};
+static const struct dpu_caps sc8180x_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_30,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 4096,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
static const struct dpu_caps sm8250_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
@@ -293,6 +320,31 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sc8180x_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x45C,
+ .features = 0,
+ .highest_bank_bit = 0x3,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x2AC, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+ .reg_off = 0x2B4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+ .reg_off = 0x2BC, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+ .reg_off = 0x2C4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x2AC, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+ .reg_off = 0x2B4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+ .reg_off = 0x2BC, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+ .reg_off = 0x2C4, .bit_off = 8},
+ },
+};
+
static const struct dpu_mdp_cfg sm8250_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -861,6 +913,16 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24,
INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
};
+static const struct dpu_intf_cfg sc8180x_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24,
INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK,
MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK,
MDP_SSPP_TOP0_INTR, 28, 29),
+ /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until
this is supported */
+ INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 999, 24, INTF_SC7180_MASK,
MDP_SSPP_TOP0_INTR, 30, 31),
+ INTF_BLK("intf_4", INTF_4, 0x6C000, INTF_DP, MSM_DP_CONTROLLER_1, 24,
INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
+
Re: [v1 1/2] drm/msm/dp: Add basic PSR support for eDP
On 12/02/2022 15:51, Vinod Polimera wrote:
Add support for basic panel self refresh (PSR) feature for eDP.
Add a new interface to set PSR state in the sink from DPU.
Program the eDP controller to issue PSR enter and exit SDP to
the sink.
Signed-off-by: Sankeerth Billakanti
Just noticed, thanks to the patchwork. Please do not send patches in
reply to other patchsets/threads. This will confuse both reviwers and
the patchwork.
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 81 +
drivers/gpu/drm/msm/dp/dp_catalog.h | 4 ++
drivers/gpu/drm/msm/dp/dp_ctrl.c| 65 -
drivers/gpu/drm/msm/dp/dp_ctrl.h| 3 ++
drivers/gpu/drm/msm/dp/dp_display.c | 12 ++
drivers/gpu/drm/msm/dp/dp_drm.c | 14 ++-
drivers/gpu/drm/msm/dp/dp_link.c| 22 ++
drivers/gpu/drm/msm/dp/dp_panel.c | 21 ++
drivers/gpu/drm/msm/dp/dp_panel.h | 6 +++
drivers/gpu/drm/msm/dp/dp_reg.h | 19 +
drivers/gpu/drm/msm/msm_drv.h | 2 +
11 files changed, 247 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c
b/drivers/gpu/drm/msm/dp/dp_catalog.c
index 6ae9b29..d20cabb 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
@@ -45,6 +45,14 @@
#define DP_INTERRUPT_STATUS2_MASK \
(DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_MASK_SHIFT)
+#define DP_INTERRUPT_STATUS4 \
+ (PSR_UPDATE_INT | PSR_CAPTURE_INT | PSR_EXIT_INT | \
+ PSR_UPDATE_ERROR_INT | PSR_WAKE_ERROR_INT)
+
+#define DP_INTERRUPT_MASK4 \
+ (PSR_UPDATE_MASK | PSR_CAPTURE_MASK | PSR_EXIT_MASK | \
+ PSR_UPDATE_ERROR_MASK | PSR_WAKE_ERROR_MASK)
+
struct dp_catalog_private {
struct device *dev;
struct dp_io *io;
@@ -343,6 +351,20 @@ void dp_catalog_ctrl_lane_mapping(struct dp_catalog
*dp_catalog)
ln_mapping);
}
+void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog,
+ bool enable)
+{
+ u32 mainlink_ctrl;
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+
+ mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL);
+ mainlink_ctrl &= ~DP_MAINLINK_CTRL_ENABLE;
+ mainlink_ctrl |= (enable & DP_MAINLINK_CTRL_ENABLE);
+
+ dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
+}
+
void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog,
bool enable)
{
@@ -581,6 +603,51 @@ void dp_catalog_ctrl_hpd_config(struct dp_catalog
*dp_catalog)
dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN);
}
+static void dp_catalog_enable_sdp(struct dp_catalog_private *catalog)
+{
+ /* trigger sdp */
+ dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x1);
+ dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x0);
+}
+
+void dp_catalog_ctrl_config_psr(struct dp_catalog *dp_catalog)
+{
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+ u32 psr_config;
+
+ /* enable PSR1 function */
+ psr_config = dp_read_link(catalog, REG_PSR_CONFIG);
+ psr_config |= BIT(0);
+ dp_write_link(catalog, REG_PSR_CONFIG, psr_config);
+
+ dp_write_ahb(catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4);
+ dp_catalog_enable_sdp(catalog);
+}
+
+void dp_catalog_ctrl_set_psr(struct dp_catalog *dp_catalog, bool enter)
+{
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+ u32 psr_cmd;
+
+ psr_cmd = dp_read_link(catalog, REG_PSR_CMD);
+
+ /*
+* BIT(0) - send psr entry SDP
+* BIT(1) - sned psr exit SDP
+*/
+ psr_cmd &= ~(BIT(0) | BIT(1));
+
+ if (enter)
+ psr_cmd |= BIT(0);
+ else
+ psr_cmd |= BIT(1);
+
+ dp_catalog_enable_sdp(catalog);
+ dp_write_link(catalog, REG_PSR_CMD, psr_cmd);
+}
+
u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
@@ -608,6 +675,20 @@ u32 dp_catalog_hpd_get_intr_status(struct dp_catalog
*dp_catalog)
return isr;
}
+int dp_catalog_ctrl_get_psr_interrupt(struct dp_catalog *dp_catalog)
+{
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+ u32 intr, intr_ack;
+
+ intr = dp_read_ahb(catalog, REG_DP_INTR_STATUS4);
+ intr_ack = (intr & DP_INTERRUPT_STATUS4)
+ << DP_INTERRUPT_STATUS_ACK_SHIFT;
+ dp_write_ahb(catalog, REG_DP_INTR_STATUS4, intr_ack);
+
+ return intr;
+}
+
int dp_catalog_ctrl_get_interrupt(struct dp_catalog *d
Re: [Intel-gfx] [PATCH v8 1/3] gpu: drm: separate panel orientation property creating and value setting
On Tuesday, February 15th, 2022 at 13:04, Emil Velikov wrote: > Greetings everyone, > > Padron for joining in so late o/ > > On Tue, 8 Feb 2022 at 08:42, Hsin-Yi Wang wrote: > > > > drm_dev_register() sets connector->registration_state to > > DRM_CONNECTOR_REGISTERED and dev->registered to true. If > > drm_connector_set_panel_orientation() is first called after > > drm_dev_register(), it will fail several checks and results in following > > warning. > > > > Add a function to create panel orientation property and set default value > > to UNKNOWN, so drivers can call this function to init the property earlier > > , and let the panel set the real value later. > > > > The warning illustrates a genuine race condition, where userspace will > read the old/invalid property value/state. So this patch masks away > the WARNING without addressing the actual issue. > Instead can we fix the respective drivers, so that no properties are > created after drm_dev_register()? > > Longer version: > As we look into drm_dev_register() it's in charge of creating the > dev/sysfs nodes (et al). Note that connectors cannot disappear at > runtime. > For panel orientation, we are creating an immutable connector > properly, meaning that as soon as drm_dev_register() is called we must > ensure that the property is available (if applicable) and set to the > correct value. Unfortunately we can't quite do this. To apply the panel orientation quirks we need to grab the EDID of the eDP connector, and this happened too late in my testing. What we can do is create the prop early during module load, and update it when we read the EDID (at the place where we create it right now). User-space will receive a hotplug event after the EDID is read, so will be able to pick up the new value if any.
[PATCH v2 0/8] drm/msm/dpu: cleanup dpu encoder code
This patchset targets DPU encoder code, removing unused artifacts (empty callbacks, MSM bus client id, etc). Changes since v1: - Split dp audio fixup from the intf_type patch - Remove atomic_check() removal, used by the posted WB support Dmitry Baryshkov (8): drm/msm/dpu: fix dp audio condition drm/msm: move struct msm_display_info to dpu driver drm/msm/dpu: remove msm_dp cached in dpu_encoder_virt drm/msm/dpu: drop bus_scaling_client field drm/msm/dpu: encoder: drop unused mode_fixup callback drm/msm/dpu: switch dpu_encoder to use atomic_mode_set drm/msm/dpu: pull connector from dpu_encoder_phys to dpu_encoder_virt drm/msm/dpu: simplify intf allocation code drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 83 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 18 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 14 +--- .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 28 +-- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 28 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 5 +- drivers/gpu/drm/msm/msm_drv.h | 18 7 files changed, 55 insertions(+), 139 deletions(-) -- 2.34.1
[PATCH v2 4/8] drm/msm/dpu: drop bus_scaling_client field
We do not use MSM bus client, so drop bus_scaling_client field from
dpu_encoder_virt.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 401e37f50d54..480d02ccff8c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -127,7 +127,6 @@ enum dpu_enc_rc_states {
* Virtual encoder registers itself with the DRM Framework as the encoder.
* @base: drm_encoder base class for registration with DRM
* @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
- * @bus_scaling_client:Client handle to the bus scaling interface
* @enabled: True if the encoder is active, protected by enc_lock
* @num_phys_encs: Actual number of physical encoders contained.
* @phys_encs: Container of physical encoders managed.
@@ -172,7 +171,6 @@ enum dpu_enc_rc_states {
struct dpu_encoder_virt {
struct drm_encoder base;
spinlock_t enc_spinlock;
- uint32_t bus_scaling_client;
bool enabled;
--
2.34.1
[PATCH v2 5/8] drm/msm/dpu: encoder: drop unused mode_fixup callback
Both cmd and vid backends provide useless mode_fixup() callback. Drop
it.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 4
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 4
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 10 --
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 14 --
4 files changed, 32 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 480d02ccff8c..394916e8fe08 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -602,10 +602,6 @@ static int dpu_encoder_virt_atomic_check(
if (phys->ops.atomic_check)
ret = phys->ops.atomic_check(phys, crtc_state,
conn_state);
- else if (phys->ops.mode_fixup)
- if (!phys->ops.mode_fixup(phys, mode, adj_mode))
- ret = -EINVAL;
-
if (ret) {
DPU_ERROR_ENC(dpu_enc,
"mode unsupported, phys idx %d\n", i);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index e7270eb6b84b..7b14948c4c87 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -84,7 +84,6 @@ struct dpu_encoder_virt_ops {
* @is_master: Whether this phys_enc is the current master
* encoder. Can be switched at enable time. Based
* on split_role and current mode (CMD/VID).
- * @mode_fixup:DRM Call. Fixup a DRM mode.
* @mode_set: DRM Call. Set a DRM mode.
* This likely caches the mode, for use at enable.
* @enable:DRM Call. Enable a DRM mode.
@@ -117,9 +116,6 @@ struct dpu_encoder_phys_ops {
struct dentry *debugfs_root);
void (*prepare_commit)(struct dpu_encoder_phys *encoder);
bool (*is_master)(struct dpu_encoder_phys *encoder);
- bool (*mode_fixup)(struct dpu_encoder_phys *encoder,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode);
void (*mode_set)(struct dpu_encoder_phys *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 35071964d0f6..1796f83b47ae 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -45,15 +45,6 @@ static bool dpu_encoder_phys_cmd_is_master(struct
dpu_encoder_phys *phys_enc)
return (phys_enc->split_role != ENC_ROLE_SLAVE);
}
-static bool dpu_encoder_phys_cmd_mode_fixup(
- struct dpu_encoder_phys *phys_enc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adj_mode)
-{
- DPU_DEBUG_CMDENC(to_dpu_encoder_phys_cmd(phys_enc), "\n");
- return true;
-}
-
static void _dpu_encoder_phys_cmd_update_intf_cfg(
struct dpu_encoder_phys *phys_enc)
{
@@ -756,7 +747,6 @@ static void dpu_encoder_phys_cmd_init_ops(
ops->prepare_commit = dpu_encoder_phys_cmd_prepare_commit;
ops->is_master = dpu_encoder_phys_cmd_is_master;
ops->mode_set = dpu_encoder_phys_cmd_mode_set;
- ops->mode_fixup = dpu_encoder_phys_cmd_mode_fixup;
ops->enable = dpu_encoder_phys_cmd_enable;
ops->disable = dpu_encoder_phys_cmd_disable;
ops->destroy = dpu_encoder_phys_cmd_destroy;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index ddd9d89cd456..1831fe37c88c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -225,19 +225,6 @@ static void programmable_fetch_config(struct
dpu_encoder_phys *phys_enc,
spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
}
-static bool dpu_encoder_phys_vid_mode_fixup(
- struct dpu_encoder_phys *phys_enc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adj_mode)
-{
- DPU_DEBUG_VIDENC(phys_enc, "\n");
-
- /*
-* Modifying mode has consequences when the mode comes back to us
-*/
- return true;
-}
-
static void dpu_encoder_phys_vid_setup_timing_engine(
struct dpu_encoder_phys *phys_enc)
{
@@ -676,7 +663,6 @@ static void dpu_encoder_phys_vid_init_ops(struct
dpu_encoder_phys_ops *ops)
{
ops->is_master = dpu_encoder_phys_vid_is_master;
[PATCH v2 7/8] drm/msm/dpu: pull connector from dpu_encoder_phys to dpu_encoder_virt
All physical encoders used by virtual encoder share the same connector,
so pull the connector field from dpu_encoder_phys into dpu_encoder_virt
structure.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 --
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index ae60d415c66d..fa1dc088a672 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -143,6 +143,7 @@ enum dpu_enc_rc_states {
* link between encoder/crtc. However in this case we need
* to track crtc in the disable() hook which is called
* _after_ encoder_mask is cleared.
+ * @connector: If a mode is set, cached pointer to the active connector
* @crtc_kickoff_cb: Callback into CRTC that will flush & start
* all CTL paths
* @crtc_kickoff_cb_data: Opaque user data given to crtc_kickoff_cb
@@ -183,6 +184,7 @@ struct dpu_encoder_virt {
bool intfs_swapped;
struct drm_crtc *crtc;
+ struct drm_connector *connector;
struct dentry *debugfs_root;
struct mutex enc_lock;
@@ -1010,6 +1012,8 @@ static void dpu_encoder_virt_atomic_mode_set(struct
drm_encoder *drm_enc,
cstate->num_mixers = num_lm;
+ dpu_enc->connector = conn_state->connector;
+
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
int num_blk;
struct dpu_hw_blk *hw_blk[MAX_CHANNELS_PER_ENC];
@@ -1047,7 +1051,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct
drm_encoder *drm_enc,
return;
}
- phys->connector = conn_state->connector;
phys->cached_mode = crtc_state->adjusted_mode;
if (phys->ops.atomic_mode_set)
phys->ops.atomic_mode_set(phys, crtc_state, conn_state);
@@ -1081,7 +1084,7 @@ static void _dpu_encoder_virt_enable_helper(struct
drm_encoder *drm_enc)
if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
!WARN_ON(dpu_enc->num_phys_encs == 0)) {
- unsigned bpc =
dpu_enc->phys_encs[0]->connector->display_info.bpc;
+ unsigned bpc = dpu_enc->connector->display_info.bpc;
for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
if (!dpu_enc->hw_pp[i])
continue;
@@ -1180,9 +1183,7 @@ static void dpu_encoder_virt_disable(struct drm_encoder
*drm_enc)
dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);
- for (i = 0; i < dpu_enc->num_phys_encs; i++) {
- dpu_enc->phys_encs[i]->connector = NULL;
- }
+ dpu_enc->connector = NULL;
DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 6309c5e30d20..43ce56109c41 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -178,7 +178,6 @@ struct dpu_encoder_irq {
* tied to a specific panel / sub-panel. Abstract type, sub-classed by
* phys_vid or phys_cmd for video mode or command mode encs respectively.
* @parent:Pointer to the containing virtual encoder
- * @connector: If a mode is set, cached pointer to the active connector
* @ops: Operations exposed to the virtual encoder
* @parent_ops:Callbacks exposed by the parent to the phys_enc
* @hw_mdptop: Hardware interface to the top registers
@@ -207,7 +206,6 @@ struct dpu_encoder_irq {
*/
struct dpu_encoder_phys {
struct drm_encoder *parent;
- struct drm_connector *connector;
struct dpu_encoder_phys_ops ops;
const struct dpu_encoder_virt_ops *parent_ops;
struct dpu_hw_mdp *hw_mdptop;
--
2.34.1
[PATCH v2 8/8] drm/msm/dpu: simplify intf allocation code
Rather than passing DRM_MODE_ENCODER_* and letting dpu_encoder to guess,
which intf type we mean, pass INTF_DSI/INTF_DP directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 26 +++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 5 ++--
3 files changed, 13 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index fa1dc088a672..597d40f78d38 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -490,7 +490,7 @@ void dpu_encoder_helper_split_config(
hw_mdptop = phys_enc->hw_mdptop;
disp_info = &dpu_enc->disp_info;
- if (disp_info->intf_type != DRM_MODE_ENCODER_DSI)
+ if (disp_info->intf_type != INTF_DSI)
return;
/**
@@ -552,7 +552,7 @@ static struct msm_display_topology dpu_encoder_get_topology(
else
topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
- if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
+ if (dpu_enc->disp_info.intf_type == INTF_DSI) {
if (dpu_kms->catalog->dspp &&
(dpu_kms->catalog->dspp_count >= topology.num_lm))
topology.num_dspp = topology.num_lm;
@@ -1074,7 +1074,7 @@ static void _dpu_encoder_virt_enable_helper(struct
drm_encoder *drm_enc)
}
- if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_TMDS &&
+ if (dpu_enc->disp_info.intf_type == INTF_DP &&
dpu_enc->cur_master->hw_mdptop &&
dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
@@ -1082,7 +1082,7 @@ static void _dpu_encoder_virt_enable_helper(struct
drm_encoder *drm_enc)
_dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
- if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
+ if (dpu_enc->disp_info.intf_type == INTF_DSI &&
!WARN_ON(dpu_enc->num_phys_encs == 0)) {
unsigned bpc = dpu_enc->connector->display_info.bpc;
for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
@@ -1949,7 +1949,6 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
{
int ret = 0;
int i = 0;
- enum dpu_intf_type intf_type = INTF_NONE;
struct dpu_enc_phys_init_params phys_params;
if (!dpu_enc) {
@@ -1965,15 +1964,6 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
phys_params.parent_ops = &dpu_encoder_parent_ops;
phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
- switch (disp_info->intf_type) {
- case DRM_MODE_ENCODER_DSI:
- intf_type = INTF_DSI;
- break;
- case DRM_MODE_ENCODER_TMDS:
- intf_type = INTF_DP;
- break;
- }
-
WARN_ON(disp_info->num_of_h_tiles < 1);
DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
@@ -2005,11 +1995,11 @@ static int dpu_encoder_setup_display(struct
dpu_encoder_virt *dpu_enc,
i, controller_id, phys_params.split_role);
phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog,
-
intf_type,
-
controller_id);
+ disp_info->intf_type,
+ controller_id);
if (phys_params.intf_idx == INTF_MAX) {
DPU_ERROR_ENC(dpu_enc, "could not get intf: type %d, id
%d\n",
- intf_type, controller_id);
+ disp_info->intf_type,
controller_id);
ret = -EINVAL;
}
@@ -2092,7 +2082,7 @@ int dpu_encoder_setup(struct drm_device *dev, struct
drm_encoder *enc,
timer_setup(&dpu_enc->frame_done_timer,
dpu_encoder_frame_done_timeout, 0);
- if (disp_info->intf_type == DRM_MODE_ENCODER_DSI)
+ if (disp_info->intf_type == INTF_DSI)
timer_setup(&dpu_enc->vsync_event_timer,
dpu_encoder_vsync_event_handler,
0);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index ebe3944355bb..3891bcbbe5a4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -36,7 +36,7 @@ void dpu_encoder_get_hw_resources(struct drm_encoder *encoder,
/**
* struct msm_display_info - defines display properties
-
[PATCH v2 6/8] drm/msm/dpu: switch dpu_encoder to use atomic_mode_set
Make dpu_encoder use atomic_mode_set to receive connector and CRTC
states as arguments rather than finding connector and CRTC by manually
looping through the respective lists.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 37 +--
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 ++--
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 18 ++---
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 14 ++-
4 files changed, 21 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 394916e8fe08..ae60d415c66d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -947,16 +947,13 @@ static int dpu_encoder_resource_control(struct
drm_encoder *drm_enc,
return 0;
}
-static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
- struct drm_display_mode *mode,
- struct drm_display_mode *adj_mode)
+static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
+struct drm_crtc_state *crtc_state,
+struct drm_connector_state
*conn_state)
{
struct dpu_encoder_virt *dpu_enc;
struct msm_drm_private *priv;
struct dpu_kms *dpu_kms;
- struct list_head *connector_list;
- struct drm_connector *conn = NULL, *conn_iter;
- struct drm_crtc *drm_crtc;
struct dpu_crtc_state *cstate;
struct dpu_global_state *global_state;
struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
@@ -976,7 +973,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
priv = drm_enc->dev->dev_private;
dpu_kms = to_dpu_kms(priv->kms);
- connector_list = &dpu_kms->dev->mode_config.connector_list;
global_state = dpu_kms_get_existing_global_state(dpu_kms);
if (IS_ERR_OR_NULL(global_state)) {
@@ -986,22 +982,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
trace_dpu_enc_mode_set(DRMID(drm_enc));
- list_for_each_entry(conn_iter, connector_list, head)
- if (conn_iter->encoder == drm_enc)
- conn = conn_iter;
-
- if (!conn) {
- DPU_ERROR_ENC(dpu_enc, "failed to find attached connector\n");
- return;
- } else if (!conn->state) {
- DPU_ERROR_ENC(dpu_enc, "invalid connector state\n");
- return;
- }
-
- drm_for_each_crtc(drm_crtc, drm_enc->dev)
- if (drm_crtc->state->encoder_mask & drm_encoder_mask(drm_enc))
- break;
-
/* Query resource that have been reserved in atomic check step. */
num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp,
@@ -1018,7 +998,7 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
: NULL;
- cstate = to_dpu_crtc_state(drm_crtc->state);
+ cstate = to_dpu_crtc_state(crtc_state);
for (i = 0; i < num_lm; i++) {
int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
@@ -1067,9 +1047,10 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder
*drm_enc,
return;
}
- phys->connector = conn->state->connector;
- if (phys->ops.mode_set)
- phys->ops.mode_set(phys, mode, adj_mode);
+ phys->connector = conn_state->connector;
+ phys->cached_mode = crtc_state->adjusted_mode;
+ if (phys->ops.atomic_mode_set)
+ phys->ops.atomic_mode_set(phys, crtc_state, conn_state);
}
}
@@ -2079,7 +2060,7 @@ static void dpu_encoder_frame_done_timeout(struct
timer_list *t)
}
static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
- .mode_set = dpu_encoder_virt_mode_set,
+ .atomic_mode_set = dpu_encoder_virt_atomic_mode_set,
.disable = dpu_encoder_virt_disable,
.enable = dpu_encoder_virt_enable,
.atomic_check = dpu_encoder_virt_atomic_check,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 7b14948c4c87..6309c5e30d20 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -84,7 +84,7 @@ struct dpu_encoder_virt_ops {
* @is_master: Whether this phys_enc is the current master
* encoder. Can be switched at enable time. Based
* on split_role and current mode (CMD/VID).
- *
[PATCH v2 2/8] drm/msm: move struct msm_display_info to dpu driver
The msm_display_info structure is not used by the rest of msm driver, so
move it into the dpu1 (dpu_encoder.h to be precise).
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 18 ++
drivers/gpu/drm/msm/msm_drv.h | 18 --
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index e241914a9677..ebe3944355bb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -34,6 +34,24 @@ struct dpu_encoder_hw_resources {
void dpu_encoder_get_hw_resources(struct drm_encoder *encoder,
struct dpu_encoder_hw_resources *hw_res);
+/**
+ * struct msm_display_info - defines display properties
+ * @intf_type: DRM_MODE_ENCODER_ type
+ * @capabilities: Bitmask of display flags
+ * @num_of_h_tiles: Number of horizontal tiles in case of split interface
+ * @h_tile_instance:Controller instance used per tile. Number of elements
is
+ * based on num_of_h_tiles
+ * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
+ * used instead of panel TE in cmd mode panels
+ */
+struct msm_display_info {
+ int intf_type;
+ uint32_t capabilities;
+ uint32_t num_of_h_tiles;
+ uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
+ bool is_te_using_watchdog_timer;
+};
+
/**
* dpu_encoder_assign_crtc - Link the encoder to the crtc it's assigned to
* @encoder: encoder pointer
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 3ab19775a5c3..57b0cd6f917e 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -109,24 +109,6 @@ struct msm_display_topology {
u32 num_dspp;
};
-/**
- * struct msm_display_info - defines display properties
- * @intf_type: DRM_MODE_ENCODER_ type
- * @capabilities: Bitmask of display flags
- * @num_of_h_tiles: Number of horizontal tiles in case of split interface
- * @h_tile_instance:Controller instance used per tile. Number of elements
is
- * based on num_of_h_tiles
- * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
- * used instead of panel TE in cmd mode panels
- */
-struct msm_display_info {
- int intf_type;
- uint32_t capabilities;
- uint32_t num_of_h_tiles;
- uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
- bool is_te_using_watchdog_timer;
-};
-
/* Commit/Event thread specific structure */
struct msm_drm_thread {
struct drm_device *dev;
--
2.34.1
[PATCH v2 3/8] drm/msm/dpu: remove msm_dp cached in dpu_encoder_virt
Stop caching msm_dp instance in dpu_encoder_virt since it's not used
now.
Fixes: 8a3b4c17f863 ("drm/msm/dp: employ bridge mechanism for display enable
and disable")
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index c59976deb1cb..401e37f50d54 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -168,7 +168,6 @@ enum dpu_enc_rc_states {
* @vsync_event_work: worker to handle vsync event for autorefresh
* @topology: topology of the display
* @idle_timeout: idle timeout duration in milliseconds
- * @dp:msm_dp pointer, for DP encoders
*/
struct dpu_encoder_virt {
struct drm_encoder base;
@@ -207,8 +206,6 @@ struct dpu_encoder_virt {
struct msm_display_topology topology;
u32 idle_timeout;
-
- struct msm_dp *dp;
};
#define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
@@ -2123,8 +2120,6 @@ int dpu_encoder_setup(struct drm_device *dev, struct
drm_encoder *enc,
timer_setup(&dpu_enc->vsync_event_timer,
dpu_encoder_vsync_event_handler,
0);
- else if (disp_info->intf_type == DRM_MODE_ENCODER_TMDS)
- dpu_enc->dp = priv->dp[disp_info->h_tile_instance[0]];
INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
dpu_encoder_off_work);
--
2.34.1
[PATCH v2 1/8] drm/msm/dpu: fix dp audio condition
DP audio enablement code which is comparing intf_type,
DRM_MODE_ENCODER_TMDS (= 2) with DRM_MODE_CONNECTOR_DisplayPort (= 10).
Which would never succeed. Fix it to check for DRM_MODE_ENCODER_TMDS.
Fixes: d13e36d7d222 ("drm/msm/dp: add audio support for Display Port on MSM")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 132844801e92..c59976deb1cb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1099,7 +1099,7 @@ static void _dpu_encoder_virt_enable_helper(struct
drm_encoder *drm_enc)
}
- if (dpu_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DisplayPort &&
+ if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_TMDS &&
dpu_enc->cur_master->hw_mdptop &&
dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
--
2.34.1
Re: [Intel-gfx] [PATCH v8 1/3] gpu: drm: separate panel orientation property creating and value setting
On Tue, 15 Feb 2022 at 13:55, Simon Ser wrote: > > On Tuesday, February 15th, 2022 at 13:04, Emil Velikov > wrote: > > > Greetings everyone, > > > > Padron for joining in so late o/ > > > > On Tue, 8 Feb 2022 at 08:42, Hsin-Yi Wang wrote: > > > > > > drm_dev_register() sets connector->registration_state to > > > DRM_CONNECTOR_REGISTERED and dev->registered to true. If > > > drm_connector_set_panel_orientation() is first called after > > > drm_dev_register(), it will fail several checks and results in following > > > warning. > > > > > > Add a function to create panel orientation property and set default value > > > to UNKNOWN, so drivers can call this function to init the property earlier > > > , and let the panel set the real value later. > > > > > > > The warning illustrates a genuine race condition, where userspace will > > read the old/invalid property value/state. So this patch masks away > > the WARNING without addressing the actual issue. > > Instead can we fix the respective drivers, so that no properties are > > created after drm_dev_register()? > > > > Longer version: > > As we look into drm_dev_register() it's in charge of creating the > > dev/sysfs nodes (et al). Note that connectors cannot disappear at > > runtime. > > For panel orientation, we are creating an immutable connector > > properly, meaning that as soon as drm_dev_register() is called we must > > ensure that the property is available (if applicable) and set to the > > correct value. > > Unfortunately we can't quite do this. To apply the panel orientation quirks we > need to grab the EDID of the eDP connector, and this happened too late in my > testing. > > What we can do is create the prop early during module load, and update it when > we read the EDID (at the place where we create it right now). User-space will > receive a hotplug event after the EDID is read, so will be able to pick up the > new value if any. Didn't quite get that, are you saying that a GETPROPERTY for the EDID, the ioctl blocks or that we get an empty EDID? The EDID hotplug even thing is neat - sounds like it also signals on panel orientation, correct? On such an event, which properties userspace should be re-fetching - everything or guess randomly? Looking through the documentation, I cannot see a clear answer :-\ Thanks Emil
Re: [PATCH] drm/msm/dpu: Disable boot loader configured data paths
On 15/02/2022 07:37, Bjorn Andersson wrote:
It's typical for the bootloader to configure CTL_0 for the boot splash
or EFIFB, but for non-DSI use cases the DPU driver tend to pick another
CTL and the system might end up with two configured data paths producing
data on the same INTF. In particular as the IOMMU configuration isn't
retained from the bootloader one of the data paths will push underflow
color, resulting in screen flickering.
Naturally the end goal would be to inherit the bootloader's
configuration and provide the user with a glitch-free handover from the
boot configuration to a running DPU.
But such effort will affect clocks, regulators, power-domains etc, and
will take time to implement. So in the meantime this patch simply
disables all the data paths, on platforms that has CTL_FETCH_ACTIVE, to
avoid the graphical artifacts.
Signed-off-by: Bjorn Andersson
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 13 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 6 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 2 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 17 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 8
5 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 02da9ecf71f1..69d4849484fa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -357,6 +357,18 @@ static void dpu_hw_ctl_clear_all_blendstages(struct
dpu_hw_ctl *ctx)
DPU_REG_WRITE(c, CTL_FETCH_PIPE_ACTIVE, 0);
}
+static void dpu_hw_ctl_disable_boot_config(struct dpu_hw_ctl *ctx)
+{
+ if (ctx->caps->features & BIT(DPU_CTL_FETCH_ACTIVE)) {
I see that you are changing only CTL_FETCH_PIPE_ACTIVE. However it still
seems like a hack.
What if instead we always disable boot config for all paths except CTL_0
(or CTL_0 and CTL_1)?
+ /*
+* Disable the pipe fetch and trigger a start, to disable the
+* data path
+*/
+ DPU_REG_WRITE(&ctx->hw, CTL_FETCH_PIPE_ACTIVE, 0);
+ DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1);
What about video vs cmd modes?
+ }
+}
+
static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
enum dpu_lm lm, struct dpu_hw_stage_cfg *stage_cfg)
{
@@ -590,6 +602,7 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
ops->trigger_pending = dpu_hw_ctl_trigger_pending;
ops->reset = dpu_hw_ctl_reset_control;
ops->wait_reset_status = dpu_hw_ctl_wait_reset_status;
+ ops->disable_boot_config = dpu_hw_ctl_disable_boot_config;
ops->clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages;
ops->setup_blendstage = dpu_hw_ctl_setup_blendstage;
ops->get_bitmask_sspp = dpu_hw_ctl_get_bitmask_sspp;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
index 806c171e5df2..c2734f6ab760 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
@@ -159,6 +159,12 @@ struct dpu_hw_ctl_ops {
*/
void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx);
+ /**
+* Disable the configuration setup by the bootloader
+* @ctx : ctl path ctx pointer
+*/
+ void (*disable_boot_config)(struct dpu_hw_ctl *ctx);
+
/**
* Configure layer mixer to pipe configuration
* @ctx : ctl path ctx pointer
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index cedc631f8498..eef2f017031a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1107,6 +1107,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
dpu_kms->rm_init = true;
+ dpu_rm_clear_boot_config(&dpu_kms->rm, dpu_kms->catalog);
+
dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio,
dpu_kms->catalog);
if (IS_ERR(dpu_kms->hw_mdp)) {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index f9c83d6e427a..3365c5e41e28 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -4,6 +4,7 @@
*/
#define pr_fmt(fmt) "[drm:%s] " fmt, __func__
+#include
#include "dpu_kms.h"
#include "dpu_hw_lm.h"
#include "dpu_hw_ctl.h"
@@ -229,6 +230,22 @@ int dpu_rm_init(struct dpu_rm *rm,
return rc ? rc : -EFAULT;
}
+void dpu_rm_clear_boot_config(struct dpu_rm *rm, struct dpu_mdss_cfg *cat)
+{
+ struct dpu_hw_ctl *ctl;
+ int i;
+
+ for (i = CTL_0; i < CTL_MAX; i++) {
+ if (!rm->ctl_blks[i - CTL_0])
+ continue;
+
+ DPU_DEBUG("disabling ctl%d boot configuration\n", i - CTL_0);
+
+ ctl = to_dpu_hw_ctl(rm->ctl_blks[i -
Re: [PATCH v6 01/10] mm: add zone device coherent type memory support
On Tue, Feb 15, 2022 at 01:16:43PM +0100, David Hildenbrand wrote: > > fact, the first version of our patches attempted to add migration > > support to DEVICE_GENERIC. But we were convinced to create a new > > ZONE_DEVICE page type for our use case instead. > > Do you know if DEVICE_GENERIC pages would end up as PageAnon()? My > assumption was that they would be part of a special mapping. We need to stop using the special PTEs and VMAs for things that have a struct page. This is a mistake DAX created that must be undone. Jason
[PATCH] drm/msm/dpu: drop unused access macros
The access macros BLK_foo are not used by the code, drop them.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 16
1 file changed, 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index cac0298aeb52..975ff3a4ae3d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -778,22 +778,6 @@ struct dpu_mdss_cfg {
unsigned long mdss_irqs;
};
-/*
- * Access Macros
- */
-#define BLK_MDP(s) ((s)->mdp)
-#define BLK_CTL(s) ((s)->ctl)
-#define BLK_VIG(s) ((s)->vig)
-#define BLK_RGB(s) ((s)->rgb)
-#define BLK_DMA(s) ((s)->dma)
-#define BLK_CURSOR(s) ((s)->cursor)
-#define BLK_MIXER(s) ((s)->mixer)
-#define BLK_PINGPONG(s) ((s)->pingpong)
-#define BLK_INTF(s) ((s)->intf)
-#define BLK_AD(s) ((s)->ad)
-#define BLK_DSPP(s) ((s)->dspp)
-#define BLK_MERGE3d(s) ((s)->merge_3d)
-
/**
* dpu_hw_catalog_init - dpu hardware catalog init API retrieves
* hardcoded target specific catalog information in config structure
--
2.34.1
Re: [Intel-gfx] [PATCH v5 15/19] drm/i915/dg2: Add DG2 unified compression
On 12.2.2022 3.17, Nanley Chery wrote:
On Tue, Feb 1, 2022 at 2:42 AM Ramalingam C wrote:
From: Matt Roper
DG2 unifies render compression and media compression into a single
format for the first time. The programming and buffer layout is
supposed to match compression on older gen12 platforms, but the actual
compression algorithm is different from any previous platform; as such,
we need a new framebuffer modifier to represent buffers in this format,
but otherwise we can re-use the existing gen12 compression driver logic.
v2:
Display version fix [Imre]
Signed-off-by: Matt Roper
cc: Radhakrishna Sripada
Signed-off-by: Mika Kahola (v2)
cc: Anshuman Gupta
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/display/intel_fb.c | 13 ++
.../drm/i915/display/skl_universal_plane.c| 26 ---
include/uapi/drm/drm_fourcc.h | 22
3 files changed, 57 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 94c57facbb46..4d4d01963f15 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -141,6 +141,14 @@ struct intel_modifier_desc {
static const struct intel_modifier_desc intel_modifiers[] = {
{
+ .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
+ .display_ver = { 13, 13 },
+ .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
+ }, {
+ .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
+ .display_ver = { 13, 13 },
+ .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC,
+ }, {
.modifier = I915_FORMAT_MOD_4_TILED,
.display_ver = { 13, 13 },
.plane_caps = INTEL_PLANE_CAP_TILING_4,
@@ -550,6 +558,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
return 128;
else
return 512;
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
case I915_FORMAT_MOD_4_TILED:
/*
* Each 4K tile consists of 64B(8*8) subtiles, with
@@ -752,6 +762,9 @@ unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
case I915_FORMAT_MOD_4_TILED:
case I915_FORMAT_MOD_Yf_TILED:
return 1 * 1024 * 1024;
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
+ return 16 * 1024;
default:
MISSING_CASE(fb->modifier);
return 0;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 5299dfe68802..c38ae0876c15 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -764,6 +764,14 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_Y;
case I915_FORMAT_MOD_4_TILED:
return PLANE_CTL_TILED_4;
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ return PLANE_CTL_TILED_4 |
+ PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
+ PLANE_CTL_CLEAR_COLOR_DISABLE;
+ case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
+ return PLANE_CTL_TILED_4 |
+ PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
+ PLANE_CTL_CLEAR_COLOR_DISABLE;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y |
PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -2094,6 +2102,10 @@ static bool gen12_plane_has_mc_ccs(struct
drm_i915_private *i915,
if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
return false;
+ /* Wa_14013215631 */
+ if (IS_DG2_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+ return false;
+
return plane_id < PLANE_SPRITE4;
}
@@ -2335,9 +2347,10 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
case PLANE_CTL_TILED_Y:
plane_config->tiling = I915_TILING_Y;
if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
- fb->modifier = DISPLAY_VER(dev_priv) >= 12 ?
- I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
- I915_FORMAT_MOD_Y_TILED_CCS;
+ if (DISPLAY_VER(dev_priv) >= 12)
+ fb->modifier =
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
+ else
+ fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12
Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2: Introduce format modifier for DG2 clear color
On 12.2.2022 3.19, Nanley Chery wrote:
On Tue, Feb 1, 2022 at 2:42 AM Ramalingam C wrote:
From: Mika Kahola
DG2 clear color render compression uses Tile4 layout. Therefore, we need
to define a new format modifier for uAPI to support clear color rendering.
v2:
Display version is fixed. [Imre]
KDoc is enhanced for cc modifier. [Nanley & Lionel]
Signed-off-by: Mika Kahola
cc: Anshuman Gupta
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/display/intel_fb.c| 8
drivers/gpu/drm/i915/display/skl_universal_plane.c | 9 -
include/uapi/drm/drm_fourcc.h | 10 ++
3 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 4d4d01963f15..3df6ef5ffec5 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -144,6 +144,12 @@ static const struct intel_modifier_desc intel_modifiers[]
= {
.modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
.display_ver = { 13, 13 },
.plane_caps = INTEL_PLANE_CAP_TILING_4 |
INTEL_PLANE_CAP_CCS_MC,
+ }, {
+ .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
+ .display_ver = { 13, 13 },
+ .plane_caps = INTEL_PLANE_CAP_TILING_4 |
INTEL_PLANE_CAP_CCS_RC_CC,
+
+ .ccs.cc_planes = BIT(1),
}, {
.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
.display_ver = { 13, 13 },
@@ -559,6 +565,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
else
return 512;
case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
case I915_FORMAT_MOD_4_TILED:
/*
@@ -763,6 +770,7 @@ unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
case I915_FORMAT_MOD_Yf_TILED:
return 1 * 1024 * 1024;
case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
return 16 * 1024;
default:
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index c38ae0876c15..b4dced1907c5 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -772,6 +772,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_4 |
PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
PLANE_CTL_CLEAR_COLOR_DISABLE;
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
+ return PLANE_CTL_TILED_4 |
PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y |
PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -2358,10 +2360,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
break;
case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
if (HAS_4TILE(dev_priv)) {
- if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+ u32 rc_mask = PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
+ PLANE_CTL_CLEAR_COLOR_DISABLE;
+
+ if ((val & rc_mask) == rc_mask)
fb->modifier =
I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
fb->modifier =
I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
+ else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+ fb->modifier =
I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
else
fb->modifier = I915_FORMAT_MOD_4_TILED;
} else {
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index b8fb7b44c03c..697614ea4b84 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -605,6 +605,16 @@ extern "C" {
*/
#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
+/*
+ * Intel color control surfaces (CCS) for DG2 clear color render compression.
+ *
+ * DG2 uses a unified compression format for clear color render compression.
What's unified about DG2's compression format? If this doesn't affect
the layout, maybe we should drop this sentence.
+ * The general layout is a tiled layout using 4Kb tiles i.e. Tile4 layout.
+ *
This also needs a pitch aligned to four tiles, right? I think we can
save some effort by referencing the DG2_RC_CCS mo
RE: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2: Introduce format modifier for DG2 clear color
> -Original Message-
> From: Juha-Pekka Heikkila
> Sent: Tuesday, February 15, 2022 6:56 AM
> To: Nanley Chery ; C, Ramalingam
>
> Cc: intel-gfx ; Chery, Nanley G
> ; Auld, Matthew ; dri-
> devel
> Subject: Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2: Introduce format
> modifier for DG2 clear color
>
> On 12.2.2022 3.19, Nanley Chery wrote:
> > On Tue, Feb 1, 2022 at 2:42 AM Ramalingam C
> wrote:
> >>
> >> From: Mika Kahola
> >>
> >> DG2 clear color render compression uses Tile4 layout. Therefore, we
> >> need to define a new format modifier for uAPI to support clear color
> rendering.
> >>
> >> v2:
> >>Display version is fixed. [Imre]
> >>KDoc is enhanced for cc modifier. [Nanley & Lionel]
> >>
> >> Signed-off-by: Mika Kahola
> >> cc: Anshuman Gupta
> >> Signed-off-by: Juha-Pekka Heikkilä
> >> Signed-off-by: Ramalingam C
> >> ---
> >> drivers/gpu/drm/i915/display/intel_fb.c| 8
> >> drivers/gpu/drm/i915/display/skl_universal_plane.c | 9 -
> >> include/uapi/drm/drm_fourcc.h | 10 ++
> >> 3 files changed, 26 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> >> b/drivers/gpu/drm/i915/display/intel_fb.c
> >> index 4d4d01963f15..3df6ef5ffec5 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> >> @@ -144,6 +144,12 @@ static const struct intel_modifier_desc
> intel_modifiers[] = {
> >> .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
> >> .display_ver = { 13, 13 },
> >> .plane_caps = INTEL_PLANE_CAP_TILING_4 |
> >> INTEL_PLANE_CAP_CCS_MC,
> >> + }, {
> >> + .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
> >> + .display_ver = { 13, 13 },
> >> + .plane_caps = INTEL_PLANE_CAP_TILING_4 |
> >> + INTEL_PLANE_CAP_CCS_RC_CC,
> >> +
> >> + .ccs.cc_planes = BIT(1),
> >> }, {
> >> .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
> >> .display_ver = { 13, 13 }, @@ -559,6 +565,7 @@
> >> intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> >> else
> >> return 512;
> >> case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> >> + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> >> case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> >> case I915_FORMAT_MOD_4_TILED:
> >> /*
> >> @@ -763,6 +770,7 @@ unsigned int intel_surf_alignment(const struct
> drm_framebuffer *fb,
> >> case I915_FORMAT_MOD_Yf_TILED:
> >> return 1 * 1024 * 1024;
> >> case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> >> + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> >> case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> >> return 16 * 1024;
> >> default:
> >> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >> index c38ae0876c15..b4dced1907c5 100644
> >> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> >> @@ -772,6 +772,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> >> return PLANE_CTL_TILED_4 |
> >> PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
> >> PLANE_CTL_CLEAR_COLOR_DISABLE;
> >> + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> >> + return PLANE_CTL_TILED_4 |
> >> + PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> >> case I915_FORMAT_MOD_Y_TILED_CCS:
> >> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> >> return PLANE_CTL_TILED_Y |
> >> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> >> @@ -2358,10 +2360,15 @@ skl_get_initial_plane_config(struct intel_crtc
> *crtc,
> >> break;
> >> case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> >> if (HAS_4TILE(dev_priv)) {
> >> - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> >> + u32 rc_mask =
> >> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> >> + PLANE_CTL_CLEAR_COLOR_DISABLE;
> >> +
> >> + if ((val & rc_mask) == rc_mask)
> >> fb->modifier =
> >> I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
> >> else if (val &
> >> PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
> >> fb->modifier =
> >> I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
> >> + else if (val &
> >> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> >> + fb->modifier =
> >> + I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
> >> else
> >> fb->modifier = I915_FORMAT_MOD_4_TILED;
> >>
Re: [PATCH] drm/msm/dpu: Disable boot loader configured data paths
On Tue 15 Feb 08:44 CST 2022, Dmitry Baryshkov wrote:
> On 15/02/2022 07:37, Bjorn Andersson wrote:
> > It's typical for the bootloader to configure CTL_0 for the boot splash
> > or EFIFB, but for non-DSI use cases the DPU driver tend to pick another
> > CTL and the system might end up with two configured data paths producing
> > data on the same INTF. In particular as the IOMMU configuration isn't
> > retained from the bootloader one of the data paths will push underflow
> > color, resulting in screen flickering.
> >
> > Naturally the end goal would be to inherit the bootloader's
> > configuration and provide the user with a glitch-free handover from the
> > boot configuration to a running DPU.
> >
> > But such effort will affect clocks, regulators, power-domains etc, and
> > will take time to implement. So in the meantime this patch simply
> > disables all the data paths, on platforms that has CTL_FETCH_ACTIVE, to
> > avoid the graphical artifacts.
> >
> > Signed-off-by: Bjorn Andersson
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 13 +
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 6 ++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c| 2 ++
> > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 17 +
> > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 8
> > 5 files changed, 46 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> > index 02da9ecf71f1..69d4849484fa 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> > @@ -357,6 +357,18 @@ static void dpu_hw_ctl_clear_all_blendstages(struct
> > dpu_hw_ctl *ctx)
> > DPU_REG_WRITE(c, CTL_FETCH_PIPE_ACTIVE, 0);
> > }
> > +static void dpu_hw_ctl_disable_boot_config(struct dpu_hw_ctl *ctx)
> > +{
> > + if (ctx->caps->features & BIT(DPU_CTL_FETCH_ACTIVE)) {
>
> I see that you are changing only CTL_FETCH_PIPE_ACTIVE. However it still
> seems like a hack.
You're not wrong, it certainly seems a little bit hacky.
I think that it would be more appropriate to try to inherit the
bootloader configuration. So the proposal here is, in my view, a
stop-gap until we start to look at "continuous splash".
> What if instead we always disable boot config for all paths except CTL_0 (or
> CTL_0 and CTL_1)?
>
On my laptop the bootloader sets up efifb using CTL_0. When Linux brings
up the eDP interface it seems to skip DPU_CTL_SPLIT_DISPLAY ctls and
picks CTL_2.
As mentioned in the message, I now have both CTL_0 and CTL_2 pushing
data to the one interface; resulting in flickering.
> > + /*
> > +* Disable the pipe fetch and trigger a start, to disable the
> > +* data path
> > +*/
> > + DPU_REG_WRITE(&ctx->hw, CTL_FETCH_PIPE_ACTIVE, 0);
> > + DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1);
>
> What about video vs cmd modes?
>
Initially I was resetting a whole bunch of properties in the CTL, but
all I want to do is stop the data flow. It's my expectation that the
steps to follow will reset the interfaces and configure the actual data
paths anew.
Perhaps I'm missing some steps here, the documentation is not clear and
this has the expected visual outcome...
Regards,
Bjorn
> > + }
> > +}
> > +
> > static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
> > enum dpu_lm lm, struct dpu_hw_stage_cfg *stage_cfg)
> > {
> > @@ -590,6 +602,7 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
> > ops->trigger_pending = dpu_hw_ctl_trigger_pending;
> > ops->reset = dpu_hw_ctl_reset_control;
> > ops->wait_reset_status = dpu_hw_ctl_wait_reset_status;
> > + ops->disable_boot_config = dpu_hw_ctl_disable_boot_config;
> > ops->clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages;
> > ops->setup_blendstage = dpu_hw_ctl_setup_blendstage;
> > ops->get_bitmask_sspp = dpu_hw_ctl_get_bitmask_sspp;
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> > index 806c171e5df2..c2734f6ab760 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> > @@ -159,6 +159,12 @@ struct dpu_hw_ctl_ops {
> > */
> > void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx);
> > + /**
> > +* Disable the configuration setup by the bootloader
> > +* @ctx : ctl path ctx pointer
> > +*/
> > + void (*disable_boot_config)(struct dpu_hw_ctl *ctx);
> > +
> > /**
> > * Configure layer mixer to pipe configuration
> > * @ctx : ctl path ctx pointer
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > index cedc631f8498..eef2f017031a 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > @@ -1107,6 +1107,8 @@ static int dpu_kms_hw_init(stru
Re: [PATCH] drm/msm/dpu: drop unused access macros
On Tue 15 Feb 08:53 CST 2022, Dmitry Baryshkov wrote:
> The access macros BLK_foo are not used by the code, drop them.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Bjorn Andersson
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 16
> 1 file changed, 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index cac0298aeb52..975ff3a4ae3d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -778,22 +778,6 @@ struct dpu_mdss_cfg {
> unsigned long mdss_irqs;
> };
>
> -/*
> - * Access Macros
> - */
> -#define BLK_MDP(s) ((s)->mdp)
> -#define BLK_CTL(s) ((s)->ctl)
> -#define BLK_VIG(s) ((s)->vig)
> -#define BLK_RGB(s) ((s)->rgb)
> -#define BLK_DMA(s) ((s)->dma)
> -#define BLK_CURSOR(s) ((s)->cursor)
> -#define BLK_MIXER(s) ((s)->mixer)
> -#define BLK_PINGPONG(s) ((s)->pingpong)
> -#define BLK_INTF(s) ((s)->intf)
> -#define BLK_AD(s) ((s)->ad)
> -#define BLK_DSPP(s) ((s)->dspp)
> -#define BLK_MERGE3d(s) ((s)->merge_3d)
> -
> /**
> * dpu_hw_catalog_init - dpu hardware catalog init API retrieves
> * hardcoded target specific catalog information in config structure
> --
> 2.34.1
>
Re: [PATCH 1/9] dt-bindings: Add arm,mali-valhall compatible
On Fri, 11 Feb 2022 15:27:20 -0500, alyssa.rosenzw...@collabora.com wrote: > From: Alyssa Rosenzweig > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.example.dt.yaml: gpu@ffe4: compatible: ['amlogic,meson-g12a-mali', 'arm,mali-bifrost'] is too short From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1591823 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
[PATCH AUTOSEL 5.16 25/34] drm/rockchip: dw_hdmi: Do not leave clock enabled in error case
From: Sascha Hauer
[ Upstream commit c0cfbb122275da1b726481de5a8cffeb24e6322b ]
The driver returns an error when devm_phy_optional_get() fails leaving
the previously enabled clock turned on. Change order and enable the
clock only after the phy has been acquired.
Signed-off-by: Sascha Hauer
Signed-off-by: Heiko Stuebner
Link:
https://patchwork.freedesktop.org/patch/msgid/20220126145549.617165-3-s.ha...@pengutronix.de
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 830bdd5e9b7ce..8677c82716784 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -529,13 +529,6 @@ static int dw_hdmi_rockchip_bind(struct device *dev,
struct device *master,
return ret;
}
- ret = clk_prepare_enable(hdmi->vpll_clk);
- if (ret) {
- DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
- ret);
- return ret;
- }
-
hdmi->phy = devm_phy_optional_get(dev, "hdmi");
if (IS_ERR(hdmi->phy)) {
ret = PTR_ERR(hdmi->phy);
@@ -544,6 +537,13 @@ static int dw_hdmi_rockchip_bind(struct device *dev,
struct device *master,
return ret;
}
+ ret = clk_prepare_enable(hdmi->vpll_clk);
+ if (ret) {
+ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
+ ret);
+ return ret;
+ }
+
drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
--
2.34.1
[PATCH AUTOSEL 5.16 28/34] display/amd: decrease message verbosity about watermarks table failure
From: Mario Limonciello
[ Upstream commit 03ad3093c7c069d6ab4403730009ebafeea9ee37 ]
A number of BIOS versions have a problem with the watermarks table not
being configured properly. This manifests as a very scary looking warning
during resume from s0i3. This should be harmless in most cases and is well
understood, so decrease the assertion to a clearer warning about the problem.
Reviewed-by: Harry Wentland
Signed-off-by: Mario Limonciello
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
index 162ae71861247..21d2cbc3cbb20 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
@@ -120,7 +120,11 @@ int dcn31_smu_send_msg_with_param(
result = dcn31_smu_wait_for_response(clk_mgr, 10, 20);
if (result == VBIOSSMC_Result_Failed) {
- ASSERT(0);
+ if (msg_id == VBIOSSMC_MSG_TransferTableDram2Smu &&
+ param == TABLE_WATERMARKS)
+ DC_LOG_WARNING("Watermarks table not configured
properly by SMU");
+ else
+ ASSERT(0);
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK);
return -1;
}
--
2.34.1
[PATCH AUTOSEL 5.16 29/34] drm/amdgpu: add utcl2_harvest to gc 10.3.1
From: Aaron Liu
[ Upstream commit a072312f43c33ea02ad88bff3375f650684a6f24 ]
Confirmed with hardware team, there is harvesting for gc 10.3.1.
Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
index b4eddf6e98a6a..ff738e9725ee8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
@@ -543,7 +543,9 @@ static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device
*adev)
adev->gfx.config.max_sh_per_se *
adev->gfx.config.max_shader_engines);
- if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 3):
/* Get SA disabled bitmap from eFuse setting */
efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
@@ -566,6 +568,9 @@ static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device
*adev)
disabled_sa = tmp;
WREG32_SOC15(GC, 0,
mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP, disabled_sa);
+ break;
+ default:
+ break;
}
}
--
2.34.1
[PATCH AUTOSEL 5.16 30/34] drm/amd/display: Cap pflip irqs per max otg number
From: Roman Li
[ Upstream commit 328e34a5ad227399391891d454043e5d73e598d2 ]
[Why]
pflip interrupt order are mapped 1 to 1 to otg id.
e.g. if irq_src=26 corresponds to otg0 then 27->otg1, 28->otg2...
Linux DM registers pflip interrupts per number of crtcs.
In fused pipe case crtc numbers can be less than otg id.
e.g. if one pipe out of 3(otg#0-2) is fused adev->mode_info.num_crtc=2
so DM only registers irq_src 26,27.
This is a bug since if pipe#2 remains unfused DM never gets
otg2 pflip interrupt (irq_src=28)
That may results in gfx failure due to pflip timeout.
[How]
Register pflip interrupts per max num of otg instead of num_crtc
Signed-off-by: Roman Li
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index efcb25ef1809a..0117b00b4ed83 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3629,7 +3629,7 @@ static int dcn10_register_irq_handlers(struct
amdgpu_device *adev)
/* Use GRPH_PFLIP interrupt */
for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
- i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT +
adev->mode_info.num_crtc - 1;
+ i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT +
dc->caps.max_otg_num - 1;
i++) {
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i,
&adev->pageflip_irq);
if (r) {
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f0fbd8ad56229..e890e063cde31 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1237,6 +1237,8 @@ struct dc *dc_create(const struct dc_init_data
*init_params)
dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
+ dc->caps.max_otg_num =
dc->res_pool->res_cap->num_timing_generator;
+
if (dc->res_pool->dmcu != NULL)
dc->versions.dmcu_version =
dc->res_pool->dmcu->dmcu_version;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 618e7989176fc..14864763a1881 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -190,6 +190,7 @@ struct dc_caps {
#endif
bool vbios_lttpr_aware;
bool vbios_lttpr_enable;
+ uint32_t max_otg_num;
};
struct dc_bug_wa {
--
2.34.1
[PATCH AUTOSEL 5.16 31/34] drm/amd/display: fix yellow carp wm clamping
From: Dmytro Laktyushkin
[ Upstream commit 60fdf98a774eee244a4e00c34a9e7729b61d0f44 ]
Fix clamping to match register field size
Reviewed-by: Charlene Liu
Acked-by: Jasdeep Dhillon
Signed-off-by: Dmytro Laktyushkin
Tested-by: Daniel Wheeler
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../drm/amd/display/dc/dcn31/dcn31_hubbub.c | 61 ++-
1 file changed, 32 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
index 90c73a1cb9861..5e3bcaf12cac4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
@@ -138,8 +138,11 @@ static uint32_t convert_and_clamp(
ret_val = wm_ns * refclk_mhz;
ret_val /= 1000;
- if (ret_val > clamp_value)
+ if (ret_val > clamp_value) {
+ /* clamping WMs is abnormal, unexpected and may lead to
underflow*/
+ ASSERT(0);
ret_val = clamp_value;
+ }
return ret_val;
}
@@ -159,7 +162,7 @@ static bool hubbub31_program_urgent_watermarks(
if (safe_to_lower || watermarks->a.urgent_ns >
hubbub2->watermarks.a.urgent_ns) {
hubbub2->watermarks.a.urgent_ns = watermarks->a.urgent_ns;
prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
- refclk_mhz, 0x1f);
+ refclk_mhz, 0x3fff);
REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,
DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A,
prog_wm_value);
@@ -193,7 +196,7 @@ static bool hubbub31_program_urgent_watermarks(
if (safe_to_lower || watermarks->a.urgent_latency_ns >
hubbub2->watermarks.a.urgent_latency_ns) {
hubbub2->watermarks.a.urgent_latency_ns =
watermarks->a.urgent_latency_ns;
prog_wm_value =
convert_and_clamp(watermarks->a.urgent_latency_ns,
- refclk_mhz, 0x1f);
+ refclk_mhz, 0x3fff);
REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0,
DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A,
prog_wm_value);
} else if (watermarks->a.urgent_latency_ns <
hubbub2->watermarks.a.urgent_latency_ns)
@@ -203,7 +206,7 @@ static bool hubbub31_program_urgent_watermarks(
if (safe_to_lower || watermarks->b.urgent_ns >
hubbub2->watermarks.b.urgent_ns) {
hubbub2->watermarks.b.urgent_ns = watermarks->b.urgent_ns;
prog_wm_value = convert_and_clamp(watermarks->b.urgent_ns,
- refclk_mhz, 0x1f);
+ refclk_mhz, 0x3fff);
REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,
DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B,
prog_wm_value);
@@ -237,7 +240,7 @@ static bool hubbub31_program_urgent_watermarks(
if (safe_to_lower || watermarks->b.urgent_latency_ns >
hubbub2->watermarks.b.urgent_latency_ns) {
hubbub2->watermarks.b.urgent_latency_ns =
watermarks->b.urgent_latency_ns;
prog_wm_value =
convert_and_clamp(watermarks->b.urgent_latency_ns,
- refclk_mhz, 0x1f);
+ refclk_mhz, 0x3fff);
REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0,
DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B,
prog_wm_value);
} else if (watermarks->b.urgent_latency_ns <
hubbub2->watermarks.b.urgent_latency_ns)
@@ -247,7 +250,7 @@ static bool hubbub31_program_urgent_watermarks(
if (safe_to_lower || watermarks->c.urgent_ns >
hubbub2->watermarks.c.urgent_ns) {
hubbub2->watermarks.c.urgent_ns = watermarks->c.urgent_ns;
prog_wm_value = convert_and_clamp(watermarks->c.urgent_ns,
- refclk_mhz, 0x1f);
+ refclk_mhz, 0x3fff);
REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0,
DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C,
prog_wm_value);
@@ -281,7 +284,7 @@ static bool hubbub31_program_urgent_watermarks(
if (safe_to_lower || watermarks->c.urgent_latency_ns >
hubbub2->watermarks.c.urgent_latency_ns) {
hubbub2->watermarks.c.urgent_latency_ns =
watermarks->c.urgent_latency_ns;
prog_wm_value =
convert_and_clamp(watermarks->c.urgent_latency_ns,
- refclk_mhz, 0x1f);
+ refclk_mhz, 0x3fff);
REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, 0,
DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C,
prog_wm_value);
} else if (watermarks->c.urgent_latency_ns <
hubbub2->watermarks.c.urgent_latency_ns)
@@ -291,7 +294,7 @@ static bool hubbub31_pro
[PATCH AUTOSEL 5.15 25/33] drm/rockchip: dw_hdmi: Do not leave clock enabled in error case
From: Sascha Hauer
[ Upstream commit c0cfbb122275da1b726481de5a8cffeb24e6322b ]
The driver returns an error when devm_phy_optional_get() fails leaving
the previously enabled clock turned on. Change order and enable the
clock only after the phy has been acquired.
Signed-off-by: Sascha Hauer
Signed-off-by: Heiko Stuebner
Link:
https://patchwork.freedesktop.org/patch/msgid/20220126145549.617165-3-s.ha...@pengutronix.de
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 830bdd5e9b7ce..8677c82716784 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -529,13 +529,6 @@ static int dw_hdmi_rockchip_bind(struct device *dev,
struct device *master,
return ret;
}
- ret = clk_prepare_enable(hdmi->vpll_clk);
- if (ret) {
- DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
- ret);
- return ret;
- }
-
hdmi->phy = devm_phy_optional_get(dev, "hdmi");
if (IS_ERR(hdmi->phy)) {
ret = PTR_ERR(hdmi->phy);
@@ -544,6 +537,13 @@ static int dw_hdmi_rockchip_bind(struct device *dev,
struct device *master,
return ret;
}
+ ret = clk_prepare_enable(hdmi->vpll_clk);
+ if (ret) {
+ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
+ ret);
+ return ret;
+ }
+
drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
--
2.34.1
[PATCH AUTOSEL 5.15 28/33] display/amd: decrease message verbosity about watermarks table failure
From: Mario Limonciello
[ Upstream commit 03ad3093c7c069d6ab4403730009ebafeea9ee37 ]
A number of BIOS versions have a problem with the watermarks table not
being configured properly. This manifests as a very scary looking warning
during resume from s0i3. This should be harmless in most cases and is well
understood, so decrease the assertion to a clearer warning about the problem.
Reviewed-by: Harry Wentland
Signed-off-by: Mario Limonciello
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
index 162ae71861247..21d2cbc3cbb20 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
@@ -120,7 +120,11 @@ int dcn31_smu_send_msg_with_param(
result = dcn31_smu_wait_for_response(clk_mgr, 10, 20);
if (result == VBIOSSMC_Result_Failed) {
- ASSERT(0);
+ if (msg_id == VBIOSSMC_MSG_TransferTableDram2Smu &&
+ param == TABLE_WATERMARKS)
+ DC_LOG_WARNING("Watermarks table not configured
properly by SMU");
+ else
+ ASSERT(0);
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK);
return -1;
}
--
2.34.1
[PATCH AUTOSEL 5.15 29/33] drm/amd/display: Cap pflip irqs per max otg number
From: Roman Li
[ Upstream commit 328e34a5ad227399391891d454043e5d73e598d2 ]
[Why]
pflip interrupt order are mapped 1 to 1 to otg id.
e.g. if irq_src=26 corresponds to otg0 then 27->otg1, 28->otg2...
Linux DM registers pflip interrupts per number of crtcs.
In fused pipe case crtc numbers can be less than otg id.
e.g. if one pipe out of 3(otg#0-2) is fused adev->mode_info.num_crtc=2
so DM only registers irq_src 26,27.
This is a bug since if pipe#2 remains unfused DM never gets
otg2 pflip interrupt (irq_src=28)
That may results in gfx failure due to pflip timeout.
[How]
Register pflip interrupts per max num of otg instead of num_crtc
Signed-off-by: Roman Li
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 16556ae892d4a..5ae9b8133d6da 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3230,7 +3230,7 @@ static int dcn10_register_irq_handlers(struct
amdgpu_device *adev)
/* Use GRPH_PFLIP interrupt */
for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
- i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT +
adev->mode_info.num_crtc - 1;
+ i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT +
dc->caps.max_otg_num - 1;
i++) {
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i,
&adev->pageflip_irq);
if (r) {
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 1860ccc3f4f2c..4fae73478840c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1118,6 +1118,8 @@ struct dc *dc_create(const struct dc_init_data
*init_params)
dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
+ dc->caps.max_otg_num =
dc->res_pool->res_cap->num_timing_generator;
+
if (dc->res_pool->dmcu != NULL)
dc->versions.dmcu_version =
dc->res_pool->dmcu->dmcu_version;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 3ab52d9a82cf6..e0f58fab5e8ed 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -185,6 +185,7 @@ struct dc_caps {
struct dc_color_caps color;
bool vbios_lttpr_aware;
bool vbios_lttpr_enable;
+ uint32_t max_otg_num;
};
struct dc_bug_wa {
--
2.34.1
[PATCH AUTOSEL 5.15 30/33] drm/amd/display: fix yellow carp wm clamping
From: Dmytro Laktyushkin
[ Upstream commit 60fdf98a774eee244a4e00c34a9e7729b61d0f44 ]
Fix clamping to match register field size
Reviewed-by: Charlene Liu
Acked-by: Jasdeep Dhillon
Signed-off-by: Dmytro Laktyushkin
Tested-by: Daniel Wheeler
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../drm/amd/display/dc/dcn31/dcn31_hubbub.c | 61 ++-
1 file changed, 32 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
index 90c73a1cb9861..5e3bcaf12cac4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
@@ -138,8 +138,11 @@ static uint32_t convert_and_clamp(
ret_val = wm_ns * refclk_mhz;
ret_val /= 1000;
- if (ret_val > clamp_value)
+ if (ret_val > clamp_value) {
+ /* clamping WMs is abnormal, unexpected and may lead to
underflow*/
+ ASSERT(0);
ret_val = clamp_value;
+ }
return ret_val;
}
@@ -159,7 +162,7 @@ static bool hubbub31_program_urgent_watermarks(
if (safe_to_lower || watermarks->a.urgent_ns >
hubbub2->watermarks.a.urgent_ns) {
hubbub2->watermarks.a.urgent_ns = watermarks->a.urgent_ns;
prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
- refclk_mhz, 0x1f);
+ refclk_mhz, 0x3fff);
REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,
DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A,
prog_wm_value);
@@ -193,7 +196,7 @@ static bool hubbub31_program_urgent_watermarks(
if (safe_to_lower || watermarks->a.urgent_latency_ns >
hubbub2->watermarks.a.urgent_latency_ns) {
hubbub2->watermarks.a.urgent_latency_ns =
watermarks->a.urgent_latency_ns;
prog_wm_value =
convert_and_clamp(watermarks->a.urgent_latency_ns,
- refclk_mhz, 0x1f);
+ refclk_mhz, 0x3fff);
REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0,
DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A,
prog_wm_value);
} else if (watermarks->a.urgent_latency_ns <
hubbub2->watermarks.a.urgent_latency_ns)
@@ -203,7 +206,7 @@ static bool hubbub31_program_urgent_watermarks(
if (safe_to_lower || watermarks->b.urgent_ns >
hubbub2->watermarks.b.urgent_ns) {
hubbub2->watermarks.b.urgent_ns = watermarks->b.urgent_ns;
prog_wm_value = convert_and_clamp(watermarks->b.urgent_ns,
- refclk_mhz, 0x1f);
+ refclk_mhz, 0x3fff);
REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,
DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B,
prog_wm_value);
@@ -237,7 +240,7 @@ static bool hubbub31_program_urgent_watermarks(
if (safe_to_lower || watermarks->b.urgent_latency_ns >
hubbub2->watermarks.b.urgent_latency_ns) {
hubbub2->watermarks.b.urgent_latency_ns =
watermarks->b.urgent_latency_ns;
prog_wm_value =
convert_and_clamp(watermarks->b.urgent_latency_ns,
- refclk_mhz, 0x1f);
+ refclk_mhz, 0x3fff);
REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0,
DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B,
prog_wm_value);
} else if (watermarks->b.urgent_latency_ns <
hubbub2->watermarks.b.urgent_latency_ns)
@@ -247,7 +250,7 @@ static bool hubbub31_program_urgent_watermarks(
if (safe_to_lower || watermarks->c.urgent_ns >
hubbub2->watermarks.c.urgent_ns) {
hubbub2->watermarks.c.urgent_ns = watermarks->c.urgent_ns;
prog_wm_value = convert_and_clamp(watermarks->c.urgent_ns,
- refclk_mhz, 0x1f);
+ refclk_mhz, 0x3fff);
REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0,
DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C,
prog_wm_value);
@@ -281,7 +284,7 @@ static bool hubbub31_program_urgent_watermarks(
if (safe_to_lower || watermarks->c.urgent_latency_ns >
hubbub2->watermarks.c.urgent_latency_ns) {
hubbub2->watermarks.c.urgent_latency_ns =
watermarks->c.urgent_latency_ns;
prog_wm_value =
convert_and_clamp(watermarks->c.urgent_latency_ns,
- refclk_mhz, 0x1f);
+ refclk_mhz, 0x3fff);
REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, 0,
DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C,
prog_wm_value);
} else if (watermarks->c.urgent_latency_ns <
hubbub2->watermarks.c.urgent_latency_ns)
@@ -291,7 +294,7 @@ static bool hubbub31_pro
[PATCH AUTOSEL 5.10 18/23] drm/rockchip: dw_hdmi: Do not leave clock enabled in error case
From: Sascha Hauer
[ Upstream commit c0cfbb122275da1b726481de5a8cffeb24e6322b ]
The driver returns an error when devm_phy_optional_get() fails leaving
the previously enabled clock turned on. Change order and enable the
clock only after the phy has been acquired.
Signed-off-by: Sascha Hauer
Signed-off-by: Heiko Stuebner
Link:
https://patchwork.freedesktop.org/patch/msgid/20220126145549.617165-3-s.ha...@pengutronix.de
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 23de359a1dec6..515e6f187dc77 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -529,13 +529,6 @@ static int dw_hdmi_rockchip_bind(struct device *dev,
struct device *master,
return ret;
}
- ret = clk_prepare_enable(hdmi->vpll_clk);
- if (ret) {
- DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
- ret);
- return ret;
- }
-
hdmi->phy = devm_phy_optional_get(dev, "hdmi");
if (IS_ERR(hdmi->phy)) {
ret = PTR_ERR(hdmi->phy);
@@ -544,6 +537,13 @@ static int dw_hdmi_rockchip_bind(struct device *dev,
struct device *master,
return ret;
}
+ ret = clk_prepare_enable(hdmi->vpll_clk);
+ if (ret) {
+ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
+ ret);
+ return ret;
+ }
+
drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
--
2.34.1
[PATCH AUTOSEL 5.4 12/17] drm/rockchip: dw_hdmi: Do not leave clock enabled in error case
From: Sascha Hauer
[ Upstream commit c0cfbb122275da1b726481de5a8cffeb24e6322b ]
The driver returns an error when devm_phy_optional_get() fails leaving
the previously enabled clock turned on. Change order and enable the
clock only after the phy has been acquired.
Signed-off-by: Sascha Hauer
Signed-off-by: Heiko Stuebner
Link:
https://patchwork.freedesktop.org/patch/msgid/20220126145549.617165-3-s.ha...@pengutronix.de
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 906891b03a38d..7805091bac32d 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -528,13 +528,6 @@ static int dw_hdmi_rockchip_bind(struct device *dev,
struct device *master,
return ret;
}
- ret = clk_prepare_enable(hdmi->vpll_clk);
- if (ret) {
- DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
- ret);
- return ret;
- }
-
hdmi->phy = devm_phy_optional_get(dev, "hdmi");
if (IS_ERR(hdmi->phy)) {
ret = PTR_ERR(hdmi->phy);
@@ -543,6 +536,13 @@ static int dw_hdmi_rockchip_bind(struct device *dev,
struct device *master,
return ret;
}
+ ret = clk_prepare_enable(hdmi->vpll_clk);
+ if (ret) {
+ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
+ ret);
+ return ret;
+ }
+
drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
DRM_MODE_ENCODER_TMDS, NULL);
--
2.34.1
Re: [PATCH v2 1/8] drm/msm/dpu: fix dp audio condition
On Tue 15 Feb 08:16 CST 2022, Dmitry Baryshkov wrote:
> DP audio enablement code which is comparing intf_type,
> DRM_MODE_ENCODER_TMDS (= 2) with DRM_MODE_CONNECTOR_DisplayPort (= 10).
> Which would never succeed. Fix it to check for DRM_MODE_ENCODER_TMDS.
>
> Fixes: d13e36d7d222 ("drm/msm/dp: add audio support for Display Port on MSM")
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Bjorn Andersson
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 132844801e92..c59976deb1cb 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -1099,7 +1099,7 @@ static void _dpu_encoder_virt_enable_helper(struct
> drm_encoder *drm_enc)
> }
>
>
> - if (dpu_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DisplayPort &&
> + if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_TMDS &&
> dpu_enc->cur_master->hw_mdptop &&
> dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
> dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
> --
> 2.34.1
>
Re: [PATCH v2 3/8] drm/msm/dpu: remove msm_dp cached in dpu_encoder_virt
On Tue 15 Feb 08:16 CST 2022, Dmitry Baryshkov wrote:
> Stop caching msm_dp instance in dpu_encoder_virt since it's not used
> now.
>
> Fixes: 8a3b4c17f863 ("drm/msm/dp: employ bridge mechanism for display enable
> and disable")
> Reviewed-by: Abhinav Kumar
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Bjorn Andersson
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 -
> 1 file changed, 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index c59976deb1cb..401e37f50d54 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -168,7 +168,6 @@ enum dpu_enc_rc_states {
> * @vsync_event_work:worker to handle vsync event for
> autorefresh
> * @topology: topology of the display
> * @idle_timeout:idle timeout duration in milliseconds
> - * @dp: msm_dp pointer, for DP encoders
> */
> struct dpu_encoder_virt {
> struct drm_encoder base;
> @@ -207,8 +206,6 @@ struct dpu_encoder_virt {
> struct msm_display_topology topology;
>
> u32 idle_timeout;
> -
> - struct msm_dp *dp;
> };
>
> #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
> @@ -2123,8 +2120,6 @@ int dpu_encoder_setup(struct drm_device *dev, struct
> drm_encoder *enc,
> timer_setup(&dpu_enc->vsync_event_timer,
> dpu_encoder_vsync_event_handler,
> 0);
> - else if (disp_info->intf_type == DRM_MODE_ENCODER_TMDS)
> - dpu_enc->dp = priv->dp[disp_info->h_tile_instance[0]];
>
> INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
> dpu_encoder_off_work);
> --
> 2.34.1
>
Re: [PATCH v2 4/8] drm/msm/dpu: drop bus_scaling_client field
On Tue 15 Feb 08:16 CST 2022, Dmitry Baryshkov wrote:
> We do not use MSM bus client, so drop bus_scaling_client field from
> dpu_encoder_virt.
>
> Reviewed-by: Abhinav Kumar
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Bjorn Andersson
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 401e37f50d54..480d02ccff8c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -127,7 +127,6 @@ enum dpu_enc_rc_states {
> * Virtual encoder registers itself with the DRM Framework as the encoder.
> * @base:drm_encoder base class for registration with DRM
> * @enc_spinlock:Virtual-Encoder-Wide Spin Lock for IRQ purposes
> - * @bus_scaling_client: Client handle to the bus scaling interface
> * @enabled: True if the encoder is active, protected by enc_lock
> * @num_phys_encs: Actual number of physical encoders contained.
> * @phys_encs: Container of physical encoders managed.
> @@ -172,7 +171,6 @@ enum dpu_enc_rc_states {
> struct dpu_encoder_virt {
> struct drm_encoder base;
> spinlock_t enc_spinlock;
> - uint32_t bus_scaling_client;
>
> bool enabled;
>
> --
> 2.34.1
>
Re: [PATCH v2 5/8] drm/msm/dpu: encoder: drop unused mode_fixup callback
On Tue 15 Feb 08:16 CST 2022, Dmitry Baryshkov wrote:
> Both cmd and vid backends provide useless mode_fixup() callback. Drop
> it.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Bjorn Andersson
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 4
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 4
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 10 --
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 14 --
> 4 files changed, 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 480d02ccff8c..394916e8fe08 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -602,10 +602,6 @@ static int dpu_encoder_virt_atomic_check(
> if (phys->ops.atomic_check)
> ret = phys->ops.atomic_check(phys, crtc_state,
> conn_state);
> - else if (phys->ops.mode_fixup)
> - if (!phys->ops.mode_fixup(phys, mode, adj_mode))
> - ret = -EINVAL;
> -
> if (ret) {
> DPU_ERROR_ENC(dpu_enc,
> "mode unsupported, phys idx %d\n", i);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index e7270eb6b84b..7b14948c4c87 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -84,7 +84,6 @@ struct dpu_encoder_virt_ops {
> * @is_master: Whether this phys_enc is the current
> master
> * encoder. Can be switched at enable time. Based
> * on split_role and current mode (CMD/VID).
> - * @mode_fixup: DRM Call. Fixup a DRM mode.
> * @mode_set:DRM Call. Set a DRM mode.
> * This likely caches the mode, for use at enable.
> * @enable: DRM Call. Enable a DRM mode.
> @@ -117,9 +116,6 @@ struct dpu_encoder_phys_ops {
> struct dentry *debugfs_root);
> void (*prepare_commit)(struct dpu_encoder_phys *encoder);
> bool (*is_master)(struct dpu_encoder_phys *encoder);
> - bool (*mode_fixup)(struct dpu_encoder_phys *encoder,
> - const struct drm_display_mode *mode,
> - struct drm_display_mode *adjusted_mode);
> void (*mode_set)(struct dpu_encoder_phys *encoder,
> struct drm_display_mode *mode,
> struct drm_display_mode *adjusted_mode);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> index 35071964d0f6..1796f83b47ae 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> @@ -45,15 +45,6 @@ static bool dpu_encoder_phys_cmd_is_master(struct
> dpu_encoder_phys *phys_enc)
> return (phys_enc->split_role != ENC_ROLE_SLAVE);
> }
>
> -static bool dpu_encoder_phys_cmd_mode_fixup(
> - struct dpu_encoder_phys *phys_enc,
> - const struct drm_display_mode *mode,
> - struct drm_display_mode *adj_mode)
> -{
> - DPU_DEBUG_CMDENC(to_dpu_encoder_phys_cmd(phys_enc), "\n");
> - return true;
> -}
> -
> static void _dpu_encoder_phys_cmd_update_intf_cfg(
> struct dpu_encoder_phys *phys_enc)
> {
> @@ -756,7 +747,6 @@ static void dpu_encoder_phys_cmd_init_ops(
> ops->prepare_commit = dpu_encoder_phys_cmd_prepare_commit;
> ops->is_master = dpu_encoder_phys_cmd_is_master;
> ops->mode_set = dpu_encoder_phys_cmd_mode_set;
> - ops->mode_fixup = dpu_encoder_phys_cmd_mode_fixup;
> ops->enable = dpu_encoder_phys_cmd_enable;
> ops->disable = dpu_encoder_phys_cmd_disable;
> ops->destroy = dpu_encoder_phys_cmd_destroy;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index ddd9d89cd456..1831fe37c88c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -225,19 +225,6 @@ static void programmable_fetch_config(struct
> dpu_encoder_phys *phys_enc,
> spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
> }
>
> -static bool dpu_encoder_phys_vid_mode_fixup(
> - struct dpu_encoder_phys *phys_enc,
> - const struct drm_display_mode *mode,
> - struct drm_display_mode *adj_mode)
> -{
> - DPU_DEBUG_VIDENC(phys_enc, "\n");
> -
> - /*
> - * Modifying mode has consequences when the mode comes back to us
> - */
> - return true;
> -}
> -
> static void dpu_encoder_phys_vid_setup_timing_e
Re: [PATCH v2 8/8] drm/msm/dpu: simplify intf allocation code
On Tue 15 Feb 08:16 CST 2022, Dmitry Baryshkov wrote:
> Rather than passing DRM_MODE_ENCODER_* and letting dpu_encoder to guess,
> which intf type we mean, pass INTF_DSI/INTF_DP directly.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 26 +++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 4 ++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 5 ++--
> 3 files changed, 13 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index fa1dc088a672..597d40f78d38 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -490,7 +490,7 @@ void dpu_encoder_helper_split_config(
> hw_mdptop = phys_enc->hw_mdptop;
> disp_info = &dpu_enc->disp_info;
>
> - if (disp_info->intf_type != DRM_MODE_ENCODER_DSI)
> + if (disp_info->intf_type != INTF_DSI)
> return;
>
> /**
> @@ -552,7 +552,7 @@ static struct msm_display_topology
> dpu_encoder_get_topology(
> else
> topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
>
> - if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) {
> + if (dpu_enc->disp_info.intf_type == INTF_DSI) {
> if (dpu_kms->catalog->dspp &&
> (dpu_kms->catalog->dspp_count >= topology.num_lm))
> topology.num_dspp = topology.num_lm;
> @@ -1074,7 +1074,7 @@ static void _dpu_encoder_virt_enable_helper(struct
> drm_encoder *drm_enc)
> }
>
>
> - if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_TMDS &&
> + if (dpu_enc->disp_info.intf_type == INTF_DP &&
> dpu_enc->cur_master->hw_mdptop &&
> dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
> dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
> @@ -1082,7 +1082,7 @@ static void _dpu_encoder_virt_enable_helper(struct
> drm_encoder *drm_enc)
>
> _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
>
> - if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&
> + if (dpu_enc->disp_info.intf_type == INTF_DSI &&
> !WARN_ON(dpu_enc->num_phys_encs == 0)) {
> unsigned bpc = dpu_enc->connector->display_info.bpc;
> for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
> @@ -1949,7 +1949,6 @@ static int dpu_encoder_setup_display(struct
> dpu_encoder_virt *dpu_enc,
> {
> int ret = 0;
> int i = 0;
> - enum dpu_intf_type intf_type = INTF_NONE;
> struct dpu_enc_phys_init_params phys_params;
>
> if (!dpu_enc) {
> @@ -1965,15 +1964,6 @@ static int dpu_encoder_setup_display(struct
> dpu_encoder_virt *dpu_enc,
> phys_params.parent_ops = &dpu_encoder_parent_ops;
> phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
>
> - switch (disp_info->intf_type) {
> - case DRM_MODE_ENCODER_DSI:
> - intf_type = INTF_DSI;
> - break;
> - case DRM_MODE_ENCODER_TMDS:
> - intf_type = INTF_DP;
> - break;
> - }
> -
> WARN_ON(disp_info->num_of_h_tiles < 1);
>
> DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
> @@ -2005,11 +1995,11 @@ static int dpu_encoder_setup_display(struct
> dpu_encoder_virt *dpu_enc,
> i, controller_id, phys_params.split_role);
>
> phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog,
> -
> intf_type,
> -
> controller_id);
> + disp_info->intf_type,
> + controller_id);
> if (phys_params.intf_idx == INTF_MAX) {
> DPU_ERROR_ENC(dpu_enc, "could not get intf: type %d, id
> %d\n",
> - intf_type, controller_id);
> + disp_info->intf_type,
> controller_id);
> ret = -EINVAL;
> }
>
> @@ -2092,7 +2082,7 @@ int dpu_encoder_setup(struct drm_device *dev, struct
> drm_encoder *enc,
> timer_setup(&dpu_enc->frame_done_timer,
> dpu_encoder_frame_done_timeout, 0);
>
> - if (disp_info->intf_type == DRM_MODE_ENCODER_DSI)
> + if (disp_info->intf_type == INTF_DSI)
> timer_setup(&dpu_enc->vsync_event_timer,
> dpu_encoder_vsync_event_handler,
> 0);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> index ebe3944355bb..3891bcbbe5a4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> +++ b/drivers/gpu/drm/msm/disp/d
[PATCH] drm: fb-helper: Avoid nesting spinlock_t into raw_spinlock_t
From: Jiri Kosina
drm_fb_helper_damage() is acquiring spinlock_t (helper->damage_lock),
while it can be called from contexts where raw_spinlock_t is held (e.g.
console_owner lock obtained on vprintk_emit() codepath).
As the critical sections protected by damage_lock are super-tiny, let's
fix this by converting it to raw_spinlock_t in order not to violate
PREEMPT_RT-imposed lock nesting rules.
This fixes the splat below.
=
[ BUG: Invalid wait context ]
5.17.0-rc4-2-gd567f5db412e #1 Not tainted
-
swapper/0/0 is trying to lock:
8c5687cc4158 (&helper->damage_lock){}-{3:3}, at:
drm_fb_helper_damage.isra.22+0x4a/0xf0
other info that might help us debug this:
context-{2:2}
3 locks held by swapper/0/0:
#0: ad776520 (console_lock){+.+.}-{0:0}, at: vprintk_emit+0xb8/0x2a0
#1: ad696120 (console_owner){-...}-{0:0}, at:
console_unlock+0x17f/0x550
#2: ad926a58 (printing_lock){}-{3:3}, at:
vt_console_print+0x7d/0x3e0
stack backtrace:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.17.0-rc4-2-gd567f5db412e #1
bed1d5e19e0e7e8c9d97fd8afa1322f7f47a4f38
Hardware name: LENOVO 20UJS2B905/20UJS2B905, BIOS R1CET63W(1.32 ) 04/09/2021
Call Trace:
dump_stack_lvl+0x58/0x71
__lock_acquire+0x165b/0x1780
? secondary_startup_64_no_verify+0xd5/0xdb
lock_acquire+0x278/0x300
? drm_fb_helper_damage.isra.22+0x4a/0xf0
? save_trace+0x3e/0x340
? __bfs+0x10f/0x240
_raw_spin_lock_irqsave+0x48/0x60
? drm_fb_helper_damage.isra.22+0x4a/0xf0
drm_fb_helper_damage.isra.22+0x4a/0xf0
soft_cursor+0x194/0x240
bit_cursor+0x386/0x630
? get_color+0x29/0x120
? bit_putcs+0x4b0/0x4b0
? console_unlock+0x17f/0x550
hide_cursor+0x2f/0x90
vt_console_print+0x3c5/0x3e0
? console_unlock+0x17f/0x550
console_unlock+0x515/0x550
vprintk_emit+0x1c8/0x2a0
_printk+0x52/0x6e
? sched_clock_tick+0x3d/0x60
collect_cpu_info_amd+0x93/0xd0
collect_cpu_info_local+0x23/0x30
flush_smp_call_function_queue+0x137/0x220
__sysvec_call_function_single+0x43/0x1c0
sysvec_call_function_single+0x43/0x80
asm_sysvec_call_function_single+0x12/0x20
RIP: 0010:cpuidle_enter_state+0x111/0x4b0
Code: 7c ff 45 84 ff 74 17 9c 58 0f 1f 44 00 00 f6 c4 02 0f 85 71 03 00 00 31
ff e8 bb 21 86 ff e8 76 2f 8e ff fb 66 0f 1f 44 00 00 <45> 85 f6 0f 88 12 01 00
00 49 63 d6 4c 2b 24 24 48 8d 04 52 48 8d
RSP: 0018:ad603e48 EFLAGS: 0206
RAX: 000127c3 RBX: 0003 RCX:
RDX: RSI: RDI: ac32617a
RBP: 8c5687ba4400 R08: 0001 R09: 0001
R10: ad603e10 R11: R12: 685eb4a0
R13: ad918f80 R14: 0003 R15:
? cpuidle_enter_state+0x10a/0x4b0
? cpuidle_enter_state+0x10a/0x4b0
cpuidle_enter+0x29/0x40
do_idle+0x24d/0x2c0
cpu_startup_entry+0x19/0x20
start_kernel+0x9c2/0x9e9
secondary_startup_64_no_verify+0xd5/0xdb
Signed-off-by: Jiri Kosina
---
drivers/gpu/drm/drm_fb_helper.c | 14 +++---
include/drm/drm_fb_helper.h | 2 +-
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index ed43b987d306..7c4ab6e6f865 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -436,11 +436,11 @@ static void drm_fb_helper_damage_work(struct work_struct
*work)
unsigned long flags;
int ret;
- spin_lock_irqsave(&helper->damage_lock, flags);
+ raw_spin_lock_irqsave(&helper->damage_lock, flags);
clip_copy = *clip;
clip->x1 = clip->y1 = ~0;
clip->x2 = clip->y2 = 0;
- spin_unlock_irqrestore(&helper->damage_lock, flags);
+ raw_spin_unlock_irqrestore(&helper->damage_lock, flags);
/* Call damage handlers only if necessary */
if (!(clip_copy.x1 < clip_copy.x2 && clip_copy.y1 < clip_copy.y2))
@@ -465,12 +465,12 @@ static void drm_fb_helper_damage_work(struct work_struct
*work)
* Restore damage clip rectangle on errors. The next run
* of the damage worker will perform the update.
*/
- spin_lock_irqsave(&helper->damage_lock, flags);
+ raw_spin_lock_irqsave(&helper->damage_lock, flags);
clip->x1 = min_t(u32, clip->x1, clip_copy.x1);
clip->y1 = min_t(u32, clip->y1, clip_copy.y1);
clip->x2 = max_t(u32, clip->x2, clip_copy.x2);
clip->y2 = max_t(u32, clip->y2, clip_copy.y2);
- spin_unlock_irqrestore(&helper->damage_lock, flags);
+ raw_spin_unlock_irqrestore(&helper->damage_lock, flags);
}
/**
@@ -486,7 +486,7 @@ void drm_fb_helper_prepare(struct drm_device *dev, struct
drm_fb_helper *helper,
const struct drm_fb_helper_funcs *funcs)
{
INIT_LIST_HEAD(&helper->kernel_fb_list);
- spin_lock_init(&helper->damage_lock);
+ raw_spin_lock_init(&helper
Re: [PATCH] drm: fb-helper: Avoid nesting spinlock_t into raw_spinlock_t
On 2022-02-15 16:43:08 [+0100], Jiri Kosina wrote:
> From: Jiri Kosina
>
> drm_fb_helper_damage() is acquiring spinlock_t (helper->damage_lock),
> while it can be called from contexts where raw_spinlock_t is held (e.g.
> console_owner lock obtained on vprintk_emit() codepath).
>
> As the critical sections protected by damage_lock are super-tiny, let's
> fix this by converting it to raw_spinlock_t in order not to violate
> PREEMPT_RT-imposed lock nesting rules.
>
> This fixes the splat below.
>
> =
> [ BUG: Invalid wait context ]
> 5.17.0-rc4-2-gd567f5db412e #1 Not tainted
rc4. Is this also the case in the RT tree which includes John's printk
changes?
> -
> swapper/0/0 is trying to lock:
> 8c5687cc4158 (&helper->damage_lock){}-{3:3}, at:
> drm_fb_helper_damage.isra.22+0x4a/0xf0
> other info that might help us debug this:
> context-{2:2}
> 3 locks held by swapper/0/0:
> #0: ad776520 (console_lock){+.+.}-{0:0}, at: vprintk_emit+0xb8/0x2a0
> #1: ad696120 (console_owner){-...}-{0:0}, at:
> console_unlock+0x17f/0x550
> #2: ad926a58 (printing_lock){}-{3:3}, at:
> vt_console_print+0x7d/0x3e0
> stack backtrace:
> CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.17.0-rc4-2-gd567f5db412e #1
> bed1d5e19e0e7e8c9d97fd8afa1322f7f47a4f38
> Hardware name: LENOVO 20UJS2B905/20UJS2B905, BIOS R1CET63W(1.32 ) 04/09/2021
> Call Trace:
>
> dump_stack_lvl+0x58/0x71
> __lock_acquire+0x165b/0x1780
> ? secondary_startup_64_no_verify+0xd5/0xdb
> lock_acquire+0x278/0x300
> ? drm_fb_helper_damage.isra.22+0x4a/0xf0
> ? save_trace+0x3e/0x340
> ? __bfs+0x10f/0x240
> _raw_spin_lock_irqsave+0x48/0x60
> ? drm_fb_helper_damage.isra.22+0x4a/0xf0
> drm_fb_helper_damage.isra.22+0x4a/0xf0
> soft_cursor+0x194/0x240
> bit_cursor+0x386/0x630
> ? get_color+0x29/0x120
> ? bit_putcs+0x4b0/0x4b0
> ? console_unlock+0x17f/0x550
> hide_cursor+0x2f/0x90
> vt_console_print+0x3c5/0x3e0
> ? console_unlock+0x17f/0x550
> console_unlock+0x515/0x550
> vprintk_emit+0x1c8/0x2a0
> _printk+0x52/0x6e
> ? sched_clock_tick+0x3d/0x60
> collect_cpu_info_amd+0x93/0xd0
> collect_cpu_info_local+0x23/0x30
> flush_smp_call_function_queue+0x137/0x220
> __sysvec_call_function_single+0x43/0x1c0
> sysvec_call_function_single+0x43/0x80
>
>
> asm_sysvec_call_function_single+0x12/0x20
> RIP: 0010:cpuidle_enter_state+0x111/0x4b0
> Code: 7c ff 45 84 ff 74 17 9c 58 0f 1f 44 00 00 f6 c4 02 0f 85 71 03 00 00
> 31 ff e8 bb 21 86 ff e8 76 2f 8e ff fb 66 0f 1f 44 00 00 <45> 85 f6 0f 88 12
> 01 00 00 49 63 d6 4c 2b 24 24 48 8d 04 52 48 8d
> RSP: 0018:ad603e48 EFLAGS: 0206
> RAX: 000127c3 RBX: 0003 RCX:
> RDX: RSI: RDI: ac32617a
> RBP: 8c5687ba4400 R08: 0001 R09: 0001
> R10: ad603e10 R11: R12: 685eb4a0
> R13: ad918f80 R14: 0003 R15:
> ? cpuidle_enter_state+0x10a/0x4b0
> ? cpuidle_enter_state+0x10a/0x4b0
> cpuidle_enter+0x29/0x40
> do_idle+0x24d/0x2c0
> cpu_startup_entry+0x19/0x20
> start_kernel+0x9c2/0x9e9
> secondary_startup_64_no_verify+0xd5/0xdb
>
>
> Signed-off-by: Jiri Kosina
> ---
> drivers/gpu/drm/drm_fb_helper.c | 14 +++---
> include/drm/drm_fb_helper.h | 2 +-
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
> index ed43b987d306..7c4ab6e6f865 100644
> --- a/drivers/gpu/drm/drm_fb_helper.c
> +++ b/drivers/gpu/drm/drm_fb_helper.c
> @@ -436,11 +436,11 @@ static void drm_fb_helper_damage_work(struct
> work_struct *work)
> unsigned long flags;
> int ret;
>
> - spin_lock_irqsave(&helper->damage_lock, flags);
> + raw_spin_lock_irqsave(&helper->damage_lock, flags);
> clip_copy = *clip;
> clip->x1 = clip->y1 = ~0;
> clip->x2 = clip->y2 = 0;
> - spin_unlock_irqrestore(&helper->damage_lock, flags);
> + raw_spin_unlock_irqrestore(&helper->damage_lock, flags);
>
> /* Call damage handlers only if necessary */
> if (!(clip_copy.x1 < clip_copy.x2 && clip_copy.y1 < clip_copy.y2))
> @@ -465,12 +465,12 @@ static void drm_fb_helper_damage_work(struct
> work_struct *work)
>* Restore damage clip rectangle on errors. The next run
>* of the damage worker will perform the update.
>*/
> - spin_lock_irqsave(&helper->damage_lock, flags);
> + raw_spin_lock_irqsave(&helper->damage_lock, flags);
> clip->x1 = min_t(u32, clip->x1, clip_copy.x1);
> clip->y1 = min_t(u32, clip->y1, clip_copy.y1);
> clip->x2 = max_t(u32, clip->x2, clip_copy.x2);
> clip->y2 = max_t(u32, clip->y2, clip_copy.y2);
> - spin_unlock_irqrestore(&helper->damage_lock, flags);
> + raw_spin_unlock_irqrestore(&helper->dama
Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2: Introduce format modifier for DG2 clear color
On 15.2.2022 17.02, Chery, Nanley G wrote:
-Original Message-
From: Juha-Pekka Heikkila
Sent: Tuesday, February 15, 2022 6:56 AM
To: Nanley Chery ; C, Ramalingam
Cc: intel-gfx ; Chery, Nanley G
; Auld, Matthew ; dri-
devel
Subject: Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2: Introduce format
modifier for DG2 clear color
On 12.2.2022 3.19, Nanley Chery wrote:
On Tue, Feb 1, 2022 at 2:42 AM Ramalingam C
wrote:
From: Mika Kahola
DG2 clear color render compression uses Tile4 layout. Therefore, we
need to define a new format modifier for uAPI to support clear color
rendering.
v2:
Display version is fixed. [Imre]
KDoc is enhanced for cc modifier. [Nanley & Lionel]
Signed-off-by: Mika Kahola
cc: Anshuman Gupta
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/display/intel_fb.c| 8
drivers/gpu/drm/i915/display/skl_universal_plane.c | 9 -
include/uapi/drm/drm_fourcc.h | 10 ++
3 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 4d4d01963f15..3df6ef5ffec5 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -144,6 +144,12 @@ static const struct intel_modifier_desc
intel_modifiers[] = {
.modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
.display_ver = { 13, 13 },
.plane_caps = INTEL_PLANE_CAP_TILING_4 |
INTEL_PLANE_CAP_CCS_MC,
+ }, {
+ .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
+ .display_ver = { 13, 13 },
+ .plane_caps = INTEL_PLANE_CAP_TILING_4 |
+ INTEL_PLANE_CAP_CCS_RC_CC,
+
+ .ccs.cc_planes = BIT(1),
}, {
.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
.display_ver = { 13, 13 }, @@ -559,6 +565,7 @@
intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
else
return 512;
case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
case I915_FORMAT_MOD_4_TILED:
/*
@@ -763,6 +770,7 @@ unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
case I915_FORMAT_MOD_Yf_TILED:
return 1 * 1024 * 1024;
case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
return 16 * 1024;
default:
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index c38ae0876c15..b4dced1907c5 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -772,6 +772,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_4 |
PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
PLANE_CTL_CLEAR_COLOR_DISABLE;
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
+ return PLANE_CTL_TILED_4 |
+ PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y |
PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -2358,10 +2360,15 @@ skl_get_initial_plane_config(struct intel_crtc
*crtc,
break;
case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
if (HAS_4TILE(dev_priv)) {
- if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+ u32 rc_mask = PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
+ PLANE_CTL_CLEAR_COLOR_DISABLE;
+
+ if ((val & rc_mask) == rc_mask)
fb->modifier =
I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
fb->modifier =
I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
+ else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+ fb->modifier =
+ I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
else
fb->modifier = I915_FORMAT_MOD_4_TILED;
} else {
diff --git a/include/uapi/drm/drm_fourcc.h
b/include/uapi/drm/drm_fourcc.h index b8fb7b44c03c..697614ea4b84
100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -605,6 +605,16 @@ extern "C" {
*/
#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS
fourcc_mod_code(INTEL,
11)
+/*
+ * Intel color control surfaces (CCS) for DG2 clear color render compression.
+ *
+ * DG2 uses
Re: [PATCH] drm: fb-helper: Avoid nesting spinlock_t into raw_spinlock_t
On 2022-02-15, Sebastian Siewior wrote: >> From: Jiri Kosina >> >> drm_fb_helper_damage() is acquiring spinlock_t (helper->damage_lock), >> while it can be called from contexts where raw_spinlock_t is held (e.g. >> console_owner lock obtained on vprintk_emit() codepath). >> >> As the critical sections protected by damage_lock are super-tiny, let's >> fix this by converting it to raw_spinlock_t in order not to violate >> PREEMPT_RT-imposed lock nesting rules. >> >> This fixes the splat below. >> >> = >> [ BUG: Invalid wait context ] >> 5.17.0-rc4-2-gd567f5db412e #1 Not tainted > > rc4. Is this also the case in the RT tree which includes John's printk > changes? In the RT tree, the fbcon's write() callback is only called in preemptible() contexts. So this is only a mainline issue. The series I recently posted to LKML [0] should also address this issue (if/when it gets accepted). John [0] https://lore.kernel.org/lkml/20220207194323.273637-1-john.ogn...@linutronix.de
[PATCH v1 1/1] drm/i915/selftests: Replace too verbose for-loop with simpler while
It's hard to parse for-loop which has some magic calculations inside.
Much cleaner to use while-loop directly.
Signed-off-by: Andy Shevchenko
---
drivers/gpu/drm/i915/selftests/i915_syncmap.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_syncmap.c
b/drivers/gpu/drm/i915/selftests/i915_syncmap.c
index 47f4ae18a1ef..26981d1c3025 100644
--- a/drivers/gpu/drm/i915/selftests/i915_syncmap.c
+++ b/drivers/gpu/drm/i915/selftests/i915_syncmap.c
@@ -36,10 +36,10 @@ __sync_print(struct i915_syncmap *p,
unsigned int i, X;
if (depth) {
- unsigned int d;
+ unsigned int d = depth;
- for (d = 0; d < depth - 1; d++) {
- if (last & BIT(depth - d - 1))
+ while (d--) {
+ if (last & BIT(d))
len = scnprintf(buf, *sz, "| ");
else
len = scnprintf(buf, *sz, "");
--
2.34.1
Re: [Intel-gfx] [PATCH v8 1/3] gpu: drm: separate panel orientation property creating and value setting
On Tuesday, February 15th, 2022 at 15:38, Emil Velikov wrote: > On Tue, 15 Feb 2022 at 13:55, Simon Ser wrote: > > > > On Tuesday, February 15th, 2022 at 13:04, Emil Velikov > > wrote: > > > > > Greetings everyone, > > > > > > Padron for joining in so late o/ > > > > > > On Tue, 8 Feb 2022 at 08:42, Hsin-Yi Wang wrote: > > > > > > > > drm_dev_register() sets connector->registration_state to > > > > DRM_CONNECTOR_REGISTERED and dev->registered to true. If > > > > drm_connector_set_panel_orientation() is first called after > > > > drm_dev_register(), it will fail several checks and results in following > > > > warning. > > > > > > > > Add a function to create panel orientation property and set default > > > > value > > > > to UNKNOWN, so drivers can call this function to init the property > > > > earlier > > > > , and let the panel set the real value later. > > > > > > > > > > The warning illustrates a genuine race condition, where userspace will > > > read the old/invalid property value/state. So this patch masks away > > > the WARNING without addressing the actual issue. > > > Instead can we fix the respective drivers, so that no properties are > > > created after drm_dev_register()? > > > > > > Longer version: > > > As we look into drm_dev_register() it's in charge of creating the > > > dev/sysfs nodes (et al). Note that connectors cannot disappear at > > > runtime. > > > For panel orientation, we are creating an immutable connector > > > properly, meaning that as soon as drm_dev_register() is called we must > > > ensure that the property is available (if applicable) and set to the > > > correct value. > > > > Unfortunately we can't quite do this. To apply the panel orientation quirks > > we > > need to grab the EDID of the eDP connector, and this happened too late in my > > testing. > > > > What we can do is create the prop early during module load, and update it > > when > > we read the EDID (at the place where we create it right now). User-space > > will > > receive a hotplug event after the EDID is read, so will be able to pick up > > the > > new value if any. > > Didn't quite get that, are you saying that a GETPROPERTY for the EDID, > the ioctl blocks or that we get an empty EDID? I'm not referring to GETPROPERTY, I'm referring to the driver getting the EDID from the sink (here, the eDP panel). In my experimentations with amdgpu I noticed that the driver module load finished before the EDID was available to the driver. Maybe other drivers behave differently and probe connectors when loaded, not sure. > The EDID hotplug even thing is neat - sounds like it also signals on > panel orientation, correct? > On such an event, which properties userspace should be re-fetching - > everything or guess randomly? > > Looking through the documentation, I cannot see a clear answer :-\ User-space should re-fetch *all* properties. In practice some user-space may only be fetching some properties, but that should get fixed in user-space. Also the kernel can indicate that only a single connector changed via the "CONNECTOR" uevent prop, or even a single connector property via "PROPERTY". See [1] for a user-space implementation. But all of this is purely an optional optimization. Re-fetching all properties is a bit slower (especially if some drmModeGetConnector calls force-probe connectors) but works perfectly fine. It would be nice to document, if you have the time feel free to send a patch and CC danvet, pq and me. [1]: https://gitlab.freedesktop.org/wlroots/wlroots/-/blob/252b2348bd62170d97c4e81fb2050f757b56d67e/backend/session/session.c#L144
Re: [Intel-gfx] [PATCH] drm/i915/guc: Initialize GuC submission locks and queues early
On 2/15/2022 1:09 AM, Tvrtko Ursulin wrote:
On 15/02/2022 01:11, Daniele Ceraolo Spurio wrote:
Move initialization of submission-related spinlock, lists and workers to
init_early. This fixes an issue where if the GuC init fails we might
still try to get the lock in the context cleanup code. Note that it is
What's the worst case impact on non-debug builds aka is Fixes: required?
There is no lock contention in this scenario and nothing is done within
the locked section (because submission is not initialized and all
contexts are marked as invalid), so no problems from the fact that the
lock doesn't work. Is that enough to avoid a fixes tag?
Daniele
Regards,
Tvrtko
safe to call the GuC context cleanup code even if the init failed
because all contexts are initialized with an invalid GuC ID, which will
cause the GuC side of the cleanup to be skipped, so it is easier to just
make sure the variables are initialized than to special case the cleanup
to handle the case when they're not.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/4932
Signed-off-by: Daniele Ceraolo Spurio
Cc: Matthew Brost
Cc: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b3a429a92c0da..2160da2c83cbf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1818,24 +1818,11 @@ int intel_guc_submission_init(struct
intel_guc *guc)
*/
GEM_BUG_ON(!guc->lrc_desc_pool);
- xa_init_flags(&guc->context_lookup, XA_FLAGS_LOCK_IRQ);
-
- spin_lock_init(&guc->submission_state.lock);
- INIT_LIST_HEAD(&guc->submission_state.guc_id_list);
- ida_init(&guc->submission_state.guc_ids);
- INIT_LIST_HEAD(&guc->submission_state.destroyed_contexts);
- INIT_WORK(&guc->submission_state.destroyed_worker,
- destroyed_worker_func);
- INIT_WORK(&guc->submission_state.reset_fail_worker,
- reset_fail_worker_func);
-
guc->submission_state.guc_ids_bitmap =
bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
if (!guc->submission_state.guc_ids_bitmap)
return -ENOMEM;
- spin_lock_init(&guc->timestamp.lock);
- INIT_DELAYED_WORK(&guc->timestamp.work, guc_timestamp_ping);
guc->timestamp.ping_delay = (POLL_TIME_CLKS /
gt->clock_frequency + 1) * HZ;
guc->timestamp.shift = gpm_timestamp_shift(gt);
@@ -3831,6 +3818,20 @@ static bool __guc_submission_selected(struct
intel_guc *guc)
void intel_guc_submission_init_early(struct intel_guc *guc)
{
+ xa_init_flags(&guc->context_lookup, XA_FLAGS_LOCK_IRQ);
+
+ spin_lock_init(&guc->submission_state.lock);
+ INIT_LIST_HEAD(&guc->submission_state.guc_id_list);
+ ida_init(&guc->submission_state.guc_ids);
+ INIT_LIST_HEAD(&guc->submission_state.destroyed_contexts);
+ INIT_WORK(&guc->submission_state.destroyed_worker,
+ destroyed_worker_func);
+ INIT_WORK(&guc->submission_state.reset_fail_worker,
+ reset_fail_worker_func);
+
+ spin_lock_init(&guc->timestamp.lock);
+ INIT_DELAYED_WORK(&guc->timestamp.work, guc_timestamp_ping);
+
guc->submission_state.num_guc_ids = GUC_MAX_LRC_DESCRIPTORS;
guc->submission_supported = __guc_submission_supported(guc);
guc->submission_selected = __guc_submission_selected(guc);
RE: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2: Introduce format modifier for DG2 clear color
> -Original Message-
> From: Juha-Pekka Heikkila
> Sent: Tuesday, February 15, 2022 8:15 AM
> To: Chery, Nanley G ; Nanley Chery
> ; C, Ramalingam
> Cc: intel-gfx ; Auld, Matthew
> ; dri-devel
> Subject: Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2: Introduce format
> modifier for DG2 clear color
>
> On 15.2.2022 17.02, Chery, Nanley G wrote:
> >
> >
> >> -Original Message-
> >> From: Juha-Pekka Heikkila
> >> Sent: Tuesday, February 15, 2022 6:56 AM
> >> To: Nanley Chery ; C, Ramalingam
> >>
> >> Cc: intel-gfx ; Chery, Nanley G
> >> ; Auld, Matthew ;
> >> dri- devel
> >> Subject: Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2: Introduce
> >> format modifier for DG2 clear color
> >>
> >> On 12.2.2022 3.19, Nanley Chery wrote:
> >>> On Tue, Feb 1, 2022 at 2:42 AM Ramalingam C
> >> wrote:
>
> From: Mika Kahola
>
> DG2 clear color render compression uses Tile4 layout. Therefore, we
> need to define a new format modifier for uAPI to support clear
> color
> >> rendering.
>
> v2:
> Display version is fixed. [Imre]
> KDoc is enhanced for cc modifier. [Nanley & Lionel]
>
> Signed-off-by: Mika Kahola
> cc: Anshuman Gupta
> Signed-off-by: Juha-Pekka Heikkilä
> Signed-off-by: Ramalingam C
> ---
> drivers/gpu/drm/i915/display/intel_fb.c| 8
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 9 -
> include/uapi/drm/drm_fourcc.h | 10 ++
> 3 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> b/drivers/gpu/drm/i915/display/intel_fb.c
> index 4d4d01963f15..3df6ef5ffec5 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -144,6 +144,12 @@ static const struct intel_modifier_desc
> >> intel_modifiers[] = {
> .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
> .display_ver = { 13, 13 },
> .plane_caps = INTEL_PLANE_CAP_TILING_4 |
> INTEL_PLANE_CAP_CCS_MC,
> + }, {
> + .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
> + .display_ver = { 13, 13 },
> + .plane_caps = INTEL_PLANE_CAP_TILING_4 |
> + INTEL_PLANE_CAP_CCS_RC_CC,
> +
> + .ccs.cc_planes = BIT(1),
> }, {
> .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
> .display_ver = { 13, 13 }, @@ -559,6 +565,7 @@
> intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> else
> return 512;
> case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> case I915_FORMAT_MOD_4_TILED:
> /*
> @@ -763,6 +770,7 @@ unsigned int intel_surf_alignment(const struct
> >> drm_framebuffer *fb,
> case I915_FORMAT_MOD_Yf_TILED:
> return 1 * 1024 * 1024;
> case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> return 16 * 1024;
> default:
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index c38ae0876c15..b4dced1907c5 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -772,6 +772,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> return PLANE_CTL_TILED_4 |
> PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
> PLANE_CTL_CLEAR_COLOR_DISABLE;
> + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> + return PLANE_CTL_TILED_4 |
> + PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return PLANE_CTL_TILED_Y |
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> @@ -2358,10 +2360,15 @@ skl_get_initial_plane_config(struct
> intel_crtc
> >> *crtc,
> break;
> case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> if (HAS_4TILE(dev_priv)) {
> - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> + u32 rc_mask =
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> +
> + PLANE_CTL_CLEAR_COLOR_DISABLE;
> +
> + if ((val & rc_mask) == rc_mask)
>
Re: [PATCH v3] drm/msm/dpu: Only create debugfs for PRIMARY minor
On 2/11/2022 4:38 PM, Dmitry Baryshkov wrote: From: Bjorn Andersson dpu_kms_debugfs_init() is invoked for each minor being registered. Most of the files created are unrelated to the minor, so there's no reason to present them per minor. The exception to this is the DisplayPort code, which ends up invoking dp_debug_get() for each minor, each time associate the allocated object with dp->debug. As such dp_debug will create debugfs files in both the PRIMARY and the RENDER minor's debugfs directory, but only the last reference will be remembered. The only use of this reference today is in the cleanup path in dp_display_deinit_sub_modules() and the dp_debug_private object does outlive the debugfs entries in either case, so there doesn't seem to be any adverse effects of this, but per the code the current behavior is unexpected, so change it to only create debugfs files for the PRIMARY minor. Signed-off-by: Bjorn Andersson [DB: slightly change description and in-patch comment] Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- This is a replacement for https://patchwork.freedesktop.org/patch/467273/ with the patch subject and comment being fixed. --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 5f0dc44119c9..c394bd6b2e5d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -271,6 +271,10 @@ static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) if (!p) return -EINVAL; + /* Only create a set of debugfs for the primary node, ignore render nodes */ + if (minor->type != DRM_MINOR_PRIMARY) + return 0; + dev = dpu_kms->dev; priv = dev->dev_private;
Re: [PATCH v2 5/8] drm/msm/dpu: encoder: drop unused mode_fixup callback
On 2/15/2022 6:16 AM, Dmitry Baryshkov wrote:
Both cmd and vid backends provide useless mode_fixup() callback. Drop
it.
Thanks for not removing the atomic_check().
BTW, can you please include that in the change log so that others
reviewing it know.
That being said,
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 4
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 4
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 10 --
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 14 --
4 files changed, 32 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 480d02ccff8c..394916e8fe08 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -602,10 +602,6 @@ static int dpu_encoder_virt_atomic_check(
if (phys->ops.atomic_check)
ret = phys->ops.atomic_check(phys, crtc_state,
conn_state);
- else if (phys->ops.mode_fixup)
- if (!phys->ops.mode_fixup(phys, mode, adj_mode))
- ret = -EINVAL;
-
if (ret) {
DPU_ERROR_ENC(dpu_enc,
"mode unsupported, phys idx %d\n", i);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index e7270eb6b84b..7b14948c4c87 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -84,7 +84,6 @@ struct dpu_encoder_virt_ops {
* @is_master:Whether this phys_enc is the current
master
*encoder. Can be switched at enable time. Based
*on split_role and current mode (CMD/VID).
- * @mode_fixup:DRM Call. Fixup a DRM mode.
* @mode_set: DRM Call. Set a DRM mode.
*This likely caches the mode, for use at enable.
* @enable: DRM Call. Enable a DRM mode.
@@ -117,9 +116,6 @@ struct dpu_encoder_phys_ops {
struct dentry *debugfs_root);
void (*prepare_commit)(struct dpu_encoder_phys *encoder);
bool (*is_master)(struct dpu_encoder_phys *encoder);
- bool (*mode_fixup)(struct dpu_encoder_phys *encoder,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode);
void (*mode_set)(struct dpu_encoder_phys *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 35071964d0f6..1796f83b47ae 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -45,15 +45,6 @@ static bool dpu_encoder_phys_cmd_is_master(struct
dpu_encoder_phys *phys_enc)
return (phys_enc->split_role != ENC_ROLE_SLAVE);
}
-static bool dpu_encoder_phys_cmd_mode_fixup(
- struct dpu_encoder_phys *phys_enc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adj_mode)
-{
- DPU_DEBUG_CMDENC(to_dpu_encoder_phys_cmd(phys_enc), "\n");
- return true;
-}
-
static void _dpu_encoder_phys_cmd_update_intf_cfg(
struct dpu_encoder_phys *phys_enc)
{
@@ -756,7 +747,6 @@ static void dpu_encoder_phys_cmd_init_ops(
ops->prepare_commit = dpu_encoder_phys_cmd_prepare_commit;
ops->is_master = dpu_encoder_phys_cmd_is_master;
ops->mode_set = dpu_encoder_phys_cmd_mode_set;
- ops->mode_fixup = dpu_encoder_phys_cmd_mode_fixup;
ops->enable = dpu_encoder_phys_cmd_enable;
ops->disable = dpu_encoder_phys_cmd_disable;
ops->destroy = dpu_encoder_phys_cmd_destroy;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index ddd9d89cd456..1831fe37c88c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -225,19 +225,6 @@ static void programmable_fetch_config(struct
dpu_encoder_phys *phys_enc,
spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
}
-static bool dpu_encoder_phys_vid_mode_fixup(
- struct dpu_encoder_phys *phys_enc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adj_mode)
-{
- DPU_DEBUG_VIDENC(phys_enc, "\n");
-
- /*
-* Modifying mode has consequences when the mode comes back to us
-*/
- return true;
-}
-
static v
[PATCH 7/8] drm/fourcc: Add DRM_FORMAT_R[124]
Introduce fourcc codes for single-channel frame buffer formats with two,
four, and sixteen intensity levels. Traditionally, the first channel
has been called the "red" channel, but the fourcc can also be used for
other light-on-dark displays.
As the number of bits per pixel is less than eight, these rely on proper
block handling for the calculation of bits per pixel and pitch.
Signed-off-by: Geert Uytterhoeven
---
drivers/gpu/drm/drm_fourcc.c | 6 ++
include/uapi/drm/drm_fourcc.h | 9 +
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 5c77ce10f53e3a64..c12e48ecb1ab8aad 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -151,6 +151,12 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_C4, .depth = 4,
.num_planes = 1,
.char_per_block = { 1, }, .block_w = { 2, }, .block_h = { 1,
}, .hsub = 1, .vsub = 1 },
{ .format = DRM_FORMAT_C8, .depth = 8,
.num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_R1, .depth = 1,
.num_planes = 1,
+ .char_per_block = { 1, }, .block_w = { 8, }, .block_h = { 1,
}, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_R2, .depth = 2,
.num_planes = 1,
+ .char_per_block = { 1, }, .block_w = { 4, }, .block_h = { 1,
}, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_R4, .depth = 4,
.num_planes = 1,
+ .char_per_block = { 1, }, .block_w = { 2, }, .block_h = { 1,
}, .hsub = 1, .vsub = 1 },
{ .format = DRM_FORMAT_R8, .depth = 8,
.num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1 },
{ .format = DRM_FORMAT_R10, .depth = 10,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
{ .format = DRM_FORMAT_R12, .depth = 12,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 3f09174670b3cce6..8605a1acc6813e6c 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -104,6 +104,15 @@ extern "C" {
#define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [3:0] C */
#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
+/* 1 bpp Red */
+#define DRM_FORMAT_R1 fourcc_code('R', '1', ' ', ' ') /* [0] R */
+
+/* 2 bpp Red */
+#define DRM_FORMAT_R2 fourcc_code('R', '2', ' ', ' ') /* [1:0] R */
+
+/* 4 bpp Red */
+#define DRM_FORMAT_R4 fourcc_code('R', '4', ' ', ' ') /* [3:0] R */
+
/* 8 bpp Red */
#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
--
2.25.1
[PATCH 1/8] drm/fourcc: Add DRM_FORMAT_C[124]
Introduce fourcc codes for color-indexed frame buffer formats with two,
four, and sixteen color, and provide a suitable mapping from bit per
pixel and depth to fourcc codes.
As the number of bits per pixel is less than eight, these rely on proper
block handling for the calculation of bits per pixel and pitch.
Signed-off-by: Geert Uytterhoeven
---
Do we want to keep the rounding down if depth < bpp, or insist on depth
== bpp? I don't think the rounding down will still be needed after
"[PATCH 4/8] drm/client: Use actual bpp when allocating frame buffers".
---
drivers/gpu/drm/drm_fourcc.c | 18 ++
include/uapi/drm/drm_fourcc.h | 3 +++
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 07741b678798b0f1..60ce63d728b8e308 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -46,6 +46,18 @@ uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t
depth)
case 8:
if (depth == 8)
fmt = DRM_FORMAT_C8;
+ fallthrough;
+ case 4:
+ if (depth == 4)
+ fmt = DRM_FORMAT_C4;
+ fallthrough;
+ case 2:
+ if (depth == 2)
+ fmt = DRM_FORMAT_C2;
+ fallthrough;
+ case 1:
+ if (depth == 1)
+ fmt = DRM_FORMAT_C1;
break;
case 16:
@@ -132,6 +144,12 @@ EXPORT_SYMBOL(drm_driver_legacy_fb_format);
const struct drm_format_info *__drm_format_info(u32 format)
{
static const struct drm_format_info formats[] = {
+ { .format = DRM_FORMAT_C1, .depth = 1,
.num_planes = 1,
+ .char_per_block = { 1, }, .block_w = { 8, }, .block_h = { 1,
}, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_C2, .depth = 2,
.num_planes = 1,
+ .char_per_block = { 1, }, .block_w = { 4, }, .block_h = { 1,
}, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_C4, .depth = 4,
.num_planes = 1,
+ .char_per_block = { 1, }, .block_w = { 2, }, .block_h = { 1,
}, .hsub = 1, .vsub = 1 },
{ .format = DRM_FORMAT_C8, .depth = 8,
.num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1 },
{ .format = DRM_FORMAT_R8, .depth = 8,
.num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1 },
{ .format = DRM_FORMAT_R10, .depth = 10,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index fc0c1454d2757d5d..3f09174670b3cce6 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -99,6 +99,9 @@ extern "C" {
#define DRM_FORMAT_INVALID 0
/* color index */
+#define DRM_FORMAT_C1 fourcc_code('C', '1', ' ', ' ') /* [0] C */
+#define DRM_FORMAT_C2 fourcc_code('C', '2', ' ', ' ') /* [1:0] C */
+#define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [3:0] C */
#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
/* 8 bpp Red */
--
2.25.1
[PATCH 8/8] drm/fourcc: Add DRM_FORMAT_D1
Introduce a fourcc code for a single-channel frame buffer format with two
darkness levels. This can be used for two-level dark-on-light displays.
As the number of bits per pixel is less than eight, this relies on
proper block handling for the calculation of bits per pixel and pitch.
Signed-off-by: Geert Uytterhoeven
---
drivers/gpu/drm/drm_fourcc.c | 2 ++
include/uapi/drm/drm_fourcc.h | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index c12e48ecb1ab8aad..d00ce5d8d1fb9dd3 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -151,6 +151,8 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_C4, .depth = 4,
.num_planes = 1,
.char_per_block = { 1, }, .block_w = { 2, }, .block_h = { 1,
}, .hsub = 1, .vsub = 1 },
{ .format = DRM_FORMAT_C8, .depth = 8,
.num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_D1, .depth = 1,
.num_planes = 1,
+ .char_per_block = { 1, }, .block_w = { 8, }, .block_h = { 1,
}, .hsub = 1, .vsub = 1 },
{ .format = DRM_FORMAT_R1, .depth = 1,
.num_planes = 1,
.char_per_block = { 1, }, .block_w = { 8, }, .block_h = { 1,
}, .hsub = 1, .vsub = 1 },
{ .format = DRM_FORMAT_R2, .depth = 2,
.num_planes = 1,
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 8605a1acc6813e6c..c15c6efcc65e5827 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -104,6 +104,9 @@ extern "C" {
#define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [3:0] C */
#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
+/* 1 bpp Darkness */
+#define DRM_FORMAT_D1 fourcc_code('D', '1', ' ', ' ') /* [0] D */
+
/* 1 bpp Red */
#define DRM_FORMAT_R1 fourcc_code('R', '1', ' ', ' ') /* [0] R */
--
2.25.1
[PATCH 6/8] drm/gem-fb-helper: Use actual bpp for size calculations
The AFBC helpers derive the number of bits per pixel from the deprecated
drm_format_info.cpp[] field, which does not take into account block
sizes.
Fix this by using the actual number of bits per pixel instead.
Signed-off-by: Geert Uytterhoeven
---
Untested.
After adding the missing block info, probably the whole function can
just be dropped, in favor of drm_format_info_bpp()?
---
drivers/gpu/drm/drm_gem_framebuffer_helper.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/drm_gem_framebuffer_helper.c
b/drivers/gpu/drm/drm_gem_framebuffer_helper.c
index 746fd8c738451247..7eca09fce095abbe 100644
--- a/drivers/gpu/drm/drm_gem_framebuffer_helper.c
+++ b/drivers/gpu/drm/drm_gem_framebuffer_helper.c
@@ -499,11 +499,8 @@ static __u32 drm_gem_afbc_get_bpp(struct drm_device *dev,
info = drm_get_format_info(dev, mode_cmd);
- /* use whatever a driver has set */
- if (info->cpp[0])
- return info->cpp[0] * 8;
-
- /* guess otherwise */
+ // FIXME DRM_FORMAT_* should provide proper block info in
+ // FIXME drivers/gpu/drm/drm_fourcc.c
switch (info->format) {
case DRM_FORMAT_YUV420_8BIT:
return 12;
@@ -512,11 +509,8 @@ static __u32 drm_gem_afbc_get_bpp(struct drm_device *dev,
case DRM_FORMAT_VUY101010:
return 30;
default:
- break;
+ return drm_format_info_bpp(info, 0);
}
-
- /* all attempts failed */
- return 0;
}
static int drm_gem_afbc_min_size(struct drm_device *dev,
--
2.25.1
[PATCH 3/8] drm/fourcc: Add drm_format_info_bpp() helper
Add a helper to retrieve the actual number of bits per pixel for a
plane, taking into account the number of characters and pixels per
block for tiled formats.
Signed-off-by: Geert Uytterhoeven
---
drivers/gpu/drm/drm_fourcc.c | 19 +++
include/drm/drm_fourcc.h | 1 +
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 60ce63d728b8e308..5c77ce10f53e3a64 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -388,6 +388,25 @@ unsigned int drm_format_info_block_height(const struct
drm_format_info *info,
}
EXPORT_SYMBOL(drm_format_info_block_height);
+/**
+ * drm_format_info_bpp - number of bits per pixel
+ * @info: pixel format info
+ * @plane: plane index
+ *
+ * Returns:
+ * The actual number of bits per pixel, depending on the plane index.
+ */
+unsigned int drm_format_info_bpp(const struct drm_format_info *info, int plane)
+{
+ if (!info || plane < 0 || plane >= info->num_planes)
+ return 0;
+
+ return info->char_per_block[plane] * 8 /
+ (drm_format_info_block_width(info, plane) *
+ drm_format_info_block_height(info, plane));
+}
+EXPORT_SYMBOL(drm_format_info_bpp);
+
/**
* drm_format_info_min_pitch - computes the minimum required pitch in bytes
* @info: pixel format info
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 22aa64d07c7905e2..3800a7ad7f0cda7a 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -313,6 +313,7 @@ unsigned int drm_format_info_block_width(const struct
drm_format_info *info,
int plane);
unsigned int drm_format_info_block_height(const struct drm_format_info *info,
int plane);
+unsigned int drm_format_info_bpp(const struct drm_format_info *info, int
plane);
uint64_t drm_format_info_min_pitch(const struct drm_format_info *info,
int plane, unsigned int buffer_width);
--
2.25.1
[PATCH 0/8] drm: Add support for low-color frame buffer formats
Hi all,
A long outstanding issue with the DRM subsystem has been the lack of
support for low-color displays, as used typically on older desktop
systems and small embedded displays.
This patch series adds support for color-indexed frame buffer formats
with 2, 4, and 16 colors. It has been tested on ARAnyM using a
work-in-progress Atari DRM driver, with text console operation and
fbtest.
Overview:
- Patches 1 and 2 give a working system, albeit with a too large pitch
(line length),
- Patches 3 and 4 reduce memory consumption by correcting the pitch
in case bpp < 8,
- Patches 5 and 6 are untested, but may become useful with DRM
userspace,
- Patches 7 and 8 add more fourcc codes for grayscale and monochrome
frame buffer formats, which may be useful for e.g. the ssd130x and
repaper drivers.
Notes:
- I haven't looked yet into making modetest draw a correct image.
- As this was used on emulated hardware only, and I do not have Atari
hardware, I do not have performance figures to compare with fbdev.
I hope to do proper measuring with an Amiga DRM driver, eventually.
Thanks for your comments!
Geert Uytterhoeven (8):
drm/fourcc: Add DRM_FORMAT_C[124]
drm/fb-helper: Add support for DRM_FORMAT_C[124]
drm/fourcc: Add drm_format_info_bpp() helper
drm/client: Use actual bpp when allocating frame buffers
drm/framebuffer: Use actual bpp for DRM_IOCTL_MODE_GETFB
drm/gem-fb-helper: Use actual bpp for size calculations
drm/fourcc: Add DRM_FORMAT_R[124]
drm/fourcc: Add DRM_FORMAT_D1
drivers/gpu/drm/drm_client.c | 4 +-
drivers/gpu/drm/drm_fb_helper.c | 120 ++-
drivers/gpu/drm/drm_fourcc.c | 45 +++
drivers/gpu/drm/drm_framebuffer.c| 2 +-
drivers/gpu/drm/drm_gem_framebuffer_helper.c | 12 +-
include/drm/drm_fourcc.h | 1 +
include/uapi/drm/drm_fourcc.h| 15 +++
7 files changed, 160 insertions(+), 39 deletions(-)
--
2.25.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH 5/8] drm/framebuffer: Use actual bpp for DRM_IOCTL_MODE_GETFB
When userspace queries the properties of a frame buffer, the number of bits per pixel is derived from the deprecated drm_format_info.cpp[] field, which does not take into account block sizes. Fix this by using the actual number of bits per pixel instead. Signed-off-by: Geert Uytterhoeven --- Untested. --- drivers/gpu/drm/drm_framebuffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c index 07f5abc875e97b96..4b9d7b01cb99c03d 100644 --- a/drivers/gpu/drm/drm_framebuffer.c +++ b/drivers/gpu/drm/drm_framebuffer.c @@ -530,7 +530,7 @@ int drm_mode_getfb(struct drm_device *dev, r->height = fb->height; r->width = fb->width; r->depth = fb->format->depth; - r->bpp = fb->format->cpp[0] * 8; + r->bpp = drm_format_info_bpp(fb->format, 0); r->pitch = fb->pitches[0]; /* GET_FB() is an unprivileged ioctl so we must not return a -- 2.25.1
[PATCH 4/8] drm/client: Use actual bpp when allocating frame buffers
When allocating a frame buffer, the number of bits per pixel needed is derived from the deprecated drm_format_info.cpp[] field. While this works for formats using less than 8 bits per pixel, it does lead to a large overallocation. Reduce memory consumption by using the actual number of bits per pixel instead. Signed-off-by: Geert Uytterhoeven --- drivers/gpu/drm/drm_client.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_client.c b/drivers/gpu/drm/drm_client.c index ce45e380f4a2028f..c6a279e3de95591a 100644 --- a/drivers/gpu/drm/drm_client.c +++ b/drivers/gpu/drm/drm_client.c @@ -264,7 +264,7 @@ drm_client_buffer_create(struct drm_client_dev *client, u32 width, u32 height, u dumb_args.width = width; dumb_args.height = height; - dumb_args.bpp = info->cpp[0] * 8; + dumb_args.bpp = drm_format_info_bpp(info, 0); ret = drm_mode_create_dumb(dev, &dumb_args, client->file); if (ret) goto err_delete; @@ -372,7 +372,7 @@ static int drm_client_buffer_addfb(struct drm_client_buffer *buffer, int ret; info = drm_format_info(format); - fb_req.bpp = info->cpp[0] * 8; + fb_req.bpp = drm_format_info_bpp(info, 0); fb_req.depth = info->depth; fb_req.width = width; fb_req.height = height; -- 2.25.1
[PATCH 2/8] drm/fb-helper: Add support for DRM_FORMAT_C[124]
Add support for color-indexed frame buffer formats with two, four, and
sixteen colors to the DRM framebuffer helper functions:
1. Add support for depths 1/2/4 to the damage helper,
2. For color-indexed modes, the length of the color bitfields must be
set to the color depth, else the logo code may pick a logo with too
many colors. Drop the incorrect DAC width comment, which
originates from the i915 driver.
3. Accept C[124] modes when validating or filling in struct
fb_var_screeninfo, and use the correct number of bits per pixel.
4. Set the visual to FB_VISUAL_PSEUDOCOLOR for all supported
color-indexed modes.
Signed-off-by: Geert Uytterhoeven
---
drivers/gpu/drm/drm_fb_helper.c | 120 +---
1 file changed, 93 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index ed43b987d306afce..a4afed0de1570841 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -376,12 +376,34 @@ static void drm_fb_helper_damage_blit_real(struct
drm_fb_helper *fb_helper,
struct iosys_map *dst)
{
struct drm_framebuffer *fb = fb_helper->fb;
- unsigned int cpp = fb->format->cpp[0];
- size_t offset = clip->y1 * fb->pitches[0] + clip->x1 * cpp;
- void *src = fb_helper->fbdev->screen_buffer + offset;
- size_t len = (clip->x2 - clip->x1) * cpp;
+ size_t offset = clip->y1 * fb->pitches[0];
+ size_t len = clip->x2 - clip->x1;
unsigned int y;
+ void *src;
+ switch (fb->format->depth) {
+ case 1:
+ offset += clip->x1 / 8;
+ len = DIV_ROUND_UP(len + clip->x1 % 8, 8);
+ break;
+
+ case 2:
+ offset += clip->x1 / 4;
+ len = DIV_ROUND_UP(len + clip->x1 % 4, 4);
+ break;
+
+ case 4:
+ offset += clip->x1 / 2;
+ len = DIV_ROUND_UP(len + clip->x1 % 2, 2);
+ break;
+
+ default:
+ offset += clip->x1 * fb->format->cpp[0];
+ len *= fb->format->cpp[0];
+ break;
+ }
+
+ src = fb_helper->fbdev->screen_buffer + offset;
iosys_map_incr(dst, offset); /* go to first pixel within clip rect */
for (y = clip->y1; y < clip->y2; y++) {
@@ -1231,19 +1253,30 @@ static bool drm_fb_pixel_format_equal(const struct
fb_var_screeninfo *var_1,
}
static void drm_fb_helper_fill_pixel_fmt(struct fb_var_screeninfo *var,
-u8 depth)
-{
- switch (depth) {
- case 8:
+const struct drm_format_info *format)
+{
+ u8 depth = format->depth;
+
+ switch (format->format) {
+ // FIXME Perhaps
+ // #define DRM_FORMAT_C0 fourcc_code('C', '0', ' ', ' ')
+ // if ((format & fourcc_code(0xff, 0xf8, 0xff, 0xff) == DRM_FORMAT_C0)
...
+ case DRM_FORMAT_C1:
+ case DRM_FORMAT_C2:
+ case DRM_FORMAT_C4:
+ case DRM_FORMAT_C8:
var->red.offset = 0;
var->green.offset = 0;
var->blue.offset = 0;
- var->red.length = 8; /* 8bit DAC */
- var->green.length = 8;
- var->blue.length = 8;
+ var->red.length = depth;
+ var->green.length = depth;
+ var->blue.length = depth;
var->transp.offset = 0;
var->transp.length = 0;
- break;
+ return;
+ }
+
+ switch (depth) {
case 15:
var->red.offset = 10;
var->green.offset = 5;
@@ -1298,7 +1331,9 @@ int drm_fb_helper_check_var(struct fb_var_screeninfo *var,
{
struct drm_fb_helper *fb_helper = info->par;
struct drm_framebuffer *fb = fb_helper->fb;
+ const struct drm_format_info *format = fb->format;
struct drm_device *dev = fb_helper->dev;
+ unsigned int bpp;
if (in_dbg_master())
return -EINVAL;
@@ -1308,22 +1343,34 @@ int drm_fb_helper_check_var(struct fb_var_screeninfo
*var,
var->pixclock = 0;
}
- if ((drm_format_info_block_width(fb->format, 0) > 1) ||
- (drm_format_info_block_height(fb->format, 0) > 1))
- return -EINVAL;
+ switch (format->format) {
+ case DRM_FORMAT_C1:
+ case DRM_FORMAT_C2:
+ case DRM_FORMAT_C4:
+ bpp = format->depth;
+ break;
+
+ default:
+ if ((drm_format_info_block_width(format, 0) > 1) ||
+ (drm_format_info_block_height(format, 0) > 1))
+ return -EINVAL;
+
+ bpp = format->cpp[0] * 8;
+ break;
+ }
/*
* Changes struct fb_var_screeninfo are currently not pushed back
* to KMS, hence fail if different settings
Re: [PATCH v2 2/2] drm/msm/dpu: Add SC8180x to hw catalog
On 2/14/2022 8:33 PM, Bjorn Andersson wrote:
From: Rob Clark
Add SC8180x to the hardware catalog, for initial support for the
platform. Due to limitations in the DP driver only one of the four DP
interfaces is left enabled.
The SC8180x platform supports the newly added DPU_INTF_WIDEBUS flag and
the Windows-on-Snapdragon bootloader leaves the widebus bit set, so this
is flagged appropriately to ensure widebus is disabled - for now.
Signed-off-by: Rob Clark
[bjorn: Reworked intf and irq definitions]
Signed-off-by: Bjorn Andersson
---
Changes since v1:
- Dropped widebus flag
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 129 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
drivers/gpu/drm/msm/msm_drv.c | 1 +
4 files changed, 132 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index aa75991903a6..7ac0fe32df49 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -90,6 +90,17 @@
BIT(MDP_INTF3_INTR) | \
BIT(MDP_INTF4_INTR))
+#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+ BIT(MDP_SSPP_TOP0_INTR2) | \
+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+ BIT(MDP_INTF0_INTR) | \
+ BIT(MDP_INTF1_INTR) | \
+ BIT(MDP_INTF2_INTR) | \
+ BIT(MDP_INTF3_INTR) | \
+ BIT(MDP_INTF4_INTR) | \
+ BIT(MDP_INTF5_INTR) | \
+ BIT(MDP_AD4_0_INTR) | \
+ BIT(MDP_AD4_1_INTR))
#define DEFAULT_PIXEL_RAM_SIZE (50 * 1024)
#define DEFAULT_DPU_LINE_WIDTH2048
@@ -225,6 +236,22 @@ static const struct dpu_caps sm8150_dpu_caps = {
.max_vdeci_exp = MAX_VERT_DECIMATION,
};
+static const struct dpu_caps sc8180x_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_30,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 4096,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
static const struct dpu_caps sm8250_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
@@ -293,6 +320,31 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sc8180x_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x45C,
+ .features = 0,
+ .highest_bank_bit = 0x3,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x2AC, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+ .reg_off = 0x2B4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+ .reg_off = 0x2BC, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+ .reg_off = 0x2C4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x2AC, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+ .reg_off = 0x2B4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+ .reg_off = 0x2BC, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+ .reg_off = 0x2C4, .bit_off = 8},
+ },
+};
+
static const struct dpu_mdp_cfg sm8250_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -861,6 +913,16 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24,
INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
};
+static const struct dpu_intf_cfg sc8180x_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24,
INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK,
MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK,
MDP_SSPP_TOP0_INTR, 28, 29),
+ /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until
this is supported */
+ INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 999, 24, INTF_SC7180_MASK,
MDP_SSPP_TOP0_INTR, 30, 31),
+ INTF_BLK("intf_4", INTF_4, 0x6C000, INTF_DP, MSM_DP_CONTROLLER_1, 24,
INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
+ INTF_BLK("intf_5", INTF_5, 0x6C800, INTF_DP, MSM_DP_CONTROLLER_2,
Re: [PATCH v1 1/1] drm/i915/selftests: Replace too verbose for-loop with simpler while
On Tue, 15 Feb 2022, Andy Shevchenko wrote:
> It's hard to parse for-loop which has some magic calculations inside.
> Much cleaner to use while-loop directly.
I assume you're trying to prove a point following our recent
for-vs-while loop discussion. I really can't think of any other reason
you'd end up looking at this file or this loop.
With the change, the loop indeed becomes simpler, but it also runs one
iteration further than the original. Whoops.
It's a selftest. The loop's been there for five years. What are we
trying to achieve here? So we disagree on loops, fine. Perhaps this is
not the best use of either of our time? Please just let the for loops in
i915 be.
BR,
Jani.
>
> Signed-off-by: Andy Shevchenko
> ---
> drivers/gpu/drm/i915/selftests/i915_syncmap.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/selftests/i915_syncmap.c
> b/drivers/gpu/drm/i915/selftests/i915_syncmap.c
> index 47f4ae18a1ef..26981d1c3025 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_syncmap.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_syncmap.c
> @@ -36,10 +36,10 @@ __sync_print(struct i915_syncmap *p,
> unsigned int i, X;
>
> if (depth) {
> - unsigned int d;
> + unsigned int d = depth;
>
> - for (d = 0; d < depth - 1; d++) {
> - if (last & BIT(depth - d - 1))
> + while (d--) {
> + if (last & BIT(d))
> len = scnprintf(buf, *sz, "| ");
> else
> len = scnprintf(buf, *sz, "");
--
Jani Nikula, Intel Open Source Graphics Center
Reworking TTMs LRU handling
Hi guys, in the last set Felix pointed out a severe bug in the iterator implementation and after investigating I've found that my test case didn't even exercised this code path. So after fixing the test case I've found a couple of more minor problems. This is the resulting patch set with everything fixed as far as I can see. Please review and/or comment, Chriustian.
[PATCH 3/6] drm/ttm: allow bulk moves for all domains
Not just TT and VRAM.
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
Tested-by: Bas Nieuwenhuizen
---
drivers/gpu/drm/ttm/ttm_resource.c | 52 +-
include/drm/ttm/ttm_device.h | 2 --
include/drm/ttm/ttm_resource.h | 4 +--
3 files changed, 17 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_resource.c
b/drivers/gpu/drm/ttm/ttm_resource.c
index 88fc96c315b8..85a33473e4d2 100644
--- a/drivers/gpu/drm/ttm/ttm_resource.c
+++ b/drivers/gpu/drm/ttm/ttm_resource.c
@@ -51,38 +51,24 @@ EXPORT_SYMBOL(ttm_lru_bulk_move_init);
*/
void ttm_lru_bulk_move_tail(struct ttm_lru_bulk_move *bulk)
{
- unsigned i;
-
- for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) {
- struct ttm_lru_bulk_move_pos *pos = &bulk->tt[i];
- struct ttm_resource_manager *man;
+ unsigned i, j;
- if (!pos->first)
- continue;
+ for (i = 0; i < TTM_NUM_MEM_TYPES; ++i) {
+ for (j = 0; j < TTM_MAX_BO_PRIORITY; ++j) {
+ struct ttm_lru_bulk_move_pos *pos = &bulk->pos[i][j];
+ struct ttm_resource_manager *man;
- lockdep_assert_held(&pos->first->bo->bdev->lru_lock);
- dma_resv_assert_held(pos->first->bo->base.resv);
- dma_resv_assert_held(pos->last->bo->base.resv);
+ if (!pos->first)
+ continue;
- man = ttm_manager_type(pos->first->bo->bdev, TTM_PL_TT);
- list_bulk_move_tail(&man->lru[i], &pos->first->lru,
- &pos->last->lru);
- }
-
- for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) {
- struct ttm_lru_bulk_move_pos *pos = &bulk->vram[i];
- struct ttm_resource_manager *man;
+ lockdep_assert_held(&pos->first->bo->bdev->lru_lock);
+ dma_resv_assert_held(pos->first->bo->base.resv);
+ dma_resv_assert_held(pos->last->bo->base.resv);
- if (!pos->first)
- continue;
-
- lockdep_assert_held(&pos->first->bo->bdev->lru_lock);
- dma_resv_assert_held(pos->first->bo->base.resv);
- dma_resv_assert_held(pos->last->bo->base.resv);
-
- man = ttm_manager_type(pos->first->bo->bdev, TTM_PL_VRAM);
- list_bulk_move_tail(&man->lru[i], &pos->first->lru,
- &pos->last->lru);
+ man = ttm_manager_type(pos->first->bo->bdev, i);
+ list_bulk_move_tail(&man->lru[j], &pos->first->lru,
+ &pos->last->lru);
+ }
}
}
EXPORT_SYMBOL(ttm_lru_bulk_move_tail);
@@ -122,15 +108,7 @@ void ttm_resource_move_to_lru_tail(struct ttm_resource
*res,
if (!bulk)
return;
- switch (res->mem_type) {
- case TTM_PL_TT:
- ttm_lru_bulk_move_set_pos(&bulk->tt[bo->priority], res);
- break;
-
- case TTM_PL_VRAM:
- ttm_lru_bulk_move_set_pos(&bulk->vram[bo->priority], res);
- break;
- }
+ ttm_lru_bulk_move_set_pos(&bulk->pos[res->mem_type][bo->priority], res);
}
/**
diff --git a/include/drm/ttm/ttm_device.h b/include/drm/ttm/ttm_device.h
index 0a4ddec78d8f..425150f35fbe 100644
--- a/include/drm/ttm/ttm_device.h
+++ b/include/drm/ttm/ttm_device.h
@@ -30,8 +30,6 @@
#include
#include
-#define TTM_NUM_MEM_TYPES 8
-
struct ttm_device;
struct ttm_placement;
struct ttm_buffer_object;
diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h
index ef0ec700e896..e8a64ca3cf25 100644
--- a/include/drm/ttm/ttm_resource.h
+++ b/include/drm/ttm/ttm_resource.h
@@ -37,6 +37,7 @@
#include
#define TTM_MAX_BO_PRIORITY4U
+#define TTM_NUM_MEM_TYPES 8
struct ttm_device;
struct ttm_resource_manager;
@@ -217,8 +218,7 @@ struct ttm_lru_bulk_move_pos {
* Helper structure for bulk moves on the LRU list.
*/
struct ttm_lru_bulk_move {
- struct ttm_lru_bulk_move_pos tt[TTM_MAX_BO_PRIORITY];
- struct ttm_lru_bulk_move_pos vram[TTM_MAX_BO_PRIORITY];
+ struct ttm_lru_bulk_move_pos
pos[TTM_NUM_MEM_TYPES][TTM_MAX_BO_PRIORITY];
};
/**
--
2.25.1
[PATCH 1/6] drm/ttm: move the LRU into resource handling v3
This way we finally fix the problem that new resource are
not immediately evict-able after allocation.
That has caused numerous problems including OOM on GDS handling
and not being able to use TTM as general resource manager.
v2: stop assuming in ttm_resource_fini that res->bo is still valid.
v3: cleanup kerneldoc, add more lockdep annotation
Signed-off-by: Christian König
Tested-by: Bas Nieuwenhuizen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 2 +-
drivers/gpu/drm/ttm/ttm_bo.c| 115 ++
drivers/gpu/drm/ttm/ttm_bo_util.c | 1 -
drivers/gpu/drm/ttm/ttm_device.c| 64 ++---
drivers/gpu/drm/ttm/ttm_resource.c | 122 +++-
include/drm/ttm/ttm_bo_api.h| 16
include/drm/ttm/ttm_bo_driver.h | 29 +-
include/drm/ttm/ttm_resource.h | 35 +++
9 files changed, 197 insertions(+), 195 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index b37fc7d7d2c7..f2ce5a0defd9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -683,12 +683,12 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device
*adev,
if (vm->bulk_moveable) {
spin_lock(&adev->mman.bdev.lru_lock);
- ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
+ ttm_lru_bulk_move_tail(&vm->lru_bulk_move);
spin_unlock(&adev->mman.bdev.lru_lock);
return;
}
- memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
+ ttm_lru_bulk_move_init(&vm->lru_bulk_move);
spin_lock(&adev->mman.bdev.lru_lock);
list_for_each_entry(bo_base, &vm->idle, vm_status) {
@@ -698,11 +698,9 @@ void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
if (!bo->parent)
continue;
- ttm_bo_move_to_lru_tail(&bo->tbo, bo->tbo.resource,
- &vm->lru_bulk_move);
+ ttm_bo_move_to_lru_tail(&bo->tbo, &vm->lru_bulk_move);
if (shadow)
ttm_bo_move_to_lru_tail(&shadow->tbo,
- shadow->tbo.resource,
&vm->lru_bulk_move);
}
spin_unlock(&adev->mman.bdev.lru_lock);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index de3fe79b665a..582e8dc9bc8c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -849,7 +849,7 @@ void i915_ttm_adjust_lru(struct drm_i915_gem_object *obj)
bo->priority = I915_TTM_PRIO_NO_PAGES;
}
- ttm_bo_move_to_lru_tail(bo, bo->resource, NULL);
+ ttm_bo_move_to_lru_tail(bo, NULL);
spin_unlock(&bo->bdev->lru_lock);
}
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index db3dc7ef5382..cb0fa932d495 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -69,108 +69,16 @@ static void ttm_bo_mem_space_debug(struct
ttm_buffer_object *bo,
}
}
-static inline void ttm_bo_move_to_pinned(struct ttm_buffer_object *bo)
-{
- struct ttm_device *bdev = bo->bdev;
-
- list_move_tail(&bo->lru, &bdev->pinned);
-
- if (bdev->funcs->del_from_lru_notify)
- bdev->funcs->del_from_lru_notify(bo);
-}
-
-static inline void ttm_bo_del_from_lru(struct ttm_buffer_object *bo)
-{
- struct ttm_device *bdev = bo->bdev;
-
- list_del_init(&bo->lru);
-
- if (bdev->funcs->del_from_lru_notify)
- bdev->funcs->del_from_lru_notify(bo);
-}
-
-static void ttm_bo_bulk_move_set_pos(struct ttm_lru_bulk_move_pos *pos,
-struct ttm_buffer_object *bo)
-{
- if (!pos->first)
- pos->first = bo;
- pos->last = bo;
-}
-
void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo,
-struct ttm_resource *mem,
struct ttm_lru_bulk_move *bulk)
{
- struct ttm_device *bdev = bo->bdev;
- struct ttm_resource_manager *man;
-
- if (!bo->deleted)
- dma_resv_assert_held(bo->base.resv);
-
- if (bo->pin_count) {
- ttm_bo_move_to_pinned(bo);
- return;
- }
-
- if (!mem)
- return;
-
- man = ttm_manager_type(bdev, mem->mem_type);
- list_move_tail(&bo->lru, &man->lru[bo->priority]);
-
- if (bdev->funcs->del_from_lru_notify)
- bdev->funcs->del_from_lru_notify(bo);
-
- if (bulk && !bo->pin_count) {
- switch (bo->resource->mem_type) {
- case TTM_PL_TT:
- ttm_bo_bulk_move_set_pos(&bulk->tt[bo->priority], bo);
- break;
+ dma_resv_
[PATCH 4/6] drm/ttm: de-inline ttm_bo_pin/unpin
Those functions are going to become more complex, don't inline them any
more.
Signed-off-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo.c | 31 +++
include/drm/ttm/ttm_bo_api.h | 30 ++
2 files changed, 33 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 11e698e3374c..ed28a4229885 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -634,6 +634,37 @@ int ttm_mem_evict_first(struct ttm_device *bdev,
return ret;
}
+/**
+ * ttm_bo_pin - Pin the buffer object.
+ * @bo: The buffer object to pin
+ *
+ * Make sure the buffer is not evicted any more during memory pressure.
+ */
+void ttm_bo_pin(struct ttm_buffer_object *bo)
+{
+ dma_resv_assert_held(bo->base.resv);
+ WARN_ON_ONCE(!kref_read(&bo->kref));
+ ++bo->pin_count;
+}
+EXPORT_SYMBOL(ttm_bo_pin);
+
+/**
+ * ttm_bo_unpin - Unpin the buffer object.
+ * @bo: The buffer object to unpin
+ *
+ * Allows the buffer object to be evicted again during memory pressure.
+ */
+void ttm_bo_unpin(struct ttm_buffer_object *bo)
+{
+ dma_resv_assert_held(bo->base.resv);
+ WARN_ON_ONCE(!kref_read(&bo->kref));
+ if (bo->pin_count)
+ --bo->pin_count;
+ else
+ WARN_ON_ONCE(true);
+}
+EXPORT_SYMBOL(ttm_bo_unpin);
+
/*
* Add the last move fence to the BO and reserve a new shared slot. We only use
* a shared slot to avoid unecessary sync and rely on the subsequent bo move to
diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h
index 3da77fc54552..885b7698fd65 100644
--- a/include/drm/ttm/ttm_bo_api.h
+++ b/include/drm/ttm/ttm_bo_api.h
@@ -524,34 +524,8 @@ ssize_t ttm_bo_io(struct ttm_device *bdev, struct file
*filp,
int ttm_bo_swapout(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx,
gfp_t gfp_flags);
-/**
- * ttm_bo_pin - Pin the buffer object.
- * @bo: The buffer object to pin
- *
- * Make sure the buffer is not evicted any more during memory pressure.
- */
-static inline void ttm_bo_pin(struct ttm_buffer_object *bo)
-{
- dma_resv_assert_held(bo->base.resv);
- WARN_ON_ONCE(!kref_read(&bo->kref));
- ++bo->pin_count;
-}
-
-/**
- * ttm_bo_unpin - Unpin the buffer object.
- * @bo: The buffer object to unpin
- *
- * Allows the buffer object to be evicted again during memory pressure.
- */
-static inline void ttm_bo_unpin(struct ttm_buffer_object *bo)
-{
- dma_resv_assert_held(bo->base.resv);
- WARN_ON_ONCE(!kref_read(&bo->kref));
- if (bo->pin_count)
- --bo->pin_count;
- else
- WARN_ON_ONCE(true);
-}
+void ttm_bo_pin(struct ttm_buffer_object *bo);
+void ttm_bo_unpin(struct ttm_buffer_object *bo);
int ttm_mem_evict_first(struct ttm_device *bdev,
struct ttm_resource_manager *man,
--
2.25.1
[PATCH 5/6] drm/ttm: rework bulk move handling v4
Instead of providing the bulk move structure for each LRU update set
this as property of the BO. This should avoid costly bulk move rebuilds
with some games under RADV.
v2: some name polishing, add a few more kerneldoc words.
v3: add some lockdep
v4: fix bugs, handle pin/unpin as well
Signed-off-by: Christian König
Tested-by: Bas Nieuwenhuizen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 72 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 -
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 2 +-
drivers/gpu/drm/ttm/ttm_bo.c| 59 +---
drivers/gpu/drm/ttm/ttm_resource.c | 90 ++---
include/drm/ttm/ttm_bo_api.h| 16 ++---
include/drm/ttm/ttm_bo_driver.h | 2 +-
include/drm/ttm/ttm_device.h| 9 ---
include/drm/ttm/ttm_resource.h | 9 ++-
10 files changed, 138 insertions(+), 125 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 5859ed0552a4..57ac118fc266 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1498,7 +1498,6 @@ static struct ttm_device_funcs amdgpu_bo_driver = {
.io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
.io_mem_pfn = amdgpu_ttm_io_mem_pfn,
.access_memory = &amdgpu_ttm_access_memory,
- .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
};
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index f2ce5a0defd9..28f5e8b21a99 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -375,7 +375,7 @@ static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base
*base,
if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
return;
- vm->bulk_moveable = false;
+ ttm_bo_set_bulk_move(&bo->tbo, &vm->lru_bulk_move);
if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
amdgpu_vm_bo_relocated(base);
else
@@ -637,36 +637,6 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
list_add(&entry->tv.head, validated);
}
-/**
- * amdgpu_vm_del_from_lru_notify - update bulk_moveable flag
- *
- * @bo: BO which was removed from the LRU
- *
- * Make sure the bulk_moveable flag is updated when a BO is removed from the
- * LRU.
- */
-void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
-{
- struct amdgpu_bo *abo;
- struct amdgpu_vm_bo_base *bo_base;
-
- if (!amdgpu_bo_is_amdgpu_bo(bo))
- return;
-
- if (bo->pin_count)
- return;
-
- abo = ttm_to_amdgpu_bo(bo);
- if (!abo->parent)
- return;
- for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
- struct amdgpu_vm *vm = bo_base->vm;
-
- if (abo->tbo.base.resv == vm->root.bo->tbo.base.resv)
- vm->bulk_moveable = false;
- }
-
-}
/**
* amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
*
@@ -679,33 +649,9 @@ void amdgpu_vm_del_from_lru_notify(struct
ttm_buffer_object *bo)
void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
struct amdgpu_vm *vm)
{
- struct amdgpu_vm_bo_base *bo_base;
-
- if (vm->bulk_moveable) {
- spin_lock(&adev->mman.bdev.lru_lock);
- ttm_lru_bulk_move_tail(&vm->lru_bulk_move);
- spin_unlock(&adev->mman.bdev.lru_lock);
- return;
- }
-
- ttm_lru_bulk_move_init(&vm->lru_bulk_move);
-
spin_lock(&adev->mman.bdev.lru_lock);
- list_for_each_entry(bo_base, &vm->idle, vm_status) {
- struct amdgpu_bo *bo = bo_base->bo;
- struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo);
-
- if (!bo->parent)
- continue;
-
- ttm_bo_move_to_lru_tail(&bo->tbo, &vm->lru_bulk_move);
- if (shadow)
- ttm_bo_move_to_lru_tail(&shadow->tbo,
- &vm->lru_bulk_move);
- }
+ ttm_lru_bulk_move_tail(&vm->lru_bulk_move);
spin_unlock(&adev->mman.bdev.lru_lock);
-
- vm->bulk_moveable = true;
}
/**
@@ -728,8 +674,6 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
struct amdgpu_vm_bo_base *bo_base, *tmp;
int r;
- vm->bulk_moveable &= list_empty(&vm->evicted);
-
list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
struct amdgpu_bo *bo = bo_base->bo;
struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo);
@@ -1047,10 +991,16 @@ static void amdgpu_vm_free_table(struct
amdgpu_vm_bo_base *entry)
if (!entry->bo)
return;
+
shadow = amdgpu_bo_shadowed(entry->bo);
+ if (shadow) {
+ ttm_bo_set_bulk_
[PATCH 6/6] drm/amdgpu: drop amdgpu_gtt_node
We have the BO pointer in the base structure now as well.
Signed-off-by: Christian König
Reviewed-by: Daniel Vetter
Tested-by: Bas Nieuwenhuizen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 49 -
include/drm/ttm/ttm_resource.h | 8
2 files changed, 26 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 3bcd27ae379d..68494b959116 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -26,23 +26,12 @@
#include "amdgpu.h"
-struct amdgpu_gtt_node {
- struct ttm_buffer_object *tbo;
- struct ttm_range_mgr_node base;
-};
-
static inline struct amdgpu_gtt_mgr *
to_gtt_mgr(struct ttm_resource_manager *man)
{
return container_of(man, struct amdgpu_gtt_mgr, manager);
}
-static inline struct amdgpu_gtt_node *
-to_amdgpu_gtt_node(struct ttm_resource *res)
-{
- return container_of(res, struct amdgpu_gtt_node, base.base);
-}
-
/**
* DOC: mem_info_gtt_total
*
@@ -106,9 +95,9 @@ const struct attribute_group amdgpu_gtt_mgr_attr_group = {
*/
bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *res)
{
- struct amdgpu_gtt_node *node = to_amdgpu_gtt_node(res);
+ struct ttm_range_mgr_node *node = to_ttm_range_mgr_node(res);
- return drm_mm_node_allocated(&node->base.mm_nodes[0]);
+ return drm_mm_node_allocated(&node->mm_nodes[0]);
}
/**
@@ -128,15 +117,14 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager
*man,
{
struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man);
uint32_t num_pages = PFN_UP(tbo->base.size);
- struct amdgpu_gtt_node *node;
+ struct ttm_range_mgr_node *node;
int r;
- node = kzalloc(struct_size(node, base.mm_nodes, 1), GFP_KERNEL);
+ node = kzalloc(struct_size(node, mm_nodes, 1), GFP_KERNEL);
if (!node)
return -ENOMEM;
- node->tbo = tbo;
- ttm_resource_init(tbo, place, &node->base.base);
+ ttm_resource_init(tbo, place, &node->base);
if (!(place->flags & TTM_PL_FLAG_TEMPORARY) &&
ttm_resource_manager_usage(man) > man->size) {
r = -ENOSPC;
@@ -145,8 +133,7 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager
*man,
if (place->lpfn) {
spin_lock(&mgr->lock);
- r = drm_mm_insert_node_in_range(&mgr->mm,
- &node->base.mm_nodes[0],
+ r = drm_mm_insert_node_in_range(&mgr->mm, &node->mm_nodes[0],
num_pages, tbo->page_alignment,
0, place->fpfn, place->lpfn,
DRM_MM_INSERT_BEST);
@@ -154,18 +141,18 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager
*man,
if (unlikely(r))
goto err_free;
- node->base.base.start = node->base.mm_nodes[0].start;
+ node->base.start = node->mm_nodes[0].start;
} else {
- node->base.mm_nodes[0].start = 0;
- node->base.mm_nodes[0].size = node->base.base.num_pages;
- node->base.base.start = AMDGPU_BO_INVALID_OFFSET;
+ node->mm_nodes[0].start = 0;
+ node->mm_nodes[0].size = node->base.num_pages;
+ node->base.start = AMDGPU_BO_INVALID_OFFSET;
}
- *res = &node->base.base;
+ *res = &node->base;
return 0;
err_free:
- ttm_resource_fini(man, &node->base.base);
+ ttm_resource_fini(man, &node->base);
kfree(node);
return r;
}
@@ -181,12 +168,12 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager
*man,
static void amdgpu_gtt_mgr_del(struct ttm_resource_manager *man,
struct ttm_resource *res)
{
- struct amdgpu_gtt_node *node = to_amdgpu_gtt_node(res);
+ struct ttm_range_mgr_node *node = to_ttm_range_mgr_node(res);
struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man);
spin_lock(&mgr->lock);
- if (drm_mm_node_allocated(&node->base.mm_nodes[0]))
- drm_mm_remove_node(&node->base.mm_nodes[0]);
+ if (drm_mm_node_allocated(&node->mm_nodes[0]))
+ drm_mm_remove_node(&node->mm_nodes[0]);
spin_unlock(&mgr->lock);
ttm_resource_fini(man, res);
@@ -202,7 +189,7 @@ static void amdgpu_gtt_mgr_del(struct ttm_resource_manager
*man,
*/
int amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr)
{
- struct amdgpu_gtt_node *node;
+ struct ttm_range_mgr_node *node;
struct drm_mm_node *mm_node;
struct amdgpu_device *adev;
int r = 0;
@@ -210,8 +197,8 @@ int amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr)
adev = container_of(mgr, typeof(*adev), mman.gtt_mgr);
spin_lock(&mgr->lock);
[PATCH 2/6] drm/ttm: add resource iterator v3
Instead of duplicating that at different places add an iterator over all
the resources in a resource manager.
v2: add lockdep annotation and kerneldoc
v3: fix various bugs pointed out by Felix
Signed-off-by: Christian König
Tested-by: Bas Nieuwenhuizen
Reviewed-by: Daniel Vetter (v3)
---
drivers/gpu/drm/ttm/ttm_bo.c | 42 ++--
drivers/gpu/drm/ttm/ttm_device.c | 26 +++
drivers/gpu/drm/ttm/ttm_resource.c | 51 ++
include/drm/ttm/ttm_resource.h | 23 ++
4 files changed, 102 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index cb0fa932d495..11e698e3374c 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -579,38 +579,30 @@ int ttm_mem_evict_first(struct ttm_device *bdev,
struct ww_acquire_ctx *ticket)
{
struct ttm_buffer_object *bo = NULL, *busy_bo = NULL;
+ struct ttm_resource_cursor cursor;
struct ttm_resource *res;
bool locked = false;
- unsigned i;
int ret;
spin_lock(&bdev->lru_lock);
- for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) {
- list_for_each_entry(res, &man->lru[i], lru) {
- bool busy;
-
- bo = res->bo;
- if (!ttm_bo_evict_swapout_allowable(bo, ctx, place,
- &locked, &busy)) {
- if (busy && !busy_bo && ticket !=
- dma_resv_locking_ctx(bo->base.resv))
- busy_bo = bo;
- continue;
- }
-
- if (!ttm_bo_get_unless_zero(bo)) {
- if (locked)
- dma_resv_unlock(bo->base.resv);
- continue;
- }
- break;
+ ttm_resource_manager_for_each_res(man, &cursor, res) {
+ bool busy;
+
+ if (!ttm_bo_evict_swapout_allowable(res->bo, ctx, place,
+ &locked, &busy)) {
+ if (busy && !busy_bo && ticket !=
+ dma_resv_locking_ctx(res->bo->base.resv))
+ busy_bo = res->bo;
+ continue;
}
- /* If the inner loop terminated early, we have our candidate */
- if (&res->lru != &man->lru[i])
- break;
-
- bo = NULL;
+ if (!ttm_bo_get_unless_zero(res->bo)) {
+ if (locked)
+ dma_resv_unlock(res->bo->base.resv);
+ continue;
+ }
+ bo = res->bo;
+ break;
}
if (!bo) {
diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c
index ba35887147ba..a0562ab386f5 100644
--- a/drivers/gpu/drm/ttm/ttm_device.c
+++ b/drivers/gpu/drm/ttm/ttm_device.c
@@ -142,10 +142,10 @@ EXPORT_SYMBOL(ttm_global_swapout);
int ttm_device_swapout(struct ttm_device *bdev, struct ttm_operation_ctx *ctx,
gfp_t gfp_flags)
{
+ struct ttm_resource_cursor cursor;
struct ttm_resource_manager *man;
- struct ttm_buffer_object *bo;
struct ttm_resource *res;
- unsigned i, j;
+ unsigned i;
int ret;
spin_lock(&bdev->lru_lock);
@@ -154,20 +154,16 @@ int ttm_device_swapout(struct ttm_device *bdev, struct
ttm_operation_ctx *ctx,
if (!man || !man->use_tt)
continue;
- for (j = 0; j < TTM_MAX_BO_PRIORITY; ++j) {
- list_for_each_entry(res, &man->lru[j], lru) {
- uint32_t num_pages;
-
- bo = res->bo;
- num_pages = PFN_UP(bo->base.size);
+ ttm_resource_manager_for_each_res(man, &cursor, res) {
+ struct ttm_buffer_object *bo = res->bo;
+ uint32_t num_pages = PFN_UP(bo->base.size);
- ret = ttm_bo_swapout(bo, ctx, gfp_flags);
- /* ttm_bo_swapout has dropped the lru_lock */
- if (!ret)
- return num_pages;
- if (ret != -EBUSY)
- return ret;
- }
+ ret = ttm_bo_swapout(bo, ctx, gfp_flags);
+ /* ttm_bo_swapout has dropped the lru_lock */
+ if (!ret)
+ return num_pages;
+ if (ret != -EBUSY)
+ return ret;
Re: [PATCH v2 2/2] drm/msm/dpu: Add SC8180x to hw catalog
On Tue 15 Feb 11:14 CST 2022, Abhinav Kumar wrote:
>
>
> On 2/14/2022 8:33 PM, Bjorn Andersson wrote:
> > From: Rob Clark
> >
> > Add SC8180x to the hardware catalog, for initial support for the
> > platform. Due to limitations in the DP driver only one of the four DP
> > interfaces is left enabled.
> >
> > The SC8180x platform supports the newly added DPU_INTF_WIDEBUS flag and
> > the Windows-on-Snapdragon bootloader leaves the widebus bit set, so this
> > is flagged appropriately to ensure widebus is disabled - for now.
> >
> > Signed-off-by: Rob Clark
> > [bjorn: Reworked intf and irq definitions]
> > Signed-off-by: Bjorn Andersson
> > ---
> >
> > Changes since v1:
> > - Dropped widebus flag
> >
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 129 ++
> > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
> > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> > drivers/gpu/drm/msm/msm_drv.c | 1 +
> > 4 files changed, 132 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > index aa75991903a6..7ac0fe32df49 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> > @@ -90,6 +90,17 @@
> > BIT(MDP_INTF3_INTR) | \
> > BIT(MDP_INTF4_INTR))
> > +#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> > + BIT(MDP_SSPP_TOP0_INTR2) | \
> > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > + BIT(MDP_INTF0_INTR) | \
> > + BIT(MDP_INTF1_INTR) | \
> > + BIT(MDP_INTF2_INTR) | \
> > + BIT(MDP_INTF3_INTR) | \
> > + BIT(MDP_INTF4_INTR) | \
> > + BIT(MDP_INTF5_INTR) | \
> > + BIT(MDP_AD4_0_INTR) | \
> > + BIT(MDP_AD4_1_INTR))
> > #define DEFAULT_PIXEL_RAM_SIZE(50 * 1024)
> > #define DEFAULT_DPU_LINE_WIDTH2048
> > @@ -225,6 +236,22 @@ static const struct dpu_caps sm8150_dpu_caps = {
> > .max_vdeci_exp = MAX_VERT_DECIMATION,
> > };
> > +static const struct dpu_caps sc8180x_dpu_caps = {
> > + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > + .max_mixer_blendstages = 0xb,
> > + .qseed_type = DPU_SSPP_SCALER_QSEED3,
> > + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
> > + .ubwc_version = DPU_HW_UBWC_VER_30,
> > + .has_src_split = true,
> > + .has_dim_layer = true,
> > + .has_idle_pc = true,
> > + .has_3d_merge = true,
> > + .max_linewidth = 4096,
> > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > + .max_hdeci_exp = MAX_HORZ_DECIMATION,
> > + .max_vdeci_exp = MAX_VERT_DECIMATION,
> > +};
> > +
> > static const struct dpu_caps sm8250_dpu_caps = {
> > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> > .max_mixer_blendstages = 0xb,
> > @@ -293,6 +320,31 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
> > },
> > };
> > +static const struct dpu_mdp_cfg sc8180x_mdp[] = {
> > + {
> > + .name = "top_0", .id = MDP_TOP,
> > + .base = 0x0, .len = 0x45C,
> > + .features = 0,
> > + .highest_bank_bit = 0x3,
> > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
> > + .reg_off = 0x2AC, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
> > + .reg_off = 0x2B4, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
> > + .reg_off = 0x2BC, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
> > + .reg_off = 0x2C4, .bit_off = 0},
> > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
> > + .reg_off = 0x2AC, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
> > + .reg_off = 0x2B4, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
> > + .reg_off = 0x2BC, .bit_off = 8},
> > + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
> > + .reg_off = 0x2C4, .bit_off = 8},
> > + },
> > +};
> > +
> > static const struct dpu_mdp_cfg sm8250_mdp[] = {
> > {
> > .name = "top_0", .id = MDP_TOP,
> > @@ -861,6 +913,16 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
> > INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24,
> > INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
> > };
> > +static const struct dpu_intf_cfg sc8180x_intf[] = {
> > + INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24,
> > INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
> > + INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK,
> > MDP_SSPP_TOP0_INTR, 26, 27),
> > + INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK,
> > MDP_SSPP_TOP0_INTR, 28, 29),
> > + /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until
> > this is supported */
> > + INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 999
Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2: Introduce format modifier for DG2 clear color
On 15.2.2022 18.44, Chery, Nanley G wrote:
-Original Message-
From: Juha-Pekka Heikkila
Sent: Tuesday, February 15, 2022 8:15 AM
To: Chery, Nanley G ; Nanley Chery
; C, Ramalingam
Cc: intel-gfx ; Auld, Matthew
; dri-devel
Subject: Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2: Introduce format
modifier for DG2 clear color
On 15.2.2022 17.02, Chery, Nanley G wrote:
-Original Message-
From: Juha-Pekka Heikkila
Sent: Tuesday, February 15, 2022 6:56 AM
To: Nanley Chery ; C, Ramalingam
Cc: intel-gfx ; Chery, Nanley G
; Auld, Matthew ;
dri- devel
Subject: Re: [Intel-gfx] [PATCH v5 16/19] uapi/drm/dg2: Introduce
format modifier for DG2 clear color
On 12.2.2022 3.19, Nanley Chery wrote:
On Tue, Feb 1, 2022 at 2:42 AM Ramalingam C
wrote:
From: Mika Kahola
DG2 clear color render compression uses Tile4 layout. Therefore, we
need to define a new format modifier for uAPI to support clear
color
rendering.
v2:
Display version is fixed. [Imre]
KDoc is enhanced for cc modifier. [Nanley & Lionel]
Signed-off-by: Mika Kahola
cc: Anshuman Gupta
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/display/intel_fb.c| 8
drivers/gpu/drm/i915/display/skl_universal_plane.c | 9 -
include/uapi/drm/drm_fourcc.h | 10 ++
3 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 4d4d01963f15..3df6ef5ffec5 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -144,6 +144,12 @@ static const struct intel_modifier_desc
intel_modifiers[] = {
.modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
.display_ver = { 13, 13 },
.plane_caps = INTEL_PLANE_CAP_TILING_4 |
INTEL_PLANE_CAP_CCS_MC,
+ }, {
+ .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
+ .display_ver = { 13, 13 },
+ .plane_caps = INTEL_PLANE_CAP_TILING_4 |
+ INTEL_PLANE_CAP_CCS_RC_CC,
+
+ .ccs.cc_planes = BIT(1),
}, {
.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
.display_ver = { 13, 13 }, @@ -559,6 +565,7 @@
intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
else
return 512;
case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
case I915_FORMAT_MOD_4_TILED:
/*
@@ -763,6 +770,7 @@ unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
case I915_FORMAT_MOD_Yf_TILED:
return 1 * 1024 * 1024;
case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
return 16 * 1024;
default:
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index c38ae0876c15..b4dced1907c5 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -772,6 +772,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_4 |
PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
PLANE_CTL_CLEAR_COLOR_DISABLE;
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
+ return PLANE_CTL_TILED_4 |
+ PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y |
PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -2358,10 +2360,15 @@ skl_get_initial_plane_config(struct
intel_crtc
*crtc,
break;
case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
if (HAS_4TILE(dev_priv)) {
- if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+ u32 rc_mask =
PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
+
+ PLANE_CTL_CLEAR_COLOR_DISABLE;
+
+ if ((val & rc_mask) == rc_mask)
fb->modifier =
I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
fb->modifier =
I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
+ else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+ fb->modifier =
+ I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
else
fb->modifier = I915_FORMAT_MOD_4_TILED;
} else {
diff --git a/include/uapi/drm/drm_fourcc.h
b/include/ua
Re: [PATCH v6 25/35] iommu/mediatek: Migrate to aggregate driver
On 10/02/2022 12:03, Yong Wu wrote: > On Thu, 2022-01-27 at 12:01 -0800, Stephen Boyd wrote: >> Use an aggregate driver instead of component ops so that we can get >> proper driver probe ordering of the aggregate device with respect to >> all >> the component devices that make up the aggregate device. >> >> Cc: Yong Wu >> Cc: Joerg Roedel >> Cc: Will Deacon >> Cc: Daniel Vetter >> Cc: "Rafael J. Wysocki" >> Cc: Rob Clark >> Cc: Russell King >> Cc: Saravana Kannan >> Signed-off-by: Stephen Boyd > > + Krzysztof > > The memory/mtk-smi.c is expected to get Ack from Krzysztof. > Please resend with cc-ing me. I don't have the patch in my mailbox (wes not on address list) and I also cannot find it in linux-arm-kernel. Best regards, Krzysztof
[PATCH][next] treewide: Replace zero-length arrays with flexible-array members
There is a regular need in the kernel to provide a way to declare
having a dynamically sized set of trailing elements in a structure.
Kernel code should always use “flexible array members”[1] for these
cases. The older style of one-element or zero-length arrays should
no longer be used[2].
This code was transformed with the help of Coccinelle:
(next-20220214$ spatch --jobs $(getconf _NPROCESSORS_ONLN) --sp-file
script.cocci --include-headers --dir . > output.patch)
@@
identifier S, member, array;
type T1, T2;
@@
struct S {
...
T1 member;
T2 array[
- 0
];
};
UAPI and wireless changes were intentionally excluded from this patch
and will be sent out separately.
[1] https://en.wikipedia.org/wiki/Flexible_array_member
[2]
https://www.kernel.org/doc/html/v5.16/process/deprecated.html#zero-length-and-one-element-arrays
Link: https://github.com/KSPP/linux/issues/78
Signed-off-by: Gustavo A. R. Silva
---
Hi all,
I'm expecting to carry this patch in my tree, so it'd be great to
get some Acks. And given the size of the patch, I'm only sending
this to mailing lists.
Thanks!
arch/alpha/include/asm/hwrpb.h| 2 +-
arch/ia64/include/asm/sal.h | 2 +-
arch/s390/include/asm/ccwgroup.h | 2 +-
arch/s390/include/asm/chsc.h | 2 +-
arch/s390/include/asm/eadm.h | 2 +-
arch/s390/include/asm/fcx.h | 4 ++--
arch/s390/include/asm/idals.h | 2 +-
arch/s390/include/asm/sclp.h | 2 +-
arch/s390/include/asm/sysinfo.h | 6 +++---
arch/sh/include/asm/thread_info.h | 2 +-
arch/sparc/include/asm/vio.h | 10 +-
arch/um/include/shared/net_kern.h | 2 +-
arch/x86/include/asm/microcode_amd.h | 2 +-
arch/x86/include/asm/microcode_intel.h| 4 ++--
arch/x86/include/asm/pci.h| 2 +-
arch/x86/include/asm/pci_x86.h| 2 +-
arch/xtensa/include/asm/bootparam.h | 2 +-
drivers/crypto/caam/pdb.h | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 2 +-
drivers/gpu/drm/nouveau/include/nvfw/hs.h | 2 +-
.../hwtracing/coresight/coresight-config.h| 2 +-
drivers/misc/bcm-vk/bcm_vk.h | 2 +-
.../misc/habanalabs/include/common/cpucp_if.h | 6 +++---
.../habanalabs/include/gaudi/gaudi_packets.h | 4 ++--
.../habanalabs/include/goya/goya_packets.h| 4 ++--
.../net/ethernet/freescale/enetc/enetc_hw.h | 2 +-
drivers/net/ethernet/i825xx/sun3_82586.h | 2 +-
.../net/ethernet/marvell/octeontx2/af/npc.h | 6 +++---
drivers/net/ethernet/qlogic/qed/qed_mfw_hsi.h | 2 +-
drivers/net/ethernet/ti/davinci_mdio.c| 2 +-
drivers/scsi/dpt/dpti_i2o.h | 2 +-
drivers/scsi/elx/libefc_sli/sli4.h| 20 +--
drivers/scsi/mpi3mr/mpi3mr.h | 2 +-
drivers/scsi/qla2xxx/qla_bsg.h| 4 ++--
drivers/scsi/qla2xxx/qla_def.h| 2 +-
drivers/scsi/qla2xxx/qla_edif_bsg.h | 4 ++--
drivers/scsi/qla2xxx/qla_fw.h | 2 +-
drivers/scsi/qla4xxx/ql4_fw.h | 2 +-
drivers/staging/r8188eu/include/ieee80211.h | 6 +++---
drivers/staging/r8188eu/include/rtw_cmd.h | 10 +-
drivers/staging/rtl8712/rtl871x_cmd.h | 8
drivers/staging/rtl8723bs/include/ieee80211.h | 2 +-
drivers/staging/rtl8723bs/include/rtw_cmd.h | 2 +-
.../include/linux/raspberrypi/vchiq.h | 2 +-
drivers/visorbus/vbuschannel.h| 2 +-
fs/cifs/ntlmssp.h | 2 +-
fs/ext4/fast_commit.h | 4 ++--
fs/ksmbd/ksmbd_netlink.h | 2 +-
fs/ksmbd/ntlmssp.h| 6 +++---
fs/ksmbd/smb2pdu.h| 8
fs/ksmbd/transport_rdma.c | 2 +-
fs/ksmbd/xattr.h | 2 +-
fs/xfs/scrub/attr.h | 2 +-
include/acpi/actbl2.h | 2 +-
include/asm-generic/tlb.h | 4 ++--
include/linux/greybus/greybus_manifest.h | 4 ++--
include/linux/greybus/hd.h| 2 +-
include/linux/greybus/module.h| 2 +-
include/linux/i3c/ccc.h | 6 +++---
include/linux/mlx5/mlx5_ifc_fpga.h| 2 +-
include/linux/platform_data/brcmfmac.h| 2 +-
.../linux/platform_data/cros_ec_commands.h| 2 +-
include/net/bluetooth/mgmt.h | 2 +-
include/net/ioam6.h | 2 +-
include/sound/sof/channel_map.h | 4 ++--
scripts/dtc/libfdt/fdt.h | 4 ++--
sound/soc/intel/atom/sst-mfld-dsp.h | 4 ++--
sound/soc/intel/skylake/skl-topology.h| 2 +-
tools/lib/perf/include/perf/event.h | 2 +-
69 files ch
Re: [PATCH v4 2/2] drm/msm/dp: enable widebus feature for display port
On 2/14/2022 8:22 PM, Bjorn Andersson wrote:
On Mon 14 Feb 16:39 CST 2022, Kuogee Hsieh wrote:
Widebus feature will transmit two pixel data per pixel clock to interface.
This feature now is required to be enabled to easy migrant to higher
resolution applications in future. However since some legacy chipsets
does not support this feature, this feature is enabled base on chip's
hardware revision.
changes in v2:
-- remove compression related code from timing
-- remove op_info from struct msm_drm_private
-- remove unnecessary wide_bus_en variables
-- pass wide_bus_en into timing configuration by struct msm_dp
Changes in v3:
-- split patch into 3 patches
-- enable widebus feature base on chip hardware revision
Signed-off-by: Kuogee Hsieh
Tested-by: Bjorn Andersson
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 +++-
drivers/gpu/drm/msm/dp/dp_catalog.c | 36 +++--
drivers/gpu/drm/msm/dp/dp_catalog.h | 3 ++-
drivers/gpu/drm/msm/dp/dp_ctrl.c| 13 +++
drivers/gpu/drm/msm/dp/dp_ctrl.h| 1 +
drivers/gpu/drm/msm/dp/dp_display.c | 30
drivers/gpu/drm/msm/dp/dp_display.h | 2 ++
drivers/gpu/drm/msm/dp/dp_panel.c | 4 ++--
drivers/gpu/drm/msm/dp/dp_panel.h | 2 +-
drivers/gpu/drm/msm/msm_drv.h | 6 +
10 files changed, 90 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 0c22839..b2d23c2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2167,8 +2167,10 @@ int dpu_encoder_setup(struct drm_device *dev, struct
drm_encoder *enc,
timer_setup(&dpu_enc->vsync_event_timer,
dpu_encoder_vsync_event_handler,
0);
- else if (disp_info->intf_type == DRM_MODE_ENCODER_TMDS)
+ else if (disp_info->intf_type == DRM_MODE_ENCODER_TMDS) {
dpu_enc->dp = priv->dp[disp_info->h_tile_instance[0]];
+ dpu_enc->wide_bus_en = msm_dp_wide_bus_enable(dpu_enc->dp);
+ }
INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
dpu_encoder_off_work);
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c
b/drivers/gpu/drm/msm/dp/dp_catalog.c
index 64f0b26..99d087e 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
@@ -483,6 +483,27 @@ int dp_catalog_ctrl_set_pattern_state_bit(struct
dp_catalog *dp_catalog,
}
/**
+ * dp_catalog_hw_revision() - retrieve DP hw revision
+ *
+ * @dp_catalog: DP catalog structure
+ *
+ * return: u32
Q: What's 2+2?
A: Integer
This should say:
Return: the controller hardware revision
+ *
+ * This function return the DP controller hw revision
That's what "Return:" in the kernel-doc is supposed to clarify...
https://docs.kernel.org/doc-guide/kernel-doc.html is good to read.
+ *
+ */
+u32 dp_catalog_hw_revision(struct dp_catalog *dp_catalog)
+{
+ u32 revision;
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+
+ revision = dp_read_ahb(catalog, REG_DP_HW_VERSION);
There's no need for a local variable here, just:
return dp_read_ahb();
+
+ return revision;
+}
+
+/**
* dp_catalog_ctrl_reset() - reset DP controller
*
* @dp_catalog: DP catalog structure
@@ -739,10 +760,11 @@ u32 dp_catalog_ctrl_read_phy_pattern(struct dp_catalog
*dp_catalog)
}
/* panel related catalog functions */
-int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog)
+int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog, bool
wide_bus_en)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
+ u32 reg;
dp_write_link(catalog, REG_DP_TOTAL_HOR_VER,
dp_catalog->total);
@@ -751,7 +773,17 @@ int dp_catalog_panel_timing_cfg(struct dp_catalog
*dp_catalog)
dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY,
dp_catalog->width_blanking);
dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, dp_catalog->dp_active);
- dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, 0);
+
+ reg = dp_read_p0(catalog, MMSS_DP_INTF_CONFIG);
+
+ if (wide_bus_en)
+ reg |= BIT(4); /* DATABUS_WIDEN */
#define DATABUS_WIDEN BIT(4)
Would save you the need for writing that comment.
+ else
+ reg &= ~BIT(4);
+
+ DRM_DEBUG_DP("wide_bus_en=%d reg=%x\n", wide_bus_en, reg);
+
+ dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, reg);
return 0;
}
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h
index 7dea101..a3a0129 100644
--- a/drivers/gpu/d
Re: [PATCH v2 2/2] drm/msm/dpu: Add SC8180x to hw catalog
On 2/15/2022 9:28 AM, Bjorn Andersson wrote:
On Tue 15 Feb 11:14 CST 2022, Abhinav Kumar wrote:
On 2/14/2022 8:33 PM, Bjorn Andersson wrote:
From: Rob Clark
Add SC8180x to the hardware catalog, for initial support for the
platform. Due to limitations in the DP driver only one of the four DP
interfaces is left enabled.
The SC8180x platform supports the newly added DPU_INTF_WIDEBUS flag and
the Windows-on-Snapdragon bootloader leaves the widebus bit set, so this
is flagged appropriately to ensure widebus is disabled - for now.
Signed-off-by: Rob Clark
[bjorn: Reworked intf and irq definitions]
Signed-off-by: Bjorn Andersson
---
Changes since v1:
- Dropped widebus flag
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 129 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
drivers/gpu/drm/msm/msm_drv.c | 1 +
4 files changed, 132 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index aa75991903a6..7ac0fe32df49 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -90,6 +90,17 @@
BIT(MDP_INTF3_INTR) | \
BIT(MDP_INTF4_INTR))
+#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+ BIT(MDP_SSPP_TOP0_INTR2) | \
+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+ BIT(MDP_INTF0_INTR) | \
+ BIT(MDP_INTF1_INTR) | \
+ BIT(MDP_INTF2_INTR) | \
+ BIT(MDP_INTF3_INTR) | \
+ BIT(MDP_INTF4_INTR) | \
+ BIT(MDP_INTF5_INTR) | \
+ BIT(MDP_AD4_0_INTR) | \
+ BIT(MDP_AD4_1_INTR))
#define DEFAULT_PIXEL_RAM_SIZE (50 * 1024)
#define DEFAULT_DPU_LINE_WIDTH 2048
@@ -225,6 +236,22 @@ static const struct dpu_caps sm8150_dpu_caps = {
.max_vdeci_exp = MAX_VERT_DECIMATION,
};
+static const struct dpu_caps sc8180x_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_30,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 4096,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+ .max_hdeci_exp = MAX_HORZ_DECIMATION,
+ .max_vdeci_exp = MAX_VERT_DECIMATION,
+};
+
static const struct dpu_caps sm8250_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
@@ -293,6 +320,31 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sc8180x_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x45C,
+ .features = 0,
+ .highest_bank_bit = 0x3,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x2AC, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+ .reg_off = 0x2B4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+ .reg_off = 0x2BC, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+ .reg_off = 0x2C4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x2AC, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+ .reg_off = 0x2B4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+ .reg_off = 0x2BC, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+ .reg_off = 0x2C4, .bit_off = 8},
+ },
+};
+
static const struct dpu_mdp_cfg sm8250_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -861,6 +913,16 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24,
INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
};
+static const struct dpu_intf_cfg sc8180x_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24,
INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+ INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK,
MDP_SSPP_TOP0_INTR, 26, 27),
+ INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK,
MDP_SSPP_TOP0_INTR, 28, 29),
+ /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until
this is supported */
+ INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 999, 24, INTF_SC7180_MASK,
MDP_SSPP_TOP0_INTR, 30, 31),
+ INTF_BLK("intf_4", INTF_4, 0x6C000, INTF_DP, MSM_DP_CONTROLLER_1, 24,
INTF_SC7180_MAS
Re: [PATCH v2 00/12] iio: buffer-dma: write() and new DMABUF based API
Hi Jonathan, Le dim., févr. 13 2022 at 18:46:16 +, Jonathan Cameron a écrit : On Mon, 7 Feb 2022 12:59:21 + Paul Cercueil wrote: Hi Jonathan, This is the V2 of my patchset that introduces a new userspace interface based on DMABUF objects to complement the fileio API, and adds write() support to the existing fileio API. Hi Paul, It's been a little while. Perhaps you could summarize the various view points around the appropriateness of using DMABUF for this? I appreciate it is a tricky topic to distil into a brief summary but I know I would find it useful even if no one else does! So we want to have a high-speed interface where buffers of samples are passed around between IIO devices and other devices (e.g. USB or network), or made available to userspace without copying the data. DMABUF is, at least in theory, exactly what we need. Quoting the documentation (https://www.kernel.org/doc/html/v5.15/driver-api/dma-buf.html): "The dma-buf subsystem provides the framework for sharing buffers for hardware (DMA) access across multiple device drivers and subsystems, and for synchronizing asynchronous hardware access. This is used, for example, by drm “prime” multi-GPU support, but is of course not limited to GPU use cases." The problem is that right now DMABUF is only really used by DRM, and to quote Daniel, "dma-buf looks like something super generic and useful, until you realize that there's a metric ton of gpu/accelerator bagage piled in". Still, it seems to be the only viable option. We could add a custom buffer-passing interface, but that would mean implementing the same buffer-passing interface on the network and USB stacks, and before we know it we re-invented DMABUFs. Cheers, -Paul Changes since v1: - the patches that were merged in v1 have been (obviously) dropped from this patchset; - the patch that was setting the write-combine cache setting has been dropped as well, as it was simply not useful. - [01/12]: * Only remove the outgoing queue, and keep the incoming queue, as we want the buffer to start streaming data as soon as it is enabled. * Remove IIO_BLOCK_STATE_DEQUEUED, since it is now functionally the same as IIO_BLOCK_STATE_DONE. - [02/12]: * Fix block->state not being reset in iio_dma_buffer_request_update() for output buffers. * Only update block->bytes_used once and add a comment about why we update it. * Add a comment about why we're setting a different state for output buffers in iio_dma_buffer_request_update() * Remove useless cast to bool (!!) in iio_dma_buffer_io() - [05/12]: Only allow the new IOCTLs on the buffer FD created with IIO_BUFFER_GET_FD_IOCTL(). - [12/12]: * Explicitly state that the new interface is optional and is not implemented by all drivers. * The IOCTLs can now only be called on the buffer FD returned by IIO_BUFFER_GET_FD_IOCTL. * Move the page up a bit in the index since it is core stuff and not driver-specific. The patches not listed here have not been modified since v1. Cheers, -Paul Alexandru Ardelean (1): iio: buffer-dma: split iio_dma_buffer_fileio_free() function Paul Cercueil (11): iio: buffer-dma: Get rid of outgoing queue iio: buffer-dma: Enable buffer write support iio: buffer-dmaengine: Support specifying buffer direction iio: buffer-dmaengine: Enable write support iio: core: Add new DMABUF interface infrastructure iio: buffer-dma: Use DMABUFs instead of custom solution iio: buffer-dma: Implement new DMABUF based userspace API iio: buffer-dmaengine: Support new DMABUF based userspace API iio: core: Add support for cyclic buffers iio: buffer-dmaengine: Add support for cyclic buffers Documentation: iio: Document high-speed DMABUF based API Documentation/driver-api/dma-buf.rst | 2 + Documentation/iio/dmabuf_api.rst | 94 +++ Documentation/iio/index.rst | 2 + drivers/iio/adc/adi-axi-adc.c | 3 +- drivers/iio/buffer/industrialio-buffer-dma.c | 610 ++ .../buffer/industrialio-buffer-dmaengine.c| 42 +- drivers/iio/industrialio-buffer.c | 60 ++ include/linux/iio/buffer-dma.h| 38 +- include/linux/iio/buffer-dmaengine.h | 5 +- include/linux/iio/buffer_impl.h | 8 + include/uapi/linux/iio/buffer.h | 30 + 11 files changed, 749 insertions(+), 145 deletions(-) create mode 100644 Documentation/iio/dmabuf_api.rst
