[Bug 214071] New: amdgpu idle power draw to high at +75Hz
https://bugzilla.kernel.org/show_bug.cgi?id=214071 Bug ID: 214071 Summary: amdgpu idle power draw to high at +75Hz Product: Drivers Version: 2.5 Kernel Version: 5.13.10 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-...@kernel-bugs.osdl.org Reporter: p...@gmx.de Regression: No For best viewing pleasure I usually set my monitor to 144Hz and native 1080p. At that refresh rate my RX6900XT draws about 35 Watts in idle situations Memory clock stays at 1000Hz. I have to lower the monitors refresh rate to 75Hz, then the card draws only 8 Watts in idle and memory clock goes significantly down to 96MHz. Using 100 or 120 Hz does not help. Situation in windows is different. The same hardware setup works in Windows10 at 1080p@144 with idle power draw of just 8 Watts. So my guess is this is a driver issue and not a hardware issue. -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.
Re: [PATCH 1/2] drm: avoid races with modesetting rights
On 13/8/21 11:49 pm, Daniel Vetter wrote: On Fri, Aug 13, 2021 at 04:54:49PM +0800, Desmond Cheong Zhi Xi wrote: In drm_client_modeset.c and drm_fb_helper.c, drm_master_internal_{acquire,release} are used to avoid races with DRM userspace. These functions hold onto drm_device.master_mutex while committing, and bail if there's already a master. However, ioctls can still race between themselves. A time-of-check-to-time-of-use error can occur if an ioctl that changes the modeset has its rights revoked after it validates its permissions, but before it completes. There are three ioctls that can affect modesetting permissions: - DROP_MASTER ioctl removes rights for a master and its leases - REVOKE_LEASE ioctl revokes rights for a specific lease - SET_MASTER ioctl sets the device master if the master role hasn't been acquired yet All these races can be avoided by introducing an SRCU that acts as a barrier for ioctls that can change modesetting permissions. Processes that perform modesetting should hold a read lock on the new drm_device.master_barrier_srcu, and ioctls that change these permissions should call synchronize_srcu before returning. This ensures that any process that might have seen old permissions are flushed out before DROP_MASTER/REVOKE_LEASE/SET_MASTER ioctls return to userspace. Reported-by: Daniel Vetter Signed-off-by: Desmond Cheong Zhi Xi This looks pretty solid, but I think there's one gap where we can still race. Scenario. Process A has a drm fd with master rights and two threads: - thread 1 does a long-running display operation (like a modeset or whatever) - thread 2 does a drop-master Then we start a new process B, which acquires master in drm_open (there is no other one left). This is like setmaster ioctl, but your DRM_MASTER_FLUSH bit doesn't work there. Ah, I see the race. I think a good place to plug this would be in drm_master_open using the drm_master_flush (or drm_master_unlock_and_flush) that you suggested below. The other thing is that for modeset stuff (which this all is) srcu is probably massive overkill, and a simple rwsem should be good enough too. Maybe even better, since the rwsem guarantees that no new reader can start once you try to acquire the write side. Makes sense, I'll switch to a rwsem then. Finally, and this is a bit a bikeshed: I don't like much how DRM_MASTER_FLUSH leaks the need of these very few places into the very core drm_ioctl function. One idea I had was to use task_work in a special function, roughly void master_flush() { down_write(master_rwsem); up_write(master_rwms); } void drm_master_flush() { init_task_work(fpriv->master_flush_work, master_flush) task_work_add(fpriv->master_flush_work); /* if task_work_add fails we're exiting, at which point the lack * of master flush doesn't matter); } And maybe put a comment above the function explaining why and how this works. We could even do a drm_master_unlock_and_flush helper, since that's really what everyone wants, and it would make it very clear which master state changes need this flush. Instead of setting a flag bit in an ioctl table very far away ... Thoughts? -Daniel Sounds good. I wasn't aware of the task_work_add mechanism to queue work before the task returns to usermode, but this seems like a more explicit way to flush. Thanks for the feedback, Daniel. I'll fix this up in a v2. --- drivers/gpu/drm/drm_auth.c | 17 ++--- drivers/gpu/drm/drm_client_modeset.c | 10 ++ drivers/gpu/drm/drm_drv.c| 2 ++ drivers/gpu/drm/drm_fb_helper.c | 20 drivers/gpu/drm/drm_internal.h | 5 +++-- drivers/gpu/drm/drm_ioctl.c | 25 + include/drm/drm_device.h | 11 +++ include/drm/drm_ioctl.h | 7 +++ 8 files changed, 76 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c index 60a6b21474b1..004506608e76 100644 --- a/drivers/gpu/drm/drm_auth.c +++ b/drivers/gpu/drm/drm_auth.c @@ -29,6 +29,7 @@ */ #include +#include #include #include @@ -448,21 +449,31 @@ void drm_master_put(struct drm_master **master) EXPORT_SYMBOL(drm_master_put); /* Used by drm_client and drm_fb_helper */ -bool drm_master_internal_acquire(struct drm_device *dev) +bool drm_master_internal_acquire(struct drm_device *dev, int *idx) { + *idx = srcu_read_lock(&dev->master_barrier_srcu); + mutex_lock(&dev->master_mutex); if (dev->master) { mutex_unlock(&dev->master_mutex); + srcu_read_unlock(&dev->master_barrier_srcu, *idx); return false; } + mutex_unlock(&dev->master_mutex); return true; } EXPORT_SYMBOL(drm_master_internal_acquire); /* Used by drm_client and drm_fb_helper */ -void drm_master_internal_release(struct drm_device *dev) +void
[Bug 214071] amdgpu idle power draw too high at +75Hz
https://bugzilla.kernel.org/show_bug.cgi?id=214071 Paul Größel (p...@gmx.de) changed: What|Removed |Added Summary|amdgpu idle power draw to |amdgpu idle power draw too |high at +75Hz |high at +75Hz -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.
[Bug 214071] amdgpu idle power draw too high at +75Hz
https://bugzilla.kernel.org/show_bug.cgi?id=214071 --- Comment #1 from Paul Größel (p...@gmx.de) --- Hardware setup: Mainboard: MSI MPG B550I GAMING EDGE WIFI CPU: Ryzen 5950X GPU: Radeon RX 6900XT Kernel 5.13.10 mesa 21.1.4 X11 -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.
Re: [PATCH v2 03/12] x86/sev: Add an x86 version of prot_guest_has()
On 8/14/21 2:08 PM, Borislav Petkov wrote: On Fri, Aug 13, 2021 at 11:59:22AM -0500, Tom Lendacky wrote: diff --git a/arch/x86/include/asm/protected_guest.h b/arch/x86/include/asm/protected_guest.h new file mode 100644 index ..51e4eefd9542 --- /dev/null +++ b/arch/x86/include/asm/protected_guest.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Protected Guest (and Host) Capability checks + * + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Author: Tom Lendacky + */ + +#ifndef _X86_PROTECTED_GUEST_H +#define _X86_PROTECTED_GUEST_H + +#include + +#ifndef __ASSEMBLY__ + +static inline bool prot_guest_has(unsigned int attr) +{ +#ifdef CONFIG_AMD_MEM_ENCRYPT + if (sme_me_mask) + return amd_prot_guest_has(attr); +#endif + + return false; +} + +#endif /* __ASSEMBLY__ */ + +#endif /* _X86_PROTECTED_GUEST_H */ I think this can be simplified more, diff ontop below: - no need for the ifdeffery as amd_prot_guest_has() has versions for both when CONFIG_AMD_MEM_ENCRYPT is set or not. Ugh, yeah, not sure why I put that in for this version since I have the static inline for when CONFIG_AMD_MEM_ENCRYPT is not set. - the sme_me_mask check is pushed there too. - and since this is vendor-specific, I'm checking the vendor bit. Yeah, yeah, cross-vendor but I don't really believe that. It's not a cross-vendor thing as opposed to a KVM or other hypervisor thing where the family doesn't have to be reported as AMD or HYGON. That's why I made the if check be for sme_me_mask. I think that is the safer way to go. Thanks, Tom --- diff --git a/arch/x86/include/asm/protected_guest.h b/arch/x86/include/asm/protected_guest.h index 51e4eefd9542..8541c76d5da4 100644 --- a/arch/x86/include/asm/protected_guest.h +++ b/arch/x86/include/asm/protected_guest.h @@ -12,18 +12,13 @@ #include -#ifndef __ASSEMBLY__ - static inline bool prot_guest_has(unsigned int attr) { -#ifdef CONFIG_AMD_MEM_ENCRYPT - if (sme_me_mask) + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || + boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) return amd_prot_guest_has(attr); -#endif return false; } -#endif /* __ASSEMBLY__ */ - #endif/* _X86_PROTECTED_GUEST_H */ diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c index edc67ddf065d..5a0442a6f072 100644 --- a/arch/x86/mm/mem_encrypt.c +++ b/arch/x86/mm/mem_encrypt.c @@ -392,6 +392,9 @@ bool noinstr sev_es_active(void) bool amd_prot_guest_has(unsigned int attr) { + if (!sme_me_mask) + return false; + switch (attr) { case PATTR_MEM_ENCRYPT: return sme_me_mask != 0;
Re: [PATCH v2 03/12] x86/sev: Add an x86 version of prot_guest_has()
On Sun, Aug 15, 2021 at 08:53:31AM -0500, Tom Lendacky wrote: > It's not a cross-vendor thing as opposed to a KVM or other hypervisor > thing where the family doesn't have to be reported as AMD or HYGON. What would be the use case? A HV starts a guest which is supposed to be encrypted using the AMD's confidential guest technology but the HV tells the guest that it is not running on an AMD SVM HV but something else? Is that even an actual use case? Or am I way off? I know we have talked about this in the past but this still sounds insane. -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette
[PATCH v7 08/13] drm/mediatek: remove unused define in mtk_drm_ddp_comp.c
Remove the unsed define in mtk_drm_ddp_comp.c Signed-off-by: jason-jh.lin --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 10 -- 1 file changed, 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 75bc00e17fc4..aaa7450b3e2b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -21,8 +21,6 @@ #include "mtk_drm_crtc.h" #define DISP_OD_EN 0x -#define DISP_OD_INTEN 0x0008 -#define DISP_OD_INTSTA 0x000c #define DISP_OD_CFG0x0020 #define DISP_OD_SIZE 0x0030 #define DISP_DITHER_5 0x0114 @@ -42,8 +40,6 @@ #define DITHER_ENGINE_EN BIT(1) #define DISP_DITHER_SIZE 0x0030 -#define LUT_10BIT_MASK 0x03ff - #define OD_RELAYMODE BIT(0) #define UFO_BYPASS BIT(2) @@ -52,18 +48,12 @@ #define DISP_DITHERING BIT(2) #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) -#define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) #define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20) -#define DITHER_ADD_RSHIFT_R(x) (((x) & 0x7) << 16) #define DITHER_NEW_BIT_MODEBIT(0) #define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28) -#define DITHER_OVFLW_BIT_B(x) (((x) & 0x7) << 24) #define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20) -#define DITHER_ADD_RSHIFT_B(x) (((x) & 0x7) << 16) #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12) -#define DITHER_OVFLW_BIT_G(x) (((x) & 0x7) << 8) #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4) -#define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0) struct mtk_ddp_comp_dev { struct clk *clk; -- 2.18.0
[PATCH v7 11/13] drm/mediatek: add DSC support for mediatek-drm
DSC is designed for real-time systems with real-time compression, transmission, decompression and display. The DSC standard is a specification of the algorithms used for compressing and decompressing image display streams, including the specification of the syntax and semantics of the compressed video bit stream. Signed-off-by: jason-jh.lin --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 47 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +- 3 files changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 28bc42fd0b8a..beabadd206c9 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -45,6 +45,12 @@ #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12) #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4) +#define DISP_REG_DSC_CON 0x +#define DSC_EN BIT(0) +#define DSC_DUAL_INOUT BIT(2) +#define DSC_BYPASS BIT(4) +#define DSC_UFOE_SEL BIT(16) + #define DISP_REG_OD_EN 0x #define DISP_REG_OD_CFG0x0020 #define OD_RELAYMODE BIT(0) @@ -211,6 +217,35 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc, DISP_DITHERING, cmdq_pkt); } +static void mtk_dsc_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + /* dsc bypass mode */ + mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs, + DISP_REG_DSC_CON, DSC_BYPASS); + mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs, + DISP_REG_DSC_CON, DSC_UFOE_SEL); + mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs, + DISP_REG_DSC_CON, DSC_DUAL_INOUT); +} + +static void mtk_dsc_start(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + writel_relaxed(DSC_EN, &priv->regs + DISP_REG_DSC_CON); +} + +static void mtk_dsc_stop(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON); +} + static void mtk_od_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -274,6 +309,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = { .stop = mtk_dpi_stop, }; +static const struct mtk_ddp_comp_funcs ddp_dsc = { + .clk_enable = mtk_ddp_clk_enable, + .clk_disable = mtk_ddp_clk_disable, + .config = mtk_dsc_config, + .start = mtk_dsc_start, + .stop = mtk_dsc_stop, +}; + static const struct mtk_ddp_comp_funcs ddp_dsi = { .start = mtk_dsi_ddp_start, .stop = mtk_dsi_ddp_stop, @@ -335,6 +378,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_CCORR] = "ccorr", [MTK_DISP_COLOR] = "color", [MTK_DISP_DITHER] = "dither", + [MTK_DISP_DSC] = "dsc", [MTK_DISP_GAMMA] = "gamma", [MTK_DISP_MUTEX] = "mutex", [MTK_DISP_OD] = "od", @@ -364,6 +408,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER,0, &ddp_dither }, [DDP_COMPONENT_DPI0]= { MTK_DPI,0, &ddp_dpi }, [DDP_COMPONENT_DPI1]= { MTK_DPI,1, &ddp_dpi }, + [DDP_COMPONENT_DSC0]= { MTK_DISP_DSC, 0, &ddp_dsc }, + [DDP_COMPONENT_DSC1]= { MTK_DISP_DSC, 1, &ddp_dsc }, [DDP_COMPONENT_DSI0]= { MTK_DSI,0, &ddp_dsi }, [DDP_COMPONENT_DSI1]= { MTK_DSI,1, &ddp_dsi }, [DDP_COMPONENT_DSI2]= { MTK_DSI,2, &ddp_dsi }, @@ -498,6 +544,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, if (type == MTK_DISP_BLS || type == MTK_DISP_CCORR || type == MTK_DISP_COLOR || + type == MTK_DISP_DSC || type == MTK_DISP_GAMMA || type == MTK_DISP_OVL || type == MTK_DISP_OVL_2L || diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index d317b944df66..560be6bc9d0e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -23,6 +23,7 @@ enum mtk_ddp_comp_type { MTK_DI
[PATCH v7 00/13] Add Mediatek Soc DRM (vdosys0) support for mt8195
Change in v7: - add dt=binding of mmsys and disp path into this series - separate th modidfication of alphabetic order, remove unused define and rename the define of register offset to individual patch - add comment for MERGE ultra and preultra setting Change in v6: - adjust alphabetic order for mediatek-drm - move the patch that add mt8195 support for mediatek-drm as the lastest patch - add MERGE define for const varriable Change in v5: - add power-domain property into vdosys0 and vdosys1 dts node. - add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h Change in v4: - extract dt-binding patches to another patch series https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597 - squash DSC module into mtk_drm_ddp_comp.c - add coment and simplify MERGE config function Change in v3: - change mmsys and display dt-bindings document from txt to yaml - add MERGE additional description in display dt-bindings document - fix mboxes-cells number of vdosys0 node in dts - drop mutex eof convert define - remove pm_runtime apis in DSC and MERGE - change DSC and MERGE enum to alphabetic order Change in v2: - add DSC yaml file - add mt8195 drm driver porting parts in to one patch - remove useless define, variable, structure member and function - simplify DSC and MERGE file and switch threre order jason-jh.lin (13): dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding dt-bindings: mediatek: display: split each block to individual yaml dt-bindings: mediatek: add mediatek,dsc.yaml for mt8195 SoC binding dt-bindings: mediatek: display: add mt8195 SoC binding arm64: dts: mt8195: add display node for vdosys0 soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 soc: mediatek: add mtk-mutex support for mt8195 vdosys0 drm/mediatek: remove unused define in mtk_drm_ddp_comp.c drm/mediatek: rename the define of register offset drm/mediatek: adjust to the alphabetic order for mediatek-drm drm/mediatek: add DSC support for mediatek-drm drm/mediatek: add MERGE support for mediatek-drm drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 .../bindings/arm/mediatek/mediatek,mmsys.yaml | 8 + .../display/mediatek/mediatek,aal.yaml| 76 + .../display/mediatek/mediatek,ccorr.yaml | 74 + .../display/mediatek/mediatek,color.yaml | 85 ++ .../display/mediatek/mediatek,disp.txt| 219 -- .../display/mediatek/mediatek,dither.yaml | 75 + .../display/mediatek/mediatek,dsc.yaml| 69 + .../display/mediatek/mediatek,gamma.yaml | 76 + .../display/mediatek/mediatek,merge.yaml | 97 +++ .../display/mediatek/mediatek,mutex.yaml | 79 ++ .../display/mediatek/mediatek,od.yaml | 52 .../display/mediatek/mediatek,ovl-2l.yaml | 86 ++ .../display/mediatek/mediatek,ovl.yaml| 101 +++ .../display/mediatek/mediatek,rdma.yaml | 112 .../display/mediatek/mediatek,split.yaml | 56 .../display/mediatek/mediatek,ufoe.yaml | 59 .../display/mediatek/mediatek,wdma.yaml | 86 ++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 111 drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 + drivers/gpu/drm/mediatek/mtk_disp_merge.c | 268 ++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 239 ++-- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 24 +- drivers/gpu/drm/mediatek/mtk_drm_drv.c| 109 --- drivers/gpu/drm/mediatek/mtk_drm_drv.h| 1 + drivers/soc/mediatek/mt8195-mmsys.h | 106 +++ drivers/soc/mediatek/mtk-mmsys.c | 11 + drivers/soc/mediatek/mtk-mutex.c | 93 +- include/linux/soc/mediatek/mtk-mmsys.h| 9 + 30 files changed, 2031 insertions(+), 365 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml create mode 100644 Documen
[PATCH v7 05/13] arm64: dts: mt8195: add display node for vdosys0
Add display node for vdosys0. Signed-off-by: jason-jh.lin --- --- This patch is based on [1][2][3] [1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile - https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.w...@mediatek.com/ [2]arm64: dts: mt8195: add IOMMU and smi nodes - https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.s...@mediatek.com/ [3]arm64: dts: mt8195: add gce node - https://patchwork.kernel.org/project/linux-mediatek/patch/20210705053429.4380-4-jason-jh@mediatek.com/ --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 111 +++ 1 file changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 04d3e95175fa..aa2a7849b822 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1155,9 +1155,120 @@ #clock-cells = <1>; }; + ovl0: disp_ovl@1c00 { + compatible = "mediatek,mt8195-disp-ovl", +"mediatek,mt8183-disp-ovl"; + reg = <0 0x1c00 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; + iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; + mediatek,gce-client-reg = +<&gce1 SUBSYS_1c00 0x 0x1000>; + }; + + rdma0: disp_rdma@1c002000 { + compatible = "mediatek,mt8195-disp-rdma"; + reg = <0 0x1c002000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; + iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; + mediatek,gce-client-reg = +<&gce1 SUBSYS_1c00 0x2000 0x1000>; + }; + + color0: disp_color@1c003000 { + compatible = "mediatek,mt8195-disp-color", +"mediatek,mt8173-disp-color"; + reg = <0 0x1c003000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; + mediatek,gce-client-reg = +<&gce1 SUBSYS_1c00 0x3000 0x1000>; + }; + + ccorr0: disp_ccorr@1c004000 { + compatible = "mediatek,mt8195-disp-ccorr", +"mediatek,mt8183-disp-ccorr"; + reg = <0 0x1c004000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; + mediatek,gce-client-reg = +<&gce1 SUBSYS_1c00 0x4000 0x1000>; + }; + + aal0: disp_aal@1c005000 { + compatible = "mediatek,mt8195-disp-aal", +"mediatek,mt8173-disp-aal"; + reg = <0 0x1c005000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; + mediatek,gce-client-reg = +<&gce1 SUBSYS_1c00 0x5000 0x1000>; + }; + + gamma0: disp_gamma@1c006000 { + compatible = "mediatek,mt8195-disp-gamma", +"mediatek,mt8173-disp-gamma"; + reg = <0 0x1c006000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; + mediatek,gce-client-reg = +<&gce1 SUBSYS_1c00 0x6000 0x1000>; + }; + + dither0: disp_dither@1c007000 { + compatible = "mediatek,mt8195-disp-dither", +"mediatek,mt8183-disp-dither"; + reg = <0 0x1c007000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; + mediatek,gce-client-reg = +<&gce1 SUBSYS_1c00 0x7000 0x1000>; + }; + +
[PATCH v7 13/13] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver. Signed-off-by: jason-jh.lin Reviewed-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 28 2 files changed, 34 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 728aaadfea8c..00e9827acefe 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { .fifo_size = 5 * SZ_1K, }; +static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = { + .fifo_size = 1920, +}; + static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-rdma", .data = &mt2701_rdma_driver_data}, @@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { .data = &mt8173_rdma_driver_data}, { .compatible = "mediatek,mt8183-disp-rdma", .data = &mt8183_rdma_driver_data}, + { .compatible = "mediatek,mt8195-disp-rdma", + .data = &mt8195_rdma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index c7f369390ce6..cfe391266212 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -147,6 +147,19 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, }; +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DSC0, + DDP_COMPONENT_MERGE0, + DDP_COMPONENT_DP_INTF0, +}; + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -186,6 +199,11 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), }; +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { + .main_path = mt8195_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main), +}; + static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; @@ -406,10 +424,14 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8183-disp-dither", .data = (void *)MTK_DISP_DITHER }, + { .compatible = "mediatek,mt8195-disp-dsc", + .data = (void *)MTK_DISP_DSC }, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, { .compatible = "mediatek,mt8183-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, + { .compatible = "mediatek,mt8195-disp-merge", + .data = (void *)MTK_DISP_MERGE }, { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2712-disp-mutex", @@ -418,6 +440,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8183-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8195-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD }, { .compatible = "mediatek,mt2701-disp-ovl", @@ -438,6 +462,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8183-disp-rdma", .data = (void *)MTK_DISP_RDMA }, + { .compatible = "mediatek,mt8195-disp-rdma", + .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE }, { .compatible = "mediatek,mt8173-disp-wdma", @@ -468,6 +494,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt8173_mmsys_driver_data}, { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data}, + {.compatible = "mediatek,mt8195-vdosys0", + .data = &mt8195_vdosys0_driver_data}, { } }; MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); -- 2.18.0
[PATCH v7 12/13] drm/mediatek: add MERGE support for mediatek-drm
Add MERGE engine file: MERGE module is used to merge two slice-per-line inputs into one side-by-side output. Signed-off-by: jason-jh.lin --- drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 + drivers/gpu/drm/mediatek/mtk_disp_merge.c | 268 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 16 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 7 files changed, 298 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index dc54a7a69005..538e0087a44c 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -3,6 +3,7 @@ mediatek-drm-y := mtk_disp_ccorr.o \ mtk_disp_color.o \ mtk_disp_gamma.o \ + mtk_disp_merge.o \ mtk_disp_ovl.o \ mtk_disp_rdma.o \ mtk_drm_crtc.o \ diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index cafd9df2d63b..f407cd9d873e 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -46,6 +46,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev); +int mtk_merge_clk_enable(struct device *dev); +void mtk_merge_clk_disable(struct device *dev); +void mtk_merge_config(struct device *dev, unsigned int width, + unsigned int height, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +void mtk_merge_start(struct device *dev); +void mtk_merge_stop(struct device *dev); + void mtk_ovl_bgclr_in_on(struct device *dev); void mtk_ovl_bgclr_in_off(struct device *dev); void mtk_ovl_bypass_shadow(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c new file mode 100644 index ..ebcb646bde9c --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include + +#include "mtk_drm_ddp_comp.h" +#include "mtk_drm_drv.h" +#include "mtk_disp_drv.h" + +#define DISP_REG_MERGE_CTRL0x000 +#define MERGE_EN 1 +#define DISP_REG_MERGE_CFG_0 0x010 +#define DISP_REG_MERGE_CFG_4 0x020 +#define DISP_REG_MERGE_CFG_10 0x038 +/* no swap */ +#define SWAP_MODE 0 +#define FLD_SWAP_MODE GENMASK(4, 0) +#define DISP_REG_MERGE_CFG_12 0x040 +#define CFG_10_10_1PI_2PO_BUF_MODE 6 +#define CFG_10_10_2PI_2PO_BUF_MODE 8 +#define FLD_CFG_MERGE_MODE GENMASK(4, 0) +#define DISP_REG_MERGE_CFG_24 0x070 +#define DISP_REG_MERGE_CFG_25 0x074 +#define DISP_REG_MERGE_CFG_36 0x0a0 +#define ULTRA_EN 1 +#define PREULTRA_EN1 +#define HALT_FOR_DVFS_EN 0 +#define FLD_ULTRA_EN GENMASK(0, 0) +#define FLD_PREULTRA_ENGENMASK(4, 4) +#define FLD_HALT_FOR_DVFS_EN GENMASK(8, 8) +#define DISP_REG_MERGE_CFG_37 0x0a4 +/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */ +#define BUFFER_MODE3 +#define FLD_BUFFER_MODEGENMASK(1, 0) +#define DISP_REG_MERGE_CFG_38 0x0a8 +#define FLD_VDE_BLOCK_ULTRAGENMASK(0, 0) +#define FLD_VALID_TH_BLOCK_ULTRA GENMASK(4, 4) +#define FLD_ULTRA_FIFO_VALID_THGENMASK(31, 16) +#define DISP_REG_MERGE_CFG_39 0x0ac +#define FLD_NVDE_FORCE_PREULTRAGENMASK(8, 8) +#define FLD_NVALID_TH_FORCE_PREULTRA GENMASK(12, 12) +#define FLD_PREULTRA_FIFO_VALID_TH GENMASK(31, 16) + +/* + * For the ultra and preultra settings, 6us ~ 9us is experience value + * and the maximum frequency of mmsys clock is 594MHz. + */ +#define DISP_REG_MERGE_CFG_40 0x0b0 +/* 6 us, 594M pixel/sec */ +#define ULTRA_TH_LOW (6 * 594) +/* 8 us, 594M pixel/sec */ +#define ULTRA_TH_HIGH (8 * 594) +#define FLD_ULTRA_TH_LOW GENMASK(15, 0) +#define FLD_ULTRA_TH_HIGH GENMASK(31, 16) +#define DISP_REG_MERGE_CFG_41 0x0b4 +/* 8 us, 594M pixel/sec */ +#define PREULTRA_TH_LOW(8 * 594) +/* 9 us, 594M pixel/sec */ +#define PREULTRA_TH_HIGH (9 * 594) +#define FLD_PREULTRA_TH_LOWGE
[PATCH v7 10/13] drm/mediatek: adjust to the alphabetic order for mediatek-drm
Adjust to the alphabetic order for the define, function, struct and array in mediatek-drm driver Signed-off-by: jason-jh.lin --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 133 ++-- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 22 ++-- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 76 +-- 3 files changed, 115 insertions(+), 116 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 93beb980414f..28bc42fd0b8a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -20,17 +20,9 @@ #include "mtk_drm_ddp_comp.h" #include "mtk_drm_crtc.h" -#define DISP_REG_OD_EN 0x -#define DISP_REG_OD_CFG0x0020 -#define DISP_REG_OD_SIZE 0x0030 -#define DISP_REG_DITHER_5 0x0114 -#define DISP_REG_DITHER_7 0x011c -#define DISP_REG_DITHER_15 0x013c -#define DISP_REG_DITHER_16 0x0140 - -#define DISP_REG_UFO_START 0x #define DISP_REG_AAL_EN0x +#define AAL_EN BIT(0) #define DISP_REG_AAL_SIZE 0x0030 #define DISP_REG_DITHER_EN 0x @@ -38,23 +30,29 @@ #define DISP_REG_DITHER_CFG0x0020 #define DITHER_RELAY_MODE BIT(0) #define DITHER_ENGINE_EN BIT(1) -#define DISP_REG_DITHER_SIZE 0x0030 - -#define OD_RELAYMODE BIT(0) - -#define UFO_BYPASS BIT(2) - -#define AAL_EN BIT(0) #define DISP_DITHERING BIT(2) +#define DISP_REG_DITHER_SIZE 0x0030 +#define DISP_REG_DITHER_5 0x0114 +#define DISP_REG_DITHER_7 0x011c +#define DISP_REG_DITHER_15 0x013c #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) #define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20) #define DITHER_NEW_BIT_MODEBIT(0) +#define DISP_REG_DITHER_16 0x0140 #define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28) #define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20) #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12) #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4) +#define DISP_REG_OD_EN 0x +#define DISP_REG_OD_CFG0x0020 +#define OD_RELAYMODE BIT(0) +#define DISP_REG_OD_SIZE 0x0030 + +#define DISP_REG_UFO_START 0x +#define UFO_BYPASS BIT(2) + struct mtk_ddp_comp_dev { struct clk *clk; void __iomem *regs; @@ -106,20 +104,6 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value, #endif } -static int mtk_ddp_clk_enable(struct device *dev) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - return clk_prepare_enable(priv->clk); -} - -static void mtk_ddp_clk_disable(struct device *dev) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - clk_disable_unprepare(priv->clk); -} - void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg, unsigned int bpc, unsigned int cfg, unsigned int dither_en, struct cmdq_pkt *cmdq_pkt) @@ -146,38 +130,19 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg, } } -static void mtk_dither_set(struct device *dev, unsigned int bpc, - unsigned int cfg, struct cmdq_pkt *cmdq_pkt) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg, - DISP_DITHERING, cmdq_pkt); -} - -static void mtk_od_config(struct device *dev, unsigned int w, - unsigned int h, unsigned int vrefresh, - unsigned int bpc, struct cmdq_pkt *cmdq_pkt) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE); - mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG); - mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt); -} -static void mtk_od_start(struct device *dev) +static int mtk_ddp_clk_enable(struct device *dev) { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - writel(1, priv->regs + DISP_REG_OD_EN); + return clk_prepare_enable(priv->clk); } -static void mtk_ufoe_start(struct device *dev) +static void mtk_ddp_clk_disable(struct dev
[PATCH v7 09/13] drm/mediatek: rename the define of register offset
Add DISP_REG prefix for the define of register offset to make the difference from the define of register value. Signed-off-by: jason-jh.lin --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 57 +++-- 1 file changed, 29 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index aaa7450b3e2b..93beb980414f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -20,25 +20,25 @@ #include "mtk_drm_ddp_comp.h" #include "mtk_drm_crtc.h" -#define DISP_OD_EN 0x -#define DISP_OD_CFG0x0020 -#define DISP_OD_SIZE 0x0030 -#define DISP_DITHER_5 0x0114 -#define DISP_DITHER_7 0x011c -#define DISP_DITHER_15 0x013c -#define DISP_DITHER_16 0x0140 +#define DISP_REG_OD_EN 0x +#define DISP_REG_OD_CFG0x0020 +#define DISP_REG_OD_SIZE 0x0030 +#define DISP_REG_DITHER_5 0x0114 +#define DISP_REG_DITHER_7 0x011c +#define DISP_REG_DITHER_15 0x013c +#define DISP_REG_DITHER_16 0x0140 #define DISP_REG_UFO_START 0x -#define DISP_AAL_EN0x -#define DISP_AAL_SIZE 0x0030 +#define DISP_REG_AAL_EN0x +#define DISP_REG_AAL_SIZE 0x0030 -#define DISP_DITHER_EN 0x +#define DISP_REG_DITHER_EN 0x #define DITHER_EN BIT(0) -#define DISP_DITHER_CFG0x0020 +#define DISP_REG_DITHER_CFG0x0020 #define DITHER_RELAY_MODE BIT(0) #define DITHER_ENGINE_EN BIT(1) -#define DISP_DITHER_SIZE 0x0030 +#define DISP_REG_DITHER_SIZE 0x0030 #define OD_RELAYMODE BIT(0) @@ -129,19 +129,19 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg, return; if (bpc >= MTK_MIN_BPC) { - mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5); - mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7); + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5); + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7); mtk_ddp_write(cmdq_pkt, DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | DITHER_NEW_BIT_MODE, - cmdq_reg, regs, DISP_DITHER_15); + cmdq_reg, regs, DISP_REG_DITHER_15); mtk_ddp_write(cmdq_pkt, DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), - cmdq_reg, regs, DISP_DITHER_16); + cmdq_reg, regs, DISP_REG_DITHER_16); mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg); } } @@ -161,16 +161,16 @@ static void mtk_od_config(struct device *dev, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_OD_SIZE); - mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_OD_CFG); - mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt); + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE); + mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG); + mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt); } static void mtk_od_start(struct device *dev) { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - writel(1, priv->regs + DISP_OD_EN); + writel(1, priv->regs + DISP_REG_OD_EN); } static void mtk_ufoe_start(struct device *dev) @@ -186,7 +186,7 @@ static void mtk_aal_config(struct device *dev, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE); + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_AAL_SIZE); } static void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) @@ -200,14 +200,14 @@ static void mtk_aal_start(struct device *dev)
[PATCH v7 03/13] dt-bindings: mediatek: add mediatek, dsc.yaml for mt8195 SoC binding
1. Add mediatek,dsc.yaml to describe DSC module in details. 2. Add mt8195 SoC binding to mediatek,dsc.yaml. Signed-off-by: jason-jh.lin --- .../display/mediatek/mediatek,dsc.yaml| 69 +++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml new file mode 100644 index ..f94a95c6a1c5 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: mediatek display DSC controller + +maintainers: + - CK Hu + +description: | + The DSC standard is a specification of the algorithms used for + compressing and decompressing image display streams, including + the specification of the syntax and semantics of the compressed + video bit stream. DSC is designed for real-time systems with + real-time compression, transmission, decompression and Display. + +properties: + compatible: +oneOf: + - items: + - const: mediatek,mt8195-disp-dsc + + reg: +maxItems: 1 + + interrupts: +maxItems: 1 + + clocks: +items: + - description: DSC Wrapper Clock + + power-domains: +description: A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle. See + Documentation/devicetree/bindings/power/power-domain.yaml for details. + + mediatek,gce-client-reg: + description: +The register of display function block to be set by gce. There are 4 arguments, +such as gce node, subsys id, offset and register size. The subsys id that is +mapping to the register of display function blocks is defined in the gce header +include/include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - power-domains + - clocks + +additionalProperties: false + +examples: + - | + +dsc0: disp_dsc_wrap@1c009000 { +compatible = "mediatek,mt8195-disp-dsc"; +reg = <0 0x1c009000 0 0x1000>; +interrupts = ; +power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; +clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; +mediatek,gce-client-reg = <&gce1 SUBSYS_1c00 0x9000 0x1000>; +}; + -- 2.18.0
[PATCH v7 06/13] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
Add mt8195 vdosys0 clock driver name and routing table to the driver data of mtk-mmsys. Signed-off-by: jason-jh.lin --- This patch is base on [1] [1] soc: mmsys: mediatek: add mask to mmsys routes - https://patchwork.kernel.org/project/linux-mediatek/patch/20210729070549.5514-1-li...@fw-web.de/ The vdosys1 impelmentation patch [2] will base on this patch [2] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 - https://patchwork.kernel.org/project/linux-mediatek/patch/20210722094551.15255-8-nancy@mediatek.com/ --- drivers/soc/mediatek/mt8195-mmsys.h| 106 + drivers/soc/mediatek/mtk-mmsys.c | 11 +++ include/linux/soc/mediatek/mtk-mmsys.h | 9 +++ 3 files changed, 126 insertions(+) create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h new file mode 100644 index ..52053da8ee59 --- /dev/null +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H +#define __SOC_MEDIATEK_MT8195_MMSYS_H + +#define MT8195_VDO0_OVL_MOUT_EN0xf14 +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0BIT(0) +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0BIT(1) +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1BIT(4) +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1BIT(5) +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) + +#define MT8195_VDO0_SEL_IN 0xf34 +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0) +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0) +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4) +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4) +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5) +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5) +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8) +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8) +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9) +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 12) +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12) +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12) +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16) +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16) +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17) +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17) +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1(0 << 20) +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE(1 << 20) +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21) +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21) +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0(0 << 22) +#define MT8195_SEL_IN_DISP_WDMA0_FROM_VPP_MERGE(1 << 22) + +#define MT8195_VDO0_SEL_OUT0xf38 +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0) +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0) +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1) +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1) +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1) +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4) +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4) +#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1(3 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8) +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11) +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA0(1 << 11) +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12) +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12) +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16) +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16) +#define MT819
[PATCH v7 04/13] dt-bindings: mediatek: display: add mt8195 SoC binding
1. Add mt8195 SoC binding to AAL, CCORR, COLOR, DITHER, GAMMA, MERGE, MUTEX, OVL and RDMA yaml schema. 2. Add MERGE additional property description for mt8195 - async clock - fifo setting enable - reset controller Signed-off-by: jason-jh.lin --- .../display/mediatek/mediatek,aal.yaml| 1 + .../display/mediatek/mediatek,ccorr.yaml | 5 +++ .../display/mediatek/mediatek,color.yaml | 1 + .../display/mediatek/mediatek,dither.yaml | 5 +++ .../display/mediatek/mediatek,gamma.yaml | 5 +++ .../display/mediatek/mediatek,merge.yaml | 40 +++ .../display/mediatek/mediatek,mutex.yaml | 2 + .../display/mediatek/mediatek,ovl.yaml| 5 +++ .../display/mediatek/mediatek,rdma.yaml | 2 + 9 files changed, 66 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml index 7be772d77e36..e1820238db43 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -25,6 +25,7 @@ properties: - enum: - mediatek,mt2712-disp-aal - mediatek,mt8183-disp-aal + - mediatek,mt8195-disp-aal - enum: - mediatek,mt8173-disp-aal diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml index 5a1c27d6b3e2..4c556a2bc64a 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml @@ -21,6 +21,11 @@ properties: oneOf: - items: - const: mediatek,mt8183-disp-ccorr + - items: + - enum: + - mediatek,mt8195-disp-ccorr + - enum: + - mediatek,mt8183-disp-ccorr reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml index 9a3edf6f0b8e..a13096196a0c 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -35,6 +35,7 @@ properties: - items: - enum: - mediatek,mt8183-disp-color + - mediatek,mt8195-disp-color - enum: - mediatek,mt8173-disp-color reg: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml index 20419f876410..e89fe7393291 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml @@ -22,6 +22,11 @@ properties: oneOf: - items: - const: mediatek,mt8183-disp-dither + - items: + - enum: + - mediatek,mt8195-disp-dither + - enum: + - mediatek,mt8183-disp-dither reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml index e2a1fc218e4f..dc78d6d05dee 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml @@ -23,6 +23,11 @@ properties: - const: mediatek,mt8173-disp-gamma - items: - const: mediatek,mt8183-disp-gamma + - items: + - enum: + - mediatek,mt8195-disp-gamma + - enum: + - mediatek,mt8183-disp-gamma reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml index 4cdce11d7fcd..1a27b037086b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -21,6 +21,8 @@ properties: oneOf: - items: - const: mediatek,mt8173-disp-merge + - items: + - const: mediatek,mt8195-disp-merge reg: maxItems: 1 @@ -36,6 +38,31 @@ properties: clocks: items: - description: MERGE Clock + - description: MERGE Async Clock + Controlling the synchronous process between MERGE and other display function + blocks cross clock domain. + + mediatek,merge-fifo-en: + description: + The setting of merge fifo is mainly provided for the display latency buffer. +to ensure that the back-end panel display data will not be underrun, +a little more data is needed in the fifo. According to the merge fifo settings, +
[PATCH v7 01/13] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
1. There are 2 mmsys, namely vdosys0 and vdosys1 in mt8195. Each of them is bound to a display pipeline, so add their definition in mtk-mmsys documentation with 2 compatibles. 2. Add description for power-domain property. Signed-off-by: jason-jh.lin --- .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 8 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 2d4ff0ce387b..68cb330d7595 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -30,6 +30,8 @@ properties: - mediatek,mt8173-mmsys - mediatek,mt8183-mmsys - mediatek,mt8365-mmsys + - mediatek,mt8195-vdosys0 + - mediatek,mt8195-vdosys1 - const: syscon - items: - const: mediatek,mt7623-mmsys @@ -39,6 +41,12 @@ properties: reg: maxItems: 1 + power-domains: +description: + A phandle and PM domain specifier as defined by bindings + of the power controller specified by phandle. See + Documentation/devicetree/bindings/power/power-domain.yaml for details. + "#clock-cells": const: 1 -- 2.18.0
[PATCH v7 07/13] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
Add mtk-mutex support for mt8195 vdosys0. Signed-off-by: jason-jh.lin --- drivers/soc/mediatek/mtk-mutex.c | 93 ++-- 1 file changed, 90 insertions(+), 3 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 2e4bcc300576..cb8bbf7f3fd8 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -17,6 +17,9 @@ #define MT8183_MUTEX0_MOD0 0x30 #define MT8183_MUTEX0_SOF0 0x2c +#define MT8195_DISP_MUTEX0_MOD00x30 +#define MT8195_DISP_MUTEX0_SOF 0x2c + #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) @@ -67,6 +70,36 @@ #define MT8173_MUTEX_MOD_DISP_PWM1 24 #define MT8173_MUTEX_MOD_DISP_OD 25 +#define MT8195_MUTEX_MOD_DISP_OVL0 0 +#define MT8195_MUTEX_MOD_DISP_WDMA01 +#define MT8195_MUTEX_MOD_DISP_RDMA02 +#define MT8195_MUTEX_MOD_DISP_COLOR0 3 +#define MT8195_MUTEX_MOD_DISP_CCORR0 4 +#define MT8195_MUTEX_MOD_DISP_AAL0 5 +#define MT8195_MUTEX_MOD_DISP_GAMMA0 6 +#define MT8195_MUTEX_MOD_DISP_DITHER0 7 +#define MT8195_MUTEX_MOD_DISP_DSI0 8 +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 +#define MT8195_MUTEX_MOD_DISP_OVL1 10 +#define MT8195_MUTEX_MOD_DISP_WDMA111 +#define MT8195_MUTEX_MOD_DISP_RDMA112 +#define MT8195_MUTEX_MOD_DISP_COLOR1 13 +#define MT8195_MUTEX_MOD_DISP_CCORR1 14 +#define MT8195_MUTEX_MOD_DISP_AAL1 15 +#define MT8195_MUTEX_MOD_DISP_GAMMA1 16 +#define MT8195_MUTEX_MOD_DISP_DITHER1 17 +#define MT8195_MUTEX_MOD_DISP_DSI1 18 +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19 +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE20 +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22 +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23 +#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24 +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25 +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26 +#define MT8195_MUTEX_MOD_DISP_PWM0 27 +#define MT8195_MUTEX_MOD_DISP_PWM1 28 + #define MT2712_MUTEX_MOD_DISP_PWM2 10 #define MT2712_MUTEX_MOD_DISP_OVL0 11 #define MT2712_MUTEX_MOD_DISP_OVL1 12 @@ -101,12 +134,27 @@ #define MT2712_MUTEX_SOF_DSI3 6 #define MT8167_MUTEX_SOF_DPI0 2 #define MT8167_MUTEX_SOF_DPI1 3 + #define MT8183_MUTEX_SOF_DSI0 1 #define MT8183_MUTEX_SOF_DPI0 2 #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) +#define MT8195_MUTEX_SOF_DSI0 1 +#define MT8195_MUTEX_SOF_DSI1 2 +#define MT8195_MUTEX_SOF_DP_INTF0 3 +#define MT8195_MUTEX_SOF_DP_INTF1 4 +#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */ +#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */ + +#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7) +#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7) +#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7) +#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7) +#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7) +#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7) + struct mtk_mutex { int id; bool claimed; @@ -120,6 +168,9 @@ enum mtk_mutex_sof_id { MUTEX_SOF_DPI1, MUTEX_SOF_DSI2, MUTEX_SOF_DSI3, + MUTEX_SOF_DP_INTF0, + MUTEX_SOF_DP_INTF1, + DDP_MUTEX_SOF_MAX, }; struct mtk_mutex_data { @@ -214,7 +265,22 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, }; -static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { +static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0, + [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0, + [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0, + [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE, +
[PATCH v7 02/13] dt-bindings: mediatek: display: split each block to individual yaml
1. Remove mediatek,dislpay.txt 2. Split each display function block to individual yaml file Signed-off-by: jason-jh.lin --- .../display/mediatek/mediatek,aal.yaml| 75 ++ .../display/mediatek/mediatek,ccorr.yaml | 69 ++ .../display/mediatek/mediatek,color.yaml | 84 +++ .../display/mediatek/mediatek,disp.txt| 219 -- .../display/mediatek/mediatek,dither.yaml | 70 ++ .../display/mediatek/mediatek,gamma.yaml | 71 ++ .../display/mediatek/mediatek,merge.yaml | 57 + .../display/mediatek/mediatek,mutex.yaml | 77 ++ .../display/mediatek/mediatek,od.yaml | 52 + .../display/mediatek/mediatek,ovl-2l.yaml | 86 +++ .../display/mediatek/mediatek,ovl.yaml| 96 .../display/mediatek/mediatek,rdma.yaml | 110 + .../display/mediatek/mediatek,split.yaml | 56 + .../display/mediatek/mediatek,ufoe.yaml | 59 + .../display/mediatek/mediatek,wdma.yaml | 86 +++ 15 files changed, 1048 insertions(+), 219 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml new file mode 100644 index ..7be772d77e36 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: mediatek display adaptive ambient light processor + +maintainers: + - CK Hu + +description: | + The mediatek display adaptive ambient light processor, namely AAL, + is responsible for backlight power saving and sunlight visibility improving. + AAL device node must be siblings to the central MMSYS_CONFIG node. + For a description of the MMSYS_CONFIG binding, see + Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details. + +properties: + compatible: +oneOf: + - items: + - const: mediatek,mt8173-disp-aal + - items: + - enum: + - mediatek,mt2712-disp-aal + - mediatek,mt8183-disp-aal + - enum: + - mediatek,mt8173-disp-aal + + reg: +maxItems: 1 + + interrupts: +maxItems: 1 + + power-domains: +description: A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle. See + Documentation/devicetree/bindings/power/power-domain.yaml for details. + + clocks: +items: + - description: AAL Clock + + mediatek,gce-client-reg: +description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/include/dt-bindings/gce/-gce.h of each chips. +$ref: /schemas/types.yaml#/definitions/phandle-array +maxItems: 1 + +required: + - compatible + - reg + - interrupts + - power-domains + - clocks + +additionalProperties: false + +examples: + - | + +aal@14015000 { +compatible = "mediatek,mt8173-disp-aal"; +reg = <0 0x14015000 0 0x1000>; +interrupts = ; +power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; +clocks = <&mmsys CLK_MM_DISP_AAL>; +mediatek,gce-client-reg = <&gce SUBSYS_1401 0x5000 0x1000>; +}; + diff --git a/
[PATCH v2] drm: avoid races with modesetting rights
In drm_client_modeset.c and drm_fb_helper.c, drm_master_internal_{acquire,release} are used to avoid races with DRM userspace. These functions hold onto drm_device.master_mutex while committing, and bail if there's already a master. However, there are other places where modesetting rights can race. A time-of-check-to-time-of-use error can occur if an ioctl that changes the modeset has its rights revoked after it validates its permissions, but before it completes. There are four places where modesetting permissions can change: - DROP_MASTER ioctl removes rights for a master and its leases - REVOKE_LEASE ioctl revokes rights for a specific lease - SET_MASTER ioctl sets the device master if the master role hasn't been acquired yet - drm_open which can create a new master for a device if one does not currently exist These races can be avoided by flushing all users that might have seen old modesetting permissions before returning to userspace. We do this using rwsem: users that perform modesetting should hold a read lock on the new drm_device.master_rwsem, and users that change these permissions should flush these readers before returning to userspace. Reported-by: Daniel Vetter Signed-off-by: Desmond Cheong Zhi Xi --- Hi, I opted to leave the drm_master_unlock_and_flush helper out of this patch, but happy to add it in if it'd be useful. Imo, when comparing it with a mutex_unlock followed by drm_master_flush, it didn't add clarity. And since we don't always hold the drm_device.master_mutex before flushing (such as in drm_mode_revoke_lease_ioctl), perhaps it's better to stick with one method to flush readers with drm_master_flush. v1 -> v2 (suggested by Daniel Vetter): - Address an additional race when drm_open runs. - Switch from SRCU to rwsem to synchronise readers and writers. - Implement drm_master_flush with task_work so that flushes can be queued to run before returning to userspace without creating a new DRM_MASTER_FLUSH ioctl flag. Best wishes, Desmond drivers/gpu/drm/drm_auth.c | 45 - drivers/gpu/drm/drm_drv.c | 1 + drivers/gpu/drm/drm_ioctl.c | 9 +++- drivers/gpu/drm/drm_lease.c | 1 + include/drm/drm_auth.h | 1 + include/drm/drm_device.h| 18 +++ 6 files changed, 73 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c index 60a6b21474b1..175bc4d1e4b4 100644 --- a/drivers/gpu/drm/drm_auth.c +++ b/drivers/gpu/drm/drm_auth.c @@ -29,6 +29,7 @@ */ #include +#include #include #include @@ -282,6 +283,7 @@ int drm_setmaster_ioctl(struct drm_device *dev, void *data, drm_set_master(dev, file_priv, false); out_unlock: mutex_unlock(&dev->master_mutex); + drm_master_flush(dev); return ret; } @@ -321,8 +323,10 @@ int drm_dropmaster_ioctl(struct drm_device *dev, void *data, } drm_drop_master(dev, file_priv); + out_unlock: mutex_unlock(&dev->master_mutex); + drm_master_flush(dev); return ret; } @@ -344,6 +348,8 @@ int drm_master_open(struct drm_file *file_priv) } mutex_unlock(&dev->master_mutex); + drm_master_flush(dev); + return ret; } @@ -450,11 +456,15 @@ EXPORT_SYMBOL(drm_master_put); /* Used by drm_client and drm_fb_helper */ bool drm_master_internal_acquire(struct drm_device *dev) { + down_read(&dev->master_rwsem); + mutex_lock(&dev->master_mutex); if (dev->master) { mutex_unlock(&dev->master_mutex); + up_read(&dev->master_rwsem); return false; } + mutex_unlock(&dev->master_mutex); return true; } @@ -463,6 +473,39 @@ EXPORT_SYMBOL(drm_master_internal_acquire); /* Used by drm_client and drm_fb_helper */ void drm_master_internal_release(struct drm_device *dev) { - mutex_unlock(&dev->master_mutex); + up_read(&dev->master_rwsem); } EXPORT_SYMBOL(drm_master_internal_release); + +/* After flushing, all readers that might have seen old master/lease + * permissions are guaranteed to have completed. + */ +void master_flush(struct callback_head *cb) +{ + struct drm_device *dev = container_of(cb, struct drm_device, + master_flush_work); + + down_write(&dev->master_rwsem); + up_write(&dev->master_rwsem); +} + +/** + * drm_master_flush - queues work to flush readers of master/lease permissions + * before returning to userspace + * @dev: DRM device + * + * Queues up work to flush all readers of master/lease permissions. This work + * is run before this task returns to user mode. Calling this function when a + * task changes modesetting rights ensures that other processes that perform + * modesetting do not race with userspace. + */ +void drm_master_flush(struct drm_device *dev) +{ + init_task_work(&dev->master_flush_work, master_flush); + task_work_add(current, &dev->master_flush_wor
Re: [PATCH v2] drm: avoid races with modesetting rights
Hi Desmond, Thank you for the patch! Yet something to improve: [auto build test ERROR on next-20210813] [also build test ERROR on v5.14-rc5] [cannot apply to linus/master v5.14-rc5 v5.14-rc4 v5.14-rc3] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Desmond-Cheong-Zhi-Xi/drm-avoid-races-with-modesetting-rights/20210815-234145 base:4b358aabb93a2c654cd1dcab1a25a589f6e2b153 config: i386-randconfig-a004-20210815 (attached as .config) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 reproduce (this is a W=1 build): # https://github.com/0day-ci/linux/commit/cf6d8354b7d7953cd866fad004cbb189adfa074f git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Desmond-Cheong-Zhi-Xi/drm-avoid-races-with-modesetting-rights/20210815-234145 git checkout cf6d8354b7d7953cd866fad004cbb189adfa074f # save the attached .config to linux build tree make W=1 ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>, old ones prefixed by <<): >> ERROR: modpost: "task_work_add" [drivers/gpu/drm/drm.ko] undefined! --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org .config.gz Description: application/gzip
Re: [PATCH v2] drm: avoid races with modesetting rights
Hi Desmond, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on next-20210813] [also build test WARNING on v5.14-rc5] [cannot apply to linus/master v5.14-rc5 v5.14-rc4 v5.14-rc3] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Desmond-Cheong-Zhi-Xi/drm-avoid-races-with-modesetting-rights/20210815-234145 base:4b358aabb93a2c654cd1dcab1a25a589f6e2b153 config: arc-randconfig-r031-20210815 (attached as .config) compiler: arceb-elf-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/cf6d8354b7d7953cd866fad004cbb189adfa074f git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Desmond-Cheong-Zhi-Xi/drm-avoid-races-with-modesetting-rights/20210815-234145 git checkout cf6d8354b7d7953cd866fad004cbb189adfa074f # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=arc If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All warnings (new ones prefixed by >>): >> drivers/gpu/drm/drm_auth.c:483:6: warning: no previous prototype for >> 'master_flush' [-Wmissing-prototypes] 483 | void master_flush(struct callback_head *cb) | ^~~~ vim +/master_flush +483 drivers/gpu/drm/drm_auth.c 479 480 /* After flushing, all readers that might have seen old master/lease 481 * permissions are guaranteed to have completed. 482 */ > 483 void master_flush(struct callback_head *cb) 484 { 485 struct drm_device *dev = container_of(cb, struct drm_device, 486master_flush_work); 487 488 down_write(&dev->master_rwsem); 489 up_write(&dev->master_rwsem); 490 } 491 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org .config.gz Description: application/gzip
[Bug 205089] amdgpu : drm:amdgpu_cs_ioctl : Failed to initialize parser -125
https://bugzilla.kernel.org/show_bug.cgi?id=205089 ctjans...@protonmail.com changed: What|Removed |Added CC||ctjans...@protonmail.com --- Comment #19 from ctjans...@protonmail.com --- I just triggered this bug aswell playing Payday 2. I have also triggered this bug when playing World of Warcraft in june. OS: EndeavourOS Linux x86_64 Kernel: 5.13.10-arch1-1 Mesa: 21.1.6 DE: GNOME 40.3 CPU: Ryzen 9 5900X GPU: RX 6800 XT -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.
[PATCH] drm/radeon: Add break to switch statement in radeonfb_create_pinned_object()
Clang + -Wimplicit-fallthrough warns: drivers/gpu/drm/radeon/radeon_fb.c:170:2: warning: unannotated fall-through between switch labels [-Wimplicit-fallthrough] default: ^ drivers/gpu/drm/radeon/radeon_fb.c:170:2: note: insert 'break;' to avoid fall-through default: ^ break; 1 warning generated. Clang's version of this warning is a little bit more pedantic than GCC's. Add the missing break to satisfy it to match what has been done all over the kernel tree. Signed-off-by: Nathan Chancellor --- drivers/gpu/drm/radeon/radeon_fb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c index 0b206b052972..c8b545181497 100644 --- a/drivers/gpu/drm/radeon/radeon_fb.c +++ b/drivers/gpu/drm/radeon/radeon_fb.c @@ -167,6 +167,7 @@ static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev, break; case 2: tiling_flags |= RADEON_TILING_SWAP_16BIT; + break; default: break; } base-commit: ba31f97d43be41ca99ab72a6131d7c226306865f -- 2.33.0.rc2
Re: [PATCH v6 02/13] mm: remove extra ZONE_DEVICE struct page refcount
On 8/15/21 8:37 AM, Christoph Hellwig wrote: diff --git a/include/linux/mm.h b/include/linux/mm.h index 8ae31622deef..d48a1f0889d1 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -1218,7 +1218,7 @@ __maybe_unused struct page *try_grab_compound_head(struct page *page, int refs, static inline __must_check bool try_get_page(struct page *page) { page = compound_head(page); - if (WARN_ON_ONCE(page_ref_count(page) <= 0)) + if (WARN_ON_ONCE(page_ref_count(page) < (int)!is_zone_device_page(page))) Please avoid the overly long line. In fact I'd be tempted to just not bother here and keep the old, more lose check. Especially given that John has a patch ready that removes try_get_page entirely. Yes. Andrew has accepted it into mmotm. Ralph's patch here was written well before my cleanup that removed try_grab_page() [1]. But now that we're here, if you drop this hunk then it will make merging easier, I think. [1] https://lore.kernel.org/r/20210813044133.1536842-4-jhubb...@nvidia.com thanks, -- John Hubbard NVIDIA
[GIT PULL] mediatek drm next for 5.15
Hi, Dave & Daniel: This includes: 1. MT8133 AAL support, adjust rdma fifo threshold formula. 2. Implement mmap as GEM object function. 3. Add support for MT8167. 4. Test component initialization earlier in the function mtk_drm_crtc_create. 5. CMDQ refinement. Regards, Chun-Kuang. The following changes since commit e73f0f0ee7541171d89f2e2491130c7771ba58d3: Linux 5.14-rc1 (2021-07-11 15:07:40 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git tags/mediatek-drm-next-5.15 for you to fetch changes up to 6e7dcd92644baebdb137e3af900064ceebcaca23: drm/mediatek: Clear pending flag when cmdq packet is done (2021-08-12 08:16:24 +0800) Mediatek DRM Next for Linux 5.15 1. MT8133 AAL support, adjust rdma fifo threshold formula. 2. Implement mmap as GEM object function. 3. Add support for MT8167. 4. Test component initialization earlier in the function mtk_drm_crtc_create. 5. CMDQ refinement. Chun-Kuang Hu (4): drm/mediatek: Use mailbox rx_callback instead of cmdq_task_cb drm/mediatek: Remove struct cmdq_client drm/mediatek: Detect CMDQ execution timeout drm/mediatek: Add cmdq_handle in mtk_crtc Dafna Hirschfeld (1): drm/mediatek: Test component initialization earlier in the function mtk_drm_crtc_create Fabien Parent (2): dt-bindings: display: mediatek: dsi: add documentation for MT8167 SoC drm/mediatek: Add support for main DDP path on MT8167 Thomas Zimmermann (1): drm/mediatek: Implement mmap as GEM object function Yongqiang Niu (4): drm/mediatek: Adjust rdma fifo threshold calculate formula drm/mediatek: Separate aal sub driver drm/mediatek: Add mt8183 aal support drm/mediatek: Clear pending flag when cmdq packet is done .../bindings/display/mediatek/mediatek,dsi.txt | 2 +- drivers/gpu/drm/mediatek/Makefile | 3 +- drivers/gpu/drm/mediatek/mtk_disp_aal.c| 167 drivers/gpu/drm/mediatek/mtk_disp_drv.h| 9 ++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +- drivers/gpu/drm/mediatek/mtk_drm_crtc.c| 173 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c| 42 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 59 +-- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_gem.c | 44 ++ drivers/gpu/drm/mediatek/mtk_drm_gem.h | 3 - 11 files changed, 386 insertions(+), 123 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_aal.c
Re: [PATCH v2 07/14] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
Hi Matthias, Thanks for the review. On Fri, 2021-08-06 at 14:20 +0200, Matthias Brugger wrote: > > On 28/07/2021 07:34, Nancy.Lin wrote: > > Hi Enric, > > > > Thanks for your review. > > > > On Fri, 2021-07-23 at 13:05 +0200, Enric Balletbo Serra wrote: > > > Hi Nancy, > > > > > > Thank you for your patch. > > > > > > Missatge de Nancy.Lin del dia dj., 22 de > > > jul. > > > 2021 a les 11:45: > > > > > > > > Add mt8195 vdosys1 clock driver name and routing table to > > > > the driver data of mtk-mmsys. > > > > > > > > Signed-off-by: Nancy.Lin > > > > --- > > > > drivers/soc/mediatek/mt8195-mmsys.h| 83 > > > > -- > > > > drivers/soc/mediatek/mtk-mmsys.c | 10 > > > > include/linux/soc/mediatek/mtk-mmsys.h | 2 + > > > > 3 files changed, 90 insertions(+), 5 deletions(-) > > > > > > > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h > > > > b/drivers/soc/mediatek/mt8195-mmsys.h > > > > index 73e9e8286d50..104ba575f765 100644 > > > > --- a/drivers/soc/mediatek/mt8195-mmsys.h > > > > +++ b/drivers/soc/mediatek/mt8195-mmsys.h > > > > @@ -64,16 +64,16 @@ > > > > #define > > > > SOUT_TO_VPP_MERGE0_P1_SEL (1 > > > > << 0) > > > > > > > > #define > > > > MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40 > > > > -#define > > > > SOUT_TO_HDR_VDO_FE0(0 > > > > << 0) > > > > > > This definition was introduced in this patch [1] that didn't land > > > yet. > > > And you're removing it now. Could you sync with Jason and only > > > introduce the bits that are needed for your patches. Also all the > > > comments I made to the Jason's patch apply here. > > > > > > [1] > > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210723090233.24007-3-jason-jh@mediatek.com/__;!!CTRNKA9wMg0ARbw!0rDdPxfBPcZC9icK37sCxT55RMqwRngO0BF4-uDwgYZP7UwQkx7iidkINqLBb7yi$ > > > > > > > > > > OK, I will sync with Jason and modify it. > > > > > > +#define > > > > SOUT_TO_MIXER_IN1_SEL (1 > > > > << 0) > > > > > > > > #define > > > > MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44 > > > > -#define > > > > SOUT_TO_HDR_VDO_FE1(0 > > > > << 0) > > > > +#define > > > > SOUT_TO_MIXER_IN2_SEL (1 > > > > << 0) > > > > > > > > #define > > > > MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48 > > > > -#define > > > > SOUT_TO_HDR_GFX_FE0(0 > > > > << 0) > > > > +#define > > > > SOUT_TO_MIXER_IN3_SEL (1 > > > > << 0) > > > > > > > > #define > > > > MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c > > > > -#define > > > > SOUT_TO_HDR_GFX_FE1(0 > > > > << 0) > > > > +#define > > > > SOUT_TO_MIXER_IN4_SEL (1 > > > > << 0) > > > > > > > > #define > > > > MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58 > > > > #define > > > > MIXER_IN1_SOUT_TO_DISP_MIXER (0 > > > > << 0) > > > > @@ -88,7 +88,7 @@ > > > > #define > > > > MIXER_IN4_SOUT_TO_DISP_MIXER (0 > > > > << 0) > > > > > > > > #define > > > > MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34 > > > > -#define > > > > MIXER_SOUT_TO_HDR_VDO_BE0 (0 > > > > << 0) > > > > +#define > > > > MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 > > > > << 0) > > > > > > > > #define > > > > MT8195_VDO1_MERGE4_SOUT_SEL0xf18 > > > > #define > > > > MERGE4_SOUT_TO_VDOSYS0 (0 > > > > << 0) > > > > @@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes > > > > mmsys_mt8195_routing_table[] = { > > > > }, { > > > > DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, > > > > MT8195_VDO0_SEL_OUT, > > > > SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE > > > > + }, > > > > + { > > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5, > > > > + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, > > > > VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 > > > > + }, > > > > + { > > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5, > > > > + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, > > > > VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 > > > > + }, > > > > + { > > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5, > > > > + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, > > > > VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 > > > > + }, > > > > + { > > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5, > > > > + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, > > > > SOUT_TO_MIXER_IN1_SEL > > > > + }, > > > > + { > > > > + DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_MERGE5, > > > >
Re: [PATCH v2 08/14] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
Hi Matthias, Thanks for the review. On Fri, 2021-08-06 at 17:30 +0200, Matthias Brugger wrote: > > On 22/07/2021 11:45, Nancy.Lin wrote: > > Add mmsys config API. > > This patch is doing a lot of things, it adds a "config" and it adds > cmdq > support. Please explain better in the commit message what the config > is for. > Please add comments to the different values of struct > mtk_mmsys_config. > OK, I will explain in more detail in the commit message. > I understand that cmdq is optional, so please make addition to cmdq a > separate > patch. OK, I will add cmdq support in another patch. > I'm a bit puzzled about that fact, can you please explain who you get > the HW to > behave the same way when you write the same value and offset to > mmsys-regs and > via cmdq. > > Thanks, > Matthias The mmsys config register settings need to take effect with the other HW settings(like OVL_ADAPTOR...) at the same vblanking time. If we use CPU to write the mmsys reg, we can't guarantee all the settings can be written in the same vblanking time. Cmdq is used for this purpose. We prepare all the related HW settings in one cmdq packet. The first command in the packet is "wait stream done", and then following with all the HW settings. After the cmdq packet is flush to GCE HW. The GCE waits for the "stream done event" to coming and then starts flushing all the HW settings. This can guarantee all the settings flush in the same vblanking. Regards, Nancy > > > > Signed-off-by: Nancy.Lin > > --- > > drivers/soc/mediatek/mt8195-mmsys.h| 38 > > drivers/soc/mediatek/mtk-mmsys.c | 50 > > ++ > > drivers/soc/mediatek/mtk-mmsys.h | 10 ++ > > include/linux/soc/mediatek/mtk-mmsys.h | 18 ++ > > 4 files changed, 116 insertions(+) > > > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h > > b/drivers/soc/mediatek/mt8195-mmsys.h > > index 104ba575f765..4bdb2087250c 100644 > > --- a/drivers/soc/mediatek/mt8195-mmsys.h > > +++ b/drivers/soc/mediatek/mt8195-mmsys.h > > @@ -154,6 +154,18 @@ > > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << > > 0) > > #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << > > 0) > > > > +#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD0xe30 > > +#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD0xe40 > > +#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD0xe50 > > +#define MT8195_VDO1_MERGE3_ASYNC_CFG_WD0xe60 > > +#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70 > > +#define MT8195_VDO1_HDR_TOP_CFG0xd00 > > +#define MT8195_VDO1_MIXER_IN1_ALPHA0xd30 > > +#define MT8195_VDO1_MIXER_IN2_ALPHA0xd34 > > +#define MT8195_VDO1_MIXER_IN3_ALPHA0xd38 > > +#define MT8195_VDO1_MIXER_IN4_ALPHA0xd3c > > +#define MT8195_VDO1_MIXER_IN4_PAD 0xd4c > > + > > static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] > > = { > > { > > DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, > > @@ -261,4 +273,30 @@ static const struct mtk_mmsys_routes > > mmsys_mt8195_routing_table[] = { > > } > > }; > > > > +static const struct mtk_mmsys_config mmsys_mt8195_config_table[] = > > { > > + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0, > > MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0}, > > + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0, > > MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16}, > > + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1, > > MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0}, > > + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1, > > MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16}, > > + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2, > > MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0}, > > + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2, > > MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16}, > > + { MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3, > > MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0}, > > + { MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3, > > MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16}, > > + { MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0, > > MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0}, > > + { MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0, > > MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16}, > > + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1, > > MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0}, > > + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1, > > MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16}, > > + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2, > > MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0}, > > + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2, > > MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16}, > > + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3, > > MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0}, > > + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3, > > MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16}, > > + { MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4, > > MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0}, > > + { MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4, > > MT8195_VDO1_MIXER_IN4_ALPHA, GENMAS
Re: [PATCH] drm/amdgpu: Cancel delayed work when GFXOFF is disabled
On 8/13/2021 9:30 PM, Michel Dänzer wrote: On 2021-08-13 5:07 p.m., Lazar, Lijo wrote: On 8/13/2021 8:10 PM, Michel Dänzer wrote: On 2021-08-13 4:14 p.m., Lazar, Lijo wrote: On 8/13/2021 7:04 PM, Michel Dänzer wrote: On 2021-08-13 1:50 p.m., Lazar, Lijo wrote: On 8/13/2021 3:59 PM, Michel Dänzer wrote: From: Michel Dänzer schedule_delayed_work does not push back the work if it was already scheduled before, so amdgpu_device_delay_enable_gfx_off ran ~100 ms after the first time GFXOFF was disabled and re-enabled, even if GFXOFF was disabled and re-enabled again during those 100 ms. This resulted in frame drops / stutter with the upcoming mutter 41 release on Navi 14, due to constantly enabling GFXOFF in the HW and disabling it again (for getting the GPU clock counter). To fix this, call cancel_delayed_work_sync when GFXOFF transitions from enabled to disabled. This makes sure the delayed work will be scheduled as intended in the reverse case. In order to avoid a deadlock, amdgpu_device_delay_enable_gfx_off needs to use mutex_trylock instead of mutex_lock. v2: * Use cancel_delayed_work_sync & mutex_trylock instead of mod_delayed_work. Signed-off-by: Michel Dänzer --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 11 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 13 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 3 +++ 3 files changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index f3fd5ec710b6..8b025f70706c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2777,7 +2777,16 @@ static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) struct amdgpu_device *adev = container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work); - mutex_lock(&adev->gfx.gfx_off_mutex); + /* mutex_lock could deadlock with cancel_delayed_work_sync in amdgpu_gfx_off_ctrl. */ + if (!mutex_trylock(&adev->gfx.gfx_off_mutex)) { + /* If there's a bug which causes amdgpu_gfx_off_ctrl to be called with enable=true + * when adev->gfx.gfx_off_req_count is already 0, we might race with that. + * Re-schedule to make sure gfx off will be re-enabled in the HW eventually. + */ + schedule_delayed_work(&adev->gfx.gfx_off_delay_work, AMDGPU_GFX_OFF_DELAY_ENABLE); + return; This is not needed and is just creating another thread to contend for mutex. Still not sure what you mean by that. What other thread? Sorry, I meant it schedules another workitem and delays GFXOFF enablement further. For ex: if it was another function like gfx_off_status holding the lock at the time of check. The checks below take care of enabling gfxoff correctly. If it's already in gfx_off state, it doesn't do anything. So I don't see why this change is needed. mutex_trylock is needed to prevent the deadlock discussed before and below. schedule_delayed_work is needed due to this scenario hinted at by the comment: 1. amdgpu_gfx_off_ctrl locks mutex, calls schedule_delayed_work 2. amdgpu_device_delay_enable_gfx_off runs, calls mutex_trylock, which fails GFXOFF would never get re-enabled in HW in this case (until amdgpu_gfx_off_ctrl calls schedule_delayed_work again). (cancel_delayed_work_sync guarantees there's no pending delayed work when it returns, even if amdgpu_device_delay_enable_gfx_off calls schedule_delayed_work) I think we need to explain based on the original code before. There is an asssumption here that the only other contention of this mutex is with the gfx_off_ctrl function. Not really. As far as I understand if the work has already started running when schedule_delayed_work is called, it will insert another in the work queue after delay. Based on that understanding I didn't find a problem with the original code. Original code as in without this patch or the mod_delayed_work patch? If so, the problem is not when the work has already started running. It's that when it hasn't started running yet, schedule_delayed_work doesn't change the timeout for the already scheduled work, so it ends up enabling GFXOFF earlier than intended (and thus at all in scenarios when it's not supposed to). I meant the original implementation of amdgpu_device_delay_enable_gfx_off(). If you indeed want to use _sync, there is a small problem with this implementation also which is roughly equivalent to the original problem you faced. amdgpu_gfx_off_ctrl(disable) locks mutex calls cancel_delayed_work_sync amdgpu_device_delay_enable_gfx_off already started running mutex_trylock fails and schedules another one amdgpu_gfx_off_ctrl(enable) schedules_delayed_work() - Delay is not extended, it's the same as when it's rearmed from work item. This cannot happen. When cancel_delayed_work_sync returns, it guarantees that
Re: Why we didn't use embedded gem object for virtio gpu when making ttm bo a gem bo subclass?
On Fri, Aug 13, 2021 at 12:42:51PM -0700, lepton wrote: > Hi Gerd, > > We found a bug in 5.4 kernel and virtgpu_gem_prime_mmap doesn't work > because it references vma_node in gem_base object while ttm code > initialized vma_node in tbo.base object. I am wondering, in your > original serial: > https://patchwork.kernel.org/project/dri-devel/cover/20190805124310.3275-1-kra...@redhat.com/ > (drm/ttm: make ttm bo a gem bo subclass), why you changed to use > embedded gem object for most gpu drivers but skipping virtio gpu? Is > there some specific reason? commit c66df701e783bc666593e6e665f13670760883ee Author: Gerd Hoffmann Date: Thu Aug 29 12:32:57 2019 +0200 drm/virtio: switch from ttm to gem shmem helpers HTH, Gerd
Re: Why we didn't use embedded gem object for virtio gpu when making ttm bo a gem bo subclass?
Hi Gerd, Thanks for your reply. I was aware of that change, but need a fix for 5.4 kernel as a temp solution for now. If the reason is just that you will move away from ttm soon,then I guess a CL like http://crrev.com/c/3092457 should work for 5.4, just hope I don't miss anything else. Thanks! On Sun, Aug 15, 2021 at 9:46 PM Gerd Hoffmann wrote: > > On Fri, Aug 13, 2021 at 12:42:51PM -0700, lepton wrote: > > Hi Gerd, > > > > We found a bug in 5.4 kernel and virtgpu_gem_prime_mmap doesn't work > > because it references vma_node in gem_base object while ttm code > > initialized vma_node in tbo.base object. I am wondering, in your > > original serial: > > https://patchwork.kernel.org/project/dri-devel/cover/20190805124310.3275-1-kra...@redhat.com/ > > (drm/ttm: make ttm bo a gem bo subclass), why you changed to use > > embedded gem object for most gpu drivers but skipping virtio gpu? Is > > there some specific reason? > > commit c66df701e783bc666593e6e665f13670760883ee > Author: Gerd Hoffmann > Date: Thu Aug 29 12:32:57 2019 +0200 > > drm/virtio: switch from ttm to gem shmem helpers > > HTH, > Gerd >
Re: Why we didn't use embedded gem object for virtio gpu when making ttm bo a gem bo subclass?
On Sun, Aug 15, 2021 at 09:51:02PM -0700, lepton wrote: > Hi Gerd, > > Thanks for your reply. I was aware of that change, but need a fix for > 5.4 kernel as a temp solution for now. > If the reason is just that you will move away from ttm soon,then I > guess a CL like http://crrev.com/c/3092457 should > work for 5.4, just hope I don't miss anything else. Looks sane on a quick glance. take care, Gerd
Re: [PATCH 1/1] drm: ttm: Don't bail from ttm_global_init if debugfs_create_dir fails
On Wed, Aug 11, 2021 at 03:59:06AM +0800, Dan Moulding wrote: > In 69de4421bb4c ("drm/ttm: Initialize debugfs from > ttm_global_init()"), ttm_global_init was changed so that if creation > of the debugfs global root directory fails, ttm_global_init will bail > out early and return an error, leading to initialization failure of > DRM drivers. However, not every system will be using debugfs. On such > a system, debugfs directory creation can be expected to fail, but DRM > drivers must still be usable. This changes it so that if creation of > TTM's debugfs root directory fails, then no biggie: keep calm and > carry on. > > Fixes: 69de4421bb4c ("drm/ttm: Initialize debugfs from ttm_global_init()") > Signed-off-by: Dan Moulding It looks ok for me. Reviewed-by: Huang Rui Thanks, Ray > --- > drivers/gpu/drm/ttm/ttm_device.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/gpu/drm/ttm/ttm_device.c > b/drivers/gpu/drm/ttm/ttm_device.c > index 74e3b460132b..2df59b3c2ea1 100644 > --- a/drivers/gpu/drm/ttm/ttm_device.c > +++ b/drivers/gpu/drm/ttm/ttm_device.c > @@ -78,9 +78,7 @@ static int ttm_global_init(void) > > ttm_debugfs_root = debugfs_create_dir("ttm", NULL); > if (IS_ERR(ttm_debugfs_root)) { > - ret = PTR_ERR(ttm_debugfs_root); > ttm_debugfs_root = NULL; > - goto out; > } > > /* Limit the number of pages in the pool to about 50% of the total > -- > 2.31.1 >
Re: [GIT PULL] mediatek drm next for 5.15
CC [M] drivers/gpu/drm/mediatek/mtk_disp_aal.o /home/airlied/devel/kernel/dim/src/drivers/gpu/drm/mediatek/mtk_drm_crtc.c:257:13: warning: ‘mtk_drm_cmdq_pkt_destroy’ defined but not used [-Wunused-function] 257 | static void mtk_drm_cmdq_pkt_destroy(struct mbox_chan *chan, struct cmdq_pkt *pkt) | ^~~~ /home/airlied/devel/kernel/dim/src/drivers/gpu/drm/mediatek/mtk_drm_crtc.c:229:12: warning: ‘mtk_drm_cmdq_pkt_create’ defined but not used [-Wunused-function] 229 | static int mtk_drm_cmdq_pkt_create(struct mbox_chan *chan, struct cmdq_pkt *pkt, |^~~ LD [M] drivers/gpu/drm/mediatek/mediatek-drm.o Warning when built with CONFIG_MTK_CMDQ turned off. Can you please fix that and resend? Dave. On Mon, 16 Aug 2021 at 09:55, Chun-Kuang Hu wrote: > > Hi, Dave & Daniel: > > This includes: > > 1. MT8133 AAL support, adjust rdma fifo threshold formula. > 2. Implement mmap as GEM object function. > 3. Add support for MT8167. > 4. Test component initialization earlier in the function mtk_drm_crtc_create. > 5. CMDQ refinement. > > Regards, > Chun-Kuang. > > > The following changes since commit e73f0f0ee7541171d89f2e2491130c7771ba58d3: > > Linux 5.14-rc1 (2021-07-11 15:07:40 -0700) > > are available in the Git repository at: > > https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git > tags/mediatek-drm-next-5.15 > > for you to fetch changes up to 6e7dcd92644baebdb137e3af900064ceebcaca23: > > drm/mediatek: Clear pending flag when cmdq packet is done (2021-08-12 > 08:16:24 +0800) > > > Mediatek DRM Next for Linux 5.15 > > 1. MT8133 AAL support, adjust rdma fifo threshold formula. > 2. Implement mmap as GEM object function. > 3. Add support for MT8167. > 4. Test component initialization earlier in the function mtk_drm_crtc_create. > 5. CMDQ refinement. > > > Chun-Kuang Hu (4): > drm/mediatek: Use mailbox rx_callback instead of cmdq_task_cb > drm/mediatek: Remove struct cmdq_client > drm/mediatek: Detect CMDQ execution timeout > drm/mediatek: Add cmdq_handle in mtk_crtc > > Dafna Hirschfeld (1): > drm/mediatek: Test component initialization earlier in the function > mtk_drm_crtc_create > > Fabien Parent (2): > dt-bindings: display: mediatek: dsi: add documentation for MT8167 SoC > drm/mediatek: Add support for main DDP path on MT8167 > > Thomas Zimmermann (1): > drm/mediatek: Implement mmap as GEM object function > > Yongqiang Niu (4): > drm/mediatek: Adjust rdma fifo threshold calculate formula > drm/mediatek: Separate aal sub driver > drm/mediatek: Add mt8183 aal support > drm/mediatek: Clear pending flag when cmdq packet is done > > .../bindings/display/mediatek/mediatek,dsi.txt | 2 +- > drivers/gpu/drm/mediatek/Makefile | 3 +- > drivers/gpu/drm/mediatek/mtk_disp_aal.c| 167 > drivers/gpu/drm/mediatek/mtk_disp_drv.h| 9 ++ > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +- > drivers/gpu/drm/mediatek/mtk_drm_crtc.c| 173 > + > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c| 42 + > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 59 +-- > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + > drivers/gpu/drm/mediatek/mtk_drm_gem.c | 44 ++ > drivers/gpu/drm/mediatek/mtk_drm_gem.h | 3 - > 11 files changed, 386 insertions(+), 123 deletions(-) > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_aal.c
Re: [PATCH] drivers:gpu:drm:amd:amdgpu:fix a potential use-after-free
Am 13.08.21 um 05:28 schrieb lwt105: in line 1503, "dma_fence_put(fence);" drop the reference to fence and may cause fence to be released. However, fence is used subsequently in line 1510 "fence->error". This may result in an use-after-free bug. It can be fixed by recording fence->error in an variable before dropping the reference to fence and referencing it after dropping. Signed-off-by: lwt105 <3061522...@qq.com> Good catch. --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 30fa1f61e0e5..99d03180e113 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1486,7 +1486,7 @@ static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev, struct drm_amdgpu_fence *fences) { uint32_t fence_count = wait->in.fence_count; - unsigned int i; + unsigned int i, error; long r = 1; Would be nice to have if you could reuse the "r" variable here instead of a new one. Regards, Christian. for (i = 0; i < fence_count; i++) { @@ -1500,6 +1500,7 @@ static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev, continue; r = dma_fence_wait_timeout(fence, true, timeout); + error = fence->error; dma_fence_put(fence); if (r < 0) return r; @@ -1507,8 +1508,8 @@ static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev, if (r == 0) break; - if (fence->error) - return fence->error; + if (error) + return error; } memset(wait, 0, sizeof(*wait));
Re: [PATCH v2] drm: avoid races with modesetting rights
On 16/8/21 2:47 am, kernel test robot wrote: Hi Desmond, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on next-20210813] [also build test WARNING on v5.14-rc5] [cannot apply to linus/master v5.14-rc5 v5.14-rc4 v5.14-rc3] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Desmond-Cheong-Zhi-Xi/drm-avoid-races-with-modesetting-rights/20210815-234145 base:4b358aabb93a2c654cd1dcab1a25a589f6e2b153 config: arc-randconfig-r031-20210815 (attached as .config) compiler: arceb-elf-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/cf6d8354b7d7953cd866fad004cbb189adfa074f git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Desmond-Cheong-Zhi-Xi/drm-avoid-races-with-modesetting-rights/20210815-234145 git checkout cf6d8354b7d7953cd866fad004cbb189adfa074f # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=arc If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All warnings (new ones prefixed by >>): drivers/gpu/drm/drm_auth.c:483:6: warning: no previous prototype for 'master_flush' [-Wmissing-prototypes] 483 | void master_flush(struct callback_head *cb) | ^~~~ My bad, this should have been declared with static. I'll add it in, thanks. vim +/master_flush +483 drivers/gpu/drm/drm_auth.c 479 480 /* After flushing, all readers that might have seen old master/lease 481 * permissions are guaranteed to have completed. 482 */ > 483 void master_flush(struct callback_head *cb) 484 { 485 struct drm_device *dev = container_of(cb, struct drm_device, 486 master_flush_work); 487 488 down_write(&dev->master_rwsem); 489 up_write(&dev->master_rwsem); 490 } 491 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
Re: [PATCH 0/1] Fix DRM driver initialization failure in kernel v5.14
On Sat, Aug 14, 2021 at 12:50:14AM +0800, Dan Moulding wrote: > Just a friendly reminder that this fix for a regression needs > review. It should be a quick review. > > It would probably be good to ensure this gets in before the final 5.14 > release, otherwise this is going to be a very visible regression for > anyone that uses DRM and does not use debugfs. > Just took a look at your patch, it's ok for me. Alex/Christian, could you help to apply this fix if you have no concern? Best Regards, Ray
[PATCH] drm/fb: Fix randconfig builds
From: Jackie Liu When CONFIG_DRM_FBDEV_EMULATION is compiled to y and CONFIG_FB is m, the compilation will fail. we need make that dependency explicit. Reported-by: k2ci Signed-off-by: Jackie Liu --- drivers/gpu/drm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 7ff89690a976..346a518b5119 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -98,7 +98,7 @@ config DRM_DEBUG_DP_MST_TOPOLOGY_REFS config DRM_FBDEV_EMULATION bool "Enable legacy fbdev support for your modesetting driver" depends on DRM - depends on FB + select FB select DRM_KMS_HELPER select FB_CFB_FILLRECT select FB_CFB_COPYAREA -- 2.25.1