date:20210128

From: zhangxuezhi 

For st7789v ic,add tearing signal detect to avoid screen tearing

Signed-off-by: zhangxuezhi 
---
v9: change pr_* to dev_*
---
 drivers/staging/fbtft/fb_st7789v.c | 132 -
 drivers/staging/fbtft/fbtft.h  |   1 +
 2 files changed, 132 insertions(+), 1 deletion(-)

diff --git a/drivers/staging/fbtft/fb_st7789v.c 
b/drivers/staging/fbtft/fb_st7789v.c
index 3a280cc..9aa2f36 100644
--- a/drivers/staging/fbtft/fb_st7789v.c
+++ b/drivers/staging/fbtft/fb_st7789v.c
@@ -9,9 +9,12 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #include 
 #include 
-
+#include 
 #include "fbtft.h"
 
 #define DRVNAME "fb_st7789v"
@@ -66,6 +69,32 @@ enum st7789v_command {
 #define MADCTL_MX BIT(6) /* bitmask for column address order */
 #define MADCTL_MY BIT(7) /* bitmask for page address order */
 
+#define SPI_PANEL_TE_TIMEOUT   400
+static struct mutex te_mutex;/*mutex for tearing line*/
+static struct completion spi_panel_te;
+
+static irqreturn_t spi_panel_te_handler(int irq, void *data)
+{
+   complete(&spi_panel_te);
+   return IRQ_HANDLED;
+}
+
+static void set_spi_panel_te_irq_status(struct fbtft_par *par, bool enable)
+{
+   static int te_irq_count;
+
+   mutex_lock(&te_mutex);
+
+   if (enable) {
+   if (++te_irq_count == 1)
+   enable_irq(gpiod_to_irq(par->gpio.te));
+   } else {
+   if (--te_irq_count == 0)
+   disable_irq(gpiod_to_irq(par->gpio.te));
+   }
+   mutex_unlock(&te_mutex);
+}
+
 /**
  * init_display() - initialize the display controller
  *
@@ -82,6 +111,33 @@ enum st7789v_command {
  */
 static int init_display(struct fbtft_par *par)
 {
+   int rc;
+   struct device *dev = par->info->device;
+
+   par->gpio.te = devm_gpiod_get_index_optional(dev, "te", 0, GPIOD_IN);
+   if (IS_ERR(par->gpio.te)) {
+   rc = PTR_ERR(par->gpio.te);
+   dev_err(par->info->device, "Failed to request te gpio: %d\n", 
rc);
+   return rc;
+   }
+   if (par->gpio.te) {
+   init_completion(&spi_panel_te);
+   mutex_init(&te_mutex);
+   rc = devm_request_irq(dev,
+ gpiod_to_irq(par->gpio.te),
+spi_panel_te_handler, IRQF_TRIGGER_RISING,
+"TE_GPIO", par);
+   if (rc) {
+   dev_err(par->info->device, "TE request_irq failed.\n");
+   devm_gpiod_put(dev, par->gpio.te);
+   return rc;
+   }
+
+   disable_irq_nosync(gpiod_to_irq(par->gpio.te));
+   } else {
+   dev_info(par->info->device, "%s:%d, TE gpio not specified\n",
+__func__, __LINE__);
+   }
/* turn off sleep mode */
write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE);
mdelay(120);
@@ -137,6 +193,9 @@ static int init_display(struct fbtft_par *par)
 */
write_reg(par, PWCTRL1, 0xA4, 0xA1);
 
+/*Tearing Effect Line On*/
+   if (par->gpio.te)
+   write_reg(par, 0x35, 0x00);
write_reg(par, MIPI_DCS_SET_DISPLAY_ON);
 
if (HSD20_IPS)
@@ -145,6 +204,76 @@ static int init_display(struct fbtft_par *par)
return 0;
 }
 
+/*
+ *
+ *   int (*write_vmem)(struct fbtft_par *par);
+ *
+ */
+
+/* 16 bit pixel over 8-bit databus */
+static int st7789v_write_vmem16_bus8(struct fbtft_par *par, size_t offset, 
size_t len)
+{
+   u16 *vmem16;
+   __be16 *txbuf16 = par->txbuf.buf;
+   size_t remain;
+   size_t to_copy;
+   size_t tx_array_size;
+   int i;
+   int ret = 0;
+   size_t startbyte_size = 0;
+
+   fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "st7789v ---%s(offset=%zu, 
len=%zu)\n",
+ __func__, offset, len);
+
+   remain = len / 2;
+   vmem16 = (u16 *)(par->info->screen_buffer + offset);
+
+   if (par->gpio.dc)
+   gpiod_set_value(par->gpio.dc, 1);
+
+   /* non buffered write */
+   if (!par->txbuf.buf)
+   return par->fbtftops.write(par, vmem16, len);
+
+   /* buffered write */
+   tx_array_size = par->txbuf.len / 2;
+
+   if (par->startbyte) {
+   txbuf16 = par->txbuf.buf + 1;
+   tx_array_size -= 2;
+   *(u8 *)(par->txbuf.buf) = par->startbyte | 0x2;
+   startbyte_size = 1;
+   }
+
+   while (remain) {
+   to_copy = min(tx_array_size, remain);
+   dev_dbg(par->info->device, "to_copy=%zu, remain=%zu\n",
+   to_copy, remain - to_copy);
+
+   for (i = 0; i < to_copy; i++)
+   txbuf16[i] = cpu_to_be16(vmem16[i]);
+
+   vm

[PATCH v5 2/2] arm64: dts: mt8192: Add node for the Mali GPU

2021-01-28 Thread Nick Fan

Add a basic GPU node for mt8192.

Signed-off-by: Nick Fan 
---
This patch depends on Mediatek power and regulator support.

Listed as following.

[1]https://lore.kernel.org/patchwork/patch/1336293/
[2]https://patchwork.kernel.org/project/linux-mediatek/list/?series=374013
[3]https://lore.kernel.org/patchwork/patch/1356037/
[4]https://patchwork.kernel.org/project/linux-mediatek/list/?series=405777
[5]https://lore.kernel.org/patchwork/patch/1356175/
[6]https://patchwork.kernel.org/project/linux-mediatek/patch/1605700894-32699-6-git-send-email-hsin-hsiung.w...@mediatek.com/
[7]https://patchwork.kernel.org/project/linux-mediatek/patch/1608104827-7937-10-git-send-email-hsin-hsiung.w...@mediatek.com/
---
---
 arch/arm64/boot/dts/mediatek/mt8192-evb.dts |   7 +
 arch/arm64/boot/dts/mediatek/mt8192.dtsi| 140 
 2 files changed, 147 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts 
b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 6c1e2b3e8a60..48c0e240dd92 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
@@ -5,6 +5,7 @@
  */
 /dts-v1/;
 #include "mt8192.dtsi"
+#include "mt6359.dtsi"
 
 / {
model = "MediaTek MT8192 evaluation board";
@@ -70,6 +71,12 @@
};
 };
 
+&gpu {
+   supply-names = "mali","sram";
+   mali-supply = <&mt6315_7_vbuck1>;
+   sram-supply = <&mt6359_vsram_others_ldo_reg>;
+};
+
 &uart0 {
status = "okay";
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index d6a4ad242a33..d0e812791185 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -822,6 +822,146 @@
#clock-cells = <1>;
};
 
+   gpu: mali@1300 {
+   compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
+   reg = <0 0x1300 0 0x4000>;
+   interrupts =
+   ,
+   ,
+   ;
+   interrupt-names =
+   "gpu",
+   "mmu",
+   "job";
+
+   clocks =
+   <&apmixedsys CLK_APMIXED_MFGPLL>,
+   <&topckgen CLK_TOP_MFG_PLL_SEL>,
+   <&topckgen CLK_TOP_MFG_REF_SEL>,
+   <&mfgcfg CLK_MFG_BG3D>;
+   clock-names =
+   "clk_main_parent",
+   "clk_mux",
+   "clk_sub_parent",
+   "subsys_mfg_cg";
+
+   power-domains =
+   <&spm MT8192_POWER_DOMAIN_MFG2>,
+   <&spm MT8192_POWER_DOMAIN_MFG3>,
+   <&spm MT8192_POWER_DOMAIN_MFG4>,
+   <&spm MT8192_POWER_DOMAIN_MFG5>,
+   <&spm MT8192_POWER_DOMAIN_MFG6>;
+   power-domain-names = "core0",
+"core1",
+"core2",
+"core3",
+"core4";
+
+   operating-points-v2 = <&gpu_opp_table>;
+   #cooling-cells = <2>;
+
+   gpu_opp_table: opp_table0 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp-35800 {
+   opp-hz = /bits/ 64 <35800>;
+   opp-microvolt = <606250>,
+   <75>;
+   };
+
+   opp-39900 {
+   opp-hz = /bits/ 64 <39900>;
+   opp-microvolt = <618750>,
+   <75>;
+   };
+
+   opp-44000 {
+   opp-hz = /bits/ 64 <44000>;
+   opp-microvolt = <631250>,
+   <75>;
+   };
+
+   opp-48200 {
+   opp-hz = /bits/ 64 <48200>;
+   opp-microvolt = <643750>,
+   <75>;
+   };
+
+   opp-52300 {
+   opp-hz = /bits/ 64 <52300>;
+

[PATCH v3 12/14] drm/bridge: imx: Add LDB support for i.MX8qxp

This patch adds a drm bridge driver for i.MX8qxp LVDS display bridge(LDB)
which is officially named as pixel mapper.  The LDB has two channels.
Each of them supports up to 24bpp parallel input color format and can map
the input to VESA or JEIDA standards.  The two channels cannot be used
simultaneously, that is to say, the user should pick one of them to use.
Two LDB channels from two LDB instances can work together in LDB split
mode to support a dual link LVDS display.  The channel indexes have to be
different.  Channel0 outputs odd pixels and channel1 outputs even pixels.
This patch supports the LDB single mode and split mode.

Signed-off-by: Liu Ying 
---
v2->v3:
* No change.

v1->v2:
* Drop unnecessary DT validation.
* Use of_graph_get_endpoint_by_regs() and of_graph_get_remote_endpoint() to
  get the input remote endpoint in imx8qxp_ldb_set_di_id().
* Avoid using companion_port OF node after putting it in
  imx8qxp_ldb_parse_dt_companion().
* Mention i.MX8qxp LDB official name 'pixel mapper' in the bridge driver
  and Kconfig help message.

 drivers/gpu/drm/bridge/imx/Kconfig   |  10 +
 drivers/gpu/drm/bridge/imx/Makefile  |   1 +
 drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c | 719 +++
 3 files changed, 730 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c

diff --git a/drivers/gpu/drm/bridge/imx/Kconfig 
b/drivers/gpu/drm/bridge/imx/Kconfig
index 23e24fd..07ad230 100644
--- a/drivers/gpu/drm/bridge/imx/Kconfig
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -6,6 +6,16 @@ config DRM_IMX_LVDS_BRIDGE_HELPER
  Helper to support Freescale i.MX LVDS Display Bridge(LDB).
  This bridge is embedded in a SoC.
 
+config DRM_IMX8QXP_LDB
+   tristate "Freescale i.MX8QXP LVDS display bridge"
+   depends on DRM_IMX_LVDS_BRIDGE_HELPER
+   depends on OF
+   depends on COMMON_CLK
+   select DRM_KMS_HELPER
+   help
+ Choose this to enable the internal LVDS Display Bridge(LDB) found in
+ Freescale i.MX8qxp processor.  Official name of LDB is pixel mapper.
+
 config DRM_IMX8QXP_PIXEL_COMBINER
tristate "Freescale i.MX8QM/QXP pixel combiner"
depends on OF
diff --git a/drivers/gpu/drm/bridge/imx/Makefile 
b/drivers/gpu/drm/bridge/imx/Makefile
index 902b703..13160f0 100644
--- a/drivers/gpu/drm/bridge/imx/Makefile
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_DRM_IMX_LVDS_BRIDGE_HELPER) += imx-ldb-helper.o
+obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o
 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c 
b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c
new file mode 100644
index ..62453b9
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c
@@ -0,0 +1,719 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define  LDB_CH_SEL(1 << 28)
+
+#define SS_CTRL0x20
+#define  CH_HSYNC_M(id)BIT(0 + ((id) * 2))
+#define  CH_VSYNC_M(id)BIT(1 + ((id) * 2))
+#define  CH_PHSYNC(id) BIT(0 + ((id) * 2))
+#define  CH_PVSYNC(id) BIT(1 + ((id) * 2))
+
+#define DRIVER_NAME"imx8qxp-ldb"
+
+struct imx8qxp_ldb_channel {
+   struct ldb_channel base;
+   struct phy *phy;
+   unsigned int di_id;
+};
+
+struct imx8qxp_ldb {
+   struct ldb base;
+   struct device *dev;
+   struct imx8qxp_ldb_channel channel[MAX_LDB_CHAN_NUM];
+   struct clk *clk_pixel;
+   struct clk *clk_bypass;
+   struct drm_bridge *companion;
+   int active_chno;
+};
+
+static inline struct imx8qxp_ldb_channel *
+base_to_imx8qxp_ldb_channel(struct ldb_channel *base)
+{
+   return container_of(base, struct imx8qxp_ldb_channel, base);
+}
+
+static inline struct imx8qxp_ldb *base_to_imx8qxp_ldb(struct ldb *base)
+{
+   return container_of(base, struct imx8qxp_ldb, base);
+}
+
+static void imx8qxp_ldb_set_phy_cfg(struct imx8qxp_ldb *imx8qxp_ldb,
+   unsigned long di_clk, bool is_split,
+   struct phy_configure_opts_lvds *phy_cfg)
+{
+   phy_cfg->bits_per_lane_and_dclk_cycle = 7;
+   phy_cfg->lanes = 4;
+
+   if (is_split) {
+   phy_cfg->differential_clk_rate = di_clk / 2;
+   phy_cfg->is_slave = !imx8qxp_ldb->companion;
+   } else {
+   phy_cfg->differential_clk_rate = di_clk;
+   phy_cfg->is_slave = false;
+   }
+}
+
+static int imx8qxp_ldb_bridge_atomic_check(struct drm_bridge *bridge,
+  struct drm_bridge_state *bridge_state

[PATCH v3 13/14] drm/bridge: imx: Add LDB support for i.MX8qm

This patch adds a drm bridge driver for i.MX8qm LVDS display bridge(LDB)
which is officially named as pixel mapper.  The LDB has two channels.
Each of them supports up to 30bpp parallel input color format and can
map the input to VESA or JEIDA standards.  The two channels can be used
simultaneously, either in dual mode or split mode.  In dual mode, the
two channels output identical data.  In split mode, channel0 outputs
odd pixels and channel1 outputs even pixels.  This patch supports the
LDB single mode and split mode.

Signed-off-by: Liu Ying 
---
v2->v3:
* No change.

v1->v2:
* Drop unnecessary check for maximum available LDB channels.
* Mention i.MX8qm LDB official name 'pixel mapper' in the bridge driver
  and Kconfig help message.

 drivers/gpu/drm/bridge/imx/Kconfig  |  10 +
 drivers/gpu/drm/bridge/imx/Makefile |   1 +
 drivers/gpu/drm/bridge/imx/imx8qm-ldb.c | 585 
 3 files changed, 596 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/imx/imx8qm-ldb.c

diff --git a/drivers/gpu/drm/bridge/imx/Kconfig 
b/drivers/gpu/drm/bridge/imx/Kconfig
index 07ad230..290509c 100644
--- a/drivers/gpu/drm/bridge/imx/Kconfig
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -6,6 +6,16 @@ config DRM_IMX_LVDS_BRIDGE_HELPER
  Helper to support Freescale i.MX LVDS Display Bridge(LDB).
  This bridge is embedded in a SoC.
 
+config DRM_IMX8QM_LDB
+   tristate "Freescale i.MX8QM LVDS display bridge"
+   depends on DRM_IMX_LVDS_BRIDGE_HELPER
+   depends on OF
+   depends on COMMON_CLK
+   select DRM_KMS_HELPER
+   help
+ Choose this to enable the internal LVDS Display Bridge(LDB) found in
+ Freescale i.MX8qm processor.  Official name of LDB is pixel mapper.
+
 config DRM_IMX8QXP_LDB
tristate "Freescale i.MX8QXP LVDS display bridge"
depends on DRM_IMX_LVDS_BRIDGE_HELPER
diff --git a/drivers/gpu/drm/bridge/imx/Makefile 
b/drivers/gpu/drm/bridge/imx/Makefile
index 13160f0..a964efc 100644
--- a/drivers/gpu/drm/bridge/imx/Makefile
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_DRM_IMX_LVDS_BRIDGE_HELPER) += imx-ldb-helper.o
+obj-$(CONFIG_DRM_IMX8QM_LDB) += imx8qm-ldb.o
 obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o
 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
diff --git a/drivers/gpu/drm/bridge/imx/imx8qm-ldb.c 
b/drivers/gpu/drm/bridge/imx/imx8qm-ldb.c
new file mode 100644
index ..bf0b5ce
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8qm-ldb.c
@@ -0,0 +1,585 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define  LDB_CH0_10BIT_EN  (1 << 22)
+#define  LDB_CH1_10BIT_EN  (1 << 23)
+#define  LDB_CH0_DATA_WIDTH_24BIT  (1 << 24)
+#define  LDB_CH1_DATA_WIDTH_24BIT  (1 << 26)
+#define  LDB_CH0_DATA_WIDTH_30BIT  (2 << 24)
+#define  LDB_CH1_DATA_WIDTH_30BIT  (2 << 26)
+
+#define SS_CTRL0x20
+#define  CH_HSYNC_M(id)BIT(0 + ((id) * 2))
+#define  CH_VSYNC_M(id)BIT(1 + ((id) * 2))
+#define  CH_PHSYNC(id) BIT(0 + ((id) * 2))
+#define  CH_PVSYNC(id) BIT(1 + ((id) * 2))
+
+#define DRIVER_NAME"imx8qm-ldb"
+
+struct imx8qm_ldb_channel {
+   struct ldb_channel base;
+   struct phy *phy;
+};
+
+struct imx8qm_ldb {
+   struct ldb base;
+   struct device *dev;
+   struct imx8qm_ldb_channel channel[MAX_LDB_CHAN_NUM];
+   struct clk *clk_pixel;
+   struct clk *clk_bypass;
+   int active_chno;
+};
+
+static inline struct imx8qm_ldb_channel *
+base_to_imx8qm_ldb_channel(struct ldb_channel *base)
+{
+   return container_of(base, struct imx8qm_ldb_channel, base);
+}
+
+static inline struct imx8qm_ldb *base_to_imx8qm_ldb(struct ldb *base)
+{
+   return container_of(base, struct imx8qm_ldb, base);
+}
+
+static void imx8qm_ldb_set_phy_cfg(struct imx8qm_ldb *imx8qm_ldb,
+  unsigned long di_clk,
+  bool is_split, bool is_slave,
+  struct phy_configure_opts_lvds *phy_cfg)
+{
+   phy_cfg->bits_per_lane_and_dclk_cycle = 7;
+   phy_cfg->lanes = 4;
+   phy_cfg->differential_clk_rate = is_split ? di_clk / 2 : di_clk;
+   phy_cfg->is_slave = is_slave;
+}
+
+static int imx8qm_ldb_bridge_atomic_check(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state 
*conn_state)
+{
+   struct ldb_channel *ldb_ch = bridge->d

[PATCH 0/2] video: omap*: Remove in_interrupt() usage.

Folks,

in the discussion about preempt count consistency across kernel
configurations:

 https://lore.kernel.org/r/20200914204209.256266...@linutronix.de/

it was concluded that the usage of in_interrupt() and related context
checks should be removed from non-core code.

In the long run, usage of 'preemptible, in_*irq etc.' should be banned from
driver code completely.

This series targets the video subsystem.

Sebastian

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[PATCH v11 7/9] drm/mediatek: enable dither function

From: Yongqiang Niu 

for 5 or 6 bpc panel, we need enable dither function
to improve the display quality

Signed-off-by: Yongqiang Niu 
Signed-off-by: Hsin-Yi Wang 
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 -
 1 file changed, 43 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 8173f709272be..e85625704d611 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -53,7 +53,9 @@
 #define DITHER_EN  BIT(0)
 #define DISP_DITHER_CFG0x0020
 #define DITHER_RELAY_MODE  BIT(0)
+#define DITHER_ENGINE_EN   BIT(1)
 #define DISP_DITHER_SIZE   0x0030
+#define DITHER_REG(idx)(0x100 + (idx) * 4)
 
 #define LUT_10BIT_MASK 0x03ff
 
@@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, unsigned 
int w,
 {
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
+   bool enable = false;
+
+   /* default value for dither reg 5 to 14 */
+   const u32 dither_setting[] = {
+   0x, /* 5 */
+   0x3002, /* 6 */
+   0x, /* 7 */
+   0x, /* 8 */
+   0x, /* 9 */
+   0x, /* 10 */
+   0x, /* 11 */
+   0x0011, /* 12 */
+   0x, /* 13 */
+   0x, /* 14 */
+   };
+
+   if (bpc == 5 || bpc == 6) {
+   enable = true;
+   mtk_ddp_write(cmdq_pkt,
+ DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
+ DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
+ DITHER_NEW_BIT_MODE,
+ &priv->cmdq_reg, priv->regs, DITHER_REG(15));
+   mtk_ddp_write(cmdq_pkt,
+ DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
+ DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
+ DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
+ DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
+ &priv->cmdq_reg, priv->regs, DITHER_REG(16));
+   }
+
+
+   if (enable) {
+   u32 idx;
+
+   for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)
+   mtk_ddp_write(cmdq_pkt, dither_setting[idx], 
&priv->cmdq_reg, priv->regs,
+ DITHER_REG(idx + 5));
+   }
+
mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, 
DISP_DITHER_SIZE);
-   mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, 
DISP_DITHER_CFG);
+mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, 
&priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
 }
 
 static void mtk_dither_start(struct device *dev)
-- 
2.30.0.280.ga3ce27912f-goog

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[PATCH v3 01/14] phy: Add LVDS configuration options

This patch allows LVDS PHYs to be configured through
the generic functions and through a custom structure
added to the generic union.

The parameters added here are based on common LVDS PHY
implementation practices.  The set of parameters
should cover all potential users.

Cc: Kishon Vijay Abraham I 
Cc: Vinod Koul 
Cc: NXP Linux Team 
Signed-off-by: Liu Ying 
---
v2->v3:
* No change.

v1->v2:
* No change.

 include/linux/phy/phy-lvds.h | 48 
 include/linux/phy/phy.h  |  4 
 2 files changed, 52 insertions(+)
 create mode 100644 include/linux/phy/phy-lvds.h

diff --git a/include/linux/phy/phy-lvds.h b/include/linux/phy/phy-lvds.h
new file mode 100644
index ..1b5b9d6
--- /dev/null
+++ b/include/linux/phy/phy-lvds.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __PHY_LVDS_H_
+#define __PHY_LVDS_H_
+
+/**
+ * struct phy_configure_opts_lvds - LVDS configuration set
+ *
+ * This structure is used to represent the configuration state of a
+ * LVDS phy.
+ */
+struct phy_configure_opts_lvds {
+   /**
+* @bits_per_lane_and_dclk_cycle:
+*
+* Number of bits per data lane and differential clock cycle.
+*/
+   unsigned int bits_per_lane_and_dclk_cycle;
+
+   /**
+* @differential_clk_rate:
+*
+* Clock rate, in Hertz, of the LVDS differential clock.
+*/
+   unsigned long differential_clk_rate;
+
+   /**
+* @lanes:
+*
+* Number of active, consecutive, data lanes, starting from
+* lane 0, used for the transmissions.
+*/
+   unsigned int lanes;
+
+   /**
+* @is_slave:
+*
+* Boolean, true if the phy is a slave which works together
+* with a master phy to support dual link transmission,
+* otherwise a regular phy or a master phy.
+*/
+   bool is_slave;
+};
+
+#endif /* __PHY_LVDS_H_ */
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index e435bdb..d450b44 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -17,6 +17,7 @@
 #include 
 
 #include 
+#include 
 #include 
 
 struct phy;
@@ -51,10 +52,13 @@ enum phy_mode {
  * the MIPI_DPHY phy mode.
  * @dp:Configuration set applicable for phys supporting
  * the DisplayPort protocol.
+ * @lvds:  Configuration set applicable for phys supporting
+ * the LVDS phy mode.
  */
 union phy_configure_opts {
struct phy_configure_opts_mipi_dphy mipi_dphy;
struct phy_configure_opts_dpdp;
+   struct phy_configure_opts_lvds  lvds;
 };
 
 /**
-- 
2.7.4

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Re: [PATCH] drm/lima: add governor data with pre-defined thresholds

2021-01-28 Thread Lukasz Luba

On 1/27/21 10:24 AM, Lukasz Luba wrote:

Hi Christian,

On 1/25/21 8:18 AM, Christian Hewitt wrote:

This patch adapts the panfrost pre-defined thresholds change [0] to the
lima driver to improve real-world performance. The upthreshold value has
been set to ramp GPU frequency to max freq faster (compared to panfrost)
to compensate for the lower overall performance of utgard devices.

[0]
https://patchwork.kernel.org/project/dri-devel/patch/20210121170445.19761-1-lukasz.l...@arm.com/

Signed-off-by: Christian Hewitt
---
I have been using Kodi as my test application. If you scroll in library
views with hundreds of list items and the panfrost values the slow GPU
ramp up is quite noticeable and the GUI feels sluggish. As everything
lima runs on is inherently slower than panfrost using devices I believe
it's better to ramp up to max freq quicker.

It's quite low value for the upthreshold, but I believe you have
experimented and observed that a bit higher (30, 40?) don't work well.
I don't know the Kodi system, though.

You can check if the other frequencies are also used in statistics for
devfreq device:
cat /sys/class/devfreq//trans_stats

If they are also used, then it OK (better than stuck at min freq).

I've just realized that your board might suffer a another issue.
Please apply this patch [1] and run your experiments with upthresholds.

[1] https://lore.kernel.org/lkml/20210127105121.20345-1-lukasz.l...@arm.com/
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Re: [PATCH v5 00/21] Host1x/TegraDRM UAPI

26.01.2021 05:45, Mikko Perttunen пишет:
>> 5. The hardware state of sync points should be reset when sync point is
>> requested, not when host1x driver is initialized.
> 
> This may be doable, but I don't think it is critical for this UAPI, so
> let's consider it after this series.
> 
> The userspace should anyway not be able to assume the initial value of
> the syncpoint upon allocation. The kernel should set it to some high
> value to catch any issues related to wraparound.

This is critical because min != max when sync point is requested.

> Also, this makes code more complicated since it now needs to ensure all
> waits on the syncpoint have completed before freeing the syncpoint,
> which can be nontrivial e.g. if the waiter is in a different virtual
> machine or some other device connected via PCIe (a real usecase).

It sounds to me that these VM sync points should be treated very
separately from a generic sync points, don't you think so? Let's not mix
them and get the generic sync points usable first.
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[PATCH v3 03/14] media: docs: Add some RGB bus formats for i.MX8qm/qxp pixel combiner

This patch adds documentations for RGB666_1X30_CPADLO, RGB888_1X30_CPADLO,
RGB666_1X36_CPADLO and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp
pixel combiner.  The RGB pixels with padding low per component are
transmitted on a 30-bit input bus(10-bit per component) from a display
controller or a 36-bit output bus(12-bit per component) to a pixel link.

Signed-off-by: Liu Ying 
---
v2->v3:
* No change.

v1->v2:
* No change.

 .../userspace-api/media/v4l/subdev-formats.rst | 156 +
 1 file changed, 156 insertions(+)

diff --git a/Documentation/userspace-api/media/v4l/subdev-formats.rst 
b/Documentation/userspace-api/media/v4l/subdev-formats.rst
index 7f16cbe..201c16d 100644
--- a/Documentation/userspace-api/media/v4l/subdev-formats.rst
+++ b/Documentation/userspace-api/media/v4l/subdev-formats.rst
@@ -1488,6 +1488,80 @@ The following tables list existing packed RGB formats.
   - b\ :sub:`2`
   - b\ :sub:`1`
   - b\ :sub:`0`
+* .. _MEDIA-BUS-FMT-RGB666-1X30-CPADLO:
+
+  - MEDIA_BUS_FMT_RGB666_1X30-CPADLO
+  - 0x101e
+  -
+  - 0
+  - 0
+  - r\ :sub:`5`
+  - r\ :sub:`4`
+  - r\ :sub:`3`
+  - r\ :sub:`2`
+  - r\ :sub:`1`
+  - r\ :sub:`0`
+  - 0
+  - 0
+  - 0
+  - 0
+  - g\ :sub:`5`
+  - g\ :sub:`4`
+  - g\ :sub:`3`
+  - g\ :sub:`2`
+  - g\ :sub:`1`
+  - g\ :sub:`0`
+  - 0
+  - 0
+  - 0
+  - 0
+  - b\ :sub:`5`
+  - b\ :sub:`4`
+  - b\ :sub:`3`
+  - b\ :sub:`2`
+  - b\ :sub:`1`
+  - b\ :sub:`0`
+  - 0
+  - 0
+  - 0
+  - 0
+* .. _MEDIA-BUS-FMT-RGB888-1X30-CPADLO:
+
+  - MEDIA_BUS_FMT_RGB888_1X30-CPADLO
+  - 0x101f
+  -
+  - 0
+  - 0
+  - r\ :sub:`7`
+  - r\ :sub:`6`
+  - r\ :sub:`5`
+  - r\ :sub:`4`
+  - r\ :sub:`3`
+  - r\ :sub:`2`
+  - r\ :sub:`1`
+  - r\ :sub:`0`
+  - 0
+  - 0
+  - g\ :sub:`7`
+  - g\ :sub:`6`
+  - g\ :sub:`5`
+  - g\ :sub:`4`
+  - g\ :sub:`3`
+  - g\ :sub:`2`
+  - g\ :sub:`1`
+  - g\ :sub:`0`
+  - 0
+  - 0
+  - b\ :sub:`7`
+  - b\ :sub:`6`
+  - b\ :sub:`5`
+  - b\ :sub:`4`
+  - b\ :sub:`3`
+  - b\ :sub:`2`
+  - b\ :sub:`1`
+  - b\ :sub:`0`
+  - 0
+  - 0
 * .. _MEDIA-BUS-FMT-ARGB888-1X32:
 
   - MEDIA_BUS_FMT_ARGB888_1X32
@@ -1665,6 +1739,88 @@ The following table list existing packed 36bit wide RGB 
formats.
   - 2
   - 1
   - 0
+* .. _MEDIA-BUS-FMT-RGB666-1X36-CPADLO:
+
+  - MEDIA_BUS_FMT_RGB666_1X36_CPADLO
+  - 0x1020
+  -
+  - r\ :sub:`5`
+  - r\ :sub:`4`
+  - r\ :sub:`3`
+  - r\ :sub:`2`
+  - r\ :sub:`1`
+  - r\ :sub:`0`
+  - 0
+  - 0
+  - 0
+  - 0
+  - 0
+  - 0
+  - g\ :sub:`5`
+  - g\ :sub:`4`
+  - g\ :sub:`3`
+  - g\ :sub:`2`
+  - g\ :sub:`1`
+  - g\ :sub:`0`
+  - 0
+  - 0
+  - 0
+  - 0
+  - 0
+  - 0
+  - b\ :sub:`5`
+  - b\ :sub:`4`
+  - b\ :sub:`3`
+  - b\ :sub:`2`
+  - b\ :sub:`1`
+  - b\ :sub:`0`
+  - 0
+  - 0
+  - 0
+  - 0
+  - 0
+  - 0
+* .. _MEDIA-BUS-FMT-RGB888-1X36-CPADLO:
+
+  - MEDIA_BUS_FMT_RGB888_1X36_CPADLO
+  - 0x1021
+  -
+  - r\ :sub:`7`
+  - r\ :sub:`6`
+  - r\ :sub:`5`
+  - r\ :sub:`4`
+  - r\ :sub:`3`
+  - r\ :sub:`2`
+  - r\ :sub:`1`
+  - r\ :sub:`0`
+  - 0
+  - 0
+  - 0
+  - 0
+  - g\ :sub:`7`
+  - g\ :sub:`6`
+  - g\ :sub:`5`
+  - g\ :sub:`4`
+  - g\ :sub:`3`
+  - g\ :sub:`2`
+  - g\ :sub:`1`
+  - g\ :sub:`0`
+  - 0
+  - 0
+  - 0
+  - 0
+  - b\ :sub:`7`
+  - b\ :sub:`6`
+  - b\ :sub:`5`
+  - b\ :sub:`4`
+  - b\ :sub:`3`
+  - b\ :sub:`2`
+  - b\ :sub:`1`
+  - b\ :sub:`0`
+  - 0
+  - 0
+  - 0
+  - 0
 * .. _MEDIA-BUS-FMT-RGB121212-1X36:
 
   - MEDIA_BUS_FMT_RGB121212_1X36
-- 
2.7.4

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[PATCH v11] staging: fbtft: add tearing signal detect

From: zhangxuezhi 

For st7789v ic,when we need continuous full screen refresh, it is best to
wait for the TE signal arrive to avoid screen tearing

Signed-off-by: zhangxuezhi 
---
v11: remove devm_gpio_put and change a dev_err to dev_info
v10: additional notes
v9: change pr_* to dev_*
v8: delete a log line
v7: return error value when request fail
v6: add te gpio request fail deal logic
v5: fix log print
v4: modify some code style and change te irq set function name
v3: modify author and signed-off-by name
v2: add release te gpio after irq request fail
---
 drivers/staging/fbtft/fb_st7789v.c | 131 -
 drivers/staging/fbtft/fbtft.h  |   1 +
 2 files changed, 131 insertions(+), 1 deletion(-)

diff --git a/drivers/staging/fbtft/fb_st7789v.c 
b/drivers/staging/fbtft/fb_st7789v.c
index 3a280cc..cfb54a4 100644
--- a/drivers/staging/fbtft/fb_st7789v.c
+++ b/drivers/staging/fbtft/fb_st7789v.c
@@ -9,9 +9,12 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #include 
 #include 
-
+#include 
 #include "fbtft.h"
 
 #define DRVNAME "fb_st7789v"
@@ -66,6 +69,32 @@ enum st7789v_command {
 #define MADCTL_MX BIT(6) /* bitmask for column address order */
 #define MADCTL_MY BIT(7) /* bitmask for page address order */
 
+#define SPI_PANEL_TE_TIMEOUT   400 /* msecs */
+static struct mutex te_mutex;/* mutex for set te gpio irq status */
+static struct completion spi_panel_te;
+
+static irqreturn_t spi_panel_te_handler(int irq, void *data)
+{
+   complete(&spi_panel_te);
+   return IRQ_HANDLED;
+}
+
+static void set_spi_panel_te_irq_status(struct fbtft_par *par, bool enable)
+{
+   static int te_irq_count;
+
+   mutex_lock(&te_mutex);
+
+   if (enable) {
+   if (++te_irq_count == 1)
+   enable_irq(gpiod_to_irq(par->gpio.te));
+   } else {
+   if (--te_irq_count == 0)
+   disable_irq(gpiod_to_irq(par->gpio.te));
+   }
+   mutex_unlock(&te_mutex);
+}
+
 /**
  * init_display() - initialize the display controller
  *
@@ -82,6 +111,32 @@ enum st7789v_command {
  */
 static int init_display(struct fbtft_par *par)
 {
+   int rc;
+   struct device *dev = par->info->device;
+
+   par->gpio.te = devm_gpiod_get_index_optional(dev, "te", 0, GPIOD_IN);
+   if (IS_ERR(par->gpio.te)) {
+   rc = PTR_ERR(par->gpio.te);
+   dev_info(par->info->device, "Failed to request te gpio: %d\n", 
rc);
+   return rc;
+   }
+   if (par->gpio.te) {
+   init_completion(&spi_panel_te);
+   mutex_init(&te_mutex);
+   rc = devm_request_irq(dev,
+ gpiod_to_irq(par->gpio.te),
+spi_panel_te_handler, IRQF_TRIGGER_RISING,
+"TE_GPIO", par);
+   if (rc) {
+   dev_err(par->info->device, "TE request_irq failed.\n");
+   return rc;
+   }
+
+   disable_irq_nosync(gpiod_to_irq(par->gpio.te));
+   } else {
+   dev_info(par->info->device, "%s:%d, TE gpio not specified\n",
+__func__, __LINE__);
+   }
/* turn off sleep mode */
write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE);
mdelay(120);
@@ -137,6 +192,9 @@ static int init_display(struct fbtft_par *par)
 */
write_reg(par, PWCTRL1, 0xA4, 0xA1);
 
+/*Tearing Effect Line On*/
+   if (par->gpio.te)
+   write_reg(par, 0x35, 0x00);
write_reg(par, MIPI_DCS_SET_DISPLAY_ON);
 
if (HSD20_IPS)
@@ -145,6 +203,76 @@ static int init_display(struct fbtft_par *par)
return 0;
 }
 
+/*
+ *
+ *   int (*write_vmem)(struct fbtft_par *par);
+ *
+ */
+
+/* 16 bit pixel over 8-bit databus */
+static int st7789v_write_vmem16_bus8(struct fbtft_par *par, size_t offset, 
size_t len)
+{
+   u16 *vmem16;
+   __be16 *txbuf16 = par->txbuf.buf;
+   size_t remain;
+   size_t to_copy;
+   size_t tx_array_size;
+   int i;
+   int ret = 0;
+   size_t startbyte_size = 0;
+
+   fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "st7789v ---%s(offset=%zu, 
len=%zu)\n",
+ __func__, offset, len);
+
+   remain = len / 2;
+   vmem16 = (u16 *)(par->info->screen_buffer + offset);
+
+   if (par->gpio.dc)
+   gpiod_set_value(par->gpio.dc, 1);
+
+   /* non buffered write */
+   if (!par->txbuf.buf)
+   return par->fbtftops.write(par, vmem16, len);
+
+   /* buffered write */
+   tx_array_size = par->txbuf.len / 2;
+
+   if (par->startbyte) {
+   txbuf16 = par->txbuf.buf + 1;
+   tx_array_size -= 2;
+   *(u8 *)(par->txbuf.buf) = par->startbyte | 0x2;
+

Re: mmotm 2021-01-25-21-18 uploaded (drm/i915/Kconfig.debug)

On 1/25/21 9:19 PM, a...@linux-foundation.org wrote:
> The mm-of-the-moment snapshot 2021-01-25-21-18 has been uploaded to
> 
>https://www.ozlabs.org/~akpm/mmotm/
> 
> mmotm-readme.txt says
> 
> README for mm-of-the-moment:
> 
> https://www.ozlabs.org/~akpm/mmotm/
> 
> This is a snapshot of my -mm patch queue.  Uploaded at random hopefully
> more than once a week.
> 
> You will need quilt to apply these patches to the latest Linus release (5.x
> or 5.x-rcY).  The series file is in broken-out.tar.gz and is duplicated in
> https://ozlabs.org/~akpm/mmotm/series
> 
> The file broken-out.tar.gz contains two datestamp files: .DATE and
> .DATE--mm-dd-hh-mm-ss.  Both contain the string -mm-dd-hh-mm-ss,
> followed by the base kernel version against which this patch series is to
> be applied.

on x86_64:

when CONFIG_COMPILE_TEST=y:

WARNING: unmet direct dependencies detected for DRM_I915_WERROR
  Depends on [n]: HAS_IOMEM [=y] && DRM_I915 [=m] && EXPERT [=y] && 
!COMPILE_TEST [=y]
  Selected by [m]:
  - DRM_I915_DEBUG [=y] && HAS_IOMEM [=y] && EXPERT [=y] && DRM_I915 [=m]


-- 
~Randy
Reported-by: Randy Dunlap 

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[PATCH 1/2] video: omap: Remove in_interrupt() usage.

From: "Ahmed S. Darwish" 

alloc_req() uses in_interrupt() to detect if it is safe to use down().

The usage of in_interrupt() in drivers is phased out and Linus clearly
requested that code which changes behaviour depending on context should
either be separated or the context be conveyed in an argument passed by the
caller, which usually knows the context.

The semaphore is used as a counting semaphore, initialized with the
number of slots in the request pool minus IRQ_REQ_POOL_SIZE - which are
reserved for the in_interrupt() user to ensure that a request is always
available. The preemptible user will block on the semphore waiting for a
request to become available in case there are no requests available.

Replace in_interrupt() with a `can_sleep' argument to indicate if it is
safe to block on the sempahore.

Signed-off-by: Ahmed S. Darwish 
Signed-off-by: Sebastian Andrzej Siewior 
---
 drivers/video/fbdev/omap/hwa742.c | 42 ---
 1 file changed, 28 insertions(+), 14 deletions(-)

diff --git a/drivers/video/fbdev/omap/hwa742.c 
b/drivers/video/fbdev/omap/hwa742.c
index cfe63932f8255..b191bef22d984 100644
--- a/drivers/video/fbdev/omap/hwa742.c
+++ b/drivers/video/fbdev/omap/hwa742.c
@@ -100,6 +100,14 @@ struct {
struct hwa742_request   req_pool[REQ_POOL_SIZE];
struct list_headpending_req_list;
struct list_headfree_req_list;
+
+   /*
+* @req_lock: protect request slots pool and its tracking lists
+* @req_sema: counter; slot allocators from task contexts must
+*push it down before acquiring a slot. This
+*guarantees that atomic contexts will always have
+*a minimum of IRQ_REQ_POOL_SIZE slots available.
+*/
struct semaphorereq_sema;
spinlock_t  req_lock;
 
@@ -224,13 +232,13 @@ static void disable_tearsync(void)
hwa742_write_reg(HWA742_NDP_CTRL, b);
 }
 
-static inline struct hwa742_request *alloc_req(void)
+static inline struct hwa742_request *alloc_req(bool can_sleep)
 {
unsigned long flags;
struct hwa742_request *req;
int req_flags = 0;
 
-   if (!in_interrupt())
+   if (can_sleep)
down(&hwa742.req_sema);
else
req_flags = REQ_FROM_IRQ_POOL;
@@ -399,8 +407,8 @@ static void send_frame_complete(void *data)
hwa742.int_ctrl->enable_plane(OMAPFB_PLANE_GFX, 0);
 }
 
-#define ADD_PREQ(_x, _y, _w, _h) do {  \
-   req = alloc_req();  \
+#define ADD_PREQ(_x, _y, _w, _h, can_sleep) do {\
+   req = alloc_req(can_sleep); \
req->handler= send_frame_handler;   \
req->complete   = send_frame_complete;  \
req->par.update.x = _x; \
@@ -413,7 +421,8 @@ static void send_frame_complete(void *data)
 } while(0)
 
 static void create_req_list(struct omapfb_update_window *win,
-   struct list_head *req_head)
+   struct list_head *req_head,
+   bool can_sleep)
 {
struct hwa742_request *req;
int x = win->x;
@@ -427,7 +436,7 @@ static void create_req_list(struct omapfb_update_window 
*win,
color_mode = win->format & OMAPFB_FORMAT_MASK;
 
if (x & 1) {
-   ADD_PREQ(x, y, 1, height);
+   ADD_PREQ(x, y, 1, height, can_sleep);
width--;
x++;
flags &= ~OMAPFB_FORMAT_FLAG_TEARSYNC;
@@ -439,19 +448,19 @@ static void create_req_list(struct omapfb_update_window 
*win,
 
if (xspan * height * 2 > hwa742.max_transmit_size) {
yspan = hwa742.max_transmit_size / (xspan * 2);
-   ADD_PREQ(x, ystart, xspan, yspan);
+   ADD_PREQ(x, ystart, xspan, yspan, can_sleep);
ystart += yspan;
yspan = height - yspan;
flags &= ~OMAPFB_FORMAT_FLAG_TEARSYNC;
}
 
-   ADD_PREQ(x, ystart, xspan, yspan);
+   ADD_PREQ(x, ystart, xspan, yspan, can_sleep);
x += xspan;
width -= xspan;
flags &= ~OMAPFB_FORMAT_FLAG_TEARSYNC;
}
if (width)
-   ADD_PREQ(x, y, 1, height);
+   ADD_PREQ(x, y, 1, height, can_sleep);
 }
 
 static void auto_update_complete(void *data)
@@ -461,12 +470,12 @@ static void auto_update_complete(void *data)
  jiffies + HWA742_AUTO_UPDATE_TIME);
 }
 
-static void hwa742_update_window_auto(struct timer_list *unused)
+static void __hwa742_update_window_auto(bool can_sleep)
 {
LIST_HEAD(req_list);
struct hwa742_request *last;
 
-   create_req_list(&hwa742.auto_update_window, &req_list);
+   create_req_list(&hwa742.auto_update_window, &req_list, can_sleep);
last = list_entry(req_list.prev, struct hwa

Re: [PATCH v6] fbtft: add tearing signal detect

On Wed, 27 Jan 2021 10:00:13 +0100
Geert Uytterhoeven  wrote:

> Hi Carlis,
> 
> On Wed, Jan 27, 2021 at 9:52 AM Carlis  wrote:
> > From: zhangxuezhi 
> >
> > For st7789v ic,add tearing signal detect to avoid screen tearing
> >
> > Signed-off-by: zhangxuezhi   
> 
> Thanks for your patch!
> 
> > --- a/drivers/staging/fbtft/fb_st7789v.c
> > +++ b/drivers/staging/fbtft/fb_st7789v.c  
> 
> > @@ -82,6 +111,34 @@ enum st7789v_command {
> >   */
> >  static int init_display(struct fbtft_par *par)
> >  {
> > +   int rc;
> > +   struct device *dev = par->info->device;
> > +
> > +   par->gpio.te = devm_gpiod_get_index_optional(dev, "te", 0,
> > GPIOD_IN);
> > +   if (IS_ERR(par->gpio.te)) {
> > +   rc = PTR_ERR(par->gpio.te);
> > +   pr_err("Failed to request te gpio: %d\n", rc);
> > +   par->gpio.te = NULL;  
> 
> Errors (e.g. -EPROBE_DEFER) should be propagated upstream,
> not ignored.
> 
> > +   }
> > +   if (par->gpio.te) {
> > +   init_completion(&spi_panel_te);
> > +   mutex_init(&te_mutex);
> > +   rc = devm_request_irq(dev,
> > + gpiod_to_irq(par->gpio.te),
> > +spi_panel_te_handler,
> > IRQF_TRIGGER_RISING,
> > +"TE_GPIO", par);
> > +   if (rc) {
> > +   pr_err("TE request_irq failed.\n");
> > +   devm_gpiod_put(dev, par->gpio.te);
> > +   par->gpio.te = NULL;  
> 
> Errors (e.g. -EPROBE_DEFER) should be propagated upstream,
> not ignored.
> 
> > +   } else {
> > +
> > disable_irq_nosync(gpiod_to_irq(par->gpio.te));
> > +   pr_info("TE request_irq completion.\n");
> > +   }
> > +   } else {
> > +   pr_info("%s:%d, TE gpio not specified\n",
> > +   __func__, __LINE__);
> > +   }
> > /* turn off sleep mode */
> > write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE);
> > mdelay(120);  
> 
> Gr{oetje,eeting}s,
> 
> Geert
> 

hi,i will fix in the patch v7
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Re: [PATCH v11 7/9] drm/mediatek: enable dither function

2021-01-28 Thread Yongqiang Niu

On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
> Hi, Hsin-Yi:
> 
> On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> > From: Yongqiang Niu 
> > 
> > for 5 or 6 bpc panel, we need enable dither function
> > to improve the display quality
> > 
> > Signed-off-by: Yongqiang Niu 
> > Signed-off-by: Hsin-Yi Wang 
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 -
> >  1 file changed, 43 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 8173f709272be..e85625704d611 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -53,7 +53,9 @@
> >  #define DITHER_EN  BIT(0)
> >  #define DISP_DITHER_CFG0x0020
> >  #define DITHER_RELAY_MODE  BIT(0)
> > +#define DITHER_ENGINE_EN   BIT(1)
> >  #define DISP_DITHER_SIZE   0x0030
> > +#define DITHER_REG(idx)(0x100 + (idx) * 4)
> >  
> >  #define LUT_10BIT_MASK 0x03ff
> >  
> > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, 
> > unsigned int w,
> >  {
> > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> >  
> > +   bool enable = false;
> > +
> > +   /* default value for dither reg 5 to 14 */
> > +   const u32 dither_setting[] = {
> > +   0x, /* 5 */
> > +   0x3002, /* 6 */
> > +   0x, /* 7 */
> > +   0x, /* 8 */
> > +   0x, /* 9 */
> > +   0x, /* 10 */
> > +   0x, /* 11 */
> > +   0x0011, /* 12 */
> > +   0x, /* 13 */
> > +   0x, /* 14 */
> 
> Could you explain what is this?

this is dither 5 to dither 14 setting
this will be useless, we just need set dither 5 and dither 7 like 
mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5);
mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7);
other value is same with hardware default value.


> 
> > +   };
> > +
> > +   if (bpc == 5 || bpc == 6) {
> > +   enable = true;
> > +   mtk_ddp_write(cmdq_pkt,
> > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
> > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> > + DITHER_NEW_BIT_MODE,
> > + &priv->cmdq_reg, priv->regs, DITHER_REG(15));
> > +   mtk_ddp_write(cmdq_pkt,
> > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
> > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
> > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
> > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> 
> This result in 0x50505050, but previous version is 0x50504040, so this
> version is correct and previous version is incorrect?

the new version set r g b 3 channel same, seams more reasonable


> 
> Regards,
> CK
> 
> > + &priv->cmdq_reg, priv->regs, DITHER_REG(16));
> > +   }
> > +
> > +
> > +   if (enable) {
> > +   u32 idx;
> > +
> > +   for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)
> > +   mtk_ddp_write(cmdq_pkt, dither_setting[idx], 
> > &priv->cmdq_reg, priv->regs,
> > + DITHER_REG(idx + 5));
> > +   }
> > +
> > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, 
> > DISP_DITHER_SIZE);
> > -   mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, 
> > DISP_DITHER_CFG);
> > +mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : 
> > DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
> >  }
> >  
> >  static void mtk_dither_start(struct device *dev)
> 
> 

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Re: [PATCH] drm/lima: add governor data with pre-defined thresholds

2021-01-28 Thread Lukasz Luba


Hi Christian,

On 1/25/21 8:18 AM, Christian Hewitt wrote:

This patch adapts the panfrost pre-defined thresholds change [0] to the
lima driver to improve real-world performance. The upthreshold value has
been set to ramp GPU frequency to max freq faster (compared to panfrost)
to compensate for the lower overall performance of utgard devices.

[0] 
https://patchwork.kernel.org/project/dri-devel/patch/20210121170445.19761-1-lukasz.l...@arm.com/

Signed-off-by: Christian Hewitt 
---
I have been using Kodi as my test application. If you scroll in library
views with hundreds of list items and the panfrost values the slow GPU
ramp up is quite noticeable and the GUI feels sluggish. As everything
lima runs on is inherently slower than panfrost using devices I believe
it's better to ramp up to max freq quicker.


It's quite low value for the upthreshold, but I believe you have
experimented and observed that a bit higher (30, 40?) don't work well.
I don't know the Kodi system, though.

You can check if the other frequencies are also used in statistics for
devfreq device:
cat /sys/class/devfreq//trans_stats

If they are also used, then it OK (better than stuck at min freq).

Regards,
Lukasz
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[PATCH v3 06/14] dt-bindings: display: bridge: Add i.MX8qm/qxp display pixel link binding

This patch adds bindings for i.MX8qm/qxp display pixel link.

Reviewed-by: Rob Herring 
Signed-off-by: Liu Ying 
---
v2->v3:
* Add Rob's R-b tag.

v1->v2:
* Use graph schema. (Laurent)
* Require all four pixel link output ports. (Laurent)
* Mention pixel link is accessed via SCU firmware. (Rob)

 .../display/bridge/fsl,imx8qxp-pixel-link.yaml | 106 +
 1 file changed, 106 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml

diff --git 
a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml 
b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
new file mode 100644
index ..3af67cc
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Display Pixel Link
+
+maintainers:
+  - Liu Ying 
+
+description: |
+  The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
+  asynchronous linkage between pixel sources(display controller or
+  camera module) and pixel consumers(imaging or displays).
+  It consists of two distinct functions, a pixel transfer function and a
+  control interface.  Multiple pixel channels can exist per one control 
channel.
+  This binding documentation is only for pixel links whose pixel sources are
+  display controllers.
+
+  The i.MX8qm/qxp Display Pixel Link is accessed via System Controller 
Unit(SCU)
+  firmware.
+
+properties:
+  compatible:
+enum:
+  - fsl,imx8qm-dc-pixel-link
+  - fsl,imx8qxp-dc-pixel-link
+
+  ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+  port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description: The pixel link input port node from upstream video source.
+
+patternProperties:
+  "^port@[1-4]$":
+$ref: /schemas/graph.yaml#/properties/port
+description: The pixel link output port node to downstream bridge.
+
+required:
+  - port@0
+  - port@1
+  - port@2
+  - port@3
+  - port@4
+
+required:
+  - compatible
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+dc0-pixel-link0 {
+compatible = "fsl,imx8qxp-dc-pixel-link";
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+/* from dc0 pixel combiner channel0 */
+port@0 {
+reg = <0>;
+
+dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {
+remote-endpoint = 
<&dc0_pixel_combiner_ch0_dc0_pixel_link0>;
+};
+};
+
+/* to PXL2DPIs in MIPI/LVDS combo subsystems */
+port@1 {
+#address-cells = <1>;
+#size-cells = <0>;
+reg = <1>;
+
+dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 {
+reg = <0>;
+remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;
+};
+
+dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 {
+reg = <1>;
+remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;
+};
+};
+
+/* unused */
+port@2 {
+reg = <2>;
+};
+
+/* unused */
+port@3 {
+reg = <3>;
+};
+
+/* to imaging subsystem */
+port@4 {
+reg = <4>;
+};
+};
+};
-- 
2.7.4

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[PATCH v11 6/9] drm/mediatek: add has_dither private data for gamma

From: Yongqiang Niu 

Not all SoC has dither function in gamma module.
Add private data to control this function setting.

Signed-off-by: Yongqiang Niu 
Signed-off-by: Hsin-Yi Wang 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
index a7e2e326b2183..22199ef11f65d 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
@@ -26,7 +26,7 @@
 #define LUT_10BIT_MASK 0x03ff
 
 struct mtk_disp_gamma_data {
-   u32 reserved;
+   bool has_dither;
 };
 
 /**
@@ -92,7 +92,8 @@ void mtk_gamma_config(struct device *dev, unsigned int w,
 
mtk_ddp_write(cmdq_pkt, h << 16 | w, &gamma->cmdq_reg, gamma->regs,
  DISP_GAMMA_SIZE);
-   mtk_dither_set_common(gamma->regs, &gamma->cmdq_reg, bpc, 
DISP_GAMMA_CFG, cmdq_pkt);
+   if (gamma->data && gamma->data->has_dither)
+   mtk_dither_set_common(gamma->regs, &gamma->cmdq_reg, bpc, 
DISP_GAMMA_CFG, cmdq_pkt);
 }
 
 void mtk_gamma_start(struct device *dev)
@@ -172,8 +173,13 @@ static int mtk_disp_gamma_remove(struct platform_device 
*pdev)
return 0;
 }
 
+static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = {
+   .has_dither = true,
+};
+
 static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = {
-   { .compatible = "mediatek,mt8173-disp-gamma"},
+   { .compatible = "mediatek,mt8173-disp-gamma",
+ .data = &mt8173_gamma_driver_data},
{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match);
-- 
2.30.0.280.ga3ce27912f-goog

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Re: [PATCH v5 00/21] sync_file API is not very suitable for DRM

26.01.2021 05:45, Mikko Perttunen пишет:
>> 4. Sync file shouldn't be needed for the part of DRM API which doesn't
>> interact with external non-DRM devices.  We should use DRM syncobj for
>> everything related to DRM, it's a superior API over sync file, it's
>> suitable for DRM scheduler.
> 
> Considering the issues with fileno limits, I suppose there is no other
> choice. Considering the recent NTSYNC proposal by Wine developers, maybe
> we should also have NTHANDLEs to get rid of restrictions of file
> descriptors.

It's odd to me that you trying to avoid the existing DRM API. This all
was solved in DRM long time ago and grate drivers have no problems with
using the DRM APIs. Even if something is really missing, then you should
add the missing features instead of re-inventing everything from scratch.

> DRM syncobjs may have some advantages over sync files, but
> also disadvantages. They cannot be poll()ed, so they cannot be combined
> with waits for other resources.

I'm not sure do you mean by "poll". Sync object supports polling very well.
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[PATCH v3 00/14] Add some DRM bridge drivers support for i.MX8qm/qxp SoCs

Hi,

This is the v3 series to add some DRM bridge drivers support
for i.MX8qm/qxp SoCs.

The bridges may chain one by one to form display pipes to support
LVDS displays.  The relevant display controller is DPU embedded in
i.MX8qm/qxp SoCs.

The DPU KMS driver can be found at:
https://www.spinics.net/lists/arm-kernel/msg871357.html

This series supports the following display pipes:
1) i.MX8qxp:
prefetch eng -> DPU -> pixel combiner -> pixel link ->
pixel link to DPI(PXL2DPI) -> LVDS display bridge(LDB)

2) i.MX8qm:
prefetch eng -> DPU -> pixel combiner -> pixel link -> LVDS display bridge(LDB)


Patch 1/14 adds LVDS PHY configuration options, which has already been sent
with the following series to add Mixel combo PHY found in i.MX8qxp:
https://www.spinics.net/lists/arm-kernel/msg862560.html

Patch 2/14 and 3/14 add bus formats used by PXL2DPI.

Patch 4/14 ~ 13/14 add drm bridge drivers and dt-bindings support for the 
bridges.

Patch 14/14 updates MAINTAINERS.


I've tested this series with a koe,tx26d202vm0bwa dual link LVDS panel and
a LVDS to HDMI bridge(with a downstream drm bridge driver).


Welcome comments, thanks.

v2->v3:
* Drop 'fsl,syscon' DT properties from fsl,imx8qxp-ldb.yaml and
  fsl,imx8qxp-pxl2dpi.yaml. (Rob)
* Mention the CSR module controls LDB and PXL2DPI in fsl,imx8qxp-ldb.yaml and
  fsl,imx8qxp-pxl2dpi.yaml.
* Call syscon_node_to_regmap() to get regmaps from LDB bridge helper driver
  and PXL2DPI bridger driver instead of syscon_regmap_lookup_by_phandle().
* Drop two macros from pixel link bridge driver which help define functions
  and define them directly.
* Properly disable all pixel link controls to POR value by calling
  imx8qxp_pixel_link_disable_all_controls() from
  imx8qxp_pixel_link_bridge_probe().
* Add Rob's R-b tags on patch 4/14 and 6/14.

v1->v2:
* Rebase the series upon the latest drm-misc-next branch(5.11-rc2 based).
* Use graph schema in the dt-bindings of the bridges. (Laurent)
* Require all four pixel link output ports in fsl,imx8qxp-pixel-link.yaml.
  (Laurent)
* Side note i.MX8qm/qxp LDB official name 'pixel mapper' in 
fsl,imx8qxp-ldb.yaml.
  (Laurent)
* Mention pixel link is accessed via SCU firmware in 
fsl,imx8qxp-pixel-link.yaml.
  (Rob)
* Use enum instead of oneOf + const for the reg property of pixel combiner
  channels in fsl,imx8qxp-pixel-combiner.yaml. (Rob)
* Rewrite the function to find the next bridge in pixel link bridge driver
  by properly using OF APIs and dropping unnecessary DT validation. (Rob)
* Drop unnecessary port availability check in i.MX8qxp pixel link to DPI
  bridge driver.
* Drop unnecessary DT validation from i.MX8qxp LDB bridge driver.
* Use of_graph_get_endpoint_by_regs() and of_graph_get_remote_endpoint() to
  get the input remote endpoint in imx8qxp_ldb_set_di_id() of i.MX8qxp LDB
  bridge driver.
* Avoid using companion_port OF node after putting it in
  imx8qxp_ldb_parse_dt_companion() of i.MX8qxp LDB bridge driver.
* Drop unnecessary check for maximum available LDB channels from
  i.MX8qm LDB bridge driver.
* Mention i.MX8qm/qxp LDB official name 'pixel mapper' in i.MX8qm/qxp LDB
  bridge drivers and Kconfig help messages.

Liu Ying (14):
  phy: Add LVDS configuration options
  media: uapi: Add some RGB bus formats for i.MX8qm/qxp pixel combiner
  media: docs: Add some RGB bus formats for i.MX8qm/qxp pixel combiner
  dt-bindings: display: bridge: Add i.MX8qm/qxp pixel combiner binding
  drm/bridge: imx: Add i.MX8qm/qxp pixel combiner support
  dt-bindings: display: bridge: Add i.MX8qm/qxp display pixel link
binding
  drm/bridge: imx: Add i.MX8qm/qxp display pixel link support
  dt-bindings: display: bridge: Add i.MX8qxp pixel link to DPI binding
  drm/bridge: imx: Add i.MX8qxp pixel link to DPI support
  drm/bridge: imx: Add LDB driver helper support
  dt-bindings: display: bridge: Add i.MX8qm/qxp LVDS display bridge
binding
  drm/bridge: imx: Add LDB support for i.MX8qxp
  drm/bridge: imx: Add LDB support for i.MX8qm
  MAINTAINERS: add maintainer for DRM bridge drivers for i.MX SoCs

 .../bindings/display/bridge/fsl,imx8qxp-ldb.yaml   | 173 +
 .../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 144 +
 .../display/bridge/fsl,imx8qxp-pixel-link.yaml | 106 +++
 .../display/bridge/fsl,imx8qxp-pxl2dpi.yaml| 102 +++
 .../userspace-api/media/v4l/subdev-formats.rst | 156 +
 MAINTAINERS|  10 +
 drivers/gpu/drm/bridge/Kconfig |   2 +
 drivers/gpu/drm/bridge/Makefile|   1 +
 drivers/gpu/drm/bridge/imx/Kconfig |  52 ++
 drivers/gpu/drm/bridge/imx/Makefile|   6 +
 drivers/gpu/drm/bridge/imx/imx-ldb-helper.c| 248 +++
 drivers/gpu/drm/bridge/imx/imx8qm-ldb.c| 585 +
 drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c   | 719 +
 .../gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c| 452 +
 drivers/gpu/drm/bridge/imx/imx8qxp-pix

Re: [PATCH v10] staging: fbtft: add tearing signal detect

2021-01-28 Thread Kari Argillander

On Thu, Jan 28, 2021 at 09:42:58AM +0800, carlis wrote:
> On Thu, 28 Jan 2021 00:32:22 +0200
> Kari Argillander  wrote:
> > >  #include "fbtft.h"
> > >  
> > >  #define DRVNAME "fb_st7789v"
> > > @@ -66,6 +69,32 @@ enum st7789v_command {
> > >  #define MADCTL_MX BIT(6) /* bitmask for column address order */
> > >  #define MADCTL_MY BIT(7) /* bitmask for page address order */
> > >  
> > > +#define SPI_PANEL_TE_TIMEOUT 400 /* msecs */
> > > +static struct mutex te_mutex;/* mutex for set te gpio irq status
> > > */  
> > 
> > Space after ;
> hi, i have fix it in the patch v11
> > 

Yeah sorry. I accidentally review wrong patch. But mostly stuff are
still relevant.

> > > @@ -82,6 +111,33 @@ enum st7789v_command {
> > >   */
> > >  static int init_display(struct fbtft_par *par)
> > >  {
> > > + int rc;
> > > + struct device *dev = par->info->device;
> > > +
> > > + par->gpio.te = devm_gpiod_get_index_optional(dev, "te", 0,
> > > GPIOD_IN);
> > > + if (IS_ERR(par->gpio.te)) {
> > > + rc = PTR_ERR(par->gpio.te);
> > > + dev_err(par->info->device, "Failed to request te
> > > gpio: %d\n", rc);
> > > + return rc;
> > > + }  
> > 
> > You request with optinal and you still want to error out? We could
> > just continue and not care about that error. User will be happier if
> > device still works somehow.
> You mean i just delete this dev_err print ?!
> like this:
>   par->gpio.te = devm_gpiod_get_index_optional(dev, "te",
> 0,GPIOD_IN); 
> if (IS_ERR(par->gpio.te))
>   return PTR_ERR(par->gpio.te);

Not exactly. I'm suggesting something like this.

if (IS_ERR(par->gpio.te) == -EPROBE_DEFER) {
return -EPROBE_DEFER;

if (IS_ERR(par->gpio.te))
par-gpio.te = NULL;

This like beginning of your patch series but the difference is that if
EPROBE_DEFER then we will try again later. Any other error and we will
just ignore TE gpio. But this is up to you what you want to do. To me
this just seems place where this kind of logic can work.

> > > + if (par->gpio.te) {
> > > + set_spi_panel_te_irq_status(par, true);
> > > + reinit_completion(&spi_panel_te);
> > > + ret =
> > > wait_for_completion_timeout(&spi_panel_te,
> > > +
> > > msecs_to_jiffies(SPI_PANEL_TE_TIMEOUT));
> > > + if (ret == 0)  
> > 
> > !ret
> > 
> > > + dev_err(par->info->device, "wait
> > > panel TE time out\n");
> > > + }
> > > + ret = par->fbtftops.write(par, par->txbuf.buf,
> > > +  startbyte_size + to_copy
> > > * 2);
> > > + if (par->gpio.te)
> > > + set_spi_panel_te_irq_status(par, false);
> > > + if (ret < 0)
> > > + return ret;
> > > + remain -= to_copy;
> > > + }
> > > +
> > > + return ret;  
> > 
> > Do we want to return something over 0? If not then this can be return
> > 0. And then you do not need to even init ret value at the beginning.
> > 
> > Also wait little bit like Greg sayd before sending new version.
> > Someone might nack about what I say or say something more.
> > 
> hi, i copy fbtft_write_vmem16_bus8 from file fbtft_bus.c and modify it
> ,just add te wait logic, i will take more time to check this original
> function.

It might be ok or not. You should still check.
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[PATCH v11 8/9] soc: mediatek: add mtk mutex support for MT8183

From: Yongqiang Niu 

Add mtk mutex support for MT8183 SoC.

Signed-off-by: Yongqiang Niu 
Signed-off-by: Hsin-Yi Wang 
---
 drivers/soc/mediatek/mtk-mutex.c | 50 
 1 file changed, 50 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index f531b119da7a9..b348f962f82a4 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -14,6 +14,8 @@
 
 #define MT2701_MUTEX0_MOD0 0x2c
 #define MT2701_MUTEX0_SOF0 0x30
+#define MT8183_DISP_MUTEX0_MOD00x30
+#define MT8183_DISP_MUTEX0_SOF00x2c
 
 #define DISP_REG_MUTEX_EN(n)   (0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)  (0x24 + 0x20 * (n))
@@ -37,6 +39,18 @@
 #define MT8167_MUTEX_MOD_DISP_DITHER   15
 #define MT8167_MUTEX_MOD_DISP_UFOE 16
 
+#define MT8183_MUTEX_MOD_DISP_RDMA00
+#define MT8183_MUTEX_MOD_DISP_RDMA11
+#define MT8183_MUTEX_MOD_DISP_OVL0 9
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L  10
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L  11
+#define MT8183_MUTEX_MOD_DISP_WDMA012
+#define MT8183_MUTEX_MOD_DISP_COLOR0   13
+#define MT8183_MUTEX_MOD_DISP_CCORR0   14
+#define MT8183_MUTEX_MOD_DISP_AAL0 15
+#define MT8183_MUTEX_MOD_DISP_GAMMA0   16
+#define MT8183_MUTEX_MOD_DISP_DITHER0  17
+
 #define MT8173_MUTEX_MOD_DISP_OVL0 11
 #define MT8173_MUTEX_MOD_DISP_OVL1 12
 #define MT8173_MUTEX_MOD_DISP_RDMA013
@@ -87,6 +101,11 @@
 #define MT2712_MUTEX_SOF_DSI3  6
 #define MT8167_MUTEX_SOF_DPI0  2
 #define MT8167_MUTEX_SOF_DPI1  3
+#define MT8183_MUTEX_SOF_DSI0  1
+#define MT8183_MUTEX_SOF_DPI0  2
+
+#define MT8183_MUTEX_EOF_DSI0  (MT8183_MUTEX_SOF_DSI0 << 6)
+#define MT8183_MUTEX_EOF_DPI0  (MT8183_MUTEX_SOF_DPI0 << 6)
 
 struct mtk_mutex {
int id;
@@ -181,6 +200,20 @@ static const unsigned int 
mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
 };
 
+static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+   [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
+   [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
+   [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
+   [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
+   [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
+   [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
+   [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
+   [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
+   [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
+   [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
+   [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
+};
+
 static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
@@ -198,6 +231,13 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 
+ 1] = {
[MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
 };
 
+/* Add EOF setting so overlay hardware can receive frame done irq */
+static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+   [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+   [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
+   [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
+};
+
 static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -227,6 +267,14 @@ static const struct mtk_mutex_data 
mt8173_mutex_driver_data = {
.mutex_sof_reg = MT2701_MUTEX0_SOF0,
 };
 
+static const struct mtk_mutex_data mt8183_mutex_driver_data = {
+   .mutex_mod = mt8183_mutex_mod,
+   .mutex_sof = mt8183_mutex_sof,
+   .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0,
+   .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0,
+   .no_clk = true,
+};
+
 struct mtk_mutex *mtk_mutex_get(struct device *dev)
 {
struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
  .data = &mt8167_mutex_driver_data},
{ .compatible = "mediatek,mt8173-disp-mutex",
  .data = &mt8173_mutex_driver_data},
+   { .compatible = "mediatek,mt8183-disp-mutex",
+ .data = &mt8183_mutex_driver_data},
{},
 };
 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
-- 
2.30.0.280.ga3ce27912f-goog

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[PATCH v4 1/3] dt-bindings:drm/bridge:anx7625:add vendor define flags

Add 'bus-type' and 'data-lanes' define for port0, add HDCP support
flag and DP tx lane0 and lane1 swing register array define.

Signed-off-by: Xin Ji 
---
 .../bindings/display/bridge/analogix,anx7625.yaml  | 54 +-
 1 file changed, 53 insertions(+), 1 deletion(-)

diff --git 
a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml 
b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
index c789784..048deec 100644
--- a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
@@ -34,6 +34,24 @@ properties:
 description: used for reset chip control, RESET_N pin B7.
 maxItems: 1
 
+  analogix,lane0-swing:
+$ref: /schemas/types.yaml#/definitions/uint32-array
+maxItems: 20
+description:
+  an array of swing register setting for DP tx lane0 PHY, please don't
+  add this property, or contact vendor.
+
+  analogix,lane1-swing:
+$ref: /schemas/types.yaml#/definitions/uint32-array
+maxItems: 20
+description:
+  an array of swing register setting for DP tx lane1 PHY, please don't
+  add this property, or contact vendor.
+
+  analogix,hdcp-support:
+type: boolean
+description: indicate the DP tx HDCP support or not.
+
   ports:
 $ref: /schemas/graph.yaml#/properties/ports
 
@@ -41,13 +59,45 @@ properties:
   port@0:
 $ref: /schemas/graph.yaml#/properties/port
 description:
-  Video port for MIPI DSI input.
+  Video port for MIPI input.
+
+properties:
+  endpoint:
+type: object
+additionalProperties: false
+
+# Properties described in
+# Documentation/devicetree/bindings/media/video-interfaces.txt
+properties:
+  remote-endpoint: true
+  bus-type: true
+  data-lanes: true
+
+required:
+  - remote-endpoint
+
+required:
+  - endpoint
+
 
   port@1:
 $ref: /schemas/graph.yaml#/properties/port
 description:
   Video port for panel or connector.
 
+properties:
+  endpoint:
+type: object
+additionalProperties: false
+
+# Properties described in
+# Documentation/devicetree/bindings/media/video-interfaces.txt
+properties:
+  remote-endpoint: true
+
+required:
+  - remote-endpoint
+
 required:
   - port@0
   - port@1
@@ -81,6 +131,8 @@ examples:
 reg = <0>;
 anx7625_in: endpoint {
 remote-endpoint = <&mipi_dsi>;
+bus-type = <5>;
+data-lanes = <0 1 2 3>;
 };
 };
 
-- 
2.7.4

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[PATCH] drm/amdkfd: dqm fence memory corruption

2021-01-28 Thread Qu Huang

Amdgpu driver uses 4-byte data type as DQM fence memory,
and transmits GPU address of fence memory to microcode
through query status PM4 message. However, query status
PM4 message definition and microcode processing are all
processed according to 8 bytes. Fence memory only allocates
4 bytes of memory, but microcode does write 8 bytes of memory,
so there is a memory corruption.

Signed-off-by: Qu Huang 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index e686ce2..8b38d0c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1161,7 +1161,7 @@ static int start_cpsch(struct device_queue_manager *dqm)
pr_debug("Allocating fence memory\n");
 
/* allocate fence memory on the gart */
-   retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
+   retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(uint64_t),
&dqm->fence_mem);
 
if (retval)
-- 
1.8.3.1

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[PATCH v4 2/3] drm/bridge: anx7625: fix not correct return value

At some time, the original code may return non zero value, force return 0
if operation finished

Signed-off-by: Xin Ji 
---
 drivers/gpu/drm/bridge/analogix/anx7625.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c 
b/drivers/gpu/drm/bridge/analogix/anx7625.c
index 65cc059..04536cc 100644
--- a/drivers/gpu/drm/bridge/analogix/anx7625.c
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
@@ -189,10 +189,10 @@ static int wait_aux_op_finish(struct anx7625_data *ctx)
   AP_AUX_CTRL_STATUS);
if (val < 0 || (val & 0x0F)) {
DRM_DEV_ERROR(dev, "aux status %02x\n", val);
-   val = -EIO;
+   return -EIO;
}
 
-   return val;
+   return 0;
 }
 
 static int anx7625_video_mute_control(struct anx7625_data *ctx,
-- 
2.7.4

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[PATCH v3 05/14] drm/bridge: imx: Add i.MX8qm/qxp pixel combiner support

This patch adds a drm bridge driver for i.MX8qm/qxp pixel combiner.
The pixel combiner takes two output streams from a single display
controller and manipulates the two streams to support a number
of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured
as either one screen, two screens, or virtual screens.  The pixel
combiner is also responsible for generating some of the control signals
for the pixel link output channel.  For now, the driver only supports
the bypass mode.

Signed-off-by: Liu Ying 
---
v2->v3:
* No change.

v1->v2:
* No change.

 drivers/gpu/drm/bridge/Kconfig |   2 +
 drivers/gpu/drm/bridge/Makefile|   1 +
 drivers/gpu/drm/bridge/imx/Kconfig |   8 +
 drivers/gpu/drm/bridge/imx/Makefile|   1 +
 .../gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c| 452 +
 5 files changed, 464 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/imx/Kconfig
 create mode 100644 drivers/gpu/drm/bridge/imx/Makefile
 create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c

diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index e4110d6c..84944e0 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -256,6 +256,8 @@ source "drivers/gpu/drm/bridge/adv7511/Kconfig"
 
 source "drivers/gpu/drm/bridge/cadence/Kconfig"
 
+source "drivers/gpu/drm/bridge/imx/Kconfig"
+
 source "drivers/gpu/drm/bridge/synopsys/Kconfig"
 
 endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 86e7acc..bc80cae 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -27,4 +27,5 @@ obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o
 
 obj-y += analogix/
 obj-y += cadence/
+obj-y += imx/
 obj-y += synopsys/
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig 
b/drivers/gpu/drm/bridge/imx/Kconfig
new file mode 100644
index ..f1c91b6
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -0,0 +1,8 @@
+config DRM_IMX8QXP_PIXEL_COMBINER
+   tristate "Freescale i.MX8QM/QXP pixel combiner"
+   depends on OF
+   depends on COMMON_CLK
+   select DRM_KMS_HELPER
+   help
+ Choose this to enable pixel combiner found in
+ Freescale i.MX8qm/qxp processors.
diff --git a/drivers/gpu/drm/bridge/imx/Makefile 
b/drivers/gpu/drm/bridge/imx/Makefile
new file mode 100644
index ..7d7c8d6
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c 
b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
new file mode 100644
index ..cd5b1be
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
@@ -0,0 +1,452 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#define PC_CTRL_REG0x0
+#define  PC_COMBINE_ENABLE BIT(0)
+#define  PC_DISP_BYPASS(n) BIT(1 + 21 * (n))
+#define  PC_DISP_HSYNC_POLARITY(n) BIT(2 + 11 * (n))
+#define  PC_DISP_HSYNC_POLARITY_POS(n) DISP_HSYNC_POLARITY(n)
+#define  PC_DISP_VSYNC_POLARITY(n) BIT(3 + 11 * (n))
+#define  PC_DISP_VSYNC_POLARITY_POS(n) DISP_VSYNC_POLARITY(n)
+#define  PC_DISP_DVALID_POLARITY(n)BIT(4 + 11 * (n))
+#define  PC_DISP_DVALID_POLARITY_POS(n)DISP_DVALID_POLARITY(n)
+#define  PC_VSYNC_MASK_ENABLE  BIT(5)
+#define  PC_SKIP_MODE  BIT(6)
+#define  PC_SKIP_NUMBER_MASK   GENMASK(12, 7)
+#define  PC_SKIP_NUMBER(n) FIELD_PREP(PC_SKIP_NUMBER_MASK, (n))
+#define  PC_DISP0_PIX_DATA_FORMAT_MASK GENMASK(18, 16)
+#define  PC_DISP0_PIX_DATA_FORMAT(fmt) \
+   FIELD_PREP(PC_DISP0_PIX_DATA_FORMAT_MASK, (fmt))
+#define  PC_DISP1_PIX_DATA_FORMAT_MASK GENMASK(21, 19)
+#define  PC_DISP1_PIX_DATA_FORMAT(fmt) \
+   FIELD_PREP(PC_DISP1_PIX_DATA_FORMAT_MASK, (fmt))
+
+#define PC_BUF_PARA_REG0x10
+#define  PC_BUF_ACTIVE_DEPTH_MASK  GENMASK(10, 0)
+#define  PC_BUF_ACTIVE_DEPTH(n)
FIELD_PREP(PC_BUF_ACTIVE_DEPTH_MASK, (n))
+
+#define PC_SW_RESET_REG0x20
+#define  PC_SW_RESET_N BIT(0)
+#define  PC_DISP_SW_RESET_N(n) BIT(1 + (n))
+#define  PC_FULL_RESET_N   (PC_SW_RESET_N |\
+PC_DISP_SW_RESET_N(0) |\
+PC_DISP_SW_RESET_N(1))
+
+#define PC_REG_SET 0x4
+#define PC_REG_CLR 0x8
+
+#define DRIVER_NAME"imx8qxp-pixel-combiner"
+
+enum imx8qxp_pc_pix_data_format {
+   RGB,
+   YUV444,
+   YUV422,
+   SPLIT_RGB,
+};
+
+stru

Re: linux-next: Tree for Jan 27 (drm/i915)

On 1/27/21 11:30 AM, Randy Dunlap wrote:
> On 1/27/21 11:08 AM, Randy Dunlap wrote:
>> On 1/27/21 6:44 AM, Stephen Rothwell wrote:
>>> Hi all,
>>>
>>> Note: the patch file has failed to upload :-(
>>>
>>> Changes since 20210125:
>>>
>>
>> on x86_64:
>>
>> ../drivers/gpu/drm/i915/i915_gem.c: In function ‘i915_gem_freeze_late’:
>> ../drivers/gpu/drm/i915/i915_gem.c:1182:2: error: implicit declaration of 
>> function ‘wbinvd_on_all_cpus’; did you mean ‘wrmsr_on_cpus’? 
>> [-Werror=implicit-function-declaration]
>>   wbinvd_on_all_cpus();
>>
> 
> My apologies: this was in Andrew's mmotm 2021-01-25.
> Sorry about that.


and now I see that it also happens in today's linux-next.

-- 
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[PATCH v3 11/14] dt-bindings: display: bridge: Add i.MX8qm/qxp LVDS display bridge binding

This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB).

Signed-off-by: Liu Ying 
---
v2->v3:
* Drop 'fsl,syscon' property. (Rob)
* Mention the CSR module controls LDB.

v1->v2:
* Use graph schema. (Laurent)
* Side note i.MX8qxp LDB official name 'pixel mapper'. (Laurent)

 .../bindings/display/bridge/fsl,imx8qxp-ldb.yaml   | 173 +
 1 file changed, 173 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml

diff --git 
a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml 
b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
new file mode 100644
index ..9454300
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
@@ -0,0 +1,173 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp LVDS Display Bridge
+
+maintainers:
+  - Liu Ying 
+
+description: |
+  The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
+
+  The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) 
module.
+  The CSR module, as a system controller, contains the LDB's configuration
+  registers.
+
+  For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
+  format and can map the input to VESA or JEIDA standards.  The two channels
+  cannot be used simultaneously, that is to say, the user should pick one of
+  them to use.  Two LDB channels from two LDB instances can work together in
+  LDB split mode to support a dual link LVDS display.  The channel indexes
+  have to be different.  Channel0 outputs odd pixels and channel1 outputs
+  even pixels.
+
+  For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
+  input color format.  The two channels can be used simultaneously, either
+  in dual mode or split mode.  In dual mode, the two channels output identical
+  data.  In split mode, channel0 outputs odd pixels and channel1 outputs even
+  pixels.
+
+  A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in
+  the SoC reference manuals.  The pixel mapper uses logic of LDBs embedded in
+  i.MX6qdl/sx SoCs, i.e., it is essentially based on them.  To keep the naming
+  consistency, this binding calls it LDB.
+
+properties:
+  compatible:
+enum:
+  - fsl,imx8qm-ldb
+  - fsl,imx8qxp-ldb
+
+  "#address-cells":
+const: 1
+
+  "#size-cells":
+const: 0
+
+  clocks:
+items:
+  - description: pixel clock
+  - description: bypass clock
+
+  clock-names:
+items:
+  - const: pixel
+  - const: bypass
+
+  power-domains:
+maxItems: 1
+
+  fsl,companion-ldb:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: |
+  A phandle which points to companion LDB which is used in LDB split mode.
+
+patternProperties:
+  "^channel@[0-1]$":
+type: object
+description: Represents a channel of LDB.
+
+properties:
+  "#address-cells":
+const: 1
+
+  "#size-cells":
+const: 0
+
+  reg:
+description: The channel index.
+enum: [ 0, 1 ]
+
+  phys:
+description: A phandle to the phy module representing the LVDS PHY.
+maxItems: 1
+
+  phy-names:
+const: lvds_phy
+
+  port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description: Input port of the channel.
+
+  port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description: Output port of the channel.
+
+required:
+  - "#address-cells"
+  - "#size-cells"
+  - reg
+  - phys
+  - phy-names
+
+additionalProperties: false
+
+required:
+  - compatible
+  - "#address-cells"
+  - "#size-cells"
+  - clocks
+  - clock-names
+  - power-domains
+  - channel@0
+  - channel@1
+
+allOf:
+  - if:
+  properties:
+compatible:
+  contains:
+const: fsl,imx8qm-ldb
+then:
+  properties:
+fsl,companion-ldb: false
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+ldb {
+#address-cells = <1>;
+#size-cells = <0>;
+compatible = "fsl,imx8qxp-ldb";
+clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
+ <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
+clock-names = "pixel", "bypass";
+power-domains = <&pd IMX_SC_R_LVDS_0>;
+
+channel@0 {
+#address-cells = <1>;
+#size-cells = <0>;
+reg = <0>;
+phys = <&mipi_lvds_0_phy>;
+phy-names = "lvds_phy";
+
+port@0 {
+reg = <0>;
+
+mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
+remote-endpoint = 
<&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
+};
+};
+};
+
+channel@1

[PATCH v11 4/9] drm/mediatek: add mtk_dither_set_common() function

Current implementation of mtk_dither_set() cast dev data to
struct mtk_ddp_comp_dev. But other devices with different dev data
would also call this function.

Separate necessary parameters out so other device components (dither,
gamma) can call this function.

Signed-off-by: Hsin-Yi Wang 
---
 drivers/gpu/drm/mediatek/mtk_disp_drv.h |  4 
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 25 +
 2 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h 
b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 46d199b7b4a29..c50d5fc9fd349 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -17,6 +17,10 @@ void mtk_color_config(struct device *dev, unsigned int w,
  unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
 void mtk_color_start(struct device *dev);
 
+void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg 
*cmdq_reg,
+  unsigned int bpc, unsigned int CFG,
+  struct cmdq_pkt *cmdq_pkt);
+
 void mtk_dpi_start(struct device *dev);
 void mtk_dpi_stop(struct device *dev);
 
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 7b5293429426d..53d25823a37cc 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -151,33 +151,40 @@ static void mtk_ddp_clk_disable(struct device *dev)
clk_disable_unprepare(priv->clk);
 }
 
-static void mtk_dither_set(struct device *dev, unsigned int bpc,
-   unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
-{
-   struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 
+void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg 
*cmdq_reg,
+  unsigned int bpc, unsigned int CFG, struct cmdq_pkt 
*cmdq_pkt)
+{
/* If bpc equal to 0, the dithering function didn't be enabled */
if (bpc == 0)
return;
 
if (bpc >= MTK_MIN_BPC) {
-   mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, 
DISP_DITHER_5);
-   mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, 
DISP_DITHER_7);
+   mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
+   mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
mtk_ddp_write(cmdq_pkt,
  DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
  DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
  DITHER_NEW_BIT_MODE,
- &priv->cmdq_reg, priv->regs, DISP_DITHER_15);
+ cmdq_reg, regs, DISP_DITHER_15);
mtk_ddp_write(cmdq_pkt,
  DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
  DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
  DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
  DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
- &priv->cmdq_reg, priv->regs, DISP_DITHER_16);
-   mtk_ddp_write(cmdq_pkt, DISP_DITHERING, &priv->cmdq_reg, 
priv->regs, CFG);
+ cmdq_reg, regs, DISP_DITHER_16);
+   mtk_ddp_write(cmdq_pkt, DISP_DITHERING, cmdq_reg, regs, CFG);
}
 }
 
+static void mtk_dither_set(struct device *dev, unsigned int bpc,
+   unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
+{
+   struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+   mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, CFG, cmdq_pkt);
+}
+
 static void mtk_od_config(struct device *dev, unsigned int w,
  unsigned int h, unsigned int vrefresh,
  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
-- 
2.30.0.280.ga3ce27912f-goog

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[PATCH v11 0/9] drm/mediatek: add support for mediatek SOC MT8183

This series is based on kernel/git/chunkuang.hu/linux.git mediatek-drm-next
The series is tested on a mt8183 krane device.

Change since v10
- fix review comments in v9

Change since v9
- change several function to rebase to mediatek-drm-next

Change since v8
- fix some review comment in v8
- separate gamma module for mt8183 has no dither function in gamma
- enable dither function for 5 or 6 bpc panel display
- separate ddp mutex patch from the whole Soc patch

Change since v7
- add dt-binding for mt8183 display
- base mmsys patch
https://patchwork.kernel.org/project/linux-mediatek/cover/1607506379-10998-1-git-send-email-yongqiang@mediatek.com/
- base dts patch
https://patchwork.kernel.org/project/linux-mediatek/cover/20201127104930.1981497-1-enric.balle...@collabora.com/
- add mt8183 function call for setting the routing registers
- add RDMA fifo size error handle

Change since v6
- move ddp component define into mtk_mmsys.h
- add mmsys private data to support different ic path connection
- add mt8183-mmsys.c to support 8183 path connection
- fix reviewed issue in v6

Change since v5
- fix reviewed issue in v5
base https://patchwork.kernel.org/project/linux-mediatek/list/?series=213219

Change since v4
- fix reviewed issue in v4

Change since v3
- fix reviewed issue in v3
- fix type error in v3
- fix conflict with iommu patch

Change since v2
- fix reviewed issue in v2
- add mutex node into dts file

Changes since v1:
- fix reviewed issue in v1
- add dts for mt8183 display nodes
- adjust display clock control flow in patch 22
- add vmap support for mediatek drm in patch 23
- fix page offset issue for mmap function in patch 24
- enable allow_fb_modifiers for mediatek drm in patch 25


Hsin-Yi Wang (1):
  drm/mediatek: add mtk_dither_set_common() function

Yongqiang Niu (8):
  arm64: dts: mt8183: rename rdma fifo size
  arm64: dts: mt8183: refine gamma compatible name
  drm/mediatek: add RDMA fifo size error handle
  drm/mediatek: separate gamma module
  drm/mediatek: add has_dither private data for gamma
  drm/mediatek: enable dither function
  soc: mediatek: add mtk mutex support for MT8183
  drm/mediatek: add support for mediatek SOC MT8183

 arch/arm64/boot/dts/mediatek/mt8183.dtsi|   7 +-
 drivers/gpu/drm/mediatek/Makefile   |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h |  14 ++
 drivers/gpu/drm/mediatek/mtk_disp_gamma.c   | 196 
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c |  18 ++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c|  10 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 138 +++---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  49 -
 drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   1 +
 drivers/soc/mediatek/mtk-mutex.c|  50 +
 10 files changed, 410 insertions(+), 74 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_gamma.c

-- 
2.30.0.280.ga3ce27912f-goog

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[PATCH v10] staging: fbtft: add tearing signal detect

From: zhangxuezhi 

For st7789v ic,when we need continuous full screen refresh, it is best to
wait for the TE signal arrive to avoid screen tearing

Signed-off-by: zhangxuezhi 
---
v10: additional notes
v9: change pr_* to dev_*
v8: delete a log line
v7: return error value when request fail
v6: add te gpio request fail deal logic
v5: fix log print
v4: modify some code style and change te irq set function name
v3: modify author and signed-off-by name
v2: add release te gpio after irq request fail
---
 drivers/staging/fbtft/fb_st7789v.c | 132 -
 drivers/staging/fbtft/fbtft.h  |   1 +
 2 files changed, 132 insertions(+), 1 deletion(-)

diff --git a/drivers/staging/fbtft/fb_st7789v.c 
b/drivers/staging/fbtft/fb_st7789v.c
index 3a280cc..cba08a8 100644
--- a/drivers/staging/fbtft/fb_st7789v.c
+++ b/drivers/staging/fbtft/fb_st7789v.c
@@ -9,9 +9,12 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #include 
 #include 
-
+#include 
 #include "fbtft.h"
 
 #define DRVNAME "fb_st7789v"
@@ -66,6 +69,32 @@ enum st7789v_command {
 #define MADCTL_MX BIT(6) /* bitmask for column address order */
 #define MADCTL_MY BIT(7) /* bitmask for page address order */
 
+#define SPI_PANEL_TE_TIMEOUT   400 /* msecs */
+static struct mutex te_mutex;/* mutex for set te gpio irq status */
+static struct completion spi_panel_te;
+
+static irqreturn_t spi_panel_te_handler(int irq, void *data)
+{
+   complete(&spi_panel_te);
+   return IRQ_HANDLED;
+}
+
+static void set_spi_panel_te_irq_status(struct fbtft_par *par, bool enable)
+{
+   static int te_irq_count;
+
+   mutex_lock(&te_mutex);
+
+   if (enable) {
+   if (++te_irq_count == 1)
+   enable_irq(gpiod_to_irq(par->gpio.te));
+   } else {
+   if (--te_irq_count == 0)
+   disable_irq(gpiod_to_irq(par->gpio.te));
+   }
+   mutex_unlock(&te_mutex);
+}
+
 /**
  * init_display() - initialize the display controller
  *
@@ -82,6 +111,33 @@ enum st7789v_command {
  */
 static int init_display(struct fbtft_par *par)
 {
+   int rc;
+   struct device *dev = par->info->device;
+
+   par->gpio.te = devm_gpiod_get_index_optional(dev, "te", 0, GPIOD_IN);
+   if (IS_ERR(par->gpio.te)) {
+   rc = PTR_ERR(par->gpio.te);
+   dev_err(par->info->device, "Failed to request te gpio: %d\n", 
rc);
+   return rc;
+   }
+   if (par->gpio.te) {
+   init_completion(&spi_panel_te);
+   mutex_init(&te_mutex);
+   rc = devm_request_irq(dev,
+ gpiod_to_irq(par->gpio.te),
+spi_panel_te_handler, IRQF_TRIGGER_RISING,
+"TE_GPIO", par);
+   if (rc) {
+   dev_err(par->info->device, "TE request_irq failed.\n");
+   devm_gpiod_put(dev, par->gpio.te);
+   return rc;
+   }
+
+   disable_irq_nosync(gpiod_to_irq(par->gpio.te));
+   } else {
+   dev_info(par->info->device, "%s:%d, TE gpio not specified\n",
+__func__, __LINE__);
+   }
/* turn off sleep mode */
write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE);
mdelay(120);
@@ -137,6 +193,9 @@ static int init_display(struct fbtft_par *par)
 */
write_reg(par, PWCTRL1, 0xA4, 0xA1);
 
+/*Tearing Effect Line On*/
+   if (par->gpio.te)
+   write_reg(par, 0x35, 0x00);
write_reg(par, MIPI_DCS_SET_DISPLAY_ON);
 
if (HSD20_IPS)
@@ -145,6 +204,76 @@ static int init_display(struct fbtft_par *par)
return 0;
 }
 
+/*
+ *
+ *   int (*write_vmem)(struct fbtft_par *par);
+ *
+ */
+
+/* 16 bit pixel over 8-bit databus */
+static int st7789v_write_vmem16_bus8(struct fbtft_par *par, size_t offset, 
size_t len)
+{
+   u16 *vmem16;
+   __be16 *txbuf16 = par->txbuf.buf;
+   size_t remain;
+   size_t to_copy;
+   size_t tx_array_size;
+   int i;
+   int ret = 0;
+   size_t startbyte_size = 0;
+
+   fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "st7789v ---%s(offset=%zu, 
len=%zu)\n",
+ __func__, offset, len);
+
+   remain = len / 2;
+   vmem16 = (u16 *)(par->info->screen_buffer + offset);
+
+   if (par->gpio.dc)
+   gpiod_set_value(par->gpio.dc, 1);
+
+   /* non buffered write */
+   if (!par->txbuf.buf)
+   return par->fbtftops.write(par, vmem16, len);
+
+   /* buffered write */
+   tx_array_size = par->txbuf.len / 2;
+
+   if (par->startbyte) {
+   txbuf16 = par->txbuf.buf + 1;
+   tx_array_size -= 2;
+   *(u8 *)(par->txbuf.buf) = par->startbyte | 0x2;
+

[PATCH v3 08/14] dt-bindings: display: bridge: Add i.MX8qxp pixel link to DPI binding

This patch adds bindings for i.MX8qxp pixel link to DPI(PXL2DPI).

Signed-off-by: Liu Ying 
---
v2->v3:
* Drop 'fsl,syscon' property. (Rob)
* Mention the CSR module controls PXL2DPI.

v1->v2:
* Use graph schema. (Laurent)

 .../display/bridge/fsl,imx8qxp-pxl2dpi.yaml| 102 +
 1 file changed, 102 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml

diff --git 
a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml 
b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
new file mode 100644
index ..6112095
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
+
+maintainers:
+  - Liu Ying 
+
+description: |
+  The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
+  interfaces the pixel link 36-bit data output and the DSI controller’s
+  MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
+  used in LVDS mode, to remap the pixel color codings between those modules.
+  This module is purely combinatorial.
+
+  The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) 
module.
+  The CSR module, as a system controller, contains the PXL2DPI's configuration
+  register.
+
+properties:
+  compatible:
+const: fsl,imx8qxp-pxl2dpi
+
+  power-domains:
+maxItems: 1
+
+  fsl,companion-pxl2dpi:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: |
+  A phandle which points to companion PXL2DPI which is used by downstream
+  LVDS Display Bridge(LDB) in split mode.
+
+  ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+  port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description: The PXL2DPI input port node from pixel link.
+
+  port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description: The PXL2DPI output port node to downstream bridge.
+
+required:
+  - port@0
+  - port@1
+
+required:
+  - compatible
+  - power-domains
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+pxl2dpi {
+compatible = "fsl,imx8qxp-pxl2dpi";
+power-domains = <&pd IMX_SC_R_MIPI_0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+#address-cells = <1>;
+#size-cells = <0>;
+reg = <0>;
+
+mipi_lvds_0_pxl2dpi_dc_pixel_link0: endpoint@0 {
+reg = <0>;
+remote-endpoint = <&dc_pixel_link0_mipi_lvds_0_pxl2dpi>;
+};
+
+mipi_lvds_0_pxl2dpi_dc_pixel_link1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>;
+};
+};
+
+port@1 {
+#address-cells = <1>;
+#size-cells = <0>;
+reg = <1>;
+
+mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
+reg = <0>;
+remote-endpoint = 
<&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
+};
+
+mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
+reg = <1>;
+remote-endpoint = 
<&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
+};
+};
+};
+};
-- 
2.7.4

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[PATCH V4] drm/stm: Fix bus_flags handling

2021-01-28 Thread Marek Vasut

The drm_display_mode_to_videomode() does not populate DISPLAY_FLAGS_DE_LOW
or DISPLAY_FLAGS_PIXDATA_NEGEDGE flags in struct videomode. Therefore, no
matter what polarity the next bridge or display might require, these flags
are never set, and thus the LTDC GCR_DEPOL and GCR_PCPOL bits are never set,
and the LTDC behaves as if both DISPLAY_FLAGS_PIXDATA_POSEDGE and
DISPLAY_FLAGS_DE_HIGH were always set.

The fix for this problem is taken almost verbatim from MXSFB driver. In
case there is a bridge attached to the LTDC, the bridge might have extra
polarity requirements, so extract bus_flags from the bridge and use them
for LTDC configuration. Otherwise, extract bus_flags from the connector,
which is the display.

Fixes: b759012c5fa7 ("drm/stm: Add STM32 LTDC driver")
Signed-off-by: Marek Vasut 
Signed-off-by: Yannick Fertre 
Cc: Alexandre Torgue 
Cc: Antonio Borneo 
Cc: Benjamin Gaignard 
Cc: Maxime Coquelin 
Cc: Philippe Cornu 
Cc: Sam Ravnborg 
Cc: Vincent Abriou 
Cc: Yannick Fertre 
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-st...@st-md-mailman.stormreply.com
To: dri-devel@lists.freedesktop.org
---
V2: Check if ldev->bridge->timings is non-NULL before accessing it
V3: get bus_flags from connector (from Yannick)
- Display controller could support several connectors (not connected at
  the same time). ie: stm32mp15c-DK2 board have 2 connectors (HDMI + DSI).
  Driver check which connector is connected to get the bus flag.
V4: get bridge from encoder (from Yannick)
---
 drivers/gpu/drm/stm/ltdc.c | 33 +++--
 1 file changed, 31 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 6e28e6b60e72..acc9f6694eb6 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -544,13 +544,42 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
 {
struct ltdc_device *ldev = crtc_to_ltdc(crtc);
struct drm_device *ddev = crtc->dev;
+   struct drm_connector_list_iter iter;
+   struct drm_connector *connector = NULL;
+   struct drm_encoder *encoder = NULL;
+   struct drm_bridge *bridge = NULL;
struct drm_display_mode *mode = &crtc->state->adjusted_mode;
struct videomode vm;
u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
u32 total_width, total_height;
+   u32 bus_flags = 0;
u32 val;
int ret;
 
+   /* get encoder from crtc */
+   drm_for_each_encoder(encoder, ddev)
+   if (encoder->crtc == crtc)
+   break;
+
+   if (encoder) {
+   /* get bridge from encoder */
+   list_for_each_entry(bridge, &encoder->bridge_chain, chain_node)
+   if (bridge->encoder == encoder)
+   break;
+
+   /* Get the connector from encoder */
+   drm_connector_list_iter_begin(ddev, &iter);
+   drm_for_each_connector_iter(connector, &iter)
+   if (connector->encoder == encoder)
+   break;
+   drm_connector_list_iter_end(&iter);
+   }
+
+   if (bridge && bridge->timings)
+   bus_flags = bridge->timings->input_bus_flags;
+   else if (connector)
+   bus_flags = connector->display_info.bus_flags;
+
if (!pm_runtime_active(ddev->dev)) {
ret = pm_runtime_get_sync(ddev->dev);
if (ret) {
@@ -586,10 +615,10 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
val |= GCR_VSPOL;
 
-   if (vm.flags & DISPLAY_FLAGS_DE_LOW)
+   if (bus_flags & DRM_BUS_FLAG_DE_LOW)
val |= GCR_DEPOL;
 
-   if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
+   if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
val |= GCR_PCPOL;
 
reg_update_bits(ldev->regs, LTDC_GCR,
-- 
2.29.2

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[PATCH v3 02/14] media: uapi: Add some RGB bus formats for i.MX8qm/qxp pixel combiner

This patch adds RGB666_1X30_CPADLO, RGB888_1X30_CPADLO, RGB666_1X36_CPADLO
and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp pixel combiner.
The RGB pixels with padding low per component are transmitted on a 30-bit
input bus(10-bit per component) from a display controller or a 36-bit
output bus(12-bit per component) to a pixel link.

Signed-off-by: Liu Ying 
---
v2->v3:
* No change.

v1->v2:
* No change.

 include/uapi/linux/media-bus-format.h | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/include/uapi/linux/media-bus-format.h 
b/include/uapi/linux/media-bus-format.h
index 0dfc11e..ec3323d 100644
--- a/include/uapi/linux/media-bus-format.h
+++ b/include/uapi/linux/media-bus-format.h
@@ -34,7 +34,7 @@
 
 #define MEDIA_BUS_FMT_FIXED0x0001
 
-/* RGB - next is   0x101e */
+/* RGB - next is   0x1022 */
 #define MEDIA_BUS_FMT_RGB444_1X12  0x1016
 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE  0x1001
 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE  0x1002
@@ -59,9 +59,13 @@
 #define MEDIA_BUS_FMT_RGB888_3X8_DELTA 0x101d
 #define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG0x1011
 #define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA   0x1012
+#define MEDIA_BUS_FMT_RGB666_1X30_CPADLO   0x101e
+#define MEDIA_BUS_FMT_RGB888_1X30_CPADLO   0x101f
 #define MEDIA_BUS_FMT_ARGB_1X320x100d
 #define MEDIA_BUS_FMT_RGB888_1X32_PADHI0x100f
 #define MEDIA_BUS_FMT_RGB101010_1X30   0x1018
+#define MEDIA_BUS_FMT_RGB666_1X36_CPADLO   0x1020
+#define MEDIA_BUS_FMT_RGB888_1X36_CPADLO   0x1021
 #define MEDIA_BUS_FMT_RGB121212_1X36   0x1019
 #define MEDIA_BUS_FMT_RGB161616_1X48   0x101a
 
-- 
2.7.4

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[PATCH v3 04/14] dt-bindings: display: bridge: Add i.MX8qm/qxp pixel combiner binding

This patch adds bindings for i.MX8qm/qxp pixel combiner.

Reviewed-by: Rob Herring 
Signed-off-by: Liu Ying 
---
v2->v3:
* Add Rob's R-b tag.

v1->v2:
* Use graph schema. (Laurent)
* Use enum instead of oneOf + const for the reg property of pixel combiner
  channels. (Rob)

 .../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 144 +
 1 file changed, 144 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml

diff --git 
a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
 
b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
new file mode 100644
index ..50bae21
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: 
http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Pixel Combiner
+
+maintainers:
+  - Liu Ying 
+
+description: |
+  The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
+  single display controller and manipulates the two streams to support a number
+  of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as
+  either one screen, two screens, or virtual screens.  The pixel combiner is
+  also responsible for generating some of the control signals for the pixel 
link
+  output channel.
+
+properties:
+  compatible:
+enum:
+  - fsl,imx8qm-pixel-combiner
+  - fsl,imx8qxp-pixel-combiner
+
+  "#address-cells":
+const: 1
+
+  "#size-cells":
+const: 0
+
+  reg:
+maxItems: 1
+
+  clocks:
+maxItems: 1
+
+  clock-names:
+const: apb
+
+  power-domains:
+maxItems: 1
+
+patternProperties:
+  "^channel@[0-1]$":
+type: object
+description: Represents a display stream of pixel combiner.
+
+properties:
+  "#address-cells":
+const: 1
+
+  "#size-cells":
+const: 0
+
+  reg:
+description: The display stream index.
+enum: [ 0, 1 ]
+
+  port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description: Input endpoint of the display stream.
+
+  port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description: Output endpoint of the display stream.
+
+required:
+  - "#address-cells"
+  - "#size-cells"
+  - reg
+  - port@0
+  - port@1
+
+additionalProperties: false
+
+required:
+  - compatible
+  - "#address-cells"
+  - "#size-cells"
+  - reg
+  - clocks
+  - clock-names
+  - power-domains
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+#include 
+pixel-combiner@5602 {
+compatible = "fsl,imx8qxp-pixel-combiner";
+#address-cells = <1>;
+#size-cells = <0>;
+reg = <0x5602 0x1>;
+clocks = <&dc0_pixel_combiner_lpcg IMX_LPCG_CLK_4>;
+clock-names = "apb";
+power-domains = <&pd IMX_SC_R_DC_0>;
+
+channel@0 {
+#address-cells = <1>;
+#size-cells = <0>;
+reg = <0>;
+
+port@0 {
+reg = <0>;
+
+dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint {
+remote-endpoint = <&dc0_dpu_disp0_dc0_pixel_combiner_ch0>;
+};
+};
+
+port@1 {
+reg = <1>;
+
+dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint {
+remote-endpoint = 
<&dc0_pixel_link0_dc0_pixel_combiner_ch0>;
+};
+};
+};
+
+channel@1 {
+#address-cells = <1>;
+#size-cells = <0>;
+reg = <1>;
+
+port@0 {
+reg = <0>;
+
+dc0_pixel_combiner_ch1_dc0_dpu_disp1: endpoint {
+remote-endpoint = <&dc0_dpu_disp1_dc0_pixel_combiner_ch1>;
+};
+};
+
+port@1 {
+reg = <1>;
+
+dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint {
+remote-endpoint = 
<&dc0_pixel_link1_dc0_pixel_combiner_ch1>;
+};
+};
+};
+};
-- 
2.7.4

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[PATCH] drm/msm/mdp5: Fix wait-for-commit for cmd panels

2021-01-28 Thread Iskren Chernev

Before the offending commit in msm_atomic_commit_tail wait_flush was
called once per frame, after the commit was submitted. After it
wait_flush is also called at the beginning to ensure previous
potentially async commits are done.

For cmd panels the source of wait_flush is a ping-pong irq notifying
a completion. The completion needs to be notified with complete_all so
multiple waiting parties (new async committers) can proceed.

Signed-off-by: Iskren Chernev 
Suggested-by: Rob Clark 
Fixes: 2d99ced787e3d ("drm/msm: async commit support")
---
 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index 0c8f9f88301fa..f5d71b2740793 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -1180,7 +1180,7 @@ static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, 
uint32_t irqstatus)
struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc,
pp_done);
 
-   complete(&mdp5_crtc->pp_completion);
+   complete_all(&mdp5_crtc->pp_completion);
 }
 
 static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc)

base-commit: 59fa6a163ffabc1bf25c5e0e33899e268a96d3cc
-- 
2.30.0

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[PATCH v4 3/3] drm/bridge: anx7625: add MIPI DPI input feature support

Add MIPI rx DPI input support

Reported-by: kernel test robot 
Signed-off-by: Xin Ji 
---
 drivers/gpu/drm/bridge/analogix/anx7625.c | 326 --
 drivers/gpu/drm/bridge/analogix/anx7625.h |  20 +-
 2 files changed, 285 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c 
b/drivers/gpu/drm/bridge/analogix/anx7625.c
index 04536cc..628ae43 100644
--- a/drivers/gpu/drm/bridge/analogix/anx7625.c
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
@@ -150,18 +150,18 @@ static int anx7625_write_and(struct anx7625_data *ctx,
return anx7625_reg_write(ctx, client, offset, (val & (mask)));
 }
 
-static int anx7625_write_and_or(struct anx7625_data *ctx,
-   struct i2c_client *client,
-   u8 offset, u8 and_mask, u8 or_mask)
+static int anx7625_config_bit_matrix(struct anx7625_data *ctx)
 {
-   int val;
+   int i, ret;
 
-   val = anx7625_reg_read(ctx, client, offset);
-   if (val < 0)
-   return val;
+   ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client,
+  AUDIO_CONTROL_REGISTER, 0x80);
+   for (i = 0; i < 13; i++)
+   ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
+VIDEO_BIT_MATRIX_12 + i,
+0x18 + i);
 
-   return anx7625_reg_write(ctx, client,
-offset, (val & and_mask) | (or_mask));
+   return ret;
 }
 
 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx)
@@ -195,6 +195,60 @@ static int wait_aux_op_finish(struct anx7625_data *ctx)
return 0;
 }
 
+static int anx7625_aux_dpcd_read(struct anx7625_data *ctx,
+u8 addrh, u8 addrm, u8 addrl,
+u8 len, u8 *buf)
+{
+   struct device *dev = &ctx->client->dev;
+   int ret;
+   u8 cmd;
+
+   if (len > MAX_DPCD_BUFFER_SIZE) {
+   DRM_DEV_ERROR(dev, "exceed aux buffer len.\n");
+   return -EINVAL;
+   }
+
+   cmd = ((len - 1) << 4) | 0x09;
+
+   /* Set command and length */
+   ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
+   AP_AUX_COMMAND, cmd);
+
+   /* Set aux access address */
+   ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
+AP_AUX_ADDR_7_0, addrl);
+   ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
+AP_AUX_ADDR_15_8, addrm);
+   ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
+AP_AUX_ADDR_19_16, addrh);
+
+   /* Enable aux access */
+   ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
+   AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
+
+   if (ret < 0) {
+   DRM_DEV_ERROR(dev, "cannot access aux related register.\n");
+   return -EIO;
+   }
+
+   usleep_range(2000, 2100);
+
+   ret = wait_aux_op_finish(ctx);
+   if (ret) {
+   DRM_DEV_ERROR(dev, "aux IO error: wait aux op finish.\n");
+   return ret;
+   }
+
+   ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
+AP_AUX_BUFF_START, len, buf);
+   if (ret < 0) {
+   DRM_DEV_ERROR(dev, "read dpcd register failed\n");
+   return -EIO;
+   }
+
+   return 0;
+}
+
 static int anx7625_video_mute_control(struct anx7625_data *ctx,
  u8 status)
 {
@@ -219,38 +273,6 @@ static int anx7625_video_mute_control(struct anx7625_data 
*ctx,
return ret;
 }
 
-static int anx7625_config_audio_input(struct anx7625_data *ctx)
-{
-   struct device *dev = &ctx->client->dev;
-   int ret;
-
-   /* Channel num */
-   ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
-   AUDIO_CHANNEL_STATUS_6, I2S_CH_2 << 5);
-
-   /* FS */
-   ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
-   AUDIO_CHANNEL_STATUS_4,
-   0xf0, AUDIO_FS_48K);
-   /* Word length */
-   ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
-   AUDIO_CHANNEL_STATUS_5,
-   0xf0, AUDIO_W_LEN_24_24MAX);
-   /* I2S */
-   ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client,
-   AUDIO_CHANNEL_STATUS_6, I2S_SLAVE_MODE);
-   ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client,
-AUDIO_CONTROL_REGISTER, ~TDM_TIMING_MODE);
-   /* Audio change flag */
-   ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
-   AP_AV_STATUS, AP_AUDIO_CHG);
-
-   if (ret < 0)
-   DRM_DEV_ERROR(dev, "fail to config audio.\n");
-
-   return ret;
-}
-
 /*

[PATCH v3 07/14] drm/bridge: imx: Add i.MX8qm/qxp display pixel link support

This patch adds a drm bridge driver for i.MX8qm/qxp display pixel link.
The pixel link forms a standard asynchronous linkage between
pixel sources(display controller or camera module) and pixel
consumers(imaging or displays).  It consists of two distinct
functions, a pixel transfer function and a control interface.

Signed-off-by: Liu Ying 
---
v2->v3:
* Drop two macros which help define functions and define them directly.
* Properly disable all pixel link controls to POR value by calling
  imx8qxp_pixel_link_disable_all_controls() from
  imx8qxp_pixel_link_bridge_probe().

v1->v2:
* Rewrite the function to find the next bridge by properly using OF APIs
  and dropping unnecessary DT validation. (Rob)

 drivers/gpu/drm/bridge/imx/Kconfig  |   8 +
 drivers/gpu/drm/bridge/imx/Makefile |   1 +
 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c | 426 
 3 files changed, 435 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c

diff --git a/drivers/gpu/drm/bridge/imx/Kconfig 
b/drivers/gpu/drm/bridge/imx/Kconfig
index f1c91b6..4d1f027 100644
--- a/drivers/gpu/drm/bridge/imx/Kconfig
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -6,3 +6,11 @@ config DRM_IMX8QXP_PIXEL_COMBINER
help
  Choose this to enable pixel combiner found in
  Freescale i.MX8qm/qxp processors.
+
+config DRM_IMX8QXP_PIXEL_LINK
+   tristate "Freescale i.MX8QM/QXP display pixel link"
+   depends on OF
+   select DRM_KMS_HELPER
+   help
+ Choose this to enable display pixel link found in
+ Freescale i.MX8qm/qxp processors.
diff --git a/drivers/gpu/drm/bridge/imx/Makefile 
b/drivers/gpu/drm/bridge/imx/Makefile
index 7d7c8d6..c15469f 100644
--- a/drivers/gpu/drm/bridge/imx/Makefile
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
+obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c 
b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
new file mode 100644
index ..2e5ba4a
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
@@ -0,0 +1,426 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+#define DRIVER_NAME"imx8qxp-display-pixel-link"
+#define PL_MAX_MST_ADDR3
+#define PL_MAX_NEXT_BRIDGES2
+
+struct imx8qxp_pixel_link {
+   struct drm_bridge bridge;
+   struct drm_bridge *next_bridge;
+   struct device *dev;
+   struct imx_sc_ipc *ipc_handle;
+   int id;
+   int stream_id;
+   int dc_id;
+   u32 sink_rsc;
+   u32 mst_addr;
+   u8 mst_addr_ctrl;
+   u8 mst_en_ctrl;
+   u8 mst_vld_ctrl;
+   u8 sync_ctrl;
+};
+
+static void imx8qxp_pixel_link_enable_mst_en(struct imx8qxp_pixel_link *pl)
+{
+   int ret;
+
+   ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->mst_en_ctrl, true);
+   if (ret)
+   DRM_DEV_ERROR(pl->dev,
+   "failed to enable DC%d stream%d pixel link mst_en: 
%d\n",
+   pl->dc_id, pl->stream_id, ret);
+}
+
+static void imx8qxp_pixel_link_enable_mst_vld(struct imx8qxp_pixel_link *pl)
+{
+   int ret;
+
+   ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->mst_vld_ctrl, true);
+   if (ret)
+   DRM_DEV_ERROR(pl->dev,
+   "failed to enable DC%d stream%d pixel link mst_vld: %d\n",
+   pl->dc_id, pl->stream_id, ret);
+}
+
+static void imx8qxp_pixel_link_enable_sync(struct imx8qxp_pixel_link *pl)
+{
+   int ret;
+
+   ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->sync_ctrl, true);
+   if (ret)
+   DRM_DEV_ERROR(pl->dev,
+   "failed to enable DC%d stream%d pixel link sync: %d\n",
+   pl->dc_id, pl->stream_id, ret);
+}
+
+static int imx8qxp_pixel_link_disable_mst_en(struct imx8qxp_pixel_link *pl)
+{
+   int ret;
+
+   ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->mst_en_ctrl, false);
+   if (ret)
+   DRM_DEV_ERROR(pl->dev,
+   "failed to disable DC%d stream%d pixel link mst_en: %d\n",
+   pl->dc_id, pl->stream_id, ret);
+
+   return ret;
+}
+
+static int imx8qxp_pixel_link_disable_mst_vld(struct imx8qxp_pixel_link *pl)
+{
+   int ret;
+
+   ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->mst_vld_ctrl, false);
+   if (ret)
+   DR

[PATCH v8] fbtft: add tearing signal detect

From: zhangxuezhi 

For st7789v ic,add tearing signal detect to avoid screen tearing

Signed-off-by: zhangxuezhi 
---
v8: delete a log line
---
 drivers/staging/fbtft/fb_st7789v.c | 132 -
 drivers/staging/fbtft/fbtft.h  |   1 +
 2 files changed, 132 insertions(+), 1 deletion(-)

diff --git a/drivers/staging/fbtft/fb_st7789v.c 
b/drivers/staging/fbtft/fb_st7789v.c
index 3a280cc..de7460c 100644
--- a/drivers/staging/fbtft/fb_st7789v.c
+++ b/drivers/staging/fbtft/fb_st7789v.c
@@ -9,9 +9,12 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #include 
 #include 
-
+#include 
 #include "fbtft.h"
 
 #define DRVNAME "fb_st7789v"
@@ -66,6 +69,32 @@ enum st7789v_command {
 #define MADCTL_MX BIT(6) /* bitmask for column address order */
 #define MADCTL_MY BIT(7) /* bitmask for page address order */
 
+#define SPI_PANEL_TE_TIMEOUT   400
+static struct mutex te_mutex;/*mutex for tearing line*/
+static struct completion spi_panel_te;
+
+static irqreturn_t spi_panel_te_handler(int irq, void *data)
+{
+   complete(&spi_panel_te);
+   return IRQ_HANDLED;
+}
+
+static void set_spi_panel_te_irq_status(struct fbtft_par *par, bool enable)
+{
+   static int te_irq_count;
+
+   mutex_lock(&te_mutex);
+
+   if (enable) {
+   if (++te_irq_count == 1)
+   enable_irq(gpiod_to_irq(par->gpio.te));
+   } else {
+   if (--te_irq_count == 0)
+   disable_irq(gpiod_to_irq(par->gpio.te));
+   }
+   mutex_unlock(&te_mutex);
+}
+
 /**
  * init_display() - initialize the display controller
  *
@@ -82,6 +111,33 @@ enum st7789v_command {
  */
 static int init_display(struct fbtft_par *par)
 {
+   int rc;
+   struct device *dev = par->info->device;
+
+   par->gpio.te = devm_gpiod_get_index_optional(dev, "te", 0, GPIOD_IN);
+   if (IS_ERR(par->gpio.te)) {
+   rc = PTR_ERR(par->gpio.te);
+   pr_err("Failed to request te gpio: %d\n", rc);
+   return rc;
+   }
+   if (par->gpio.te) {
+   init_completion(&spi_panel_te);
+   mutex_init(&te_mutex);
+   rc = devm_request_irq(dev,
+ gpiod_to_irq(par->gpio.te),
+spi_panel_te_handler, IRQF_TRIGGER_RISING,
+"TE_GPIO", par);
+   if (rc) {
+   pr_err("TE request_irq failed.\n");
+   devm_gpiod_put(dev, par->gpio.te);
+   return rc;
+   }
+
+   disable_irq_nosync(gpiod_to_irq(par->gpio.te));
+   } else {
+   pr_info("%s:%d, TE gpio not specified\n",
+   __func__, __LINE__);
+   }
/* turn off sleep mode */
write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE);
mdelay(120);
@@ -137,6 +193,9 @@ static int init_display(struct fbtft_par *par)
 */
write_reg(par, PWCTRL1, 0xA4, 0xA1);
 
+/*Tearing Effect Line On*/
+   if (par->gpio.te)
+   write_reg(par, 0x35, 0x00);
write_reg(par, MIPI_DCS_SET_DISPLAY_ON);
 
if (HSD20_IPS)
@@ -145,6 +204,76 @@ static int init_display(struct fbtft_par *par)
return 0;
 }
 
+/*
+ *
+ *   int (*write_vmem)(struct fbtft_par *par);
+ *
+ */
+
+/* 16 bit pixel over 8-bit databus */
+static int st7789v_write_vmem16_bus8(struct fbtft_par *par, size_t offset, 
size_t len)
+{
+   u16 *vmem16;
+   __be16 *txbuf16 = par->txbuf.buf;
+   size_t remain;
+   size_t to_copy;
+   size_t tx_array_size;
+   int i;
+   int ret = 0;
+   size_t startbyte_size = 0;
+
+   fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "st7789v ---%s(offset=%zu, 
len=%zu)\n",
+ __func__, offset, len);
+
+   remain = len / 2;
+   vmem16 = (u16 *)(par->info->screen_buffer + offset);
+
+   if (par->gpio.dc)
+   gpiod_set_value(par->gpio.dc, 1);
+
+   /* non buffered write */
+   if (!par->txbuf.buf)
+   return par->fbtftops.write(par, vmem16, len);
+
+   /* buffered write */
+   tx_array_size = par->txbuf.len / 2;
+
+   if (par->startbyte) {
+   txbuf16 = par->txbuf.buf + 1;
+   tx_array_size -= 2;
+   *(u8 *)(par->txbuf.buf) = par->startbyte | 0x2;
+   startbyte_size = 1;
+   }
+
+   while (remain) {
+   to_copy = min(tx_array_size, remain);
+   dev_dbg(par->info->device, "to_copy=%zu, remain=%zu\n",
+   to_copy, remain - to_copy);
+
+   for (i = 0; i < to_copy; i++)
+   txbuf16[i] = cpu_to_be16(vmem16[i]);
+
+   vmem16 = vmem16 + to_copy;
+   if (par->gpio.te) {
+

[PATCH v11 2/9] arm64: dts: mt8183: refine gamma compatible name

From: Yongqiang Niu 

mt8183 gamma is different with mt8173
remove mt8173 compatible name for mt8183 gamma

Signed-off-by: Yongqiang Niu 
Signed-off-by: Hsin-Yi Wang 
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 6c84ccb709af6..9c0073cfad452 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1055,8 +1055,7 @@ aal0: aal@1401 {
};
 
gamma0: gamma@14011000 {
-   compatible = "mediatek,mt8183-disp-gamma",
-"mediatek,mt8173-disp-gamma";
+   compatible = "mediatek,mt8183-disp-gamma";
reg = <0 0x14011000 0 0x1000>;
interrupts = ;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
-- 
2.30.0.280.ga3ce27912f-goog

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[PATCH] drm/lima: Use delayed timer as default in devfreq profile

2021-01-28 Thread Lukasz Luba

Devfreq framework supports 2 modes for monitoring devices.
Use delayed timer as default instead of deferrable timer
in order to monitor the GPU status regardless of CPU idle.

Signed-off-by: Lukasz Luba 
---
Hi all,

I've missed the Lima driver while working on Panfrost patch for fixing
the issue with default devfreq framework polling mode. More about this
and the patch, can be found here [1].

Regards,
Lukasz Luba

[1] https://lore.kernel.org/lkml/20210105164111.30122-1-lukasz.l...@arm.com/

 drivers/gpu/drm/lima/lima_devfreq.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/lima/lima_devfreq.c 
b/drivers/gpu/drm/lima/lima_devfreq.c
index 5686ad4aaf7c..f1c9eb3e71bd 100644
--- a/drivers/gpu/drm/lima/lima_devfreq.c
+++ b/drivers/gpu/drm/lima/lima_devfreq.c
@@ -81,6 +81,7 @@ static int lima_devfreq_get_dev_status(struct device *dev,
 }
 
 static struct devfreq_dev_profile lima_devfreq_profile = {
+   .timer = DEVFREQ_TIMER_DELAYED,
.polling_ms = 50, /* ~3 frames */
.target = lima_devfreq_target,
.get_dev_status = lima_devfreq_get_dev_status,
-- 
2.17.1

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[PATCH v3 10/14] drm/bridge: imx: Add LDB driver helper support

This patch adds a helper to support LDB drm bridge drivers for
i.MX SoCs.  Helper functions exported from this driver should
implement common logics for all LDB modules embedded in i.MX SoCs.

Signed-off-by: Liu Ying 
---
v2->v3:
* Call syscon_node_to_regmap() to get regmap instead of
  syscon_regmap_lookup_by_phandle().

v1->v2:
* No change.

 drivers/gpu/drm/bridge/imx/Kconfig  |   8 +
 drivers/gpu/drm/bridge/imx/Makefile |   1 +
 drivers/gpu/drm/bridge/imx/imx-ldb-helper.c | 248 
 include/drm/bridge/imx_ldb_helper.h |  98 +++
 4 files changed, 355 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
 create mode 100644 include/drm/bridge/imx_ldb_helper.h

diff --git a/drivers/gpu/drm/bridge/imx/Kconfig 
b/drivers/gpu/drm/bridge/imx/Kconfig
index 1ea1ce7..23e24fd 100644
--- a/drivers/gpu/drm/bridge/imx/Kconfig
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -1,3 +1,11 @@
+config DRM_IMX_LVDS_BRIDGE_HELPER
+   tristate "Freescale i.MX LVDS display bridge helper"
+   depends on OF
+   select DRM_PANEL_BRIDGE
+   help
+ Helper to support Freescale i.MX LVDS Display Bridge(LDB).
+ This bridge is embedded in a SoC.
+
 config DRM_IMX8QXP_PIXEL_COMBINER
tristate "Freescale i.MX8QM/QXP pixel combiner"
depends on OF
diff --git a/drivers/gpu/drm/bridge/imx/Makefile 
b/drivers/gpu/drm/bridge/imx/Makefile
index e74dd64..902b703 100644
--- a/drivers/gpu/drm/bridge/imx/Makefile
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_DRM_IMX_LVDS_BRIDGE_HELPER) += imx-ldb-helper.o
 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
diff --git a/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c 
b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
new file mode 100644
index ..94d7f9e
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
@@ -0,0 +1,248 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Sascha Hauer, Pengutronix
+ * Copyright 2019,2020 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch)
+{
+   return ldb_ch->link_type == LDB_CH_SINGLE_LINK;
+}
+EXPORT_SYMBOL_GPL(ldb_channel_is_single_link);
+
+bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch)
+{
+   return ldb_ch->link_type == LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS ||
+  ldb_ch->link_type == LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS;
+}
+EXPORT_SYMBOL_GPL(ldb_channel_is_split_link);
+
+int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge,
+  struct drm_bridge_state *bridge_state,
+  struct drm_crtc_state *crtc_state,
+  struct drm_connector_state *conn_state)
+{
+   struct ldb_channel *ldb_ch = bridge->driver_private;
+
+   ldb_ch->in_bus_format = bridge_state->input_bus_cfg.format;
+   ldb_ch->out_bus_format = bridge_state->output_bus_cfg.format;
+
+   return 0;
+}
+EXPORT_SYMBOL_GPL(ldb_bridge_atomic_check_helper);
+
+void ldb_bridge_mode_set_helper(struct drm_bridge *bridge,
+   const struct drm_display_mode *mode,
+   const struct drm_display_mode *adjusted_mode)
+{
+   struct ldb_channel *ldb_ch = bridge->driver_private;
+   struct ldb *ldb = ldb_ch->ldb;
+   bool is_split = ldb_channel_is_split_link(ldb_ch);
+
+   if (is_split)
+   ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
+
+   switch (ldb_ch->out_bus_format) {
+   case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
+   break;
+   case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
+   if (ldb_ch->chno == 0 || is_split)
+   ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
+   if (ldb_ch->chno == 1 || is_split)
+   ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
+   break;
+   case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
+   if (ldb_ch->chno == 0 || is_split)
+   ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
+LDB_BIT_MAP_CH0_JEIDA;
+   if (ldb_ch->chno == 1 || is_split)
+   ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
+LDB_BIT_MAP_CH1_JEIDA;
+   break;
+   }
+}
+EXPORT_SYMBOL_GPL(ldb_bridge_mode_set_helper);
+
+void ldb_bridge_enable_helper(struct drm_bridge *bridge)
+{
+   struct ldb_channel *ldb_ch = bridge->driver_private;
+   struct ldb *ldb = ldb_ch->ldb;
+
+   /*
+* Platform specific bridge drivers should set ldb_ctrl properly
+* for the enablement, so just write the ctrl_reg here.
+*/
+   regmap_write(ldb->regmap, ldb->ctrl_reg,

[PATCH v11 1/9] arm64: dts: mt8183: rename rdma fifo size

From: Yongqiang Niu 

property name must include only lowercase and '-'

Signed-off-by: Yongqiang Niu 
Signed-off-by: Hsin-Yi Wang 
Reviewed-by: Chun-Kuang Hu 
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 5b782a4769e7e..6c84ccb709af6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1011,7 +1011,7 @@ rdma0: rdma@1400b000 {
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
mediatek,larb = <&larb0>;
-   mediatek,rdma_fifo_size = <5120>;
+   mediatek,rdma-fifo-size = <5120>;
mediatek,gce-client-reg = <&gce SUBSYS_1400 0xb000 
0x1000>;
};
 
@@ -1023,7 +1023,7 @@ rdma1: rdma@1400c000 {
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
mediatek,larb = <&larb0>;
-   mediatek,rdma_fifo_size = <2048>;
+   mediatek,rdma-fifo-size = <2048>;
mediatek,gce-client-reg = <&gce SUBSYS_1400 0xc000 
0x1000>;
};
 
-- 
2.30.0.280.ga3ce27912f-goog

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Re: [PATCH v1 2/2] mm: simplify free_highmem_page() and free_reserved_page()

2021-01-28 Thread Oscar Salvador

On Tue, Jan 26, 2021 at 07:21:13PM +0100, David Hildenbrand wrote:
> adjust_managed_page_count() as called by free_reserved_page() properly
> handles pages in a highmem zone, so we can reuse it for
> free_highmem_page().
> 
> We can now get rid of totalhigh_pages_inc() and simplify
> free_reserved_page().
> 
> Cc: Andrew Morton 
> Cc: Thomas Gleixner 
> Cc: "Peter Zijlstra (Intel)" 
> Cc: Mike Rapoport 
> Cc: Oscar Salvador 
> Cc: Michal Hocko 
> Cc: Wei Yang 
> Signed-off-by: David Hildenbrand 

Reviewed-by: Oscar Salvador 

> +#define free_highmem_page(page) free_reserved_page(page)

Should we place that under #ifdef CONFIG_HIGHMEM to make clear
that it is only used on that config?
Maybe the #ifdefery ugliness does not pay off.

-- 
Oscar Salvador
SUSE L3
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Re: [PATCH v1 1/2] video: fbdev: acornfb: remove free_unused_pages()

2021-01-28 Thread Oscar Salvador

On Tue, Jan 26, 2021 at 07:21:12PM +0100, David Hildenbrand wrote:
> This function is never used and it is one of the last remaining user of
> __free_reserved_page(). Let's just drop it.
> 
> Cc: Andrew Morton 
> Cc: Thomas Gleixner 
> Cc: "Peter Zijlstra (Intel)" 
> Cc: Mike Rapoport 
> Cc: Oscar Salvador 
> Cc: Michal Hocko 
> Cc: Wei Yang 
> Cc: "Gustavo A. R. Silva" 
> Cc: Sam Ravnborg 
> Signed-off-by: David Hildenbrand 

Reviewed-by: Oscar Salvador 

> ---
>  drivers/video/fbdev/acornfb.c | 34 --
>  1 file changed, 34 deletions(-)
> 
> diff --git a/drivers/video/fbdev/acornfb.c b/drivers/video/fbdev/acornfb.c
> index bcc92aecf666..1b72edc01cfb 100644
> --- a/drivers/video/fbdev/acornfb.c
> +++ b/drivers/video/fbdev/acornfb.c
> @@ -921,40 +921,6 @@ static int acornfb_detect_monitortype(void)
>   return 4;
>  }
>  
> -/*
> - * This enables the unused memory to be freed on older Acorn machines.
> - * We are freeing memory on behalf of the architecture initialisation
> - * code here.
> - */
> -static inline void
> -free_unused_pages(unsigned int virtual_start, unsigned int virtual_end)
> -{
> - int mb_freed = 0;
> -
> - /*
> -  * Align addresses
> -  */
> - virtual_start = PAGE_ALIGN(virtual_start);
> - virtual_end = PAGE_ALIGN(virtual_end);
> -
> - while (virtual_start < virtual_end) {
> - struct page *page;
> -
> - /*
> -  * Clear page reserved bit,
> -  * set count to 1, and free
> -  * the page.
> -  */
> - page = virt_to_page(virtual_start);
> - __free_reserved_page(page);
> -
> - virtual_start += PAGE_SIZE;
> - mb_freed += PAGE_SIZE / 1024;
> - }
> -
> - printk("acornfb: freed %dK memory\n", mb_freed);
> -}
> -
>  static int acornfb_probe(struct platform_device *dev)
>  {
>   unsigned long size;
> -- 
> 2.29.2
> 

-- 
Oscar Salvador
SUSE L3
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RE: [PATCH v6] drm/bridge: add it6505 driver

2021-01-28 Thread allen.chen

Hi Andrzej

I will fixed these and upstream.

Thanks for your comment.


-Original Message-
From: Andrzej Hajda [mailto:a.ha...@samsung.com] 
Sent: Friday, January 22, 2021 7:02 PM
To: Allen Chen (陳柏宇)
Cc: Kenneth Hung (洪家倫); Jitao Shi; Jau-Chih Tseng (曾昭智); Yilun Lin; David 
Airlie; Neil Armstrong; Jernej Skrabec; open list:DRM DRIVERS; open list; 
Hermes Wu (吳佳宏); moderated list:ARM/Mediatek SoC support; Laurent Pinchart; 
Pi-Hsun Shih; Matthias Brugger; moderated list:ARM/Mediatek SoC support; Jonas 
Karlman
Subject: Re: [PATCH v6] drm/bridge: add it6505 driver

Hi Allen,

Sorry for long delay.

W dniu 08.12.2020 o 11:58, allen pisze:
> This adds support for the iTE IT6505.
> This device can convert DPI signal to DP output.
>
> From: Allen Chen 
> Signed-off-by: Jitao Shi 
> Signed-off-by: Pi-Hsun Shih 
> Signed-off-by: Yilun Lin 
> Signed-off-by: Hermes Wu 
> Signed-off-by: Allen Chen 
> ---
>   drivers/gpu/drm/bridge/Kconfig  |7 +
>   drivers/gpu/drm/bridge/Makefile |1 +
>   drivers/gpu/drm/bridge/ite-it6505.c | 3343 +++
>   3 files changed, 3351 insertions(+)
>   create mode 100644 drivers/gpu/drm/bridge/ite-it6505.c
>
> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> index e4110d6ca7b3c..25d34d7196004 100644
> --- a/drivers/gpu/drm/bridge/Kconfig
> +++ b/drivers/gpu/drm/bridge/Kconfig
> @@ -74,6 +74,13 @@ config DRM_LONTIUM_LT9611UXC
> HDMI signals
> Please say Y if you have such hardware.
>   
> +config DRM_ITE_IT6505
> + tristate "ITE IT6505 DisplayPort bridge"
> + depends on OF
> + select DRM_KMS_HELPER
> + help
> +   ITE IT6505 DisplayPort bridge chip driver.
> +
>   config DRM_LVDS_CODEC
>   tristate "Transparent LVDS encoders and decoders support"
>   depends on OF
> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
> index 86e7acc76f8d6..2b2f8f0b5b0fa 100644
> --- a/drivers/gpu/drm/bridge/Makefile
> +++ b/drivers/gpu/drm/bridge/Makefile
> @@ -4,6 +4,7 @@ obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
>   obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
>   obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o
>   obj-$(CONFIG_DRM_LONTIUM_LT9611UXC) += lontium-lt9611uxc.o
> +obj-$(CONFIG_DRM_ITE_IT6505) += ite-it6505.o


Please keep alphabetic order.


>   obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
>   obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) += 
> megachips-stdp-ge-b850v3-fw.o
>   obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
> diff --git a/drivers/gpu/drm/bridge/ite-it6505.c 
> b/drivers/gpu/drm/bridge/ite-it6505.c
> new file mode 100644
> index 0..5e76719a51a4a
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/ite-it6505.c
> @@ -0,0 +1,3343 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + */
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +#define REG_IC_VER 0x04
> +
> +#define REG_RESET_CTRL 0x05
> +#define VIDEO_RESET BIT(0)
> +#define AUDIO_RESET BIT(1)
> +#define ALL_LOGIC_RESET BIT(2)
> +#define AUX_RESET BIT(3)
> +#define HDCP_RESET BIT(4)
> +
> +#define INT_STATUS_01 0x06
> +#define INT_MASK_01 0x09
> +#define INT_HPD_CHANGE BIT(0)
> +#define INT_RECEIVE_HPD_IRQ BIT(1)
> +#define INT_SCDT_CHANGE BIT(2)
> +#define INT_HDCP_FAIL BIT(3)
> +#define INT_HDCP_DONE BIT(4)
> +
> +#define INT_STATUS_02 0x07
> +#define INT_MASK_02 0x0A
> +#define INT_AUX_CMD_FAIL BIT(0)
> +#define INT_HDCP_KSV_CHECK BIT(1)
> +#define INT_AUDIO_FIFO_ERROR BIT(2)
> +
> +#define INT_STATUS_03 0x08
> +#define INT_MASK_03 0x0B
> +#define INT_LINK_TRAIN_FAIL BIT(4)
> +#define INT_VID_FIFO_ERROR BIT(5)
> +#define INT_IO_LATCH_FIFO_OVERFLOW BIT(7)
> +
> +#define REG_SYSTEM_STS 0x0D
> +#define INT_STS BIT(0)
> +#define HPD_STS BIT(1)
> +#define VIDEO_STB BIT(2)
> +
> +#define REG_LINK_TRAIN_STS 0x0E
> +#define LINK_STATE_CR BIT(2)
> +#define LINK_STATE_EQ BIT(3)
> +#define LINK_STATE_NORP BIT(4)
> +
> +#define REG_BANK_SEL 0x0F
> +#define REG_CLK_CTRL0 0x10
> +#define M_PCLK_DELAY 0x03
> +
> +#define REG_AUX_OPT 0x11
> +#define AUX_AUTO_RST BIT(0)
> +#define AUX_FIX_FREQ BIT(3)
> +
> +#define REG_DATA_CTRL0 0x12
> +#define VIDEO_LATCH_EDGE BIT(4)
> +#define ENABLE_PCLK_COUNTER BIT(7)
> +
> +#define REG_PCLK_COUNTER_VALUE 0x13
> +
> +#define REG_501_FIFO_CTRL 0x15
> +#define RST_501_FIFO BIT(1)
> +
> +#define REG_TRAIN_CTRL0 0x16
> +#define FORCE_LBR BIT(0)
> +#define LANE_COUNT_MASK 0x06
> +#define LANE_SWAP BIT(3)
> +#define SPREAD_AMP_5 BIT(4)
> +#define FORCE_CR_DONE BIT(5)
> +#define FORCE_EQ_DONE BIT(6)
> +
> +#defi

[RFC] in_atomic() usage in amba-clcd.c / FB_ARMCLCD

The mba-clcd driver uses in_interrupt() in clcdfb_sleep():
| /*
|  * Unfortunately, the enable/disable functions may be called either from
|  * process or IRQ context, and we _need_ to delay.  This is _not_ good.
|  */
| static inline void clcdfb_sleep(unsigned int ms)
| {
| if (in_atomic()) {
| mdelay(ms);
| } else {
| msleep(ms);
| }
| }

I traced it back to its initial merge:
bfe694f833643 ("[ARM] Add ARM AMBA CLCD framebuffer driver.")
https://git.kernel.org/history/history/c/bfe694f833643

The driver has been removed and added back in the meantime. 
I've been looking for the IRQ context as described in the comment and
couldn't find it. The functions calling clcdfb_sleep() also call
conditionally backlight_update_status() which acquires a mutex.

Is this part really outdated and now msleep() could be used
unconditionally?

Sebastian
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Re: [PATCH v10] staging: fbtft: add tearing signal detect

On Wed, 27 Jan 2021 14:51:55 +0100
Greg KH  wrote:

> On Wed, Jan 27, 2021 at 09:42:52PM +0800, Carlis wrote:
> > From: zhangxuezhi 
> > 
> > For st7789v ic,when we need continuous full screen refresh, it is
> > best to wait for the TE signal arrive to avoid screen tearing
> > 
> > Signed-off-by: zhangxuezhi   
> 
> Please slow down and wait at least a day between patch submissions,
> there is no rush here.
> 
> And also, ALWAYS run scripts/checkpatch.pl on your submissions, so
> that you don't have a maintainer asking you about basic problems,
> like are in this current patch :(
> 
> thanks,
> 
> greg k-h

hi,
  This is my first patch contribution to Linux, so some of the rules
are not very clear .In addition, I can confirm that before sending
patch, I check it with checkPatch.py every time.Thank you very much for
your help

regards
zhangxuezhi
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[PATCH v3 14/14] MAINTAINERS: add maintainer for DRM bridge drivers for i.MX SoCs

Add myself as the maintainer of DRM bridge drivers for i.MX SoCs.

Signed-off-by: Liu Ying 
---
v2->v3:
* No change.

v1->v2:
* No change.

 MAINTAINERS | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 9d241b8..d96c917 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5892,6 +5892,16 @@ F:   Documentation/devicetree/bindings/display/imx/
 F: drivers/gpu/drm/imx/
 F: drivers/gpu/ipu-v3/
 
+DRM DRIVERS FOR FREESCALE IMX BRIDGE
+M: Liu Ying 
+L: dri-devel@lists.freedesktop.org
+S: Maintained
+F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
+F: 
Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
+F: 
Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
+F: 
Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
+F: drivers/gpu/drm/bridge/imx/
+
 DRM DRIVERS FOR GMA500 (Poulsbo, Moorestown and derivative chipsets)
 M: Patrik Jakobsson 
 L: dri-devel@lists.freedesktop.org
-- 
2.7.4

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Re: [PATCH v5 00/21] support option where all commands are collected into a single,dedicated cmdstream

26.01.2021 05:45, Mikko Perttunen пишет:
>> 6. We will need to allocate a host1x BO for a job's cmdstream and add a
>> restart command to the end of the job's stream.  CDMA will jump into the
>> job's stream from push buffer.
>>
>> We could add a flag for that to drm_tegra_submit_cmd_gather, saying that
>> gather should be inlined into job's main cmdstream.
>>
>> This will remove a need to have a large push buffer that will easily
>> overflow, it's a real problem and upstream driver even has a bug where
>> it locks up on overflow.
>>
>> How it will look from CDMA perspective:
>>
>> PUSHBUF |
>> -
>> ... |  | JOB   |
>>  |  -   | JOB GATHER |
>> RESTART    --> CMD    |   --
>>  |  |GATHER ---> DATA    |
>> ... <-- RESTART|   |    |
>>  |  |   |
>>
> 
> Let me check if I understood you correctly:
> - You would like to have the job's cmdbuf have further GATHER opcodes
> that jump into smaller gathers?

I want jobs to be a self-contained. Instead of pushing commands to the
PB of a kernel driver, we'll push them to job's cmdstream. This means
that for each new job we'll need to allocate a host1x buffer.

> I assume this is needed because currently WAITs are placed into the
> pushbuffer, so the job will take a lot of space in the pushbuffer if
> there are a lot of waits (and GATHERs in between these waits)?

Yes, and with drm-sched we will just need to limit the max number of
jobs in the h/w queue (i.e. push buffer) and then push buffer won't ever
overflow. Problem solved.

> If so, perhaps as a simpler alternative we could change the firewall to
> allow SETCLASS into HOST1X for waiting specifically, then userspace
> could just submit one big cmdbuf taking only little space in the
> pushbuffer? Although that would only allow direct ID/threshold waits.

My solution doesn't require changes to firewall, not sure whether it's
easier.

> In any case, it seems that this can be added in a later patch, so we
> should omit it from this series for simplicity. If it is impossible for
> the userspace to deal with it, we could disable the firewall
> temporarily, or implement the above change in the firewall.

I won't be able to test UAPI fully until all features are at least on
par with the experimental driver of grate kernel.
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Re: linux-next: Tree for Jan 27 (drm/i915)

On 1/27/21 6:44 AM, Stephen Rothwell wrote:
> Hi all,
> 
> Note: the patch file has failed to upload :-(
> 
> Changes since 20210125:
> 

on x86_64:

../drivers/gpu/drm/i915/i915_gem.c: In function ‘i915_gem_freeze_late’:
../drivers/gpu/drm/i915/i915_gem.c:1182:2: error: implicit declaration of 
function ‘wbinvd_on_all_cpus’; did you mean ‘wrmsr_on_cpus’? 
[-Werror=implicit-function-declaration]
  wbinvd_on_all_cpus();

-- 
~Randy
Reported-by: Randy Dunlap 

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Re: [PATCH v9] staging: fbtft: add tearing signal detect

On Wed, 27 Jan 2021 14:11:31 +0100
Greg KH  wrote:

> On Wed, Jan 27, 2021 at 08:57:37PM +0800, Carlis wrote:
> > From: zhangxuezhi 
> > 
> > For st7789v ic,add tearing signal detect to avoid screen tearing  
> 
> I need a much better changelog description here please.
> 
> > 
> > Signed-off-by: zhangxuezhi 
> > ---
> > v9: change pr_* to dev_*
> > ---  
> 
> What changed in all of your previous versions?  All of them should be
> listed here, right?
> 
> 
> 
> >  drivers/staging/fbtft/fb_st7789v.c | 132
> > - drivers/staging/fbtft/fbtft.h
> >  |   1 + 2 files changed, 132 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/staging/fbtft/fb_st7789v.c
> > b/drivers/staging/fbtft/fb_st7789v.c index 3a280cc..9aa2f36 100644
> > --- a/drivers/staging/fbtft/fb_st7789v.c
> > +++ b/drivers/staging/fbtft/fb_st7789v.c
> > @@ -9,9 +9,12 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> > +#include 
> > +#include 
> >  #include 
> >  #include 
> > -
> > +#include 
> >  #include "fbtft.h"
> >  
> >  #define DRVNAME "fb_st7789v"
> > @@ -66,6 +69,32 @@ enum st7789v_command {
> >  #define MADCTL_MX BIT(6) /* bitmask for column address order */
> >  #define MADCTL_MY BIT(7) /* bitmask for page address order */
> >  
> > +#define SPI_PANEL_TE_TIMEOUT   400  
> 
> What is the units here?  Where did this value come from?

hi,the units is msecs,and i got this value from a qcom mdp spi
drivers,and i will add the notes you need in the patch v10
> 
> > +static struct mutex te_mutex;/*mutex for tearing line*/  
> 
> Does that look correct???
> 
> thanks,
> 
> greg k-h

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Re: [PATCH v10] staging: fbtft: add tearing signal detect

On Wed, 27 Jan 2021 16:02:35 +0100
Greg KH  wrote:

> On Wed, Jan 27, 2021 at 05:49:46PM +0300, Dan Carpenter wrote:
> > On Wed, Jan 27, 2021 at 03:25:20PM +0100, Greg KH wrote:  
> > > On Wed, Jan 27, 2021 at 10:17:08PM +0800, carlis wrote:  
> > > > On Wed, 27 Jan 2021 15:13:05 +0100
> > > > Greg KH  wrote:
> > > >   
> > > > > On Wed, Jan 27, 2021 at 10:08:09PM +0800, carlis wrote:  
> > > > > > On Wed, 27 Jan 2021 14:51:55 +0100
> > > > > > Greg KH  wrote:
> > > > > > 
> > > > > > > On Wed, Jan 27, 2021 at 09:42:52PM +0800, Carlis wrote:
> > > > > > >  
> > > > > > > > From: zhangxuezhi 
> > > > > > > > 
> > > > > > > > For st7789v ic,when we need continuous full screen
> > > > > > > > refresh, it is best to wait for the TE signal arrive to
> > > > > > > > avoid screen tearing
> > > > > > > > 
> > > > > > > > Signed-off-by: zhangxuezhi 
> > > > > > > >   
> > > > > > > 
> > > > > > > Please slow down and wait at least a day between patch
> > > > > > > submissions, there is no rush here.
> > > > > > > 
> > > > > > > And also, ALWAYS run scripts/checkpatch.pl on your
> > > > > > > submissions, so that you don't have a maintainer asking
> > > > > > > you about basic problems, like are in this current patch
> > > > > > > :(
> > > > > > > 
> > > > > > > thanks,
> > > > > > > 
> > > > > > > greg k-h
> > > > > > 
> > > > > > hi,
> > > > > >   This is my first patch contribution to Linux, so some of
> > > > > > the rules are not very clear .In addition, I can confirm
> > > > > > that before sending patch, I check it with checkPatch.py
> > > > > > every time.Thank you very much for your help
> > > > > 
> > > > > Please read Documentation/SubmittingPatches which has a link
> > > > > to the checklist and other documentation you should read.
> > > > > 
> > > > > And I doubt you are running checkpatch on your submission, as
> > > > > there is obvious coding style issues in it.  If so, please
> > > > > provide the output as it must be broken :(
> > > > > 
> > > > > thanks,
> > > > > 
> > > > > greg k-h  
> > > > hi, the patch v11 checkpatch.pl output is below:
> > > > 
> > > > carlis@bf-rmsz-10:~/work/linux-kernel/linux$
> > > > ./scripts/checkpatch.pl
> > > > 0001-staging-fbtft-add-tearing-signal-detect.patch total: 0
> > > > errors, 0 warnings, 0 checks, 176 lines checked
> > > > 
> > > > 0001-staging-fbtft-add-tearing-signal-detect.patch has no
> > > > obvious style problems and is ready for submission.  
> > > 
> > > Wow, my apologies!
> > > 
> > > Andy and Joe, there's something wrong here that is missing the
> > > fact that a line is being indented with spaces and not tabs in
> > > the patch at
> > > https://lore.kernel.org/r/1611754972-151016-1-git-send-email-zhangxuez...@gmail.com
> > > 
> > > Any ideas what broke?
> > >   
> > 
> > /*Tearing Effect Line On*/
> > 
> > Comments are the exception to the "no spaces at the start of a line"
> > rule.  I was expecting that the kbuild-bot would send a Smatch
> > warning for inconsistent indenting, but comments are not counted
> > there either.
> > 
> > I'm sort of surprised that we don't have checkpatch rule about the
> > missing space characters.  It should be: "/* Tearing Effect Line On
> > */".  
> 
> That was going to be my next question, lots of comments added in this
> patch don't have spaces...
> 
> thanks,
> 
> greg k-h

Ok,i will fix it in patch v12 tomorrow

regards,
zhangxuezhi
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Re: [PATCH v1 1/2] video: fbdev: acornfb: remove free_unused_pages()

2021-01-28 Thread Anshuman Khandual




On 1/26/21 11:51 PM, David Hildenbrand wrote:
> This function is never used and it is one of the last remaining user of
> __free_reserved_page(). Let's just drop it.
> 
> Cc: Andrew Morton 
> Cc: Thomas Gleixner 
> Cc: "Peter Zijlstra (Intel)" 
> Cc: Mike Rapoport 
> Cc: Oscar Salvador 
> Cc: Michal Hocko 
> Cc: Wei Yang 
> Cc: "Gustavo A. R. Silva" 
> Cc: Sam Ravnborg 
> Signed-off-by: David Hildenbrand 

There is no other reference for free_unused_pages() in the tree.

Reviewed-by: Anshuman Khandual 

> ---
>  drivers/video/fbdev/acornfb.c | 34 --
>  1 file changed, 34 deletions(-)
> 
> diff --git a/drivers/video/fbdev/acornfb.c b/drivers/video/fbdev/acornfb.c
> index bcc92aecf666..1b72edc01cfb 100644
> --- a/drivers/video/fbdev/acornfb.c
> +++ b/drivers/video/fbdev/acornfb.c
> @@ -921,40 +921,6 @@ static int acornfb_detect_monitortype(void)
>   return 4;
>  }
>  
> -/*
> - * This enables the unused memory to be freed on older Acorn machines.
> - * We are freeing memory on behalf of the architecture initialisation
> - * code here.
> - */
> -static inline void
> -free_unused_pages(unsigned int virtual_start, unsigned int virtual_end)
> -{
> - int mb_freed = 0;
> -
> - /*
> -  * Align addresses
> -  */
> - virtual_start = PAGE_ALIGN(virtual_start);
> - virtual_end = PAGE_ALIGN(virtual_end);
> -
> - while (virtual_start < virtual_end) {
> - struct page *page;
> -
> - /*
> -  * Clear page reserved bit,
> -  * set count to 1, and free
> -  * the page.
> -  */
> - page = virt_to_page(virtual_start);
> - __free_reserved_page(page);
> -
> - virtual_start += PAGE_SIZE;
> - mb_freed += PAGE_SIZE / 1024;
> - }
> -
> - printk("acornfb: freed %dK memory\n", mb_freed);
> -}
> -
>  static int acornfb_probe(struct platform_device *dev)
>  {
>   unsigned long size;
> 
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[PATCH v3 09/14] drm/bridge: imx: Add i.MX8qxp pixel link to DPI support

This patch adds a drm bridge driver for i.MX8qxp pixel link to display
pixel interface(PXL2DPI).  The PXL2DPI interfaces the pixel link 36-bit
data output and the DSI controller’s MIPI-DPI 24-bit data input, and
inputs of LVDS Display Bridge(LDB) module used in LVDS mode, to remap
the pixel color codings between those modules. The PXL2DPI is purely
combinatorial.

Signed-off-by: Liu Ying 
---
v2->v3:
* Call syscon_node_to_regmap() to get regmap instead of
  syscon_regmap_lookup_by_phandle().

v1->v2:
* Drop unnecessary port availability check.

 drivers/gpu/drm/bridge/imx/Kconfig   |   8 +
 drivers/gpu/drm/bridge/imx/Makefile  |   1 +
 drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c | 488 +++
 3 files changed, 497 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c

diff --git a/drivers/gpu/drm/bridge/imx/Kconfig 
b/drivers/gpu/drm/bridge/imx/Kconfig
index 4d1f027..1ea1ce7 100644
--- a/drivers/gpu/drm/bridge/imx/Kconfig
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -14,3 +14,11 @@ config DRM_IMX8QXP_PIXEL_LINK
help
  Choose this to enable display pixel link found in
  Freescale i.MX8qm/qxp processors.
+
+config DRM_IMX8QXP_PIXEL_LINK_TO_DPI
+   tristate "Freescale i.MX8QXP pixel link to display pixel interface"
+   depends on OF
+   select DRM_KMS_HELPER
+   help
+ Choose this to enable pixel link to display pixel interface(PXL2DPI)
+ found in Freescale i.MX8qxp processor.
diff --git a/drivers/gpu/drm/bridge/imx/Makefile 
b/drivers/gpu/drm/bridge/imx/Makefile
index c15469f..e74dd64 100644
--- a/drivers/gpu/drm/bridge/imx/Makefile
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
+obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c 
b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
new file mode 100644
index ..63ab1a7
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
@@ -0,0 +1,488 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define PXL2DPI_CTRL   0x40
+#define  CFG1_16BIT0x0
+#define  CFG2_16BIT0x1
+#define  CFG3_16BIT0x2
+#define  CFG1_18BIT0x3
+#define  CFG2_18BIT0x4
+#define  CFG_24BIT 0x5
+
+#define DRIVER_NAME"imx8qxp-pxl2dpi"
+
+struct imx8qxp_pxl2dpi {
+   struct regmap *regmap;
+   struct drm_bridge bridge;
+   struct drm_bridge *next_bridge;
+   struct drm_bridge *companion;
+   struct device *dev;
+   struct imx_sc_ipc *ipc_handle;
+   u32 rsc;
+   u32 in_bus_format;
+   u32 out_bus_format;
+   u32 pl_sel;
+   int id;
+};
+
+#define bridge_to_p2d(b)   container_of(b, struct imx8qxp_pxl2dpi, bridge)
+
+static int imx8qxp_pxl2dpi_bridge_attach(struct drm_bridge *bridge,
+enum drm_bridge_attach_flags flags)
+{
+   struct imx8qxp_pxl2dpi *p2d = bridge->driver_private;
+
+   if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+   DRM_DEV_ERROR(p2d->dev,
+ "do not support creating a drm_connector\n");
+   return -EINVAL;
+   }
+
+   if (!bridge->encoder) {
+   DRM_DEV_ERROR(p2d->dev, "missing encoder\n");
+   return -ENODEV;
+   }
+
+   return drm_bridge_attach(bridge->encoder,
+p2d->next_bridge, bridge,
+DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+}
+
+static int
+imx8qxp_pxl2dpi_bridge_atomic_check(struct drm_bridge *bridge,
+   struct drm_bridge_state *bridge_state,
+   struct drm_crtc_state *crtc_state,
+   struct drm_connector_state *conn_state)
+{
+   struct imx8qxp_pxl2dpi *p2d = bridge->driver_private;
+
+   p2d->in_bus_format = bridge_state->input_bus_cfg.format;
+   p2d->out_bus_format = bridge_state->output_bus_cfg.format;
+
+   return 0;
+}
+
+static void
+imx8qxp_pxl2dpi_bridge_mode_set(struct drm_bridge *bridge,
+   const struct drm_display_mode *mode,
+   const struct drm_display_mode *adjusted_mode)
+{
+   struct imx8qxp_pxl2dpi *p2d = bridge->driver_private;
+   struct imx8qxp_pxl2dpi *companion_p2d;
+   int ret;
+
+   ret = pm_runtime_get_sync(p2d->dev);
+   if (ret < 0)
+   DRM_DEV_ERROR(p2d->dev,
+ "failed to get runtime PM sync: %d\n", ret);
+
+   ret = imx_sc_misc_set_control(p2d->ipc_handle, p2d->rsc,
+ IMX_SC_C_PXL_LINK_S

Re: [PATCH v5 00/21] Host1x/TegraDRM UAPI

28.01.2021 00:57, Mikko Perttunen пишет:
> 
> 
> On 1/27/21 11:26 PM, Dmitry Osipenko wrote:
>> 26.01.2021 05:45, Mikko Perttunen пишет:
 5. The hardware state of sync points should be reset when sync point is
 requested, not when host1x driver is initialized.
>>>
>>> This may be doable, but I don't think it is critical for this UAPI, so
>>> let's consider it after this series.
>>>
>>> The userspace should anyway not be able to assume the initial value of
>>> the syncpoint upon allocation. The kernel should set it to some high
>>> value to catch any issues related to wraparound.
>>
>> This is critical because min != max when sync point is requested.
> 
> That I would just consider a bug, and it can be fixed. But it's
> orthogonal to whether the value gets reset every time the syncpoint is
> allocated.
> 
>>
>>> Also, this makes code more complicated since it now needs to ensure all
>>> waits on the syncpoint have completed before freeing the syncpoint,
>>> which can be nontrivial e.g. if the waiter is in a different virtual
>>> machine or some other device connected via PCIe (a real usecase).
>>
>> It sounds to me that these VM sync points should be treated very
>> separately from a generic sync points, don't you think so? Let's not mix
>> them and get the generic sync points usable first.
>>
> 
> They are not special in any way, I'm just referring to cases where the
> waiter (consumer) is remote. The allocator of the syncpoint (producer)
> doesn't necessarily even need to know about it. The same concern is
> applicable within a single VM, or single application as well. Just
> putting out the point that this is something that needs to be taken care
> of if we were to reset the value.

Will kernel driver know that it deals with a VM sync point?

Will it be possible to get a non-VM sync point explicitly?

If driver knows that it deals with a VM sync point, then we can treat it
specially, avoiding the reset and etc.
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Re: [PATCH v2 00/15] drm/vc4: hdmi: Add CEC support for the BCM2711

2021-01-28 Thread Hans Verkuil

On 18/01/2021 14:55, Hans Verkuil wrote:
> On 12/01/2021 16:24, Hans Verkuil wrote:
>> Hi Maxime,
>>
>> On 11/01/2021 15:22, Maxime Ripard wrote:
>>> Hi,
>>>
>>> Here's a series introducing the CEC support for the BCM2711 found on the
>>> RaspberryPi4.
>>>
>>> The BCM2711 HDMI controller uses a similar layout for the CEC registers, the
>>> main difference being that the interrupt handling part is now shared between
>>> both HDMI controllers.
>>>
>>> This series is mainly about fixing a couple of bugs, reworking the driver to
>>> support having two different interrupts, one for each direction, provided 
>>> by an
>>> external irqchip, and enables the irqchip driver for the controller we have.
>>>
>>> This has been tested on an RPi3 and RPi4, but requires the latest firmware.
>>> It's is based on the 10 and 12 bpc series.
>>
>> Thank you for this series, I plan to test this later this week.
> 
> Testing is delayed: my microHDMI to HDMI adapter has problems with the CEC pin
> (possibly not connected at all). I've ordered adapter cables (hopefully of 
> better
> quality), but those haven't arrived yet. I expect them later this week.

After testing this you can add my:

Acked-by: Hans Verkuil 
Tested-by: Hans Verkuil 

for the patches in this series.

Thank you for working on this!

Regards,

Hans

> 
> Regards,
> 
>   Hans
> 
>>
>> Regards,
>>
>>  Hans
>>
>>>
>>> Here is the cec-compliance output:
>>>
>>> pi@raspberrypi:~$ cec-ctl --tuner -p 1.0.0.0
>>> The CEC adapter doesn't allow setting the physical address manually, ignore 
>>> this option.
>>>
>>> Driver Info:
>>> Driver Name: vc4_hdmi
>>> Adapter Name   : vc4
>>> Capabilities   : 0x010e
>>> Logical Addresses
>>> Transmit
>>> Passthrough
>>> Driver version : 5.10.0
>>> Available Logical Addresses: 1
>>> Physical Address   : 1.0.0.0
>>> Logical Address Mask   : 0x0008
>>> CEC Version: 2.0
>>> Vendor ID  : 0x000c03 (HDMI)
>>> OSD Name   : Tuner
>>> Logical Addresses  : 1 (Allow RC Passthrough)
>>>
>>>   Logical Address  : 3 (Tuner 1)
>>> Primary Device Type: Tuner
>>> Logical Address Type   : Tuner
>>> All Device Types   : Tuner
>>> RC TV Profile  : None
>>> Device Features:
>>> None
>>>
>>> pi@raspberrypi:~$ cec-compliance
>>> cec-compliance SHA : not available
>>> Driver Info:
>>> Driver Name: vc4_hdmi
>>> Adapter Name   : vc4
>>> Capabilities   : 0x010e
>>> Logical Addresses
>>> Transmit
>>> Passthrough
>>> Driver version : 5.10.0
>>> Available Logical Addresses: 1
>>> Physical Address   : 1.0.0.0
>>> Logical Address Mask   : 0x0008
>>> CEC Version: 2.0
>>> Vendor ID  : 0x000c03 (HDMI)
>>> OSD Name   : Tuner
>>> Logical Addresses  : 1 (Allow RC Passthrough)
>>>
>>>   Logical Address  : 3 (Tuner 1)
>>> Primary Device Type: Tuner
>>> Logical Address Type   : Tuner
>>> All Device Types   : Tuner
>>> RC TV Profile  : None
>>> Device Features:
>>> None
>>>
>>> Compliance test for device /dev/cec0:
>>>
>>> The test results mean the following:
>>> OK  Supported correctly by the device.
>>> OK (Not Supported)  Not supported and not mandatory for the device.
>>> OK (Presumed)   Presumably supported.  Manually check to 
>>> confirm.
>>> OK (Unexpected) Supported correctly but is not expected to be 
>>> supported for this device.
>>> OK (Refused)Supported by the device, but was refused.
>>> FAILFailed and was expected to be supported by this 
>>> device.
>>>
>>> Find remote devices:
>>> Polling: OK
>>>
>>> Network topology:
>>> System Information for device 0 (TV) from device 3 (Tuner 1):
>>> CEC Version: 2.0
>>> Physical Address   : 0.0.0.0
>>> Primary Device Type: TV
>>> Vendor ID  : 0x000c03
>>> OSD Name   : 'TV  '
>>> Power Status   : Tx, OK, Rx, OK, Feature Abort
>>>
>>> Total: 1, Succeeded: 1, Failed: 0, Warnings: 0
>>>
>>> pi@raspberrypi:~$ cec-ctl -d1 --tuner -p 1.0.0.0
>>> The CEC adapter doesn't allow setting the physical address manually, ignore 
>>> this option.
>>>
>>> Driver Info:
>>> Driver Name: vc4_hdmi
>>> Adapter Name   : vc4
>>> Capabilities   : 0x010e
>>> Logical Addresses
>>> Transmit
>>> Passthro

[PATCH v7] fbtft: add tearing signal detect

From: zhangxuezhi 

For st7789v ic,add tearing signal detect to avoid screen tearing

Signed-off-by: zhangxuezhi 
---
v7: request fail to return error value
---
 drivers/staging/fbtft/fb_st7789v.c | 133 -
 drivers/staging/fbtft/fbtft.h  |   1 +
 2 files changed, 133 insertions(+), 1 deletion(-)

diff --git a/drivers/staging/fbtft/fb_st7789v.c 
b/drivers/staging/fbtft/fb_st7789v.c
index 3a280cc..c964cc1 100644
--- a/drivers/staging/fbtft/fb_st7789v.c
+++ b/drivers/staging/fbtft/fb_st7789v.c
@@ -9,9 +9,12 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #include 
 #include 
-
+#include 
 #include "fbtft.h"
 
 #define DRVNAME "fb_st7789v"
@@ -66,6 +69,32 @@ enum st7789v_command {
 #define MADCTL_MX BIT(6) /* bitmask for column address order */
 #define MADCTL_MY BIT(7) /* bitmask for page address order */
 
+#define SPI_PANEL_TE_TIMEOUT   400
+static struct mutex te_mutex;/*mutex for tearing line*/
+static struct completion spi_panel_te;
+
+static irqreturn_t spi_panel_te_handler(int irq, void *data)
+{
+   complete(&spi_panel_te);
+   return IRQ_HANDLED;
+}
+
+static void set_spi_panel_te_irq_status(struct fbtft_par *par, bool enable)
+{
+   static int te_irq_count;
+
+   mutex_lock(&te_mutex);
+
+   if (enable) {
+   if (++te_irq_count == 1)
+   enable_irq(gpiod_to_irq(par->gpio.te));
+   } else {
+   if (--te_irq_count == 0)
+   disable_irq(gpiod_to_irq(par->gpio.te));
+   }
+   mutex_unlock(&te_mutex);
+}
+
 /**
  * init_display() - initialize the display controller
  *
@@ -82,6 +111,34 @@ enum st7789v_command {
  */
 static int init_display(struct fbtft_par *par)
 {
+   int rc;
+   struct device *dev = par->info->device;
+
+   par->gpio.te = devm_gpiod_get_index_optional(dev, "te", 0, GPIOD_IN);
+   if (IS_ERR(par->gpio.te)) {
+   rc = PTR_ERR(par->gpio.te);
+   pr_err("Failed to request te gpio: %d\n", rc);
+   return rc;
+   }
+   if (par->gpio.te) {
+   init_completion(&spi_panel_te);
+   mutex_init(&te_mutex);
+   rc = devm_request_irq(dev,
+ gpiod_to_irq(par->gpio.te),
+spi_panel_te_handler, IRQF_TRIGGER_RISING,
+"TE_GPIO", par);
+   if (rc) {
+   pr_err("TE request_irq failed.\n");
+   devm_gpiod_put(dev, par->gpio.te);
+   return rc;
+   }
+
+   disable_irq_nosync(gpiod_to_irq(par->gpio.te));
+   pr_info("TE request_irq completion.\n");
+   } else {
+   pr_info("%s:%d, TE gpio not specified\n",
+   __func__, __LINE__);
+   }
/* turn off sleep mode */
write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE);
mdelay(120);
@@ -137,6 +194,9 @@ static int init_display(struct fbtft_par *par)
 */
write_reg(par, PWCTRL1, 0xA4, 0xA1);
 
+/*Tearing Effect Line On*/
+   if (par->gpio.te)
+   write_reg(par, 0x35, 0x00);
write_reg(par, MIPI_DCS_SET_DISPLAY_ON);
 
if (HSD20_IPS)
@@ -145,6 +205,76 @@ static int init_display(struct fbtft_par *par)
return 0;
 }
 
+/*
+ *
+ *   int (*write_vmem)(struct fbtft_par *par);
+ *
+ */
+
+/* 16 bit pixel over 8-bit databus */
+static int st7789v_write_vmem16_bus8(struct fbtft_par *par, size_t offset, 
size_t len)
+{
+   u16 *vmem16;
+   __be16 *txbuf16 = par->txbuf.buf;
+   size_t remain;
+   size_t to_copy;
+   size_t tx_array_size;
+   int i;
+   int ret = 0;
+   size_t startbyte_size = 0;
+
+   fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "st7789v ---%s(offset=%zu, 
len=%zu)\n",
+ __func__, offset, len);
+
+   remain = len / 2;
+   vmem16 = (u16 *)(par->info->screen_buffer + offset);
+
+   if (par->gpio.dc)
+   gpiod_set_value(par->gpio.dc, 1);
+
+   /* non buffered write */
+   if (!par->txbuf.buf)
+   return par->fbtftops.write(par, vmem16, len);
+
+   /* buffered write */
+   tx_array_size = par->txbuf.len / 2;
+
+   if (par->startbyte) {
+   txbuf16 = par->txbuf.buf + 1;
+   tx_array_size -= 2;
+   *(u8 *)(par->txbuf.buf) = par->startbyte | 0x2;
+   startbyte_size = 1;
+   }
+
+   while (remain) {
+   to_copy = min(tx_array_size, remain);
+   dev_dbg(par->info->device, "to_copy=%zu, remain=%zu\n",
+   to_copy, remain - to_copy);
+
+   for (i = 0; i < to_copy; i++)
+   txbuf16[i] = cpu_to_be16(vmem16[i]);
+
+

Re: [PATCH v9] staging: fbtft: add tearing signal detect

On Wed, 27 Jan 2021 14:47:04 +0100
Geert Uytterhoeven  wrote:

> Hi Carlis,
> 
> On Wed, Jan 27, 2021 at 2:03 PM Carlis  wrote:
> > From: zhangxuezhi 
> >
> > For st7789v ic,add tearing signal detect to avoid screen tearing
> >
> > Signed-off-by: zhangxuezhi 
> > ---
> > v9: change pr_* to dev_*  
> 
> Thanks for the update!
> 
> > --- a/drivers/staging/fbtft/fb_st7789v.c
> > +++ b/drivers/staging/fbtft/fb_st7789v.c
> > @@ -9,9 +9,12 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> > +#include 
> > +#include 
> >  #include 
> >  #include 
> > -
> > +#include 
> >  #include "fbtft.h"
> >
> >  #define DRVNAME "fb_st7789v"
> > @@ -66,6 +69,32 @@ enum st7789v_command {
> >  #define MADCTL_MX BIT(6) /* bitmask for column address order */
> >  #define MADCTL_MY BIT(7) /* bitmask for page address order */
> >
> > +#define SPI_PANEL_TE_TIMEOUT   400
> > +static struct mutex te_mutex;/*mutex for tearing line*/
> > +static struct completion spi_panel_te;
> > +
> > +static irqreturn_t spi_panel_te_handler(int irq, void *data)
> > +{
> > +   complete(&spi_panel_te);
> > +   return IRQ_HANDLED;
> > +}
> > +
> > +static void set_spi_panel_te_irq_status(struct fbtft_par *par,
> > bool enable) +{
> > +   static int te_irq_count;
> > +
> > +   mutex_lock(&te_mutex);
> > +
> > +   if (enable) {
> > +   if (++te_irq_count == 1)
> > +   enable_irq(gpiod_to_irq(par->gpio.te));
> > +   } else {
> > +   if (--te_irq_count == 0)
> > +   disable_irq(gpiod_to_irq(par->gpio.te));
> > +   }
> > +   mutex_unlock(&te_mutex);
> > +}
> > +
> >  /**
> >   * init_display() - initialize the display controller
> >   *
> > @@ -82,6 +111,33 @@ enum st7789v_command {
> >   */
> >  static int init_display(struct fbtft_par *par)
> >  {
> > +   int rc;
> > +   struct device *dev = par->info->device;
> > +
> > +   par->gpio.te = devm_gpiod_get_index_optional(dev, "te", 0,
> > GPIOD_IN);
> > +   if (IS_ERR(par->gpio.te)) {
> > +   rc = PTR_ERR(par->gpio.te);
> > +   dev_err(par->info->device, "Failed to request te
> > gpio: %d\n", rc);  
> 
> This also prints an error in case of -EPROBE_DEFER.
> dev_err_probe()?
> 
> > +   return rc;
> > +   }
> > +   if (par->gpio.te) {
> > +   init_completion(&spi_panel_te);
> > +   mutex_init(&te_mutex);
> > +   rc = devm_request_irq(dev,
> > + gpiod_to_irq(par->gpio.te),
> > +spi_panel_te_handler,
> > IRQF_TRIGGER_RISING,
> > +"TE_GPIO", par);
> > +   if (rc) {
> > +   dev_err(par->info->device, "TE request_irq
> > failed.\n");
> > +   devm_gpiod_put(dev, par->gpio.te);  
> 
> No need to call devm_gpiod_put() here, as it's managed automatically.
> 
> Gr{oetje,eeting}s,
> 
> Geert
> 

hi,i will fix in patch v11
regards
zhangxuezhi1


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Re: [PATCH v5 00/21] Host1x sync point UAPI should not be used for tracking DRM jobs

26.01.2021 05:45, Mikko Perttunen пишет:
>> 2. We will probably need a dedicated drm_tegra_submit_cmd for sync point
>> increments.  The job's sync point will be allocated dynamically when job
>> is submitted.  We will need a fag for the sync_incr and wait_syncpt
>> commands, saying "it's a job's sync point increment/wait"
> 
> Negative. Like I have explained in previous discussions, with the
> current way the usage of hardware resources is much more deterministic
> and obvious. I disagree on the point that this is much more complicated
> for the userspace. Separating syncpoint and channel allocation is one of
> the primary motivations of this series for me.

Sync points are a limited resource. The most sensible way to work around
it is to keep sync points within kernel as much as possible. This is not
only much simpler for user space, but also allows to utilize DRM API
properly without re-inventing what already exists and it's easier to
maintain hardware in a good state.

If you need to use a dedicated sync point for VMs, then just allocate
that special sync point and use it. But this sync point won't be used
for jobs tracking by kernel driver. Is there any problem with this?

The primary motivation for me is to get a practically usable kernel
driver for userspace.
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[PATCH] dt-bindings: mxsfb: Add interconnect bindings for LCDIF path

2021-01-28 Thread Martin Kepplinger

Add optional interconnect properties for the dram path requests.

Signed-off-by: Martin Kepplinger 
---
 Documentation/devicetree/bindings/display/fsl,lcdif.yaml | 8 
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml 
b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml
index a4c3064c778c..44d744800a7c 100644
--- a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml
+++ b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml
@@ -50,6 +50,14 @@ properties:
   interrupts:
 maxItems: 1
 
+  interconnects:
+items:
+  - description: Interconnect path between LCDIF and main memory
+
+  interconnect-names:
+items:
+  - const: dram
+
   port:
 $ref: /schemas/graph.yaml#/properties/port
 description: The LCDIF output port
-- 
2.20.1

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Re: [PATCH v1 2/2] mm: simplify free_highmem_page() and free_reserved_page()

2021-01-28 Thread Anshuman Khandual




On 1/26/21 11:51 PM, David Hildenbrand wrote:
> adjust_managed_page_count() as called by free_reserved_page() properly
> handles pages in a highmem zone, so we can reuse it for
> free_highmem_page().
> 
> We can now get rid of totalhigh_pages_inc() and simplify
> free_reserved_page().
> 
> Cc: Andrew Morton 
> Cc: Thomas Gleixner 
> Cc: "Peter Zijlstra (Intel)" 
> Cc: Mike Rapoport 
> Cc: Oscar Salvador 
> Cc: Michal Hocko 
> Cc: Wei Yang 
> Signed-off-by: David Hildenbrand 

Reviewed-by: Anshuman Khandual 

> ---
>  include/linux/highmem-internal.h |  5 -
>  include/linux/mm.h   | 16 ++--
>  mm/page_alloc.c  | 11 ---
>  3 files changed, 2 insertions(+), 30 deletions(-)
> 
> diff --git a/include/linux/highmem-internal.h 
> b/include/linux/highmem-internal.h
> index 1bbe96dc8be6..7902c7d8b55f 100644
> --- a/include/linux/highmem-internal.h
> +++ b/include/linux/highmem-internal.h
> @@ -127,11 +127,6 @@ static inline unsigned long totalhigh_pages(void)
>   return (unsigned long)atomic_long_read(&_totalhigh_pages);
>  }
>  
> -static inline void totalhigh_pages_inc(void)
> -{
> - atomic_long_inc(&_totalhigh_pages);
> -}
> -
>  static inline void totalhigh_pages_add(long count)
>  {
>   atomic_long_add(count, &_totalhigh_pages);
> diff --git a/include/linux/mm.h b/include/linux/mm.h
> index a5d618d08506..494c69433a34 100644
> --- a/include/linux/mm.h
> +++ b/include/linux/mm.h
> @@ -2303,32 +2303,20 @@ extern void free_initmem(void);
>  extern unsigned long free_reserved_area(void *start, void *end,
>   int poison, const char *s);
>  
> -#ifdef   CONFIG_HIGHMEM
> -/*
> - * Free a highmem page into the buddy system, adjusting totalhigh_pages
> - * and totalram_pages.
> - */
> -extern void free_highmem_page(struct page *page);
> -#endif
> -
>  extern void adjust_managed_page_count(struct page *page, long count);
>  extern void mem_init_print_info(const char *str);
>  
>  extern void reserve_bootmem_region(phys_addr_t start, phys_addr_t end);
>  
>  /* Free the reserved page into the buddy system, so it gets managed. */
> -static inline void __free_reserved_page(struct page *page)
> +static inline void free_reserved_page(struct page *page)
>  {
>   ClearPageReserved(page);
>   init_page_count(page);
>   __free_page(page);
> -}
> -
> -static inline void free_reserved_page(struct page *page)
> -{
> - __free_reserved_page(page);
>   adjust_managed_page_count(page, 1);
>  }
> +#define free_highmem_page(page) free_reserved_page(page)
>  
>  static inline void mark_page_reserved(struct page *page)
>  {
> diff --git a/mm/page_alloc.c b/mm/page_alloc.c
> index b031a5ae0bd5..b2e42f10d4d4 100644
> --- a/mm/page_alloc.c
> +++ b/mm/page_alloc.c
> @@ -7711,17 +7711,6 @@ unsigned long free_reserved_area(void *start, void 
> *end, int poison, const char
>   return pages;
>  }
>  
> -#ifdef   CONFIG_HIGHMEM
> -void free_highmem_page(struct page *page)
> -{
> - __free_reserved_page(page);
> - totalram_pages_inc();
> - atomic_long_inc(&page_zone(page)->managed_pages);
> - totalhigh_pages_inc();
> -}
> -#endif
> -
> -
>  void __init mem_init_print_info(const char *str)
>  {
>   unsigned long physpages, codesize, datasize, rosize, bss_size;
> 
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Re: linux-next: Tree for Jan 27 (drm/i915)

On 1/27/21 11:08 AM, Randy Dunlap wrote:
> On 1/27/21 6:44 AM, Stephen Rothwell wrote:
>> Hi all,
>>
>> Note: the patch file has failed to upload :-(
>>
>> Changes since 20210125:
>>
> 
> on x86_64:
> 
> ../drivers/gpu/drm/i915/i915_gem.c: In function ‘i915_gem_freeze_late’:
> ../drivers/gpu/drm/i915/i915_gem.c:1182:2: error: implicit declaration of 
> function ‘wbinvd_on_all_cpus’; did you mean ‘wrmsr_on_cpus’? 
> [-Werror=implicit-function-declaration]
>   wbinvd_on_all_cpus();
> 

My apologies: this was in Andrew's mmotm 2021-01-25.
Sorry about that.

-- 
~Randy

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Re: [PATCH v10] staging: fbtft: add tearing signal detect

2021-01-28 Thread Kari Argillander

On Wed, Jan 27, 2021 at 09:42:52PM +0800, Carlis wrote:
> For st7789v ic,when we need continuous full screen refresh, it is best to
> wait for the TE signal arrive to avoid screen tearing
 
> diff --git a/drivers/staging/fbtft/fb_st7789v.c 
> b/drivers/staging/fbtft/fb_st7789v.c
> index 3a280cc..cba08a8 100644
> --- a/drivers/staging/fbtft/fb_st7789v.c
> +++ b/drivers/staging/fbtft/fb_st7789v.c
> @@ -9,9 +9,12 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
> +#include 
>  #include 
>  #include 
> -
> +#include 

Space after local headers. Also this should one up so all Linux headers
are group together. You agreed?

>  #include "fbtft.h"
>  
>  #define DRVNAME "fb_st7789v"
> @@ -66,6 +69,32 @@ enum st7789v_command {
>  #define MADCTL_MX BIT(6) /* bitmask for column address order */
>  #define MADCTL_MY BIT(7) /* bitmask for page address order */
>  
> +#define SPI_PANEL_TE_TIMEOUT 400 /* msecs */
> +static struct mutex te_mutex;/* mutex for set te gpio irq status */

Space after ;

> +static struct completion spi_panel_te;

What if multiple displays? Is this possible for user?

> +
> +static irqreturn_t spi_panel_te_handler(int irq, void *data)
> +{
> + complete(&spi_panel_te);
> + return IRQ_HANDLED;
> +}
> +
> +static void set_spi_panel_te_irq_status(struct fbtft_par *par, bool enable)
> +{
> + static int te_irq_count;

Same here. Maybe you can think better way and then this code would also be
cleaner.

> +
> + mutex_lock(&te_mutex);

So locking should be done if we really do action and not just in case.

> +
> + if (enable) {
> + if (++te_irq_count == 1)
> + enable_irq(gpiod_to_irq(par->gpio.te));
> + } else {
> + if (--te_irq_count == 0)
> + disable_irq(gpiod_to_irq(par->gpio.te));
> + }
> + mutex_unlock(&te_mutex);
> +}
> +
>  /**
>   * init_display() - initialize the display controller
>   *
> @@ -82,6 +111,33 @@ enum st7789v_command {
>   */
>  static int init_display(struct fbtft_par *par)
>  {
> + int rc;
> + struct device *dev = par->info->device;
> +
> + par->gpio.te = devm_gpiod_get_index_optional(dev, "te", 0, GPIOD_IN);
> + if (IS_ERR(par->gpio.te)) {
> + rc = PTR_ERR(par->gpio.te);
> + dev_err(par->info->device, "Failed to request te gpio: %d\n", 
> rc);
> + return rc;
> + }

You request with optinal and you still want to error out? We could just
continue and not care about that error. User will be happier if device
still works somehow.

> + if (par->gpio.te) {
> + init_completion(&spi_panel_te);
> + mutex_init(&te_mutex);
> + rc = devm_request_irq(dev,
> +   gpiod_to_irq(par->gpio.te),
> +  spi_panel_te_handler, IRQF_TRIGGER_RISING,
> +  "TE_GPIO", par);
> + if (rc) {
> + dev_err(par->info->device, "TE request_irq failed.\n");
> + devm_gpiod_put(dev, par->gpio.te);
> + return rc;
> + }
> +
> + disable_irq_nosync(gpiod_to_irq(par->gpio.te));
> + } else {
> + dev_info(par->info->device, "%s:%d, TE gpio not specified\n",
> +  __func__, __LINE__);
> + }
>   /* turn off sleep mode */
>   write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE);
>   mdelay(120);
> @@ -137,6 +193,9 @@ static int init_display(struct fbtft_par *par)
>*/
>   write_reg(par, PWCTRL1, 0xA4, 0xA1);
>  
> +/*Tearing Effect Line On*/

Spaces and why upcase everything?

> + if (par->gpio.te)
> + write_reg(par, 0x35, 0x00);
>   write_reg(par, MIPI_DCS_SET_DISPLAY_ON);
>  
>   if (HSD20_IPS)
> @@ -145,6 +204,76 @@ static int init_display(struct fbtft_par *par)
>   return 0;
>  }
>  
> +/*
> + *
> + *   int (*write_vmem)(struct fbtft_par *par);
> + *
> + 
> */
> +

Why this kind of function comment? Please use same as another function
comments in this file. They are atleast almoust like kernel-doc style.

> +/* 16 bit pixel over 8-bit databus */
> +static int st7789v_write_vmem16_bus8(struct fbtft_par *par, size_t offset, 
> size_t len)
> +{
> + u16 *vmem16;
> + __be16 *txbuf16 = par->txbuf.buf;
> + size_t remain;
> + size_t to_copy;
> + size_t tx_array_size;
> + int i;
> + int ret = 0;
> + size_t startbyte_size = 0;
> +
> + fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "st7789v ---%s(offset=%zu, 
> len=%zu)\n",
> +   __func__, offset, len);
> +
> + remain = len / 2;
> + vmem16 = (u16 *)(par->info->screen_buffer + offset);
> +
> + if (par->gpio.dc)
> + gpiod_set_value(par->gpio.dc, 1);
> +
> + /* non buffered write */
> + if (!pa

[PATCH v4 0/3] Add MIPI rx DPI support

Hi all, this patch series implement MIPI rx DPI feature. Please help to review.

This is the v4 version, any mistakes, please let me know,
I'll fix it in the next series.

Change history:
v4: Fix Rob Herring comment
 - Rebase code on the branch 'drm-misc-next'
 - Change 'analogix,hdcp-support' type to boolean

v3: Fix Rob Herring, Dan Carpenter, Nicolas comment
 - Split the patch, fix not correct return data
 - Fix several coding format
 - Split DP tx swing register setting to two property
 - Add HDCP support vender flag
 - remove 'analogix,swing-setting' and 'analogix,mipi-dpi-in' property

v2: Fix Rob Herring comment
 - Fix yamllint warnings/errors in analogix,anx7625.yaml
 - Fix kernel robot compile warning

v1: initial MIPI rx DPI feature support

Xin Ji (3):
  dt-bindings:drm/bridge:anx7625:add vendor define flags
  drm/bridge: anx7625: fix not correct return value
  drm/bridge: anx7625: add MIPI DPI input feature support

 .../bindings/display/bridge/analogix,anx7625.yaml  |  54 +++-
 drivers/gpu/drm/bridge/analogix/anx7625.c  | 330 +
 drivers/gpu/drm/bridge/analogix/anx7625.h  |  20 +-
 3 files changed, 340 insertions(+), 64 deletions(-)

-- 
2.7.4

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Re: [PATCH v4 1/2] dt-bindings: Add DT schema for Arm Mali Valhall GPU

2021-01-28 Thread Nick Fan

Thanks for your review.
These are fixed in v5 as following link.
https://lore.kernel.org/patchwork/patch/1372271/

Nick Fan

On Thu, 2021-01-14 at 14:14 -0600, Rob Herring wrote:
> On Tue, Jan 12, 2021 at 02:49:32PM +0800, Nick Fan wrote:
> > Add devicetree schema for Arm Mali Valhall GPU
> > 
> > Define a compatible string for the Mali Valhall GPU
> > for Mediatek's SoC platform.
> > 
> > Signed-off-by: Nick Fan 
> > ---
> >  .../bindings/gpu/arm,mali-valhall.yaml| 252 ++
> >  1 file changed, 252 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml 
> > b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
> > new file mode 100644
> > index ..ecf249a58435
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
> > @@ -0,0 +1,252 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (c) 2020 MediaTek Inc.
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/gpu/arm,mali-valhall.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: ARM Mali Valhall GPU
> > +
> > +maintainers:
> > +  - Rob Herring 
> > +
> > +properties:
> > +  $nodename:
> > +pattern: '^gpu@[a-f0-9]+$'
> > +
> > +  compatible:
> > +items:
> > +  - enum:
> > +  - mediatek,mt8192-mali
> > +  - const: arm,mali-valhall
> > +
> > +  reg:
> > +maxItems: 1
> > +
> > +  interrupts:
> > +items:
> > +  - description: GPU interrupt
> > +  - description: MMU interrupt
> > +  - description: Job interrupt
> > +
> > +  interrupt-names:
> > +items:
> > +  - const: gpu
> > +  - const: mmu
> > +  - const: job
> > +
> > +  clocks:
> > +minItems: 1
> > +
> > +  power-domains:
> > +minItems: 1
> > +maxItems: 5
> > +
> > +  mali-supply: true
> > +  sram-supply: true
> > +
> > +  operating-points-v2: true
> > +
> > +  "#cooling-cells":
> > +const: 2
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - interrupt-names
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +allOf:
> > +  - if:
> > +  properties:
> > +compatible:
> > +  contains:
> > +const: mediatek,mt8192-mali
> > +then:
> > +  properties:
> > +sram-supply: true
> > +power-domains:
> > +  description:
> > +List of phandle and PM domain specifier as documented in
> > +Documentation/devicetree/bindings/power/power_domain.txt
> > +  minItems: 5
> > +  maxItems: 5
> > +power-domain-names:
> > +  items:
> > +- const: core0
> > +- const: core1
> > +- const: core2
> > +- const: core3
> > +- const: core4
> > +
> > +  required:
> > +- sram-supply
> > +- power-domains
> > +
> > +examples:
> > +  - |
> > +#include 
> > +#include 
> > +
> > +gpu@1300 {
> > +   compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
> > +   reg = <0x1300 0x4000>;
> > +   interrupts =
> > +   ,
> > +   ,
> > +   ;
> > +   interrupt-names =
> > +   "gpu",
> > +   "mmu",
> > +   "job";
> > +
> > +   clocks = <&mfgcfg 0>;
> > +
> > +   power-domains =
> > +   <&spm 4>,
> > +   <&spm 5>,
> > +   <&spm 6>,
> > +   <&spm 7>,
> > +   <&spm 8>;
> > +
> > +   operating-points-v2 = <&gpu_opp_table>;
> > +   mali-supply = <&mt6315_7_vbuck1>;
> > +   sram-supply = <&mt6359_vsram_others_ldo_reg>;
> > +};
> > +
> > +gpu_opp_table: opp_table0 {
> 
> Make this a child node of the gpu node.
> 
> > +  compatible = "operating-points-v2";
> > +  opp-shared;
> > +
> > +  opp-35800 {
> > +  opp-hz = /bits/ 64 <35800>;
> > +  opp-hz-real = /bits/ 64 <35800>,
> > +/bits/ 64 <35800>;
> 
> This is not part of the OPP binding. It's not clear what it's purpose 
> would be given the values are always the same as opp-hz.
> 
> 
> > +  opp-microvolt = <606250>,
> > +  <75>;
> > +  };
> > +
> > +  opp-39900 {
> > +  opp-hz = /bits/ 64 <39900>;
> > +  opp-hz-real = /bits/ 64 <39900>,
> > +/bits/ 64 <39900>;
> > +  opp-microvolt = <618750>,
> > +  <75>;
> > +  };
> > +
> > +  opp-44000 {
> > +  opp-hz = /bits/ 64 <44000>;
> > +  opp-hz-real = /bits/ 64 <44000>,
> > +/bits/ 64 <44000>;
> > +

Re: [PATCH v11 7/9] drm/mediatek: enable dither function

2021-01-28 Thread Yongqiang Niu

On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote:
> On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
> > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
> > > Hi, Hsin-Yi:
> > > 
> > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> > > > From: Yongqiang Niu 
> > > > 
> > > > for 5 or 6 bpc panel, we need enable dither function
> > > > to improve the display quality
> > > > 
> > > > Signed-off-by: Yongqiang Niu 
> > > > Signed-off-by: Hsin-Yi Wang 
> > > > ---
> > > >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 -
> > > >  1 file changed, 43 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
> > > > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > index 8173f709272be..e85625704d611 100644
> > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > @@ -53,7 +53,9 @@
> > > >  #define DITHER_EN  BIT(0)
> > > >  #define DISP_DITHER_CFG0x0020
> > > >  #define DITHER_RELAY_MODE  BIT(0)
> > > > +#define DITHER_ENGINE_EN   BIT(1)
> > > >  #define DISP_DITHER_SIZE   0x0030
> > > > +#define DITHER_REG(idx)(0x100 + (idx) 
> > > > * 4)
> > > >  
> > > >  #define LUT_10BIT_MASK 0x03ff
> > > >  
> > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, 
> > > > unsigned int w,
> > > >  {
> > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > > >  
> > > > +   bool enable = false;
> > > > +
> > > > +   /* default value for dither reg 5 to 14 */
> > > > +   const u32 dither_setting[] = {
> > > > +   0x, /* 5 */
> > > > +   0x3002, /* 6 */
> > > > +   0x, /* 7 */
> > > > +   0x, /* 8 */
> > > > +   0x, /* 9 */
> > > > +   0x, /* 10 */
> > > > +   0x, /* 11 */
> > > > +   0x0011, /* 12 */
> > > > +   0x, /* 13 */
> > > > +   0x, /* 14 */
> > > 
> > > Could you explain what is this?
> > 
> > this is dither 5 to dither 14 setting
> > this will be useless, we just need set dither 5 and dither 7 like 
> > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5);
> > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7);
> > other value is same with hardware default value.
> > 
> > 
> > > 
> > > > +   };
> > > > +
> > > > +   if (bpc == 5 || bpc == 6) {
> > > > +   enable = true;
> > > > +   mtk_ddp_write(cmdq_pkt,
> > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) 
> > > > |
> > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> > > > + DITHER_NEW_BIT_MODE,
> > > > + &priv->cmdq_reg, priv->regs, 
> > > > DITHER_REG(15));
> > > > +   mtk_ddp_write(cmdq_pkt,
> > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) 
> > > > |
> > > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
> > > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) 
> > > > |
> > > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> > > 
> > > This result in 0x50505050, but previous version is 0x50504040, so this
> > > version is correct and previous version is incorrect?
> > 
> > the new version set r g b 3 channel same, seams more reasonable
> > 
> > 
> 
> So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15,
> DISP_DITHER_16 is identical to mtk_dither_set(), so call
> mtk_dither_set() instead of duplication here.
> 

dither enable set in mtk_dither_set is
mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG);

that is different 8183 and mt8192.
mt8173 dither enable in gamma is bit2
mt8183 and mt8192 dither engine enable is bit 1


> Regards,
> CK
> > > 
> > > Regards,
> > > CK
> > > 
> > > > + &priv->cmdq_reg, priv->regs, 
> > > > DITHER_REG(16));
> > > > +   }
> > > > +
> > > > +
> > > > +   if (enable) {
> > > > +   u32 idx;
> > > > +
> > > > +   for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)
> > > > +   mtk_ddp_write(cmdq_pkt, dither_setting[idx], 
> > > > &priv->cmdq_reg, priv->regs,
> > > > + DITHER_REG(idx + 5));
> > > > +   }
> > > > +
> > > > mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, 
> > > > priv->regs, DISP_DITHER_SIZE);
> > > > -   mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, 
> > > > priv->regs, DISP_DITHER_CFG);
> > > > +mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : 
> > > > DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
> > > >  }
> > > >

[PATCH v11 3/9] drm/mediatek: add RDMA fifo size error handle

From: Yongqiang Niu 

This patch add RDMA fifo size error handle
rdma fifo size will not always bigger than the calculated threshold
if that case happened, we need set fifo size as the threshold

Signed-off-by: Yongqiang Niu 
Signed-off-by: Hsin-Yi Wang 
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index b84004394970f..04b9542010b00 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -168,6 +168,10 @@ void mtk_rdma_config(struct device *dev, unsigned int 
width,
 * account for blanking, and with a pixel depth of 4 bytes:
 */
threshold = width * height * vrefresh * 4 * 7 / 100;
+
+   if (threshold > rdma_fifo_size)
+   threshold = rdma_fifo_size;
+
reg = RDMA_FIFO_UNDERFLOW_EN |
  RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
  RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
-- 
2.30.0.280.ga3ce27912f-goog

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Re: [PATCH v10] staging: fbtft: add tearing signal detect

On Wed, 27 Jan 2021 15:13:05 +0100
Greg KH  wrote:

> On Wed, Jan 27, 2021 at 10:08:09PM +0800, carlis wrote:
> > On Wed, 27 Jan 2021 14:51:55 +0100
> > Greg KH  wrote:
> >   
> > > On Wed, Jan 27, 2021 at 09:42:52PM +0800, Carlis wrote:  
> > > > From: zhangxuezhi 
> > > > 
> > > > For st7789v ic,when we need continuous full screen refresh, it
> > > > is best to wait for the TE signal arrive to avoid screen tearing
> > > > 
> > > > Signed-off-by: zhangxuezhi 
> > > 
> > > Please slow down and wait at least a day between patch
> > > submissions, there is no rush here.
> > > 
> > > And also, ALWAYS run scripts/checkpatch.pl on your submissions, so
> > > that you don't have a maintainer asking you about basic problems,
> > > like are in this current patch :(
> > > 
> > > thanks,
> > > 
> > > greg k-h  
> > 
> > hi,
> >   This is my first patch contribution to Linux, so some of the rules
> > are not very clear .In addition, I can confirm that before sending
> > patch, I check it with checkPatch.py every time.Thank you very much
> > for your help  
> 
> Please read Documentation/SubmittingPatches which has a link to the
> checklist and other documentation you should read.
> 
> And I doubt you are running checkpatch on your submission, as there is
> obvious coding style issues in it.  If so, please provide the output
> as it must be broken :(
> 
> thanks,
> 
> greg k-h
hi, the patch v11 checkpatch.pl output is below:

carlis@bf-rmsz-10:~/work/linux-kernel/linux$ ./scripts/checkpatch.pl
0001-staging-fbtft-add-tearing-signal-detect.patch total: 0 errors, 0
warnings, 0 checks, 176 lines checked

0001-staging-fbtft-add-tearing-signal-detect.patch has no obvious style
problems and is ready for submission.


regards
zhangxuezhi

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[PATCH v5 1/2] dt-bindings: Add DT schema for Arm Mali Valhall GPU

2021-01-28 Thread Nick Fan

Add devicetree schema for Arm Mali Valhall GPU

Define a compatible string for the Mali Valhall GPU
for Mediatek's SoC platform.

Signed-off-by: Nick Fan 
---
 .../bindings/gpu/arm,mali-valhall.yaml| 217 ++
 1 file changed, 217 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml 
b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
new file mode 100644
index ..275c14ad173a
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
@@ -0,0 +1,217 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/arm,mali-valhall.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Mali Valhall GPU
+
+maintainers:
+  - Rob Herring 
+
+properties:
+  $nodename:
+pattern: '^gpu@[a-f0-9]+$'
+
+  compatible:
+items:
+  - enum:
+  - mediatek,mt8192-mali
+  - const: arm,mali-valhall
+
+  reg:
+maxItems: 1
+
+  interrupts:
+items:
+  - description: GPU interrupt
+  - description: MMU interrupt
+  - description: Job interrupt
+
+  interrupt-names:
+items:
+  - const: gpu
+  - const: mmu
+  - const: job
+
+  clocks:
+minItems: 1
+
+  power-domains:
+minItems: 1
+maxItems: 5
+
+  mali-supply: true
+  sram-supply: true
+
+  operating-points-v2: true
+  opp_table: true
+
+  "#cooling-cells":
+const: 2
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - clocks
+
+additionalProperties: false
+
+allOf:
+  - if:
+  properties:
+compatible:
+  contains:
+const: mediatek,mt8192-mali
+then:
+  properties:
+power-domains:
+  minItems: 5
+  maxItems: 5
+
+power-domain-names:
+  items:
+- const: core0
+- const: core1
+- const: core2
+- const: core3
+- const: core4
+
+  required:
+- sram-supply
+- power-domains
+
+examples:
+  - |
+#include 
+#include 
+
+gpu@1300 {
+   compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
+   reg = <0x1300 0x4000>;
+   interrupts =
+   ,
+   ,
+   ;
+   interrupt-names =
+   "gpu",
+   "mmu",
+   "job";
+
+   clocks = <&mfgcfg 0>;
+
+   power-domains =
+   <&spm 4>,
+   <&spm 5>,
+   <&spm 6>,
+   <&spm 7>,
+   <&spm 8>;
+
+   operating-points-v2 = <&gpu_opp_table>;
+   mali-supply = <&mt6315_7_vbuck1>;
+   sram-supply = <&mt6359_vsram_others_ldo_reg>;
+   gpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-35800 {
+   opp-hz = /bits/ 64 <35800>;
+   opp-microvolt = <606250>,
+   <75>;
+ };
+
+ opp-39900 {
+   opp-hz = /bits/ 64 <39900>;
+   opp-microvolt = <618750>,
+   <75>;
+ };
+
+ opp-44000 {
+   opp-hz = /bits/ 64 <44000>;
+   opp-microvolt = <631250>,
+   <75>;
+ };
+
+ opp-48200 {
+   opp-hz = /bits/ 64 <48200>;
+   opp-microvolt = <643750>,
+   <75>;
+ };
+
+ opp-52300 {
+   opp-hz = /bits/ 64 <52300>;
+   opp-microvolt = <656250>,
+   <75>;
+ };
+
+ opp-56400 {
+   opp-hz = /bits/ 64 <56400>;
+   opp-microvolt = <668750>,
+   <75>;
+ };
+
+ opp-60500 {
+   opp-hz = /bits/ 64 <60500>;
+   opp-microvolt = <681250>,
+   <75>;
+ };
+
+ opp-64700 {
+   opp-hz = /bits/ 64 <64700>;
+   opp-microvolt = <693750>,
+   <75>;
+ };
+
+ opp-68800 {
+   opp-hz = /bits/ 64 <68800>;
+   opp-microvolt = <706250>,
+   <75>;
+ };
+
+ opp-72400 {
+   opp-hz = /bits/ 64 <72400>;
+   opp-microvolt = <725000>,
+   <75>;
+ };
+
+ opp-7600

Re: [PATCH v10 4/9] drm/mediatek: generalize mtk_dither_set() function

On Thu, Jan 28, 2021 at 12:39 PM CK Hu  wrote:
>
> Hi, Hsin-Yi:
>
> On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> > There may be data structure other than mtk_ddp_comp_dev that would call
> > mtk_dither_set(), so use regs as parameter instead of device.
>
> You does not change the interface of mtk_dither_set(). You move the
> common part in mtk_dither_set() to a new function which could be called
> by another caller.
>
> Regards,
> CK.
>
Current mtk_dither_set() cast dev data to struct mtk_ddp_comp_dev. But
mtk_disp_gamma in next patch would also call this function. But it's
dev data is struct mtk_disp_gamma, which is different, so we can't
cast to mtk_ddp_comp_dev. I separate the necessary parameters (regs,
cmdq_reg) out, so both component dither and gamma can both call this
separated function.

This is similar to the mtk_gamma_set_common() in the next patch, which
gamma and aal both used.

> >
> > Signed-off-by: Hsin-Yi Wang 
> > ---
> >  drivers/gpu/drm/mediatek/mtk_disp_drv.h |  4 
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 25 +
> >  2 files changed, 20 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h 
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index 46d199b7b4a29..c50d5fc9fd349 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -17,6 +17,10 @@ void mtk_color_config(struct device *dev, unsigned int w,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> >  void mtk_color_start(struct device *dev);
> >
> > +void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg 
> > *cmdq_reg,
> > +unsigned int bpc, unsigned int CFG,
> > +struct cmdq_pkt *cmdq_pkt);
> > +
> >  void mtk_dpi_start(struct device *dev);
> >  void mtk_dpi_stop(struct device *dev);
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 7b5293429426d..53d25823a37cc 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -151,33 +151,40 @@ static void mtk_ddp_clk_disable(struct device *dev)
> >   clk_disable_unprepare(priv->clk);
> >  }
> >
> > -static void mtk_dither_set(struct device *dev, unsigned int bpc,
> > - unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
> > -{
> > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> >
> > +void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg 
> > *cmdq_reg,
> > +unsigned int bpc, unsigned int CFG, struct 
> > cmdq_pkt *cmdq_pkt)
> > +{
> >   /* If bpc equal to 0, the dithering function didn't be enabled */
> >   if (bpc == 0)
> >   return;
> >
> >   if (bpc >= MTK_MIN_BPC) {
> > - mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, 
> > DISP_DITHER_5);
> > - mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, 
> > DISP_DITHER_7);
> > + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
> > + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
> >   mtk_ddp_write(cmdq_pkt,
> > DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
> > DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> > DITHER_NEW_BIT_MODE,
> > -   &priv->cmdq_reg, priv->regs, DISP_DITHER_15);
> > +   cmdq_reg, regs, DISP_DITHER_15);
> >   mtk_ddp_write(cmdq_pkt,
> > DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
> > DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
> > DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
> > DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> > -   &priv->cmdq_reg, priv->regs, DISP_DITHER_16);
> > - mtk_ddp_write(cmdq_pkt, DISP_DITHERING, &priv->cmdq_reg, 
> > priv->regs, CFG);
> > +   cmdq_reg, regs, DISP_DITHER_16);
> > + mtk_ddp_write(cmdq_pkt, DISP_DITHERING, cmdq_reg, regs, CFG);
> >   }
> >  }
> >
> > +static void mtk_dither_set(struct device *dev, unsigned int bpc,
> > + unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
> > +{
> > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > + mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, CFG, 
> > cmdq_pkt);
> > +}
> > +
> >  static void mtk_od_config(struct device *dev, unsigned int w,
> > unsigned int h, unsigned int vrefresh,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
>
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Re: [PATCH v6] fbtft: add tearing signal detect

On Wed, 27 Jan 2021 11:59:51 +0300
Dan Carpenter  wrote:

> On Wed, Jan 27, 2021 at 03:28:22PM +0800, Carlis wrote:
> >  static int init_display(struct fbtft_par *par)
> >  {
> > +   int rc;
> > +   struct device *dev = par->info->device;
> > +
> > +   par->gpio.te = devm_gpiod_get_index_optional(dev, "te", 0,
> > GPIOD_IN);
> > +   if (IS_ERR(par->gpio.te)) {
> > +   rc = PTR_ERR(par->gpio.te);
> > +   pr_err("Failed to request te gpio: %d\n", rc);
> > +   par->gpio.te = NULL;
> > +   }
> > +   if (par->gpio.te) {
> > +   init_completion(&spi_panel_te);
> > +   mutex_init(&te_mutex);
> > +   rc = devm_request_irq(dev,
> > + gpiod_to_irq(par->gpio.te),
> > +spi_panel_te_handler,
> > IRQF_TRIGGER_RISING,
> > +"TE_GPIO", par);
> > +   if (rc) {
> > +   pr_err("TE request_irq failed.\n");
> > +   devm_gpiod_put(dev, par->gpio.te);
> > +   par->gpio.te = NULL;
> > +   } else {
> > +
> > disable_irq_nosync(gpiod_to_irq(par->gpio.te));
> > +   pr_info("TE request_irq completion.\n");  
> 
> #SadFaceEmoji
> 
> > +   }
> > +   } else {
> > +   pr_info("%s:%d, TE gpio not specified\n",
> > +   __func__, __LINE__);
> > +   }  
> 
> regards,
> dan carpenter
> 
Sorry,i will delete this log in patch v8
regards
zhangxuezhi
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[PATCH 2/2] video: omapfb: Remove WARN_ON(in_interrupt()).

From: "Ahmed S. Darwish" 

dsi_sync_vc() uses in_interrupt() to create a warning if the function is
used in non-preemptible context.

The usage of in_interrupt() in drivers is phased out and Linus clearly
requested that code which changes behaviour depending on context should
either be separated or the context be conveyed in an argument passed by the
caller, which usually knows the context.

The wait_for_completion() function (used in dsi_sync_vc_vp() and
dsi_sync_vc_l4() has already a check if it is invoked from proper
context.

Remove WARN_ON(in_interrupt()) from the driver.

Signed-off-by: Ahmed S. Darwish 
Signed-off-by: Sebastian Andrzej Siewior 
---
 drivers/video/fbdev/omap2/omapfb/dss/dsi.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/video/fbdev/omap2/omapfb/dss/dsi.c 
b/drivers/video/fbdev/omap2/omapfb/dss/dsi.c
index dc34bb04b865c..df90091de75f8 100644
--- a/drivers/video/fbdev/omap2/omapfb/dss/dsi.c
+++ b/drivers/video/fbdev/omap2/omapfb/dss/dsi.c
@@ -2373,8 +2373,6 @@ static int dsi_sync_vc(struct platform_device *dsidev, 
int channel)
 
WARN_ON_ONCE(!dsi_bus_is_locked(dsidev));
 
-   WARN_ON(in_interrupt());
-
if (!dsi_vc_is_enabled(dsidev, channel))
return 0;
 
-- 
2.30.0

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[PATCH v11 9/9] drm/mediatek: add support for mediatek SOC MT8183

From: Yongqiang Niu 

1. add ovl private data
2. add rdma private data
3. add gamma privte data
4. add main and external path module for crtc create

Signed-off-by: Yongqiang Niu 
Signed-off-by: Hsin-Yi Wang 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_disp_gamma.c |  1 +
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c   | 18 +
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c  |  6 +++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c| 45 +++
 4 files changed, 70 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
index 22199ef11f65d..16f73267bb202 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
@@ -180,6 +180,7 @@ static const struct mtk_disp_gamma_data 
mt8173_gamma_driver_data = {
 static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = {
{ .compatible = "mediatek,mt8173-disp-gamma",
  .data = &mt8173_gamma_driver_data},
+   { .compatible = "mediatek,mt8183-disp-gamma"},
{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c 
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 1c295c58a5e82..da7e38a28759b 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -424,11 +424,29 @@ static const struct mtk_disp_ovl_data 
mt8173_ovl_driver_data = {
.fmt_rgb565_is_0 = true,
 };
 
+static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
+   .addr = DISP_REG_OVL_ADDR_MT8173,
+   .gmc_bits = 10,
+   .layer_nr = 4,
+   .fmt_rgb565_is_0 = true,
+};
+
+static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
+   .addr = DISP_REG_OVL_ADDR_MT8173,
+   .gmc_bits = 10,
+   .layer_nr = 2,
+   .fmt_rgb565_is_0 = true,
+};
+
 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-ovl",
  .data = &mt2701_ovl_driver_data},
{ .compatible = "mediatek,mt8173-disp-ovl",
  .data = &mt8173_ovl_driver_data},
+   { .compatible = "mediatek,mt8183-disp-ovl",
+ .data = &mt8183_ovl_driver_data},
+   { .compatible = "mediatek,mt8183-disp-ovl-2l",
+ .data = &mt8183_ovl_2l_driver_data},
{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 04b9542010b00..29fa5f3a05c30 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -355,11 +355,17 @@ static const struct mtk_disp_rdma_data 
mt8173_rdma_driver_data = {
.fifo_size = SZ_8K,
 };
 
+static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
+   .fifo_size = 5 * SZ_1K,
+};
+
 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
  .data = &mt2701_rdma_driver_data},
{ .compatible = "mediatek,mt8173-disp-rdma",
  .data = &mt8173_rdma_driver_data},
+   { .compatible = "mediatek,mt8183-disp-rdma",
+ .data = &mt8183_rdma_driver_data},
{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c 
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 279d3e6f11563..486e73e675ad5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -129,6 +129,24 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
DDP_COMPONENT_DPI0,
 };
 
+static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
+   DDP_COMPONENT_OVL0,
+   DDP_COMPONENT_OVL_2L0,
+   DDP_COMPONENT_RDMA0,
+   DDP_COMPONENT_COLOR0,
+   DDP_COMPONENT_CCORR,
+   DDP_COMPONENT_AAL0,
+   DDP_COMPONENT_GAMMA,
+   DDP_COMPONENT_DITHER,
+   DDP_COMPONENT_DSI0,
+};
+
+static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
+   DDP_COMPONENT_OVL_2L1,
+   DDP_COMPONENT_RDMA1,
+   DDP_COMPONENT_DPI0,
+};
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -161,6 +179,13 @@ static const struct mtk_mmsys_driver_data 
mt8173_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
+   .main_path = mt8183_mtk_ddp_main,
+   .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
+   .ext_path = mt8183_mtk_ddp_ext,
+   .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
+};
+
 static int mtk_drm_kms_init(struct drm_device *drm)
 {
struct mtk_drm_private *private = drm->dev_private;
@@ -375,12 +400,20 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
  .data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8173-disp-o

Re: [PATCH v10 8/9] drm/mediatek: add DDP support for MT8183

On Thu, Jan 28, 2021 at 2:13 PM CK Hu  wrote:
>
> Hi, Hsin-Yi:
>
> Modify the title's prefix to 'soc: mediatek:'
>
> On Wed, 2021-01-27 at 12:54 +0800, Hsin-Yi Wang wrote:
> > From: Yongqiang Niu 
> >
> > Add DDP support for MT8183 SoC.
> >
> > Signed-off-by: Yongqiang Niu 
> > Signed-off-by: Hsin-Yi Wang 
> > ---
> >  drivers/soc/mediatek/mtk-mutex.c | 50 
> >  1 file changed, 50 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c 
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index f531b119da7a9..f64e9c33e85ad 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -14,6 +14,8 @@
> >
> >  #define MT2701_MUTEX0_MOD0   0x2c
> >  #define MT2701_MUTEX0_SOF0   0x30
> > +#define MT8183_DISP_MUTEX0_MOD0  0x30
> > +#define MT8183_DISP_MUTEX0_SOF0  0x2c
>
> Modify 'DISP_MUTEX' to 'MUTEX'
>
> >
> >  #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> >  #define DISP_REG_MUTEX(n)(0x24 + 0x20 * (n))
> > @@ -37,6 +39,18 @@
> >  #define MT8167_MUTEX_MOD_DISP_DITHER 15
> >  #define MT8167_MUTEX_MOD_DISP_UFOE   16
> >
> > +#define MT8183_MUTEX_MOD_DISP_RDMA0  0
> > +#define MT8183_MUTEX_MOD_DISP_RDMA1  1
> > +#define MT8183_MUTEX_MOD_DISP_OVL0   9
> > +#define MT8183_MUTEX_MOD_DISP_OVL0_2L10
> > +#define MT8183_MUTEX_MOD_DISP_OVL1_2L11
> > +#define MT8183_MUTEX_MOD_DISP_WDMA0  12
> > +#define MT8183_MUTEX_MOD_DISP_COLOR0 13
> > +#define MT8183_MUTEX_MOD_DISP_CCORR0 14
> > +#define MT8183_MUTEX_MOD_DISP_AAL0   15
> > +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
> > +#define MT8183_MUTEX_MOD_DISP_DITHER017
> > +
> >  #define MT8173_MUTEX_MOD_DISP_OVL0   11
> >  #define MT8173_MUTEX_MOD_DISP_OVL1   12
> >  #define MT8173_MUTEX_MOD_DISP_RDMA0  13
> > @@ -87,6 +101,12 @@
> >  #define MT2712_MUTEX_SOF_DSI36
> >  #define MT8167_MUTEX_SOF_DPI02
> >  #define MT8167_MUTEX_SOF_DPI13
> > +#define MT8183_MUTEX_SOF_DSI01
> > +#define MT8183_MUTEX_SOF_DPI02
> > +
> > +/* Add EOF setting so overlay hardware can receive frame done irq */
> > +#define MT8183_MUTEX_EOF_DSI0
> > (MT8183_MUTEX_SOF_DSI0 << 6)
> > +#define MT8183_MUTEX_EOF_DPI0
> > (MT8183_MUTEX_SOF_DPI0 << 6)
> >

Hi CK, comment is added here. I can move to mt8183_mutex_sof if preferred.

> >  struct mtk_mutex {
> >   int id;
> > @@ -181,6 +201,20 @@ static const unsigned int 
> > mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> >   [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
> >  };
> >
> > +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> > + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> > + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> > + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> > + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> > + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> > + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> > + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
> > + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
> > + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
> > + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> > +};
> > +
> >  static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> >   [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> >   [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> > @@ -198,6 +232,12 @@ static const unsigned int 
> > mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> >   [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
> >  };
> >
> > +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> > + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> > + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> > + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
>
> According to discussion in [1], add comment for the odd EOF setting.
>
> [1]
> https://patchwork.kernel.org/project/linux-mediatek/patch/1595469798-3824-8-git-send-email-yongqiang@mediatek.com/
>
> Regards,
> CK.
>
>
> > +};
> > +
> >  static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> >   .mutex_mod = mt2701_mutex_mod,
> >   .mutex_sof = mt2712_mutex_sof,
> > @@ -227,6 +267,14 @@ static const struct mtk_mutex_data 
> > mt8173_mutex_driver_data = {
> >   .mutex_sof_reg = MT2701_MUTEX0_SOF0,
> >  };
> >
> > +static const struct mtk_mutex_data mt8183_mutex_driver_data = {
> > + .mutex_mod = mt8183_mutex_mod,
> > + .mutex_sof = mt8183_mutex_sof,
> > + .mut

Re: [PATCH v5 00/21] sync_file API is not very suitable for DRM

28.01.2021 00:53, Mikko Perttunen пишет:
> On 1/27/21 11:35 PM, Dmitry Osipenko wrote:
>> 26.01.2021 05:45, Mikko Perttunen пишет:
 4. Sync file shouldn't be needed for the part of DRM API which doesn't
 interact with external non-DRM devices.  We should use DRM syncobj for
 everything related to DRM, it's a superior API over sync file, it's
 suitable for DRM scheduler.
>>>
>>> Considering the issues with fileno limits, I suppose there is no other
>>> choice. Considering the recent NTSYNC proposal by Wine developers, maybe
>>> we should also have NTHANDLEs to get rid of restrictions of file
>>> descriptors.
>>
>> It's odd to me that you trying to avoid the existing DRM API. This all
>> was solved in DRM long time ago and grate drivers have no problems with
>> using the DRM APIs. Even if something is really missing, then you should
>> add the missing features instead of re-inventing everything from scratch.
>>
> 
> DRM is only one of many subsystems that will have to deal with
> syncpoints, so I have wanted to have a central solution instead of
> reimplementing the same stuff everywhere. sync_files seem like the
> "missing feature", but they are difficult to use it with the fileno
> limits. But as has been said many times, they are intended only to
> transfer fences between the implementations in individual drivers, so I
> guess I will have to abandon this dream.

Let's focus on finishing the basics first, using what we already have.
Sync file + syncobj should be good enough for what we need right now.

>>> DRM syncobjs may have some advantages over sync files, but
>>> also disadvantages. They cannot be poll()ed, so they cannot be combined
>>> with waits for other resources.
>>
>> I'm not sure do you mean by "poll". Sync object supports polling very
>> well.
>>
> 
> I mean the poll/select etc. series of functions, which wait for file
> descriptors to become ready. If there's some trick that allows syncobjs
> to be used for that, then please tell.

Please explain in details what problem you need to solve, give an example.
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Re: [PATCH v3, 07/15] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase

2021-01-28 Thread Yongqiang Niu

On Tue, 2021-01-12 at 07:59 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
> 
> Yongqiang Niu  於 2021年1月11日 週一 下午3:44寫道：
> >
> > enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
> 
> Could you describe more information? Without this patch, what would happen?
> 

without this patch, ovl will hang up when more than 1 layer enabled

> >
> > Signed-off-by: Yongqiang Niu 
> > ---
> >  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12 
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c 
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > index b47c238..4934bee 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > @@ -23,6 +23,7 @@
> >  #define DISP_REG_OVL_RST   0x0014
> >  #define DISP_REG_OVL_ROI_SIZE  0x0020
> >  #define DISP_REG_OVL_DATAPATH_CON  0x0024
> > +#define OVL_LAYER_SMI_ID_ENBIT(0)
> >  #define OVL_BGCLR_SEL_IN   BIT(2)
> >  #define DISP_REG_OVL_ROI_BGCLR 0x0028
> >  #define DISP_REG_OVL_SRC_CON   0x002c
> > @@ -61,6 +62,7 @@ struct mtk_disp_ovl_data {
> > unsigned int gmc_bits;
> > unsigned int layer_nr;
> > bool fmt_rgb565_is_0;
> > +   bool smi_id_en;
> >  };
> >
> >  /**
> > @@ -116,7 +118,17 @@ static void mtk_ovl_disable_vblank(struct mtk_ddp_comp 
> > *comp)
> >
> >  static void mtk_ovl_start(struct mtk_ddp_comp *comp)
> >  {
> > +   struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
> > +
> > writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN);
> > +
> > +   if(ovl->data->smi_id_en) {
> > +   unsigned int reg;
> > +
> > +   reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
> > +   reg = reg | OVL_LAYER_SMI_ID_EN;
> > +   writel_relaxed(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
> 
> I think this setting should before write 1 to DISP_REG_OVL_EN.
> 
> > +   }
> >  }
> >
> >  static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
> 
> Should clear DISP_REG_OVL_DATAPATH_CON when stop?
> 
> Regards,
> Chun-Kuang.
> 
> > --
> > 1.8.1.1.dirty
> > ___
> > Linux-mediatek mailing list
> > linux-media...@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek

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Re: [PATCH v10] staging: fbtft: add tearing signal detect

On Thu, 28 Jan 2021 00:32:22 +0200
Kari Argillander  wrote:

> On Wed, Jan 27, 2021 at 09:42:52PM +0800, Carlis wrote:
> > For st7789v ic,when we need continuous full screen refresh, it is
> > best to wait for the TE signal arrive to avoid screen tearing  
>  
> > diff --git a/drivers/staging/fbtft/fb_st7789v.c
> > b/drivers/staging/fbtft/fb_st7789v.c index 3a280cc..cba08a8 100644
> > --- a/drivers/staging/fbtft/fb_st7789v.c
> > +++ b/drivers/staging/fbtft/fb_st7789v.c
> > @@ -9,9 +9,12 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> > +#include 
> > +#include 
> >  #include 
> >  #include 
> > -
> > +#include   
> 
> Space after local headers. Also this should one up so all Linux
> headers are group together. You agreed?
> 
OK,i will fix it in patch v12 tomorrow

> >  #include "fbtft.h"
> >  
> >  #define DRVNAME "fb_st7789v"
> > @@ -66,6 +69,32 @@ enum st7789v_command {
> >  #define MADCTL_MX BIT(6) /* bitmask for column address order */
> >  #define MADCTL_MY BIT(7) /* bitmask for page address order */
> >  
> > +#define SPI_PANEL_TE_TIMEOUT   400 /* msecs */
> > +static struct mutex te_mutex;/* mutex for set te gpio irq status
> > */  
> 
> Space after ;
hi, i have fix it in the patch v11
> 
> > +static struct completion spi_panel_te;  
> 
> What if multiple displays? Is this possible for user?
I will check it carefully again about this logic.
> 
> > +
> > +static irqreturn_t spi_panel_te_handler(int irq, void *data)
> > +{
> > +   complete(&spi_panel_te);
> > +   return IRQ_HANDLED;
> > +}
> > +
> > +static void set_spi_panel_te_irq_status(struct fbtft_par *par,
> > bool enable) +{
> > +   static int te_irq_count;  
> 
> Same here. Maybe you can think better way and then this code would
> also be cleaner.
> 
> > +
> > +   mutex_lock(&te_mutex);  
> 
> So locking should be done if we really do action and not just in case.
> 
> > +
> > +   if (enable) {
> > +   if (++te_irq_count == 1)
> > +   enable_irq(gpiod_to_irq(par->gpio.te));
> > +   } else {
> > +   if (--te_irq_count == 0)
> > +   disable_irq(gpiod_to_irq(par->gpio.te));
> > +   }
> > +   mutex_unlock(&te_mutex);
> > +}
> > +
> >  /**
> >   * init_display() - initialize the display controller
> >   *
> > @@ -82,6 +111,33 @@ enum st7789v_command {
> >   */
> >  static int init_display(struct fbtft_par *par)
> >  {
> > +   int rc;
> > +   struct device *dev = par->info->device;
> > +
> > +   par->gpio.te = devm_gpiod_get_index_optional(dev, "te", 0,
> > GPIOD_IN);
> > +   if (IS_ERR(par->gpio.te)) {
> > +   rc = PTR_ERR(par->gpio.te);
> > +   dev_err(par->info->device, "Failed to request te
> > gpio: %d\n", rc);
> > +   return rc;
> > +   }  
> 
> You request with optinal and you still want to error out? We could
> just continue and not care about that error. User will be happier if
> device still works somehow.
You mean i just delete this dev_err print ?!
like this:
par->gpio.te = devm_gpiod_get_index_optional(dev, "te",
0,GPIOD_IN); 
if (IS_ERR(par->gpio.te))
return PTR_ERR(par->gpio.te);
> 
> > +   if (par->gpio.te) {
> > +   init_completion(&spi_panel_te);
> > +   mutex_init(&te_mutex);
> > +   rc = devm_request_irq(dev,
> > + gpiod_to_irq(par->gpio.te),
> > +spi_panel_te_handler,
> > IRQF_TRIGGER_RISING,
> > +"TE_GPIO", par);
> > +   if (rc) {
> > +   dev_err(par->info->device, "TE request_irq
> > failed.\n");
> > +   devm_gpiod_put(dev, par->gpio.te);
> > +   return rc;
> > +   }
> > +
> > +   disable_irq_nosync(gpiod_to_irq(par->gpio.te));
> > +   } else {
> > +   dev_info(par->info->device, "%s:%d, TE gpio not
> > specified\n",
> > +__func__, __LINE__);
> > +   }
> > /* turn off sleep mode */
> > write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE);
> > mdelay(120);
> > @@ -137,6 +193,9 @@ static int init_display(struct fbtft_par *par)
> >  */
> > write_reg(par, PWCTRL1, 0xA4, 0xA1);
> >  
> > +/*Tearing Effect Line On*/  
> 
> Spaces and why upcase everything?
i will fix it in patch v12 tomorrow
> 
> > +   if (par->gpio.te)
> > +   write_reg(par, 0x35, 0x00);
> > write_reg(par, MIPI_DCS_SET_DISPLAY_ON);
> >  
> > if (HSD20_IPS)
> > @@ -145,6 +204,76 @@ static int init_display(struct fbtft_par *par)
> > return 0;
> >  }
> >  
> > +/*
> > + *
> > + *   int (*write_vmem)(struct fbtft_par *par);
> > + *
> > +
> > */
> > +  
> 
> Why this kind of function comment? Please use same as another function
> comments in this file. They are atleast almoust like kernel-doc style.
i will fix it in patch v12 tomorrow
> > +/* 16 bit pi

[PATCH v11 5/9] drm/mediatek: separate gamma module