Re: [patch V3 13/37] mips/mm/highmem: Switch to generic kmap atomic
Hi Thomas, Le sam. 9 janv. 2021 à 1:33, Thomas Bogendoerfer a écrit : On Sat, Jan 09, 2021 at 12:58:05AM +0100, Thomas Bogendoerfer wrote: On Fri, Jan 08, 2021 at 08:20:43PM +, Paul Cercueil wrote: > Hi Thomas, > > 5.11 does not boot anymore on Ingenic SoCs, I bisected it to this commit. > > Any idea what could be happening? not yet, kernel crash log of a Malta QEMU is below. update: This dirty hack lets the Malta QEMU boot again: diff --git a/mm/highmem.c b/mm/highmem.c index c3a9ea7875ef..190cdda1149d 100644 --- a/mm/highmem.c +++ b/mm/highmem.c @@ -515,7 +515,7 @@ void *__kmap_local_pfn_prot(unsigned long pfn, pgprot_t prot) vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); BUG_ON(!pte_none(*(kmap_pte - idx))); pteval = pfn_pte(pfn, prot); - set_pte_at(&init_mm, vaddr, kmap_pte - idx, pteval); + set_pte(kmap_pte - idx, pteval); arch_kmap_local_post_map(vaddr, pteval); current->kmap_ctrl.pteval[kmap_local_idx()] = pteval; preempt_enable(); set_pte_at() tries to update cache and could do an kmap_atomic() there. Not sure, if this is allowed at this point. Yes, I can confirm that your workaround works here too. Cheers, -Paul ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3, 00/15] drm/mediatek: add support for mediatek SOC MT8192
This series are based on 5.11-rc1 and SoC MT8183, and provide 15 patch to support mediatek SOC MT8192 Changes since v2: - fix review comment in v2 - add pm runtime for gamma and color - move ddp path select patch to mmsys series - remove some useless patch Yongqiang Niu (15): dt-bindings: mediatek: add description for postmask dt-bindings: mediatek: add description for mt8192 display arm64: dts: mt8192: add display node drm/mediatek: add component OVL_2L2 drm/mediatek: add component POSTMASK drm/mediatek: add component RDMA4 drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase drm/mediatek: check if fb is null drm/mediatek: Add pm runtime support for gamma drm/mediatek: Add pm runtime support for color drm/mediatek: fix aal size config drm/mediatek: separate ccorr module drm/mediatek: add matrix bits private data for ccorr drm/mediatek: add DDP support for MT8192 drm/mediatek: add support for mediatek SOC MT8192 .../bindings/display/mediatek/mediatek,disp.txt| 3 +- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 +++ drivers/gpu/drm/mediatek/Makefile | 4 +- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 245 + drivers/gpu/drm/mediatek/mtk_disp_color.c | 5 + drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 5 + drivers/gpu/drm/mediatek/mtk_disp_ovl.c| 34 ++- drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 161 ++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 + drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 35 +++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c| 98 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h| 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 52 - drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 + 14 files changed, 687 insertions(+), 98 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c -- 1.8.1.1.dirty ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3, 15/15] drm/mediatek: add support for mediatek SOC MT8192
add support for mediatek SOC MT8192
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c| 6
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 +
drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 1 +
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42
5 files changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
index 755e75b..da3fd98 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
@@ -221,9 +221,15 @@ static int mtk_disp_ccorr_remove(struct platform_device
*pdev)
.matrix_bits = CCORR_MATRIX_BITS,
};
+static const struct mtk_disp_ccorr_data mt8192_ccorr_driver_data = {
+ .matrix_bits = 13,
+};
+
static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
{ .compatible = "mediatek,mt8183-disp-ccorr",
.data = &mt8183_ccorr_driver_data},
+ { .compatible = "mediatek,mt8192-disp-ccorr",
+ .data = &mt8192_ccorr_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 8e7f494..4e6679e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -457,6 +457,22 @@ static int mtk_disp_ovl_remove(struct platform_device
*pdev)
.fmt_rgb565_is_0 = true,
};
+static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
+ .addr = DISP_REG_OVL_ADDR_MT8173,
+ .gmc_bits = 10,
+ .layer_nr = 4,
+ .fmt_rgb565_is_0 = true,
+ .smi_id_en = true,
+};
+
+static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
+ .addr = DISP_REG_OVL_ADDR_MT8173,
+ .gmc_bits = 10,
+ .layer_nr = 2,
+ .fmt_rgb565_is_0 = true,
+ .smi_id_en = true,
+};
+
static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-ovl",
.data = &mt2701_ovl_driver_data},
@@ -466,6 +482,10 @@ static int mtk_disp_ovl_remove(struct platform_device
*pdev)
.data = &mt8183_ovl_driver_data},
{ .compatible = "mediatek,mt8183-disp-ovl-2l",
.data = &mt8183_ovl_2l_driver_data},
+ { .compatible = "mediatek,mt8192-disp-ovl",
+ .data = &mt8192_ovl_driver_data},
+ { .compatible = "mediatek,mt8192-disp-ovl-2l",
+ .data = &mt8192_ovl_2l_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
index 736224c..3b38157 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
@@ -145,6 +145,7 @@ static int mtk_disp_postmask_remove(struct platform_device
*pdev)
}
static const struct of_device_id mtk_disp_postmask_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8192-disp-postmask"},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_postmask_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index e914e3a..b160ebe 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -364,6 +364,10 @@ static int mtk_disp_rdma_remove(struct platform_device
*pdev)
.fifo_size = 5 * SZ_1K,
};
+static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
+ .fifo_size = 5 * SZ_1K,
+};
+
static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = &mt2701_rdma_driver_data},
@@ -371,6 +375,8 @@ static int mtk_disp_rdma_remove(struct platform_device
*pdev)
.data = &mt8173_rdma_driver_data},
{ .compatible = "mediatek,mt8183-disp-rdma",
.data = &mt8183_rdma_driver_data},
+ { .compatible = "mediatek,mt8192-disp-rdma",
+ .data = &mt8192_rdma_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 79e86f7..24ce37c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -149,6 +149,25 @@
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_OVL_2L0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_POSTMASK0,
+ DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DSI0,
+};
+
+static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
+ DDP_COMPONENT_OVL_2L2,
+ DDP_COMPONENT_RDMA4,
+ DDP_COMPONENT
[PATCH 2/3] drm/sun4i: de2/de3: Remove redundant CSC matrices
YUV to RGB matrices are almost identical to YVU to RGB matrices. They
only have second and third column reversed. Do that reversion in code in
order to lower amount of static data and redundancy.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_csc.c | 99 +++
1 file changed, 34 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c
b/drivers/gpu/drm/sun4i/sun8i_csc.c
index 5c6ad643dae2..1d10714e417e 100644
--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
+++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
@@ -46,33 +46,6 @@ static const u32 yuv2rgb[2][2][12] = {
},
};
-static const u32 yvu2rgb[2][2][12] = {
- [DRM_COLOR_YCBCR_LIMITED_RANGE] = {
- [DRM_COLOR_YCBCR_BT601] = {
- 0x04A8, 0x0662, 0x, 0xFFFC8451,
- 0x04A8, 0xFCC0, 0xFE6F, 0x00021E4D,
- 0x04A8, 0x, 0x0811, 0xFFFBACA9,
- },
- [DRM_COLOR_YCBCR_BT709] = {
- 0x04A8, 0x072B, 0x, 0xFFFC1F99,
- 0x04A8, 0xFDDF, 0xFF26, 0x00013383,
- 0x04A8, 0x, 0x0873, 0xFFFB7BEF,
- }
- },
- [DRM_COLOR_YCBCR_FULL_RANGE] = {
- [DRM_COLOR_YCBCR_BT601] = {
- 0x0400, 0x059B, 0x, 0xFFFD322E,
- 0x0400, 0xFD25, 0xFEA0, 0x00021DD5,
- 0x0400, 0x, 0x0716, 0xFFFC74BD,
- },
- [DRM_COLOR_YCBCR_BT709] = {
- 0x0400, 0x064C, 0x, 0xFFFCD9B4,
- 0x0400, 0xFE21, 0xFF41, 0x00014F96,
- 0x0400, 0x, 0x076C, 0xFFFC49EF,
- }
- },
-};
-
/*
* DE3 has a bit different CSC units. Factors are in two's complement format.
* First three factors in a row are multiplication factors which have 17 bits
@@ -123,33 +96,6 @@ static const u32 yuv2rgb_de3[2][2][12] = {
},
};
-static const u32 yvu2rgb_de3[2][2][12] = {
- [DRM_COLOR_YCBCR_LIMITED_RANGE] = {
- [DRM_COLOR_YCBCR_BT601] = {
- 0x0002542A, 0x0003312A, 0x, 0xFFC0,
- 0x0002542A, 0xFFFE5FC3, 0x376B, 0xFE00,
- 0x0002542A, 0x, 0x000408D2, 0xFE00,
- },
- [DRM_COLOR_YCBCR_BT709] = {
- 0x0002542A, 0x000395E2, 0x, 0xFFC0,
- 0x0002542A, 0xFFFEEF27, 0x92D2, 0xFE00,
- 0x0002542A, 0x, 0x0004398C, 0xFE00,
- }
- },
- [DRM_COLOR_YCBCR_FULL_RANGE] = {
- [DRM_COLOR_YCBCR_BT601] = {
- 0x0002, 0x0002CDD2, 0x, 0x,
- 0x0002, 0xFFFE925D, 0x4FCE, 0xFE00,
- 0x0002, 0x, 0x00038B43, 0xFE00,
- },
- [DRM_COLOR_YCBCR_BT709] = {
- 0x0002, 0x0003264C, 0x, 0x,
- 0x0002, 0x1053, 0xA018, 0xFE00,
- 0x0002, 0x, 0x0003B611, 0xFE00,
- }
- },
-};
-
static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
enum sun8i_csc_mode mode,
enum drm_color_encoding encoding,
@@ -157,21 +103,30 @@ static void sun8i_csc_set_coefficients(struct regmap
*map, u32 base,
{
const u32 *table;
u32 base_reg;
+ int i;
+
+ table = yuv2rgb[range][encoding];
switch (mode) {
case SUN8I_CSC_MODE_YUV2RGB:
- table = yuv2rgb[range][encoding];
+ base_reg = SUN8I_CSC_COEFF(base, 0);
+ regmap_bulk_write(map, base_reg, table, 12);
break;
case SUN8I_CSC_MODE_YVU2RGB:
- table = yvu2rgb[range][encoding];
+ for (i = 0; i < 12; i++) {
+ if ((i & 3) == 1)
+ base_reg = SUN8I_CSC_COEFF(base, i + 1);
+ else if ((i & 3) == 2)
+ base_reg = SUN8I_CSC_COEFF(base, i - 1);
+ else
+ base_reg = SUN8I_CSC_COEFF(base, i);
+ regmap_write(map, base_reg, table[i]);
+ }
break;
default:
DRM_WARN("Wrong CSC mode specified.\n");
return;
}
-
- base_reg = SUN8I_CSC_COEFF(base, 0);
- regmap_bulk_write(map, base_reg, table, 12);
}
static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer,
@@ -180,22 +135,36 @@ static void sun8i_de3_ccsc_set_coefficients(st
[PATCH 1/3] drm/sun4i: csc: Rework DE3 CSC macros
Rework DE3 CSC macros to take just one coordinate instead of two. This will make its usage easier in subsequent commit. Signed-off-by: Jernej Skrabec --- drivers/gpu/drm/sun4i/sun8i_csc.c | 2 +- drivers/gpu/drm/sun4i/sun8i_mixer.h | 6 ++ 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c index 781955dd4995..5c6ad643dae2 100644 --- a/drivers/gpu/drm/sun4i/sun8i_csc.c +++ b/drivers/gpu/drm/sun4i/sun8i_csc.c @@ -194,7 +194,7 @@ static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer, return; } - base_reg = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0, 0); + base_reg = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0); regmap_bulk_write(map, base_reg, table, 12); } diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h index 7576b523fdbb..145833a9d82d 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h @@ -50,10 +50,8 @@ #define SUN8I_MIXER_BLEND_CK_MIN(base, x) ((base) + 0xe0 + 0x04 * (x)) #define SUN8I_MIXER_BLEND_OUTCTL(base) ((base) + 0xfc) #define SUN50I_MIXER_BLEND_CSC_CTL(base) ((base) + 0x100) -#define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x, y) \ - ((base) + 0x110 + (layer) * 0x30 + (x) * 0x10 + 4 * (y)) -#define SUN50I_MIXER_BLEND_CSC_CONST(base, layer, i) \ - ((base) + 0x110 + (layer) * 0x30 + (i) * 0x10 + 0x0c) +#define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x) \ + ((base) + 0x110 + (layer) * 0x30 + (x) * 4) #define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK GENMASK(12, 8) #define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe)BIT(8 + pipe) -- 2.30.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3, 12/15] drm/mediatek: separate ccorr module
ccorr ctm matrix bits will be different in mt8192
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 222
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 92 +---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
5 files changed, 231 insertions(+), 95 deletions(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index ce5ad59..a02f534 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
-mediatek-drm-y := mtk_disp_color.o \
+mediatek-drm-y := mtk_disp_ccorr.o \
+ mtk_disp_color.o \
mtk_disp_gamma.o \
mtk_disp_ovl.o \
mtk_disp_postmask.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
new file mode 100644
index 000..63b3ef6
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
@@ -0,0 +1,222 @@
+/*
+ * SPDX-License-Identifier:
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+
+#define DISP_CCORR_EN 0x
+#define CCORR_EN BIT(0)
+#define DISP_CCORR_CFG 0x0020
+#define CCORR_RELAY_MODE BIT(0)
+#define CCORR_ENGINE_ENBIT(1)
+#define CCORR_GAMMA_OFFBIT(2)
+#define CCORR_WGAMUT_SRC_CLIP BIT(3)
+#define DISP_CCORR_SIZE0x0030
+#define DISP_CCORR_COEF_0 0x0080
+#define DISP_CCORR_COEF_1 0x0084
+#define DISP_CCORR_COEF_2 0x0088
+#define DISP_CCORR_COEF_3 0x008C
+#define DISP_CCORR_COEF_4 0x0090
+
+struct mtk_disp_ccorr_data {
+ u32 reserved;
+};
+
+/**
+ * struct mtk_disp_ccorr - DISP_CCORR driver structure
+ * @ddp_comp - structure containing type enum and hardware resources
+ * @crtc - associated crtc to report irq events to
+ */
+struct mtk_disp_ccorr {
+ struct mtk_ddp_comp ddp_comp;
+ const struct mtk_disp_ccorr_data*data;
+};
+
+static inline struct mtk_disp_ccorr *comp_to_ccorr(struct mtk_ddp_comp *comp)
+{
+ return container_of(comp, struct mtk_disp_ccorr, ddp_comp);
+}
+
+static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
+unsigned int h, unsigned int vrefresh,
+unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_CCORR_SIZE);
+ mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
+}
+
+static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
+{
+ writel(CCORR_EN, comp->regs + DISP_CCORR_EN);
+}
+
+static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
+{
+ writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
+}
+
+/* Converts a DRM S31.32 value to the HW S1.10 format. */
+static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
+{
+ u16 r;
+
+ /* Sign bit. */
+ r = in & BIT_ULL(63) ? BIT(11) : 0;
+
+ if ((in & GENMASK_ULL(62, 33)) > 0) {
+ /* identity value 0x1 -> 0x400, */
+ /* if bigger this, set it to max 0x7ff. */
+ r |= GENMASK(10, 0);
+ } else {
+ /* take the 11 most important bits. */
+ r |= (in >> 22) & GENMASK(10, 0);
+ }
+
+ return r;
+}
+
+static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
+ struct drm_crtc_state *state)
+{
+ struct drm_property_blob *blob = state->ctm;
+ struct drm_color_ctm *ctm;
+ const u64 *input;
+ uint16_t coeffs[9] = { 0 };
+ int i;
+ struct cmdq_pkt *cmdq_pkt = NULL;
+
+ if (!blob)
+ return;
+
+ ctm = (struct drm_color_ctm *)blob->data;
+ input = ctm->matrix;
+
+ for (i = 0; i < ARRAY_SIZE(coeffs); i++)
+ coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
+
+ mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
+ comp, DISP_CCORR_COEF_0);
+ mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
+ comp, DISP_CCORR_COEF_1);
+ mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
+ comp, DISP_CCORR_COEF_2);
+ mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
+ comp, DISP_CCORR_COEF_3);
+ mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
+ comp, DIS
[PATCH v3, 03/15] arm64: dts: mt8192: add display node
add display node
Signed-off-by: Yongqiang Niu
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 +++
1 file changed, 134 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index e12e024..dcf9fdf 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -15,6 +15,11 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ ovl2-2l2 = &ovl_2l2;
+ rdma4 = &rdma4;
+ };
+
clk26m: oscillator0 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -508,5 +513,134 @@
#size-cells = <0>;
status = "disabled";
};
+
+ mmsys: syscon@1400 {
+ compatible = "mediatek,mt8192-mmsys", "syscon";
+ reg = <0 0x1400 0 0x1000>;
+ //mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
+ // <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400 0
0x1000>;
+ #clock-cells = <1>;
+ };
+
+mutex: mutex@14001000 {
+ compatible = "mediatek,mt8192-disp-mutex";
+ reg = <0 0x14001000 0 0x1000>;
+ interrupts = ;
+ //clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+ //mediatek,gce-events =
,
+ //
;
+ };
+
+ ovl0: ovl@14005000 {
+ compatible = "mediatek,mt8192-disp-ovl";
+ reg = <0 0x14005000 0 0x1000>;
+ interrupts = ;
+ //clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ //iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400
0x5000 0x1000>;
+ };
+
+ ovl_2l0: ovl@14006000 {
+ compatible = "mediatek,mt8192-disp-ovl-2l";
+ reg = <0 0x14006000 0 0x1000>;
+ interrupts = ;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ //clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+ //iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400
0x6000 0x1000>;
+ };
+
+ rdma0: rdma@14007000 {
+ compatible = "mediatek,mt8192-disp-rdma";
+ reg = <0 0x14007000 0 0x1000>;
+ interrupts = ;
+ //clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ //iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
+ //mediatek,larb = <&larb0>;
+ //mediatek,rdma-fifo-size = <5120>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400
0x7000 0x1000>;
+ };
+
+ color0: color@14009000 {
+ compatible = "mediatek,mt8192-disp-color",
+"mediatek,mt8173-disp-color";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = ;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ //clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400
0x9000 0x1000>;
+ };
+
+ ccorr0: ccorr@1400a000 {
+ compatible = "mediatek,mt8192-disp-ccorr";
+ reg = <0 0x1400a000 0 0x1000>;
+ interrupts = ;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ //clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400
0xa000 0x1000>;
+ };
+
+ aal0: aal@1400b000 {
+ compatible = "mediatek,mt8192-disp-aal";
+ reg = <0 0x1400b000 0 0x1000>;
+ interrupts = ;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ //clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400
0xb000 0x1000>;
+ };
+
+ gamma0: gamma@1400c000 {
+ compatible = "mediatek,mt8183-disp-gamma",
+"mediatek,mt8192-disp-gamma";
+ reg = <0 0x1400c000 0 0x1000>;
Re: [PATCH v1] drm/panel: simple: add SGD GKTW70SDAD1SD
On 09/01/21, Fabio Estevam wrote: > Hi Oliver, > > On Fri, Jan 8, 2021 at 7:24 PM Oliver Graute wrote: > > > > On 19/12/20, Oliver Graute wrote: > > > Add support for the Solomon Goldentek Display Model: GKTW70SDAD1SD > > > to panel-simple. > > > > > > The panel spec from Variscite can be found at: > > > https://www.variscite.com/wp-content/uploads/2017/12/VLCD-CAP-GLD-RGB.pdf > > > > some clue what bus_format and bus_flags I have to use? > > > > [ 42.505156] panel-simple panel-lcd: Specify missing bus_flags > > [ 42.511090] panel-simple panel-lcd: Specify missing bus_format > > [ 42.615131] mxsfb 21c8000.lcdif: Cannot connect bridge: -517 > > Does this patch work? > https://pastebin.com/raw/diTMVsh8 the first two errors are gone. But I still get this: [ 42.387107] mxsfb 21c8000.lcdif: Cannot connect bridge: -517 The panel is still off perhaps I miss something else. Best Regards, Oliver ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [patch V3 13/37] mips/mm/highmem: Switch to generic kmap atomic
> Am 10.01.2021 um 12:35 schrieb Paul Cercueil : > > Hi Thomas, > > Le sam. 9 janv. 2021 à 1:33, Thomas Bogendoerfer > a écrit : >> On Sat, Jan 09, 2021 at 12:58:05AM +0100, Thomas Bogendoerfer wrote: >>> On Fri, Jan 08, 2021 at 08:20:43PM +, Paul Cercueil wrote: >>> > Hi Thomas, >>> > >>> > 5.11 does not boot anymore on Ingenic SoCs, I bisected it to this commit. Just for completeness, I have no such problems booting CI20/jz4780 or Skytone400/jz4730 (unpublished work) with 5.11-rc2. But may depend on board capabilites (ram size, memory layout or something else). >>> > >>> > Any idea what could be happening? >>> not yet, kernel crash log of a Malta QEMU is below. >> update: >> This dirty hack lets the Malta QEMU boot again: >> diff --git a/mm/highmem.c b/mm/highmem.c >> index c3a9ea7875ef..190cdda1149d 100644 >> --- a/mm/highmem.c >> +++ b/mm/highmem.c >> @@ -515,7 +515,7 @@ void *__kmap_local_pfn_prot(unsigned long pfn, pgprot_t >> prot) >> vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); >> BUG_ON(!pte_none(*(kmap_pte - idx))); >> pteval = pfn_pte(pfn, prot); >> -set_pte_at(&init_mm, vaddr, kmap_pte - idx, pteval); >> +set_pte(kmap_pte - idx, pteval); >> arch_kmap_local_post_map(vaddr, pteval); >> current->kmap_ctrl.pteval[kmap_local_idx()] = pteval; >> preempt_enable(); >> set_pte_at() tries to update cache and could do an kmap_atomic() there. >> Not sure, if this is allowed at this point. > > Yes, I can confirm that your workaround works here too. > > Cheers, > -Paul > > ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm/hisilicon: Use drm_crtc_mask()
Use drm_crtc_mask() where appropriate.
Signed-off-by: Tian Tao
---
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c
b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c
index c76f996..1c5f2fa 100644
--- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c
+++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c
@@ -96,6 +96,7 @@ int hibmc_vdac_init(struct hibmc_drm_private *priv)
struct drm_device *dev = &priv->dev;
struct hibmc_connector *hibmc_connector = &priv->connector;
struct drm_encoder *encoder = &priv->encoder;
+ struct drm_crtc *crtc = &priv->crtc;
struct drm_connector *connector = &hibmc_connector->base;
int ret;
@@ -105,7 +106,7 @@ int hibmc_vdac_init(struct hibmc_drm_private *priv)
return ret;
}
- encoder->possible_crtcs = 0x1;
+ encoder->possible_crtcs = drm_crtc_mask(crtc);
ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DAC);
if (ret) {
drm_err(dev, "failed to init encoder: %d\n", ret);
--
2.7.4
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[PATCH v3, 04/15] drm/mediatek: add component OVL_2L2
This patch add component OVL_2L2
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 81ed076..a715127 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -383,6 +383,7 @@ struct mtk_ddp_comp_match {
[DDP_COMPONENT_OVL1]= { MTK_DISP_OVL, 1, NULL },
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L,0, NULL },
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L,1, NULL },
+ [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L,2, NULL },
[DDP_COMPONENT_PWM0]= { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1]= { MTK_DISP_PWM, 1, NULL },
[DDP_COMPONENT_PWM2]= { MTK_DISP_PWM, 2, NULL },
--
1.8.1.1.dirty
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Re: [PATCH v8] backlight: lms283gf05: Convert to GPIO descriptors
Hi Linus,
On 10/1/2021 1:09 pm, Linus Walleij wrote:
> This converts the lms283gf05 backlight driver to use GPIO
> descriptors and switches the single PXA Palm Z2 device
> over to defining these.
>
> Since the platform data was only used to convey GPIO
> information we can delete the platform data header.
>
> Notice that we define the proper active low semantics in
> the board file GPIO descriptor table (active low) and
> assert the reset line by bringing it to "1" (asserted).
>
> Cc: Marek Vasut
> Cc: Daniel Mack
> Cc: Haojian Zhuang
> Cc: Robert Jarzmik
> Reviewed-by: Daniel Thompson
Reviewed-by: Daniel Mack
Thanks for working on this! The PXA tree is usually maintained by
Robert, but I haven't heard from him in a while.
Maybe this patch can go through some broader ARM tree like Arnd's (cc'ed)?
Daniel
> Signed-off-by: Linus Walleij
> ---
> ChangeLog v7->v8:
> - Rebase onto v5.11-rc1
> - I wonder why this never seems to get merged...?
> ChangeLog v6->v7:
> - Rebase onto v5.10-rc1
> ChangeLog v5->v6:
> - Rebase onto v5.9-rc1
> ChangeLog v4->v5:
> - Rebase on v5.8-rc1
> - Collected Daniel's Reviewed-by tag.
> ChangeLog v3->v4:
> - Check IS_ERR() on the returned GPIO descriptor.
> - Unconditionally set consumer name since the API tolerates NULL.
> ChangeLog v2->v3:
> - Fix a use-before-allocated bug discovered by compile tests.
> - Remove unused ret variable as autobuilders complained.
> ChangeLog v1->v2:
> - Bring up the GPIO de-asserted in probe()
>
> Marek: I saw this was written by you, are you regularly
> testing the Z2 device?
> ---
> arch/arm/mach-pxa/z2.c | 12 +---
> drivers/video/backlight/lms283gf05.c | 43 +++-
> include/linux/spi/lms283gf05.h | 16 ---
> 3 files changed, 25 insertions(+), 46 deletions(-)
> delete mode 100644 include/linux/spi/lms283gf05.h
>
> diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
> index 21fd76bb09cd..89eb5243c85f 100644
> --- a/arch/arm/mach-pxa/z2.c
> +++ b/arch/arm/mach-pxa/z2.c
> @@ -20,7 +20,6 @@
> #include
> #include
> #include
> -#include
> #include
> #include
> #include
> @@ -578,8 +577,13 @@ static struct pxa2xx_spi_chip lms283_chip_info = {
> .gpio_cs= GPIO88_ZIPITZ2_LCD_CS,
> };
>
> -static const struct lms283gf05_pdata lms283_pdata = {
> - .reset_gpio = GPIO19_ZIPITZ2_LCD_RESET,
> +static struct gpiod_lookup_table lms283_gpio_table = {
> + .dev_id = "spi2.0", /* SPI bus 2 chip select 0 */
> + .table = {
> + GPIO_LOOKUP("gpio-pxa", GPIO19_ZIPITZ2_LCD_RESET,
> + "reset", GPIO_ACTIVE_LOW),
> + { },
> + },
> };
>
> static struct spi_board_info spi_board_info[] __initdata = {
> @@ -595,7 +599,6 @@ static struct spi_board_info spi_board_info[] __initdata
> = {
> {
> .modalias = "lms283gf05",
> .controller_data= &lms283_chip_info,
> - .platform_data = &lms283_pdata,
> .max_speed_hz = 40,
> .bus_num= 2,
> .chip_select= 0,
> @@ -615,6 +618,7 @@ static void __init z2_spi_init(void)
> {
> pxa2xx_set_spi_info(1, &pxa_ssp1_master_info);
> pxa2xx_set_spi_info(2, &pxa_ssp2_master_info);
> + gpiod_add_lookup_table(&lms283_gpio_table);
> spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
> }
> #else
> diff --git a/drivers/video/backlight/lms283gf05.c
> b/drivers/video/backlight/lms283gf05.c
> index 0e45685bcc1c..36856962ed83 100644
> --- a/drivers/video/backlight/lms283gf05.c
> +++ b/drivers/video/backlight/lms283gf05.c
> @@ -9,16 +9,16 @@
> #include
> #include
> #include
> -#include
> +#include
> #include
>
> #include
> -#include
> #include
>
> struct lms283gf05_state {
> struct spi_device *spi;
> struct lcd_device *ld;
> + struct gpio_desc*reset;
> };
>
> struct lms283gf05_seq {
> @@ -90,13 +90,13 @@ static const struct lms283gf05_seq disp_pdwnseq[] = {
> };
>
>
> -static void lms283gf05_reset(unsigned long gpio, bool inverted)
> +static void lms283gf05_reset(struct gpio_desc *gpiod)
> {
> - gpio_set_value(gpio, !inverted);
> + gpiod_set_value(gpiod, 0); /* De-asserted */
> mdelay(100);
> - gpio_set_value(gpio, inverted);
> + gpiod_set_value(gpiod, 1); /* Asserted */
> mdelay(20);
> - gpio_set_value(gpio, !inverted);
> + gpiod_set_value(gpiod, 0); /* De-asserted */
> mdelay(20);
> }
>
> @@ -125,18 +125,15 @@ static int lms283gf05_power_set(struct lcd_device *ld,
> int power)
> {
> struct lms283gf05_state *st = lcd_get_data(ld);
> struct spi_device *spi = st->spi;
> - struct lms283gf05_pdata *pdata = dev_get_platdata(&spi->dev);
>
> if (power <= FB_BLANK_NORMAL) {
> - if (pdata)
> - lms283gf05_reset(pdata->reset_gpio,
> - pdata->res
[PATCH v3, 06/15] drm/mediatek: add component RDMA4
This patch add component RDMA4
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index bc6b10a..fc01fea 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -392,6 +392,7 @@ struct mtk_ddp_comp_match {
[DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL },
[DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL },
[DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
+ [DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, NULL },
[DDP_COMPONENT_UFOE]= { MTK_DISP_UFOE, 0, &ddp_ufoe },
[DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
[DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
--
1.8.1.1.dirty
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[PATCH v3, 05/15] drm/mediatek: add component POSTMASK
This patch add component POSTMASK,
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/Makefile| 1 +
drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 160 +++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
6 files changed, 168 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index 17a08e2..ce5ad59 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -3,6 +3,7 @@
mediatek-drm-y := mtk_disp_color.o \
mtk_disp_gamma.o \
mtk_disp_ovl.o \
+ mtk_disp_postmask.o \
mtk_disp_rdma.o \
mtk_drm_crtc.o \
mtk_drm_ddp.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
new file mode 100644
index 000..736224c
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
@@ -0,0 +1,160 @@
+/*
+ * SPDX-License-Identifier:
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+
+#define DISP_POSTMASK_EN 0x
+#define POSTMASK_ENBIT(0)
+#define DISP_POSTMASK_CFG 0x0020
+#define POSTMASK_RELAY_MODEBIT(0)
+#define DISP_POSTMASK_SIZE 0x0030
+
+struct mtk_disp_postmask_data {
+ u32 reserved;
+};
+
+/**
+ * struct mtk_disp_postmask - DISP_postmask driver structure
+ * @ddp_comp - structure containing type enum and hardware resources
+ * @crtc - associated crtc to report irq events to
+ */
+struct mtk_disp_postmask {
+ struct mtk_ddp_comp ddp_comp;
+ const struct mtk_disp_postmask_data *data;
+};
+
+static inline struct mtk_disp_postmask *comp_to_postmask(struct mtk_ddp_comp
*comp)
+{
+ return container_of(comp, struct mtk_disp_postmask, ddp_comp);
+}
+
+static void mtk_postmask_config(struct mtk_ddp_comp *comp, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_POSTMASK_SIZE);
+ mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, comp, DISP_POSTMASK_CFG);
+}
+
+static void mtk_postmask_start(struct mtk_ddp_comp *comp)
+{
+ writel(POSTMASK_EN, comp->regs + DISP_POSTMASK_EN);
+}
+
+static void mtk_postmask_stop(struct mtk_ddp_comp *comp)
+{
+ writel_relaxed(0x0, comp->regs + DISP_POSTMASK_EN);
+}
+
+static const struct mtk_ddp_comp_funcs mtk_disp_postmask_funcs = {
+ .config = mtk_postmask_config,
+ .start = mtk_postmask_start,
+ .stop = mtk_postmask_stop,
+};
+
+static int mtk_disp_postmask_bind(struct device *dev, struct device *master,
void *data)
+{
+ struct mtk_disp_postmask *priv = dev_get_drvdata(dev);
+ struct drm_device *drm_dev = data;
+ int ret;
+
+ ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp);
+ if (ret < 0) {
+ dev_err(dev, "Failed to register component %pOF: %d\n",
+ dev->of_node, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void mtk_disp_postmask_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_disp_postmask *priv = dev_get_drvdata(dev);
+ struct drm_device *drm_dev = data;
+
+ mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp);
+}
+
+static const struct component_ops mtk_disp_postmask_component_ops = {
+ .bind = mtk_disp_postmask_bind,
+ .unbind = mtk_disp_postmask_unbind,
+};
+
+static int mtk_disp_postmask_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_disp_postmask *priv;
+ int comp_id;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_POSTMASK);
+ if (comp_id < 0) {
+ dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
+ return comp_id;
+ }
+
+ ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
+ &mtk_disp_postmask_funcs);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Failed to initialize component: %d\n",
+ ret);
+
+ return ret;
+ }
+
+ priv->data = of_devic
[PATCH v3, 08/15] drm/mediatek: check if fb is null
It's possible that state->base.fb is null. Add a check before access its
format.
Fixes: b6b1bb980ec4 ( drm/mediatek: Turn off Alpha bit when plane format has no
alpha)
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 4934bee..8e7f494 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -279,7 +279,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp,
unsigned int idx,
}
con = ovl_fmt_convert(ovl, fmt);
- if (state->base.fb->format->has_alpha)
+ if (state->base.fb && state->base.fb->format->has_alpha)
con |= OVL_CON_AEN | OVL_CON_ALPHA;
if (pending->rotation & DRM_MODE_REFLECT_Y) {
--
1.8.1.1.dirty
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[PATCH v3, 09/15] drm/mediatek: Add pm runtime support for gamma
gamma power domain need controled in the device.
Signed-off-by: Yongqiang Niu
Signed-off-by: Yidi Lin
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
index 3c1ea07..da93079 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
#include "mtk_drm_crtc.h"
@@ -156,6 +157,8 @@ static int mtk_disp_gamma_probe(struct platform_device
*pdev)
platform_set_drvdata(pdev, priv);
+ pm_runtime_enable(dev);
+
ret = component_add(dev, &mtk_disp_gamma_component_ops);
if (ret)
dev_err(dev, "Failed to add component: %d\n", ret);
@@ -165,6 +168,8 @@ static int mtk_disp_gamma_probe(struct platform_device
*pdev)
static int mtk_disp_gamma_remove(struct platform_device *pdev)
{
+ pm_runtime_disable(&pdev->dev);
+
component_del(&pdev->dev, &mtk_disp_gamma_component_ops);
return 0;
--
1.8.1.1.dirty
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[PATCH v3, 01/15] dt-bindings: mediatek: add description for postmask
add description for postmask postmask is used control round corner for display frame Signed-off-by: Yongqiang Niu --- Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index c562cda..9d9ab65 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -37,6 +37,7 @@ Required properties (all function blocks): "mediatek,-disp-aal" - adaptive ambient light controller "mediatek,-disp-gamma"- gamma correction "mediatek,-disp-merge"- merge streams from two RDMA sources + "mediatek,-disp-postmask" - control round corner for display frame "mediatek,-disp-split"- split stream to two encoders "mediatek,-disp-ufoe" - data compression engine "mediatek,-dsi" - DSI controller, see mediatek,dsi.txt -- 1.8.1.1.dirty ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3, 13/15] drm/mediatek: add matrix bits private data for ccorr
matrix bits of mt8183 is 12
matrix bits of mt8192 is 13
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 23 ---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
index 63b3ef6..755e75b 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
@@ -30,8 +30,10 @@
#define DISP_CCORR_COEF_3 0x008C
#define DISP_CCORR_COEF_4 0x0090
+#define CCORR_MATRIX_BITS 12
+
struct mtk_disp_ccorr_data {
- u32 reserved;
+ u32 matrix_bits;
};
/**
@@ -96,6 +98,8 @@ static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
uint16_t coeffs[9] = { 0 };
int i;
struct cmdq_pkt *cmdq_pkt = NULL;
+ struct mtk_disp_ccorr *ccorr = comp_to_ccorr(comp);
+ u32 matrix_bits;
if (!blob)
return;
@@ -103,8 +107,16 @@ static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
ctm = (struct drm_color_ctm *)blob->data;
input = ctm->matrix;
- for (i = 0; i < ARRAY_SIZE(coeffs); i++)
+ if (ccorr->data)
+ matrix_bits = ccorr->data->matrix_bits;
+ else
+ matrix_bits = CCORR_MATRIX_BITS;
+
+ for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
+ if (matrix_bits > CCORR_MATRIX_BITS)
+ coeffs[i] <<= (matrix_bits - CCORR_MATRIX_BITS);
+ }
mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
comp, DISP_CCORR_COEF_0);
@@ -205,8 +217,13 @@ static int mtk_disp_ccorr_remove(struct platform_device
*pdev)
return 0;
}
+static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = {
+ .matrix_bits = CCORR_MATRIX_BITS,
+};
+
static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
- { .compatible = "mediatek,mt8183-disp-ccorr"},
+ { .compatible = "mediatek,mt8183-disp-ccorr",
+ .data = &mt8183_ccorr_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
--
1.8.1.1.dirty
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[PATCH v3, 11/15] drm/mediatek: fix aal size config
the orginal setting is not correct, fix it follow hardware data sheet.
if keep this error setting, mt8173/mt8183 display ok
but mt8192 display abnormal.
Fixes: 0664d1392c26 (drm/mediatek: Add AAL engine basic function)
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index fc01fea..6081800 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -174,7 +174,7 @@ static void mtk_aal_config(struct mtk_ddp_comp *comp,
unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
- mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_AAL_SIZE);
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_SIZE);
}
static void mtk_aal_start(struct mtk_ddp_comp *comp)
--
1.8.1.1.dirty
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[PATCH v3, 07/15] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index b47c238..4934bee 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -23,6 +23,7 @@
#define DISP_REG_OVL_RST 0x0014
#define DISP_REG_OVL_ROI_SIZE 0x0020
#define DISP_REG_OVL_DATAPATH_CON 0x0024
+#define OVL_LAYER_SMI_ID_ENBIT(0)
#define OVL_BGCLR_SEL_IN BIT(2)
#define DISP_REG_OVL_ROI_BGCLR 0x0028
#define DISP_REG_OVL_SRC_CON 0x002c
@@ -61,6 +62,7 @@ struct mtk_disp_ovl_data {
unsigned int gmc_bits;
unsigned int layer_nr;
bool fmt_rgb565_is_0;
+ bool smi_id_en;
};
/**
@@ -116,7 +118,17 @@ static void mtk_ovl_disable_vblank(struct mtk_ddp_comp
*comp)
static void mtk_ovl_start(struct mtk_ddp_comp *comp)
{
+ struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
+
writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN);
+
+ if(ovl->data->smi_id_en) {
+ unsigned int reg;
+
+ reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
+ reg = reg | OVL_LAYER_SMI_ID_EN;
+ writel_relaxed(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
+ }
}
static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
--
1.8.1.1.dirty
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Re: [PATCH v1] drm/panel: simple: add SGD GKTW70SDAD1SD
On 10/01/21, Fabio Estevam wrote: > Hi Oliver, > > On Sun, Jan 10, 2021 at 12:35 PM Oliver Graute > wrote: > > > the first two errors are gone. But I still get this: > > > > [ 42.387107] mxsfb 21c8000.lcdif: Cannot connect bridge: -517 > > > > The panel is still off perhaps I miss something else. > > Some suggestions: > > - Take a look at arch/arm/boot/dts/imx6ul-14x14-evk.dtsi as a > reference as it has display functional > - Use imx_v6_v7_defconfig to make sure all the required drivers are selected ok I checked imx6ul-14x14-evk.dtsi and use imx_v6_v7_defconfig > - If it still does not work, share the dts and schematics here the schematics and my dts. The board is using a LVDS connector for the display. https://www.variscite.de/wp-content/uploads/2017/12/VAR-6ULCustomboard-Schematics.pdf https://lore.kernel.org/linux-arm-kernel/1610144511-19018-3-git-send-email-oliver.gra...@gmail.com/ Thx for your help, Best Regards, Oliver ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [Freedreno] [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx
Hi Rob, On 2021-01-08 22:16, Rob Clark wrote: On Fri, Jan 8, 2021 at 6:05 AM Sai Prakash Ranjan wrote: On 2021-01-08 19:09, Konrad Dybcio wrote: >> Konrad, can you please test this below change without your change? > > This brings no difference, a BUG still happens. We're still calling > to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330 > into an A640.. > > Also, relying on disabling LLCC in the config is out of question as it > makes the arm32 kernel not compile with DRM/MSM and it just removes > the functionality on devices with a6xx.. (unless somebody removes the > dependency on it, which in my opinion is even worse and will cause > more problems for developers!). > Disabling LLCC is not the suggestion, I was under the impression that was the cause here for the smmu bug. Anyways, the check for llc slice in case llcc is disabled is not correct as well. I will send a patch for that as well. > The bigger question is how and why did that piece of code ever make it > to adreno_gpu.c and not a6xx_gpu.c? > My mistake, I will move it. Thanks, since we don't have kernel-CI coverage for gpu, and there probably isn't one person who has all the different devices supported (or enough hours in the day to test them all), it is probably better/safer to keep things in the backend code that is specific to a given generation. Agreed, I will post this change soon and will introduce some feature check as well because we will need it for iommu prot flag as per discussion here - https://lore.kernel.org/lkml/20210108181830.GA5457@willie-the-truck/ > To solve it in a cleaner way I propose to move it to an a6xx-specific > file, or if it's going to be used with next-gen GPUs, perhaps manage > calling of this code via an adreno quirk/feature in adreno_device.c. > Now that I think about it, A5xx GPMU en/disable could probably managed > like that, instead of using tons of if-statements for each GPU model > that has it.. > > While we're at it, do ALL (and I truly do mean ALL, including the > low-end ones, this will be important later on) A6xx GPUs make use of > that feature? > I do not have a list of all A6XX GPUs with me currently, but from what I know, A618, A630, A640, A650 has the support. From the PoV of bringing up new a6xx, we should probably consider that some of them may not *yet* have LLCC enabled. I have an 8cx laptop and once I find time to get the display working, the next step would be bringing up a680.. and I'd probably like to start without LLCC.. Right, once I move the LLCC code to a6xx specific address space creation, without LLCC slices for GPU specified in qcom llcc driver, we will not be using it. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3, 14/15] drm/mediatek: add DDP support for MT8192
Add DDP support for MT8192 SoC.
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 35 ++
1 file changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 1308046..7aa7fc3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -40,6 +40,18 @@
#define MT8167_MUTEX_MOD_DISP_DITHER 15
#define MT8167_MUTEX_MOD_DISP_UFOE 16
+#define MT8192_MUTEX_MOD_DISP_OVL0 0
+#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1
+#define MT8192_MUTEX_MOD_DISP_RDMA02
+#define MT8192_MUTEX_MOD_DISP_COLOR0 4
+#define MT8192_MUTEX_MOD_DISP_CCORR0 5
+#define MT8192_MUTEX_MOD_DISP_AAL0 6
+#define MT8192_MUTEX_MOD_DISP_GAMMA0 7
+#define MT8192_MUTEX_MOD_DISP_POSTMASK08
+#define MT8192_MUTEX_MOD_DISP_DITHER0 9
+#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16
+#define MT8192_MUTEX_MOD_DISP_RDMA417
+
#define MT8183_MUTEX_MOD_DISP_RDMA00
#define MT8183_MUTEX_MOD_DISP_RDMA11
#define MT8183_MUTEX_MOD_DISP_OVL0 9
@@ -215,6 +227,20 @@ struct mtk_ddp {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
+static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
+ [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
+ [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
+ [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
+ [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L,
+ [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L,
+ [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
+};
+
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
[DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
@@ -275,6 +301,13 @@ struct mtk_ddp {
.no_clk = true,
};
+static const struct mtk_ddp_data mt8192_ddp_driver_data = {
+ .mutex_mod = mt8192_mutex_mod,
+ .mutex_sof = mt8183_mutex_sof,
+ .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0,
+};
+
struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id)
{
struct mtk_ddp *ddp = dev_get_drvdata(dev);
@@ -497,6 +530,8 @@ static int mtk_ddp_remove(struct platform_device *pdev)
.data = &mt8173_ddp_driver_data},
{ .compatible = "mediatek,mt8183-disp-mutex",
.data = &mt8183_ddp_driver_data},
+ { .compatible = "mediatek,mt8192-disp-mutex",
+ .data = &mt8192_ddp_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, ddp_driver_dt_match);
--
1.8.1.1.dirty
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[PATCH v3, 02/15] dt-bindings: mediatek: add description for mt8192 display
add description for mt8192 display Signed-off-by: Yongqiang Niu Reviewed-by: Chun-Kuang Hu Acked-by: Rob Herring --- Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index 9d9ab65..b47e1a0 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -44,7 +44,7 @@ Required properties (all function blocks): "mediatek,-dpi" - DPI controller, see mediatek,dpi.txt "mediatek,-disp-mutex"- display mutex "mediatek,-disp-od" - overdrive - the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173 and mt8183. + the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192. - reg: Physical base address and length of the function block register space - interrupts: The interrupt signal from the function block (required, except for merge and split function blocks). -- 1.8.1.1.dirty ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3, 10/15] drm/mediatek: Add pm runtime support for color
color power domain need controled in the device.
Signed-off-by: Yongqiang Niu
Signed-off-by: Yidi Lin
---
drivers/gpu/drm/mediatek/mtk_disp_color.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c
b/drivers/gpu/drm/mediatek/mtk_disp_color.c
index 6048cbc..14b9dd3 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_color.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include "mtk_drm_crtc.h"
@@ -132,6 +133,8 @@ static int mtk_disp_color_probe(struct platform_device
*pdev)
platform_set_drvdata(pdev, priv);
+ pm_runtime_enable(dev);
+
ret = component_add(dev, &mtk_disp_color_component_ops);
if (ret)
dev_err(dev, "Failed to add component: %d\n", ret);
@@ -141,6 +144,8 @@ static int mtk_disp_color_probe(struct platform_device
*pdev)
static int mtk_disp_color_remove(struct platform_device *pdev)
{
+ pm_runtime_disable(&pdev->dev);
+
component_del(&pdev->dev, &mtk_disp_color_component_ops);
return 0;
--
1.8.1.1.dirty
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[PATCH 0/3] drm/sun4i: de2/de3: CSC improvements
This short series reworks CSC handling to remove duplicated constants (patch 1 and 2) and adds BT2020 encoding to DE3 (patch 3). Please take a look. Best regards, Jernej Jernej Skrabec (3): drm/sun4i: csc: Rework DE3 CSC macros drm/sun4i: de2/de3: Remove redundant CSC matrices drm/sun4i: Add support for BT2020 to DE3 drivers/gpu/drm/sun4i/sun8i_csc.c | 109 ++--- drivers/gpu/drm/sun4i/sun8i_mixer.h| 6 +- drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 2 + 3 files changed, 48 insertions(+), 69 deletions(-) -- 2.30.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 3/3] drm/sun4i: Add support for BT2020 to DE3
DE3 supports 10-bit formats, so it's only naturally to also support
BT2020 encoding.
Add support for it.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/sun8i_csc.c | 12 +++-
drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 2 ++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c
b/drivers/gpu/drm/sun4i/sun8i_csc.c
index 1d10714e417e..9bd62de0c288 100644
--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
+++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
@@ -69,7 +69,7 @@ static const u32 yuv2rgb[2][2][12] = {
* c20 c21 c22 [d2 const2]
*/
-static const u32 yuv2rgb_de3[2][2][12] = {
+static const u32 yuv2rgb_de3[2][3][12] = {
[DRM_COLOR_YCBCR_LIMITED_RANGE] = {
[DRM_COLOR_YCBCR_BT601] = {
0x0002542A, 0x, 0x0003312A, 0xFFC0,
@@ -80,6 +80,11 @@ static const u32 yuv2rgb_de3[2][2][12] = {
0x0002542A, 0x, 0x000395E2, 0xFFC0,
0x0002542A, 0x92D2, 0xFFFEEF27, 0xFE00,
0x0002542A, 0x0004398C, 0x, 0xFE00,
+ },
+ [DRM_COLOR_YCBCR_BT2020] = {
+ 0x0002542A, 0x, 0x00035B7B, 0xFFC0,
+ 0x0002542A, 0xA017, 0xFFFEB2FC, 0xFE00,
+ 0x0002542A, 0x00044896, 0x, 0xFE00,
}
},
[DRM_COLOR_YCBCR_FULL_RANGE] = {
@@ -92,6 +97,11 @@ static const u32 yuv2rgb_de3[2][2][12] = {
0x0002, 0x, 0x0003264C, 0x,
0x0002, 0xA018, 0x1053, 0xFE00,
0x0002, 0x0003B611, 0x, 0xFE00,
+ },
+ [DRM_COLOR_YCBCR_BT2020] = {
+ 0x0002, 0x, 0x0002F2FE, 0x,
+ 0x0002, 0xABC0, 0xFFFEDB78, 0xFE00,
+ 0x0002, 0x0003C346, 0x, 0xFE00,
}
},
};
diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
index 76393fc976fe..8cc294a9969d 100644
--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
@@ -543,6 +543,8 @@ struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct
drm_device *drm,
supported_encodings = BIT(DRM_COLOR_YCBCR_BT601) |
BIT(DRM_COLOR_YCBCR_BT709);
+ if (mixer->cfg->is_de3)
+ supported_encodings |= BIT(DRM_COLOR_YCBCR_BT2020);
supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
BIT(DRM_COLOR_YCBCR_FULL_RANGE);
--
2.30.0
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[PATCH v9 00/19] HDCP 2.2 and HDCP 1.4 Gen12 DP MST support
This v9 version has fixed crome-os NULL pointer dereference by just reordering connector status condition. It has been tested manually with below IGT series on TGL and ICL. https://patchwork.freedesktop.org/series/82987/ [PATCH v9 12/19] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len has an Ack from Tomas to merge it via drm-intel. [PATCH v9 13/19] drm/hdcp: Max MST content streams has an Ack from drm-misc maintainer to merge it via drm-intel. Test-with: 20201126050320.2434-2-karthik@intel.com Anshuman Gupta (19): drm/i915/hdcp: Update CP property in update_pipe drm/i915/hdcp: Get conn while content_type changed drm/i915/hotplug: Handle CP_IRQ for DP-MST drm/i915/hdcp: No HDCP when encoder is't initialized drm/i915/hdcp: DP MST transcoder for link and stream drm/i915/hdcp: Move HDCP enc status timeout to header drm/i915/hdcp: HDCP stream encryption support drm/i915/hdcp: Configure HDCP1.4 MST steram encryption status drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support drm/i915/hdcp: Pass dig_port to intel_hdcp_init drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len drm/hdcp: Max MST content streams drm/i915/hdcp: MST streams support in hdcp port_data drm/i915/hdcp: Pass connector to check_2_2_link drm/i915/hdcp: Add HDCP 2.2 stream register drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks drm/i915/hdcp: Configure HDCP2.2 MST steram encryption status drm/i915/hdcp: Enable HDCP 2.2 MST support drivers/gpu/drm/i915/display/intel_ddi.c | 14 +- drivers/gpu/drm/i915/display/intel_ddi.h | 6 +- .../drm/i915/display/intel_display_types.h| 20 +- drivers/gpu/drm/i915/display/intel_dp.c | 14 +- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 186 +-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 9 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 303 ++ drivers/gpu/drm/i915/display/intel_hdcp.h | 8 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 19 +- drivers/gpu/drm/i915/i915_reg.h | 40 +++ drivers/misc/mei/hdcp/mei_hdcp.c | 3 +- include/drm/drm_hdcp.h| 8 +- 12 files changed, 510 insertions(+), 120 deletions(-) -- 2.26.2 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v9 01/19] drm/i915/hdcp: Update CP property in update_pipe
When crtc state need_modeset is true it is not necessary
it is going to be a real modeset, it can turns to be a
fastset instead of modeset.
This turns content protection property to be DESIRED and hdcp
update_pipe left with property to be in DESIRED state but
actual hdcp->value was ENABLED.
This issue is caught with DP MST setup, where we have multiple
connector in same DP_MST topology. When disabling HDCP on one of
DP MST connector leads to set the crtc state need_modeset to true
for all other crtc driving the other DP-MST topology connectors.
This turns up other DP MST connectors CP property to be DESIRED
despite the actual hdcp->value is ENABLED.
Above scenario fails the DP MST HDCP IGT test, disabling HDCP on
one MST stream should not cause to disable HDCP on another MST
stream on same DP MST topology.
v2:
- Fixed connector->base.registration_state == DRM_CONNECTOR_REGISTERED
WARN_ON.
v3:
- Commit log improvement. [Uma]
- Added a comment before scheduling prop_work. [Uma]
Fixes: 33f9a623bfc6 ("drm/i915/hdcp: Update CP as per the kernel internal
state")
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b2a4bbcfdcd2..eee8263405b9 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2221,6 +2221,14 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
*state,
desired_and_not_enabled =
hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED;
mutex_unlock(&hdcp->mutex);
+ /*
+* If HDCP already ENABLED and CP property is DESIRED, schedule
+* prop_work to update correct CP property to user space.
+*/
+ if (!desired_and_not_enabled &&
!content_protection_type_changed) {
+ drm_connector_get(&connector->base);
+ schedule_work(&hdcp->prop_work);
+ }
}
if (desired_and_not_enabled || content_protection_type_changed)
--
2.26.2
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[PATCH v9 02/19] drm/i915/hdcp: Get conn while content_type changed
Get DRM connector reference count while scheduling a prop work
to avoid any possible destroy of DRM connector when it is in
DRM_CONNECTOR_REGISTERED state.
Fixes: a6597faa2d59 ("drm/i915: Protect workers against disappearing
connectors")
Cc: Sean Paul
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index eee8263405b9..b9d8825e2bb1 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2210,6 +2210,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
*state,
if (content_protection_type_changed) {
mutex_lock(&hdcp->mutex);
hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+ drm_connector_get(&connector->base);
schedule_work(&hdcp->prop_work);
mutex_unlock(&hdcp->mutex);
}
--
2.26.2
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[PATCH v9 03/19] drm/i915/hotplug: Handle CP_IRQ for DP-MST
Handle CP_IRQ in DEVICE_SERVICE_IRQ_VECTOR_ESI0
It requires to call intel_hdcp_handle_cp_irq() in case
of CP_IRQ is triggered by a sink in DP-MST topology.
Cc: "Ville Syrjälä"
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index b2bc0c8c39c7..501b9a8a2f45 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5783,6 +5783,17 @@ static void intel_dp_handle_test_request(struct intel_dp
*intel_dp)
"Could not write test response to sink\n");
}
+static void
+intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled)
+{
+ drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled);
+
+ if (esi[1] & DP_CP_IRQ) {
+ intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
+ *handled = true;
+ }
+}
+
/**
* intel_dp_check_mst_status - service any pending MST interrupts, check link
status
* @intel_dp: Intel DP struct
@@ -5827,7 +5838,8 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
- drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
+ intel_dp_mst_hpd_irq(intel_dp, esi, &handled);
+
if (!handled)
break;
--
2.26.2
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[PATCH v9 04/19] drm/i915/hdcp: No HDCP when encoder is't initialized
There can be situation when DP MST connector is created without
mst modeset being done, in those cases connector->encoder will be
NULL. MST connector->encoder initializes after modeset.
Don't enable HDCP in such cases to prevent any crash.
Cc: Ramalingam C
Cc: Juston Li
Tested-by: Karthik B S
Reviewed-by: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b9d8825e2bb1..7d63e9495956 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2106,6 +2106,12 @@ int intel_hdcp_enable(struct intel_connector *connector,
if (!hdcp->shim)
return -ENOENT;
+ if (!connector->encoder) {
+ drm_err(&dev_priv->drm, "[%s:%d] encoder is not initialized\n",
+ connector->base.name, connector->base.base.id);
+ return -ENODEV;
+ }
+
mutex_lock(&hdcp->mutex);
mutex_lock(&dig_port->hdcp_mutex);
drm_WARN_ON(&dev_priv->drm,
--
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[PATCH v9 05/19] drm/i915/hdcp: DP MST transcoder for link and stream
Gen12 has H/W delta with respect to HDCP{1.x,2.x} display engine
instances lies in Transcoder instead of DDI as in Gen11.
This requires hdcp driver to use mst_master_transcoder for link
authentication and stream transcoder for stream encryption
separately.
This will be used for both HDCP 1.4 and HDCP 2.2 over DP MST
on Gen12.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
.../gpu/drm/i915/display/intel_display_types.h| 2 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 15 +++
drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +-
5 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6863236df1d0..14c2c0a15464 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4252,7 +4252,7 @@ static void intel_enable_ddi(struct intel_atomic_state
*state,
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
intel_hdcp_enable(to_intel_connector(conn_state->connector),
- crtc_state->cpu_transcoder,
+ crtc_state,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5bc5bfbc4551..729a9792051f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -436,6 +436,8 @@ struct intel_hdcp {
* Hence caching the transcoder here.
*/
enum transcoder cpu_transcoder;
+ /* Only used for DP MST stream encryption */
+ enum transcoder stream_transcoder;
};
struct intel_connector {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 27f04aed8764..47beb442094f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -569,7 +569,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state
*state,
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
intel_hdcp_enable(to_intel_connector(conn_state->connector),
- pipe_config->cpu_transcoder,
+ pipe_config,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 7d63e9495956..293f72d1d215 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2095,7 +2095,7 @@ int intel_hdcp_init(struct intel_connector *connector,
}
int intel_hdcp_enable(struct intel_connector *connector,
- enum transcoder cpu_transcoder, u8 content_type)
+ const struct intel_crtc_state *pipe_config, u8
content_type)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
@@ -2117,10 +2117,17 @@ int intel_hdcp_enable(struct intel_connector *connector,
drm_WARN_ON(&dev_priv->drm,
hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
hdcp->content_type = content_type;
- hdcp->cpu_transcoder = cpu_transcoder;
+
+ if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) {
+ hdcp->cpu_transcoder = pipe_config->mst_master_transcoder;
+ hdcp->stream_transcoder = pipe_config->cpu_transcoder;
+ } else {
+ hdcp->cpu_transcoder = pipe_config->cpu_transcoder;
+ hdcp->stream_transcoder = INVALID_TRANSCODER;
+ }
if (INTEL_GEN(dev_priv) >= 12)
- hdcp->port_data.fw_tc = intel_get_mei_fw_tc(cpu_transcoder);
+ hdcp->port_data.fw_tc =
intel_get_mei_fw_tc(hdcp->cpu_transcoder);
/*
* Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
@@ -2240,7 +2247,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
*state,
if (desired_and_not_enabled || content_protection_type_changed)
intel_hdcp_enable(connector,
- crtc_state->cpu_transcoder,
+ crtc_state,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h
b/drivers/gpu/drm/i915/display/intel_hdcp.h
index 1bbf5b67ed0a..bc51c1e9b481 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -25,7 +25,7 @@
[PATCH v9 06/19] drm/i915/hdcp: Move HDCP enc status timeout to header
DP MST stream encryption status requires time of a link frame
in order to change its status, but as there were some HDCP
encryption timeout observed earlier, it is safer to use
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS timeout for stream status too,
it requires to move the macro to a header.
It will be used by both HDCP{1.x,2.x} stream status timeout.
Related: 'commit 7e90e8d0c0ea ("drm/i915: Increase timeout for Encrypt
status change")'
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 9 -
drivers/gpu/drm/i915/display/intel_hdcp.h | 2 ++
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 293f72d1d215..6e6465b4ecfa 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -23,7 +23,6 @@
#include "intel_connector.h"
#define KEY_LOAD_TRIES 5
-#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
#define HDCP2_LC_RETRY_CNT 3
static
@@ -762,7 +761,7 @@ static int intel_hdcp_auth(struct intel_connector
*connector)
if (intel_de_wait_for_set(dev_priv,
HDCP_STATUS(dev_priv, cpu_transcoder, port),
HDCP_STATUS_ENC,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
drm_err(&dev_priv->drm, "Timed out waiting for encryption\n");
return -ETIMEDOUT;
}
@@ -809,7 +808,7 @@ static int _intel_hdcp_disable(struct intel_connector
*connector)
intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
if (intel_de_wait_for_clear(dev_priv,
HDCP_STATUS(dev_priv, cpu_transcoder, port),
- ~0, ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS))
{
drm_err(&dev_priv->drm,
"Failed to disable HDCP, timeout clearing status\n");
return -ETIMEDOUT;
@@ -1641,7 +1640,7 @@ static int hdcp2_enable_encryption(struct intel_connector
*connector)
HDCP2_STATUS(dev_priv, cpu_transcoder,
port),
LINK_ENCRYPTION_STATUS,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
return ret;
}
@@ -1665,7 +1664,7 @@ static int hdcp2_disable_encryption(struct
intel_connector *connector)
HDCP2_STATUS(dev_priv, cpu_transcoder,
port),
LINK_ENCRYPTION_STATUS,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
if (ret == -ETIMEDOUT)
drm_dbg_kms(&dev_priv->drm, "Disable Encryption Timedout");
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h
b/drivers/gpu/drm/i915/display/intel_hdcp.h
index bc51c1e9b481..b912a3a0f5b8 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -8,6 +8,8 @@
#include
+#define HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
+
struct drm_connector;
struct drm_connector_state;
struct drm_i915_private;
--
2.26.2
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[PATCH v9 07/19] drm/i915/hdcp: HDCP stream encryption support
Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
encryption over DP MST Transport Link.
HDCP 1.4 stream encryption requires to validate the stream encryption
status in HDCP_STATUS_{TRANSCODER,PORT} register driving that link
in order to enable/disable the stream encryption.
Both of above requirement are same for all Gen with respect to
B.Spec Documentation.
v2:
- Cosmetic changes function name, error msg print and
stream typo fixes. [Uma]
v3:
- uniformity for connector detail in DMESG. [Ram]
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--
drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
.../drm/i915/display/intel_display_types.h| 4 +
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 90 ---
drivers/gpu/drm/i915/display/intel_hdmi.c | 14 +--
drivers/gpu/drm/i915/i915_reg.h | 1 +
6 files changed, 97 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 14c2c0a15464..046c49931b98 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2029,9 +2029,9 @@ void intel_ddi_disable_transcoder_func(const struct
intel_crtc_state *crtc_state
}
}
-int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
-enum transcoder cpu_transcoder,
-bool enable)
+int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
+ enum transcoder cpu_transcoder,
+ bool enable, u32 hdcp_mask)
{
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -2046,9 +2046,9 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder
*intel_encoder,
tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (enable)
- tmp |= TRANS_DDI_HDCP_SIGNALLING;
+ tmp |= hdcp_mask;
else
- tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
+ tmp &= ~hdcp_mask;
intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
b/drivers/gpu/drm/i915/display/intel_ddi.h
index dcc711cfe4fe..a4dd815c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -50,9 +50,9 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
u32 ddi_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
-int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
-enum transcoder cpu_transcoder,
-bool enable);
+int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
+ enum transcoder cpu_transcoder,
+ bool enable, u32 hdcp_mask);
void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
#endif /* __INTEL_DDI_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 729a9792051f..f0aeba9a222a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -343,6 +343,10 @@ struct intel_hdcp_shim {
enum transcoder cpu_transcoder,
bool enable);
+ /* Enable/Disable stream encryption on DP MST Transport Link */
+ int (*stream_encryption)(struct intel_connector *connector,
+bool enable);
+
/* Ensures the link is still protected */
bool (*check_link)(struct intel_digital_port *dig_port,
struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 03424d20e9f7..94c5462fa037 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -16,6 +16,30 @@
#include "intel_dp.h"
#include "intel_hdcp.h"
+static unsigned int transcoder_to_stream_enc_status(enum transcoder
cpu_transcoder)
+{
+ u32 stream_enc_mask;
+
+ switch (cpu_transcoder) {
+ case TRANSCODER_A:
+ stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
+ break;
+ case TRANSCODER_B:
+ stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
+ break;
+ case TRAN
[PATCH v9 08/19] drm/i915/hdcp: Configure HDCP1.4 MST steram encryption status
Enable HDCP 1.4 DP MST stream encryption.
Enable stream encryption once encryption is enabled on
the DP transport driving the link for each stream which
has requested encryption.
Disable stream encryption for each stream that no longer
requires encryption before disabling HDCP encryption on
the link.
v2:
- Added debug print for stream encryption.
- Disable the hdcp on port after disabling last stream
encryption.
v3:
- Cosmetic change, removed the value less comment. [Uma]
v4:
- Split the Gen12 HDCP enablement patch. [Ram]
- Add connector details in drm_err.
v5:
- uniformity for connector detail in DMESG. [Ram]
- comments improvement. [Ram]
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 38 +++
1 file changed, 25 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 6e6465b4ecfa..fce444d69521 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -766,10 +766,17 @@ static int intel_hdcp_auth(struct intel_connector
*connector)
return -ETIMEDOUT;
}
- /*
-* XXX: If we have MST-connected devices, we need to enable encryption
-* on those as well.
-*/
+ /* DP MST Auth Part 1 Step 2.a and Step 2.b */
+ if (shim->stream_encryption) {
+ ret = shim->stream_encryption(connector, true);
+ if (ret) {
+ drm_err(&dev_priv->drm, "[%s:%d] Failed to enable HDCP
1.4 stream enc\n",
+ connector->base.name, connector->base.base.id);
+ return ret;
+ }
+ drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 transcoder: %s stream
encrypted\n",
+ transcoder_name(hdcp->stream_transcoder));
+ }
if (repeater_present)
return intel_hdcp_auth_downstream(connector);
@@ -791,18 +798,23 @@ static int _intel_hdcp_disable(struct intel_connector
*connector)
drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n",
connector->base.name, connector->base.base.id);
+ if (hdcp->shim->stream_encryption) {
+ ret = hdcp->shim->stream_encryption(connector, false);
+ if (ret) {
+ drm_err(&dev_priv->drm, "[%s:%d] Failed to disable HDCP
1.4 stream enc\n",
+ connector->base.name, connector->base.base.id);
+ return ret;
+ }
+ drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 transcoder: %s stream
encryption disabled\n",
+ transcoder_name(hdcp->stream_transcoder));
+ }
+
/*
-* If there are other connectors on this port using HDCP, don't disable
-* it. Instead, toggle the HDCP signalling off on that particular
-* connector/pipe and exit.
+* If there are other connectors on this port using HDCP, don't disable
it
+* until it disabled HDCP encryption for all connectors in MST topology.
*/
- if (dig_port->num_hdcp_streams > 0) {
- ret = hdcp->shim->toggle_signalling(dig_port,
- cpu_transcoder, false);
- if (ret)
- DRM_ERROR("Failed to disable HDCP signalling\n");
+ if (dig_port->num_hdcp_streams > 0)
return ret;
- }
hdcp->hdcp_encrypted = false;
intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
--
2.26.2
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[PATCH v9 09/19] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
Enable HDCP 1.4 over DP MST for Gen12.
v2:
- Enable HDCP for <= Gen12 platforms. [Ram]
v3:
- Connector detials in debug msg. [Ram]
Cc: Ramalingam C
Reviewed-by: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 47beb442094f..f76e2c2a83b8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -829,12 +829,11 @@ static struct drm_connector
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
-
- /* TODO: Figure out how to make HDCP work on GEN12+ */
- if (INTEL_GEN(dev_priv) < 12) {
+ if (INTEL_GEN(dev_priv) <= 12) {
ret = intel_dp_init_hdcp(dig_port, intel_connector);
if (ret)
- DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
+ drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init
failed, skipping.\n",
+ connector->name, connector->base.id);
}
/*
--
2.26.2
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[PATCH v9 10/19] drm/i915/hdcp: Pass dig_port to intel_hdcp_init
Pass dig_port as an argument to intel_hdcp_init()
and intel_hdcp2_init().
This will be required for HDCP 2.2 stream encryption.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_hdcp.c| 12 +++-
drivers/gpu/drm/i915/display/intel_hdcp.h| 4 +++-
drivers/gpu/drm/i915/display/intel_hdmi.c| 2 +-
4 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 94c5462fa037..3f23f8b53dcd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -755,10 +755,10 @@ int intel_dp_init_hdcp(struct intel_digital_port
*dig_port,
return 0;
if (intel_connector->mst_port)
- return intel_hdcp_init(intel_connector, port,
+ return intel_hdcp_init(intel_connector, dig_port,
&intel_dp_mst_hdcp_shim);
else if (!intel_dp_is_edp(intel_dp))
- return intel_hdcp_init(intel_connector, port,
+ return intel_hdcp_init(intel_connector, dig_port,
&intel_dp_hdcp_shim);
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index fce444d69521..4ad086e7ec3c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1979,12 +1979,13 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum
transcoder cpu_transcoder)
}
static int initialize_hdcp_port_data(struct intel_connector *connector,
-enum port port,
+struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
struct hdcp_port_data *data = &hdcp->port_data;
+ enum port port = dig_port->base.port;
if (INTEL_GEN(dev_priv) < 12)
data->fw_ddi = intel_get_mei_fw_ddi_index(port);
@@ -2057,14 +2058,15 @@ void intel_hdcp_component_init(struct drm_i915_private
*dev_priv)
}
}
-static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
+static void intel_hdcp2_init(struct intel_connector *connector,
+struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
- ret = initialize_hdcp_port_data(connector, port, shim);
+ ret = initialize_hdcp_port_data(connector, dig_port, shim);
if (ret) {
drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n");
return;
@@ -2074,7 +2076,7 @@ static void intel_hdcp2_init(struct intel_connector
*connector, enum port port,
}
int intel_hdcp_init(struct intel_connector *connector,
- enum port port,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
@@ -2085,7 +2087,7 @@ int intel_hdcp_init(struct intel_connector *connector,
return -EINVAL;
if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
- intel_hdcp2_init(connector, port, shim);
+ intel_hdcp2_init(connector, dig_port, shim);
ret =
drm_connector_attach_content_protection_property(&connector->base,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h
b/drivers/gpu/drm/i915/display/intel_hdcp.h
index b912a3a0f5b8..8f53b0c7fe5c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -18,13 +18,15 @@ struct intel_connector;
struct intel_crtc_state;
struct intel_encoder;
struct intel_hdcp_shim;
+struct intel_digital_port;
enum port;
enum transcoder;
void intel_hdcp_atomic_check(struct drm_connector *connector,
struct drm_connector_state *old_state,
struct drm_connector_state *new_state);
-int intel_hdcp_init(struct intel_connector *connector, enum port port,
+int intel_hdcp_init(struct intel_connector *connector,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *hdcp_shim);
int intel_hdcp_enable(struct intel_connector *connector,
const struct intel_crtc_state *pipe_config, u8
content_type);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index e072
[PATCH v9 11/19] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
hdcp_port_data is specific to a port on which HDCP
encryption is getting enabled, so encapsulate it to
intel_digital_port.
This will be required to enable HDCP 2.2 stream encryption.
v2:
- 's/port_data/hdcp_port_data'. [Ram]
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +
.../drm/i915/display/intel_display_types.h| 5 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 56 +++
3 files changed, 39 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 046c49931b98..54418a6cc3d4 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4965,6 +4965,8 @@ static void intel_ddi_encoder_destroy(struct drm_encoder
*encoder)
intel_dp_encoder_flush_work(encoder);
drm_encoder_cleanup(encoder);
+ if (dig_port)
+ kfree(dig_port->hdcp_port_data.streams);
kfree(dig_port);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index f0aeba9a222a..b74c10c8b01c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -406,7 +406,6 @@ struct intel_hdcp {
* content can flow only through a link protected by HDCP2.2.
*/
u8 content_type;
- struct hdcp_port_data port_data;
bool is_paired;
bool is_repeater;
@@ -1503,10 +1502,12 @@ struct intel_digital_port {
enum phy_fia tc_phy_fia;
u8 tc_phy_fia_idx;
- /* protects num_hdcp_streams reference count */
+ /* protects num_hdcp_streams reference count, hdcp_port_data */
struct mutex hdcp_mutex;
/* the number of pipes using HDCP signalling out of this port */
unsigned int num_hdcp_streams;
+ /* HDCP port data need to pass to security f/w */
+ struct hdcp_port_data hdcp_port_data;
void (*write_infoframe)(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 4ad086e7ec3c..2bec26123a05 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -15,6 +15,7 @@
#include
#include
+#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_display_power.h"
#include "intel_display_types.h"
@@ -1025,7 +1026,8 @@ static int
hdcp2_prepare_ake_init(struct intel_connector *connector,
struct hdcp2_ake_init *ake_data)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1054,7 +1056,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector
*connector,
struct hdcp2_ake_no_stored_km *ek_pub_km,
size_t *msg_sz)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1081,7 +1084,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector
*connector,
static int hdcp2_verify_hprime(struct intel_connector *connector,
struct hdcp2_ake_send_hprime *rx_hprime)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1106,7 +1110,8 @@ static int
hdcp2_store_pairing_info(struct intel_connector *connector,
struct hdcp2_ake_send_pairing_info *pairing_info)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1132,7 +1137,8 @@ static int
hdcp2_prepare_lc_init(struct intel_connector *connector,
struct hdcp2_lc_init *lc_init)
{
- struct hdcp_port_data *data = &conn
[PATCH v9 12/19] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len
Fix the size of WIRED_REPEATER_AUTH_STREAM_REQ cmd buffer size. It is based upon the actual number of MST streams and size of wired_cmd_repeater_auth_stream_req_in. Excluding the size of hdcp_cmd_header. v2: - hdcp_cmd_header size annotation nitpick. [Tomas] Cc: Tomas Winkler Cc: Ramalingam C Acked-by: Tomas Winkler Reviewed-by: Uma Shankar Reviewed-by: Ramalingam C Tested-by: Karthik B S Signed-off-by: Anshuman Gupta --- drivers/misc/mei/hdcp/mei_hdcp.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c index 9ae9669e46ea..3506a3534294 100644 --- a/drivers/misc/mei/hdcp/mei_hdcp.c +++ b/drivers/misc/mei/hdcp/mei_hdcp.c @@ -569,8 +569,7 @@ static int mei_hdcp_verify_mprime(struct device *dev, verify_mprime_in->header.api_version = HDCP_API_VERSION; verify_mprime_in->header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ; verify_mprime_in->header.status = ME_HDCP_STATUS_SUCCESS; - verify_mprime_in->header.buffer_len = - WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN; + verify_mprime_in->header.buffer_len = cmd_size - sizeof(verify_mprime_in->header); verify_mprime_in->port.integrated_port_type = data->port_type; verify_mprime_in->port.physical_port = (u8)data->fw_ddi; -- 2.26.2 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v9 13/19] drm/hdcp: Max MST content streams
Let's define Maximum MST content streams up to four generically which can be supported by modern display controllers. Cc: Sean Paul Cc: Ramalingam C Acked-by: Maarten Lankhorst Reviewed-by: Uma Shankar Reviewed-by: Ramalingam C Tested-by: Karthik B S Signed-off-by: Anshuman Gupta --- include/drm/drm_hdcp.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h index fe58dbb46962..ac22c246542a 100644 --- a/include/drm/drm_hdcp.h +++ b/include/drm/drm_hdcp.h @@ -101,11 +101,11 @@ /* Following Macros take a byte at a time for bit(s) masking */ /* - * TODO: This has to be changed for DP MST, as multiple stream on - * same port is possible. - * For HDCP2.2 on HDMI and DP SST this value is always 1. + * TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual + * H/W MST streams capacity. + * This required to be moved out to platform specific header. */ -#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1 +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4 #define HDCP_2_2_TXCAP_MASK_LEN2 #define HDCP_2_2_RXCAPS_LEN3 #define HDCP_2_2_RX_REPEATER(x)((x) & BIT(0)) -- 2.26.2 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v9 14/19] drm/i915/hdcp: MST streams support in hdcp port_data
Add support for multiple mst stream in hdcp port data
which will be used by RepeaterAuthStreamManage msg and
HDCP 2.2 security f/w for m' validation.
Security f/w doesn't have any provision to mark the stream_type
for each stream separately, it just take single input of
stream_type while authenticating the port and applies the
same stream_type to all streams. So driver mark each stream_type
with common highest supported content type for all streams
in DP MST Topology.
Security f/w supports RepeaterAuthStreamManage msg and m'
validation only once during port authentication and encryption.
Though it is not compulsory, security fw should support dynamic
update of content_type and should support RepeaterAuthStreamManage
msg and m' validation whenever required.
v2:
- Init the hdcp port data k for HDMI/DP SST stream.
v3:
- Cosmetic changes. [Uma]
v4:
- 's/port_auth/hdcp_port_auth'. [Ram]
- Commit log improvement.
v5:
- Comment and commit log improvement. [Ram]
v6:
- Check first connector connected status before intel_encoder_is_mst
to avoid any NULL pointer dereference.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_types.h| 4 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 113 +++---
2 files changed, 102 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index b74c10c8b01c..b37a02a73de6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1502,10 +1502,12 @@ struct intel_digital_port {
enum phy_fia tc_phy_fia;
u8 tc_phy_fia_idx;
- /* protects num_hdcp_streams reference count, hdcp_port_data */
+ /* protects num_hdcp_streams reference count, hdcp_port_data and
hdcp_auth_status */
struct mutex hdcp_mutex;
/* the number of pipes using HDCP signalling out of this port */
unsigned int num_hdcp_streams;
+ /* port HDCP auth status */
+ bool hdcp_auth_status;
/* HDCP port data need to pass to security f/w */
struct hdcp_port_data hdcp_port_data;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 2bec26123a05..bd87694def74 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -26,6 +26,74 @@
#define KEY_LOAD_TRIES 5
#define HDCP2_LC_RETRY_CNT 3
+static int intel_conn_to_vcpi(struct intel_connector *connector)
+{
+ /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
+ return connector->port ? connector->port->vcpi.vcpi : 0;
+}
+
+/*
+ * intel_hdcp_required_content_stream selects the most highest common possible
HDCP
+ * content_type for all streams in DP MST topology because security f/w doesn't
+ * have any provision to mark content_type for each stream separately, it marks
+ * all available streams with the content_type proivided at the time of port
+ * authentication. This may prohibit the userspace to use type1 content on
+ * HDCP 2.2 capable sink because of other sink are not capable of HDCP 2.2 in
+ * DP MST topology. Though it is not compulsory, security fw should change its
+ * policy to mark different content_types for different streams.
+ */
+static int
+intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
+{
+ struct drm_connector_list_iter conn_iter;
+ struct intel_digital_port *conn_dig_port;
+ struct intel_connector *connector;
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct hdcp_port_data *data = &dig_port->hdcp_port_data;
+ bool enforce_type0 = false;
+ int k;
+
+ if (dig_port->hdcp_auth_status)
+ return 0;
+
+ drm_connector_list_iter_begin(&i915->drm, &conn_iter);
+ for_each_intel_connector_iter(connector, &conn_iter) {
+ if (connector->base.status == connector_status_disconnected)
+ continue;
+
+ if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
+ continue;
+
+ conn_dig_port = intel_attached_dig_port(connector);
+ if (conn_dig_port != dig_port)
+ continue;
+
+ if (!enforce_type0 && !intel_hdcp2_capable(connector))
+ enforce_type0 = true;
+
+ data->streams[data->k].stream_id =
intel_conn_to_vcpi(connector);
+ data->k++;
+
+ /* if there is only one active stream */
+ if (dig_port->dp.active_mst_links <= 1)
+ break;
+ }
+ drm_connector_list_iter_end(&conn_iter);
+
+ if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) || data->k
== 0))
+ return -E
[PATCH v9 15/19] drm/i915/hdcp: Pass connector to check_2_2_link
This requires for HDCP 2.2 MST check link.
As for DP/HDMI shims check_2_2_link retrieves the connector
from dig_port, this is not sufficient or DP MST connector,
there can be multiple DP MST topology connector associated
with same dig_port.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
4 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index b37a02a73de6..63de25b40eff 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -379,7 +379,8 @@ struct intel_hdcp_shim {
bool is_repeater, u8 type);
/* HDCP2.2 Link Integrity Check */
- int (*check_2_2_link)(struct intel_digital_port *dig_port);
+ int (*check_2_2_link)(struct intel_digital_port *dig_port,
+ struct intel_connector *connector);
};
struct intel_hdcp {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 3f23f8b53dcd..9ade1ad3a80c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -585,7 +585,8 @@ int intel_dp_hdcp2_config_stream_type(struct
intel_digital_port *dig_port,
}
static
-int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port)
+int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
u8 rx_status;
int ret;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index bd87694def74..3a71577d50cd 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1947,7 +1947,7 @@ static int intel_hdcp2_check_link(struct intel_connector
*connector)
goto out;
}
- ret = hdcp->shim->check_2_2_link(dig_port);
+ ret = hdcp->shim->check_2_2_link(dig_port, connector);
if (ret == HDCP_LINK_PROTECTED) {
if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
intel_hdcp_update_value(connector,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 25d76460f8f9..977e6b6c35c7 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1733,7 +1733,8 @@ int intel_hdmi_hdcp2_read_msg(struct intel_digital_port
*dig_port,
}
static
-int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port)
+int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
int ret;
--
2.26.2
___
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v9 16/19] drm/i915/hdcp: Add HDCP 2.2 stream register
Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
and HDCP2_AUTH_STREAM register in i915_reg header.
B.Spec: 21780
B.Spec: 14410
B.Spec: 50573
v2
- Modified naming convention of HDCP2_STREAM_STATUS
for pre-gen12 platforms inline with B.Spec.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 39 +
1 file changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b448e507d41e..cade0a7a97b2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9873,6 +9873,7 @@ enum skl_power_gate {
_PORTD_HDCP2_BASE, \
_PORTE_HDCP2_BASE, \
_PORTF_HDCP2_BASE) + (x))
+
#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
#define _TRANSA_HDCP2_AUTH 0x66498
#define _TRANSB_HDCP2_AUTH 0x66598
@@ -9912,6 +9913,44 @@ enum skl_power_gate {
TRANS_HDCP2_STATUS(trans) : \
PORT_HDCP2_STATUS(port))
+#define _PIPEA_HDCP2_STREAM_STATUS 0x668C0
+#define _PIPEB_HDCP2_STREAM_STATUS 0x665C0
+#define _PIPEC_HDCP2_STREAM_STATUS 0x666C0
+#define _PIPED_HDCP2_STREAM_STATUS 0x667C0
+#define PIPE_HDCP2_STREAM_STATUS(pipe) _MMIO(_PICK((pipe), \
+
_PIPEA_HDCP2_STREAM_STATUS, \
+
_PIPEB_HDCP2_STREAM_STATUS, \
+
_PIPEC_HDCP2_STREAM_STATUS, \
+
_PIPED_HDCP2_STREAM_STATUS))
+
+#define _TRANSA_HDCP2_STREAM_STATUS0x664C0
+#define _TRANSB_HDCP2_STREAM_STATUS0x665C0
+#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \
+
_TRANSA_HDCP2_STREAM_STATUS, \
+ _TRANSB_HDCP2_STREAM_STATUS)
+#define STREAM_ENCRYPTION_STATUS BIT(31)
+#define STREAM_TYPE_STATUS BIT(30)
+#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+TRANS_HDCP2_STREAM_STATUS(trans) : \
+PIPE_HDCP2_STREAM_STATUS(pipe))
+
+#define _PORTA_HDCP2_AUTH_STREAM 0x66F00
+#define _PORTB_HDCP2_AUTH_STREAM 0x66F04
+#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \
+ _PORTA_HDCP2_AUTH_STREAM, \
+ _PORTB_HDCP2_AUTH_STREAM)
+#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00
+#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04
+#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP2_AUTH_STREAM, \
+ _TRANSB_HDCP2_AUTH_STREAM)
+#define AUTH_STREAM_TYPE BIT(31)
+#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+TRANS_HDCP2_AUTH_STREAM(trans) : \
+PORT_HDCP2_AUTH_STREAM(port))
+
/* Per-pipe DDI Function Control */
#define _TRANS_DDI_FUNC_CTL_A 0x60400
#define _TRANS_DDI_FUNC_CTL_B 0x61400
--
2.26.2
___
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v9 17/19] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
Add support for HDCP 2.2 DP MST shim callback.
This adds existing DP HDCP shim callback for Link Authentication
and Encryption and HDCP 2.2 stream encryption
callback.
v2:
- Added a WARN_ON() instead of drm_err. [Uma]
- Cosmetic changes. [Uma]
v3:
- 's/port_data/hdcp_port_data' [Ram]
- skip redundant link check. [Ram]
v4:
- use pipe instead of port to access HDCP2_STREAM_STATUS
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_types.h| 4 +
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 89 +--
2 files changed, 85 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 63de25b40eff..da91e3f4ff27 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -378,6 +378,10 @@ struct intel_hdcp_shim {
int (*config_stream_type)(struct intel_digital_port *dig_port,
bool is_repeater, u8 type);
+ /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
+ int (*stream_2_2_encryption)(struct intel_connector *connector,
+bool enable);
+
/* HDCP2.2 Link Integrity Check */
int (*check_2_2_link)(struct intel_digital_port *dig_port,
struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 9ade1ad3a80c..f372e25edab4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -698,18 +698,14 @@ intel_dp_mst_hdcp_stream_encryption(struct
intel_connector *connector,
return 0;
}
-static
-bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
- struct intel_connector *connector)
+static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port,
+struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- struct intel_dp *intel_dp = &dig_port->dp;
struct drm_dp_query_stream_enc_status_ack_reply reply;
+ struct intel_dp *intel_dp = &dig_port->dp;
int ret;
- if (!intel_dp_hdcp_check_link(dig_port, connector))
- return false;
-
ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr,
connector->port, &reply);
if (ret) {
@@ -726,6 +722,78 @@ bool intel_dp_mst_hdcp_check_link(struct
intel_digital_port *dig_port,
return reply.auth_completed && reply.encryption_enabled;
}
+static
+bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
+{
+ if (!intel_dp_hdcp_check_link(dig_port, connector))
+ return false;
+
+ return intel_dp_mst_get_qses_status(dig_port, connector);
+}
+
+static int
+intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
+bool enable)
+{
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct hdcp_port_data *data = &dig_port->hdcp_port_data;
+ struct intel_hdcp *hdcp = &connector->hdcp;
+ enum transcoder cpu_transcoder = hdcp->stream_transcoder;
+ enum pipe pipe = (enum pipe)cpu_transcoder;
+ enum port port = dig_port->base.port;
+ int ret;
+
+ drm_WARN_ON(&i915->drm, enable &&
+ !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915,
cpu_transcoder, port))
+ & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
+
+ ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
+ if (ret)
+ return ret;
+
+ /* Wait for encryption confirmation */
+ if (intel_de_wait_for_register(i915,
+ HDCP2_STREAM_STATUS(i915,
cpu_transcoder, pipe),
+ STREAM_ENCRYPTION_STATUS,
+ enable ? STREAM_ENCRYPTION_STATUS : 0,
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ drm_err(&i915->drm, "Timed out waiting for transcoder: %s
stream encryption %s\n",
+ transcoder_name(cpu_transcoder), enable ? "enabled" :
"disabled");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+/*
+ * DP v2.0 I.3.3 ignore the stream signature L' in QSES reply msg reply.
+ * I.3.5 MST source device may use a QSES msg to query downstream status
+ * for a particular stream.
+ */
+static
+int intel_dp_mst_hdcp2_che
[PATCH v9 18/19] drm/i915/hdcp: Configure HDCP2.2 MST steram encryption status
Authenticate and enable port encryption only once for
an active HDCP 2.2 session, once port is authenticated
and encrypted enable encryption for each stream that
requires encryption on this port.
Similarly disable the stream encryption for each encrypted
stream, once all encrypted stream encryption is disabled,
disable the port HDCP encryption and deauthenticate the port.
v2:
- Add connector details in drm_err. [Ram]
- 's/port_auth/hdcp_auth_status'. [Ram]
- Added a debug print for stream enc.
v3:
- uniformity for connector detail in DMESG. [Ram]
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 51 ++-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 3a71577d50cd..576c3777c52f 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1700,6 +1700,36 @@ static int hdcp2_authenticate_sink(struct
intel_connector *connector)
return ret;
}
+static int hdcp2_enable_stream_encryption(struct intel_connector *connector)
+{
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct intel_hdcp *hdcp = &connector->hdcp;
+ enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
+ enum port port = dig_port->base.port;
+ int ret = 0;
+
+ if (!(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder,
port)) &
+ LINK_ENCRYPTION_STATUS)) {
+ drm_err(&dev_priv->drm, "[%s:%d] HDCP 2.2 Link is not
encrypted\n",
+ connector->base.name, connector->base.base.id);
+ return -EPERM;
+ }
+
+ if (hdcp->shim->stream_2_2_encryption) {
+ ret = hdcp->shim->stream_2_2_encryption(connector, true);
+ if (ret) {
+ drm_err(&dev_priv->drm, "[%s:%d] Failed to enable HDCP
2.2 stream enc\n",
+ connector->base.name, connector->base.base.id);
+ return ret;
+ }
+ drm_dbg_kms(&dev_priv->drm, "HDCP 2.2 transcoder: %s stream
encrypted\n",
+ transcoder_name(hdcp->stream_transcoder));
+ }
+
+ return ret;
+}
+
static int hdcp2_enable_encryption(struct intel_connector *connector)
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
@@ -1838,7 +1868,7 @@ static int hdcp2_authenticate_and_encrypt(struct
intel_connector *connector)
drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
}
- if (!ret) {
+ if (!ret && !dig_port->hdcp_auth_status) {
/*
* Ensuring the required 200mSec min time interval between
* Session Key Exchange and encryption.
@@ -1853,6 +1883,8 @@ static int hdcp2_authenticate_and_encrypt(struct
intel_connector *connector)
}
}
+ ret = hdcp2_enable_stream_encryption(connector);
+
return ret;
}
@@ -1898,11 +1930,26 @@ static int _intel_hdcp2_disable(struct intel_connector
*connector)
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
+ struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
connector->base.name, connector->base.base.id);
+ if (hdcp->shim->stream_2_2_encryption) {
+ ret = hdcp->shim->stream_2_2_encryption(connector, false);
+ if (ret) {
+ drm_err(&i915->drm, "[%s:%d] Failed to disable HDCP 2.2
stream enc\n",
+ connector->base.name, connector->base.base.id);
+ return ret;
+ }
+ drm_dbg_kms(&i915->drm, "HDCP 2.2 transcoder: %s stream
encryption disabled\n",
+ transcoder_name(hdcp->stream_transcoder));
+ }
+
+ if (dig_port->num_hdcp_streams > 0)
+ return ret;
+
ret = hdcp2_disable_encryption(connector);
if (hdcp2_deauthenticate_port(connector) < 0)
@@ -1926,6 +1973,7 @@ static int intel_hdcp2_check_link(struct intel_connector
*connector)
int ret = 0;
mutex_lock(&hdcp->mutex);
+ mutex_lock(&dig_port->hdcp_mutex);
cpu_transcoder = hdcp->cpu_transcoder;
/* hdcp2_check_link is expected only when HDCP2.2 is Enabled */
@@ -2003,6 +2051,7 @@ static int intel_hdcp2_check_link(struct intel_connector
*connector)
}
out:
+ mutex_unlock(&dig
[PATCH v9 19/19] drm/i915/hdcp: Enable HDCP 2.2 MST support
Enable HDCP 2.2 MST support till Gen12. Cc: Ramalingam C Reviewed-by: Ramalingam C Tested-by: Karthik B S Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 576c3777c52f..db8dff2eeb0a 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -2233,7 +2233,7 @@ int intel_hdcp_init(struct intel_connector *connector, if (!shim) return -EINVAL; - if (is_hdcp2_supported(dev_priv) && !connector->mst_port) + if (is_hdcp2_supported(dev_priv)) intel_hdcp2_init(connector, dig_port, shim); ret = -- 2.26.2 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] amdgpu: Avoid sleeping during FPU critical sections
Am 08.01.21 um 22:58 schrieb Jeremy Cline:
dcn20_resource_construct() includes a number of kzalloc(GFP_KERNEL)
calls which can sleep, but kernel_fpu_begin() disables preemption and
sleeping in this context is invalid.
The only places the FPU appears to be required is in the
init_soc_bounding_box() function and when calculating the
{min,max}_fill_clk_mhz. Narrow the scope to just these two parts to
avoid sleeping while using the FPU.
Fixes: 7a8a3430be15 ("amdgpu: Wrap FPU dependent functions in dc20")
Cc: Timothy Pearson
Signed-off-by: Jeremy Cline
Good catch, but I would rather replace the kzalloc(GFP_KERNEL) with a
kzalloc(GFP_ATOMIC) for now.
We have tons of problems with this DC_FP_START()/DC_FP_END() annotations
and are even in the process of moving them out of the file because the
compiles tend to clutter FP registers even outside of the annotated
ranges on some architectures.
Regards,
Christian.
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index e04ecf0fc0db..a4fa5bf016c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3622,6 +3622,7 @@ static bool init_soc_bounding_box(struct dc *dc,
if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
int i;
+ DC_FP_START();
dcn2_0_nv12_soc.sr_exit_time_us =
fixed16_to_double_to_cpu(bb->sr_exit_time_us);
dcn2_0_nv12_soc.sr_enter_plus_exit_time_us =
@@ -3721,6 +3722,7 @@ static bool init_soc_bounding_box(struct dc *dc,
dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts =
fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
}
+ DC_FP_END();
}
if (pool->base.pp_smu) {
@@ -3777,8 +3779,6 @@ static bool dcn20_resource_construct(
enum dml_project dml_project_version =
get_dml_project_version(ctx->asic_id.hw_internal_rev);
- DC_FP_START();
-
ctx->dc_bios->regs = &bios_regs;
pool->base.funcs = &dcn20_res_pool_funcs;
@@ -3959,8 +3959,10 @@ static bool dcn20_resource_construct(
ranges.reader_wm_sets[i].wm_inst = i;
ranges.reader_wm_sets[i].min_drain_clk_mhz =
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
ranges.reader_wm_sets[i].max_drain_clk_mhz =
PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+ DC_FP_START();
ranges.reader_wm_sets[i].min_fill_clk_mhz = (i >
0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
ranges.reader_wm_sets[i].max_fill_clk_mhz =
loaded_bb->clock_limits[i].dram_speed_mts / 16;
+ DC_FP_END();
ranges.num_reader_wm_sets = i + 1;
}
@@ -4125,12 +4127,10 @@ static bool dcn20_resource_construct(
pool->base.oem_device = NULL;
}
- DC_FP_END();
return true;
create_fail:
- DC_FP_END();
dcn20_resource_destruct(pool);
return false;
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Re: [drm:dm_plane_helper_prepare_fb [amdgpu]] *ERROR* Failed to pin framebuffer with error -12
Hi Mikhail
Am 10.01.21 um 23:26 schrieb Mikhail Gavrilov:
Hi folks,
today I joined to testing Kernel 5.11 and saw that the kernel log was
flooded with BUG messages:
BUG: sleeping function called from invalid context at mm/vmalloc.c:1756
in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 266, name: kswapd0
INFO: lockdep is turned off.
CPU: 15 PID: 266 Comm: kswapd0 Tainted: GW-
--- 5.11.0-0.rc2.20210108gitf5e6c330254a.119.fc34.x86_64 #1
Hardware name: System manufacturer System Product Name/ROG STRIX
X570-I GAMING, BIOS 2802 10/21/2020
Call Trace:
dump_stack+0x8b/0xb0
___might_sleep.cold+0xb6/0xc6
vm_unmap_aliases+0x21/0x40
change_page_attr_set_clr+0x9e/0x190
set_memory_wb+0x2f/0x80
ttm_pool_free_page+0x28/0x90 [ttm]
ttm_pool_shrink+0x45/0xb0 [ttm]
ttm_pool_shrinker_scan+0xa/0x20 [ttm]
do_shrink_slab+0x177/0x3a0
shrink_slab+0x9c/0x290
shrink_node+0x2e6/0x700
balance_pgdat+0x2f5/0x650
kswapd+0x21d/0x4d0
? do_wait_intr_irq+0xd0/0xd0
? balance_pgdat+0x650/0x650
kthread+0x13a/0x150
? __kthread_bind_mask+0x60/0x60
ret_from_fork+0x22/0x30
I'm probably responsible for this. Need to double check why we try to
allocate memory while freeing some.
But the most unpleasant thing is that after a while the monitor turns
off and does not go on again until the restart.
This is accompanied by an entry in the kernel log:
amdgpu :0b:00.0: amdgpu: ff7d8b94 pin failed
[drm:dm_plane_helper_prepare_fb [amdgpu]] *ERROR* Failed to pin
framebuffer with error -12
-12 is just -ENOMEM. Looks like a memory leak to me, maybe caused by the
problem above, maybe something completely unrelated.
I will take a look.
Thanks,
Christian.
$ grep "Failed to pin framebuffer with error" -Rn .
./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:5816:
DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
$ git blame -L 5811,5821 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
Blaming lines: 0% (11/9167), done.
5d43be0ccbc2f (Christian König 2017-10-26 18:06:23 +0200 5811)
domain = AMDGPU_GEM_DOMAIN_VRAM;
e7b07ceef2a65 (Harry Wentland 2017-08-10 13:29:07 -0400 5812)
7b7c6c81b3a37 (Junwei Zhang2018-06-25 12:51:14 +0800 5813) r =
amdgpu_bo_pin(rbo, domain);
e7b07ceef2a65 (Harry Wentland 2017-08-10 13:29:07 -0400 5814) if
(unlikely(r != 0)) {
30b7c6147d18d (Harry Wentland 2017-10-26 15:35:14 -0400 5815)
if (r != -ERESTARTSYS)
30b7c6147d18d (Harry Wentland 2017-10-26 15:35:14 -0400 5816)
DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
0f257b09531b4 (Chunming Zhou 2019-05-07 19:45:31 +0800 5817)
ttm_eu_backoff_reservation(&ticket, &list);
e7b07ceef2a65 (Harry Wentland 2017-08-10 13:29:07 -0400 5818)
return r;
e7b07ceef2a65 (Harry Wentland 2017-08-10 13:29:07 -0400 5819) }
e7b07ceef2a65 (Harry Wentland 2017-08-10 13:29:07 -0400 5820)
bb812f1ea87dd (Junwei Zhang2018-06-25 13:32:24 +0800 5821) r =
amdgpu_ttm_alloc_gart(&rbo->tbo);
Who knows how to fix it?
Full kernel logs is here:
[1]
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpastebin.com%2FfLasjDHX&data=04%7C01%7Cchristian.koenig%40amd.com%7C15ef83e462e049429be208d8b5b6c6bb%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637459143942981908%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Uj9Ob3lUCAsH8NrxC715zSfl5Yqc44ySVo%2FZkdyTpCM%3D&reserved=0
[2]
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpastebin.com%2Fg3wR2r9e&data=04%7C01%7Cchristian.koenig%40amd.com%7C15ef83e462e049429be208d8b5b6c6bb%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637459143942981908%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=u8irMU3i8c37W5SkyiaAi%2FtwMoPorezm3NI1EYI3csE%3D&reserved=0
--
Best Regards,
Mike Gavrilov.
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Re: [PATCH] MAINTAINERS: update radeon/amdgpu/amdkfd git trees
Am 08.01.21 um 22:33 schrieb Alex Deucher: On Fri, Jan 8, 2021 at 3:52 PM Abramov, Slava wrote: [AMD Official Use Only - Internal Distribution Only] Why not just https://gitlab.freedesktop.org/agd5f/linux ? I guess that works too. Either works for me. Reviewed-by: Christian König Christian. Alex From: amd-gfx on behalf of Alex Deucher Sent: Friday, January 8, 2021 2:30 PM To: amd-gfx list ; Maling list - DRI developers ; Dave Airlie ; Daniel Vetter Cc: Deucher, Alexander Subject: Re: [PATCH] MAINTAINERS: update radeon/amdgpu/amdkfd git trees On Tue, Jan 5, 2021 at 3:15 PM Alex Deucher wrote: FDO is out of space, so move to gitlab. Signed-off-by: Alex Deucher Ping? Any objections? Alex --- MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index eb18459c1d16..e2877be6b10d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -907,7 +907,7 @@ AMD KFD M: Felix Kuehling L: amd-...@lists.freedesktop.org S: Supported -T: git git://people.freedesktop.org/~agd5f/linux +T: git https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fagd5f%2Flinux.git&data=04%7C01%7Cslava.abramov%40amd.com%7Cb4e8adc5393c4b052d6908d8b40bd5db%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637457310677496846%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=xK4Oo8juN%2FoF1jVnLclPtt9MKLzRQ3GPiercdH9ogFE%3D&reserved=0 F: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd*.[ch] F: drivers/gpu/drm/amd/amdkfd/ F: drivers/gpu/drm/amd/include/cik_structs.h @@ -14596,7 +14596,7 @@ M: Alex Deucher M: Christian König L: amd-...@lists.freedesktop.org S: Supported -T: git git://people.freedesktop.org/~agd5f/linux +T: git https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fagd5f%2Flinux.git&data=04%7C01%7Cslava.abramov%40amd.com%7Cb4e8adc5393c4b052d6908d8b40bd5db%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637457310677506842%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=ANez%2BLHaergD6Lae8arcJDyibaf5yPgRyrBfzBpd3vY%3D&reserved=0 F: drivers/gpu/drm/amd/ F: drivers/gpu/drm/radeon/ F: include/uapi/drm/amdgpu_drm.h -- 2.29.2 ___ amd-gfx mailing list amd-...@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cslava.abramov%40amd.com%7Cb4e8adc5393c4b052d6908d8b40bd5db%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637457310677506842%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=gyiwTSaZfiAQpII%2BJUprm5wINz5QEWdQYnm05WoDbD0%3D&reserved=0 ___ amd-gfx mailing list amd-...@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH V4 3/3] drm/vkms: Add information about module options
On Sun, Jan 10, 2021 at 07:35:41PM +0530, Sumera Priyadarsini wrote: > Update vkms documentation to contain usage of `modinfo` > command and steps to load vkms with module options enabled. > > Signed-off-by: Sumera Priyadarsini > --- > Documentation/gpu/vkms.rst | 10 ++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/gpu/vkms.rst b/Documentation/gpu/vkms.rst > index 9e030c74a82e..45fe02f643a8 100644 > --- a/Documentation/gpu/vkms.rst > +++ b/Documentation/gpu/vkms.rst > @@ -35,6 +35,16 @@ Now, to load the driver, use:: > On running the lsmod command now, the VKMS driver will appear listed. > You can also observe the driver being loaded in the dmesg logs. > Maybe start out with "vkms has optional features to simulate different kinds of hardware, which are exposed as module options." Just to make it clear why you'd want to look at module options and set them. Otherwise lgtm, with that change on the entire series: Acked-by: Daniel Vetter > +You can use the `modinfo` command to see module options for vkms:: > + > + modinfo vkms > + > +Module options are helpful when testing, and enabling modules > +can be done while loading vkms. For example, to load vkms with cursor > enabled, > +use:: > + > + sudo modprobe vkms enable_cursor=1 > + > To disable the driver, use :: > >sudo modprobe -r vkms > -- > 2.25.1 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/ttm: Remove pinned bos from LRU in ttm_bo_move_to_lru_tail() v2
Am 08.01.21 um 19:49 schrieb Mike Lothian: Hi This breaks things for me on my Prime system https://gitlab.freedesktop.org/drm/misc/-/issues/23 This is most likely not correct. The patch just fixes another bug which would break prime before it hits the issue in the i915 driver. Christian. Cheers Mike ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 1/2] drm/radeon: stop re-init the TTM page pool
Am 08.01.21 um 16:53 schrieb Daniel Vetter:
On Fri, Jan 8, 2021 at 3:36 PM Christian König wrote:
Am 08.01.21 um 15:31 schrieb Daniel Vetter:
On Thu, Jan 07, 2021 at 09:08:29PM +0100, Christian König wrote:
Am 07.01.21 um 19:07 schrieb Daniel Vetter:
On Tue, Jan 05, 2021 at 07:23:08PM +0100, Christian König wrote:
Drivers are not supposed to init the page pool directly any more.
Signed-off-by: Christian König
Please include reported-by credits and link to the bug reports on
lore.kernel.org when merging this. Also I guess this should have a Fixes:
line?
I'm not aware of a bug report, but the reported-by/Fixes lines are indeed
missing.
This one here:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fdri-devel%2F20201231104020.GA4504%40zn.tnic%2F&data=04%7C01%7Cchristian.koenig%40amd.com%7C3aede203348b4f32ea3108d8b3e224ec%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637457131179258488%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=bHVw4lj1f8g4ohVTeuKNkb0LAbLwY6N4KWortr3VtAo%3D&reserved=0
Or did I get confused, and the above is yet another bug?
Yeah, but that was just reported by mail. The bug tracker I've saw was
opened after the patch was already pushed.
Still good to give reported-by credits for mailing list reports and
link to lore.kernel.org for the report, that's not just useful for
bugzilla reports.
That's indeed true, but I was distracted by the fact that drm-misc-fixes
wasn't up to date :)
Going to add that earlier next time.
BTW: Any idea why dim add-link doesn't work?
Hm we occasionally have fun with email parsing (it's hard) and especially
python changes in how encodings are handled differently between python2
and python3. If you have a specific example I can try and take a look why
it doesn't work.
It just looks up and doesn't seem to do anything. I'm not familiar with
python so I can just describe the symptoms.
I meant tell me which mail (patchwork or lore) and I'll try to
reproduce and see what's maybe up.
It doesn't seem to work in general. E.g. any patch I try I just don't
get any progress in over 10 Minutes.
Maybe some server is not responding?
Christian.
-Daniel
Christian.
-Daniel
And maybe some words on how/why stuff blows up.
Just a typo. I've forgot to remove two lines in radeon while rebasing and
still had the symbols exported so never noticed this.
Christian.
-Daniel
---
drivers/gpu/drm/radeon/radeon_ttm.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c
b/drivers/gpu/drm/radeon/radeon_ttm.c
index d4328ff57757..35b715f82ed8 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -729,9 +729,6 @@ int radeon_ttm_init(struct radeon_device *rdev)
}
rdev->mman.initialized = true;
- ttm_pool_init(&rdev->mman.bdev.pool, rdev->dev, rdev->need_swiotlb,
-dma_addressing_limited(&rdev->pdev->dev));
-
r = radeon_ttm_init_vram(rdev);
if (r) {
DRM_ERROR("Failed initializing VRAM heap.\n");
--
2.25.1
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[PATCH][next] drm/amdgpu: Add missing BOOTUP_DEFAULT to profile_name[]
From: Colin Ian King
A recent change added a new BOOTUP_DEFAULT power profile mode
to the PP_SMC_POWER_PROFILE enum but omitted updating the
corresponding profile_name array. Fix this by adding in the
missing BOOTUP_DEFAULT to profile_name[].
Addresses-Coverity: ("Out-of-bounds read")
Fixes: c27c9778a19e ("drm/amd/powerplay: support BOOTUP_DEFAULT power profile
mode")
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 75ddcadf3802..4763cb095820 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -774,6 +774,7 @@ static int vangogh_get_power_profile_mode(struct
smu_context *smu,
char *buf)
{
static const char *profile_name[] = {
+ "BOOTUP_DEFAULT",
"FULL_SCREEN_3D",
"VIDEO",
"VR",
--
2.29.2
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[PATCH v5 05/21] gpu: host1x: Use HW-equivalent syncpoint expiration check
Make syncpoint expiration checks always use the same logic used by
the hardware. This ensures that there are no race conditions that
could occur because of the hardware triggering a syncpoint interrupt
and then the driver disagreeing.
One situation where this could occur is if a job incremented a
syncpoint too many times -- then the hardware would trigger an
interrupt, but the driver would assume that a syncpoint value
greater than the syncpoint's max value is in the future, and not
clean up the job.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/syncpt.c | 51 ++---
1 file changed, 2 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/host1x/syncpt.c b/drivers/gpu/host1x/syncpt.c
index e48b4595cf53..9ccdf7709946 100644
--- a/drivers/gpu/host1x/syncpt.c
+++ b/drivers/gpu/host1x/syncpt.c
@@ -306,59 +306,12 @@ EXPORT_SYMBOL(host1x_syncpt_wait);
bool host1x_syncpt_is_expired(struct host1x_syncpt *sp, u32 thresh)
{
u32 current_val;
- u32 future_val;
smp_rmb();
current_val = (u32)atomic_read(&sp->min_val);
- future_val = (u32)atomic_read(&sp->max_val);
-
- /* Note the use of unsigned arithmetic here (mod 1<<32).
-*
-* c = current_val = min_val= the current value of the syncpoint.
-* t = thresh = the value we are checking
-* f = future_val = max_val= the value c will reach when all
-*outstanding increments have completed.
-*
-* Note that c always chases f until it reaches f.
-*
-* Dtf = (f - t)
-* Dtc = (c - t)
-*
-* Consider all cases:
-*
-* A) .c..t..f.Dtf < Dtc need to wait
-* B) .c.f..t..Dtf > Dtc expired
-* C) ..t..c.f.Dtf > Dtc expired(Dct very
large)
-*
-* Any case where f==c: always expired (for any t).Dtf == Dcf
-* Any case where t==c: always expired (for any f).Dtf >= Dtc
(because Dtc==0)
-* Any case where t==f!=c: always wait.Dtf < Dtc
(because Dtf==0,
-* Dtc!=0)
-*
-* Other cases:
-*
-* A) .t..f..c.Dtf < Dtc need to wait
-* A) .f..c..t.Dtf < Dtc need to wait
-* A) .f..t..c.Dtf > Dtc expired
-*
-* So:
-* Dtf >= Dtc implies EXPIRED (return true)
-* Dtf < Dtc implies WAIT (return false)
-*
-* Note: If t is expired then we *cannot* wait on it. We would wait
-* forever (hang the system).
-*
-* Note: do NOT get clever and remove the -thresh from both sides. It
-* is NOT the same.
-*
-* If future valueis zero, we have a client managed sync point. In that
-* case we do a direct comparison.
-*/
- if (!host1x_syncpt_client_managed(sp))
- return future_val - thresh >= current_val - thresh;
- else
- return (s32)(current_val - thresh) >= 0;
+
+ return ((current_val - thresh) & 0x8000U) == 0U;
}
int host1x_syncpt_init(struct host1x *host)
--
2.30.0
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[PATCH v5 10/21] gpu: host1x: Add no-recovery mode
Add a new property for jobs to enable or disable recovery i.e.
CPU increments of syncpoints to max value on job timeout. This
allows for a more solid model for hanged jobs, where userspace
doesn't need to guess if a syncpoint increment happened because
the job completed, or because job timeout was triggered.
On job timeout, we stop the channel, NOP all future jobs on the
channel using the same syncpoint, mark the syncpoint as locked
and resume the channel from the next job, if any.
The future jobs are NOPed, since because we don't do the CPU
increments, the value of the syncpoint is no longer synchronized,
and any waiters would become confused if a future job incremented
the syncpoint. The syncpoint is marked locked to ensure that any
future jobs cannot increment the syncpoint either, until the
application has recognized the situation and reallocated the
syncpoint.
Signed-off-by: Mikko Perttunen
---
v5:
* Update for change in put_ref prototype.
* Fixed typo in comment.
v3:
* Move 'locked' check inside CDMA lock to prevent race
* Add clarifying comment to NOP-patching code
---
drivers/gpu/drm/tegra/drm.c| 1 +
drivers/gpu/host1x/cdma.c | 58 ++
drivers/gpu/host1x/hw/channel_hw.c | 2 +-
drivers/gpu/host1x/job.c | 4 +++
drivers/gpu/host1x/syncpt.c| 2 ++
drivers/gpu/host1x/syncpt.h| 12 +++
include/linux/host1x.h | 9 +
7 files changed, 81 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 5a6037eff37f..cd81b52a9e06 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -197,6 +197,7 @@ int tegra_drm_submit(struct tegra_drm_context *context,
job->client = client;
job->class = client->class;
job->serialize = true;
+ job->syncpt_recovery = true;
/*
* Track referenced BOs so that they can be unreferenced after the
diff --git a/drivers/gpu/host1x/cdma.c b/drivers/gpu/host1x/cdma.c
index 6e6ca774f68d..765e5aa64eb6 100644
--- a/drivers/gpu/host1x/cdma.c
+++ b/drivers/gpu/host1x/cdma.c
@@ -312,10 +312,6 @@ static void update_cdma_locked(struct host1x_cdma *cdma)
bool signal = false;
struct host1x_job *job, *n;
- /* If CDMA is stopped, queue is cleared and we can return */
- if (!cdma->running)
- return;
-
/*
* Walk the sync queue, reading the sync point registers as necessary,
* to consume as many sync queue entries as possible without blocking
@@ -324,7 +320,8 @@ static void update_cdma_locked(struct host1x_cdma *cdma)
struct host1x_syncpt *sp = job->syncpt;
/* Check whether this syncpt has completed, and bail if not */
- if (!host1x_syncpt_is_expired(sp, job->syncpt_end)) {
+ if (!host1x_syncpt_is_expired(sp, job->syncpt_end) &&
+ !job->cancelled) {
/* Start timer on next pending syncpt */
if (job->timeout)
cdma_start_timer_locked(cdma, job);
@@ -413,8 +410,11 @@ void host1x_cdma_update_sync_queue(struct host1x_cdma
*cdma,
else
restart_addr = cdma->last_pos;
+ if (!job)
+ goto resume;
+
/* do CPU increments for the remaining syncpts */
- if (job) {
+ if (job->syncpt_recovery) {
dev_dbg(dev, "%s: perform CPU incr on pending buffers\n",
__func__);
@@ -433,8 +433,44 @@ void host1x_cdma_update_sync_queue(struct host1x_cdma
*cdma,
dev_dbg(dev, "%s: finished sync_queue modification\n",
__func__);
+ } else {
+ struct host1x_job *failed_job = job;
+
+ host1x_job_dump(dev, job);
+
+ host1x_syncpt_set_locked(job->syncpt);
+ failed_job->cancelled = true;
+
+ list_for_each_entry_continue(job, &cdma->sync_queue, list) {
+ unsigned int i;
+
+ if (job->syncpt != failed_job->syncpt)
+ continue;
+
+ for (i = 0; i < job->num_slots; i++) {
+ unsigned int slot = (job->first_get/8 + i) %
+ HOST1X_PUSHBUFFER_SLOTS;
+ u32 *mapped = cdma->push_buffer.mapped;
+
+ /*
+* Overwrite opcodes with 0 word writes
+* to offset 0xbad. This does nothing but
+* has a easily detected signature in debug
+* traces.
+*/
+ mapped[2*slot+0] = 0x1bad;
+ mapped[2*slot+1] = 0x1bad;
+ }
+
+
[PATCH v5 04/21] gpu: host1x: Remove cancelled waiters immediately
Before this patch, cancelled waiters would only be cleaned up
once their threshold value was reached. Make host1x_intr_put_ref
process the cancellation immediately to fix this.
Signed-off-by: Mikko Perttunen
---
v5:
* Add parameter to flush, i.e. wait for all pending waiters to
complete before returning. The reason this is not always true
is that the pending waiter might be the place that is calling
the put_ref.
---
drivers/gpu/host1x/intr.c | 23 +--
drivers/gpu/host1x/intr.h | 4 +++-
drivers/gpu/host1x/syncpt.c | 2 +-
3 files changed, 21 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/host1x/intr.c b/drivers/gpu/host1x/intr.c
index 9245add23b5d..70e1096a4fe9 100644
--- a/drivers/gpu/host1x/intr.c
+++ b/drivers/gpu/host1x/intr.c
@@ -242,18 +242,29 @@ int host1x_intr_add_action(struct host1x *host, struct
host1x_syncpt *syncpt,
return 0;
}
-void host1x_intr_put_ref(struct host1x *host, unsigned int id, void *ref)
+void host1x_intr_put_ref(struct host1x *host, unsigned int id, void *ref,
+bool flush)
{
struct host1x_waitlist *waiter = ref;
struct host1x_syncpt *syncpt;
- while (atomic_cmpxchg(&waiter->state, WLS_PENDING, WLS_CANCELLED) ==
- WLS_REMOVED)
- schedule();
+ atomic_cmpxchg(&waiter->state, WLS_PENDING, WLS_CANCELLED);
syncpt = host->syncpt + id;
- (void)process_wait_list(host, syncpt,
- host1x_syncpt_load(host->syncpt + id));
+
+ spin_lock(&syncpt->intr.lock);
+ if (atomic_cmpxchg(&waiter->state, WLS_CANCELLED, WLS_HANDLED) ==
+ WLS_CANCELLED) {
+ list_del(&waiter->list);
+ kref_put(&waiter->refcount, waiter_release);
+ }
+ spin_unlock(&syncpt->intr.lock);
+
+ if (flush) {
+ /* Wait until any concurrently executing handler has finished.
*/
+ while (atomic_read(&waiter->state) != WLS_HANDLED)
+ cpu_relax();
+ }
kref_put(&waiter->refcount, waiter_release);
}
diff --git a/drivers/gpu/host1x/intr.h b/drivers/gpu/host1x/intr.h
index aac38194398f..6ea55e615e3a 100644
--- a/drivers/gpu/host1x/intr.h
+++ b/drivers/gpu/host1x/intr.h
@@ -74,8 +74,10 @@ int host1x_intr_add_action(struct host1x *host, struct
host1x_syncpt *syncpt,
* Unreference an action submitted to host1x_intr_add_action().
* You must call this if you passed non-NULL as ref.
* @ref the ref returned from host1x_intr_add_action()
+ * @flush wait until any pending handlers have completed before returning.
*/
-void host1x_intr_put_ref(struct host1x *host, unsigned int id, void *ref);
+void host1x_intr_put_ref(struct host1x *host, unsigned int id, void *ref,
+bool flush);
/* Initialize host1x sync point interrupt */
int host1x_intr_init(struct host1x *host, unsigned int irq_sync);
diff --git a/drivers/gpu/host1x/syncpt.c b/drivers/gpu/host1x/syncpt.c
index 5982fdf64e1c..e48b4595cf53 100644
--- a/drivers/gpu/host1x/syncpt.c
+++ b/drivers/gpu/host1x/syncpt.c
@@ -293,7 +293,7 @@ int host1x_syncpt_wait(struct host1x_syncpt *sp, u32
thresh, long timeout,
}
}
- host1x_intr_put_ref(sp->host, sp->id, ref);
+ host1x_intr_put_ref(sp->host, sp->id, ref, true);
done:
return err;
--
2.30.0
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 02/21] gpu: host1x: Allow syncpoints without associated client
Syncpoints don't need to be associated with any client,
so remove the property, and expose host1x_syncpt_alloc.
This will allow allocating syncpoints without prior knowledge
of the engine that it will be used with.
Signed-off-by: Mikko Perttunen
---
v3:
* Clean up host1x_syncpt_alloc signature to allow specifying
a name for the syncpoint.
* Export the function.
---
drivers/gpu/host1x/syncpt.c | 22 ++
drivers/gpu/host1x/syncpt.h | 1 -
include/linux/host1x.h | 3 +++
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/host1x/syncpt.c b/drivers/gpu/host1x/syncpt.c
index fce7892d5137..5982fdf64e1c 100644
--- a/drivers/gpu/host1x/syncpt.c
+++ b/drivers/gpu/host1x/syncpt.c
@@ -42,13 +42,13 @@ static void host1x_syncpt_base_free(struct
host1x_syncpt_base *base)
base->requested = false;
}
-static struct host1x_syncpt *host1x_syncpt_alloc(struct host1x *host,
-struct host1x_client *client,
-unsigned long flags)
+struct host1x_syncpt *host1x_syncpt_alloc(struct host1x *host,
+ unsigned long flags,
+ const char *name)
{
struct host1x_syncpt *sp = host->syncpt;
+ char *full_name;
unsigned int i;
- char *name;
mutex_lock(&host->syncpt_mutex);
@@ -64,13 +64,11 @@ static struct host1x_syncpt *host1x_syncpt_alloc(struct
host1x *host,
goto unlock;
}
- name = kasprintf(GFP_KERNEL, "%02u-%s", sp->id,
-client ? dev_name(client->dev) : NULL);
- if (!name)
+ full_name = kasprintf(GFP_KERNEL, "%u-%s", sp->id, name);
+ if (!full_name)
goto free_base;
- sp->client = client;
- sp->name = name;
+ sp->name = full_name;
if (flags & HOST1X_SYNCPT_CLIENT_MANAGED)
sp->client_managed = true;
@@ -87,6 +85,7 @@ static struct host1x_syncpt *host1x_syncpt_alloc(struct
host1x *host,
mutex_unlock(&host->syncpt_mutex);
return NULL;
}
+EXPORT_SYMBOL(host1x_syncpt_alloc);
/**
* host1x_syncpt_id() - retrieve syncpoint ID
@@ -401,7 +400,7 @@ int host1x_syncpt_init(struct host1x *host)
host1x_hw_syncpt_enable_protection(host);
/* Allocate sync point to use for clearing waits for expired fences */
- host->nop_sp = host1x_syncpt_alloc(host, NULL, 0);
+ host->nop_sp = host1x_syncpt_alloc(host, 0, "reserved-nop");
if (!host->nop_sp)
return -ENOMEM;
@@ -423,7 +422,7 @@ struct host1x_syncpt *host1x_syncpt_request(struct
host1x_client *client,
{
struct host1x *host = dev_get_drvdata(client->host->parent);
- return host1x_syncpt_alloc(host, client, flags);
+ return host1x_syncpt_alloc(host, flags, dev_name(client->dev));
}
EXPORT_SYMBOL(host1x_syncpt_request);
@@ -447,7 +446,6 @@ void host1x_syncpt_free(struct host1x_syncpt *sp)
host1x_syncpt_base_free(sp->base);
kfree(sp->name);
sp->base = NULL;
- sp->client = NULL;
sp->name = NULL;
sp->client_managed = false;
diff --git a/drivers/gpu/host1x/syncpt.h b/drivers/gpu/host1x/syncpt.h
index 8e1d04dacaa0..3aa6b25b1b9c 100644
--- a/drivers/gpu/host1x/syncpt.h
+++ b/drivers/gpu/host1x/syncpt.h
@@ -33,7 +33,6 @@ struct host1x_syncpt {
const char *name;
bool client_managed;
struct host1x *host;
- struct host1x_client *client;
struct host1x_syncpt_base *base;
/* interrupt data */
diff --git a/include/linux/host1x.h b/include/linux/host1x.h
index 9eb77c87a83b..7137ce0e35d4 100644
--- a/include/linux/host1x.h
+++ b/include/linux/host1x.h
@@ -154,6 +154,9 @@ int host1x_syncpt_wait(struct host1x_syncpt *sp, u32
thresh, long timeout,
struct host1x_syncpt *host1x_syncpt_request(struct host1x_client *client,
unsigned long flags);
void host1x_syncpt_free(struct host1x_syncpt *sp);
+struct host1x_syncpt *host1x_syncpt_alloc(struct host1x *host,
+ unsigned long flags,
+ const char *name);
struct host1x_syncpt_base *host1x_syncpt_get_base(struct host1x_syncpt *sp);
u32 host1x_syncpt_base_id(struct host1x_syncpt_base *base);
--
2.30.0
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 11/21] gpu: host1x: Add job release callback
Add a callback field to the job structure, to be called just before
the job is to be freed. This allows the job's submitter to clean
up any of its own state, like decrement runtime PM refcounts.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/job.c | 3 +++
include/linux/host1x.h | 4
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/host1x/job.c b/drivers/gpu/host1x/job.c
index 8f59b34672c2..09097e19c0d0 100644
--- a/drivers/gpu/host1x/job.c
+++ b/drivers/gpu/host1x/job.c
@@ -79,6 +79,9 @@ static void job_free(struct kref *ref)
{
struct host1x_job *job = container_of(ref, struct host1x_job, ref);
+ if (job->release)
+ job->release(job);
+
if (job->waiter)
host1x_intr_put_ref(job->syncpt->host, job->syncpt->id,
job->waiter, false);
diff --git a/include/linux/host1x.h b/include/linux/host1x.h
index 81ca70066c76..d48cab563d5c 100644
--- a/include/linux/host1x.h
+++ b/include/linux/host1x.h
@@ -265,6 +265,10 @@ struct host1x_job {
/* Fast-forward syncpoint increments on job timeout */
bool syncpt_recovery;
+
+ /* Callback called when job is freed */
+ void (*release)(struct host1x_job *job);
+ void *user_data;
};
struct host1x_job *host1x_job_alloc(struct host1x_channel *ch,
--
2.30.0
___
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[PATCH v5 19/21] drm/tegra: Implement new UAPI
Implement the non-submission parts of the new UAPI, including
channel management and memory mapping. The UAPI is under the
CONFIG_DRM_TEGRA_STAGING config flag for now.
Signed-off-by: Mikko Perttunen
---
v5:
* Set iova_end in both mapping paths
v4:
* New patch, split out from combined UAPI + submit patch.
---
drivers/gpu/drm/tegra/Makefile| 1 +
drivers/gpu/drm/tegra/drm.c | 41 ++--
drivers/gpu/drm/tegra/drm.h | 5 +
drivers/gpu/drm/tegra/uapi.h | 63 ++
drivers/gpu/drm/tegra/uapi/uapi.c | 307 ++
5 files changed, 401 insertions(+), 16 deletions(-)
create mode 100644 drivers/gpu/drm/tegra/uapi.h
create mode 100644 drivers/gpu/drm/tegra/uapi/uapi.c
diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile
index d6cf202414f0..0abdb21b38b9 100644
--- a/drivers/gpu/drm/tegra/Makefile
+++ b/drivers/gpu/drm/tegra/Makefile
@@ -3,6 +3,7 @@ ccflags-$(CONFIG_DRM_TEGRA_DEBUG) += -DDEBUG
tegra-drm-y := \
drm.o \
+ uapi/uapi.o \
gem.o \
fb.o \
dp.o \
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index afd3f143c5e0..6a51035ce33f 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -20,6 +20,7 @@
#include
#include
+#include "uapi.h"
#include "drm.h"
#include "gem.h"
@@ -33,11 +34,6 @@
#define CARVEOUT_SZ SZ_64M
#define CDMA_GATHER_FETCHES_MAX_NB 16383
-struct tegra_drm_file {
- struct idr contexts;
- struct mutex lock;
-};
-
static int tegra_atomic_check(struct drm_device *drm,
struct drm_atomic_state *state)
{
@@ -90,7 +86,8 @@ static int tegra_drm_open(struct drm_device *drm, struct
drm_file *filp)
if (!fpriv)
return -ENOMEM;
- idr_init_base(&fpriv->contexts, 1);
+ idr_init_base(&fpriv->legacy_contexts, 1);
+ xa_init_flags(&fpriv->contexts, XA_FLAGS_ALLOC1);
mutex_init(&fpriv->lock);
filp->driver_priv = fpriv;
@@ -429,7 +426,7 @@ static int tegra_client_open(struct tegra_drm_file *fpriv,
if (err < 0)
return err;
- err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
+ err = idr_alloc(&fpriv->legacy_contexts, context, 1, 0, GFP_KERNEL);
if (err < 0) {
client->ops->close_channel(context);
return err;
@@ -484,13 +481,13 @@ static int tegra_close_channel(struct drm_device *drm,
void *data,
mutex_lock(&fpriv->lock);
- context = idr_find(&fpriv->contexts, args->context);
+ context = idr_find(&fpriv->legacy_contexts, args->context);
if (!context) {
err = -EINVAL;
goto unlock;
}
- idr_remove(&fpriv->contexts, context->id);
+ idr_remove(&fpriv->legacy_contexts, context->id);
tegra_drm_context_free(context);
unlock:
@@ -509,7 +506,7 @@ static int tegra_get_syncpt(struct drm_device *drm, void
*data,
mutex_lock(&fpriv->lock);
- context = idr_find(&fpriv->contexts, args->context);
+ context = idr_find(&fpriv->legacy_contexts, args->context);
if (!context) {
err = -ENODEV;
goto unlock;
@@ -538,7 +535,7 @@ static int tegra_submit(struct drm_device *drm, void *data,
mutex_lock(&fpriv->lock);
- context = idr_find(&fpriv->contexts, args->context);
+ context = idr_find(&fpriv->legacy_contexts, args->context);
if (!context) {
err = -ENODEV;
goto unlock;
@@ -563,7 +560,7 @@ static int tegra_get_syncpt_base(struct drm_device *drm,
void *data,
mutex_lock(&fpriv->lock);
- context = idr_find(&fpriv->contexts, args->context);
+ context = idr_find(&fpriv->legacy_contexts, args->context);
if (!context) {
err = -ENODEV;
goto unlock;
@@ -732,10 +729,21 @@ static int tegra_gem_get_flags(struct drm_device *drm,
void *data,
static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
#ifdef CONFIG_DRM_TEGRA_STAGING
- DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
+ DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_OPEN, tegra_drm_ioctl_channel_open,
+ DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_CLOSE, tegra_drm_ioctl_channel_close,
+ DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_MAP, tegra_drm_ioctl_channel_map,
DRM_RENDER_ALLOW),
- DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
+ DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_UNMAP, tegra_drm_ioctl_channel_unmap,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_drm_ioctl_gem_create,
+ DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_drm_ioctl_gem_mmap,
+ DRM_RENDER_ALLOW),
+
+ DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE_LEGACY,
[PATCH v5 09/21] gpu: host1x: DMA fences and userspace fence creation
Add an implementation of dma_fences based on syncpoints. Syncpoint
interrupts are used to signal fences. Additionally, after
software signaling has been enabled, a 30 second timeout is started.
If the syncpoint threshold is not reached within this period,
the fence is signalled with an -ETIMEDOUT error code. This is to
allow fences that would never reach their syncpoint threshold to
be cleaned up.
Additionally, add a new /dev/host1x IOCTL for creating sync_file
file descriptors backed by syncpoint fences.
Signed-off-by: Mikko Perttunen
---
v5:
* Update for change in put_ref prototype.
v4:
* Fix _signal prototype and include it to avoid warning
* Remove use of unused local in error path
v3:
* Move declaration of host1x_fence_extract to public header
---
drivers/gpu/host1x/Makefile | 1 +
drivers/gpu/host1x/fence.c | 208
drivers/gpu/host1x/fence.h | 13 +++
drivers/gpu/host1x/intr.c | 9 ++
drivers/gpu/host1x/intr.h | 2 +
drivers/gpu/host1x/uapi.c | 103 ++
include/linux/host1x.h | 4 +
7 files changed, 340 insertions(+)
create mode 100644 drivers/gpu/host1x/fence.c
create mode 100644 drivers/gpu/host1x/fence.h
diff --git a/drivers/gpu/host1x/Makefile b/drivers/gpu/host1x/Makefile
index 882f928d75e1..a48af2cefae1 100644
--- a/drivers/gpu/host1x/Makefile
+++ b/drivers/gpu/host1x/Makefile
@@ -10,6 +10,7 @@ host1x-y = \
debug.o \
mipi.o \
uapi.o \
+ fence.o \
hw/host1x01.o \
hw/host1x02.o \
hw/host1x04.o \
diff --git a/drivers/gpu/host1x/fence.c b/drivers/gpu/host1x/fence.c
new file mode 100644
index ..e96ad93ff656
--- /dev/null
+++ b/drivers/gpu/host1x/fence.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Syncpoint dma_fence implementation
+ *
+ * Copyright (c) 2020, NVIDIA Corporation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "fence.h"
+#include "intr.h"
+#include "syncpt.h"
+
+DEFINE_SPINLOCK(lock);
+
+struct host1x_syncpt_fence {
+ struct dma_fence base;
+
+ atomic_t signaling;
+
+ struct host1x_syncpt *sp;
+ u32 threshold;
+
+ struct host1x_waitlist *waiter;
+ void *waiter_ref;
+
+ struct delayed_work timeout_work;
+};
+
+static const char *syncpt_fence_get_driver_name(struct dma_fence *f)
+{
+ return "host1x";
+}
+
+static const char *syncpt_fence_get_timeline_name(struct dma_fence *f)
+{
+ return "syncpoint";
+}
+
+static bool syncpt_fence_enable_signaling(struct dma_fence *f)
+{
+ struct host1x_syncpt_fence *sf =
+ container_of(f, struct host1x_syncpt_fence, base);
+ int err;
+
+ if (host1x_syncpt_is_expired(sf->sp, sf->threshold))
+ return false;
+
+ dma_fence_get(f);
+
+ /*
+* The dma_fence framework requires the fence driver to keep a
+* reference to any fences for which 'enable_signaling' has been
+* called (and that have not been signalled).
+*
+* We provide a userspace API to create arbitrary syncpoint fences,
+* so we cannot normally guarantee that all fences get signalled.
+* As such, setup a timeout, so that long-lasting fences will get
+* reaped eventually.
+*/
+ schedule_delayed_work(&sf->timeout_work, msecs_to_jiffies(3));
+
+ err = host1x_intr_add_action(sf->sp->host, sf->sp, sf->threshold,
+HOST1X_INTR_ACTION_SIGNAL_FENCE, f,
+sf->waiter, &sf->waiter_ref);
+ if (err) {
+ cancel_delayed_work_sync(&sf->timeout_work);
+ dma_fence_put(f);
+ return false;
+ }
+
+ /* intr framework takes ownership of waiter */
+ sf->waiter = NULL;
+
+ /*
+* The fence may get signalled at any time after the above call,
+* so we need to initialize all state used by signalling
+* before it.
+*/
+
+ return true;
+}
+
+static void syncpt_fence_release(struct dma_fence *f)
+{
+ struct host1x_syncpt_fence *sf =
+ container_of(f, struct host1x_syncpt_fence, base);
+
+ if (sf->waiter)
+ kfree(sf->waiter);
+
+ dma_fence_free(f);
+}
+
+const struct dma_fence_ops syncpt_fence_ops = {
+ .get_driver_name = syncpt_fence_get_driver_name,
+ .get_timeline_name = syncpt_fence_get_timeline_name,
+ .enable_signaling = syncpt_fence_enable_signaling,
+ .release = syncpt_fence_release,
+};
+
+void host1x_fence_signal(struct host1x_syncpt_fence *f)
+{
+ if (atomic_xchg(&f->signaling, 1))
+ return;
+
+ /*
+* Cancel pending timeout work - if it races, it will
+* not get 'f->signaling' and return.
+*/
+ cancel_delayed_work_sync(&f->timeout_work);
+
+ host1x_intr_put_ref(f->sp->host, f->sp->id, f->waiter_ref, false);
+
+ dma_fen
[PATCH v5 00/21] Host1x/TegraDRM UAPI
Hi all, here's the fifth revision of the Host1x/TegraDRM UAPI proposal, containing primarily small bug fixes. It has also been rebased on top of recent linux-next. vaapi-tegra-driver has been updated to support the new UAPI as well as Tegra186: https://github.com/cyndis/vaapi-tegra-driver The `putsurface` program has been tested to work. The test suite for the new UAPI is available at https://github.com/cyndis/uapi-test The series can be also found in https://github.com/cyndis/linux/commits/work/host1x-uapi-v5. Older versions: v1: https://www.spinics.net/lists/linux-tegra/msg51000.html v2: https://www.spinics.net/lists/linux-tegra/msg53061.html v3: https://www.spinics.net/lists/linux-tegra/msg54370.html v4: https://www.spinics.net/lists/dri-devel/msg279897.html Thank you, Mikko Mikko Perttunen (21): gpu: host1x: Use different lock classes for each client gpu: host1x: Allow syncpoints without associated client gpu: host1x: Show number of pending waiters in debugfs gpu: host1x: Remove cancelled waiters immediately gpu: host1x: Use HW-equivalent syncpoint expiration check gpu: host1x: Cleanup and refcounting for syncpoints gpu: host1x: Introduce UAPI header gpu: host1x: Implement /dev/host1x device node gpu: host1x: DMA fences and userspace fence creation gpu: host1x: Add no-recovery mode gpu: host1x: Add job release callback gpu: host1x: Add support for syncpoint waits in CDMA pushbuffer gpu: host1x: Reset max value when freeing a syncpoint gpu: host1x: Reserve VBLANK syncpoints at initialization drm/tegra: Add new UAPI to header drm/tegra: Boot VIC during runtime PM resume drm/tegra: Set resv fields when importing/exporting GEMs drm/tegra: Allocate per-engine channel in core code drm/tegra: Implement new UAPI drm/tegra: Implement job submission part of new UAPI drm/tegra: Add job firewall drivers/gpu/drm/tegra/Makefile | 4 + drivers/gpu/drm/tegra/dc.c | 10 +- drivers/gpu/drm/tegra/drm.c| 69 ++-- drivers/gpu/drm/tegra/drm.h| 9 + drivers/gpu/drm/tegra/gem.c| 2 + drivers/gpu/drm/tegra/gr2d.c | 4 +- drivers/gpu/drm/tegra/gr3d.c | 4 +- drivers/gpu/drm/tegra/uapi.h | 63 drivers/gpu/drm/tegra/uapi/firewall.c | 221 + drivers/gpu/drm/tegra/uapi/gather_bo.c | 86 + drivers/gpu/drm/tegra/uapi/gather_bo.h | 22 ++ drivers/gpu/drm/tegra/uapi/submit.c| 436 + drivers/gpu/drm/tegra/uapi/submit.h| 21 ++ drivers/gpu/drm/tegra/uapi/uapi.c | 307 + drivers/gpu/drm/tegra/vic.c| 118 --- drivers/gpu/host1x/Makefile| 2 + drivers/gpu/host1x/bus.c | 7 +- drivers/gpu/host1x/cdma.c | 69 +++- drivers/gpu/host1x/debug.c | 14 +- drivers/gpu/host1x/dev.c | 15 + drivers/gpu/host1x/dev.h | 16 +- drivers/gpu/host1x/fence.c | 208 drivers/gpu/host1x/fence.h | 13 + drivers/gpu/host1x/hw/cdma_hw.c| 2 +- drivers/gpu/host1x/hw/channel_hw.c | 63 ++-- drivers/gpu/host1x/hw/debug_hw.c | 11 +- drivers/gpu/host1x/intr.c | 32 +- drivers/gpu/host1x/intr.h | 6 +- drivers/gpu/host1x/job.c | 79 +++-- drivers/gpu/host1x/job.h | 14 + drivers/gpu/host1x/syncpt.c| 187 ++- drivers/gpu/host1x/syncpt.h| 16 +- drivers/gpu/host1x/uapi.c | 385 ++ drivers/gpu/host1x/uapi.h | 22 ++ drivers/staging/media/tegra-video/vi.c | 4 +- include/linux/host1x.h | 47 ++- include/uapi/drm/tegra_drm.h | 338 +-- include/uapi/linux/host1x.h| 134 38 files changed, 2771 insertions(+), 289 deletions(-) create mode 100644 drivers/gpu/drm/tegra/uapi.h create mode 100644 drivers/gpu/drm/tegra/uapi/firewall.c create mode 100644 drivers/gpu/drm/tegra/uapi/gather_bo.c create mode 100644 drivers/gpu/drm/tegra/uapi/gather_bo.h create mode 100644 drivers/gpu/drm/tegra/uapi/submit.c create mode 100644 drivers/gpu/drm/tegra/uapi/submit.h create mode 100644 drivers/gpu/drm/tegra/uapi/uapi.c create mode 100644 drivers/gpu/host1x/fence.c create mode 100644 drivers/gpu/host1x/fence.h create mode 100644 drivers/gpu/host1x/uapi.c create mode 100644 drivers/gpu/host1x/uapi.h create mode 100644 include/uapi/linux/host1x.h -- 2.30.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 14/21] gpu: host1x: Reserve VBLANK syncpoints at initialization
On T20-T148 chips, the bootloader can set up a boot splash
screen with DC configured to increment syncpoint 26/27
at VBLANK. Because of this we shouldn't allow these syncpoints
to be allocated until DC has been reset and will no longer
increment them in the background.
As such, on these chips, reserve those two syncpoints at
initialization, and only mark them free once the DC
driver has indicated it's safe to do so.
Signed-off-by: Mikko Perttunen
---
v3:
* New patch
---
drivers/gpu/drm/tegra/dc.c | 6 ++
drivers/gpu/host1x/dev.c| 6 ++
drivers/gpu/host1x/dev.h| 6 ++
drivers/gpu/host1x/syncpt.c | 34 +-
include/linux/host1x.h | 3 +++
5 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 033032dfc4b9..d0cee40ab3e6 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -2033,6 +2033,12 @@ static int tegra_dc_init(struct host1x_client *client)
struct drm_plane *cursor = NULL;
int err;
+ /*
+* DC has been reset by now, so VBLANK syncpoint can be released
+* for general use.
+*/
+ host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe);
+
/*
* XXX do not register DCs with no window groups because we cannot
* assign a primary plane to them, which in turn will cause KMS to
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 641317d23828..8b50fbb22846 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -77,6 +77,7 @@ static const struct host1x_info host1x01_info = {
.has_hypervisor = false,
.num_sid_entries = 0,
.sid_table = NULL,
+ .reserve_vblank_syncpts = true,
};
static const struct host1x_info host1x02_info = {
@@ -91,6 +92,7 @@ static const struct host1x_info host1x02_info = {
.has_hypervisor = false,
.num_sid_entries = 0,
.sid_table = NULL,
+ .reserve_vblank_syncpts = true,
};
static const struct host1x_info host1x04_info = {
@@ -105,6 +107,7 @@ static const struct host1x_info host1x04_info = {
.has_hypervisor = false,
.num_sid_entries = 0,
.sid_table = NULL,
+ .reserve_vblank_syncpts = false,
};
static const struct host1x_info host1x05_info = {
@@ -119,6 +122,7 @@ static const struct host1x_info host1x05_info = {
.has_hypervisor = false,
.num_sid_entries = 0,
.sid_table = NULL,
+ .reserve_vblank_syncpts = false,
};
static const struct host1x_sid_entry tegra186_sid_table[] = {
@@ -142,6 +146,7 @@ static const struct host1x_info host1x06_info = {
.has_hypervisor = true,
.num_sid_entries = ARRAY_SIZE(tegra186_sid_table),
.sid_table = tegra186_sid_table,
+ .reserve_vblank_syncpts = false,
};
static const struct host1x_sid_entry tegra194_sid_table[] = {
@@ -165,6 +170,7 @@ static const struct host1x_info host1x07_info = {
.has_hypervisor = true,
.num_sid_entries = ARRAY_SIZE(tegra194_sid_table),
.sid_table = tegra194_sid_table,
+ .reserve_vblank_syncpts = false,
};
static const struct of_device_id host1x_of_match[] = {
diff --git a/drivers/gpu/host1x/dev.h b/drivers/gpu/host1x/dev.h
index 7b8b7e20e32b..e360bc4a25f6 100644
--- a/drivers/gpu/host1x/dev.h
+++ b/drivers/gpu/host1x/dev.h
@@ -102,6 +102,12 @@ struct host1x_info {
bool has_hypervisor; /* has hypervisor registers */
unsigned int num_sid_entries;
const struct host1x_sid_entry *sid_table;
+ /*
+* On T20-T148, the boot chain may setup DC to increment syncpoints
+* 26/27 on VBLANK. As such we cannot use these syncpoints until
+* the display driver disables VBLANK increments.
+*/
+ bool reserve_vblank_syncpts;
};
struct host1x {
diff --git a/drivers/gpu/host1x/syncpt.c b/drivers/gpu/host1x/syncpt.c
index 9c39f5bfc70c..100270ac5bcf 100644
--- a/drivers/gpu/host1x/syncpt.c
+++ b/drivers/gpu/host1x/syncpt.c
@@ -52,7 +52,7 @@ struct host1x_syncpt *host1x_syncpt_alloc(struct host1x *host,
mutex_lock(&host->syncpt_mutex);
- for (i = 0; i < host->info->nb_pts && sp->name; i++, sp++)
+ for (i = 0; i < host->info->nb_pts && kref_read(&sp->ref); i++, sp++)
;
if (i >= host->info->nb_pts)
@@ -359,6 +359,11 @@ int host1x_syncpt_init(struct host1x *host)
if (!host->nop_sp)
return -ENOMEM;
+ if (host->info->reserve_vblank_syncpts) {
+ kref_init(&host->syncpt[26].ref);
+ kref_init(&host->syncpt[27].ref);
+ }
+
return 0;
}
@@ -545,3 +550,30 @@ u32 host1x_syncpt_base_id(struct host1x_syncpt_base *base)
return base->id;
}
EXPORT_SYMBOL(host1x_syncpt_base_id);
+
+static void do_nothing(struct kref *ref)
+{
+}
+
+/**
+ * host1x_syncpt_release_vblank_reservation() - Make VBLANK syncpoint
+ *
[PATCH v5 15/21] drm/tegra: Add new UAPI to header
Update the tegra_drm.h UAPI header, adding the new proposed UAPI.
The old staging UAPI is left in for now, with minor modification
to avoid name collisions.
Signed-off-by: Mikko Perttunen
---
v4:
* Remove features that are not strictly necessary
* Remove padding/reserved fields in IOCTL structs where
DRM's zero extension feature allows future expansion
v3:
* Remove timeout field
* Inline the syncpt_incrs array to the submit structure
* Remove WRITE_RELOC (it is now implicit)
---
include/uapi/drm/tegra_drm.h | 338 ---
1 file changed, 311 insertions(+), 27 deletions(-)
diff --git a/include/uapi/drm/tegra_drm.h b/include/uapi/drm/tegra_drm.h
index c4df3c3668b3..014bc393c298 100644
--- a/include/uapi/drm/tegra_drm.h
+++ b/include/uapi/drm/tegra_drm.h
@@ -1,24 +1,5 @@
-/*
- * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+/* SPDX-License-Identifier: MIT */
+/* Copyright (c) 2012-2020 NVIDIA Corporation */
#ifndef _UAPI_TEGRA_DRM_H_
#define _UAPI_TEGRA_DRM_H_
@@ -29,6 +10,8 @@
extern "C" {
#endif
+/* TegraDRM legacy UAPI. Only enabled with STAGING */
+
#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
@@ -644,13 +627,13 @@ struct drm_tegra_gem_get_flags {
__u32 flags;
};
-#define DRM_TEGRA_GEM_CREATE 0x00
-#define DRM_TEGRA_GEM_MMAP 0x01
+#define DRM_TEGRA_GEM_CREATE_LEGACY0x00
+#define DRM_TEGRA_GEM_MMAP_LEGACY 0x01
#define DRM_TEGRA_SYNCPT_READ 0x02
#define DRM_TEGRA_SYNCPT_INCR 0x03
#define DRM_TEGRA_SYNCPT_WAIT 0x04
-#define DRM_TEGRA_OPEN_CHANNEL 0x05
-#define DRM_TEGRA_CLOSE_CHANNEL0x06
+#define DRM_TEGRA_OPEN_CHANNEL 0x05
+#define DRM_TEGRA_CLOSE_CHANNEL0x06
#define DRM_TEGRA_GET_SYNCPT 0x07
#define DRM_TEGRA_SUBMIT 0x08
#define DRM_TEGRA_GET_SYNCPT_BASE 0x09
@@ -659,8 +642,8 @@ struct drm_tegra_gem_get_flags {
#define DRM_TEGRA_GEM_SET_FLAGS0x0c
#define DRM_TEGRA_GEM_GET_FLAGS0x0d
-#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
-#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE +
DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
+#define DRM_IOCTL_TEGRA_GEM_CREATE_LEGACY DRM_IOWR(DRM_COMMAND_BASE +
DRM_TEGRA_GEM_CREATE_LEGACY, struct drm_tegra_gem_create)
+#define DRM_IOCTL_TEGRA_GEM_MMAP_LEGACY DRM_IOWR(DRM_COMMAND_BASE +
DRM_TEGRA_GEM_MMAP_LEGACY, struct drm_tegra_gem_mmap)
#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE +
DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE +
DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE +
DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
@@ -674,6 +657,307 @@ struct drm_tegra_gem_get_flags {
#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE +
DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE +
DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
+/* New TegraDRM UAPI */
+
+struct drm_tegra_channel_open {
+ /**
+* @host1x_class: [in]
+*
+* Host1x class of the engine that will be programmed using this
+* channel.
+*/
+ __u32 host1x_class;
+
+ /**
+* @flags: [in]
+*
+* Flags.
+*/
+ __u32 flags;
+
+ /**
+* @channel_ctx: [out]
+*
+* Opaque identifier corresponding to the opened channel.
+*/
+ __u32 channel_ctx;
+
+ /**
+* @hardware_version: [out]
+*
+* Version of the engine hardware. This can be used by
[PATCH v5 20/21] drm/tegra: Implement job submission part of new UAPI
Implement the job submission IOCTL with a minimum feature set.
Signed-off-by: Mikko Perttunen
---
v5:
* Add 16K size limit to copies from userspace.
* Guard RELOC_BLOCKLINEAR flag handling to only exist in ARM64
to prevent oversized shift on 32-bit platforms.
v4:
* Remove all features that are not strictly necessary.
* Split into two patches.
v3:
* Remove WRITE_RELOC. Relocations are now patched implicitly
when patching is needed.
* Directly call PM runtime APIs on devices instead of using
power_on/power_off callbacks.
* Remove incorrect mutex unlock in tegra_drm_ioctl_channel_open
* Use XA_FLAGS_ALLOC1 instead of XA_FLAGS_ALLOC
* Accommodate for removal of timeout field and inlining of
syncpt_incrs array.
* Copy entire user arrays at a time instead of going through
elements one-by-one.
* Implement waiting of DMA reservations.
* Split out gather_bo implementation into a separate file.
* Fix length parameter passed to sg_init_one in gather_bo
* Cosmetic cleanup.
---
drivers/gpu/drm/tegra/Makefile | 2 +
drivers/gpu/drm/tegra/drm.c| 2 +
drivers/gpu/drm/tegra/uapi/gather_bo.c | 86 +
drivers/gpu/drm/tegra/uapi/gather_bo.h | 22 ++
drivers/gpu/drm/tegra/uapi/submit.c| 428 +
drivers/gpu/drm/tegra/uapi/submit.h| 17 +
6 files changed, 557 insertions(+)
create mode 100644 drivers/gpu/drm/tegra/uapi/gather_bo.c
create mode 100644 drivers/gpu/drm/tegra/uapi/gather_bo.h
create mode 100644 drivers/gpu/drm/tegra/uapi/submit.c
create mode 100644 drivers/gpu/drm/tegra/uapi/submit.h
diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile
index 0abdb21b38b9..059322e88943 100644
--- a/drivers/gpu/drm/tegra/Makefile
+++ b/drivers/gpu/drm/tegra/Makefile
@@ -4,6 +4,8 @@ ccflags-$(CONFIG_DRM_TEGRA_DEBUG) += -DDEBUG
tegra-drm-y := \
drm.o \
uapi/uapi.o \
+ uapi/submit.o \
+ uapi/gather_bo.o \
gem.o \
fb.o \
dp.o \
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 6a51035ce33f..60eab403ae9b 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -737,6 +737,8 @@ static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_UNMAP, tegra_drm_ioctl_channel_unmap,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_SUBMIT, tegra_drm_ioctl_channel_submit,
+ DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_drm_ioctl_gem_create,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_drm_ioctl_gem_mmap,
diff --git a/drivers/gpu/drm/tegra/uapi/gather_bo.c
b/drivers/gpu/drm/tegra/uapi/gather_bo.c
new file mode 100644
index ..b487a0d44648
--- /dev/null
+++ b/drivers/gpu/drm/tegra/uapi/gather_bo.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2020 NVIDIA Corporation */
+
+#include
+#include
+
+#include "gather_bo.h"
+
+static struct host1x_bo *gather_bo_get(struct host1x_bo *host_bo)
+{
+ struct gather_bo *bo = container_of(host_bo, struct gather_bo, base);
+
+ kref_get(&bo->ref);
+
+ return host_bo;
+}
+
+static void gather_bo_release(struct kref *ref)
+{
+ struct gather_bo *bo = container_of(ref, struct gather_bo, ref);
+
+ kfree(bo->gather_data);
+ kfree(bo);
+}
+
+void gather_bo_put(struct host1x_bo *host_bo)
+{
+ struct gather_bo *bo = container_of(host_bo, struct gather_bo, base);
+
+ kref_put(&bo->ref, gather_bo_release);
+}
+
+static struct sg_table *
+gather_bo_pin(struct device *dev, struct host1x_bo *host_bo, dma_addr_t *phys)
+{
+ struct gather_bo *bo = container_of(host_bo, struct gather_bo, base);
+ struct sg_table *sgt;
+ int err;
+
+ if (phys) {
+ *phys = virt_to_phys(bo->gather_data);
+ return NULL;
+ }
+
+ sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
+ if (!sgt)
+ return ERR_PTR(-ENOMEM);
+
+ err = sg_alloc_table(sgt, 1, GFP_KERNEL);
+ if (err) {
+ kfree(sgt);
+ return ERR_PTR(err);
+ }
+
+ sg_init_one(sgt->sgl, bo->gather_data, bo->gather_data_words*4);
+
+ return sgt;
+}
+
+static void gather_bo_unpin(struct device *dev, struct sg_table *sgt)
+{
+ if (sgt) {
+ sg_free_table(sgt);
+ kfree(sgt);
+ }
+}
+
+static void *gather_bo_mmap(struct host1x_bo *host_bo)
+{
+ struct gather_bo *bo = container_of(host_bo, struct gather_bo, base);
+
+ return bo->gather_data;
+}
+
+static void gather_bo_munmap(struct host1x_bo *host_bo, void *addr)
+{
+}
+
+const struct host1x_bo_ops gather_bo_ops = {
+ .get = gather_bo_get,
+ .put = gather_bo_put,
+ .pin = gather_bo_pin,
+ .unpin = gather_bo_unpin,
+ .mmap = gather_bo_mmap,
+ .mu
[PATCH v5 16/21] drm/tegra: Boot VIC during runtime PM resume
With the new UAPI implementation, engines are powered on and off
when there are active jobs, and the core code handles channel
allocation. To accommodate that, boot the engine as part of
runtime PM instead of using the open_channel callback, which is
not used by the new submit path.
Signed-off-by: Mikko Perttunen
---
v3:
* runtime_get/put is now done directly from submit path, so no
callbacks are added
* Reworded.
---
drivers/gpu/drm/tegra/vic.c | 114 +---
1 file changed, 53 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c
index cb476da59adc..5d2ad125dca3 100644
--- a/drivers/gpu/drm/tegra/vic.c
+++ b/drivers/gpu/drm/tegra/vic.c
@@ -29,7 +29,6 @@ struct vic_config {
struct vic {
struct falcon falcon;
- bool booted;
void __iomem *regs;
struct tegra_drm_client client;
@@ -52,48 +51,6 @@ static void vic_writel(struct vic *vic, u32 value, unsigned
int offset)
writel(value, vic->regs + offset);
}
-static int vic_runtime_resume(struct device *dev)
-{
- struct vic *vic = dev_get_drvdata(dev);
- int err;
-
- err = clk_prepare_enable(vic->clk);
- if (err < 0)
- return err;
-
- usleep_range(10, 20);
-
- err = reset_control_deassert(vic->rst);
- if (err < 0)
- goto disable;
-
- usleep_range(10, 20);
-
- return 0;
-
-disable:
- clk_disable_unprepare(vic->clk);
- return err;
-}
-
-static int vic_runtime_suspend(struct device *dev)
-{
- struct vic *vic = dev_get_drvdata(dev);
- int err;
-
- err = reset_control_assert(vic->rst);
- if (err < 0)
- return err;
-
- usleep_range(2000, 4000);
-
- clk_disable_unprepare(vic->clk);
-
- vic->booted = false;
-
- return 0;
-}
-
static int vic_boot(struct vic *vic)
{
#ifdef CONFIG_IOMMU_API
@@ -103,9 +60,6 @@ static int vic_boot(struct vic *vic)
void *hdr;
int err = 0;
- if (vic->booted)
- return 0;
-
#ifdef CONFIG_IOMMU_API
if (vic->config->supports_sid && spec) {
u32 value;
@@ -153,8 +107,6 @@ static int vic_boot(struct vic *vic)
return err;
}
- vic->booted = true;
-
return 0;
}
@@ -308,35 +260,76 @@ static int vic_load_firmware(struct vic *vic)
return err;
}
-static int vic_open_channel(struct tegra_drm_client *client,
- struct tegra_drm_context *context)
+
+static int vic_runtime_resume(struct device *dev)
{
- struct vic *vic = to_vic(client);
+ struct vic *vic = dev_get_drvdata(dev);
int err;
- err = pm_runtime_get_sync(vic->dev);
+ err = clk_prepare_enable(vic->clk);
if (err < 0)
return err;
+ usleep_range(10, 20);
+
+ err = reset_control_deassert(vic->rst);
+ if (err < 0)
+ goto disable;
+
+ usleep_range(10, 20);
+
err = vic_load_firmware(vic);
if (err < 0)
- goto rpm_put;
+ goto assert;
err = vic_boot(vic);
if (err < 0)
- goto rpm_put;
+ goto assert;
+
+ return 0;
+
+assert:
+ reset_control_assert(vic->rst);
+disable:
+ clk_disable_unprepare(vic->clk);
+ return err;
+}
+
+static int vic_runtime_suspend(struct device *dev)
+{
+ struct vic *vic = dev_get_drvdata(dev);
+ int err;
+
+ err = reset_control_assert(vic->rst);
+ if (err < 0)
+ return err;
+
+ usleep_range(2000, 4000);
+
+ clk_disable_unprepare(vic->clk);
+
+ return 0;
+}
+
+static int vic_open_channel(struct tegra_drm_client *client,
+ struct tegra_drm_context *context)
+{
+ struct vic *vic = to_vic(client);
+ int err;
+
+ err = pm_runtime_get_sync(vic->dev);
+ if (err < 0) {
+ pm_runtime_put(vic->dev);
+ return err;
+ }
context->channel = host1x_channel_get(vic->channel);
if (!context->channel) {
- err = -ENOMEM;
- goto rpm_put;
+ pm_runtime_put(vic->dev);
+ return -ENOMEM;
}
return 0;
-
-rpm_put:
- pm_runtime_put(vic->dev);
- return err;
}
static void vic_close_channel(struct tegra_drm_context *context)
@@ -344,7 +337,6 @@ static void vic_close_channel(struct tegra_drm_context
*context)
struct vic *vic = to_vic(context->client);
host1x_channel_put(context->channel);
-
pm_runtime_put(vic->dev);
}
--
2.30.0
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[PATCH v5 01/21] gpu: host1x: Use different lock classes for each client
To avoid false lockdep warnings, give each client lock a different
lock class, passed from the initialization site by macro.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/bus.c | 7 ---
include/linux/host1x.h | 9 -
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/host1x/bus.c b/drivers/gpu/host1x/bus.c
index 347fb962b6c9..8fc79e9cb652 100644
--- a/drivers/gpu/host1x/bus.c
+++ b/drivers/gpu/host1x/bus.c
@@ -715,13 +715,14 @@ EXPORT_SYMBOL(host1x_driver_unregister);
* device and call host1x_device_init(), which will in turn call each client's
* &host1x_client_ops.init implementation.
*/
-int host1x_client_register(struct host1x_client *client)
+int __host1x_client_register(struct host1x_client *client,
+ struct lock_class_key *key)
{
struct host1x *host1x;
int err;
INIT_LIST_HEAD(&client->list);
- mutex_init(&client->lock);
+ __mutex_init(&client->lock, "host1x client lock", key);
client->usecount = 0;
mutex_lock(&devices_lock);
@@ -742,7 +743,7 @@ int host1x_client_register(struct host1x_client *client)
return 0;
}
-EXPORT_SYMBOL(host1x_client_register);
+EXPORT_SYMBOL(__host1x_client_register);
/**
* host1x_client_unregister() - unregister a host1x client
diff --git a/include/linux/host1x.h b/include/linux/host1x.h
index ce59a6a6a008..9eb77c87a83b 100644
--- a/include/linux/host1x.h
+++ b/include/linux/host1x.h
@@ -320,7 +320,14 @@ static inline struct host1x_device
*to_host1x_device(struct device *dev)
int host1x_device_init(struct host1x_device *device);
int host1x_device_exit(struct host1x_device *device);
-int host1x_client_register(struct host1x_client *client);
+int __host1x_client_register(struct host1x_client *client,
+struct lock_class_key *key);
+#define host1x_client_register(class) \
+ ({ \
+ static struct lock_class_key __key; \
+ __host1x_client_register(class, &__key); \
+ })
+
int host1x_client_unregister(struct host1x_client *client);
int host1x_client_suspend(struct host1x_client *client);
--
2.30.0
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[PATCH v5 21/21] drm/tegra: Add job firewall
Add a firewall that validates jobs before submission to ensure
they don't do anything they aren't allowed to do, like accessing
memory they should not access.
The firewall is functionality-wise a copy of the firewall already
implemented in gpu/host1x. It is copied here as it makes more
sense for it to live on the DRM side, as it is only needed for
userspace job submissions, and generally the data it needs to
do its job is easier to access here.
In the future, the other implementation will be removed.
Signed-off-by: Mikko Perttunen
---
v5:
* Support SETCLASS opcode
v3:
* New patch
---
drivers/gpu/drm/tegra/Makefile| 1 +
drivers/gpu/drm/tegra/uapi/firewall.c | 221 ++
drivers/gpu/drm/tegra/uapi/submit.c | 14 +-
drivers/gpu/drm/tegra/uapi/submit.h | 4 +
4 files changed, 237 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/tegra/uapi/firewall.c
diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile
index 059322e88943..4e3295f436f1 100644
--- a/drivers/gpu/drm/tegra/Makefile
+++ b/drivers/gpu/drm/tegra/Makefile
@@ -5,6 +5,7 @@ tegra-drm-y := \
drm.o \
uapi/uapi.o \
uapi/submit.o \
+ uapi/firewall.o \
uapi/gather_bo.o \
gem.o \
fb.o \
diff --git a/drivers/gpu/drm/tegra/uapi/firewall.c
b/drivers/gpu/drm/tegra/uapi/firewall.c
new file mode 100644
index ..57427c2d23fa
--- /dev/null
+++ b/drivers/gpu/drm/tegra/uapi/firewall.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2010-2020 NVIDIA Corporation */
+
+#include "../drm.h"
+#include "../uapi.h"
+
+#include "submit.h"
+
+struct tegra_drm_firewall {
+ struct tegra_drm_submit_data *submit;
+ struct tegra_drm_client *client;
+ u32 *data;
+ u32 pos;
+ u32 end;
+ u32 class;
+};
+
+static int fw_next(struct tegra_drm_firewall *fw, u32 *word)
+{
+ if (fw->pos == fw->end)
+ return -EINVAL;
+
+ *word = fw->data[fw->pos++];
+
+ return 0;
+}
+
+static bool fw_check_addr_valid(struct tegra_drm_firewall *fw, u32 offset)
+{
+ u32 i;
+
+ for (i = 0; i < fw->submit->num_used_mappings; i++) {
+ struct tegra_drm_mapping *m =
fw->submit->used_mappings[i].mapping;
+
+ if (offset >= m->iova && offset <= m->iova_end)
+ return true;
+ }
+
+ return false;
+}
+
+static int fw_check_reg(struct tegra_drm_firewall *fw, u32 offset)
+{
+ bool is_addr;
+ u32 word;
+ int err;
+
+ err = fw_next(fw, &word);
+ if (err)
+ return err;
+
+ if (!fw->client->ops->is_addr_reg)
+ return 0;
+
+ is_addr = fw->client->ops->is_addr_reg(fw->client->base.dev, fw->class,
+ offset);
+
+ if (!is_addr)
+ return 0;
+
+ if (!fw_check_addr_valid(fw, word))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int fw_check_regs_seq(struct tegra_drm_firewall *fw, u32 offset,
+u32 count, bool incr)
+{
+ u32 i;
+
+ for (i = 0; i < count; i++) {
+ if (fw_check_reg(fw, offset))
+ return -EINVAL;
+
+ if (incr)
+ offset++;
+ }
+
+ return 0;
+}
+
+static int fw_check_regs_mask(struct tegra_drm_firewall *fw, u32 offset,
+ u16 mask)
+{
+ unsigned long bmask = mask;
+ unsigned int bit;
+
+ for_each_set_bit(bit, &bmask, 16) {
+ if (fw_check_reg(fw, offset+bit))
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int fw_check_regs_imm(struct tegra_drm_firewall *fw, u32 offset)
+{
+ bool is_addr;
+
+ is_addr = fw->client->ops->is_addr_reg(fw->client->base.dev, fw->class,
+ offset);
+ if (is_addr)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int fw_check_class(struct tegra_drm_firewall *fw, u32 class)
+{
+ if (!fw->client->ops->is_valid_class)
+ return -EINVAL;
+
+ if (!fw->client->ops->is_valid_class(class))
+ return -EINVAL;
+
+ return 0;
+}
+
+enum {
+HOST1X_OPCODE_SETCLASS = 0x00,
+HOST1X_OPCODE_INCR = 0x01,
+HOST1X_OPCODE_NONINCR = 0x02,
+HOST1X_OPCODE_MASK = 0x03,
+HOST1X_OPCODE_IMM = 0x04,
+HOST1X_OPCODE_RESTART = 0x05,
+HOST1X_OPCODE_GATHER= 0x06,
+HOST1X_OPCODE_SETSTRMID = 0x07,
+HOST1X_OPCODE_SETAPPID = 0x08,
+HOST1X_OPCODE_SETPYLD = 0x09,
+HOST1X_OPCODE_INCR_W= 0x0a,
+HOST1X_OPCODE_NONINCR_W = 0x0b,
+HOST1X_OPCODE_GATHER_W = 0x0c,
+HOST1X_OPCODE_RESTART_W = 0x0d,
+HOST1X_OPCODE_EXTEND= 0x0e,
+};
+
+int tegra_drm_fw_validate(struct tegra_drm_client *client, u3
[PATCH v5 18/21] drm/tegra: Allocate per-engine channel in core code
To avoid duplication, allocate the per-engine shared channel in the
core code instead. Once MLOCKs are implemented on Host1x side, we
can also update this to avoid allocating a shared channel when
MLOCKs are enabled.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/drm/tegra/drm.c | 11 +++
drivers/gpu/drm/tegra/drm.h | 4
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index cd81b52a9e06..afd3f143c5e0 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -880,6 +880,14 @@ static const struct drm_driver tegra_drm_driver = {
int tegra_drm_register_client(struct tegra_drm *tegra,
struct tegra_drm_client *client)
{
+ /*
+* When MLOCKs are implemented, change to allocate a shared channel
+* only when MLOCKs are disabled.
+*/
+ client->shared_channel = host1x_channel_request(&client->base);
+ if (!client->shared_channel)
+ return -EBUSY;
+
mutex_lock(&tegra->clients_lock);
list_add_tail(&client->list, &tegra->clients);
client->drm = tegra;
@@ -896,6 +904,9 @@ int tegra_drm_unregister_client(struct tegra_drm *tegra,
client->drm = NULL;
mutex_unlock(&tegra->clients_lock);
+ if (client->shared_channel)
+ host1x_channel_put(client->shared_channel);
+
return 0;
}
diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index f38de08e0c95..0f38f159aa8e 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -87,8 +87,12 @@ struct tegra_drm_client {
struct list_head list;
struct tegra_drm *drm;
+ /* Set by driver */
unsigned int version;
const struct tegra_drm_client_ops *ops;
+
+ /* Set by TegraDRM core */
+ struct host1x_channel *shared_channel;
};
static inline struct tegra_drm_client *
--
2.30.0
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[PATCH v5 03/21] gpu: host1x: Show number of pending waiters in debugfs
Show the number of pending waiters in the debugfs status file.
This is useful for testing to verify that waiters do not leak
or accumulate incorrectly.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/debug.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/host1x/debug.c b/drivers/gpu/host1x/debug.c
index 1b4997bda1c7..8a14880c61bb 100644
--- a/drivers/gpu/host1x/debug.c
+++ b/drivers/gpu/host1x/debug.c
@@ -69,6 +69,7 @@ static int show_channel(struct host1x_channel *ch, void
*data, bool show_fifo)
static void show_syncpts(struct host1x *m, struct output *o)
{
+ struct list_head *pos;
unsigned int i;
host1x_debug_output(o, " syncpts \n");
@@ -76,12 +77,19 @@ static void show_syncpts(struct host1x *m, struct output *o)
for (i = 0; i < host1x_syncpt_nb_pts(m); i++) {
u32 max = host1x_syncpt_read_max(m->syncpt + i);
u32 min = host1x_syncpt_load(m->syncpt + i);
+ unsigned int waiters = 0;
- if (!min && !max)
+ spin_lock(&m->syncpt[i].intr.lock);
+ list_for_each(pos, &m->syncpt[i].intr.wait_head)
+ waiters++;
+ spin_unlock(&m->syncpt[i].intr.lock);
+
+ if (!min && !max && !waiters)
continue;
- host1x_debug_output(o, "id %u (%s) min %d max %d\n",
- i, m->syncpt[i].name, min, max);
+ host1x_debug_output(o,
+ "id %u (%s) min %d max %d (%d waiters)\n",
+ i, m->syncpt[i].name, min, max, waiters);
}
for (i = 0; i < host1x_syncpt_nb_bases(m); i++) {
--
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[PATCH v5 17/21] drm/tegra: Set resv fields when importing/exporting GEMs
To allow sharing of implicit fences when exporting/importing dma_buf objects, set the 'resv' fields when importing or exporting GEM objects. Signed-off-by: Mikko Perttunen --- drivers/gpu/drm/tegra/gem.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/tegra/gem.c b/drivers/gpu/drm/tegra/gem.c index 26af8daa9a16..731e6bdc01b4 100644 --- a/drivers/gpu/drm/tegra/gem.c +++ b/drivers/gpu/drm/tegra/gem.c @@ -431,6 +431,7 @@ static struct tegra_bo *tegra_bo_import(struct drm_device *drm, } bo->gem.import_attach = attach; + bo->gem.resv = buf->resv; return bo; @@ -683,6 +684,7 @@ struct dma_buf *tegra_gem_prime_export(struct drm_gem_object *gem, exp_info.size = gem->size; exp_info.flags = flags; exp_info.priv = gem; + exp_info.resv = gem->resv; return drm_gem_dmabuf_export(gem->dev, &exp_info); } -- 2.30.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 12/21] gpu: host1x: Add support for syncpoint waits in CDMA pushbuffer
Add support for inserting syncpoint waits in the CDMA pushbuffer.
These waits need to be done in HOST1X class, while gather submitted
by the application execute in engine class.
Support is added by converting the gather list of job into a command
list that can include both gathers and waits. When the job is
submitted, these commands are pushed as the appropriate opcodes
on the CDMA pushbuffer.
Signed-off-by: Mikko Perttunen
---
drivers/gpu/host1x/hw/channel_hw.c | 51 +++
drivers/gpu/host1x/hw/debug_hw.c | 9 +++-
drivers/gpu/host1x/job.c | 67 +-
drivers/gpu/host1x/job.h | 14 +++
include/linux/host1x.h | 5 ++-
5 files changed, 105 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/host1x/hw/channel_hw.c
b/drivers/gpu/host1x/hw/channel_hw.c
index bf21512e5078..d88a32f73f5e 100644
--- a/drivers/gpu/host1x/hw/channel_hw.c
+++ b/drivers/gpu/host1x/hw/channel_hw.c
@@ -55,31 +55,46 @@ static void submit_gathers(struct host1x_job *job)
#endif
unsigned int i;
- for (i = 0; i < job->num_gathers; i++) {
- struct host1x_job_gather *g = &job->gathers[i];
- dma_addr_t addr = g->base + g->offset;
- u32 op2, op3;
+ for (i = 0; i < job->num_cmds; i++) {
+ struct host1x_job_cmd *cmd = &job->cmds[i];
- op2 = lower_32_bits(addr);
- op3 = upper_32_bits(addr);
+ if (cmd->is_wait) {
+ /* TODO use modern wait */
+ host1x_cdma_push(cdma,
+host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
+ host1x_uclass_wait_syncpt_r(), 1),
+host1x_class_host_wait_syncpt(cmd->wait.id,
+ cmd->wait.threshold));
+ host1x_cdma_push(
+ cdma, host1x_opcode_setclass(job->class, 0, 0),
+ HOST1X_OPCODE_NOP);
+ } else {
+ struct host1x_job_gather *g = &cmd->gather;
- trace_write_gather(cdma, g->bo, g->offset, g->words);
+ dma_addr_t addr = g->base + g->offset;
+ u32 op2, op3;
- if (op3 != 0) {
+ op2 = lower_32_bits(addr);
+ op3 = upper_32_bits(addr);
+
+ trace_write_gather(cdma, g->bo, g->offset, g->words);
+
+ if (op3 != 0) {
#if HOST1X_HW >= 6
- u32 op1 = host1x_opcode_gather_wide(g->words);
- u32 op4 = HOST1X_OPCODE_NOP;
+ u32 op1 = host1x_opcode_gather_wide(g->words);
+ u32 op4 = HOST1X_OPCODE_NOP;
- host1x_cdma_push_wide(cdma, op1, op2, op3, op4);
+ host1x_cdma_push_wide(cdma, op1, op2, op3, op4);
#else
- dev_err(dev, "invalid gather for push buffer %pad\n",
- &addr);
- continue;
+ dev_err(dev, "invalid gather for push buffer
%pad\n",
+ &addr);
+ continue;
#endif
- } else {
- u32 op1 = host1x_opcode_gather(g->words);
+ } else {
+ u32 op1 = host1x_opcode_gather(g->words);
- host1x_cdma_push(cdma, op1, op2);
+ host1x_cdma_push(cdma, op1, op2);
+ }
}
}
}
@@ -126,7 +141,7 @@ static int channel_submit(struct host1x_job *job)
struct host1x *host = dev_get_drvdata(ch->dev->parent);
trace_host1x_channel_submit(dev_name(ch->dev),
- job->num_gathers, job->num_relocs,
+ job->num_cmds, job->num_relocs,
job->syncpt->id, job->syncpt_incrs);
/* before error checks, return current max */
diff --git a/drivers/gpu/host1x/hw/debug_hw.c b/drivers/gpu/host1x/hw/debug_hw.c
index ceb48229d14b..35952fd5597e 100644
--- a/drivers/gpu/host1x/hw/debug_hw.c
+++ b/drivers/gpu/host1x/hw/debug_hw.c
@@ -208,10 +208,15 @@ static void show_channel_gathers(struct output *o, struct
host1x_cdma *cdma)
job->first_get, job->timeout,
job->num_slots, job->num_unpins);
- for (i = 0; i < job->num_gathers; i++) {
- struct host1x_job_gather *g = &job->gathers[i];
+ for (i = 0; i < job->num_cmds; i++) {
+ struct host1x_job_gather *g;
u32 *mapped;
+ if (job->cmds[i].is_wait)
+
[PATCH v5 13/21] gpu: host1x: Reset max value when freeing a syncpoint
With job recovery becoming optional, syncpoints may have a mismatch
between their value and max value when freed. As such, when freeing,
set the max value to the current value of the syncpoint so that it
is in a sane state for the next user.
Signed-off-by: Mikko Perttunen
---
v3:
* Use host1x_syncpt_read instead of read_min to ensure syncpoint
value is current.
---
drivers/gpu/host1x/syncpt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/host1x/syncpt.c b/drivers/gpu/host1x/syncpt.c
index 81315cd1a3ed..9c39f5bfc70c 100644
--- a/drivers/gpu/host1x/syncpt.c
+++ b/drivers/gpu/host1x/syncpt.c
@@ -385,6 +385,7 @@ static void syncpt_release(struct kref *ref)
{
struct host1x_syncpt *sp = container_of(ref, struct host1x_syncpt, ref);
+ atomic_set(&sp->max_val, host1x_syncpt_read(sp));
sp->locked = false;
mutex_lock(&sp->host->syncpt_mutex);
--
2.30.0
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[PATCH v5 07/21] gpu: host1x: Introduce UAPI header
Add the userspace interface header, specifying interfaces
for allocating and accessing syncpoints from userspace,
and for creating sync_file based fences based on syncpoint
thresholds.
Signed-off-by: Mikko Perttunen
---
include/uapi/linux/host1x.h | 134
1 file changed, 134 insertions(+)
create mode 100644 include/uapi/linux/host1x.h
diff --git a/include/uapi/linux/host1x.h b/include/uapi/linux/host1x.h
new file mode 100644
index ..9c8fb9425cb2
--- /dev/null
+++ b/include/uapi/linux/host1x.h
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/* Copyright (c) 2020 NVIDIA Corporation */
+
+#ifndef _UAPI__LINUX_HOST1X_H
+#define _UAPI__LINUX_HOST1X_H
+
+#include
+#include
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+struct host1x_allocate_syncpoint {
+ /**
+* @fd: [out]
+*
+* New file descriptor representing the allocated syncpoint.
+*/
+ __s32 fd;
+
+ __u32 reserved[3];
+};
+
+struct host1x_syncpoint_info {
+ /**
+* @id: [out]
+*
+* System-global ID of the syncpoint.
+*/
+ __u32 id;
+
+ __u32 reserved[3];
+};
+
+struct host1x_syncpoint_increment {
+ /**
+* @count: [in]
+*
+* Number of times to increment the syncpoint. The syncpoint can
+* be observed at in-between values, but each increment is atomic.
+*/
+ __u32 count;
+};
+
+struct host1x_read_syncpoint {
+ /**
+* @id: [in]
+*
+* ID of the syncpoint to read.
+*/
+ __u32 id;
+
+ /**
+* @value: [out]
+*
+* Current value of the syncpoint.
+*/
+ __u32 value;
+};
+
+struct host1x_create_fence {
+ /**
+* @id: [in]
+*
+* ID of the syncpoint to create a fence for.
+*/
+ __u32 id;
+
+ /**
+* @threshold: [in]
+*
+* When the syncpoint reaches this value, the fence will be signaled.
+* The syncpoint is considered to have reached the threshold when the
+* following condition is true:
+*
+* ((value - threshold) & 0x8000U) == 0U
+*
+*/
+ __u32 threshold;
+
+ /**
+* @fence_fd: [out]
+*
+* New sync_file file descriptor containing the created fence.
+*/
+ __s32 fence_fd;
+
+ __u32 reserved[1];
+};
+
+struct host1x_fence_extract_fence {
+ __u32 id;
+ __u32 threshold;
+};
+
+struct host1x_fence_extract {
+ /**
+* @fence_fd: [in]
+*
+* sync_file file descriptor
+*/
+ __s32 fence_fd;
+
+ /**
+* @num_fences: [in,out]
+*
+* In: size of the `fences_ptr` array counted in elements.
+* Out: required size of the `fences_ptr` array counted in elements.
+*/
+ __u32 num_fences;
+
+ /**
+* @fences_ptr: [in]
+*
+* Pointer to array of `struct host1x_fence_extract_fence`.
+*/
+ __u64 fences_ptr;
+
+ __u32 reserved[2];
+};
+
+#define HOST1X_IOCTL_ALLOCATE_SYNCPOINT _IOWR('X', 0x00, struct
host1x_allocate_syncpoint)
+#define HOST1X_IOCTL_READ_SYNCPOINT _IOR ('X', 0x01, struct
host1x_read_syncpoint)
+#define HOST1X_IOCTL_CREATE_FENCE_IOWR('X', 0x02, struct
host1x_create_fence)
+#define HOST1X_IOCTL_SYNCPOINT_INFO _IOWR('X', 0x03, struct
host1x_syncpoint_info)
+#define HOST1X_IOCTL_SYNCPOINT_INCREMENT _IOWR('X', 0x04, struct
host1x_syncpoint_increment)
+#define HOST1X_IOCTL_FENCE_EXTRACT _IOWR('X', 0x05, struct
host1x_fence_extract)
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
--
2.30.0
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[PATCH v5 06/21] gpu: host1x: Cleanup and refcounting for syncpoints
Add reference counting for allocated syncpoints to allow keeping
them allocated while jobs are referencing them. Additionally,
clean up various places using syncpoint IDs to use host1x_syncpt
pointers instead.
Signed-off-by: Mikko Perttunen
---
v5:
- Remove host1x_syncpt_put in submit code, as job_put already
puts the syncpoint.
- Changes due to rebase in VI driver.
v4:
- Update from _free to _put in VI driver as well
---
drivers/gpu/drm/tegra/dc.c | 4 +-
drivers/gpu/drm/tegra/drm.c| 14 ++---
drivers/gpu/drm/tegra/gr2d.c | 4 +-
drivers/gpu/drm/tegra/gr3d.c | 4 +-
drivers/gpu/drm/tegra/vic.c| 4 +-
drivers/gpu/host1x/cdma.c | 11 ++--
drivers/gpu/host1x/dev.h | 7 ++-
drivers/gpu/host1x/hw/cdma_hw.c| 2 +-
drivers/gpu/host1x/hw/channel_hw.c | 10 ++--
drivers/gpu/host1x/hw/debug_hw.c | 2 +-
drivers/gpu/host1x/job.c | 5 +-
drivers/gpu/host1x/syncpt.c| 75 +++---
drivers/gpu/host1x/syncpt.h| 3 ++
drivers/staging/media/tegra-video/vi.c | 4 +-
include/linux/host1x.h | 8 +--
15 files changed, 98 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 85dd7131553a..033032dfc4b9 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -2129,7 +2129,7 @@ static int tegra_dc_init(struct host1x_client *client)
drm_plane_cleanup(primary);
host1x_client_iommu_detach(client);
- host1x_syncpt_free(dc->syncpt);
+ host1x_syncpt_put(dc->syncpt);
return err;
}
@@ -2154,7 +2154,7 @@ static int tegra_dc_exit(struct host1x_client *client)
}
host1x_client_iommu_detach(client);
- host1x_syncpt_free(dc->syncpt);
+ host1x_syncpt_put(dc->syncpt);
return 0;
}
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index e45c8414e2a3..5a6037eff37f 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -171,7 +171,7 @@ int tegra_drm_submit(struct tegra_drm_context *context,
struct drm_tegra_syncpt syncpt;
struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
struct drm_gem_object **refs;
- struct host1x_syncpt *sp;
+ struct host1x_syncpt *sp = NULL;
struct host1x_job *job;
unsigned int num_refs;
int err;
@@ -298,8 +298,8 @@ int tegra_drm_submit(struct tegra_drm_context *context,
goto fail;
}
- /* check whether syncpoint ID is valid */
- sp = host1x_syncpt_get(host1x, syncpt.id);
+ /* Syncpoint ref will be dropped on job release. */
+ sp = host1x_syncpt_get_by_id(host1x, syncpt.id);
if (!sp) {
err = -ENOENT;
goto fail;
@@ -308,7 +308,7 @@ int tegra_drm_submit(struct tegra_drm_context *context,
job->is_addr_reg = context->client->ops->is_addr_reg;
job->is_valid_class = context->client->ops->is_valid_class;
job->syncpt_incrs = syncpt.incrs;
- job->syncpt_id = syncpt.id;
+ job->syncpt = sp;
job->timeout = 1;
if (args->timeout && args->timeout < 1)
@@ -380,7 +380,7 @@ static int tegra_syncpt_read(struct drm_device *drm, void
*data,
struct drm_tegra_syncpt_read *args = data;
struct host1x_syncpt *sp;
- sp = host1x_syncpt_get(host, args->id);
+ sp = host1x_syncpt_get_by_id_noref(host, args->id);
if (!sp)
return -EINVAL;
@@ -395,7 +395,7 @@ static int tegra_syncpt_incr(struct drm_device *drm, void
*data,
struct drm_tegra_syncpt_incr *args = data;
struct host1x_syncpt *sp;
- sp = host1x_syncpt_get(host1x, args->id);
+ sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
if (!sp)
return -EINVAL;
@@ -409,7 +409,7 @@ static int tegra_syncpt_wait(struct drm_device *drm, void
*data,
struct drm_tegra_syncpt_wait *args = data;
struct host1x_syncpt *sp;
- sp = host1x_syncpt_get(host1x, args->id);
+ sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
if (!sp)
return -EINVAL;
diff --git a/drivers/gpu/drm/tegra/gr2d.c b/drivers/gpu/drm/tegra/gr2d.c
index 1a0d3ba6e525..d857a99b21a7 100644
--- a/drivers/gpu/drm/tegra/gr2d.c
+++ b/drivers/gpu/drm/tegra/gr2d.c
@@ -67,7 +67,7 @@ static int gr2d_init(struct host1x_client *client)
detach:
host1x_client_iommu_detach(client);
free:
- host1x_syncpt_free(client->syncpts[0]);
+ host1x_syncpt_put(client->syncpts[0]);
put:
host1x_channel_put(gr2d->channel);
return err;
@@ -86,7 +86,7 @@ static int gr2d_exit(struct host1x_client *client)
return err;
host1x_client_iommu_detach(client);
- host1x_syncpt_free(client->syncpts[0]);
+ host1x_syncpt_put(client->syncpts[0]);
[PATCH v5 08/21] gpu: host1x: Implement /dev/host1x device node
Add the /dev/host1x device node, implementing the following
functionality:
- Reading syncpoint values
- Allocating syncpoints (providing syncpoint FDs)
- Incrementing syncpoints (based on syncpoint FD)
Signed-off-by: Mikko Perttunen
---
v4:
* Put UAPI under CONFIG_DRM_TEGRA_STAGING
v3:
* Pass process name as syncpoint name when allocating
syncpoint.
---
drivers/gpu/host1x/Makefile | 1 +
drivers/gpu/host1x/dev.c| 9 ++
drivers/gpu/host1x/dev.h| 3 +
drivers/gpu/host1x/uapi.c | 282
drivers/gpu/host1x/uapi.h | 22 +++
include/linux/host1x.h | 2 +
6 files changed, 319 insertions(+)
create mode 100644 drivers/gpu/host1x/uapi.c
create mode 100644 drivers/gpu/host1x/uapi.h
diff --git a/drivers/gpu/host1x/Makefile b/drivers/gpu/host1x/Makefile
index 096017b8789d..882f928d75e1 100644
--- a/drivers/gpu/host1x/Makefile
+++ b/drivers/gpu/host1x/Makefile
@@ -9,6 +9,7 @@ host1x-y = \
job.o \
debug.o \
mipi.o \
+ uapi.o \
hw/host1x01.o \
hw/host1x02.o \
hw/host1x04.o \
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index d0ebb70e2fdd..641317d23828 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -461,6 +461,12 @@ static int host1x_probe(struct platform_device *pdev)
goto deinit_syncpt;
}
+ err = host1x_uapi_init(&host->uapi, host);
+ if (err) {
+ dev_err(&pdev->dev, "failed to initialize uapi\n");
+ goto deinit_intr;
+ }
+
host1x_debug_init(host);
if (host->info->has_hypervisor)
@@ -480,6 +486,8 @@ static int host1x_probe(struct platform_device *pdev)
host1x_unregister(host);
deinit_debugfs:
host1x_debug_deinit(host);
+ host1x_uapi_deinit(&host->uapi);
+deinit_intr:
host1x_intr_deinit(host);
deinit_syncpt:
host1x_syncpt_deinit(host);
@@ -501,6 +509,7 @@ static int host1x_remove(struct platform_device *pdev)
host1x_unregister(host);
host1x_debug_deinit(host);
+ host1x_uapi_deinit(&host->uapi);
host1x_intr_deinit(host);
host1x_syncpt_deinit(host);
reset_control_assert(host->rst);
diff --git a/drivers/gpu/host1x/dev.h b/drivers/gpu/host1x/dev.h
index 63010ae37a97..7b8b7e20e32b 100644
--- a/drivers/gpu/host1x/dev.h
+++ b/drivers/gpu/host1x/dev.h
@@ -17,6 +17,7 @@
#include "intr.h"
#include "job.h"
#include "syncpt.h"
+#include "uapi.h"
struct host1x_syncpt;
struct host1x_syncpt_base;
@@ -143,6 +144,8 @@ struct host1x {
struct list_head list;
struct device_dma_parameters dma_parms;
+
+ struct host1x_uapi uapi;
};
void host1x_hypervisor_writel(struct host1x *host1x, u32 r, u32 v);
diff --git a/drivers/gpu/host1x/uapi.c b/drivers/gpu/host1x/uapi.c
new file mode 100644
index ..27b8761c3f35
--- /dev/null
+++ b/drivers/gpu/host1x/uapi.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * /dev/host1x syncpoint interface
+ *
+ * Copyright (c) 2020, NVIDIA Corporation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dev.h"
+#include "syncpt.h"
+#include "uapi.h"
+
+#include
+
+static int syncpt_file_release(struct inode *inode, struct file *file)
+{
+ struct host1x_syncpt *sp = file->private_data;
+
+ host1x_syncpt_put(sp);
+
+ return 0;
+}
+
+static int syncpt_file_ioctl_info(struct host1x_syncpt *sp, void __user *data)
+{
+ struct host1x_syncpoint_info args;
+ unsigned long copy_err;
+
+ copy_err = copy_from_user(&args, data, sizeof(args));
+ if (copy_err)
+ return -EFAULT;
+
+ if (args.reserved[0] || args.reserved[1] || args.reserved[2])
+ return -EINVAL;
+
+ args.id = sp->id;
+
+ copy_err = copy_to_user(data, &args, sizeof(args));
+ if (copy_err)
+ return -EFAULT;
+
+ return 0;
+}
+
+static int syncpt_file_ioctl_incr(struct host1x_syncpt *sp, void __user *data)
+{
+ struct host1x_syncpoint_increment args;
+ unsigned long copy_err;
+ u32 i;
+
+ copy_err = copy_from_user(&args, data, sizeof(args));
+ if (copy_err)
+ return -EFAULT;
+
+ for (i = 0; i < args.count; i++) {
+ host1x_syncpt_incr(sp);
+ if (signal_pending(current))
+ return -EINTR;
+ }
+
+ return 0;
+}
+
+static long syncpt_file_ioctl(struct file *file, unsigned int cmd,
+ unsigned long arg)
+{
+ void __user *data = (void __user *)arg;
+ long err;
+
+ switch (cmd) {
+ case HOST1X_IOCTL_SYNCPOINT_INFO:
+ err = syncpt_file_ioctl_info(file->private_data, data);
+ break;
+
+ case HOST1X_IOCTL_SYNCPOINT_INCREMENT:
+ err = syncpt_file_ioctl_incr(file->private_data, data);
+ break;
+
+ default:
+
[PATCH] drm/bridge: nwl-dsi: Avoid potential multiplication overflow on 32-bit
As nwl_dsi.lanes is u32, and NSEC_PER_SEC is 10L, the second multiplication in dsi->lanes * 8 * NSEC_PER_SEC will overflow on a 32-bit platform. Fix this by making the constant unsigned long long, forcing 64-bit arithmetic. While iMX8 is arm64, this driver is currently used on 64-bit platforms only, where long is 64-bit, so this cannot happen. But the issue may start to happen when the driver is reused for a 32-bit SoC, or when code is copied for a new driver. Signed-off-by: Geert Uytterhoeven --- Compile-tested only. --- drivers/gpu/drm/bridge/nwl-dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c index 66b67402f1acd57d..a8da3081efdcc84e 100644 --- a/drivers/gpu/drm/bridge/nwl-dsi.c +++ b/drivers/gpu/drm/bridge/nwl-dsi.c @@ -195,7 +195,7 @@ static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps) u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp, - dsi->lanes * 8 * NSEC_PER_SEC); + dsi->lanes * 8ULL * NSEC_PER_SEC); } /* -- 2.25.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/fourcc: fix Amlogic format modifier masks
Hi,
On 10/01/2021 13:51, Simon Ser wrote:
> The comment says the layout and options use 8 bits, and the shift
> uses 8 bits. However the mask is 0xf, ie. 0b (4 bits).
>
> This could be surprising when introducing new layouts or options
> that take more than 4 bits, as this would silently drop the high
> bits.
Indeed, but the masks are "private", and would be updated accordingly when
introducing new layouts.
>
> Make the masks consistent with the comment and the shift.
>
> Found when writing a drm_info patch [1].
>
> [1]: https://github.com/ascent12/drm_info/pull/67
>
> Signed-off-by: Simon Ser
> Fixes: d6528ec88309 ("drm/fourcc: Add modifier definitions for describing
> Amlogic Video Framebuffer Compression")
> Cc: Neil Armstrong
> Cc: Sam Ravnborg
> Cc: Kevin Hilman
> Cc: Daniel Vetter
> ---
> include/uapi/drm/drm_fourcc.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 723c8e23ca87..5f42a14481bd 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -1036,9 +1036,9 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64
> modifier)
> * Not all combinations are valid, and different SoCs may support different
> * combinations of layout and options.
> */
> -#define __fourcc_mod_amlogic_layout_mask 0xf
> +#define __fourcc_mod_amlogic_layout_mask 0xff
> #define __fourcc_mod_amlogic_options_shift 8
> -#define __fourcc_mod_amlogic_options_mask 0xf
> +#define __fourcc_mod_amlogic_options_mask 0xff
>
> #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
> fourcc_mod_code(AMLOGIC, \
>
Anyway:
Acked-by: Neil Armstrong
Thanks,
Neil
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[PATCH] drm/ttm: make the pool shrinker lock a mutex
set_pages_wb() might sleep and so we can't do this in an atomic context.
Signed-off-by: Christian König
Reported-by: Mikhail Gavrilov
Fixes: d099fc8f540a ("drm/ttm: new TT backend allocation pool v3")
---
drivers/gpu/drm/ttm/ttm_pool.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c
index a00b7ab9c14c..6a6eeba423d1 100644
--- a/drivers/gpu/drm/ttm/ttm_pool.c
+++ b/drivers/gpu/drm/ttm/ttm_pool.c
@@ -66,7 +66,7 @@ static struct ttm_pool_type global_uncached[MAX_ORDER];
static struct ttm_pool_type global_dma32_write_combined[MAX_ORDER];
static struct ttm_pool_type global_dma32_uncached[MAX_ORDER];
-static spinlock_t shrinker_lock;
+static struct mutex shrinker_lock;
static struct list_head shrinker_list;
static struct shrinker mm_shrinker;
@@ -249,9 +249,9 @@ static void ttm_pool_type_init(struct ttm_pool_type *pt,
struct ttm_pool *pool,
spin_lock_init(&pt->lock);
INIT_LIST_HEAD(&pt->pages);
- spin_lock(&shrinker_lock);
+ mutex_lock(&shrinker_lock);
list_add_tail(&pt->shrinker_list, &shrinker_list);
- spin_unlock(&shrinker_lock);
+ mutex_unlock(&shrinker_lock);
}
/* Remove a pool_type from the global shrinker list and free all pages */
@@ -259,9 +259,9 @@ static void ttm_pool_type_fini(struct ttm_pool_type *pt)
{
struct page *p, *tmp;
- spin_lock(&shrinker_lock);
+ mutex_lock(&shrinker_lock);
list_del(&pt->shrinker_list);
- spin_unlock(&shrinker_lock);
+ mutex_unlock(&shrinker_lock);
list_for_each_entry_safe(p, tmp, &pt->pages, lru)
ttm_pool_free_page(pt->pool, pt->caching, pt->order, p);
@@ -302,7 +302,7 @@ static unsigned int ttm_pool_shrink(void)
unsigned int num_freed;
struct page *p;
- spin_lock(&shrinker_lock);
+ mutex_lock(&shrinker_lock);
pt = list_first_entry(&shrinker_list, typeof(*pt), shrinker_list);
p = ttm_pool_type_take(pt);
@@ -314,7 +314,7 @@ static unsigned int ttm_pool_shrink(void)
}
list_move_tail(&pt->shrinker_list, &shrinker_list);
- spin_unlock(&shrinker_lock);
+ mutex_unlock(&shrinker_lock);
return num_freed;
}
@@ -564,7 +564,7 @@ int ttm_pool_debugfs(struct ttm_pool *pool, struct seq_file
*m)
{
unsigned int i;
- spin_lock(&shrinker_lock);
+ mutex_lock(&shrinker_lock);
seq_puts(m, "\t ");
for (i = 0; i < MAX_ORDER; ++i)
@@ -600,7 +600,7 @@ int ttm_pool_debugfs(struct ttm_pool *pool, struct seq_file
*m)
seq_printf(m, "\ntotal\t: %8lu of %8lu\n",
atomic_long_read(&allocated_pages), page_pool_size);
- spin_unlock(&shrinker_lock);
+ mutex_unlock(&shrinker_lock);
return 0;
}
@@ -644,7 +644,7 @@ int ttm_pool_mgr_init(unsigned long num_pages)
if (!page_pool_size)
page_pool_size = num_pages;
- spin_lock_init(&shrinker_lock);
+ mutex_init(&shrinker_lock);
INIT_LIST_HEAD(&shrinker_list);
for (i = 0; i < MAX_ORDER; ++i) {
--
2.25.1
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Re: [drm:dm_plane_helper_prepare_fb [amdgpu]] *ERROR* Failed to pin framebuffer with error -12
Am 11.01.21 um 10:03 schrieb Christian König:
Hi Mikhail
Am 10.01.21 um 23:26 schrieb Mikhail Gavrilov:
Hi folks,
today I joined to testing Kernel 5.11 and saw that the kernel log was
flooded with BUG messages:
BUG: sleeping function called from invalid context at mm/vmalloc.c:1756
in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 266, name:
kswapd0
INFO: lockdep is turned off.
CPU: 15 PID: 266 Comm: kswapd0 Tainted: G W -
--- 5.11.0-0.rc2.20210108gitf5e6c330254a.119.fc34.x86_64 #1
Hardware name: System manufacturer System Product Name/ROG STRIX
X570-I GAMING, BIOS 2802 10/21/2020
Call Trace:
dump_stack+0x8b/0xb0
___might_sleep.cold+0xb6/0xc6
vm_unmap_aliases+0x21/0x40
change_page_attr_set_clr+0x9e/0x190
set_memory_wb+0x2f/0x80
ttm_pool_free_page+0x28/0x90 [ttm]
ttm_pool_shrink+0x45/0xb0 [ttm]
ttm_pool_shrinker_scan+0xa/0x20 [ttm]
do_shrink_slab+0x177/0x3a0
shrink_slab+0x9c/0x290
shrink_node+0x2e6/0x700
balance_pgdat+0x2f5/0x650
kswapd+0x21d/0x4d0
? do_wait_intr_irq+0xd0/0xd0
? balance_pgdat+0x650/0x650
kthread+0x13a/0x150
? __kthread_bind_mask+0x60/0x60
ret_from_fork+0x22/0x30
I'm probably responsible for this. Need to double check why we try to
allocate memory while freeing some.
Changing the page table attributes while releasing memory might sleep.
So we can't use a spinlock here.
Thanks for the report, a patch to fix this is on the mailing list now.
But the most unpleasant thing is that after a while the monitor turns
off and does not go on again until the restart.
This is accompanied by an entry in the kernel log:
amdgpu :0b:00.0: amdgpu: ff7d8b94 pin failed
[drm:dm_plane_helper_prepare_fb [amdgpu]] *ERROR* Failed to pin
framebuffer with error -12
-12 is just -ENOMEM. Looks like a memory leak to me, maybe caused by
the problem above, maybe something completely unrelated.
I will take a look.
The looks like a completely unrelated memory leak to me.
Probably best if you open up a bug report for this.
Thanks,
Christian.
Thanks,
Christian.
$ grep "Failed to pin framebuffer with error" -Rn .
./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:5816:
DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
$ git blame -L 5811,5821
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
Blaming lines: 0% (11/9167), done.
5d43be0ccbc2f (Christian König 2017-10-26 18:06:23 +0200 5811)
domain = AMDGPU_GEM_DOMAIN_VRAM;
e7b07ceef2a65 (Harry Wentland 2017-08-10 13:29:07 -0400 5812)
7b7c6c81b3a37 (Junwei Zhang 2018-06-25 12:51:14 +0800 5813) r =
amdgpu_bo_pin(rbo, domain);
e7b07ceef2a65 (Harry Wentland 2017-08-10 13:29:07 -0400 5814) if
(unlikely(r != 0)) {
30b7c6147d18d (Harry Wentland 2017-10-26 15:35:14 -0400 5815)
if (r != -ERESTARTSYS)
30b7c6147d18d (Harry Wentland 2017-10-26 15:35:14 -0400 5816)
DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
0f257b09531b4 (Chunming Zhou 2019-05-07 19:45:31 +0800 5817)
ttm_eu_backoff_reservation(&ticket, &list);
e7b07ceef2a65 (Harry Wentland 2017-08-10 13:29:07 -0400 5818)
return r;
e7b07ceef2a65 (Harry Wentland 2017-08-10 13:29:07 -0400 5819) }
e7b07ceef2a65 (Harry Wentland 2017-08-10 13:29:07 -0400 5820)
bb812f1ea87dd (Junwei Zhang 2018-06-25 13:32:24 +0800 5821) r =
amdgpu_ttm_alloc_gart(&rbo->tbo);
Who knows how to fix it?
Full kernel logs is here:
[1]
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpastebin.com%2FfLasjDHX&data=04%7C01%7Cchristian.koenig%40amd.com%7C15ef83e462e049429be208d8b5b6c6bb%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637459143942981908%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Uj9Ob3lUCAsH8NrxC715zSfl5Yqc44ySVo%2FZkdyTpCM%3D&reserved=0
[2]
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpastebin.com%2Fg3wR2r9e&data=04%7C01%7Cchristian.koenig%40amd.com%7C15ef83e462e049429be208d8b5b6c6bb%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637459143942981908%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=u8irMU3i8c37W5SkyiaAi%2FtwMoPorezm3NI1EYI3csE%3D&reserved=0
--
Best Regards,
Mike Gavrilov.
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[PATCH v2] drm/i915: selftest_lrc: Fix error code in live_preempt_user()
This error path should return a negative error code instead of success.
Fixes: c92724de6db1 ("drm/i915/selftests: Try to detect rollback during
batchbuffer preemption")
Signed-off-by: Dan Carpenter
Reviewed-by: Chris Wilson
---
v2: The first version of the patch fixed some other error paths but
those have already been fixed.
drivers/gpu/drm/i915/gt/selftest_lrc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 95d41c01d0e0..e11d6bb26e86 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -3264,8 +3264,10 @@ static int live_preempt_user(void *arg)
rq = create_gpr_client(engine, global,
NUM_GPR * i * sizeof(u32));
- if (IS_ERR(rq))
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
goto end_test;
+ }
client[i] = rq;
}
--
2.29.2
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Re: [PATCH v2] drm: Check actual format for legacy pageflip.
On Sat, Jan 9, 2021 at 9:11 PM Bas Nieuwenhuizen
wrote:
>
> With modifiers one can actually have different format_info structs
> for the same format, which now matters for AMDGPU since we convert
> implicit modifiers to explicit modifiers with multiple planes.
>
> I checked other drivers and it doesn't look like they end up triggering
> this case so I think this is safe to relax.
>
> Signed-off-by: Bas Nieuwenhuizen
> Reviewed-by: Daniel Vetter
> Reviewed-by: Zhan Liu
> Acked-by: Christian König
> Acked-by: Alex Deucher
> Fixes: 816853f9dc40 ("drm/amd/display: Set new format info for converted
> metadata.")
Do you have commit rights to drm-misc or do you need someone to commit
this for you?
Thanks!
Alex
> ---
> drivers/gpu/drm/drm_plane.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
> index e6231947f987..a0cb746bcb0a 100644
> --- a/drivers/gpu/drm/drm_plane.c
> +++ b/drivers/gpu/drm/drm_plane.c
> @@ -1163,7 +1163,14 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
> if (ret)
> goto out;
>
> - if (old_fb->format != fb->format) {
> + /*
> +* Only check the FOURCC format code, excluding modifiers. This is
> +* enough for all legacy drivers. Atomic drivers have their own
> +* checks in their ->atomic_check implementation, which will
> +* return -EINVAL if any hw or driver constraint is violated due
> +* to modifier changes.
> +*/
> + if (old_fb->format->format != fb->format->format) {
> DRM_DEBUG_KMS("Page flip is not allowed to change frame
> buffer format.\n");
> ret = -EINVAL;
> goto out;
> --
> 2.29.2
>
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RE: [PATCH v16 0/4] RDMA: Add dma-buf support
Jason, will this series be able to get into 5.12? > -Original Message- > From: Xiong, Jianxin > Sent: Tuesday, December 15, 2020 1:27 PM > To: linux-r...@vger.kernel.org; dri-devel@lists.freedesktop.org > Cc: Xiong, Jianxin ; Doug Ledford > ; Jason Gunthorpe ; Leon Romanovsky > ; Sumit Semwal ; Christian Koenig > ; Vetter, Daniel > > Subject: [PATCH v16 0/4] RDMA: Add dma-buf support > > This is the sixteenth version of the patch set. Changelog: > > v16: > * Add "select DMA_SHARED_BUFFER" to Kconfig when IB UMEM is enabled. > This fixes the auto build test error with a random config. > > v15: https://www.spinics.net/lists/linux-rdma/msg98369.html > * Rebase to the latest linux-rdma 'for-next' branch (commit 0583531bb9ef) > to pick up RDMA core and mlx5 updates > * Let ib_umem_dmabuf_get() return 'struct ib_umem_dmabuf *' instead of > 'struct ib_umem *' > * Move the check of on demand paging support to mlx5_ib_reg_user_mr_dmabuf() > * Check iova alignment at the entry point of the uverb command so that > mlx5_umem_dmabuf_default_pgsz() can always succeed > > v14: https://www.spinics.net/lists/linux-rdma/msg98265.html > * Check return value of dma_fence_wait() > * Fix a dma-buf leak in ib_umem_dmabuf_get() > * Fix return value type cast for ib_umem_dmabuf_get() > * Return -EOPNOTSUPP instead of -EINVAL for unimplemented functions > * Remove an unnecessary use of unlikely() > * Remove left-over commit message resulted from rebase > > v13: https://www.spinics.net/lists/linux-rdma/msg98227.html > * Rebase to the latest linux-rdma 'for-next' branch (5.10.0-rc6+) > * Check for device on-demand paging capability at the entry point of > the new verbs command to avoid calling device's reg_user_mr_dmabuf() > method when CONFIG_INFINIBAND_ON_DEMAND_PAGING is diabled. > > v12: https://www.spinics.net/lists/linux-rdma/msg97943.html > * Move the prototype of function ib_umem_dmabuf_release() to ib_umem.h > and remove umem_dmabuf.h > * Break a line that is too long > > v11: https://www.spinics.net/lists/linux-rdma/msg97860.html > * Rework the parameter checking code inside ib_umem_dmabuf_get() > * Fix incorrect error handling in the new verbs command handler > * Put a duplicated code sequence for checking iova and setting page size > into a function > * In the invalidation callback, check for if the buffer has been mapped > and thus the presence of a valid driver mr is ensured > * The patch that checks for dma_virt_ops is dropped because it is no > longer needed > * The patch that documents that dma-buf size is fixed has landed at: > https://cgit.freedesktop.org/drm/drm-misc/commit/?id=476b485be03c > and thus is no longer included here > * The matching user space patch set is sent separately > > v10: https://www.spinics.net/lists/linux-rdma/msg97483.html > * Don't map the pages in ib_umem_dmabuf_get(); use the size information > of the dma-buf object to validate the umem size instead > * Use PAGE_SIZE directly instead of use ib_umem_find_best_pgsz() when > the MR is created since the pages have not been mapped yet and dma-buf > requires PAGE_SIZE anyway > * Always call mlx5_umem_find_best_pgsz() after mapping the pages to > verify that the page size requirement is satisfied > * Add a patch to document that dma-buf size is fixed > > v9: https://www.spinics.net/lists/linux-rdma/msg97432.html > * Clean up the code for sg list in-place modification > * Prevent dma-buf pages from being mapped multiple times > * Map the pages in ib_umem_dmabuf_get() so that inproper values of > address/length/iova can be caught early > * Check for unsupported flags in the new uverbs command > * Add missing uverbs_finalize_uobj_create() > * Sort uverbs objects by name > * Fix formating issue -- unnecessary alignment of '=' > * Unmap pages in mlx5_ib_fence_dmabuf_mr() > * Remove address range checking from pagefault_dmabuf_mr() > > v8: https://www.spinics.net/lists/linux-rdma/msg97370.html > * Modify the dma-buf sg list in place to get a proper umem sg list and > restore it before calling dma_buf_unmap_attachment() > * Validate the umem sg list with ib_umem_find_best_pgsz() > * Remove the logic for slicing the sg list at runtime > > v7: https://www.spinics.net/lists/linux-rdma/msg97297.html > * Rebase on top of latest mlx5 MR patch series > * Slice dma-buf sg list at runtime instead of creating a new list > * Preload the buffer page mapping when the MR is created > * Move the 'dma_virt_ops' check into dma_buf_dynamic_attach() > > v6: https://www.spinics.net/lists/linux-rdma/msg96923.html > * Move the dma-buf invalidation callback from the core to the device > driver > * Move mapping update from work queue to pagefault handler > * Add dma-buf based MRs to the xarray of mmkeys so that the pagefault > handler can be reached > * Update the new driver method and uverbs command signature by changing > the paramter 'addr' to 'offset' > * Modify the sg list returned from dma_buf_map_attac
Re: [PATCH v2] drm/i915: selftest_lrc: Fix error code in live_preempt_user()
Hi Dan,
On Mon, Jan 11, 2021 at 05:18:08PM +0300, Dan Carpenter wrote:
> This error path should return a negative error code instead of success.
>
> Fixes: c92724de6db1 ("drm/i915/selftests: Try to detect rollback during
> batchbuffer preemption")
> Signed-off-by: Dan Carpenter
> Reviewed-by: Chris Wilson
Reviewed-by: Andi Shyti
Thanks,
Andi
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Re: [PATCH] amdgpu: Avoid sleeping during FPU critical sections
Hi,
On Mon, Jan 11, 2021 at 09:53:56AM +0100, Christian König wrote:
> Am 08.01.21 um 22:58 schrieb Jeremy Cline:
> > dcn20_resource_construct() includes a number of kzalloc(GFP_KERNEL)
> > calls which can sleep, but kernel_fpu_begin() disables preemption and
> > sleeping in this context is invalid.
> >
> > The only places the FPU appears to be required is in the
> > init_soc_bounding_box() function and when calculating the
> > {min,max}_fill_clk_mhz. Narrow the scope to just these two parts to
> > avoid sleeping while using the FPU.
> >
> > Fixes: 7a8a3430be15 ("amdgpu: Wrap FPU dependent functions in dc20")
> > Cc: Timothy Pearson
> > Signed-off-by: Jeremy Cline
>
> Good catch, but I would rather replace the kzalloc(GFP_KERNEL) with a
> kzalloc(GFP_ATOMIC) for now.
>
> We have tons of problems with this DC_FP_START()/DC_FP_END() annotations and
> are even in the process of moving them out of the file because the compiles
> tend to clutter FP registers even outside of the annotated ranges on some
> architectures.
>
Thanks for the review. Is it acceptable to move the DC_FP_END()
annotation up to the last usage? Keeping it where it is is probably
do-able, but covers things like calls to resource_construct() which
makes use of struct resource_create_funcs. I'm guessing only a sub-set
of the implementations are called via this function, but having an
interface which can't sleep sometimes doesn't sound appealing.
Happy to do it, but before I go down that road I just wanted to make
sure that's what you had in mind.
Thanks,
Jeremy
> > ---
> > drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 8
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> > b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> > index e04ecf0fc0db..a4fa5bf016c1 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> > @@ -3622,6 +3622,7 @@ static bool init_soc_bounding_box(struct dc *dc,
> > if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
> > int i;
> > + DC_FP_START();
> > dcn2_0_nv12_soc.sr_exit_time_us =
> > fixed16_to_double_to_cpu(bb->sr_exit_time_us);
> > dcn2_0_nv12_soc.sr_enter_plus_exit_time_us =
> > @@ -3721,6 +3722,7 @@ static bool init_soc_bounding_box(struct dc *dc,
> > dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts =
> >
> > fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
> > }
> > + DC_FP_END();
> > }
> > if (pool->base.pp_smu) {
> > @@ -3777,8 +3779,6 @@ static bool dcn20_resource_construct(
> > enum dml_project dml_project_version =
> > get_dml_project_version(ctx->asic_id.hw_internal_rev);
> > - DC_FP_START();
> > -
> > ctx->dc_bios->regs = &bios_regs;
> > pool->base.funcs = &dcn20_res_pool_funcs;
> > @@ -3959,8 +3959,10 @@ static bool dcn20_resource_construct(
> > ranges.reader_wm_sets[i].wm_inst = i;
> > ranges.reader_wm_sets[i].min_drain_clk_mhz =
> > PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
> > ranges.reader_wm_sets[i].max_drain_clk_mhz =
> > PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
> > + DC_FP_START();
> > ranges.reader_wm_sets[i].min_fill_clk_mhz = (i
> > > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
> > ranges.reader_wm_sets[i].max_fill_clk_mhz =
> > loaded_bb->clock_limits[i].dram_speed_mts / 16;
> > + DC_FP_END();
> > ranges.num_reader_wm_sets = i + 1;
> > }
> > @@ -4125,12 +4127,10 @@ static bool dcn20_resource_construct(
> > pool->base.oem_device = NULL;
> > }
> > - DC_FP_END();
> > return true;
> > create_fail:
> > - DC_FP_END();
> > dcn20_resource_destruct(pool);
> > return false;
>
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Re: [PATCH v2 02/10] drm: uapi: amd: Use SPDX in DRM drivers uAPI headers
On Tue, Dec 15, 2020 at 9:44 PM Laurent Pinchart wrote: > > The AMD DRM drivers uAPI headers are licensed under the MIT license, > and carry copies of the license with slight variations. Replace them > with SPDX headers. > > Signed-off-by: Laurent Pinchart Acked-by: Alex Deucher > --- > include/uapi/drm/amdgpu_drm.h | 19 +-- > include/uapi/drm/r128_drm.h | 20 +--- > include/uapi/drm/radeon_drm.h | 20 +--- > 3 files changed, 3 insertions(+), 56 deletions(-) > > diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h > index 7fb9c09ee93f..8ca36b088d71 100644 > --- a/include/uapi/drm/amdgpu_drm.h > +++ b/include/uapi/drm/amdgpu_drm.h > @@ -1,3 +1,4 @@ > +/* SPDX-License-Identifier: MIT */ > /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- > * > * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. > @@ -5,24 +6,6 @@ > * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. > * Copyright 2014 Advanced Micro Devices, Inc. > * > - * Permission is hereby granted, free of charge, to any person obtaining a > - * copy of this software and associated documentation files (the "Software"), > - * to deal in the Software without restriction, including without limitation > - * the rights to use, copy, modify, merge, publish, distribute, sublicense, > - * and/or sell copies of the Software, and to permit persons to whom the > - * Software is furnished to do so, subject to the following conditions: > - * > - * The above copyright notice and this permission notice shall be included in > - * all copies or substantial portions of the Software. > - * > - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR > - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > - * OTHER DEALINGS IN THE SOFTWARE. > - * > * Authors: > *Kevin E. Martin > *Gareth Hughes > diff --git a/include/uapi/drm/r128_drm.h b/include/uapi/drm/r128_drm.h > index 690e9c62f510..c426e6a1c843 100644 > --- a/include/uapi/drm/r128_drm.h > +++ b/include/uapi/drm/r128_drm.h > @@ -1,3 +1,4 @@ > +/* SPDX-License-Identifier: MIT */ > /* r128_drm.h -- Public header for the r128 driver -*- linux-c -*- > * Created: Wed Apr 5 19:24:19 2000 by ke...@precisioninsight.com > */ > @@ -6,25 +7,6 @@ > * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. > * All rights reserved. > * > - * Permission is hereby granted, free of charge, to any person obtaining a > - * copy of this software and associated documentation files (the "Software"), > - * to deal in the Software without restriction, including without limitation > - * the rights to use, copy, modify, merge, publish, distribute, sublicense, > - * and/or sell copies of the Software, and to permit persons to whom the > - * Software is furnished to do so, subject to the following conditions: > - * > - * The above copyright notice and this permission notice (including the next > - * paragraph) shall be included in all copies or substantial portions of the > - * Software. > - * > - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR > - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > OTHER > - * DEALINGS IN THE SOFTWARE. > - * > * Authors: > *Gareth Hughes > *Kevin E. Martin > diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h > index 490a59cc4532..b5c4ef813a9e 100644 > --- a/include/uapi/drm/radeon_drm.h > +++ b/include/uapi/drm/radeon_drm.h > @@ -1,3 +1,4 @@ > +/* SPDX-License-Identifier: MIT */ > /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- > * > * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. > @@ -5,25 +6,6 @@ > * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. > * All rights reserved. > * > - * Permission is hereby granted, free of charge, to any person obtaining a > - * copy of this software and associated documentation files (the "Software"), > - * to deal in the Software without restriction, including without limitation > - * the rights to use, copy, modify, merge, publish, distribute, sublicense, > - * and/or sell copies of the Software, and to permit persons to whom the > - * Software is furnished to do so, subject to the following conditions: > - * > -
Re: [PATCH -next] drm/amd/display: tweak the kerneldoc for active_vblank_irq_count
[AMD Official Use Only - Internal Distribution Only]
Thanks,
Reviewed-by: Bhawanpreet Lakha
From: Lukas Bulwahn
Sent: January 11, 2021 3:46 AM
To: Lakha, Bhawanpreet ; Kazlauskas, Nicholas
; Deucher, Alexander ;
Koenig, Christian ; amd-...@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org ;
linux-ker...@vger.kernel.org ;
linux-...@vger.kernel.org ;
kernel-janit...@vger.kernel.org ; Lukas
Bulwahn
Subject: [PATCH -next] drm/amd/display: tweak the kerneldoc for
active_vblank_irq_count
Commit 71338cb4a7c2 ("drm/amd/display: enable idle optimizations for linux
(MALL stutter)") adds active_vblank_irq_count to amdgpu_display_manager
in ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h.
The kerneldoc is incorrectly formatted, and make htmldocs warns:
./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:
340: warning: Incorrect use of kernel-doc format: *
@active_vblank_irq_count
379: warning: Function parameter or member 'active_vblank_irq_count' not
described in 'amdgpu_display_manager'
Tweak the kerneldoc for active_vblank_irq_count.
Signed-off-by: Lukas Bulwahn
---
applies on amdgpu's -next and next-20210111
Bhawanpreet, Nick, please review and ack.
Alex, Christian, please pick on top of the commit above.
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index f084e2fc9569..5ee1b766884e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -337,7 +337,7 @@ struct amdgpu_display_manager {
const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
/**
-* @active_vblank_irq_count
+* @active_vblank_irq_count:
*
* number of currently active vblank irqs
*/
--
2.17.1
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Re: [PATCH -next] drm/amd/display: tweak the kerneldoc for active_vblank_irq_count
Applied. Thanks!
Alex
On Mon, Jan 11, 2021 at 10:54 AM Lakha, Bhawanpreet
wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
>
> Thanks,
>
> Reviewed-by: Bhawanpreet Lakha
>
> From: Lukas Bulwahn
> Sent: January 11, 2021 3:46 AM
> To: Lakha, Bhawanpreet ; Kazlauskas, Nicholas
> ; Deucher, Alexander
> ; Koenig, Christian ;
> amd-...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org ;
> linux-ker...@vger.kernel.org ;
> linux-...@vger.kernel.org ;
> kernel-janit...@vger.kernel.org ; Lukas
> Bulwahn
> Subject: [PATCH -next] drm/amd/display: tweak the kerneldoc for
> active_vblank_irq_count
>
> Commit 71338cb4a7c2 ("drm/amd/display: enable idle optimizations for linux
> (MALL stutter)") adds active_vblank_irq_count to amdgpu_display_manager
> in ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h.
>
> The kerneldoc is incorrectly formatted, and make htmldocs warns:
>
> ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:
> 340: warning: Incorrect use of kernel-doc format: *
> @active_vblank_irq_count
> 379: warning: Function parameter or member 'active_vblank_irq_count' not
> described in 'amdgpu_display_manager'
>
> Tweak the kerneldoc for active_vblank_irq_count.
>
> Signed-off-by: Lukas Bulwahn
> ---
> applies on amdgpu's -next and next-20210111
>
> Bhawanpreet, Nick, please review and ack.
>
> Alex, Christian, please pick on top of the commit above.
>
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> index f084e2fc9569..5ee1b766884e 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
> @@ -337,7 +337,7 @@ struct amdgpu_display_manager {
> const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
>
> /**
> -* @active_vblank_irq_count
> +* @active_vblank_irq_count:
> *
> * number of currently active vblank irqs
> */
> --
> 2.17.1
>
> ___
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Re: [Freedreno] [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx
On Mon, Jan 11, 2021 at 09:54:12AM +0530, Sai Prakash Ranjan wrote: > Hi Rob, > > On 2021-01-08 22:16, Rob Clark wrote: > >On Fri, Jan 8, 2021 at 6:05 AM Sai Prakash Ranjan > > wrote: > >> > >>On 2021-01-08 19:09, Konrad Dybcio wrote: > Konrad, can you please test this below change without your change? > >>> > >>> This brings no difference, a BUG still happens. We're still calling > >>> to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330 > >>> into an A640.. > >>> > >>> Also, relying on disabling LLCC in the config is out of question as it > >>> makes the arm32 kernel not compile with DRM/MSM and it just removes > >>> the functionality on devices with a6xx.. (unless somebody removes the > >>> dependency on it, which in my opinion is even worse and will cause > >>> more problems for developers!). > >>> > >> > >>Disabling LLCC is not the suggestion, I was under the impression that > >>was the cause here for the smmu bug. Anyways, the check for llc slice > >>in case llcc is disabled is not correct as well. I will send a patch for > >>that as well. > >> > >>> The bigger question is how and why did that piece of code ever make it > >>> to adreno_gpu.c and not a6xx_gpu.c? > >>> > >> > >>My mistake, I will move it. > > > >Thanks, since we don't have kernel-CI coverage for gpu, and there > >probably isn't one person who has all the different devices supported > >(or enough hours in the day to test them all), it is probably > >better/safer to keep things in the backend code that is specific to a > >given generation. > > > > Agreed, I will post this change soon and will introduce some feature > check as well because we will need it for iommu prot flag as per discussion > here - https://lore.kernel.org/lkml/20210108181830.GA5457@willie-the-truck/ > > >>> To solve it in a cleaner way I propose to move it to an a6xx-specific > >>> file, or if it's going to be used with next-gen GPUs, perhaps manage > >>> calling of this code via an adreno quirk/feature in adreno_device.c. > >>> Now that I think about it, A5xx GPMU en/disable could probably managed > >>> like that, instead of using tons of if-statements for each GPU model > >>> that has it.. > >>> > >>> While we're at it, do ALL (and I truly do mean ALL, including the > >>> low-end ones, this will be important later on) A6xx GPUs make use of > >>> that feature? > >>> > >> > >>I do not have a list of all A6XX GPUs with me currently, but from what > >>I know, A618, A630, A640, A650 has the support. > >> > > > >From the PoV of bringing up new a6xx, we should probably consider that > >some of them may not *yet* have LLCC enabled. I have an 8cx laptop > >and once I find time to get the display working, the next step would > >be bringing up a680.. and I'd probably like to start without LLCC.. > > > > Right, once I move the LLCC code to a6xx specific address space creation, > without LLCC slices for GPU specified in qcom llcc driver, we will not > be using it. Right. The problem here was that we were assuming an a6xx container in generic code. Testing the existence of LLCC or not is a different problem but it is my understanding that if we set the attribute without LLCC enabled it just gets ignored. Is that correct Sai? Jordan > Thanks, > Sai > > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3 01/12] drm: Add dummy page per device or GEM object
On Fri, Jan 08, 2021 at 04:49:55PM +, Grodzovsky, Andrey wrote: > Ok then, I guess I will proceed with the dummy pages list implementation then. > > Andrey > > > From: Koenig, Christian > Sent: 08 January 2021 09:52 > To: Grodzovsky, Andrey ; Daniel Vetter > > Cc: amd-...@lists.freedesktop.org ; > dri-devel@lists.freedesktop.org ; > daniel.vet...@ffwll.ch ; r...@kernel.org > ; l.st...@pengutronix.de ; > yuq...@gmail.com ; e...@anholt.net ; > Deucher, Alexander ; gre...@linuxfoundation.org > ; ppaala...@gmail.com ; > Wentland, Harry > Subject: Re: [PATCH v3 01/12] drm: Add dummy page per device or GEM object > > Mhm, I'm not aware of any let over pointer between TTM and GEM and we > worked quite hard on reducing the size of the amdgpu_bo, so another > extra pointer just for that corner case would suck quite a bit. We have a ton of other pointers in struct amdgpu_bo (or any of it's lower things) which are fairly single-use, so I'm really not much seeing the point in making this a special case. It also means the lifetime management becomes a bit iffy, since we can't throw away the dummy page then the last reference to the bo is released (since we don't track it there), but only when the last pointer to the device is released. Potentially this means a pile of dangling pages hanging around for too long. If you need some ideas for redundant pointers: - destroy callback (kinda not cool to not have this const anyway), we could refcount it all with the overall gem bo. Quite a bit of work. - bdev pointer, if we move the device ttm stuff into struct drm_device, or create a common struct ttm_device, we can ditch that - We could probably merge a few of the fields and find 8 bytes somewhere - we still have 2 krefs, would probably need to fix that before we can merge the destroy callbacks So there's plenty of room still, if the size of a bo struct is really that critical. Imo it's not. -Daniel > > Christian. > > Am 08.01.21 um 15:46 schrieb Andrey Grodzovsky: > > Daniel had some objections to this (see bellow) and so I guess I need > > you both to agree on the approach before I proceed. > > > > Andrey > > > > On 1/8/21 9:33 AM, Christian König wrote: > >> Am 08.01.21 um 15:26 schrieb Andrey Grodzovsky: > >>> Hey Christian, just a ping. > >> > >> Was there any question for me here? > >> > >> As far as I can see the best approach would still be to fill the VMA > >> with a single dummy page and avoid pointers in the GEM object. > >> > >> Christian. > >> > >>> > >>> Andrey > >>> > >>> On 1/7/21 11:37 AM, Andrey Grodzovsky wrote: > > On 1/7/21 11:30 AM, Daniel Vetter wrote: > > On Thu, Jan 07, 2021 at 11:26:52AM -0500, Andrey Grodzovsky wrote: > >> On 1/7/21 11:21 AM, Daniel Vetter wrote: > >>> On Tue, Jan 05, 2021 at 04:04:16PM -0500, Andrey Grodzovsky wrote: > On 11/23/20 3:01 AM, Christian König wrote: > > Am 23.11.20 um 05:54 schrieb Andrey Grodzovsky: > >> On 11/21/20 9:15 AM, Christian König wrote: > >>> Am 21.11.20 um 06:21 schrieb Andrey Grodzovsky: > Will be used to reroute CPU mapped BO's page faults once > device is removed. > >>> Uff, one page for each exported DMA-buf? That's not > >>> something we can do. > >>> > >>> We need to find a different approach here. > >>> > >>> Can't we call alloc_page() on each fault and link them together > >>> so they are freed when the device is finally reaped? > >> For sure better to optimize and allocate on demand when we reach > >> this corner case, but why the linking ? > >> Shouldn't drm_prime_gem_destroy be good enough place to free ? > > I want to avoid keeping the page in the GEM object. > > > > What we can do is to allocate a page on demand for each fault > > and link > > the together in the bdev instead. > > > > And when the bdev is then finally destroyed after the last > > application > > closed we can finally release all of them. > > > > Christian. > Hey, started to implement this and then realized that by > allocating a page > for each fault indiscriminately > we will be allocating a new page for each faulting virtual > address within a > VA range belonging the same BO > and this is obviously too much and not the intention. Should I > instead use > let's say a hashtable with the hash > key being faulting BO address to actually keep allocating and > reusing same > dummy zero page per GEM BO > (or for that matter DRM file object address for non imported > BOs) ? > >>> Why do we need a hashtable? All the sw structures to track this > >>> should > >>> still be around: > >>> - if gem_bo->dma_buf is set the buffer is currently e
Re: [PATCH v3 01/12] drm: Add dummy page per device or GEM object
On Mon, Jan 11, 2021 at 05:13:56PM +0100, Daniel Vetter wrote: > On Fri, Jan 08, 2021 at 04:49:55PM +, Grodzovsky, Andrey wrote: > > Ok then, I guess I will proceed with the dummy pages list implementation > > then. > > > > Andrey > > > > > > From: Koenig, Christian > > Sent: 08 January 2021 09:52 > > To: Grodzovsky, Andrey ; Daniel Vetter > > > > Cc: amd-...@lists.freedesktop.org ; > > dri-devel@lists.freedesktop.org ; > > daniel.vet...@ffwll.ch ; r...@kernel.org > > ; l.st...@pengutronix.de ; > > yuq...@gmail.com ; e...@anholt.net ; > > Deucher, Alexander ; gre...@linuxfoundation.org > > ; ppaala...@gmail.com ; > > Wentland, Harry > > Subject: Re: [PATCH v3 01/12] drm: Add dummy page per device or GEM object > > > > Mhm, I'm not aware of any let over pointer between TTM and GEM and we > > worked quite hard on reducing the size of the amdgpu_bo, so another > > extra pointer just for that corner case would suck quite a bit. > > We have a ton of other pointers in struct amdgpu_bo (or any of it's lower > things) which are fairly single-use, so I'm really not much seeing the > point in making this a special case. It also means the lifetime management > becomes a bit iffy, since we can't throw away the dummy page then the last > reference to the bo is released (since we don't track it there), but only > when the last pointer to the device is released. Potentially this means a > pile of dangling pages hanging around for too long. Also if you really, really, really want to have this list, please don't reinvent it since we have it already. drmm_ is exactly meant for resources that should be freed when the final drm_device reference disappears. -Daniel > If you need some ideas for redundant pointers: > - destroy callback (kinda not cool to not have this const anyway), we > could refcount it all with the overall gem bo. Quite a bit of work. > - bdev pointer, if we move the device ttm stuff into struct drm_device, or > create a common struct ttm_device, we can ditch that > - We could probably merge a few of the fields and find 8 bytes somewhere > - we still have 2 krefs, would probably need to fix that before we can > merge the destroy callbacks > > So there's plenty of room still, if the size of a bo struct is really that > critical. Imo it's not. > > > > > > Christian. > > > > Am 08.01.21 um 15:46 schrieb Andrey Grodzovsky: > > > Daniel had some objections to this (see bellow) and so I guess I need > > > you both to agree on the approach before I proceed. > > > > > > Andrey > > > > > > On 1/8/21 9:33 AM, Christian König wrote: > > >> Am 08.01.21 um 15:26 schrieb Andrey Grodzovsky: > > >>> Hey Christian, just a ping. > > >> > > >> Was there any question for me here? > > >> > > >> As far as I can see the best approach would still be to fill the VMA > > >> with a single dummy page and avoid pointers in the GEM object. > > >> > > >> Christian. > > >> > > >>> > > >>> Andrey > > >>> > > >>> On 1/7/21 11:37 AM, Andrey Grodzovsky wrote: > > > > On 1/7/21 11:30 AM, Daniel Vetter wrote: > > > On Thu, Jan 07, 2021 at 11:26:52AM -0500, Andrey Grodzovsky wrote: > > >> On 1/7/21 11:21 AM, Daniel Vetter wrote: > > >>> On Tue, Jan 05, 2021 at 04:04:16PM -0500, Andrey Grodzovsky wrote: > > On 11/23/20 3:01 AM, Christian König wrote: > > > Am 23.11.20 um 05:54 schrieb Andrey Grodzovsky: > > >> On 11/21/20 9:15 AM, Christian König wrote: > > >>> Am 21.11.20 um 06:21 schrieb Andrey Grodzovsky: > > Will be used to reroute CPU mapped BO's page faults once > > device is removed. > > >>> Uff, one page for each exported DMA-buf? That's not > > >>> something we can do. > > >>> > > >>> We need to find a different approach here. > > >>> > > >>> Can't we call alloc_page() on each fault and link them together > > >>> so they are freed when the device is finally reaped? > > >> For sure better to optimize and allocate on demand when we reach > > >> this corner case, but why the linking ? > > >> Shouldn't drm_prime_gem_destroy be good enough place to free ? > > > I want to avoid keeping the page in the GEM object. > > > > > > What we can do is to allocate a page on demand for each fault > > > and link > > > the together in the bdev instead. > > > > > > And when the bdev is then finally destroyed after the last > > > application > > > closed we can finally release all of them. > > > > > > Christian. > > Hey, started to implement this and then realized that by > > allocating a page > > for each fault indiscriminately > > we will be allocating a new page for each faulting virtual > > address within a > > VA range belonging the same BO > > and this is obviously too much and not
Re: [PATCH 1/2] drm/radeon: stop re-init the TTM page pool
On Mon, Jan 11, 2021 at 11:16:13AM +0100, Christian König wrote:
> Am 08.01.21 um 16:53 schrieb Daniel Vetter:
> > On Fri, Jan 8, 2021 at 3:36 PM Christian König
> > wrote:
> > > Am 08.01.21 um 15:31 schrieb Daniel Vetter:
> > > > On Thu, Jan 07, 2021 at 09:08:29PM +0100, Christian König wrote:
> > > > > Am 07.01.21 um 19:07 schrieb Daniel Vetter:
> > > > > > On Tue, Jan 05, 2021 at 07:23:08PM +0100, Christian König wrote:
> > > > > > > Drivers are not supposed to init the page pool directly any more.
> > > > > > >
> > > > > > > Signed-off-by: Christian König
> > > > > > Please include reported-by credits and link to the bug reports on
> > > > > > lore.kernel.org when merging this. Also I guess this should have a
> > > > > > Fixes:
> > > > > > line?
> > > > > I'm not aware of a bug report, but the reported-by/Fixes lines are
> > > > > indeed
> > > > > missing.
> > > > This one here:
> > > >
> > > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fdri-devel%2F20201231104020.GA4504%40zn.tnic%2F&data=04%7C01%7Cchristian.koenig%40amd.com%7C3aede203348b4f32ea3108d8b3e224ec%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637457131179258488%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=bHVw4lj1f8g4ohVTeuKNkb0LAbLwY6N4KWortr3VtAo%3D&reserved=0
> > > >
> > > > Or did I get confused, and the above is yet another bug?
> > > Yeah, but that was just reported by mail. The bug tracker I've saw was
> > > opened after the patch was already pushed.
> > Still good to give reported-by credits for mailing list reports and
> > link to lore.kernel.org for the report, that's not just useful for
> > bugzilla reports.
>
> That's indeed true, but I was distracted by the fact that drm-misc-fixes
> wasn't up to date :)
>
> Going to add that earlier next time.
>
> > > > > BTW: Any idea why dim add-link doesn't work?
> > > > Hm we occasionally have fun with email parsing (it's hard) and
> > > > especially
> > > > python changes in how encodings are handled differently between python2
> > > > and python3. If you have a specific example I can try and take a look
> > > > why
> > > > it doesn't work.
> > > It just looks up and doesn't seem to do anything. I'm not familiar with
> > > python so I can just describe the symptoms.
> > I meant tell me which mail (patchwork or lore) and I'll try to
> > reproduce and see what's maybe up.
>
> It doesn't seem to work in general. E.g. any patch I try I just don't get
> any progress in over 10 Minutes.
>
> Maybe some server is not responding?
Uh dim add-link pretty similar to dim apply-patch, it takes the mbox on
stdin and does only local git stuff with it.
-Daniel
>
> Christian.
>
> > -Daniel
> >
> > > Christian.
> > >
> > > > -Daniel
> > > >
> > > > > > And maybe some words on how/why stuff blows up.
> > > > > Just a typo. I've forgot to remove two lines in radeon while rebasing
> > > > > and
> > > > > still had the symbols exported so never noticed this.
> > > > >
> > > > > Christian.
> > > > >
> > > > > > -Daniel
> > > > > >
> > > > > > > ---
> > > > > > > drivers/gpu/drm/radeon/radeon_ttm.c | 3 ---
> > > > > > > 1 file changed, 3 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c
> > > > > > > b/drivers/gpu/drm/radeon/radeon_ttm.c
> > > > > > > index d4328ff57757..35b715f82ed8 100644
> > > > > > > --- a/drivers/gpu/drm/radeon/radeon_ttm.c
> > > > > > > +++ b/drivers/gpu/drm/radeon/radeon_ttm.c
> > > > > > > @@ -729,9 +729,6 @@ int radeon_ttm_init(struct radeon_device
> > > > > > > *rdev)
> > > > > > > }
> > > > > > > rdev->mman.initialized = true;
> > > > > > > - ttm_pool_init(&rdev->mman.bdev.pool, rdev->dev,
> > > > > > > rdev->need_swiotlb,
> > > > > > > -dma_addressing_limited(&rdev->pdev->dev));
> > > > > > > -
> > > > > > > r = radeon_ttm_init_vram(rdev);
> > > > > > > if (r) {
> > > > > > > DRM_ERROR("Failed initializing VRAM heap.\n");
> > > > > > > --
> > > > > > > 2.25.1
> > > > > > >
> > > > > > > ___
> > > > > > > dri-devel mailing list
> > > > > > > dri-devel@lists.freedesktop.org
> > > > > > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Fdri-devel&data=04%7C01%7Cchristian.koenig%40amd.com%7C3aede203348b4f32ea3108d8b3e224ec%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637457131179258488%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=pHzuAsJcXf5HlAfJ7wYYc%2BsizZhSLBGWXBhCyVNRCfo%3D&reserved=0
> >
>
--
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH] drm/panel: panel-simple: add bus-format and connector-type to Innolux n116bge
Hi, On Sat, Jan 9, 2021 at 5:10 AM Heiko Stuebner wrote: > > From: Heiko Stuebner > > The Innolux n116bge panel has an eDP connector and 3*6 bits bus format. > > Signed-off-by: Heiko Stuebner > --- > drivers/gpu/drm/panel/panel-simple.c | 2 ++ > 1 file changed, 2 insertions(+) This looks right to me. Reviewed-by: Douglas Anderson ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v8] backlight: lms283gf05: Convert to GPIO descriptors
On Sun, 10 Jan 2021, Linus Walleij wrote: > This converts the lms283gf05 backlight driver to use GPIO > descriptors and switches the single PXA Palm Z2 device > over to defining these. > > Since the platform data was only used to convey GPIO > information we can delete the platform data header. > > Notice that we define the proper active low semantics in > the board file GPIO descriptor table (active low) and > assert the reset line by bringing it to "1" (asserted). > > Cc: Marek Vasut > Cc: Daniel Mack > Cc: Haojian Zhuang > Cc: Robert Jarzmik > Reviewed-by: Daniel Thompson > Signed-off-by: Linus Walleij > --- > ChangeLog v7->v8: > - Rebase onto v5.11-rc1 > - I wonder why this never seems to get merged...? Because you need SPI & PXA Acks and a merge plan. > ChangeLog v6->v7: > - Rebase onto v5.10-rc1 > ChangeLog v5->v6: > - Rebase onto v5.9-rc1 > ChangeLog v4->v5: > - Rebase on v5.8-rc1 > - Collected Daniel's Reviewed-by tag. > ChangeLog v3->v4: > - Check IS_ERR() on the returned GPIO descriptor. > - Unconditionally set consumer name since the API tolerates NULL. > ChangeLog v2->v3: > - Fix a use-before-allocated bug discovered by compile tests. > - Remove unused ret variable as autobuilders complained. > ChangeLog v1->v2: > - Bring up the GPIO de-asserted in probe() > > Marek: I saw this was written by you, are you regularly > testing the Z2 device? > --- > arch/arm/mach-pxa/z2.c | 12 +--- > drivers/video/backlight/lms283gf05.c | 43 +++- > include/linux/spi/lms283gf05.h | 16 --- > 3 files changed, 25 insertions(+), 46 deletions(-) > delete mode 100644 include/linux/spi/lms283gf05.h -- Lee Jones [李琼斯] Senior Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH][next] drm/amdgpu: Add missing BOOTUP_DEFAULT to profile_name[]
On Mon, Jan 11, 2021 at 6:46 AM Colin King wrote:
>
> From: Colin Ian King
>
> A recent change added a new BOOTUP_DEFAULT power profile mode
> to the PP_SMC_POWER_PROFILE enum but omitted updating the
> corresponding profile_name array. Fix this by adding in the
> missing BOOTUP_DEFAULT to profile_name[].
>
> Addresses-Coverity: ("Out-of-bounds read")
> Fixes: c27c9778a19e ("drm/amd/powerplay: support BOOTUP_DEFAULT power profile
> mode")
> Signed-off-by: Colin Ian King
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index 75ddcadf3802..4763cb095820 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -774,6 +774,7 @@ static int vangogh_get_power_profile_mode(struct
> smu_context *smu,
>char *buf)
> {
> static const char *profile_name[] = {
> + "BOOTUP_DEFAULT",
> "FULL_SCREEN_3D",
> "VIDEO",
> "VR",
> --
> 2.29.2
>
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Re: [PATCH 00/35] Add HMM-based SVM memory manager to KFD
On Fri, Jan 08, 2021 at 12:56:24PM -0500, Felix Kuehling wrote: > > Am 2021-01-08 um 11:53 a.m. schrieb Daniel Vetter: > > On Fri, Jan 8, 2021 at 5:36 PM Felix Kuehling > > wrote: > >> > >> Am 2021-01-08 um 11:06 a.m. schrieb Daniel Vetter: > >>> On Fri, Jan 8, 2021 at 4:58 PM Felix Kuehling > >>> wrote: > Am 2021-01-08 um 9:40 a.m. schrieb Daniel Vetter: > > On Thu, Jan 07, 2021 at 11:25:41AM -0500, Felix Kuehling wrote: > >> Am 2021-01-07 um 4:23 a.m. schrieb Daniel Vetter: > >>> On Wed, Jan 06, 2021 at 10:00:52PM -0500, Felix Kuehling wrote: > This is the first version of our HMM based shared virtual memory > manager > for KFD. There are still a number of known issues that we're working > through > (see below). This will likely lead to some pretty significant > changes in > MMU notifier handling and locking on the migration code paths. So > don't > get hung up on those details yet. > > But I think this is a good time to start getting feedback. We're > pretty > confident about the ioctl API, which is both simple and extensible > for the > future. (see patches 4,16) The user mode side of the API can be > found here: > https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/blob/fxkamd/hmm-wip/src/svm.c > > I'd also like another pair of eyes on how we're interfacing with the > GPU VM > code in amdgpu_vm.c (see patches 12,13), retry page fault handling > (24,25), > and some retry IRQ handling changes (32). > > > Known issues: > * won't work with IOMMU enabled, we need to dma_map all pages > properly > * still working on some race conditions and random bugs > * performance is not great yet > >>> Still catching up, but I think there's another one for your list: > >>> > >>> * hmm gpu context preempt vs page fault handling. I've had a short > >>>discussion about this one with Christian before the holidays, and > >>> also > >>>some private chats with Jerome. It's nasty since no easy fix, much > >>> less > >>>a good idea what's the best approach here. > >> Do you have a pointer to that discussion or any more details? > > Essentially if you're handling an hmm page fault from the gpu, you can > > deadlock by calling dma_fence_wait on a (chain of, possibly) other > > command > > submissions or compute contexts with dma_fence_wait. Which deadlocks if > > you can't preempt while you have that page fault pending. Two solutions: > > > > - your hw can (at least for compute ctx) preempt even when a page fault > > is > > pending > Our GFXv9 GPUs can do this. GFXv10 cannot. > >>> Uh, why did your hw guys drop this :-/ > > Performance. It's the same reason why the XNACK mode selection API > exists (patch 16). When we enable recoverable page fault handling in the > compute units on GFXv9, it costs some performance even when no page > faults are happening. On GFXv10 that retry fault handling moved out of > the compute units, so they don't take the performance hit. But that > sacrificed the ability to preempt during page faults. We'll need to work > with our hardware teams to restore that capability in a future generation. Ah yes, you need to stall in more points in the compute cores to make sure you can recover if the page fault gets interrupted. Maybe my knowledge is outdated, but my understanding is that nvidia can also preempt (but only for compute jobs, since oh dear the pain this would be for all the fixed function stuff). Since gfx10 moved page fault handling further away from compute cores, do you know whether this now means you can do page faults for (some?) fixed function stuff too? Or still only for compute? Supporting page fault for 3d would be real pain with the corner we're stuck in right now, but better we know about this early than later :-/ > >>> > > - lots of screaming in trying to come up with an alternate solution. > > They > > all suck. > My idea for GFXv10 is to avoid preemption for memory management purposes > and rely 100% on page faults instead. That is, if the memory manager > needs to prevent GPU access to certain memory, just invalidate the GPU > page table entries pointing to that memory. No waiting for fences is > necessary, except for the SDMA job that invalidates the PTEs, which runs > on a special high-priority queue that should never deadlock. That should > prevent the CPU getting involved in deadlocks in kernel mode. But you > can still deadlock the GPU in user mode if all compute units get stuck > in page faults and can't switch to any useful work any more. So it's > possible that we won't be able to use GPU page faults on our GFXv
Re: [PATCH] amdgpu: Avoid sleeping during FPU critical sections
On Mon, Jan 11, 2021 at 09:53:56AM +0100, Christian König wrote:
> Am 08.01.21 um 22:58 schrieb Jeremy Cline:
> > dcn20_resource_construct() includes a number of kzalloc(GFP_KERNEL)
> > calls which can sleep, but kernel_fpu_begin() disables preemption and
> > sleeping in this context is invalid.
> >
> > The only places the FPU appears to be required is in the
> > init_soc_bounding_box() function and when calculating the
> > {min,max}_fill_clk_mhz. Narrow the scope to just these two parts to
> > avoid sleeping while using the FPU.
> >
> > Fixes: 7a8a3430be15 ("amdgpu: Wrap FPU dependent functions in dc20")
> > Cc: Timothy Pearson
> > Signed-off-by: Jeremy Cline
>
> Good catch, but I would rather replace the kzalloc(GFP_KERNEL) with a
> kzalloc(GFP_ATOMIC) for now.
>
> We have tons of problems with this DC_FP_START()/DC_FP_END() annotations and
> are even in the process of moving them out of the file because the compiles
> tend to clutter FP registers even outside of the annotated ranges on some
> architectures.
Out of curiosity, what's the plan? Soft-fp implementation for DC so you
can keep the algorithms all unchanged, or redoing them as some fixed point
with careful review and retesting everything? Something else?
-Daniel
>
> Regards,
> Christian.
>
> > ---
> > drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 8
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> > b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> > index e04ecf0fc0db..a4fa5bf016c1 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> > @@ -3622,6 +3622,7 @@ static bool init_soc_bounding_box(struct dc *dc,
> > if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
> > int i;
> > + DC_FP_START();
> > dcn2_0_nv12_soc.sr_exit_time_us =
> > fixed16_to_double_to_cpu(bb->sr_exit_time_us);
> > dcn2_0_nv12_soc.sr_enter_plus_exit_time_us =
> > @@ -3721,6 +3722,7 @@ static bool init_soc_bounding_box(struct dc *dc,
> > dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts =
> >
> > fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
> > }
> > + DC_FP_END();
> > }
> > if (pool->base.pp_smu) {
> > @@ -3777,8 +3779,6 @@ static bool dcn20_resource_construct(
> > enum dml_project dml_project_version =
> > get_dml_project_version(ctx->asic_id.hw_internal_rev);
> > - DC_FP_START();
> > -
> > ctx->dc_bios->regs = &bios_regs;
> > pool->base.funcs = &dcn20_res_pool_funcs;
> > @@ -3959,8 +3959,10 @@ static bool dcn20_resource_construct(
> > ranges.reader_wm_sets[i].wm_inst = i;
> > ranges.reader_wm_sets[i].min_drain_clk_mhz =
> > PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
> > ranges.reader_wm_sets[i].max_drain_clk_mhz =
> > PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
> > + DC_FP_START();
> > ranges.reader_wm_sets[i].min_fill_clk_mhz = (i
> > > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
> > ranges.reader_wm_sets[i].max_fill_clk_mhz =
> > loaded_bb->clock_limits[i].dram_speed_mts / 16;
> > + DC_FP_END();
> > ranges.num_reader_wm_sets = i + 1;
> > }
> > @@ -4125,12 +4127,10 @@ static bool dcn20_resource_construct(
> > pool->base.oem_device = NULL;
> > }
> > - DC_FP_END();
> > return true;
> > create_fail:
> > - DC_FP_END();
> > dcn20_resource_destruct(pool);
> > return false;
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH v2] drm: Check actual format for legacy pageflip.
On Mon, Jan 11, 2021 at 4:02 PM Alex Deucher wrote:
>
> On Sat, Jan 9, 2021 at 9:11 PM Bas Nieuwenhuizen
> wrote:
> >
> > With modifiers one can actually have different format_info structs
> > for the same format, which now matters for AMDGPU since we convert
> > implicit modifiers to explicit modifiers with multiple planes.
> >
> > I checked other drivers and it doesn't look like they end up triggering
> > this case so I think this is safe to relax.
> >
> > Signed-off-by: Bas Nieuwenhuizen
> > Reviewed-by: Daniel Vetter
> > Reviewed-by: Zhan Liu
> > Acked-by: Christian König
> > Acked-by: Alex Deucher
> > Fixes: 816853f9dc40 ("drm/amd/display: Set new format info for converted
> > metadata.")
>
> Do you have commit rights to drm-misc or do you need someone to commit
> this for you?
I don't have commit rights so if the patch could be committed for me
that would be appreciated!
>
> Thanks!
>
> Alex
>
> > ---
> > drivers/gpu/drm/drm_plane.c | 9 -
> > 1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
> > index e6231947f987..a0cb746bcb0a 100644
> > --- a/drivers/gpu/drm/drm_plane.c
> > +++ b/drivers/gpu/drm/drm_plane.c
> > @@ -1163,7 +1163,14 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
> > if (ret)
> > goto out;
> >
> > - if (old_fb->format != fb->format) {
> > + /*
> > +* Only check the FOURCC format code, excluding modifiers. This is
> > +* enough for all legacy drivers. Atomic drivers have their own
> > +* checks in their ->atomic_check implementation, which will
> > +* return -EINVAL if any hw or driver constraint is violated due
> > +* to modifier changes.
> > +*/
> > + if (old_fb->format->format != fb->format->format) {
> > DRM_DEBUG_KMS("Page flip is not allowed to change frame
> > buffer format.\n");
> > ret = -EINVAL;
> > goto out;
> > --
> > 2.29.2
> >
> > ___
> > amd-gfx mailing list
> > amd-...@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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[PATCH] drm/ttm: Fix address passed to dma_mapping_error() in ttm_pool_map()
check_unmap() is producing a warning about a missing map error check.
The return value from dma_map_page() should be checked for an error, not
the caller-provided dma_addr.
Fixes: d099fc8f540a ("drm/ttm: new TT backend allocation pool v3")
Signed-off-by: Jeremy Cline
---
drivers/gpu/drm/ttm/ttm_pool.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c
index 7b2f60616750..0aa197204b08 100644
--- a/drivers/gpu/drm/ttm/ttm_pool.c
+++ b/drivers/gpu/drm/ttm/ttm_pool.c
@@ -190,7 +190,7 @@ static int ttm_pool_map(struct ttm_pool *pool, unsigned int
order,
size_t size = (1ULL << order) * PAGE_SIZE;
addr = dma_map_page(pool->dev, p, 0, size, DMA_BIDIRECTIONAL);
- if (dma_mapping_error(pool->dev, **dma_addr))
+ if (dma_mapping_error(pool->dev, addr))
return -EFAULT;
}
--
2.29.2
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Re: [PATCH v4 1/2] drm/msm: Add speed-bin support to a618 gpu
On Fri, Jan 08, 2021 at 11:45:30PM +0530, Akhil P Oommen wrote:
> Some GPUs support different max frequencies depending on the platform.
> To identify the correct variant, we should check the gpu speedbin
> fuse value. Add support for this speedbin detection to a6xx family
> along with the required fuse details for a618 gpu.
Reviewed-by: Jordan Crouse
> Signed-off-by: Akhil P Oommen
> ---
> Changes from v2:
> 1. Made the changes a6xx specific to save space.
> Changes from v1:
> 1. Added the changes to support a618 sku to the series.
> 2. Avoid failing probe in case of an unsupported sku. (Rob)
> Changes from v3:
> 1. Replace a618_speedbins[] with a function. (Jordan)
>
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83
> +++
> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +
> 2 files changed, 85 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 1306618..499d134 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -10,6 +10,7 @@
>
> #include
> #include
> +#include
> #include
>
> #define GPU_PAS_ID 13
> @@ -1208,6 +1209,10 @@ static void a6xx_destroy(struct msm_gpu *gpu)
> a6xx_gmu_remove(a6xx_gpu);
>
> adreno_gpu_cleanup(adreno_gpu);
> +
> + if (a6xx_gpu->opp_table)
> + dev_pm_opp_put_supported_hw(a6xx_gpu->opp_table);
> +
> kfree(a6xx_gpu);
> }
>
> @@ -1264,6 +1269,78 @@ static uint32_t a6xx_get_rptr(struct msm_gpu *gpu,
> struct msm_ringbuffer *ring)
> return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR);
> }
>
> +static u32 a618_get_speed_bin(u32 fuse)
> +{
> + if (fuse == 0)
> + return 0;
> + else if (fuse == 169)
> + return 1;
> + else if (fuse == 174)
> + return 2;
> +
> + return UINT_MAX;
> +}
> +
> +static u32 fuse_to_supp_hw(struct device *dev, u32 revn, u32 fuse)
> +{
> + u32 val = UINT_MAX;
> +
> + if (revn == 618)
> + val = a618_get_speed_bin(fuse);
> +
> + if (val == UINT_MAX) {
> + DRM_DEV_ERROR(dev,
> + "missing support for speed-bin: %u. Some OPPs may not
> be supported by hardware",
> + fuse);
> + return UINT_MAX;
> + }
> +
> + return (1 << val);
> +}
> +
> +static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu
> *a6xx_gpu,
> + u32 revn)
> +{
> + struct opp_table *opp_table;
> + struct nvmem_cell *cell;
> + u32 supp_hw = UINT_MAX;
> + void *buf;
> +
> + cell = nvmem_cell_get(dev, "speed_bin");
> + /*
> + * -ENOENT means that the platform doesn't support speedbin which is
> + * fine
> + */
> + if (PTR_ERR(cell) == -ENOENT)
> + return 0;
> + else if (IS_ERR(cell)) {
> + DRM_DEV_ERROR(dev,
> + "failed to read speed-bin. Some OPPs may not be
> supported by hardware");
> + goto done;
> + }
> +
> + buf = nvmem_cell_read(cell, NULL);
> + if (IS_ERR(buf)) {
> + nvmem_cell_put(cell);
> + DRM_DEV_ERROR(dev,
> + "failed to read speed-bin. Some OPPs may not be
> supported by hardware");
> + goto done;
> + }
> +
> + supp_hw = fuse_to_supp_hw(dev, revn, *((u32 *) buf));
> +
> + kfree(buf);
> + nvmem_cell_put(cell);
> +
> +done:
> + opp_table = dev_pm_opp_set_supported_hw(dev, &supp_hw, 1);
> + if (IS_ERR(opp_table))
> + return PTR_ERR(opp_table);
> +
> + a6xx_gpu->opp_table = opp_table;
> + return 0;
> +}
> +
> static const struct adreno_gpu_funcs funcs = {
> .base = {
> .get_param = adreno_get_param,
> @@ -1325,6 +1402,12 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
>
> a6xx_llc_slices_init(pdev, a6xx_gpu);
>
> + ret = a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info->revn);
> + if (ret) {
> + a6xx_destroy(&(a6xx_gpu->base.base));
> + return ERR_PTR(ret);
> + }
> +
> ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
> if (ret) {
> a6xx_destroy(&(a6xx_gpu->base.base));
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> index e793d32..ce0610c 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> @@ -33,6 +33,8 @@ struct a6xx_gpu {
> void *llc_slice;
> void *htw_llc_slice;
> bool have_mmu500;
> +
> + struct opp_table *opp_table;
> };
>
> #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base)
> --
> 2.7.4
>
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