[Bug 210683] Nasty amdgpu powersave regression Navi14

2020-12-27 Thread bugzilla-daemon
https://bugzilla.kernel.org/show_bug.cgi?id=210683

--- Comment #9 from Andreas Prittwitz (m4n...@gmx.de) ---
I have done some addtional testing.
I am running an up to date openSUSE Tumleweed with KDE Plasma.
My monitor is capable of running at 60, 100, 120 and 144 Hz refresh rate.

For some reason unknown to me it was set to 60 Hz after the last update.
With this setting it idled at 35 W instead of the usual 11 W.
Also the memory/GPU frequencies come down to what they used to and where they
should be.

After setting it back to 144 Hz, wattage at idle came back down to 11 W.
Setting it back to 60 Hz refresh rate lets the wattage come back up to 35 W.
This is reproducible any time.

Setting it to 100 and 120 Hz resepectively lets the graphics card also idle at
11W.

It seems, at least on my system, that this bug only affects me, when the
monitor is set to 60 Hz refresh rate.

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[Bug 210683] Nasty amdgpu powersave regression Navi14

2020-12-27 Thread bugzilla-daemon
https://bugzilla.kernel.org/show_bug.cgi?id=210683

--- Comment #10 from Andreas Prittwitz (m4n...@gmx.de) ---
I have done some addtional testing.
I am running an up to date openSUSE Tumleweed with KDE Plasma.
My monitor is capable of running at 60, 100, 120 and 144 Hz refresh rate.

For some reason unknown to me it was set to 60 Hz after the last update.
With this setting it idled at 35 W instead of the usual 11 W.

After setting it back to 144 Hz, wattage at idle came back down to 11 W.
Also the memory/GPU frequencies come down to what they used to and where they
should be.

Setting it back to 60 Hz refresh rate lets the wattage come back up to 35 W.
This is reproducible any time.

Setting it to 100 and 120 Hz resepectively lets the graphics card also idle at
11W.

It seems, at least on my system, that this bug only affects me, when the
monitor is set to 60 Hz refresh rate.

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Re: [PATCH 1/2] dt-bindings: Convert Arm Mali Valhall GPU to DT schema

2020-12-27 Thread Rob Herring
On Thu, 24 Dec 2020 20:31:18 +0800, Nick Fan wrote:
> Convert the Arm Valhall GPU binding to DT schema format.
> 
> Define a compatible string for the Mali Valhall GPU
> for Mediatek's SoC platform.
> 
> Signed-off-by: Nick Fan 
> ---
>  .../bindings/gpu/arm,mali-valhall.yaml| 252 ++
>  1 file changed, 252 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
./Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml: $id: relative 
path/filename doesn't match actual path or filename
expected: http://devicetree.org/schemas/gpu/arm,mali-valhall.yaml#

See https://patchwork.ozlabs.org/patch/1420519

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

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Re: [PATCH v1 1/2] dt-bindings: drm/bridge: anx7625: add DPI flag and swing setting

2020-12-27 Thread Rob Herring
On Fri, 25 Dec 2020 19:01:09 +0800, Xin Ji wrote:
> Add DPI flag for distinguish MIPI input signal type, DSI or DPI. Add
> swing setting for adjusting DP tx PHY swing
> 
> Signed-off-by: Xin Ji 
> ---
>  .../bindings/display/bridge/analogix,anx7625.yaml | 19 
> +++
>  1 file changed, 19 insertions(+)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.example.dt.yaml:
 encoder@58: anx,swing-setting: 'anyOf' conditional failed, one must be fixed:
[[0, 20], [1, 84], [2, 100], [3, 116], [4, 41], [5, 123], [6, 119], [7, 
91], [8, 127], [12, 32], [13, 96], [16, 96], [18, 64], [19, 96], [20, 20], [21, 
84], [22, 100], [23, 116], [24, 41], [25, 123], [26, 119], [27, 91], [28, 127], 
[32, 32], [33, 96], [36, 96], [38, 64], [39, 96]] is too long
[0, 20] is too long
[1, 84] is too long
[2, 100] is too long
[3, 116] is too long
[4, 41] is too long
[5, 123] is too long
[6, 119] is too long
[7, 91] is too long
[8, 127] is too long
[12, 32] is too long
[13, 96] is too long
[16, 96] is too long
[18, 64] is too long
[19, 96] is too long
[20, 20] is too long
[21, 84] is too long
[22, 100] is too long
[23, 116] is too long
[24, 41] is too long
[25, 123] is too long
[26, 119] is too long
[27, 91] is too long
[28, 127] is too long
[32, 32] is too long
[33, 96] is too long
[36, 96] is too long
[38, 64] is too long
[39, 96] is too long
From schema: 
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.example.dt.yaml:
 encoder@58: 'anx,mipi-dpi-in', 'anx,swing-setting' do not match any of the 
regexes: '^#.*', 
'^(at25|bm|devbus|dmacap|dsa|exynos|fsi[ab]|gpio-fan|gpio-key|gpio|gpmc|hdmi|i2c-gpio),.*',
 '^(keypad|m25p|max8952|max8997|max8998|mpmc),.*', 
'^(pinctrl-single|#pinctrl-single|PowerPC),.*', 
'^(pl022|pxa-mmc|rcar_sound|rotary-encoder|s5m8767|sdhci),.*', 
'^(simple-audio-card|st-plgpio|st-spics|ts),.*', '^70mai,.*', '^GEFanuc,.*', 
'^ORCL,.*', '^SUNW,.*', '^[a-zA-Z0-9#_][a-zA-Z0-9+\\-._@]{0,63}$', 
'^[a-zA-Z0-9+\\-._]*@[0-9a-zA-Z,]*$', '^abb,.*', '^abilis,.*', '^abracon,.*', 
'^abt,.*', '^acer,.*', '^acme,.*', '^actions,.*', '^active-semi,.*', '^ad,.*', 
'^adafruit,.*', '^adapteva,.*', '^adaptrum,.*', '^adh,.*', '^adi,.*', 
'^advantech,.*', '^aeroflexgaisler,.*', '^al,.*', '^allegro,.*', '^allo,.*', 
'^allwinner,.*', '^alphascale,.*', '^alps,.*', '^alt,.*', '^altr,.*', 
'^amarula,.*', '^
 amazon,.*', '^amcc,.*', '^amd,.*', '^amediatech,.*', '^amlogic,.*', 
'^ampere,.*', '^ampire,.*', '^ams,.*', '^amstaos,.*', '^analogix,.*', 
'^andestech,.*', '^anvo,.*', '^apm,.*', '^aptina,.*', '^arasan,.*', 
'^archermind,.*', '^arctic,.*', '^arcx,.*', '^aries,.*', '^arm,.*', 
'^armadeus,.*', '^arrow,.*', '^artesyn,.*', '^asahi-kasei,.*', '^asc,.*', 
'^aspeed,.*', '^asus,.*', '^atlas,.*', '^atmel,.*', '^auo,.*', '^auvidea,.*', 
'^avago,.*', '^avia,.*', '^avic,.*', '^avnet,.*', '^awinic,.*', '^axentia,.*', 
'^axis,.*', '^azoteq,.*', '^azw,.*', '^baikal,.*', '^bananapi,.*', 
'^beacon,.*', '^beagle,.*', '^bhf,.*', '^bitmain,.*', '^boe,.*', '^bosch,.*', 
'^boundary,.*', '^brcm,.*', '^broadmobi,.*', '^bticino,.*', '^buffalo,.*', 
'^bur,.*', '^calaosystems,.*', '^calxeda,.*', '^caninos,.*', '^capella,.*', 
'^cascoda,.*', '^catalyst,.*', '^cavium,.*', '^cdns,.*', '^cdtech,.*', 
'^cellwise,.*', '^ceva,.*', '^checkpoint,.*', '^chefree,.*', '^chipidea,.*', 
'^chipone,.*', '^chipspark,.*', '^chrontel,.*', 
 '^chrp,.*', '^chunghwa,.*', '^chuwi,.*', '^ciaa,.*', '^cirrus,.*', 
'^cloudengines,.*', '^cnm,.*', '^cnxt,.*', '^colorfly,.*', '^compulab,.*', 
'^coreriver,.*', '^corpro,.*', '^cortina,.*', '^cosmic,.*', '^crane,.*', 
'^creative,.*', '^crystalfontz,.*', '^csky,.*', '^csq,.*', '^cubietech,.*', 
'^cypress,.*', '^cznic,.*', '^dallas,.*', '^dataimage,.*', '^davicom,.*', 
'^dell,.*', '^delta,.*', '^denx,.*', '^devantech,.*', '^dfi,.*', '^dh,.*', 
'^difrnce,.*', '^digi,.*', '^digilent,.*', '^dioo,.*', '^dlc,.*', '^dlg,.*', 
'^dlink,.*', '^dmo,.*', '^domintech,.*', '^dongwoon,.*', '^dptechnics,.*', 
'^dragino,.*', '^dserve,.*', '^dynaimage,.*', '^ea,.*', '^ebs-systart,.*', 
'^ebv,.*', '^eckelmann,.*', '^edt,.*', '^eeti,.*', '^einfochips,.*', 
'^elan,.*', '^element14,.*', '^elgin,.*', '^elida,.*', '^elimo,.*', 
'^embest,.*', '^emlid,.*', '^emmicro,.*', '^empire-electronix,.*', 
'^emtrion,.*', '^endless,.*', '^ene,.*', '^energymicro,.*', '^engicam,.*', 
'^epcos,.*', '^epfl,.*', '^epson,.*', '^esp,.*', '^
 est,.*', '^ettus,.*', '^eukrea,.*', '^everest,.*', '^everspin,.*', 

Re: [bug] Radeon 3900XT not switch to graphic mode on kernel 5.10

2020-12-27 Thread Mikhail Gavrilov
On Sun, 27 Dec 2020 at 21:39, Mikhail Gavrilov
 wrote:
> I suppose the root of cause my problem here:
>
> [3.961326] amdgpu :0b:00.0: Direct firmware load for
> amdgpu/sienna_cichlid_sos.bin failed with error -2
> [3.961359] amdgpu :0b:00.0: amdgpu: failed to init sos firmware
> [3.961433] [drm:psp_sw_init [amdgpu]] *ERROR* Failed to load psp firmware!
> [3.961529] [drm:amdgpu_device_init.cold [amdgpu]] *ERROR* sw_init
> of IP block  failed -2
> [3.961549] amdgpu :0b:00.0: amdgpu: amdgpu_device_ip_init failed
> [3.961569] amdgpu :0b:00.0: amdgpu: Fatal error during GPU init
> [3.961911] amdgpu: probe of :0b:00.0 failed with error -2
>

# dnf provides */sienna_cichlid_sos.bin
Last metadata expiration check: 3:01:27 ago on Sun 27 Dec 2020 06:53:25 PM +05.
linux-firmware-20201218-116.fc34.noarch : Firmware files used by the
Linux kernel
Repo: @System
Matched from:
Filename: /usr/lib/firmware/amdgpu/sienna_cichlid_sos.bin

linux-firmware-20201218-116.fc34.noarch : Firmware files used by the
Linux kernel
Repo: rawhide
Matched from:
Filename: /usr/lib/firmware/amdgpu/sienna_cichlid_sos.bin

# dnf install linux-firmware-20201218-116.fc34.noarch
Last metadata expiration check: 3:02:11 ago on Sun 27 Dec 2020 06:53:25 PM +05.
Package linux-firmware-20201218-116.fc34.noarch is already installed.
Dependencies resolved.
Nothing to do.
Complete!

Looks like firmware is present. So I didn't understand why the kernel
cannot read firmware.

--
Best Regards,
Mike Gavrilov.
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Re: [bug] Radeon 3900XT not switch to graphic mode on kernel 5.10

2020-12-27 Thread Ernst Sjöstrand
-2 means no such file or directory. Perhaps you need to rebuild your
ramdisk manually for some reason.

Regards
//Ernst

Den sön 27 dec. 2020 kl 17:58 skrev Mikhail Gavrilov <
mikhail.v.gavri...@gmail.com>:

> On Sun, 27 Dec 2020 at 21:39, Mikhail Gavrilov
>  wrote:
> > I suppose the root of cause my problem here:
> >
> > [3.961326] amdgpu :0b:00.0: Direct firmware load for
> > amdgpu/sienna_cichlid_sos.bin failed with error -2
> > [3.961359] amdgpu :0b:00.0: amdgpu: failed to init sos firmware
> > [3.961433] [drm:psp_sw_init [amdgpu]] *ERROR* Failed to load psp
> firmware!
> > [3.961529] [drm:amdgpu_device_init.cold [amdgpu]] *ERROR* sw_init
> > of IP block  failed -2
> > [3.961549] amdgpu :0b:00.0: amdgpu: amdgpu_device_ip_init failed
> > [3.961569] amdgpu :0b:00.0: amdgpu: Fatal error during GPU init
> > [3.961911] amdgpu: probe of :0b:00.0 failed with error -2
> >
>
> # dnf provides */sienna_cichlid_sos.bin
> Last metadata expiration check: 3:01:27 ago on Sun 27 Dec 2020 06:53:25 PM
> +05.
> linux-firmware-20201218-116.fc34.noarch : Firmware files used by the
> Linux kernel
> Repo: @System
> Matched from:
> Filename: /usr/lib/firmware/amdgpu/sienna_cichlid_sos.bin
>
> linux-firmware-20201218-116.fc34.noarch : Firmware files used by the
> Linux kernel
> Repo: rawhide
> Matched from:
> Filename: /usr/lib/firmware/amdgpu/sienna_cichlid_sos.bin
>
> # dnf install linux-firmware-20201218-116.fc34.noarch
> Last metadata expiration check: 3:02:11 ago on Sun 27 Dec 2020 06:53:25 PM
> +05.
> Package linux-firmware-20201218-116.fc34.noarch is already installed.
> Dependencies resolved.
> Nothing to do.
> Complete!
>
> Looks like firmware is present. So I didn't understand why the kernel
> cannot read firmware.
>
> --
> Best Regards,
> Mike Gavrilov.
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[Bug 210921] New: amdgpu on Radeon R9 280X floods "[drm] Display Core has been requested via kernel parameter but isn't supported by ASIC, ignoring"

2020-12-27 Thread bugzilla-daemon
https://bugzilla.kernel.org/show_bug.cgi?id=210921

Bug ID: 210921
   Summary: amdgpu on Radeon R9 280X floods "[drm] Display Core
has been requested via kernel parameter but isn't
supported by ASIC, ignoring"
   Product: Drivers
   Version: 2.5
Kernel Version: 5.9.14
  Hardware: All
OS: Linux
  Tree: Mainline
Status: NEW
  Severity: low
  Priority: P1
 Component: Video(DRI - non Intel)
  Assignee: drivers_video-...@kernel-bugs.osdl.org
  Reporter: alexandre.f.dem...@gmail.com
Regression: No

A small extract of what is spurted in logs when using an Radeon R9 280X with
amdgpu.

[...]
[47837.292590] [drm] Display Core has been requested via kernel parameter but
isn't supported by ASIC, ignoring
[47837.409321] [drm] Display Core has been requested via kernel parameter but
isn't supported by ASIC, ignoring
[47837.553302] [drm] Display Core has been requested via kernel parameter but
isn't supported by ASIC, ignoring
[47837.640563] [drm] Display Core has been requested via kernel parameter but
isn't supported by ASIC, ignoring
[...]

My R9 280X was put aside in the last year for a Vega FE. However, I'm back at
working on VCE 1 and this is one of the things I've found out since plugging
the card in. I don't see why we should continually print (and at that pace...)
that this is not supported. Report it once and move along.

I've narrowed down the issue to line 3037 in
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c. DRM_INFO should be replaced by
DRM_INFO_ONCE.

By the way, the card is still rock solid for any regular work and many games in
my library.

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[Bug 210321] /display/dc/dcn20/dcn20_resource.c:3240 dcn20_validate_bandwidth_fp+0x8b/0xd0 [amdgpu]

2020-12-27 Thread bugzilla-daemon
https://bugzilla.kernel.org/show_bug.cgi?id=210321

Florian Evers (florian-ev...@gmx.de) changed:

   What|Removed |Added

 CC||florian-ev...@gmx.de

--- Comment #1 from Florian Evers (florian-ev...@gmx.de) ---
Similar issue un my box. Today I updated from kernel 5.9.16 to kernel 5.10.3
and found this in the dmesg log:


[So Dez 27 19:12:10 2020] [ cut here ]
[So Dez 27 19:12:10 2020] WARNING: CPU: 16 PID: 4138 at
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:3240
dcn20_validate_bandwidth_fp+0x8b/0xd0
[So Dez 27 19:12:10 2020] CPU: 16 PID: 4138 Comm: X Tainted: GT
5.10.3-gentoo #1
[So Dez 27 19:12:10 2020] Hardware name: Gigabyte Technology Co., Ltd. X570
AORUS MASTER/X570 AORUS MASTER, BIOS F30 09/07/2020
[So Dez 27 19:12:10 2020] RIP: 0010:dcn20_validate_bandwidth_fp+0x8b/0xd0
[So Dez 27 19:12:10 2020] Code: 01 7b 2b 22 85 0c 1f 00 00 75 25 31 d2 f2 0f 11
85 50 26 00 00 48 89 ee 4c 89 e7 e8 cf f5 ff ff 89 c2 22 95 0c 1f 00 00 75 32
<0f> 0b eb 02 75 d3 f2 0f 10 14 24 f2 0f 11 95 50 26 00 00 48 83 c4
[So Dez 27 19:12:10 2020] RSP: 0018:9af6c5203b50 EFLAGS: 00010246
[So Dez 27 19:12:10 2020] RAX: 0001 RBX:  RCX:
0000
[So Dez 27 19:12:10 2020] RDX:  RSI: 1f37e77bc0bcc6d8 RDI:
0002adc0
[So Dez 27 19:12:10 2020] RBP: 8bceb4de R08: 0006 R09:

[So Dez 27 19:12:10 2020] R10: 8bcd4360 R11: 00010001 R12:
8bcd4360
[So Dez 27 19:12:10 2020] R13: 8bcd4360 R14: 8bcd40ca4c90 R15:
8bcd42ee0308
[So Dez 27 19:12:10 2020] FS:  7fb79eed18c0() GS:8bdc3f00()
knlGS:
[So Dez 27 19:12:10 2020] CS:  0010 DS:  ES:  CR0: 80050033
[So Dez 27 19:12:10 2020] CR2: 5613b60d8608 CR3: 00011a3a8000 CR4:
00350ee0
[So Dez 27 19:12:10 2020] Call Trace:
[So Dez 27 19:12:10 2020]  dcn20_validate_bandwidth+0x1f/0x30
[So Dez 27 19:12:10 2020]  dc_validate_global_state+0x22f/0x2a0
[So Dez 27 19:12:10 2020]  amdgpu_dm_atomic_check+0xb02/0xbe0
[So Dez 27 19:12:10 2020]  drm_atomic_check_only+0x584/0x800
[So Dez 27 19:12:10 2020]  ? _raw_spin_unlock_irqrestore+0xf/0x30
[So Dez 27 19:12:10 2020]  drm_atomic_commit+0xe/0x50
[So Dez 27 19:12:10 2020]  drm_atomic_connector_commit_dpms+0xd2/0xf0
[So Dez 27 19:12:10 2020]  drm_mode_obj_set_property_ioctl+0x193/0x3d0
[So Dez 27 19:12:10 2020]  ? drm_connector_set_obj_prop+0x80/0x80
[So Dez 27 19:12:10 2020]  drm_connector_property_set_ioctl+0x3c/0x60
[So Dez 27 19:12:10 2020]  drm_ioctl_kernel+0xad/0xf0
[So Dez 27 19:12:10 2020]  drm_ioctl+0x215/0x390
[So Dez 27 19:12:10 2020]  ? drm_connector_set_obj_prop+0x80/0x80
[So Dez 27 19:12:10 2020]  amdgpu_drm_ioctl+0x44/0x80
[So Dez 27 19:12:10 2020]  __x64_sys_ioctl+0x7e/0xb0
[So Dez 27 19:12:10 2020]  do_syscall_64+0x33/0x80
[So Dez 27 19:12:10 2020]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[So Dez 27 19:12:10 2020] RIP: 0033:0x7fb79f103d77
[So Dez 27 19:12:10 2020] Code: 01 75 a5 49 8d 3c 1c e8 f7 fe ff ff 85 c0 78 a6
5b 4c 89 e0 5d 41 5c c3 66 2e 0f 1f 84 00 00 00 00 00 90 b8 10 00 00 00 0f 05
<48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d c1 70 0c 00 f7 d8 64 89 01 48
[So Dez 27 19:12:10 2020] RSP: 002b:7ffddf8e14d8 EFLAGS: 0246 ORIG_RAX:
0010
[So Dez 27 19:12:10 2020] RAX: ffda RBX: 7ffddf8e1510 RCX:
7fb79f103d77
[So Dez 27 19:12:10 2020] RDX: 7ffddf8e1510 RSI: c01064ab RDI:
000c
[So Dez 27 19:12:10 2020] RBP: c01064ab R08:  R09:
7fb79f7d1d10
[So Dez 27 19:12:10 2020] R10: 7fb79f7d1d20 R11: 0246 R12:
5613b703c390
[So Dez 27 19:12:10 2020] R13: 000c R14:  R15:
5613b6113e00
[So Dez 27 19:12:10 2020] ---[ end trace 4936e0098b209a6c ]---


waterstation ~ # emerge --info
Portage 3.0.9 (python 3.8.6-final-0, default/linux/amd64/17.1/desktop/plasma,
gcc-9.3.0, glibc-2.32-r3, 5.10.3-gentoo x86_64)
=
System uname:
Linux-5.10.3-gentoo-x86_64-AMD_Ryzen_9_3900X_12-Core_Processor-with-glibc2.2.5
KiB Mem:65794276 total,  56616072 free
KiB Swap:   16864252 total,  16864252 free
Timestamp of repository gentoo: Sun, 27 Dec 2020 15:00:01 +
Head commit of repository gentoo: 465bb6880edff24a20d24e074a4da935c3be4123
sh bash 5.0_p18
ld GNU ld (Gentoo 2.34 p6) 2.34.0
app-shells/bash:  5.0_p18::gentoo
dev-java/java-config: 2.3.1::gentoo
dev-lang/perl:5.30.3::gentoo
dev-lang/python:  2.7.18-r4::gentoo, 3.7.9::gentoo, 3.8.6::gentoo,
3.9.0::gentoo
dev-util/cmake:   3.17.4-r1::gentoo
dev-util/pkgconfig:   0.29.2::gentoo
sys-apps/baselayout:  2.7::gentoo
sys-apps/openrc:  0.42.1::gentoo
sys-apps/sandbox: 2

Re: [bug] Radeon 3900XT not switch to graphic mode on kernel 5.10

2020-12-27 Thread Bridgman, John
[AMD Official Use Only - Internal Distribution Only]

If you want to pick up the firmware directly it is maintained at...

https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/amdgpu


-rw-r--r-- sienna_cichlid_ce.bin 263296   logstatsplain
-rw-r--r-- sienna_cichlid_dmcub.bin 80244 logstatsplain
-rw-r--r-- sienna_cichlid_me.bin 263424   logstatsplain
-rw-r--r-- sienna_cichlid_mec.bin 268592  logstatsplain
-rw-r--r-- sienna_cichlid_mec2.bin 268592 logstatsplain
-rw-r--r-- sienna_cichlid_pfp.bin 263424  logstatsplain
-rw-r--r-- sienna_cichlid_rlc.bin 128592  logstatsplain
-rw-r--r-- sienna_cichlid_sdma.bin 34048  logstatsplain
-rw-r--r-- sienna_cichlid_smc.bin 247396  logstatsplain
-rw-r--r-- sienna_cichlid_sos.bin 215152  logstatsplain
-rw-r--r-- sienna_cichlid_ta.bin 333568   logstatsplain
-rw-r--r-- sienna_cichlid_vcn.bin 504224  logstatsplain

My understanding was that the firmware was also added to Fedora back in 
November but I'm having a tough time finding confirmation of that.



From: amd-gfx  on behalf of Mikhail 
Gavrilov 
Sent: December 27, 2020 11:39 AM
To: amd-gfx list ; Linux List Kernel Mailing 
; dri-devel 
Subject: [bug] Radeon 3900XT not switch to graphic mode on kernel 5.10

Hi folks.
I bought myself a gift a new AMD 6900 XT graphics card to replace the
AMD Radeon VII.
But all joy was overshadowed that this video card did not working in Linux.
Output on the my boot screen was ended with message "fb0: switching to
amdgpudrmfb from EFI VGA" and videocard not switched to graphic mode.
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fphotos.app.goo.gl%2FzwpErNrusq9CNyES7&data=04%7C01%7Cjohn.bridgman%40amd.com%7C37ba164fc80241451b9808d8aa864aa2%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637446841356919588%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C2000&sdata=Y3V3lbEaXNwHiakgRUAeO7gBJASeElBaIwZ9Vmd0AgU%3D&reserved=0

I suppose the root of cause my problem here:

[3.961326] amdgpu :0b:00.0: Direct firmware load for
amdgpu/sienna_cichlid_sos.bin failed with error -2
[3.961359] amdgpu :0b:00.0: amdgpu: failed to init sos firmware
[3.961433] [drm:psp_sw_init [amdgpu]] *ERROR* Failed to load psp firmware!
[3.961529] [drm:amdgpu_device_init.cold [amdgpu]] *ERROR* sw_init
of IP block  failed -2
[3.961549] amdgpu :0b:00.0: amdgpu: amdgpu_device_ip_init failed
[3.961569] amdgpu :0b:00.0: amdgpu: Fatal error during GPU init
[3.961911] amdgpu: probe of :0b:00.0 failed with error -2

Can anybody here help me get firmware?
my distro: Fedora Rawhide
kernel: 5.10 rc6
mesa: from git 21.0.0 devel

Sorry for disturb and merry xmas.


--
Best Regards,
Mike Gavrilov.
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel


[PATCH V3] drm/ast: Fixed CVE for DP501

2020-12-27 Thread KuoHsiang Chou
[Bug][DP501]
If ASPEED P2A (PCI to AHB) bridge is disabled and disallowed for
CVE_2019_6260 item3, and then the monitor's EDID is unable read through
Parade DP501.
The reason is the DP501's FW is mapped to BMC addressing space rather
than Host addressing space.
The resolution is that using "pci_iomap_range()" maps to DP501's FW that
stored on the end of FB (Frame Buffer).
0In this case, FrameBuffer reserves the last 2MB used for the image of
DP501.

Signed-off-by: KuoHsiang Chou 
Reported-by: kernel test robot 
---
 drivers/gpu/drm/ast/ast_dp501.c | 139 +++-
 drivers/gpu/drm/ast/ast_drv.h   |  12 +++
 drivers/gpu/drm/ast/ast_main.c  |   8 ++
 3 files changed, 123 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/ast/ast_dp501.c b/drivers/gpu/drm/ast/ast_dp501.c
index 88121c0e0d05..cd93c44f2662 100644
--- a/drivers/gpu/drm/ast/ast_dp501.c
+++ b/drivers/gpu/drm/ast/ast_dp501.c
@@ -189,6 +189,9 @@ bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 
size)
u32 i, data;
u32 boot_address;

+   if (ast->config_mode != ast_use_p2a)
+   return false;
+
data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
if (data) {
boot_address = get_fw_base(ast);
@@ -207,6 +210,9 @@ static bool ast_launch_m68k(struct drm_device *dev)
u8 *fw_addr = NULL;
u8 jreg;

+   if (ast->config_mode != ast_use_p2a)
+   return false;
+
data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
if (!data) {

@@ -271,25 +277,55 @@ u8 ast_get_dp501_max_clk(struct drm_device *dev)
struct ast_private *ast = to_ast_private(dev);
u32 boot_address, offset, data;
u8 linkcap[4], linkrate, linklanes, maxclk = 0xff;
+   u32 *plinkcap;

-   boot_address = get_fw_base(ast);
-
-   /* validate FW version */
-   offset = 0xf000;
-   data = ast_mindwm(ast, boot_address + offset);
-   if ((data & 0xf0) != 0x10) /* version: 1x */
-   return maxclk;
-
-   /* Read Link Capability */
-   offset  = 0xf014;
-   *(u32 *)linkcap = ast_mindwm(ast, boot_address + offset);
-   if (linkcap[2] == 0) {
-   linkrate = linkcap[0];
-   linklanes = linkcap[1];
-   data = (linkrate == 0x0a) ? (90 * linklanes) : (54 * linklanes);
-   if (data > 0xff)
-   data = 0xff;
-   maxclk = (u8)data;
+   if (ast->config_mode == ast_use_p2a) {
+   boot_address = get_fw_base(ast);
+
+   /* validate FW version */
+   offset = AST_DP501_GBL_VERSION;
+   data = ast_mindwm(ast, boot_address + offset);
+   if ((data & AST_DP501_FW_VERSION_MASK) != 
AST_DP501_FW_VERSION_1) /* version: 1x */
+   return maxclk;
+
+   /* Read Link Capability */
+   offset  = AST_DP501_LINKRATE;
+   plinkcap = (u32 *)linkcap;
+   *plinkcap  = ast_mindwm(ast, boot_address + offset);
+   if (linkcap[2] == 0) {
+   linkrate = linkcap[0];
+   linklanes = linkcap[1];
+   data = (linkrate == 0x0a) ? (90 * linklanes) : (54 * 
linklanes);
+   if (data > 0xff)
+   data = 0xff;
+   maxclk = (u8)data;
+   }
+   } else {
+   if (!ast->dp501_fw_buf)
+   return AST_DP501_DEFAULT_DCLK;  /* 1024x768 as default 
*/
+
+   /* dummy read */
+   offset = 0x;
+   data = readl(ast->dp501_fw_buf + offset);
+
+   /* validate FW version */
+   offset = AST_DP501_GBL_VERSION;
+   data = readl(ast->dp501_fw_buf + offset);
+   if ((data & AST_DP501_FW_VERSION_MASK) != 
AST_DP501_FW_VERSION_1) /* version: 1x */
+   return maxclk;
+
+   /* Read Link Capability */
+   offset = AST_DP501_LINKRATE;
+   plinkcap = (u32 *)linkcap;
+   *plinkcap = readl(ast->dp501_fw_buf + offset);
+   if (linkcap[2] == 0) {
+   linkrate = linkcap[0];
+   linklanes = linkcap[1];
+   data = (linkrate == 0x0a) ? (90 * linklanes) : (54 * 
linklanes);
+   if (data > 0xff)
+   data = 0xff;
+   maxclk = (u8)data;
+   }
}
return maxclk;
 }
@@ -298,26 +334,57 @@ bool ast_dp501_read_edid(struct drm_device *dev, u8 
*ediddata)
 {
struct ast_private *ast = to_ast_private(dev);
u32 i, boot_address, offset, data;
+   u32 *pEDIDidx;

-   boot_address = get_fw_base(ast);
-
-   /* validate FW version */
-   offset = 0xf000;
-   data = ast_mindwm(ast, boot_address + offset);
-   if ((data & 0xf0) != 0x10)
-   return false;
-
-

[PATCH V3] drm/ast: Fixed CVE for DP501

2020-12-27 Thread KuoHsiang Chou
[Bug][DP501]
If ASPEED P2A (PCI to AHB) bridge is disabled and disallowed for
CVE_2019_6260 item3, and then the monitor's EDID is unable read through
Parade DP501.
The reason is the DP501's FW is mapped to BMC addressing space rather
than Host addressing space.
The resolution is that using "pci_iomap_range()" maps to DP501's FW that
stored on the end of FB (Frame Buffer).
0In this case, FrameBuffer reserves the last 2MB used for the image of
DP501.

Signed-off-by: KuoHsiang Chou 
Reported-by: kernel test robot 
---
 drivers/gpu/drm/ast/ast_dp501.c | 139 +++-
 drivers/gpu/drm/ast/ast_drv.h   |  12 +++
 drivers/gpu/drm/ast/ast_main.c  |   8 ++
 3 files changed, 123 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/ast/ast_dp501.c b/drivers/gpu/drm/ast/ast_dp501.c
index 88121c0e0d05..cd93c44f2662 100644
--- a/drivers/gpu/drm/ast/ast_dp501.c
+++ b/drivers/gpu/drm/ast/ast_dp501.c
@@ -189,6 +189,9 @@ bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 
size)
u32 i, data;
u32 boot_address;

+   if (ast->config_mode != ast_use_p2a)
+   return false;
+
data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
if (data) {
boot_address = get_fw_base(ast);
@@ -207,6 +210,9 @@ static bool ast_launch_m68k(struct drm_device *dev)
u8 *fw_addr = NULL;
u8 jreg;

+   if (ast->config_mode != ast_use_p2a)
+   return false;
+
data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
if (!data) {

@@ -271,25 +277,55 @@ u8 ast_get_dp501_max_clk(struct drm_device *dev)
struct ast_private *ast = to_ast_private(dev);
u32 boot_address, offset, data;
u8 linkcap[4], linkrate, linklanes, maxclk = 0xff;
+   u32 *plinkcap;

-   boot_address = get_fw_base(ast);
-
-   /* validate FW version */
-   offset = 0xf000;
-   data = ast_mindwm(ast, boot_address + offset);
-   if ((data & 0xf0) != 0x10) /* version: 1x */
-   return maxclk;
-
-   /* Read Link Capability */
-   offset  = 0xf014;
-   *(u32 *)linkcap = ast_mindwm(ast, boot_address + offset);
-   if (linkcap[2] == 0) {
-   linkrate = linkcap[0];
-   linklanes = linkcap[1];
-   data = (linkrate == 0x0a) ? (90 * linklanes) : (54 * linklanes);
-   if (data > 0xff)
-   data = 0xff;
-   maxclk = (u8)data;
+   if (ast->config_mode == ast_use_p2a) {
+   boot_address = get_fw_base(ast);
+
+   /* validate FW version */
+   offset = AST_DP501_GBL_VERSION;
+   data = ast_mindwm(ast, boot_address + offset);
+   if ((data & AST_DP501_FW_VERSION_MASK) != 
AST_DP501_FW_VERSION_1) /* version: 1x */
+   return maxclk;
+
+   /* Read Link Capability */
+   offset  = AST_DP501_LINKRATE;
+   plinkcap = (u32 *)linkcap;
+   *plinkcap  = ast_mindwm(ast, boot_address + offset);
+   if (linkcap[2] == 0) {
+   linkrate = linkcap[0];
+   linklanes = linkcap[1];
+   data = (linkrate == 0x0a) ? (90 * linklanes) : (54 * 
linklanes);
+   if (data > 0xff)
+   data = 0xff;
+   maxclk = (u8)data;
+   }
+   } else {
+   if (!ast->dp501_fw_buf)
+   return AST_DP501_DEFAULT_DCLK;  /* 1024x768 as default 
*/
+
+   /* dummy read */
+   offset = 0x;
+   data = readl(ast->dp501_fw_buf + offset);
+
+   /* validate FW version */
+   offset = AST_DP501_GBL_VERSION;
+   data = readl(ast->dp501_fw_buf + offset);
+   if ((data & AST_DP501_FW_VERSION_MASK) != 
AST_DP501_FW_VERSION_1) /* version: 1x */
+   return maxclk;
+
+   /* Read Link Capability */
+   offset = AST_DP501_LINKRATE;
+   plinkcap = (u32 *)linkcap;
+   *plinkcap = readl(ast->dp501_fw_buf + offset);
+   if (linkcap[2] == 0) {
+   linkrate = linkcap[0];
+   linklanes = linkcap[1];
+   data = (linkrate == 0x0a) ? (90 * linklanes) : (54 * 
linklanes);
+   if (data > 0xff)
+   data = 0xff;
+   maxclk = (u8)data;
+   }
}
return maxclk;
 }
@@ -298,26 +334,57 @@ bool ast_dp501_read_edid(struct drm_device *dev, u8 
*ediddata)
 {
struct ast_private *ast = to_ast_private(dev);
u32 i, boot_address, offset, data;
+   u32 *pEDIDidx;

-   boot_address = get_fw_base(ast);
-
-   /* validate FW version */
-   offset = 0xf000;
-   data = ast_mindwm(ast, boot_address + offset);
-   if ((data & 0xf0) != 0x10)
-   return false;
-
-