date:20201119




Am 05.11.20 um 14:56 schrieb Maxime Ripard:

The code that assigns HVS channels during atomic_check is starting to grow
a bit big, let's move it into a separate function.

Reviewed-by: Hoegeun Kwon 
Tested-by: Hoegeun Kwon 
Signed-off-by: Maxime Ripard 
---
  drivers/gpu/drm/vc4/vc4_kms.c | 18 +++---
  1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index ad69c70f66a2..bb2efc5d2d01 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -662,13 +662,13 @@ static int vc4_load_tracker_obj_init(struct vc4_dev *vc4)
return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, 
NULL);
  }
  
-static int

-vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
+static int vc4_pv_muxing_atomic_check(struct drm_device *dev,
+ struct drm_atomic_state *state)
  {
unsigned long unassigned_channels = GENMASK(HVS_NUM_CHANNELS - 1, 0);
struct drm_crtc_state *old_crtc_state, *new_crtc_state;
struct drm_crtc *crtc;
-   int i, ret;
+   unsigned int i;


Thanks for fixing the type. It's always itching me when people use 
signed types for counters and array indices. It's just... not right. :) 
If you want to be super-correct you might as well make it size_t. Anyway


Reviewed-by: Thomas Zimmermann 

  
  	/*

 * Since the HVS FIFOs are shared across all the pixelvalves and
@@ -741,6 +741,18 @@ vc4_atomic_check(struct drm_device *dev, struct 
drm_atomic_state *state)
}
}
  
+	return 0;

+}
+
+static int
+vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
+{
+   int ret;
+
+   ret = vc4_pv_muxing_atomic_check(dev, state);
+   if (ret)
+   return ret;
+
ret = vc4_ctm_atomic_check(dev, state);
if (ret < 0)
return ret;



--
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(HRB 36809, AG Nürnberg)
Geschäftsführer: Felix Imendörffer


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Re: [PATCH v2 8/8] drm/amdgpu: Prevent any job recoveries after device is unplugged.

2020-11-19 Thread Christian König


Am 18.11.20 um 17:20 schrieb Andrey Grodzovsky:


On 11/18/20 7:01 AM, Christian König wrote:

Am 18.11.20 um 08:39 schrieb Daniel Vetter:

On Tue, Nov 17, 2020 at 9:07 PM Andrey Grodzovsky
 wrote:


On 11/17/20 2:49 PM, Daniel Vetter wrote:

On Tue, Nov 17, 2020 at 02:18:49PM -0500, Andrey Grodzovsky wrote:

On 11/17/20 1:52 PM, Daniel Vetter wrote:

On Tue, Nov 17, 2020 at 01:38:14PM -0500, Andrey Grodzovsky wrote:

On 6/22/20 5:53 AM, Daniel Vetter wrote:
On Sun, Jun 21, 2020 at 02:03:08AM -0400, Andrey Grodzovsky 
wrote:
No point to try recovery if device is gone, just messes up 
things.


Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 16 


 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 8 
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

index 6932d75..5d6d3d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1129,12 +1129,28 @@ static int amdgpu_pci_probe(struct 
pci_dev *pdev,

  return ret;
 }
+static void amdgpu_cancel_all_tdr(struct amdgpu_device *adev)
+{
+    int i;
+
+    for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
+    struct amdgpu_ring *ring = adev->rings[i];
+
+    if (!ring || !ring->sched.thread)
+    continue;
+
+ cancel_delayed_work_sync(&ring->sched.work_tdr);
+    }
+}
I think this is a function that's supposed to be in 
drm/scheduler, not
here. Might also just be your cleanup code being ordered 
wrongly, or your

split in one of the earlier patches not done quite right.
-Daniel
This function iterates across all the schedulers per amdgpu 
device and accesses
amdgpu specific structures , drm/scheduler deals with single 
scheduler at most

so looks to me like this is the right place for this function
I guess we could keep track of all schedulers somewhere in a 
list in

struct drm_device and wrap this up. That was kinda the idea.

Minimally I think a tiny wrapper with docs for the
cancel_delayed_work_sync(&sched->work_tdr); which explains what 
you must

observe to make sure there's no race.

Will do



I'm not exactly sure there's no
guarantee here we won't get a new tdr work launched right 
afterwards at

least, so this looks a bit like a hack.

Note that for any TDR work happening post amdgpu_cancel_all_tdr
amdgpu_job_timedout->drm_dev_is_unplugged
will return true and so it will return early. To make it water 
proof tight

against race
i can switch from drm_dev_is_unplugged to drm_dev_enter/exit
Hm that's confusing. You do a work_cancel_sync, so that at least 
looks

like "tdr work must not run after this point"

If you only rely on drm_dev_enter/exit check with the tdr work, then
there's no need to cancel anything.


Agree, synchronize_srcu from drm_dev_unplug should play the role
of 'flushing' any earlier (in progress) tdr work which is
using drm_dev_enter/exit pair. Any later arising tdr will terminate 
early when

drm_dev_enter
returns false.

Nope, anything you put into the work itself cannot close this race.
It's the schedule_work that matters here. Or I'm missing something ...
I thought that the tdr work you're cancelling here is launched by
drm/scheduler code, not by the amd callback?



My bad, you are right, I am supposed to put drm_dev_enter.exit pair 
into drm_sched_job_timedout





Yes that is correct. Canceling the work item is not the right 
approach at all, nor is adding dev_enter/exit pair in the recovery 
handler.



Without adding the dev_enter/exit guarding pair in the recovery 
handler you are ending up with GPU reset starting while
the device is already unplugged, this leads to multiple errors and 
general mess.





What we need to do here is to stop the scheduler thread and then wait 
for any timeout handling to have finished.


Otherwise it can scheduler a new timeout just after we have canceled 
this one.


Regards,
Christian.



Schedulers are stopped from amdgpu_driver_unload_kms which indeed 
happens after drm_dev_unplug
so yes, there is still a chance for new work being scheduler and 
timeout armed after but, once i fix the code
to place drm_dev_enter/exit pair into drm_sched_job_timeout I don't 
see why that not a good solution ?


Yeah that should work as well, but then you also don't need to cancel 
the work item from the driver.


Any tdr work started after drm_dev_unplug finished will simply abort 
on entry to drm_sched_job_timedout
because drm_dev_enter will be false and the function will return 
without rearming the timeout timer and

so will have no impact.

The only issue i see here now is of possible use after free if some 
late tdr work will try to execute after
drm device already gone, for this we probably should add 
cancel_delayed_work_sync(sched.work_tdr)

to drm_sched_fini after sched->thread is stopped there.


Good point, that is indeed missing as far as I can see.

Chr

Re: [PATCH v3 5/7] drm/vc4: kms: Document the muxing corner cases


Hi,

A few suggestions below. But I'm not a native speaker.

Am 05.11.20 um 14:56 schrieb Maxime Ripard:

We've had a number of muxing corner-cases with specific ways to reproduce
them, so let's document them to make sure they aren't lost and introduce
regressions later on.

Reviewed-by: Hoegeun Kwon 
Tested-by: Hoegeun Kwon 
Signed-off-by: Maxime Ripard 
---
  drivers/gpu/drm/vc4/vc4_kms.c | 22 ++
  1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index bb2efc5d2d01..499c6914fce4 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -662,6 +662,28 @@ static int vc4_load_tracker_obj_init(struct vc4_dev *vc4)
return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, 
NULL);
  }
  
+/*

+ * The BCM2711 HVS has up to 7 output connected to the pixelvalves and


'7 outputs'

Is it 'pixelvalves' or 'pixel valves'?


+ * the TXP (and therefore all the CRTCs found on that platform).
+ *
+ * The naive (and our initial) implementation would just iterate over
+ * all the active CRTCs, try to find a suitable FIFO, and then remove it
+ * from the available FIFOs pool. However, there's a few corner cases


I'd write. 'and remove it from the pool of available FIFOs'. Sounds more 
natural to me.


'there are a few'


+ * that need to be considered:
+ *
+ * - When running in a dual-display setup (so with two CRTCs involved),
+ *   we can update the state of a single CRTC (for example by changing
+ *   its mode using xrandr under X11) without affecting the other. In
+ *   this case, the other CRTC wouldn't be in the state at all, so we
+ *   need to consider all the running CRTCs in the DRM device to assign
+ *   a FIFO, not just the one in the state.
+ *
+ * - Since we need the pixelvalve to be disabled and enabled back when
+ *   the FIFO is changed, we should keep the FIFO assigned for as long
+ *   as the CRTC is enabled, only considering it free again once that
+ *   CRTC has been disabled. This can be tested by booting X11 on a
+ *   single display, and changing the resolution down and then back up.
+ */


With my suggestions considered,

Acked-by: Thomas Zimmermann 


  static int vc4_pv_muxing_atomic_check(struct drm_device *dev,
  struct drm_atomic_state *state)
  {



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Re: [PATCH v3 1/7] drm/vc4: kms: Switch to drmm_add_action_or_reset




Am 05.11.20 um 14:56 schrieb Maxime Ripard:

Even though it was pointed in the review by Daniel, and I thought to have
fixed it while applying the patches, but it turns out I forgot to commit
the fixes in the process. Properly fix it this time.

Fixes: dcda7c28bff2 ("drm/vc4: kms: Add functions to create the state objects")
Signed-off-by: Maxime Ripard 


Reviewed-by: Thomas Zimmermann 


---
  drivers/gpu/drm/vc4/vc4_kms.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index 2b951cae04ad..44db31e16e91 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -113,7 +113,7 @@ static int vc4_ctm_obj_init(struct vc4_dev *vc4)
drm_atomic_private_obj_init(&vc4->base, &vc4->ctm_manager, 
&ctm_state->base,
&vc4_ctm_state_funcs);
  
-	return drmm_add_action(&vc4->base, vc4_ctm_obj_fini, NULL);

+   return drmm_add_action_or_reset(&vc4->base, vc4_ctm_obj_fini, NULL);
  }
  
  /* Converts a DRM S31.32 value to the HW S0.9 format. */

@@ -657,7 +657,7 @@ static int vc4_load_tracker_obj_init(struct vc4_dev *vc4)
&load_state->base,
&vc4_load_tracker_state_funcs);
  
-	return drmm_add_action(&vc4->base, vc4_load_tracker_obj_fini, NULL);

+   return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, 
NULL);
  }
  
  #define NUM_OUTPUTS  6




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Re: [PATCH v3 3/7] drm/vc4: kms: Rename NUM_CHANNELS




Am 05.11.20 um 14:56 schrieb Maxime Ripard:

The NUM_CHANNELS define has a pretty generic name and was right before the
function using it. Let's move to something that makes the hardware-specific
nature more obvious, and to a more appropriate place.

Reviewed-by: Hoegeun Kwon 
Tested-by: Hoegeun Kwon 
Signed-off-by: Maxime Ripard 


Reviewed-by: Thomas Zimmermann 


---
  drivers/gpu/drm/vc4/vc4_kms.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index 4b558ccb18fe..ad69c70f66a2 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -24,6 +24,8 @@
  #include "vc4_drv.h"
  #include "vc4_regs.h"
  
+#define HVS_NUM_CHANNELS 3

+
  struct vc4_ctm_state {
struct drm_private_state base;
struct drm_color_ctm *ctm;
@@ -660,12 +662,10 @@ static int vc4_load_tracker_obj_init(struct vc4_dev *vc4)
return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, 
NULL);
  }
  
-#define NUM_CHANNELS 3

-
  static int
  vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
  {
-   unsigned long unassigned_channels = GENMASK(NUM_CHANNELS - 1, 0);
+   unsigned long unassigned_channels = GENMASK(HVS_NUM_CHANNELS - 1, 0);
struct drm_crtc_state *old_crtc_state, *new_crtc_state;
struct drm_crtc *crtc;
int i, ret;



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[PATCH v3 07/11] dt-bindings: phy: convert MIP DSI PHY binding to YAML schema

Convert MIPI DSI PHY binding to YAML schema mediatek,dsi-phy.yaml

Cc: Chun-Kuang Hu 
Signed-off-by: Chunfeng Yun 
---
v3: new patch
---
 .../display/mediatek/mediatek,dsi.txt | 18 +---
 .../bindings/phy/mediatek,dsi-phy.yaml| 83 +++
 2 files changed, 84 insertions(+), 17 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index f06f24d405a5..8238a86686be 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -22,23 +22,7 @@ Required properties:
 MIPI TX Configuration Module
 
 
-The MIPI TX configuration module controls the MIPI D-PHY.
-
-Required properties:
-- compatible: "mediatek,-mipi-tx"
-- the supported chips are mt2701, 7623, mt8173 and mt8183.
-- reg: Physical base address and length of the controller's registers
-- clocks: PLL reference clock
-- clock-output-names: name of the output clock line to the DSI encoder
-- #clock-cells: must be <0>;
-- #phy-cells: must be <0>.
-
-Optional properties:
-- drive-strength-microamp: adjust driving current, should be 3000 ~ 6000. And
-  the step is 200.
-- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
-   unspecified default values shall be used.
-- nvmem-cell-names: Should be "calibration-data"
+See phy/mediatek,dsi-phy.yaml
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml 
b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
new file mode 100644
index ..87f8df251ab0
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MIPI Display Serial Interface (DSI) PHY binding
+
+maintainers:
+  - Chun-Kuang Hu 
+  - Chunfeng Yun 
+
+description: The MIPI DSI PHY supports up to 4-lane output.
+
+properties:
+  $nodename:
+pattern: "^dsi-phy@[0-9a-f]+$"
+
+  compatible:
+enum:
+  - mediatek,mt2701-mipi-tx
+  - mediatek,mt7623-mipi-tx
+  - mediatek,mt8173-mipi-tx
+
+  reg:
+maxItems: 1
+
+  clocks:
+items:
+  - description: PLL reference clock
+
+  clock-output-names:
+maxItems: 1
+
+  "#phy-cells":
+const: 0
+
+  "#clock-cells":
+const: 0
+
+  nvmem-cells:
+maxItems: 1
+description: A phandle to the calibration data provided by a nvmem device,
+  if unspecified, default values shall be used.
+
+  nvmem-cell-names:
+items:
+  - const: calibration-data
+
+  drive-strength-microamp:
+description: adjust driving current, the step is 200.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 2000
+maximum: 6000
+default: 4600
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-output-names
+  - "#phy-cells"
+  - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+dsi-phy@10215000 {
+compatible = "mediatek,mt8173-mipi-tx";
+reg = <0x10215000 0x1000>;
+clocks = <&clk26m>;
+clock-output-names = "mipi_tx0_pll";
+drive-strength-microamp = <4000>;
+nvmem-cells= <&mipi_tx_calibration>;
+nvmem-cell-names = "calibration-data";
+#clock-cells = <0>;
+#phy-cells = <0>;
+};
+
+...
-- 
2.18.0

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[PATCH v3 04/11] dt-bindings: phy: convert phy-mtk-tphy.txt to YAML schema

Convert phy-mtk-tphy.txt to YAML schema mediatek,tphy.yaml

Signed-off-by: Chunfeng Yun 
---
v3:
  1. fix dt_binding_check error in example after add mtu3.yaml
  Changes suggested by Rob:
  2. fix wrong indentation
  3. remove '|' due to no formatting to preserve
  4. add a space after '#'
  5. drop unused labels and status in examples
  6. modify file mode

v2:
  1. modify description and compatible
---
 .../bindings/phy/mediatek,tphy.yaml   | 260 ++
 .../devicetree/bindings/phy/phy-mtk-tphy.txt  | 162 ---
 2 files changed, 260 insertions(+), 162 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
 delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt

diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml 
b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
new file mode 100644
index ..602e6ff45785
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
@@ -0,0 +1,260 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek T-PHY Controller Device Tree Bindings
+
+maintainers:
+  - Chunfeng Yun 
+
+description: |
+  The T-PHY controller supports physical layer functionality for a number of
+  controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
+
+  Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
+  T-PHY V2 (mt2712) when works on USB mode:
+  ---
+  Version 1:
+  portoffsetbank
+  shared  0xSPLLC
+  0x0100FMREG
+  u2 port00x0800U2PHY_COM
+  u3 port00x0900U3PHYD
+  0x0a00U3PHYD_BANK2
+  0x0b00U3PHYA
+  0x0c00U3PHYA_DA
+  u2 port10x1000U2PHY_COM
+  u3 port10x1100U3PHYD
+  0x1200U3PHYD_BANK2
+  0x1300U3PHYA
+  0x1400U3PHYA_DA
+  u2 port20x1800U2PHY_COM
+  ...
+
+  Version 2:
+  portoffsetbank
+  u2 port00xMISC
+  0x0100FMREG
+  0x0300U2PHY_COM
+  u3 port00x0700SPLLC
+  0x0800CHIP
+  0x0900U3PHYD
+  0x0a00U3PHYD_BANK2
+  0x0b00U3PHYA
+  0x0c00U3PHYA_DA
+  u2 port10x1000MISC
+  0x1100FMREG
+  0x1300U2PHY_COM
+  u3 port10x1700SPLLC
+  0x1800CHIP
+  0x1900U3PHYD
+  0x1a00U3PHYD_BANK2
+  0x1b00U3PHYA
+  0x1c00U3PHYA_DA
+  u2 port20x2000MISC
+  ...
+
+  SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
+  into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
+  added on V2.
+
+properties:
+  $nodename:
+pattern: "^t-phy@[0-9a-f]+$"
+
+  compatible:
+oneOf:
+  - items:
+  - enum:
+  - mediatek,mt2701-tphy
+  - mediatek,mt7623-tphy
+  - mediatek,mt7622-tphy
+  - mediatek,mt8516-tphy
+  - const: mediatek,generic-tphy-v1
+  - items:
+  - enum:
+  - mediatek,mt2712-tphy
+  - mediatek,mt7629-tphy
+  - mediatek,mt8183-tphy
+  - const: mediatek,generic-tphy-v2
+  - const: mediatek,mt2701-u3phy
+deprecated: true
+  - const: mediatek,mt2712-u3phy
+deprecated: true
+  - const: mediatek,mt8173-u3phy
+
+  reg:
+description:
+  Register shared by multiple ports, exclude port's private register.
+  It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
+  T-PHY V2, such as mt2712.
+maxItems: 1
+
+  "#address-cells":
+enum: [1, 2]
+
+  "#size-cells":
+enum: [1, 2]
+
+  # Used with non-empty value if optional 'reg' is not provided.
+  # The format of the value is an arbitrary number of triplets of
+  # (child-bus-address, parent-bus-address, length).
+  ranges: true
+
+  mediatek,src-ref-clk-mhz:
+description:
+  Frequency of reference clock for slew rate calibrate
+default: 26
+
+  mediatek,src-coef:
+description:
+  Coefficient for slew rate calibrate, depends on SoC process
+$ref: /schemas/types.yaml#/definitions/uint32
+default: 28
+
+# Required child node:
+patternProperties:
+  "^usb-phy@[0-9a-f]+$":
+type: object
+description:
+  A sub-node is required for each port the controller provides.
+  Address range information including the usual 'reg' property
+  is used inside these nodes to describe the controller's topology.
+
+properties:
+  reg:
+maxItems: 1
+
+  clocks:
+minItems: 1
+maxItems: 2
+items:
+  - description: Referenc

Re: [PATCH v9 01/17] memory: tegra30: Support interconnect framework

2020-11-19 Thread Georgi Djakov


On 18.11.20 0:02, Dmitry Osipenko wrote:

17.11.2020 23:24, Georgi Djakov пишет:

Hi Dmitry,

Thank you working on this!

On 15.11.20 23:29, Dmitry Osipenko wrote:

Now Internal and External memory controllers are memory interconnection
providers. This allows us to use interconnect API for tuning of memory
configuration. EMC driver now supports OPPs and DVFS. MC driver now
supports tuning of memory arbitration latency, which needs to be done
for ISO memory clients, like a Display client for example.

Tested-by: Peter Geis 
Signed-off-by: Dmitry Osipenko 
---
   drivers/memory/tegra/Kconfig   |   1 +
   drivers/memory/tegra/tegra30-emc.c | 349 +++--
   drivers/memory/tegra/tegra30.c | 173 +-
   3 files changed, 501 insertions(+), 22 deletions(-)


[..]> diff --git a/drivers/memory/tegra/tegra30.c
b/drivers/memory/tegra/tegra30.c

index d0314f29608d..ea849003014b 100644
--- a/drivers/memory/tegra/tegra30.c
+++ b/drivers/memory/tegra/tegra30.c

[..]

+
+static int tegra30_mc_icc_set(struct icc_node *src, struct icc_node
*dst)
+{
+    struct tegra_mc *mc = icc_provider_to_tegra_mc(src->provider);
+    const struct tegra_mc_client *client = &mc->soc->clients[src->id];
+    u64 peak_bandwidth = icc_units_to_bps(src->peak_bw);
+
+    /*
+ * Skip pre-initialization that is done by icc_node_add(), which
sets
+ * bandwidth to maximum for all clients before drivers are loaded.
+ *
+ * This doesn't make sense for us because we don't have drivers
for all
+ * clients and it's okay to keep configuration left from bootloader
+ * during boot, at least for today.
+ */
+    if (src == dst)
+    return 0;


Nit: The "proper" way to express this should be to implement the
.get_bw() callback to return zero as initial average/peak bandwidth.
I'm wondering if this will work here?

The rest looks good to me!


Hello Georgi,

Returning zeros doesn't allow us to skip the initialization that is done
by provider->set(node, node) in icc_node_add(). It will reconfigure
memory latency in accordance to a zero memory bandwidth, which is wrong
to do.

It actually should be more preferred to preset bandwidth to a maximum
before all drivers are synced, but this should be done only once we will
wire up all drivers to use ICC framework. For now it's safer to keep the
default hardware configuration untouched.


Ok, thanks for clarifying! Is there a way to read this hardware 
configuration and convert it to initial bandwidth? That's the

idea of the get_bw() callback actually. I am just curious and
trying to get a better understanding how this works and if it
would be useful for Tegra.

Thanks,
Georgi
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[PATCH v2 1/3] drm: bridge: cdns-mhdp8546: Modify atomic_get_input_bus_format bridge function

Modify atomic_get_input_bus_format function to return input formats
supported instead of using hardcoded value.

Signed-off-by: Yuti Amonkar 
---
 .../drm/bridge/cadence/cdns-mhdp8546-core.c   | 45 ++-
 1 file changed, 35 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c 
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index 6beccd2a408e..7c80555ab4ab 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -2078,27 +2078,52 @@ cdns_mhdp_bridge_atomic_reset(struct drm_bridge *bridge)
return &cdns_mhdp_state->base;
 }
 
+#define MAX_INPUT_FORMAT 11
+
 static u32 *cdns_mhdp_get_input_bus_fmts(struct drm_bridge *bridge,
- struct drm_bridge_state *bridge_state,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state,
- u32 output_fmt,
- unsigned int *num_input_fmts)
-{
+struct drm_bridge_state *bridge_state,
+struct drm_crtc_state *crtc_state,
+struct drm_connector_state *conn_state,
+u32 output_fmt,
+unsigned int *num_input_fmts)
+{
+   struct drm_connector *conn = conn_state->connector;
+   struct drm_display_info *info = &conn->display_info;
u32 *input_fmts;
-   u32 default_bus_format = MEDIA_BUS_FMT_RGB121212_1X36;
+   unsigned int i = 0;
 
*num_input_fmts = 0;
 
if (output_fmt != MEDIA_BUS_FMT_FIXED)
return NULL;
 
-   input_fmts = kzalloc(sizeof(*input_fmts), GFP_KERNEL);
+   input_fmts = kcalloc(MAX_INPUT_FORMAT,
+sizeof(*input_fmts), GFP_KERNEL);
if (!input_fmts)
return NULL;
 
-   *num_input_fmts = 1;
-   input_fmts[0] = default_bus_format;
+   if (info->color_formats & DRM_COLOR_FORMAT_RGB444) {
+   input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
+   input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
+   input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
+   input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
+   }
+
+   if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) {
+   input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
+   input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
+   input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
+   input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
+   }
+
+   if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) {
+   input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
+   input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
+   input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
+   }
+
+   *num_input_fmts = i;
+
return input_fmts;
 }
 
-- 
2.17.1

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[PATCH v3 03/11] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema

Convert phy-mtk-xsphy.txt to YAML schema mediatek,xsphy.yaml

Signed-off-by: Chunfeng Yun 
---
v3:
  1. remove type for property with standard unit suffix suggested by Rob
  2. remove '|' for descritpion
  3. fix yamllint warning

v2:
  1. modify description and compatible definition suggested by Rob
---
 .../bindings/phy/mediatek,xsphy.yaml  | 199 ++
 .../devicetree/bindings/phy/phy-mtk-xsphy.txt | 109 --
 2 files changed, 199 insertions(+), 109 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
 delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt

diff --git a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml 
b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
new file mode 100644
index ..598fd2b95c29
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
@@ -0,0 +1,199 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek XS-PHY Controller Device Tree Bindings
+
+maintainers:
+  - Chunfeng Yun 
+
+description: |
+  The XS-PHY controller supports physical layer functionality for USB3.1
+  GEN2 controller on MediaTek SoCs.
+
+  Banks layout of xsphy
+  --
+  portoffsetbank
+  u2 port00xMISC
+  0x0100FMREG
+  0x0300U2PHY_COM
+  u2 port10x1000MISC
+  0x1100FMREG
+  0x1300U2PHY_COM
+  u2 port20x2000MISC
+  ...
+  u31 common  0x3000DIG_GLB
+  0x3100PHYA_GLB
+  u31 port0   0x3400DIG_LN_TOP
+  0x3500DIG_LN_TX0
+  0x3600DIG_LN_RX0
+  0x3700DIG_LN_DAIF
+  0x3800PHYA_LN
+  u31 port1   0x3a00DIG_LN_TOP
+  0x3b00DIG_LN_TX0
+  0x3c00DIG_LN_RX0
+  0x3d00DIG_LN_DAIF
+  0x3e00PHYA_LN
+  ...
+  DIG_GLB & PHYA_GLB are shared by U31 ports.
+
+properties:
+  $nodename:
+pattern: "^xs-phy@[0-9a-f]+$"
+
+  compatible:
+items:
+  - enum:
+  - mediatek,mt3611-xsphy
+  - mediatek,mt3612-xsphy
+  - const: mediatek,xsphy
+
+  reg:
+description:
+  Register shared by multiple U3 ports, exclude port's private register,
+  if only U2 ports provided, shouldn't use the property.
+maxItems: 1
+
+  "#address-cells":
+enum: [1, 2]
+
+  "#size-cells":
+enum: [1, 2]
+
+  ranges: true
+
+  mediatek,src-ref-clk-mhz:
+description:
+  Frequency of reference clock for slew rate calibrate
+default: 26
+
+  mediatek,src-coef:
+description:
+  Coefficient for slew rate calibrate, depends on SoC process
+$ref: /schemas/types.yaml#/definitions/uint32
+default: 17
+
+# Required child node:
+patternProperties:
+  "^usb-phy@[0-9a-f]+$":
+type: object
+description:
+  A sub-node is required for each port the controller provides.
+  Address range information including the usual 'reg' property
+  is used inside these nodes to describe the controller's topology.
+
+properties:
+  reg:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
+
+  clock-names:
+items:
+  - const: ref
+
+  "#phy-cells":
+const: 1
+description: |
+  The cells contain the following arguments.
+
+  - description: The PHY type
+  enum:
+- PHY_TYPE_USB2
+- PHY_TYPE_USB3
+
+  # The following optional vendor properties are only for debug or HQA test
+  mediatek,eye-src:
+description:
+  The value of slew rate calibrate (U2 phy)
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 1
+maximum: 7
+
+  mediatek,eye-vrt:
+description:
+  The selection of VRT reference voltage (U2 phy)
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 1
+maximum: 7
+
+  mediatek,eye-term:
+description:
+  The selection of HS_TX TERM reference voltage (U2 phy)
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 1
+maximum: 7
+
+  mediatek,efuse-intr:
+description:
+  The selection of Internal Resistor (U2/U3 phy)
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 1
+maximum: 63
+
+  mediatek,efuse-tx-imp:
+description:
+  The selection of TX Impedance (U3 phy)
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 1
+maximum: 31
+
+  mediatek,efuse-rx-imp:
+description:
+  The selection of RX Impedance (U3 phy)
+$ref

[PATCH v3 10/11] dt-bindings: usb: convert mediatek, mtu3.txt to YAML schema

Convert mediatek,mtu3.txt to YAML schema mediatek,mtu3.yaml

Signed-off-by: Chunfeng Yun 
---
v3:
  1. fix yamllint warning
  2. remove pinctrl* properties
  3. remove unnecessary '|'
  4. drop unused labels in example

v2: new patch
---
 .../devicetree/bindings/usb/mediatek,mtu3.txt | 108 -
 .../bindings/usb/mediatek,mtu3.yaml   | 218 ++
 2 files changed, 218 insertions(+), 108 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
 create mode 100644 Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml

diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt 
b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
deleted file mode 100644
index a82ca438aec1..
--- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
+++ /dev/null
@@ -1,108 +0,0 @@
-The device node for Mediatek USB3.0 DRD controller
-
-Required properties:
- - compatible : should be "mediatek,-mtu3", "mediatek,mtu3",
-   soc-model is the name of SoC, such as mt8173, mt2712 etc,
-   when using "mediatek,mtu3" compatible string, you need SoC specific
-   ones in addition, one of:
-   - "mediatek,mt8173-mtu3"
- - reg : specifies physical base address and size of the registers
- - reg-names: should be "mac" for device IP and "ippc" for IP port control
- - interrupts : interrupt used by the device IP
- - power-domains : a phandle to USB power domain node to control USB's
-   mtcmos
- - vusb33-supply : regulator of USB avdd3.3v
- - clocks : a list of phandle + clock-specifier pairs, one for each
-   entry in clock-names
- - clock-names : must contain "sys_ck" for clock of controller,
-   the following clocks are optional:
-   "ref_ck", "mcu_ck" and "dma_ck";
- - phys : see usb-hcd.yaml in the current directory
- - dr_mode : should be one of "host", "peripheral" or "otg",
-   refer to usb/generic.txt
-
-Optional properties:
- - #address-cells, #size-cells : should be '2' if the device has sub-nodes
-   with 'reg' property
- - ranges : allows valid 1:1 translation between child's address space and
-   parent's address space
- - extcon : external connector for vbus and idpin changes detection, needed
-   when supports dual-role mode.
-   it's considered valid for compatibility reasons, not allowed for
-   new bindings, and use "usb-role-switch" property instead.
- - vbus-supply : reference to the VBUS regulator, needed when supports
-   dual-role mode.
-   it's considered valid for compatibility reasons, not allowed for
-   new bindings, and put into a usb-connector node.
-   see connector/usb-connector.yaml.
- - pinctrl-names : a pinctrl state named "default" is optional, and need be
-   defined if auto drd switch is enabled, that means the property dr_mode
-   is set as "otg", and meanwhile the property "mediatek,enable-manual-drd"
-   is not set.
- - pinctrl-0 : pin control group
-   See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
-
- - maximum-speed : valid arguments are "super-speed", "high-speed" and
-   "full-speed"; refer to usb/generic.txt
- - usb-role-switch : use USB Role Switch to support dual-role switch, but
-   not extcon; see usb/generic.txt.
- - enable-manual-drd : supports manual dual-role switch via debugfs; usually
-   used when receptacle is TYPE-A and also wants to support dual-role
-   mode.
- - wakeup-source: enable USB remote wakeup of host mode.
- - mediatek,syscon-wakeup : phandle to syscon used to access the register
-   of the USB wakeup glue layer between SSUSB and SPM; it depends on
-   "wakeup-source", and has two arguments:
-   - the first one : register base address of the glue layer in syscon;
-   - the second one : hardware version of the glue layer
-   - 1 : used by mt8173 etc
-   - 2 : used by mt2712 etc
- - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0,
-   bit1 for u3port1, ... etc;
-
-additionally the properties from usb-hcd.yaml (in the current directory) are
-supported.
-
-Sub-nodes:
-The xhci should be added as subnode to mtu3 as shown in the following example
-if host mode is enabled. The DT binding details of xhci can be found in:
-Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
-
-The port would be added as subnode if use "usb-role-switch" property.
-   see graph.txt
-
-Example:
-ssusb: usb@11271000 {
-   compatible = "mediatek,mt8173-mtu3";
-   reg = <0 0x11271000 0 0x3000>,
- <0 0x11280700 0 0x0100>;
-   reg-names = "mac", "ippc";
-   interrupts = ;
-   phys = <&phy_port0 PHY_TYPE_USB3>,
-  <&phy_port1 PHY_TYPE_USB2>;
-   power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
-   clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>,
-<&pericfg CLK_PERI_USB0>,
-<&pericfg CLK_PERI_USB1>;
-   clock-names = "sys_ck", "ref_ck"

[PATCH v2 3/5] thermal: devfreq_cooling: add new registration functions with Energy Model

The Energy Model (EM) framework supports devices such as Devfreq. Create
new registration functions which automatically register EM for the thermal
devfreq_cooling devices. This patch prepares the code for coming changes
which are going to replace old power model with the new EM.

Signed-off-by: Lukasz Luba 
---
 drivers/thermal/devfreq_cooling.c | 99 ++-
 include/linux/devfreq_cooling.h   | 22 +++
 2 files changed, 120 insertions(+), 1 deletion(-)

diff --git a/drivers/thermal/devfreq_cooling.c 
b/drivers/thermal/devfreq_cooling.c
index 925523694462..b354271742c5 100644
--- a/drivers/thermal/devfreq_cooling.c
+++ b/drivers/thermal/devfreq_cooling.c
@@ -50,6 +50,8 @@ static DEFINE_IDA(devfreq_ida);
  * @capped_state:  index to cooling state with in dynamic power budget
  * @req_max_freq:  PM QoS request for limiting the maximum frequency
  * of the devfreq device.
+ * @em:Energy Model for the associated Devfreq device
+ * @em_registered: Devfreq cooling registered the EM and should free it.
  */
 struct devfreq_cooling_device {
int id;
@@ -63,6 +65,8 @@ struct devfreq_cooling_device {
u32 res_util;
int capped_state;
struct dev_pm_qos_request req_max_freq;
+   struct em_perf_domain *em;
+   bool em_registered;
 };
 
 static int devfreq_cooling_get_max_state(struct thermal_cooling_device *cdev,
@@ -583,22 +587,115 @@ struct thermal_cooling_device 
*devfreq_cooling_register(struct devfreq *df)
 }
 EXPORT_SYMBOL_GPL(devfreq_cooling_register);
 
+/**
+ * devfreq_cooling_em_register_power() - Register devfreq cooling device with
+ * power information and attempt to register Energy Model (EM)
+ * @df:Pointer to devfreq device.
+ * @dfc_power: Pointer to devfreq_cooling_power.
+ * @em_cb: Callback functions providing the data of the EM
+ *
+ * Register a devfreq cooling device and attempt to register Energy Model. The
+ * available OPPs must be registered for the device.
+ *
+ * If @dfc_power is provided, the cooling device is registered with the
+ * power extensions. If @em_cb is provided it will be called for each OPP to
+ * calculate power value and cost. If @em_cb is not provided then simple Energy
+ * Model is going to be used, which requires "dynamic-power-coefficient" a
+ * devicetree property.
+ */
+struct thermal_cooling_device *
+devfreq_cooling_em_register_power(struct devfreq *df,
+ struct devfreq_cooling_power *dfc_power,
+ struct em_data_callback *em_cb)
+{
+   struct thermal_cooling_device *cdev;
+   struct devfreq_cooling_device *dfc;
+   struct device_node *np = NULL;
+   struct device *dev;
+   int nr_opp, ret;
+
+   if (IS_ERR_OR_NULL(df))
+   return ERR_PTR(-EINVAL);
+
+   dev = df->dev.parent;
+
+   if (em_cb) {
+   nr_opp = dev_pm_opp_get_opp_count(dev);
+   if (nr_opp <= 0) {
+   dev_err(dev, "No valid OPPs found\n");
+   return ERR_PTR(-EINVAL);
+   }
+
+   ret = em_dev_register_perf_domain(dev, nr_opp, em_cb, NULL, 
false);
+   } else {
+   ret = dev_pm_opp_of_register_em(dev, NULL);
+   }
+
+   if (ret)
+   dev_warn(dev, "Unable to register EM for devfreq cooling device 
(%d)\n",
+ret);
+
+   if (dev->of_node)
+   np = of_node_get(dev->of_node);
+
+   cdev = of_devfreq_cooling_register_power(np, df, dfc_power);
+
+   if (np)
+   of_node_put(np);
+
+   if (IS_ERR_OR_NULL(cdev)) {
+   if (!ret)
+   em_dev_unregister_perf_domain(dev);
+   } else {
+   dfc = cdev->devdata;
+   dfc->em_registered = !ret;
+   }
+
+   return cdev;
+}
+EXPORT_SYMBOL_GPL(devfreq_cooling_em_register_power);
+
+/**
+ * devfreq_cooling_em_register() - Register devfreq cooling device together
+ * with Energy Model.
+ * @df:Pointer to devfreq device.
+ * @em_cb: Callback functions providing the data of the Energy Model
+ *
+ * This function attempts to register Energy Model for devfreq device and then
+ * register the devfreq cooling device.
+ */
+struct thermal_cooling_device *
+devfreq_cooling_em_register(struct devfreq *df, struct em_data_callback *em_cb)
+{
+   return devfreq_cooling_em_register_power(df, NULL, em_cb);
+}
+EXPORT_SYMBOL_GPL(devfreq_cooling_em_register);
+
 /**
  * devfreq_cooling_unregister() - Unregister devfreq cooling device.
  * @cdev: Pointer to devfreq cooling device to unregister.
+ *
+ * Unregisters devfreq cooling device and related Energy Model if it was
+ * present.
  */
 void devfreq_cooling_unregister(struct thermal_cooling_device *cdev)
 {
struct devfreq_cooling_device *dfc;
+   struct device *dev;
 
-   if (!cd

[PATCH v2 2/3] drm: bridge: cdns-mhdp8546: Remove setting of bus format using connector info

As we are using bus negotiations for selecting bus format
remove the setting of bus format using the connector info
structure.

Signed-off-by: Yuti Amonkar 
---
 drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c 
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index 7c80555ab4ab..d5e94bd74df1 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -1630,7 +1630,6 @@ static const struct drm_connector_funcs 
cdns_mhdp_conn_funcs = {
 
 static int cdns_mhdp_connector_init(struct cdns_mhdp_device *mhdp)
 {
-   u32 bus_format = MEDIA_BUS_FMT_RGB121212_1X36;
struct drm_connector *conn = &mhdp->connector;
struct drm_bridge *bridge = &mhdp->bridge;
int ret;
@@ -1651,11 +1650,6 @@ static int cdns_mhdp_connector_init(struct 
cdns_mhdp_device *mhdp)
 
drm_connector_helper_add(conn, &cdns_mhdp_conn_helper_funcs);
 
-   ret = drm_display_info_set_bus_formats(&conn->display_info,
-  &bus_format, 1);
-   if (ret)
-   return ret;
-
ret = drm_connector_attach_encoder(conn, bridge->encoder);
if (ret) {
dev_err(mhdp->dev, "Failed to attach connector to encoder\n");
-- 
2.17.1

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[GIT PULL] Allwinner MBUS and DMA-ops rework

Hi Arnd, Olof,

Here's the PR for the MBUS rework we discussed in the last couple of
weeks, for what will become 5.11.

As Arnd suggested, this is based on a PR sent to drm-misc-fixes to merge
the initial fix for a probe error in drm/sun4i due to
dma_direct_set_offset.

Thanks!
Maxime

The following changes since commit 957a1ea3599210e9996777a734ea5284eaef75c7:

  drm/sun4i: backend: Fix probe failure with multiple backends (2020-11-18 
09:01:30 +0100)

are available in the Git repository at:

  ssh://g...@gitolite.kernel.org/pub/scm/linux/kernel/git/mripard/linux.git 
tags/sunxi-rework-mbus

for you to fetch changes up to 16fee29b07358293f135759d9fdbf1267da57ebd:

  dma-mapping: remove the dma_direct_set_offset export (2020-11-18 09:11:38 
+0100)


Allwinner MBUS and DMA-ops rework

The Allwinner SoCs have a number of high-bandwidth devices connected to
a memory bus with a different RAM mapping than the CPU.

This was addressed before through drivers setting the DMA offsets
directly, and subsequently changed to calls to dma_direct_set_offset.
However that wasn't really meant to be exported to modules (and thus
drivers). The duplicated code also led to small inconsistencies across
drivers in how we dealt with DT backward compatibility.

Move all that DMA setup code into a platform bus notifier to share that
code and remove the export on dma_direct_set_offset.


Christoph Hellwig (1):
  dma-mapping: remove the dma_direct_set_offset export

Maxime Ripard (6):
  soc: sunxi: Deal with the MBUS DMA offsets in a central place
  drm/sun4i: backend: Remove the MBUS quirks
  media: sun4i: Remove the MBUS quirks
  media: sun6i: Remove the MBUS quirks
  media: cedrus: Remove the MBUS quirks
  media: sun8i-di: Remove the call to of_dma_configure

 arch/arm/mach-keystone/keystone.c  |   2 +-
 arch/arm/mach-omap1/usb.c  |   2 +-
 arch/sh/drivers/pci/pcie-sh7786.c  |   2 +-
 arch/x86/pci/sta2x11-fixup.c   |   3 +-
 drivers/gpu/drm/sun4i/sun4i_backend.c  |  19 ---
 drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c |  27 -
 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c |  17 ---
 drivers/media/platform/sunxi/sun8i-di/sun8i-di.c   |   4 -
 drivers/soc/sunxi/Kconfig  |   8 ++
 drivers/soc/sunxi/Makefile |   1 +
 drivers/soc/sunxi/sunxi_mbus.c | 132 +
 drivers/staging/media/sunxi/cedrus/cedrus.c|   1 -
 drivers/staging/media/sunxi/cedrus/cedrus.h|   3 -
 drivers/staging/media/sunxi/cedrus/cedrus_hw.c |  18 ---
 include/linux/dma-map-ops.h|   3 +
 include/linux/dma-mapping.h|   7 --
 kernel/dma/direct.c|   1 -
 17 files changed, 149 insertions(+), 101 deletions(-)
 create mode 100644 drivers/soc/sunxi/sunxi_mbus.c


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[PATCH v5 0/7] Enable rk3066a HDMI sound

First fix some legacy things in clk-rk3188.c that was never updated,
because probably nobody used rk3066a I2S before in the mainline kernel.
Update the rk3066a HDMI documents with a #sound-dai-cells property.
Include the code for sound in the HDMI driver.
Add a simple-sound-card compatible node to rk3066a.dtsi,
because I2S0 and HDMI TX are connected internally.
And as last enable rk3066a HDMI sound in the rk3066a-mk808.dts file.

Changed v5:
  removed unused variable
  fill frame structure

Johan Jonker (6):
  clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and
uart clocks
  clk: rockchip: fix i2s gate bits on rk3066 and rk3188
  dt-bindings: display: add #sound-dai-cells property to rockchip rk3066
hdmi
  ARM: dts: rockchip: rk3066a: add #sound-dai-cells to hdmi node
  ARM: dts: rockchip: add hdmi-sound node to rk3066a.dtsi
  ARM: dts: rockchip: enable hdmi_sound and i2s0 for rk3066a-mk808

Zheng Yang (1):
  drm: rockchip: add sound support to rk3066 hdmi driver

 .../display/rockchip/rockchip,rk3066-hdmi.yaml |   4 +
 arch/arm/boot/dts/rk3066a-mk808.dts|   8 +
 arch/arm/boot/dts/rk3066a.dtsi |  17 ++
 drivers/clk/rockchip/clk-rk3188.c  |  35 +--
 drivers/gpu/drm/rockchip/Kconfig   |   2 +
 drivers/gpu/drm/rockchip/rk3066_hdmi.c | 275 -
 6 files changed, 323 insertions(+), 18 deletions(-)

--
2.11.0

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RE: Linux 5.10-rc4

2020-11-19 Thread David Laight

From: Linus Torvalds
> Sent: 18 November 2020 18:11
> 
> On Wed, Nov 18, 2020 at 4:12 AM David Laight  wrote:
> >
> > I've got the 'splat' below during boot.
> > This is an 8-core C2758 Atom cpu using the on-board/cpu graphics.
> > User space is Ubuntu 20.04.
> >
> > Additionally the X display has all the colours and alignment slightly
> > messed up.
> > 5.9.0 was ok.
> > I'm just guessing the two issues are related.
> 
> Sounds likely.  But it would be lovely if you could bisect when
> exactly the problem(s) started to both verify that, and just to
> pinpoint the exact change..

I'm working on it - have been all afternoon.
(I'm on holiday and it is raining...)

5.10-rc1 fails, so it is something in the merge window.
I suspect I'll just hit the pull of the drm changes.
The bisect suddenly build a 5.9-rc5+ kernel!
So I'm retesting a good/bad pair with likely dates and will restart it.

Annoyingly the test system defaults to booting the highest version
kernel - not the one I've just build; I may have given it a wrong answer.
The builds also all take 20 minutes; so the bisect is slow.

David

-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, 
UK
Registration No: 1397386 (Wales)
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[PATCH v2 1/9] dt-binding: soc: xilinx: ai-engine: Add AI engine binding

Xilinx AI engine array can be partitioned statically for different
applications. In the device tree, there will be device node for the AI
engine device, and device nodes for the statically configured AI engine
partitions. Each of the statically configured partition has a partition
ID in the system.

Signed-off-by: Wendy Liang 
---
 .../bindings/soc/xilinx/xlnx,ai-engine.yaml| 126 +
 1 file changed, 126 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml

diff --git a/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml 
b/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
new file mode 100644
index 000..1de5623
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/xilinx/xlnx,ai-engine.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx AI Engine
+
+maintainers:
+  - Wendy Liang 
+
+description: |+
+  The Xilinx AI Engine is a tile processor with many cores (up to 400) that
+  can run in parallel. The data routing between cores is configured through
+  internal switches, and shim tiles interface with external interconnect, such
+  as memory or PL.
+
+properties:
+  compatible:
+const: xlnx,ai-engine-v1.0
+
+  reg:
+description: |
+  Physical base address and length of the device registers.
+  The AI engine address space assigned to Linux is defined by Xilinx
+  platform design tool.
+
+  '#address-cells':
+enum: [2]
+description: |
+  size of cell to describe AI engine range of tiles address.
+  It is the location of the starting tile of the range.
+  As the AI engine tiles are 2D array, the location of a tile
+  is presented as (column, row), the address cell is 2.
+
+  '#size-cells':
+enum: [2]
+description: |
+  size of cell to describe AI engine range of tiles size.
+  As the AI engine tiles are 2D array, the size cell is 2.
+
+  power-domains:
+maxItems: 1
+description: phandle to the associated power domain
+
+  interrupts:
+maxItems: 3
+
+  interrupt-names:
+description: |
+  Should be "interrupt1", "interrupt2" or "interrupt3".
+
+required:
+  - compatible
+  - reg
+  - '#address-cells'
+  - '#size-cells'
+  - power-domains
+  - interrupt-parent
+  - interrupts
+  - interrupt-names
+
+patternProperties:
+  "^aie_partition@[0-9]+$":
+type: object
+description: |
+  AI engine partition which is a group of column based tiles of the AI
+  engine device. Each AI engine partition is isolated from the other
+  AI engine partitions. An AI engine partition is defined by Xilinx
+  platform design tools. Each partition has a SHIM row and core tiles rows.
+  A SHIM row contains SHIM tiles which are the interface to external
+  components. AXI master can access AI engine registers, push data to and
+  fetch data from AI engine through the SHIM tiles. Core tiles are the
+  compute tiles.
+
+properties:
+  reg:
+description: |
+  It describes the group of tiles of the AI engine partition. It needs
+  to include the SHIM row. The format is defined by the parent AI 
engine
+  device node's '#address-cells' and '#size-cells' properties. e.g. a 
v1
+  AI engine device has 2D tiles array, the first row is SHIM row. A
+  partition which has 50 columns and 8 rows of core tiles and 1 row of
+  SHIM tiles will be presented as <0 0 50 9>.
+
+  label:
+maxItems: 1
+
+  xlnx,partition-id:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: |
+  AI engine partition ID, which is defined by Xilinx platform design
+  tool to identify the AI engine partition in the system.
+
+required:
+  - reg
+  - xlnx,partition-id
+additionalProperties: false
+
+additionalProperties: false
+
+examples:
+  - |
+bus {
+  #address-cells = <2>;
+  #size-cells = <2>;
+
+  ai_engine: ai-engine@200 {
+compatible = "xlnx,ai-engine-v1.0";
+reg = <0x200 0x0 0x1 0x0>;
+#address-cells = <2>;
+#size-cells = <2>;
+power-domains = <&versal_firmware 0x18224072>;
+interrupt-parent = <&gic>;
+interrupts = <0x0 0x94 0x4>,
+ <0x0 0x95 0x4>,
+ <0x0 0x96 0x4>;
+interrupt-names = "interrupt1", "interrupt2", "interrupt3";
+
+aie_partition0: aie_partition@0 {
+/* 50 columns and 8 core tile rows + 1 SHIM row */
+reg = <0 0 50 9>;
+xlnx,partition-id = <1>;
+};
+  };
+};
-- 
2.7.4

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[PATCH v2 3/3] drm: bridge: cdns-mhdp8546: Retrieve the pixel format and bpc based on bus format

Get the pixel format and bpc based on the output bus format
negotiated instead of hardcoding the values.

Signed-off-by: Yuti Amonkar 
---
 .../drm/bridge/cadence/cdns-mhdp8546-core.c   | 82 +++
 1 file changed, 64 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c 
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index d5e94bd74df1..e1f4bbd09816 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -1512,24 +1512,8 @@ static int cdns_mhdp_get_modes(struct drm_connector 
*connector)
 
drm_connector_update_edid_property(connector, edid);
num_modes = drm_add_edid_modes(connector, edid);
-   kfree(edid);
 
-   /*
-* HACK: Warn about unsupported display formats until we deal
-*   with them correctly.
-*/
-   if (connector->display_info.color_formats &&
-   !(connector->display_info.color_formats &
- mhdp->display_fmt.color_format))
-   dev_warn(mhdp->dev,
-"%s: No supported color_format found (0x%08x)\n",
-   __func__, connector->display_info.color_formats);
-
-   if (connector->display_info.bpc &&
-   connector->display_info.bpc < mhdp->display_fmt.bpc)
-   dev_warn(mhdp->dev, "%s: Display bpc only %d < %d\n",
-__func__, connector->display_info.bpc,
-mhdp->display_fmt.bpc);
+   kfree(edid);
 
return num_modes;
 }
@@ -1689,6 +1673,66 @@ static int cdns_mhdp_attach(struct drm_bridge *bridge,
return 0;
 }
 
+static void cdns_mhdp_get_display_fmt(struct cdns_mhdp_device *mhdp,
+ struct drm_bridge_state *state)
+{
+   u32 bus_fmt, bpc, pxlfmt;
+
+   bus_fmt = state->output_bus_cfg.format;
+   switch (bus_fmt) {
+   case MEDIA_BUS_FMT_RGB161616_1X48:
+   pxlfmt = DRM_COLOR_FORMAT_RGB444;
+   bpc = 16;
+   break;
+   case MEDIA_BUS_FMT_YUV16_1X48:
+   pxlfmt = DRM_COLOR_FORMAT_YCRCB444;
+   bpc = 16;
+   break;
+   case MEDIA_BUS_FMT_RGB121212_1X36:
+   pxlfmt = DRM_COLOR_FORMAT_RGB444;
+   bpc = 12;
+   break;
+   case MEDIA_BUS_FMT_UYVY12_1X24:
+   pxlfmt = DRM_COLOR_FORMAT_YCRCB422;
+   bpc = 12;
+   break;
+   case MEDIA_BUS_FMT_YUV12_1X36:
+   pxlfmt = DRM_COLOR_FORMAT_YCRCB444;
+   bpc = 12;
+   break;
+   case MEDIA_BUS_FMT_RGB101010_1X30:
+   pxlfmt = DRM_COLOR_FORMAT_RGB444;
+   bpc = 10;
+   break;
+   case MEDIA_BUS_FMT_UYVY10_1X20:
+   pxlfmt = DRM_COLOR_FORMAT_YCRCB422;
+   bpc = 10;
+   break;
+   case MEDIA_BUS_FMT_YUV10_1X30:
+   pxlfmt = DRM_COLOR_FORMAT_YCRCB444;
+   bpc = 10;
+   break;
+   case MEDIA_BUS_FMT_RGB888_1X24:
+   pxlfmt = DRM_COLOR_FORMAT_RGB444;
+   bpc = 8;
+   break;
+   case MEDIA_BUS_FMT_UYVY8_1X16:
+   pxlfmt = DRM_COLOR_FORMAT_YCRCB422;
+   bpc = 8;
+   break;
+   case MEDIA_BUS_FMT_YUV8_1X24:
+   pxlfmt = DRM_COLOR_FORMAT_YCRCB444;
+   bpc = 8;
+   break;
+   default:
+   pxlfmt = DRM_COLOR_FORMAT_RGB444;
+   bpc = 8;
+   }
+
+   mhdp->display_fmt.color_format = pxlfmt;
+   mhdp->display_fmt.bpc = bpc;
+}
+
 static void cdns_mhdp_configure_video(struct cdns_mhdp_device *mhdp,
  const struct drm_display_mode *mode)
 {
@@ -2129,6 +2173,8 @@ static int cdns_mhdp_atomic_check(struct drm_bridge 
*bridge,
struct cdns_mhdp_device *mhdp = bridge_to_mhdp(bridge);
const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 
+   cdns_mhdp_get_display_fmt(mhdp, bridge_state);
+
mutex_lock(&mhdp->link_mutex);
 
if (!cdns_mhdp_bandwidth_ok(mhdp, mode, mhdp->link.num_lanes,
@@ -2456,7 +2502,7 @@ static int cdns_mhdp_probe(struct platform_device *pdev)
mhdp->link.rate = mhdp->host.link_rate;
mhdp->link.num_lanes = mhdp->host.lanes_cnt;
 
-   /* The only currently supported format */
+   /* Initialize color format bpc and y_only to default values*/
mhdp->display_fmt.y_only = false;
mhdp->display_fmt.color_format = DRM_COLOR_FORMAT_RGB444;
mhdp->display_fmt.bpc = 8;
-- 
2.17.1

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Re: [PATCH v2 07/22] drm/msm: Do rpm get sooner in the submit path

2020-11-19 Thread Viresh Kumar

On 18-11-20, 08:53, Rob Clark wrote:
> On Tue, Nov 17, 2020 at 9:28 PM Viresh Kumar  wrote:
> >
> > On 17-11-20, 09:02, Rob Clark wrote:
> > > With that on top of the previous patch,
> >
> > Don't you still have this ? Which fixed the lockdep in the remove path.
> >
> > https://lore.kernel.org/lkml/20201022080644.2ck4okrxygmkuatn@vireshk-i7/
> >
> > To make it clear you need these patches to fix the OPP stuff:
> >
> > //From 5.10-rc3 (the one from the above link).
> > commit e0df59de670b ("opp: Reduce the size of critical section in 
> > _opp_table_kref_release()")

This fixes debugfs stuff while the OPP table is removed.

> > //Below two from linux-next
> > commit ef43f01ac069 ("opp: Always add entries in dev_list with 
> > opp_table->lock held")
> > commit 27c09484dd3d ("opp: Allocate the OPP table outside of 
> > opp_table_lock")

This fixes debugfs stuff while the OPP table is added.

> > This matches the diff I gave you earlier.
> >
> 
> no, I did not have all three, only "opp: Allocate the OPP table
> outside of opp_table_lock" plus the fixup.  But with all three:

And looking at the lockdep you gave now, it looks like we have a
problem with OPP table's internal lock (opp_table->lock) as well apart
from the global opp_table_lock.

I wish there was a way for me to reproduce the lockdep :(

I know this is exhausting for both of us and I really want to be over
with it as soon as possible, this really should be the last patch
here, please try this along with other two. This fixes the debugfs
thing while the OPPs in the OPP table are removed (they are already
added without a lock around debugfs stuff).

AFAIU, there is no further debugfs stuff that happens from within the
locks and so this really should be the last patch unless I missed
something.

-- 
viresh

-8<-
From: Viresh Kumar 
Date: Thu, 19 Nov 2020 11:24:32 +0530
Subject: [PATCH] opp: Reduce the size of critical section in
 _opp_kref_release()

There is a lot of stuff here which can be done outside of the
opp_table->lock, do that. This helps avoiding a circular dependency
lockdeps around debugfs.

Reported-by: Rob Clark 
Signed-off-by: Viresh Kumar 
---
 drivers/opp/core.c | 94 +++---
 1 file changed, 47 insertions(+), 47 deletions(-)

diff --git a/drivers/opp/core.c b/drivers/opp/core.c
index 9d145bb99a59..4268eb359915 100644
--- a/drivers/opp/core.c
+++ b/drivers/opp/core.c
@@ -1251,9 +1251,14 @@ void _opp_free(struct dev_pm_opp *opp)
kfree(opp);
 }
 
-static void _opp_kref_release(struct dev_pm_opp *opp,
- struct opp_table *opp_table)
+static void _opp_kref_release(struct kref *kref)
 {
+   struct dev_pm_opp *opp = container_of(kref, struct dev_pm_opp, kref);
+   struct opp_table *opp_table = opp->opp_table;
+
+   list_del(&opp->node);
+   mutex_unlock(&opp_table->lock);
+
/*
 * Notify the changes in the availability of the operable
 * frequency/voltage list.
@@ -1261,27 +1266,9 @@ static void _opp_kref_release(struct dev_pm_opp *opp,
blocking_notifier_call_chain(&opp_table->head, OPP_EVENT_REMOVE, opp);
_of_opp_free_required_opps(opp_table, opp);
opp_debug_remove_one(opp);
-   list_del(&opp->node);
kfree(opp);
 }
 
-static void _opp_kref_release_unlocked(struct kref *kref)
-{
-   struct dev_pm_opp *opp = container_of(kref, struct dev_pm_opp, kref);
-   struct opp_table *opp_table = opp->opp_table;
-
-   _opp_kref_release(opp, opp_table);
-}
-
-static void _opp_kref_release_locked(struct kref *kref)
-{
-   struct dev_pm_opp *opp = container_of(kref, struct dev_pm_opp, kref);
-   struct opp_table *opp_table = opp->opp_table;
-
-   _opp_kref_release(opp, opp_table);
-   mutex_unlock(&opp_table->lock);
-}
-
 void dev_pm_opp_get(struct dev_pm_opp *opp)
 {
kref_get(&opp->kref);
@@ -1289,16 +1276,10 @@ void dev_pm_opp_get(struct dev_pm_opp *opp)
 
 void dev_pm_opp_put(struct dev_pm_opp *opp)
 {
-   kref_put_mutex(&opp->kref, _opp_kref_release_locked,
-  &opp->opp_table->lock);
+   kref_put_mutex(&opp->kref, _opp_kref_release, &opp->opp_table->lock);
 }
 EXPORT_SYMBOL_GPL(dev_pm_opp_put);
 
-static void dev_pm_opp_put_unlocked(struct dev_pm_opp *opp)
-{
-   kref_put(&opp->kref, _opp_kref_release_unlocked);
-}
-
 /**
  * dev_pm_opp_remove()  - Remove an OPP from OPP table
  * @dev:   device for which we do this operation
@@ -1342,30 +1323,49 @@ void dev_pm_opp_remove(struct device *dev, unsigned 
long freq)
 }
 EXPORT_SYMBOL_GPL(dev_pm_opp_remove);
 
+static struct dev_pm_opp *_opp_get_next(struct opp_table *opp_table,
+   bool dynamic)
+{
+   struct dev_pm_opp *opp = NULL, *temp;
+
+   mutex_lock(&opp_table->lock);
+   list_for_each_entry(temp, &opp_table->opp_list, node) {
+   if (dynamic == temp->dynamic) {
+

[PATCH v5 6/7] ARM: dts: rockchip: add hdmi-sound node to rk3066a.dtsi

Add hdmi-sound node to rk3066a.dtsi, so that it
can be reused by boards with HDMI support.

Signed-off-by: Johan Jonker 
---
 arch/arm/boot/dts/rk3066a.dtsi | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 67fcb0dc9..f91ce3054 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -49,6 +49,22 @@
ports = <&vop0_out>, <&vop1_out>;
};
 
+   hdmi_sound: hdmi-sound {
+   compatible = "simple-audio-card";
+   simple-audio-card,name = "HDMI";
+   simple-audio-card,format = "i2s";
+   simple-audio-card,mclk-fs = <256>;
+   status = "disabled";
+
+   simple-audio-card,codec {
+   sound-dai = <&hdmi>;
+   };
+
+   simple-audio-card,cpu {
+   sound-dai = <&i2s0>;
+   };
+   };
+
sram: sram@1008 {
compatible = "mmio-sram";
reg = <0x1008 0x1>;
-- 
2.11.0

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[PATCH v3 08/11] dt-bindings: usb: convert mediatek, musb.txt to YAML schema

Convert mediatek,musb.txt to YAML schema mediatek,musb.yaml

Cc: Min Guo 
Signed-off-by: Chunfeng Yun 
Reviewed-by: Rob Herring 
---
v3: add Reviewed-by Rob
v2: new patch
---
 .../devicetree/bindings/usb/mediatek,musb.txt |  57 -
 .../bindings/usb/mediatek,musb.yaml   | 113 ++
 2 files changed, 113 insertions(+), 57 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/usb/mediatek,musb.txt
 create mode 100644 Documentation/devicetree/bindings/usb/mediatek,musb.yaml

diff --git a/Documentation/devicetree/bindings/usb/mediatek,musb.txt 
b/Documentation/devicetree/bindings/usb/mediatek,musb.txt
deleted file mode 100644
index 5eedb0296562..
--- a/Documentation/devicetree/bindings/usb/mediatek,musb.txt
+++ /dev/null
@@ -1,57 +0,0 @@
-MediaTek musb DRD/OTG controller

-
-Required properties:
- - compatible  : should be one of:
- "mediatek,mt2701-musb"
- ...
- followed by "mediatek,mtk-musb"
- - reg : specifies physical base address and size of
- the registers
- - interrupts  : interrupt used by musb controller
- - interrupt-names : must be "mc"
- - phys: PHY specifier for the OTG phy
- - dr_mode : should be one of "host", "peripheral" or "otg",
- refer to usb/generic.txt
- - clocks  : a list of phandle + clock-specifier pairs, one for
- each entry in clock-names
- - clock-names : must contain "main", "mcu", "univpll"
- for clocks of controller
-
-Optional properties:
- - power-domains   : a phandle to USB power domain node to control USB's
- MTCMOS
-
-Required child nodes:
- usb connector node as defined in bindings/connector/usb-connector.yaml
-Optional properties:
- - id-gpios: input GPIO for USB ID pin.
- - vbus-gpios  : input GPIO for USB VBUS pin.
- - vbus-supply : reference to the VBUS regulator, needed when supports
- dual-role mode
- - usb-role-switch : use USB Role Switch to support dual-role switch, see
- usb/generic.txt.
-
-Example:
-
-usb2: usb@1120 {
-   compatible = "mediatek,mt2701-musb",
-"mediatek,mtk-musb";
-   reg = <0 0x1120 0 0x1000>;
-   interrupts = ;
-   interrupt-names = "mc";
-   phys = <&u2port2 PHY_TYPE_USB2>;
-   dr_mode = "otg";
-   clocks = <&pericfg CLK_PERI_USB0>,
-<&pericfg CLK_PERI_USB0_MCU>,
-<&pericfg CLK_PERI_USB_SLV>;
-   clock-names = "main","mcu","univpll";
-   power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
-   usb-role-switch;
-   connector{
-   compatible = "gpio-usb-b-connector", "usb-b-connector";
-   type = "micro";
-   id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>;
-   vbus-supply = <&usb_vbus>;
-   };
-};
diff --git a/Documentation/devicetree/bindings/usb/mediatek,musb.yaml 
b/Documentation/devicetree/bindings/usb/mediatek,musb.yaml
new file mode 100644
index ..3e60df4b91bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/mediatek,musb.yaml
@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/mediatek,musb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MUSB DRD/OTG Controller Device Tree Bindings
+
+maintainers:
+  - Min Guo 
+
+properties:
+  $nodename:
+pattern: '^usb@[0-9a-f]+$'
+
+  compatible:
+items:
+  - enum:
+  - mediatek,mt2701-musb
+  - const: mediatek,mtk-musb
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  interrupt-names:
+items:
+  - const: mc
+
+  clocks:
+items:
+  - description: The main/core clock
+  - description: The system bus clock
+  - description: The 48Mhz clock
+
+  clock-names:
+items:
+  - const: main
+  - const: mcu
+  - const: univpll
+
+  phys:
+maxItems: 1
+
+  usb-role-switch:
+$ref: /schemas/types.yaml#/definitions/flag
+description: Support role switch. See usb/generic.txt
+type: boolean
+
+  dr_mode:
+enum:
+  - host
+  - otg
+  - peripheral
+
+  power-domains:
+description: A phandle to USB power domain node to control USB's MTCMOS
+maxItems: 1
+
+  connector:
+$ref: /connector/usb-connector.yaml#
+description: Connector for dual role switch
+type: object
+
+dependencies:
+  usb-role-switch: [ 'connector' ]
+  connector: [ 'usb-role-switch' ]
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - phys
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+usb@1120 {
+

[PATCH v3 02/11] dt-bindings: net: btusb: change reference file name

Due to usb-device.txt is converted into usb-device.yaml,
so modify reference file names at the same time.

Signed-off-by: Chunfeng Yun 
---
v2~v3: no changes
---
 Documentation/devicetree/bindings/net/btusb.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/btusb.txt 
b/Documentation/devicetree/bindings/net/btusb.txt
index b1ad6ee68e90..a9c3f4277f69 100644
--- a/Documentation/devicetree/bindings/net/btusb.txt
+++ b/Documentation/devicetree/bindings/net/btusb.txt
@@ -4,7 +4,7 @@ Generic Bluetooth controller over USB (btusb driver)
 Required properties:
 
   - compatible : should comply with the format "usbVID,PID" specified in
-Documentation/devicetree/bindings/usb/usb-device.txt
+Documentation/devicetree/bindings/usb/usb-device.yaml
 At the time of writing, the only OF supported devices
 (more may be added later) are:
 
-- 
2.18.0

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[PATCH v5 1/7] clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks

Add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks,
so that the parent COMPOSITE_FRACMUX and COMPOSITE_NOMUX
also update.

Signed-off-by: Johan Jonker 
---
 drivers/clk/rockchip/clk-rk3188.c | 28 ++--
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3188.c 
b/drivers/clk/rockchip/clk-rk3188.c
index 730020fcc..db8c58813 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -255,19 +255,19 @@ static struct rockchip_clk_branch common_spdif_fracmux 
__initdata =
RK2928_CLKSEL_CON(5), 8, 2, MFLAGS);
 
 static struct rockchip_clk_branch common_uart0_fracmux __initdata =
-   MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0,
+   MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
 
 static struct rockchip_clk_branch common_uart1_fracmux __initdata =
-   MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0,
+   MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
 
 static struct rockchip_clk_branch common_uart2_fracmux __initdata =
-   MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0,
+   MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
 
 static struct rockchip_clk_branch common_uart3_fracmux __initdata =
-   MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0,
+   MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
 
 static struct rockchip_clk_branch common_clk_branches[] __initdata = {
@@ -408,28 +408,28 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0,
RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 8, GFLAGS),
-   COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", 0,
+   COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(17), 0,
RK2928_CLKGATE_CON(1), 9, GFLAGS,
&common_uart0_fracmux),
COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0,
RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 10, GFLAGS),
-   COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", 0,
+   COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(18), 0,
RK2928_CLKGATE_CON(1), 11, GFLAGS,
&common_uart1_fracmux),
COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0,
RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 12, GFLAGS),
-   COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", 0,
+   COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(19), 0,
RK2928_CLKGATE_CON(1), 13, GFLAGS,
&common_uart2_fracmux),
COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0,
RK2928_CLKSEL_CON(16), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 14, GFLAGS),
-   COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", 0,
+   COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(20), 0,
RK2928_CLKGATE_CON(1), 15, GFLAGS,
&common_uart3_fracmux),
@@ -543,15 +543,15 @@ static struct clk_div_table div_aclk_cpu_t[] = {
 };
 
 static struct rockchip_clk_branch rk3066a_i2s0_fracmux __initdata =
-   MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
+   MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(2), 8, 2, MFLAGS);
 
 static struct rockchip_clk_branch rk3066a_i2s1_fracmux __initdata =
-   MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0,
+   MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
 
 static struct rockchip_clk_branch rk3066a_i2s2_fracmux __initdata =
-   MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0,
+   MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(4), 8, 2, MFLAGS);
 
 static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
@@ -615,21 +615,21 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] 
__initdata = {
COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
RK2928_CLKSEL_CON(2), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 7, GFLAGS),
-   COMPOSITE_FRACMUX(0, "i2s0_fra

[PATCH] via/via_irq: use func to replace string function name

This change also fix checkpatch.pl warning:
WARNING: Prefer using '"%s...", __func__' to using
'via_driver_irq_postinstall', this function's name, in a string
+   DRM_DEBUG("via_driver_irq_postinstall\n");

Signed-off-by: Bernard Zhao 
---
 drivers/gpu/drm/via/via_irq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/via/via_irq.c b/drivers/gpu/drm/via/via_irq.c
index 24cc445169e2..56ce5d4ee24a 100644
--- a/drivers/gpu/drm/via/via_irq.c
+++ b/drivers/gpu/drm/via/via_irq.c
@@ -308,7 +308,7 @@ int via_driver_irq_postinstall(struct drm_device *dev)
drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
u32 status;
 
-   DRM_DEBUG("via_driver_irq_postinstall\n");
+   DRM_DEBUG("fun: %s\n", __func__);
if (!dev_priv)
return -EINVAL;
 
-- 
2.29.0

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[PATCH 9/9] misc: xilinx-ai-engine: Add support for servicing error interrupts

From: Nishad Saraf 

AI engine errors events can be routed to generate interrupt. The
errors events routing will be done during AI engine configuration.
At runtime, Linux kernel AI engine driver monitors the interrupt and
backtracks errors events.
As error events from 400 AIE tiles and 50 shim tiles are channeled on
a single interrupt line, backtracking the source the interrupt to an
AIE module is required. To keep the top-half interrupt short,
backtracking is deferred to bottom half by scheduling a task in shared
workqueue.

Signed-off-by: Nishad Saraf 
Signed-off-by: Wendy Liang 
---
 drivers/misc/xilinx-ai-engine/Makefile |   1 +
 drivers/misc/xilinx-ai-engine/ai-engine-aie.c  | 121 
 drivers/misc/xilinx-ai-engine/ai-engine-dev.c  |  14 +
 drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 144 +
 .../misc/xilinx-ai-engine/ai-engine-interrupt.c| 661 +
 drivers/misc/xilinx-ai-engine/ai-engine-part.c |  44 ++
 drivers/misc/xilinx-ai-engine/ai-engine-res.c  |  54 ++
 7 files changed, 1039 insertions(+)
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-interrupt.c

diff --git a/drivers/misc/xilinx-ai-engine/Makefile 
b/drivers/misc/xilinx-ai-engine/Makefile
index 2e67b25..9607ecb 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -9,6 +9,7 @@ xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
   ai-engine-clock.o \
   ai-engine-dev.o \
   ai-engine-dma.o \
+  ai-engine-interrupt.o \
   ai-engine-mem.o \
   ai-engine-part.o \
   ai-engine-res.o \
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c 
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index ff721b3..af0f997 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -33,7 +33,10 @@
 #define AIE_SHIMPL_CLKCNTR_REGOFF  0x00036040U
 #define AIE_SHIMPL_COLRESET_REGOFF 0x00036048U
 #define AIE_SHIMPL_RESET_REGOFF0x0003604cU
+#define AIE_SHIMPL_GROUP_ERROR_REGOFF  0x0003450cU
 #define AIE_TILE_CORE_CLKCNTR_REGOFF   0x00036040U
+#define AIE_TILE_CORE_GROUP_ERROR_REGOFF   0x00034510U
+#define AIE_TILE_MEM_GROUP_ERROR_REGOFF0x00014514U
 
 /*
  * Register masks
@@ -93,11 +96,27 @@ static const struct aie_tile_regs aie_kernel_regs[] = {
 .soff = AIE_SHIMPL_CLKCNTR_REGOFF,
 .eoff = AIE_SHIMPL_CLKCNTR_REGOFF,
},
+   /* SHIM group error enable */
+   {.attribute = (AIE_TILE_TYPE_SHIMPL | AIE_TILE_TYPE_SHIMNOC) <<
+ AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_SHIMPL_GROUP_ERROR_REGOFF,
+.eoff = AIE_SHIMPL_GROUP_ERROR_REGOFF,
+   },
/* Tile clock control */
{.attribute = AIE_TILE_TYPE_TILE << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
 .soff = AIE_TILE_CORE_CLKCNTR_REGOFF,
 .eoff = AIE_TILE_CORE_CLKCNTR_REGOFF,
},
+   /* Tile group error for core module */
+   {.attribute = AIE_TILE_TYPE_TILE << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_TILE_CORE_GROUP_ERROR_REGOFF,
+.eoff = AIE_TILE_CORE_GROUP_ERROR_REGOFF,
+   },
+   /* Tile group error for memory module */
+   {.attribute = AIE_TILE_TYPE_TILE << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_TILE_MEM_GROUP_ERROR_REGOFF,
+.eoff = AIE_TILE_MEM_GROUP_ERROR_REGOFF,
+   },
 };
 
 static const struct aie_single_reg_field aie_col_rst = {
@@ -128,6 +147,103 @@ static const struct aie_dma_attr aie_shimdma = {
.bd_len = 0x14U,
 };
 
+static const struct aie_event_attr aie_pl_event = {
+   .bc_event = {
+   .mask = GENMASK(6, 0),
+   .regoff = 0x0U,
+   },
+   .group_error = {
+   .mask = GENMASK(10, 0),
+   .regoff = 0xcU,
+   },
+   .bc_regoff = 0x34010U,
+   .status_regoff = 0x34200U,
+   .group_regoff = 0x34500U,
+   .base_error_event = 62U,
+   .num_broadcasts = 16U,
+   .base_bc_event = 107U,
+   .num_events = 128U,
+};
+
+static const struct aie_event_attr aie_mem_event = {
+   .bc_event = {
+   .mask = GENMASK(6, 0),
+   .regoff = 0x0U,
+   },
+   .group_error = {
+   .mask = GENMASK(13, 0),
+   .regoff = 0x14U,
+   },
+   .bc_regoff = 0x14010U,
+   .status_regoff = 0x14200U,
+   .group_regoff = 0x14500U,
+   .base_error_event = 87U,
+   .num_broadcasts = 16U,
+   .base_bc_event = 107U,
+   .num_events = 128U,
+};
+
+static const struct aie_event_attr aie_core_event = {
+   .bc_event = {
+   .mask = GENMASK(6, 0),
+   .regoff = 0x0U,
+   },
+   .group_erro

[PATCH v5 5/7] ARM: dts: rockchip: rk3066a: add #sound-dai-cells to hdmi node

'#sound-dai-cells' is required to properly interpret
the list of DAI specified in the 'sound-dai' property,
so add them to the 'hdmi' node for 'rk3066a.dtsi'.

Signed-off-by: Johan Jonker 
---
 arch/arm/boot/dts/rk3066a.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 252750c97..67fcb0dc9 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -124,6 +124,7 @@
pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
power-domains = <&power RK3066_PD_VIO>;
rockchip,grf = <&grf>;
+   #sound-dai-cells = <0>;
status = "disabled";
 
ports {
-- 
2.11.0

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[GIT PULL] Fix for drm/sun4i shared with arm-soc

Hi,

Here's a fix shared with the DMA work for sun4i that will be merged
through arm-soc.

This conflicts with the subsequent work done for sun4i and
dma_direct_set_offset, so it would be better to merge that fix through a
PR in drm-misc-fixes.

Maxime

The following changes since commit 3650b228f83adda7e5ee532e2b90429c03f7b9ec:

  Linux 5.10-rc1 (2020-10-25 15:14:11 -0700)

are available in the Git repository at:

  ssh://g...@gitolite.kernel.org/pub/scm/linux/kernel/git/mripard/linux.git 
tags/drm/sun4i-dma-fix-pull-request

for you to fetch changes up to 957a1ea3599210e9996777a734ea5284eaef75c7:

  drm/sun4i: backend: Fix probe failure with multiple backends (2020-11-18 
09:01:30 +0100)


Fix for drm/sun4i shared with arm-soc

This patch is a preliminary fix that will conflict with subsequent work merged
through arm-soc.


Maxime Ripard (1):
  drm/sun4i: backend: Fix probe failure with multiple backends

 drivers/gpu/drm/sun4i/sun4i_backend.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)


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[PATCH v2 0/9] Xilinx AI engine kernel driver

AI engine is the acceleration engine provided by Xilinx. These engines
provide high compute density for vector-based algorithms, and flexible
custom compute and data movement. It has core tiles for compute and
shim tiles to interface the FPGA fabric.

You can check the AI engine architecture document for more hardware details:
https://www.xilinx.com/support/documentation/architecture-manuals/am009-versal-ai-engine.pdf

This patch series adds a Linux kernel driver to manage the Xilinx AI
engine array device and AI engine partitions (groups of AI engine tiles
dedicated to an application).

v2:
* Fix dtschema check errors
* Fix test bot warning on interrupt implementation. Removed set but
  unused  varaible.
* Fix compilation unused function warning of firmware change in case
  ZynqMP firmware is not configured
* There are other warning on ZynqMP firmware reported from testbot
  which is not introduced by this patch set.
  "[PATCH] firmware: xlnx-zynqmp: fix compilation warning" is submitted
  for those fixes.

Izhar Ameer Shaikh (1):
  firmware: xilinx: Add IOCTL support for AIE ISR Clear

Nishad Saraf (2):
  misc: xilinx-ai-engine: Add support to request device management
services
  misc: xilinx-ai-engine: Add support for servicing error interrupts

Wendy Liang (6):
  dt-binding: soc: xilinx: ai-engine: Add AI engine binding
  misc: Add Xilinx AI engine device driver
  misc: xilinx-ai-engine: Implement AI engine cleanup sequence
  misc: xilinx-ai-engine: expose AI engine tile memories to userspace
  misc: xilinx-ai-engine: add setting shim dma bd operation
  misc: xilinx-ai-engine: add request and release tiles

 .../bindings/soc/xilinx/xlnx,ai-engine.yaml| 126 
 MAINTAINERS|   8 +
 drivers/firmware/xilinx/zynqmp.c   |  14 +
 drivers/misc/Kconfig   |  12 +
 drivers/misc/Makefile  |   1 +
 drivers/misc/xilinx-ai-engine/Makefile |  16 +
 drivers/misc/xilinx-ai-engine/ai-engine-aie.c  | 608 +++
 drivers/misc/xilinx-ai-engine/ai-engine-clock.c| 244 
 drivers/misc/xilinx-ai-engine/ai-engine-dev.c  | 492 +++
 drivers/misc/xilinx-ai-engine/ai-engine-dma.c  | 481 +++
 drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 519 
 .../misc/xilinx-ai-engine/ai-engine-interrupt.c| 659 +
 drivers/misc/xilinx-ai-engine/ai-engine-mem.c  | 274 +
 drivers/misc/xilinx-ai-engine/ai-engine-part.c | 635 
 drivers/misc/xilinx-ai-engine/ai-engine-res.c  | 219 +++
 drivers/misc/xilinx-ai-engine/ai-engine-reset.c| 159 +
 include/linux/firmware/xlnx-zynqmp.h   |   8 +
 include/uapi/linux/xlnx-ai-engine.h| 236 
 18 files changed, 4711 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
 create mode 100644 drivers/misc/xilinx-ai-engine/Makefile
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-aie.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-clock.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dev.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dma.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-internal.h
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-interrupt.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-mem.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-part.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-res.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-reset.c
 create mode 100644 include/uapi/linux/xlnx-ai-engine.h

-- 
2.7.4

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[PATCH v5 2/7] clk: rockchip: fix i2s gate bits on rk3066 and rk3188

The Rockchip PX2/RK3066 uses these bits in CRU_CLKGATE7_CON:

hclk_i2s_8ch_gate_en  bit 4 (dtsi: i2s0)
hclk_i2s0_2ch_gate_en bit 2 (dtsi: i2s1)
hclk_i2s1_2ch_gate_en bit 3 (dtsi: i2s2)

The Rockchip PX3/RK3188 uses this bit in CRU_CLKGATE7_CON:

hclk_i2s_2ch_gate_en  bit 2 (dtsi: i2s0)

The bits got somehow mixed up in the clk-rk3188.c file.
The labels in the dtsi files are not suppose to change.
The sclk and hclk names should match for
"trace_event=clk_disable,clk_enable",
so remove GATE HCLK_I2S0 from the common clock tree and
fix the bits in the rk3066 and rk3188 clock tree.

Signed-off-by: Johan Jonker 
---
Changed v3:
  reword
---
 drivers/clk/rockchip/clk-rk3188.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3188.c 
b/drivers/clk/rockchip/clk-rk3188.c
index db8c58813..0b76ad34d 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -449,7 +449,6 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
 
/* hclk_cpu gates */
GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, 
GFLAGS),
-   GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, 
GFLAGS),
GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, 
GFLAGS),
GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS),
/* hclk_ahb2apb is part of a clk branch */
@@ -634,8 +633,9 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] 
__initdata = {
RK2928_CLKGATE_CON(0), 12, GFLAGS,
&rk3066a_i2s2_fracmux),
 
-   GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, 
GFLAGS),
-   GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, 
GFLAGS),
+   GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, 
GFLAGS),
+   GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, 
GFLAGS),
+   GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, 
GFLAGS),
GATE(HCLK_CIF1, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, 
GFLAGS),
GATE(HCLK_HDMI, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, 
GFLAGS),
 
@@ -728,6 +728,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] 
__initdata = {
RK2928_CLKGATE_CON(0), 10, GFLAGS,
&rk3188_i2s0_fracmux),
 
+   GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, 
GFLAGS),
GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
 
-- 
2.11.0

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[PATCH 6/9] misc: xilinx-ai-engine: add request and release tiles

Add request/release and related clock gating functions to AI engine
driver:
* scanning when the partition is being requested to know which tiles
  are in use.
* check if a tile is gated or not
* tiles requesting and releasing ioctl so that user application can
  enable/disable tiles at runtime.

Signed-off-by: Wendy Liang 
Reviewed-by: Hyun Kwon 
---
 drivers/misc/xilinx-ai-engine/Makefile |   1 +
 drivers/misc/xilinx-ai-engine/ai-engine-aie.c  | 227 ++-
 drivers/misc/xilinx-ai-engine/ai-engine-clock.c| 244 +
 drivers/misc/xilinx-ai-engine/ai-engine-dev.c  |  19 +-
 drivers/misc/xilinx-ai-engine/ai-engine-internal.h |  34 +++
 drivers/misc/xilinx-ai-engine/ai-engine-part.c |  32 +++
 drivers/misc/xilinx-ai-engine/ai-engine-res.c  |  51 +
 include/uapi/linux/xlnx-ai-engine.h|  31 +++
 8 files changed, 631 insertions(+), 8 deletions(-)
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-clock.c

diff --git a/drivers/misc/xilinx-ai-engine/Makefile 
b/drivers/misc/xilinx-ai-engine/Makefile
index 1b743fa..2e67b25 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -6,6 +6,7 @@
 obj-$(CONFIG_XILINX_AIE)   += xilinx-aie.o
 
 xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
+  ai-engine-clock.o \
   ai-engine-dev.o \
   ai-engine-dma.o \
   ai-engine-mem.o \
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c 
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index 19c262d..ff721b3 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -41,6 +41,9 @@
 #define AIE_SHIMPL_SHIMRST_MASK0x1U
 #define AIE_SHIMPL_COLRST_MASK 0x1U
 #define AIE_SHIMPL_CLKCNTR_COLBUF_MASK 0x1U
+#define AIE_SHIMPL_CLKCNTR_NEXTCLK_MASKBIT(1)
+#define AIE_TILE_CLKCNTR_COLBUF_MASK   BIT(0)
+#define AIE_TILE_CLKCNTR_NEXTCLK_MASK  BIT(1)
 
 /*
  * AI engine SHIM reset ID.
@@ -221,10 +224,232 @@ static int aie_reset_shim(struct aie_device *adev, 
struct aie_range *range)
return 0;
 }
 
+static int aie_init_part_clk_state(struct aie_partition *apart)
+{
+   int ret, num_tiles;
+
+   num_tiles = apart->range.size.col * (apart->range.size.row - 1);
+
+   ret = aie_resource_initialize(&apart->cores_clk_state, num_tiles);
+   if (ret) {
+   dev_err(&apart->dev,
+   "failed to initialize cores clock state resource.\n");
+   return ret;
+   }
+
+   ret = aie_resource_initialize(&apart->tiles_inuse, num_tiles);
+   if (ret) {
+   dev_err(&apart->dev,
+   "failed to initialize tiles in use resource.\n");
+   return ret;
+   }
+
+   return 0;
+}
+
+static int aie_scan_part_clocks(struct aie_partition *apart)
+{
+   struct aie_device *adev = apart->adev;
+   struct aie_range *range = &apart->range;
+   struct aie_location loc;
+
+   /* Clear the bitmap of cores and memories clock state */
+   aie_resource_put_region(&apart->cores_clk_state, 0,
+   apart->cores_clk_state.total);
+
+   for (loc.col = range->start.col;
+loc.col < range->start.col + range->size.col;
+loc.col++) {
+   for (loc.row = range->start.row;
+loc.row < range->start.row + range->size.row - 1;
+loc.row++) {
+   void __iomem *va;
+   u32 val, nbitpos;
+
+   /*
+* Reading registers of the current tile to see the next
+* tile is clock gated.
+*/
+   nbitpos = loc.col * (range->size.row - 1) + loc.row;
+
+   if (aie_get_tile_type(&loc) != AIE_TILE_TYPE_TILE) {
+   /* Checks shim tile for next core tile */
+   va = adev->base +
+aie_cal_regoff(adev, loc,
+   AIE_SHIMPL_CLKCNTR_REGOFF);
+   val = ioread32(va);
+
+   /*
+* check if the clock buffer and the next clock
+* tile is set, if one of them is not set, the
+* tiles of the column are clock gated.
+*/
+   if (!(val & AIE_SHIMPL_CLKCNTR_COLBUF_MASK) ||
+   !(val & AIE_SHIMPL_CLKCNTR_NEXTCLK_MASK))
+   break;
+
+   /* Set next tile in the row clock state on */
+

[PATCH v3 05/11] dt-bindings: phy: convert phy-mtk-ufs.txt to YAML schema

Convert phy-mtk-ufs.txt to YAML schema mediatek,ufs-phy.yaml

Cc: Stanley Chu 
Signed-off-by: Chunfeng Yun 
Reviewed-by: Rob Herring 
---
v3: add Reviewed-by Rob
v2: fix binding check warning of reg in example
---
 .../bindings/phy/mediatek,ufs-phy.yaml| 64 +++
 .../devicetree/bindings/phy/phy-mtk-ufs.txt   | 38 ---
 2 files changed, 64 insertions(+), 38 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
 delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt

diff --git a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml 
b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
new file mode 100644
index ..3a9be82e7f13
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,ufs-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Universal Flash Storage (UFS) M-PHY binding
+
+maintainers:
+  - Stanley Chu 
+  - Chunfeng Yun 
+
+description: |
+  UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
+  Each UFS M-PHY node should have its own node.
+  To bind UFS M-PHY with UFS host controller, the controller node should
+  contain a phandle reference to UFS M-PHY node.
+
+properties:
+  $nodename:
+pattern: "^ufs-phy@[0-9a-f]+$"
+
+  compatible:
+const: mediatek,mt8183-ufsphy
+
+  reg:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Unipro core control clock.
+  - description: M-PHY core control clock.
+
+  clock-names:
+items:
+  - const: unipro
+  - const: mp
+
+  "#phy-cells":
+const: 0
+
+required:
+  - compatible
+  - reg
+  - "#phy-cells"
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+ufsphy: ufs-phy@11fa {
+compatible = "mediatek,mt8183-ufsphy";
+reg = <0x11fa 0xc000>;
+clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
+ <&infracfg CLK_INFRA_UFS_MP_SAP_BCLK>;
+clock-names = "unipro", "mp";
+#phy-cells = <0>;
+};
+
+...
diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt 
b/Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt
deleted file mode 100644
index 5789029a1d42..
--- a/Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-MediaTek Universal Flash Storage (UFS) M-PHY binding
-
-
-UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
-Each UFS M-PHY node should have its own node.
-
-To bind UFS M-PHY with UFS host controller, the controller node should
-contain a phandle reference to UFS M-PHY node.
-
-Required properties for UFS M-PHY nodes:
-- compatible : Compatible list, contains the following controller:
-   "mediatek,mt8183-ufsphy" for ufs phy
-   persent on MT81xx chipsets.
-- reg: Address and length of the UFS M-PHY register set.
-- #phy-cells : This property shall be set to 0.
-- clocks : List of phandle and clock specifier pairs.
-- clock-names: List of clock input name strings sorted in the same
-   order as the clocks property. Following clocks are
-   mandatory.
-   "unipro": Unipro core control clock.
-   "mp": M-PHY core control clock.
-
-Example:
-
-   ufsphy: phy@11fa {
-   compatible = "mediatek,mt8183-ufsphy";
-   reg = <0 0x11fa 0 0xc000>;
-   #phy-cells = <0>;
-
-   clocks = <&infracfg_ao INFRACFG_AO_UNIPRO_SCK_CG>,
-<&infracfg_ao INFRACFG_AO_UFS_MP_SAP_BCLK_CG>;
-   clock-names = "unipro", "mp";
-   };
-
-   ufshci@1127 {
-   ...
-   phys = <&ufsphy>;
-   };
-- 
2.18.0

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[PATCH v2 5/9] misc: xilinx-ai-engine: add setting shim dma bd operation

Add operation to set SHIM DMA buffer descriptor.

The following operations are added to set the buffer descriptors:
* attach DMA buffer which enables AI engine device to access the DMA
  buffer memory
* detach DMA buffer which disables AI engine device to access the DMA
  buffer memory
* set DMA buffer descriptor, which takes buffer descriptor contents
  pointer, the dmabuf fd, and the offset to the start of dmabuf as
  as argument. It validates the dmabuf and the offset and size of the
  buffer. And then it calculates the DMA address of the buffer and set
  the buffer descriptor content to the hardware DMA buffer descriptor.

The main logic to control what's go into the buffer descriptor and which
buffer descriptor to use is in the userspace AI engine library.

Signed-off-by: Wendy Liang 
Reviewed-by: Hyun Kwon 
---
 drivers/misc/xilinx-ai-engine/Makefile |   1 +
 drivers/misc/xilinx-ai-engine/ai-engine-aie.c  |  19 +
 drivers/misc/xilinx-ai-engine/ai-engine-dma.c  | 481 +
 drivers/misc/xilinx-ai-engine/ai-engine-internal.h |  45 ++
 drivers/misc/xilinx-ai-engine/ai-engine-part.c |  17 +
 include/uapi/linux/xlnx-ai-engine.h|  43 ++
 6 files changed, 606 insertions(+)
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dma.c

diff --git a/drivers/misc/xilinx-ai-engine/Makefile 
b/drivers/misc/xilinx-ai-engine/Makefile
index 2dbed42..1b743fa 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_XILINX_AIE)+= xilinx-aie.o
 
 xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
   ai-engine-dev.o \
+  ai-engine-dma.o \
   ai-engine-mem.o \
   ai-engine-part.o \
   ai-engine-res.o \
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c 
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index 7fce2f00..19c262d 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -107,6 +107,24 @@ static const struct aie_single_reg_field aie_col_clkbuf = {
.regoff = AIE_SHIMPL_CLKCNTR_REGOFF,
 };
 
+static const struct aie_dma_attr aie_shimdma = {
+   .laddr = {
+   .mask = 0xU,
+   .regoff = 0U,
+   },
+   .haddr = {
+   .mask = 0xU,
+   .regoff = 0x8U,
+   },
+   .buflen = {
+   .mask = 0xU,
+   .regoff = 0x4U,
+   },
+   .bd_regoff = 0x0001d000U,
+   .num_bds = 16,
+   .bd_len = 0x14U,
+};
+
 static u32 aie_get_tile_type(struct aie_location *loc)
 {
if (loc->row)
@@ -232,6 +250,7 @@ int aie_device_init(struct aie_device *adev)
adev->kernel_regs = aie_kernel_regs;
adev->col_rst = &aie_col_rst;
adev->col_clkbuf = &aie_col_clkbuf;
+   adev->shim_dma = &aiev1_shimdma;
 
/* Get the columns resource */
/* Get number of columns from AI engine memory resource */
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-dma.c 
b/drivers/misc/xilinx-ai-engine/ai-engine-dma.c
new file mode 100644
index 000..007bec4
--- /dev/null
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-dma.c
@@ -0,0 +1,481 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx AI Engine driver DMA implementation
+ *
+ * Copyright (C) 2020 Xilinx, Inc.
+ */
+
+#include "ai-engine-internal.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * struct aie_dmabuf - AI engine dmabuf information
+ * @attach: dmabuf attachment pointer
+ * @sgt: scatter/gather table
+ * @refs: refcount of the attached aie_dmabuf
+ * @node: list node
+ */
+struct aie_dmabuf {
+   struct dma_buf_attachment *attach;
+   struct sg_table *sgt;
+   refcount_t refs;
+   struct list_head node;
+};
+
+/**
+ * aie_part_find_dmabuf() - find a attached dmabuf
+ * @apart: AI engine partition
+ * @dmabuf: pointer to dmabuf
+ * @return: pointer to AI engine dmabuf struct of the found dmabuf, if dmabuf
+ * is not found, returns NULL.
+ *
+ * This function scans all the attached dmabufs to see the input dmabuf is
+ * in the list. if it is attached, return the corresponding struct aie_dmabuf
+ * pointer.
+ */
+static struct aie_dmabuf *
+aie_part_find_dmabuf(struct aie_partition *apart, struct dma_buf *dmabuf)
+{
+   struct aie_dmabuf *adbuf;
+
+   list_for_each_entry(adbuf, &apart->dbufs, node) {
+   if (dmabuf == adbuf->attach->dmabuf)
+   return adbuf;
+   }
+
+   return NULL;
+}
+
+/**
+ * aie_part_get_dmabuf_da_from_off() - get DMA address from offset to a dmabuf
+ * @apart: AI engine partition
+ * @dmabuf_fd: dmabuf file descriptor
+ * @off: offset to the start of a dmabuf
+ * @len: memory length
+ * @return: dma address, or 0 if @off or @len

[PATCH v2 2/9] misc: Add Xilinx AI engine device driver

Create AI engine device/partition hierarchical structure.

Each AI engine device can have multiple logical partitions(groups of AI
engine tiles). Each partition is column based and has its own node ID
in the system. AI engine device driver manages its partitions.

Applications can access AI engine partition through the AI engine
partition driver instance. AI engine registers write is moved to kernel
as there are registers in the AI engine array needs privilege
permission.

Signed-off-by: Wendy Liang 
Signed-off-by: Hyun Kwon 
---
 MAINTAINERS|   8 +
 drivers/misc/Kconfig   |  12 +
 drivers/misc/Makefile  |   1 +
 drivers/misc/xilinx-ai-engine/Makefile |  11 +
 drivers/misc/xilinx-ai-engine/ai-engine-aie.c  | 115 +
 drivers/misc/xilinx-ai-engine/ai-engine-dev.c  | 448 ++
 drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 226 ++
 drivers/misc/xilinx-ai-engine/ai-engine-part.c | 498 +
 drivers/misc/xilinx-ai-engine/ai-engine-res.c  | 114 +
 include/uapi/linux/xlnx-ai-engine.h| 107 +
 10 files changed, 1540 insertions(+)
 create mode 100644 drivers/misc/xilinx-ai-engine/Makefile
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-aie.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dev.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-internal.h
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-part.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-res.c
 create mode 100644 include/uapi/linux/xlnx-ai-engine.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 5cc595a..40e3351 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19283,6 +19283,14 @@ T: git https://github.com/Xilinx/linux-xlnx.git
 F: Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
 F: drivers/phy/xilinx/phy-zynqmp.c
 
+XILINX AI ENGINE DRIVER
+M: Wendy Liang 
+S: Supported
+F: Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
+F: drivers/misc/xilinx-ai-engine/
+F: include/linux/xlnx-ai-engine.h
+F: include/uapi/linux/xlnx-ai-engine.h
+
 XILLYBUS DRIVER
 M: Eli Billauer 
 L: linux-ker...@vger.kernel.org
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index fafa8b0..0b8ce4d 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -444,6 +444,18 @@ config XILINX_SDFEC
 
  If unsure, say N.
 
+config XILINX_AIE
+   tristate "Xilinx AI engine"
+   depends on ARM64 || COMPILE_TEST
+   help
+ This option enables support for the Xilinx AI engine driver.
+ One Xilinx AI engine device can have multiple partitions (groups of
+ AI engine tiles). Xilinx AI engine device driver instance manages
+ AI engine partitions. User application access its partitions through
+ AI engine partition instance file operations.
+
+ If unsure, say N
+
 config MISC_RTSX
tristate
default MISC_RTSX_PCI || MISC_RTSX_USB
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index d23231e..2176b18 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_HABANA_AI)   += habanalabs/
 obj-$(CONFIG_UACCE)+= uacce/
 obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
 obj-$(CONFIG_HISI_HIKEY_USB)   += hisi_hikey_usb.o
+obj-$(CONFIG_XILINX_AIE)   += xilinx-ai-engine/
diff --git a/drivers/misc/xilinx-ai-engine/Makefile 
b/drivers/misc/xilinx-ai-engine/Makefile
new file mode 100644
index 000..7827a0a
--- /dev/null
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Makefile for Xilinx AI engine device driver
+#
+
+obj-$(CONFIG_XILINX_AIE)   += xilinx-aie.o
+
+xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
+  ai-engine-dev.o \
+  ai-engine-part.o \
+  ai-engine-res.o
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c 
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
new file mode 100644
index 000..319260f
--- /dev/null
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx AI Engine driver AIE device specific implementation
+ *
+ * Copyright (C) 2020 Xilinx, Inc.
+ */
+
+#include 
+
+#include "ai-engine-internal.h"
+
+#define AIE_ARRAY_SHIFT30U
+#define AIE_COL_SHIFT  23U
+#define AIE_ROW_SHIFT  18U
+
+/*
+ * Registers offsets
+ */
+#define AIE_SHIMNOC_L2INTR_MASK_REGOFF 0x00015000U
+#define AIE_SHIMNOC_L2INTR_INTR_REGOFF 0x00015010U
+#define AIE_SHIMNOC_DMA_BD0_ADDRLOW_REGOFF 0x0001d000U
+#define AIE_SHIMNOC_DMA_BD15_PACKET_REGOFF 0x0001d13cU
+#define AIE_SHIMNOC_AXIMM_REGOFF   0x0001e020U
+#define AIE_SHIMPL_

[PATCH v2 2/5] thermal: devfreq_cooling: get a copy of device status

Devfreq cooling needs to now the correct status of the device in order
to operate. Do not rely on Devfreq last_status which might be a stale data
and get more up-to-date values of the load.

Devfreq framework can change the device status in the background. To
mitigate this situation make a copy of the status structure and use it
for internal calculations.

In addition this patch adds normalization function, which also makes sure
that whatever data comes from the device, it is in a sane range.

Signed-off-by: Lukasz Luba 
---
 drivers/thermal/devfreq_cooling.c | 52 +--
 1 file changed, 43 insertions(+), 9 deletions(-)

diff --git a/drivers/thermal/devfreq_cooling.c 
b/drivers/thermal/devfreq_cooling.c
index 659c0143c9f0..925523694462 100644
--- a/drivers/thermal/devfreq_cooling.c
+++ b/drivers/thermal/devfreq_cooling.c
@@ -227,20 +227,46 @@ static inline unsigned long get_total_power(struct 
devfreq_cooling_device *dfc,
   voltage);
 }
 
+static void _normalize_load(struct devfreq_dev_status *status)
+{
+   /* Make some space if needed */
+   if (status->busy_time > 0x) {
+   status->busy_time >>= 10;
+   status->total_time >>= 10;
+   }
+
+   if (status->busy_time > status->total_time)
+   status->busy_time = status->total_time;
+
+   status->busy_time *= 100;
+   status->busy_time /= status->total_time ? : 1;
+
+   /* Avoid division by 0 */
+   status->busy_time = status->busy_time ? : 1;
+   status->total_time = 100;
+}
 
 static int devfreq_cooling_get_requested_power(struct thermal_cooling_device 
*cdev,
   u32 *power)
 {
struct devfreq_cooling_device *dfc = cdev->devdata;
struct devfreq *df = dfc->devfreq;
-   struct devfreq_dev_status *status = &df->last_status;
+   struct devfreq_dev_status status;
unsigned long state;
-   unsigned long freq = status->current_frequency;
+   unsigned long freq;
unsigned long voltage;
u32 dyn_power = 0;
u32 static_power = 0;
int res;
 
+   mutex_lock(&df->lock);
+   res = df->profile->get_dev_status(df->dev.parent, &status);
+   mutex_unlock(&df->lock);
+   if (res)
+   return res;
+
+   freq = status.current_frequency;
+
state = freq_get_state(dfc, freq);
if (state == THERMAL_CSTATE_INVALID) {
res = -EAGAIN;
@@ -268,16 +294,18 @@ static int devfreq_cooling_get_requested_power(struct 
thermal_cooling_device *cd
} else {
dyn_power = dfc->power_table[state];
 
+   _normalize_load(&status);
+
/* Scale dynamic power for utilization */
-   dyn_power *= status->busy_time;
-   dyn_power /= status->total_time;
+   dyn_power *= status.busy_time;
+   dyn_power /= status.total_time;
/* Get static power */
static_power = get_static_power(dfc, freq);
 
*power = dyn_power + static_power;
}
 
-   trace_thermal_power_devfreq_get_power(cdev, status, freq, *power);
+   trace_thermal_power_devfreq_get_power(cdev, &status, freq, *power);
 
return 0;
 fail:
@@ -309,14 +337,20 @@ static int devfreq_cooling_power2state(struct 
thermal_cooling_device *cdev,
 {
struct devfreq_cooling_device *dfc = cdev->devdata;
struct devfreq *df = dfc->devfreq;
-   struct devfreq_dev_status *status = &df->last_status;
-   unsigned long freq = status->current_frequency;
+   struct devfreq_dev_status status;
unsigned long busy_time;
+   unsigned long freq;
s32 dyn_power;
u32 static_power;
s32 est_power;
int i;
 
+   mutex_lock(&df->lock);
+   status = df->last_status;
+   mutex_unlock(&df->lock);
+
+   freq = status.current_frequency;
+
if (dfc->power_ops->get_real_power) {
/* Scale for resource utilization */
est_power = power * dfc->res_util;
@@ -328,8 +362,8 @@ static int devfreq_cooling_power2state(struct 
thermal_cooling_device *cdev,
dyn_power = dyn_power > 0 ? dyn_power : 0;
 
/* Scale dynamic power for utilization */
-   busy_time = status->busy_time ?: 1;
-   est_power = (dyn_power * status->total_time) / busy_time;
+   busy_time = status.busy_time ?: 1;
+   est_power = (dyn_power * status.total_time) / busy_time;
}
 
/*
-- 
2.17.1

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[PATCH 2/9] misc: Add Xilinx AI engine device driver

Create AI engine device/partition hierarchical structure.

Each AI engine device can have multiple logical partitions(groups of AI
engine tiles). Each partition is column based and has its own node ID
in the system. AI engine device driver manages its partitions.

Applications can access AI engine partition through the AI engine
partition driver instance. AI engine registers write is moved to kernel
as there are registers in the AI engine array needs privilege
permission.

Signed-off-by: Wendy Liang 
Signed-off-by: Hyun Kwon 
---
 MAINTAINERS|   8 +
 drivers/misc/Kconfig   |  12 +
 drivers/misc/Makefile  |   1 +
 drivers/misc/xilinx-ai-engine/Makefile |  11 +
 drivers/misc/xilinx-ai-engine/ai-engine-aie.c  | 115 +
 drivers/misc/xilinx-ai-engine/ai-engine-dev.c  | 448 ++
 drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 226 ++
 drivers/misc/xilinx-ai-engine/ai-engine-part.c | 498 +
 drivers/misc/xilinx-ai-engine/ai-engine-res.c  | 114 +
 include/uapi/linux/xlnx-ai-engine.h| 107 +
 10 files changed, 1540 insertions(+)
 create mode 100644 drivers/misc/xilinx-ai-engine/Makefile
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-aie.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dev.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-internal.h
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-part.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-res.c
 create mode 100644 include/uapi/linux/xlnx-ai-engine.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 5cc595a..40e3351 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19283,6 +19283,14 @@ T: git https://github.com/Xilinx/linux-xlnx.git
 F: Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
 F: drivers/phy/xilinx/phy-zynqmp.c
 
+XILINX AI ENGINE DRIVER
+M: Wendy Liang 
+S: Supported
+F: Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
+F: drivers/misc/xilinx-ai-engine/
+F: include/linux/xlnx-ai-engine.h
+F: include/uapi/linux/xlnx-ai-engine.h
+
 XILLYBUS DRIVER
 M: Eli Billauer 
 L: linux-ker...@vger.kernel.org
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index fafa8b0..0b8ce4d 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -444,6 +444,18 @@ config XILINX_SDFEC
 
  If unsure, say N.
 
+config XILINX_AIE
+   tristate "Xilinx AI engine"
+   depends on ARM64 || COMPILE_TEST
+   help
+ This option enables support for the Xilinx AI engine driver.
+ One Xilinx AI engine device can have multiple partitions (groups of
+ AI engine tiles). Xilinx AI engine device driver instance manages
+ AI engine partitions. User application access its partitions through
+ AI engine partition instance file operations.
+
+ If unsure, say N
+
 config MISC_RTSX
tristate
default MISC_RTSX_PCI || MISC_RTSX_USB
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index d23231e..2176b18 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_HABANA_AI)   += habanalabs/
 obj-$(CONFIG_UACCE)+= uacce/
 obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
 obj-$(CONFIG_HISI_HIKEY_USB)   += hisi_hikey_usb.o
+obj-$(CONFIG_XILINX_AIE)   += xilinx-ai-engine/
diff --git a/drivers/misc/xilinx-ai-engine/Makefile 
b/drivers/misc/xilinx-ai-engine/Makefile
new file mode 100644
index 000..7827a0a
--- /dev/null
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Makefile for Xilinx AI engine device driver
+#
+
+obj-$(CONFIG_XILINX_AIE)   += xilinx-aie.o
+
+xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
+  ai-engine-dev.o \
+  ai-engine-part.o \
+  ai-engine-res.o
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c 
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
new file mode 100644
index 000..319260f
--- /dev/null
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx AI Engine driver AIE device specific implementation
+ *
+ * Copyright (C) 2020 Xilinx, Inc.
+ */
+
+#include 
+
+#include "ai-engine-internal.h"
+
+#define AIE_ARRAY_SHIFT30U
+#define AIE_COL_SHIFT  23U
+#define AIE_ROW_SHIFT  18U
+
+/*
+ * Registers offsets
+ */
+#define AIE_SHIMNOC_L2INTR_MASK_REGOFF 0x00015000U
+#define AIE_SHIMNOC_L2INTR_INTR_REGOFF 0x00015010U
+#define AIE_SHIMNOC_DMA_BD0_ADDRLOW_REGOFF 0x0001d000U
+#define AIE_SHIMNOC_DMA_BD15_PACKET_REGOFF 0x0001d13cU
+#define AIE_SHIMNOC_AXIMM_REGOFF   0x0001e020U
+#define AIE_SHIMPL_

[PATCH 5/9] misc: xilinx-ai-engine: add setting shim dma bd operation

Add operation to set SHIM DMA buffer descriptor.

The following operations are added to set the buffer descriptors:
* attach DMA buffer which enables AI engine device to access the DMA
  buffer memory
* detach DMA buffer which disables AI engine device to access the DMA
  buffer memory
* set DMA buffer descriptor, which takes buffer descriptor contents
  pointer, the dmabuf fd, and the offset to the start of dmabuf as
  as argument. It validates the dmabuf and the offset and size of the
  buffer. And then it calculates the DMA address of the buffer and set
  the buffer descriptor content to the hardware DMA buffer descriptor.

The main logic to control what's go into the buffer descriptor and which
buffer descriptor to use is in the userspace AI engine library.

Signed-off-by: Wendy Liang 
Reviewed-by: Hyun Kwon 
---
 drivers/misc/xilinx-ai-engine/Makefile |   1 +
 drivers/misc/xilinx-ai-engine/ai-engine-aie.c  |  19 +
 drivers/misc/xilinx-ai-engine/ai-engine-dma.c  | 481 +
 drivers/misc/xilinx-ai-engine/ai-engine-internal.h |  45 ++
 drivers/misc/xilinx-ai-engine/ai-engine-part.c |  17 +
 include/uapi/linux/xlnx-ai-engine.h|  43 ++
 6 files changed, 606 insertions(+)
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dma.c

diff --git a/drivers/misc/xilinx-ai-engine/Makefile 
b/drivers/misc/xilinx-ai-engine/Makefile
index 2dbed42..1b743fa 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_XILINX_AIE)+= xilinx-aie.o
 
 xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
   ai-engine-dev.o \
+  ai-engine-dma.o \
   ai-engine-mem.o \
   ai-engine-part.o \
   ai-engine-res.o \
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c 
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index 7fce2f00..19c262d 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -107,6 +107,24 @@ static const struct aie_single_reg_field aie_col_clkbuf = {
.regoff = AIE_SHIMPL_CLKCNTR_REGOFF,
 };
 
+static const struct aie_dma_attr aie_shimdma = {
+   .laddr = {
+   .mask = 0xU,
+   .regoff = 0U,
+   },
+   .haddr = {
+   .mask = 0xU,
+   .regoff = 0x8U,
+   },
+   .buflen = {
+   .mask = 0xU,
+   .regoff = 0x4U,
+   },
+   .bd_regoff = 0x0001d000U,
+   .num_bds = 16,
+   .bd_len = 0x14U,
+};
+
 static u32 aie_get_tile_type(struct aie_location *loc)
 {
if (loc->row)
@@ -232,6 +250,7 @@ int aie_device_init(struct aie_device *adev)
adev->kernel_regs = aie_kernel_regs;
adev->col_rst = &aie_col_rst;
adev->col_clkbuf = &aie_col_clkbuf;
+   adev->shim_dma = &aiev1_shimdma;
 
/* Get the columns resource */
/* Get number of columns from AI engine memory resource */
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-dma.c 
b/drivers/misc/xilinx-ai-engine/ai-engine-dma.c
new file mode 100644
index 000..007bec4
--- /dev/null
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-dma.c
@@ -0,0 +1,481 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx AI Engine driver DMA implementation
+ *
+ * Copyright (C) 2020 Xilinx, Inc.
+ */
+
+#include "ai-engine-internal.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * struct aie_dmabuf - AI engine dmabuf information
+ * @attach: dmabuf attachment pointer
+ * @sgt: scatter/gather table
+ * @refs: refcount of the attached aie_dmabuf
+ * @node: list node
+ */
+struct aie_dmabuf {
+   struct dma_buf_attachment *attach;
+   struct sg_table *sgt;
+   refcount_t refs;
+   struct list_head node;
+};
+
+/**
+ * aie_part_find_dmabuf() - find a attached dmabuf
+ * @apart: AI engine partition
+ * @dmabuf: pointer to dmabuf
+ * @return: pointer to AI engine dmabuf struct of the found dmabuf, if dmabuf
+ * is not found, returns NULL.
+ *
+ * This function scans all the attached dmabufs to see the input dmabuf is
+ * in the list. if it is attached, return the corresponding struct aie_dmabuf
+ * pointer.
+ */
+static struct aie_dmabuf *
+aie_part_find_dmabuf(struct aie_partition *apart, struct dma_buf *dmabuf)
+{
+   struct aie_dmabuf *adbuf;
+
+   list_for_each_entry(adbuf, &apart->dbufs, node) {
+   if (dmabuf == adbuf->attach->dmabuf)
+   return adbuf;
+   }
+
+   return NULL;
+}
+
+/**
+ * aie_part_get_dmabuf_da_from_off() - get DMA address from offset to a dmabuf
+ * @apart: AI engine partition
+ * @dmabuf_fd: dmabuf file descriptor
+ * @off: offset to the start of a dmabuf
+ * @len: memory length
+ * @return: dma address, or 0 if @off or @len

[PATCH v2 1/5] thermal: devfreq_cooling: change tracing function and arguments

Prepare for deleting the static and dynamic power calculation and clean
the trace function. These two fields are going to be removed in the next
changes.

Reviewed-by: Steven Rostedt (VMware)  # for tracing code
Signed-off-by: Lukasz Luba 
---
 drivers/thermal/devfreq_cooling.c |  3 +--
 include/trace/events/thermal.h| 19 +--
 2 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/drivers/thermal/devfreq_cooling.c 
b/drivers/thermal/devfreq_cooling.c
index dfab49a67252..659c0143c9f0 100644
--- a/drivers/thermal/devfreq_cooling.c
+++ b/drivers/thermal/devfreq_cooling.c
@@ -277,8 +277,7 @@ static int devfreq_cooling_get_requested_power(struct 
thermal_cooling_device *cd
*power = dyn_power + static_power;
}
 
-   trace_thermal_power_devfreq_get_power(cdev, status, freq, dyn_power,
- static_power, *power);
+   trace_thermal_power_devfreq_get_power(cdev, status, freq, *power);
 
return 0;
 fail:
diff --git a/include/trace/events/thermal.h b/include/trace/events/thermal.h
index 135e5421f003..8a5f04888abd 100644
--- a/include/trace/events/thermal.h
+++ b/include/trace/events/thermal.h
@@ -153,31 +153,30 @@ TRACE_EVENT(thermal_power_cpu_limit,
 TRACE_EVENT(thermal_power_devfreq_get_power,
TP_PROTO(struct thermal_cooling_device *cdev,
 struct devfreq_dev_status *status, unsigned long freq,
-   u32 dynamic_power, u32 static_power, u32 power),
+   u32 power),
 
-   TP_ARGS(cdev, status,  freq, dynamic_power, static_power, power),
+   TP_ARGS(cdev, status,  freq, power),
 
TP_STRUCT__entry(
__string(type, cdev->type)
__field(unsigned long, freq  )
-   __field(u32,   load  )
-   __field(u32,   dynamic_power )
-   __field(u32,   static_power  )
+   __field(u32,   busy_time)
+   __field(u32,   total_time)
__field(u32,   power)
),
 
TP_fast_assign(
__assign_str(type, cdev->type);
__entry->freq = freq;
-   __entry->load = (100 * status->busy_time) / status->total_time;
-   __entry->dynamic_power = dynamic_power;
-   __entry->static_power = static_power;
+   __entry->busy_time = status->busy_time;
+   __entry->total_time = status->total_time;
__entry->power = power;
),
 
-   TP_printk("type=%s freq=%lu load=%u dynamic_power=%u static_power=%u 
power=%u",
+   TP_printk("type=%s freq=%lu load=%u power=%u",
__get_str(type), __entry->freq,
-   __entry->load, __entry->dynamic_power, __entry->static_power,
+   __entry->total_time == 0 ? 0 :
+   (100 * __entry->busy_time) / __entry->total_time,
__entry->power)
 );
 
-- 
2.17.1

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[PATCH v3 01/11] dt-bindings: usb: convert usb-device.txt to YAML schema

Convert usb-device.txt to YAML schema usb-device.yaml

Signed-off-by: Chunfeng Yun 
---
v3:
  1. remove $nodenmae and items key word for compatilbe;
  2. add additionalProperties;

  The followings are suggested by Rob:
  3. merge the following patch
[v2,1/4] dt-bindings: usb: convert usb-device.txt to YAML schema
[v2,2/4] dt-bindings: usb: add properties for hard wired devices
  4. define the unit-address for hard-wired device in usb-hcd.yaml,
 also define its 'reg' and 'compatible';
  5. This series is base on Serge's series:

https://patchwork.kernel.org/project/linux-usb/cover/2020090853.14112-1-sergey.se...@baikalelectronics.ru/
[v4,00/18] dt-bindings: usb: Add generic USB HCD, xHCI, DWC USB3 DT schema

v2 changes suggested by Rob:
  1. modify pattern to support any USB class
  2. convert usb-device.txt into usb-device.yaml
---
 .../devicetree/bindings/usb/usb-device.txt| 102 --
 .../devicetree/bindings/usb/usb-device.yaml   | 125 ++
 .../devicetree/bindings/usb/usb-hcd.yaml  |  33 +
 3 files changed, 158 insertions(+), 102 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/usb/usb-device.txt
 create mode 100644 Documentation/devicetree/bindings/usb/usb-device.yaml

diff --git a/Documentation/devicetree/bindings/usb/usb-device.txt 
b/Documentation/devicetree/bindings/usb/usb-device.txt
deleted file mode 100644
index 036be172b1ae..
--- a/Documentation/devicetree/bindings/usb/usb-device.txt
+++ /dev/null
@@ -1,102 +0,0 @@
-Generic USB Device Properties
-
-Usually, we only use device tree for hard wired USB device.
-The reference binding doc is from:
-http://www.devicetree.org/open-firmware/bindings/usb/usb-1_0.ps
-
-Four types of device-tree nodes are defined: "host-controller nodes"
-representing USB host controllers, "device nodes" representing USB devices,
-"interface nodes" representing USB interfaces and "combined nodes"
-representing simple USB devices.
-
-A combined node shall be used instead of a device node and an interface node
-for devices of class 0 or 9 (hub) with a single configuration and a single
-interface.
-
-A "hub node" is a combined node or an interface node that represents a USB
-hub.
-
-
-Required properties for device nodes:
-- compatible: "usbVID,PID", where VID is the vendor id and PID the product id.
-  The textual representation of VID and PID shall be in lower case hexadecimal
-  with leading zeroes suppressed. The other compatible strings from the above
-  standard binding could also be used, but a device adhering to this binding
-  may leave out all except for "usbVID,PID".
-- reg: the number of the USB hub port or the USB host-controller port to which
-  this device is attached. The range is 1-255.
-
-
-Required properties for device nodes with interface nodes:
-- #address-cells: shall be 2
-- #size-cells: shall be 0
-
-
-Required properties for interface nodes:
-- compatible: "usbifVID,PID.configCN.IN", where VID is the vendor id, PID is
-  the product id, CN is the configuration value and IN is the interface
-  number. The textual representation of VID, PID, CN and IN shall be in lower
-  case hexadecimal with leading zeroes suppressed. The other compatible
-  strings from the above standard binding could also be used, but a device
-  adhering to this binding may leave out all except for
-  "usbifVID,PID.configCN.IN".
-- reg: the interface number and configuration value
-
-The configuration component is not included in the textual representation of
-an interface-node unit address for configuration 1.
-
-
-Required properties for combined nodes:
-- compatible: "usbVID,PID", where VID is the vendor id and PID the product id.
-  The textual representation of VID and PID shall be in lower case hexadecimal
-  with leading zeroes suppressed. The other compatible strings from the above
-  standard binding could also be used, but a device adhering to this binding
-  may leave out all except for "usbVID,PID".
-- reg: the number of the USB hub port or the USB host-controller port to which
-  this device is attached. The range is 1-255.
-
-
-Required properties for hub nodes with device nodes:
-- #address-cells: shall be 1
-- #size-cells: shall be 0
-
-
-Required properties for host-controller nodes with device nodes:
-- #address-cells: shall be 1
-- #size-cells: shall be 0
-
-
-Example:
-
-&usb1 {/* host controller */
-   #address-cells = <1>;
-   #size-cells = <0>;
-
-   hub@1 { /* hub connected to port 1 */
-   compatible = "usb5e3,608";
-   reg = <1>;
-   };
-
-   device@2 {  /* device connected to port 2 */
-   compatible = "usb123,4567";
-   reg = <2>;
-   };
-
-   device@3 {  /* device connected to port 3 */
-   compatible = "usb123,abcd";
-   reg = <3>;
-
-   #address-cells = <2>;
-   #size-cells = <0>;
-
-   interface@0 {

[PATCH v2 5/5] drm/panfrost: Register devfreq cooling and attempt to add Energy Model

Register devfreq cooling device and attempt to register Energy Model. This
will add the devfreq device to the Energy Model framework. It will create
a dedicated and unified data structures used i.e. in thermal framework.
The last NULL parameter indicates that the power model is simplified and
created based on DT 'dynamic-power-coefficient', voltage and frequency.

Reviewed-by: Steven Price 
Reviewed-by: Alyssa Rosenzweig 
Signed-off-by: Lukasz Luba 
---
 drivers/gpu/drm/panfrost/panfrost_devfreq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c 
b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index 78e9d82f7318..f44d28fad085 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -138,7 +138,7 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
}
pfdevfreq->devfreq = devfreq;
 
-   cooling = of_devfreq_cooling_register(dev->of_node, devfreq);
+   cooling = devfreq_cooling_em_register(devfreq, NULL);
if (IS_ERR(cooling))
DRM_DEV_INFO(dev, "Failed to register cooling device\n");
else
-- 
2.17.1

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[PATCH v2 0/3] Add bus format negotiation support for Cadence MHDP8546 driver

This patch series add bus format negotiation support for Cadence MHDP8546
bridge driver.

The patch series has four patches in the below sequence:
1. drm: bridge: cdns-mhdp8546: Modify atomic_get_input_bus_format bridge
function.
Return all the input formats supported.
2. drm: bridge: cdns-mhdp8546: Remove setting of bus format using connector
info
Remove the bus format configuration using connector info structure.
3. drm: bridge: cdns-mhdp8546: Retrieve the pixel format and bpc based on bus
format
Get the pixel format and bpc based on negotiated output bus format.

This patch series is dependent on tidss series [1] for the new connector model
support.

[1]

https://patchwork.kernel.org/project/dri-devel/cover/20201109170601.21557-1-nikhil...@ti.com/

Version History:

v2:
- Remove the Add output bus format negotiation patch from the series,
as we use ouput format as MEDIA_BUS_FMT_FIXED and that is the
default value if atomic_get_output_bus_fmts function is not implemented.
- Return NULL if output format is not MEDIA_BUS_FMT_FIXED.
- Return the supported color formats based on the display info structure.

Yuti Amonkar (3):
drm: bridge: cdns-mhdp8546: Modify atomic_get_input_bus_format bridge
function
drm: bridge: cdns-mhdp8546: Remove setting of bus format using
connector info
drm: bridge: cdns-mhdp8546: Retrieve the pixel format and bpc based on
bus format

.../drm/bridge/cadence/cdns-mhdp8546-core.c | 133 +-
1 file changed, 99 insertions(+), 34 deletions(-)

--
2.17.1

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[PATCH] drm/vmwgfx: use min_t to replace min

Use min_t to replace min, min_t is a bit fast because min use
twice typeof.
This patch also fix check_patch.pl warning:
WARNING: min() should probably be min_t(unsigned long, num_pages,
VMW_PPN_PER_REMAP)
+unsigned long nr = min(num_pages, (unsigned long)
VMW_PPN_PER_REMAP);

Signed-off-by: Bernard Zhao 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c
index 83c0d5a3e4fd..b8f6fe1a71e6 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c
@@ -72,7 +72,7 @@ static int vmw_gmr2_bind(struct vmw_private *dev_priv,
SVGA_REMAP_GMR2_PPN64 : SVGA_REMAP_GMR2_PPN32;
 
while (num_pages > 0) {
-   unsigned long nr = min(num_pages, (unsigned 
long)VMW_PPN_PER_REMAP);
+   unsigned long nr = min_t((unsigned long), num_pages, 
VMW_PPN_PER_REMAP);
 
remap_cmd.offsetPages = remap_pos;
remap_cmd.numPages = nr;
-- 
2.29.0

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[PATCH 0/9] Xilinx AI engine kernel driver

AI engine is the acceleration engine provided by Xilinx. These engines
provide high compute density for vector-based algorithms, and flexible
custom compute and data movement. It has core tiles for compute and
shim tiles to interface the FPGA fabric.

You can check the AI engine architecture document for more hardware details:
https://www.xilinx.com/support/documentation/architecture-manuals/am009-versal-ai-engine.pdf

This patch series adds a Linux kernel driver to manage the Xilinx AI
engine array device and AI engine partitions (groups of AI engine tiles
dedicated to an application).

Izhar Ameer Shaikh (1):
  firmware: xilinx: Add IOCTL support for AIE ISR Clear

Nishad Saraf (2):
  misc: xilinx-ai-engine: Add support to request device management
services
  misc: xilinx-ai-engine: Add support for servicing error interrupts

Wendy Liang (6):
  dt-binding: soc: xilinx: ai-engine: Add AI engine binding
  misc: Add Xilinx AI engine device driver
  misc: xilinx-ai-engine: Implement AI engine cleanup sequence
  misc: xilinx-ai-engine: expose AI engine tile memories to userspace
  misc: xilinx-ai-engine: add setting shim dma bd operation
  misc: xilinx-ai-engine: add request and release tiles

 .../bindings/soc/xilinx/xlnx,ai-engine.yaml| 119 
 MAINTAINERS|   8 +
 drivers/firmware/xilinx/zynqmp.c   |  14 +
 drivers/misc/Kconfig   |  12 +
 drivers/misc/Makefile  |   1 +
 drivers/misc/xilinx-ai-engine/Makefile |  16 +
 drivers/misc/xilinx-ai-engine/ai-engine-aie.c  | 608 +++
 drivers/misc/xilinx-ai-engine/ai-engine-clock.c| 244 
 drivers/misc/xilinx-ai-engine/ai-engine-dev.c  | 492 +++
 drivers/misc/xilinx-ai-engine/ai-engine-dma.c  | 481 +++
 drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 519 
 .../misc/xilinx-ai-engine/ai-engine-interrupt.c| 661 +
 drivers/misc/xilinx-ai-engine/ai-engine-mem.c  | 274 +
 drivers/misc/xilinx-ai-engine/ai-engine-part.c | 635 
 drivers/misc/xilinx-ai-engine/ai-engine-res.c  | 219 +++
 drivers/misc/xilinx-ai-engine/ai-engine-reset.c| 159 +
 include/linux/firmware/xlnx-zynqmp.h   |   8 +
 include/uapi/linux/xlnx-ai-engine.h| 236 
 18 files changed, 4706 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
 create mode 100644 drivers/misc/xilinx-ai-engine/Makefile
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-aie.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-clock.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dev.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dma.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-internal.h
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-interrupt.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-mem.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-part.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-res.c
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-reset.c
 create mode 100644 include/uapi/linux/xlnx-ai-engine.h

-- 
2.7.4

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[PATCH 7/9] misc: xilinx-ai-engine: Add support to request device management services

From: Nishad Saraf 

Platform management services like device control, resets, power
management, etc. are provided by Platform, Loader and Manager(PLM)
through firmware driver APIs. For requesting some of these services,
this change reads AI Engine platform management node ID from DT node.
Some other features like clearing interrupts in the NoC interconnect
might only be valid for particular silicon revisions. For supporting
such silicon specific features, AI Engine driver will query and store
this information in device instance. While at it, this change makes
EEMI operations accessible to all the other source files in the
driver.

Signed-off-by: Nishad Saraf 
Signed-off-by: Wendy Liang 
---
 drivers/misc/xilinx-ai-engine/ai-engine-dev.c  | 25 +-
 drivers/misc/xilinx-ai-engine/ai-engine-internal.h |  6 ++
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-dev.c 
b/drivers/misc/xilinx-ai-engine/ai-engine-dev.c
index 7e69ff4..78eae90 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-dev.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-dev.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -25,7 +26,8 @@
 
 #include "ai-engine-internal.h"
 
-#define AIE_DEV_MAX(MINORMASK + 1)
+#define AIE_DEV_MAX(MINORMASK + 1)
+#define VERSAL_SILICON_REV_MASKGENMASK(31, 28)
 
 static dev_t aie_major;
 struct class *aie_class;
@@ -318,6 +320,7 @@ static int xilinx_ai_engine_probe(struct platform_device 
*pdev)
 {
struct aie_device *adev;
struct device *dev;
+   u32 idcode, version, pm_reg[2];
int ret;
 
adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL);
@@ -345,6 +348,26 @@ static int xilinx_ai_engine_probe(struct platform_device 
*pdev)
return ret;
}
 
+   /*
+* AI Engine platform management node ID is required for requesting
+* services from firmware driver.
+*/
+   ret = of_property_read_u32_array(pdev->dev.of_node, "power-domains",
+pm_reg, ARRAY_SIZE(pm_reg));
+   if (ret < 0) {
+   dev_err(&pdev->dev,
+   "Failed to read power management information\n");
+   return ret;
+   }
+   adev->pm_node_id = pm_reg[1];
+
+   ret = zynqmp_pm_get_chipid(&idcode, &version);
+   if (ret < 0) {
+   dev_err(&pdev->dev, "Failed to get chip ID\n");
+   return ret;
+   }
+   adev->version = FIELD_GET(VERSAL_SILICON_REV_MASK, idcode);
+
dev = &adev->dev;
device_initialize(dev);
dev->class = aie_class;
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h 
b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
index 131d22a..b21b7025 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
@@ -41,6 +41,10 @@
 #define AIE_REGS_ATTR_PERM_MASKGENMASK(15, \
AIE_REGS_ATTR_PERM_SHIFT)
 
+/* Silicon Engineering Sample(ES) revision ID */
+#define VERSAL_ES1_REV_ID  0x0
+#define VERSAL_ES2_REV_ID  0x1
+
 /**
  * struct aie_tile_regs - contiguous range of AI engine register
  *   within an AI engine tile
@@ -173,6 +177,7 @@ struct aie_resource {
  *   while columns are occupied by partitions.
  * @num_kernel_regs: number of kernel only registers range
  * @version: AI engine device version
+ * @pm_node_id: AI Engine platform management node ID
  */
 struct aie_device {
struct list_head partitions;
@@ -193,6 +198,7 @@ struct aie_device {
u32 row_shift;
u32 num_kernel_regs;
int version;
+   u32 pm_node_id;
 };
 
 /**
-- 
2.7.4

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[PATCH v5 7/7] ARM: dts: rockchip: enable hdmi_sound and i2s0 for rk3066a-mk808

Make some noise with mk808. Enable the hdmi_sound node and
add i2s0 as sound source for hdmi.

Signed-off-by: Johan Jonker 
---
 arch/arm/boot/dts/rk3066a-mk808.dts | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts 
b/arch/arm/boot/dts/rk3066a-mk808.dts
index eed9e60cf..5fe74c097 100644
--- a/arch/arm/boot/dts/rk3066a-mk808.dts
+++ b/arch/arm/boot/dts/rk3066a-mk808.dts
@@ -116,6 +116,14 @@
};
 };
 
+&hdmi_sound {
+   status = "okay";
+};
+
+&i2s0 {
+   status = "okay";
+};
+
 &mmc0 {
bus-width = <4>;
cap-mmc-highspeed;
-- 
2.11.0

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[PATCH v2 4/9] misc: xilinx-ai-engine: expose AI engine tile memories to userspace

There is no concern to have userspace to directly access AI engine
program and data memories. It will be much faster to directly copy
data to and from these memories from userspace.

We choose to use DMA buf for the data and program memory because of the
DMA buf features. DMA buf can share the DMA memory between applications
and different devices, which can benefit on how to share data with AI
engine device in future.

There is one DMA buf per type of memory in an AI engine partition. e.g.
There is one DMA buf for all the tile core program memories in an AI
engine partition. There is another DMA buf for all the tile data
memories in an AI engine partition.

Signed-off-by: Wendy Liang 
Reviewed-by: Hyun Kwon 
---
 drivers/misc/xilinx-ai-engine/Makefile |   1 +
 drivers/misc/xilinx-ai-engine/ai-engine-aie.c  |  36 +++
 drivers/misc/xilinx-ai-engine/ai-engine-internal.h |  30 +++
 drivers/misc/xilinx-ai-engine/ai-engine-mem.c  | 274 +
 drivers/misc/xilinx-ai-engine/ai-engine-part.c |  47 
 drivers/misc/xilinx-ai-engine/ai-engine-reset.c|  38 +++
 include/uapi/linux/xlnx-ai-engine.h|  49 
 7 files changed, 475 insertions(+)
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-mem.c

diff --git a/drivers/misc/xilinx-ai-engine/Makefile 
b/drivers/misc/xilinx-ai-engine/Makefile
index 39bec61..2dbed42 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_XILINX_AIE)+= xilinx-aie.o
 
 xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
   ai-engine-dev.o \
+  ai-engine-mem.o \
   ai-engine-part.o \
   ai-engine-res.o \
   ai-engine-reset.o
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c 
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index 36127f0..7fce2f00 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -12,10 +12,14 @@
 
 #include "ai-engine-internal.h"
 
+#define KBYTES(n)  ((n) * 1024)
+
 #define AIE_ARRAY_SHIFT30U
 #define AIE_COL_SHIFT  23U
 #define AIE_ROW_SHIFT  18U
 
+#define NUM_MEMS_PER_TILE  2U
+
 /*
  * Registers offsets
  */
@@ -114,6 +118,37 @@ static u32 aie_get_tile_type(struct aie_location *loc)
return AIE_TILE_TYPE_SHIMNOC;
 }
 
+static unsigned int aie_get_mem_info(struct aie_range *range,
+struct aie_part_mem *pmem)
+{
+   unsigned int i;
+
+   if (range->start.row + range->size.row <= 1) {
+   /* SHIM row only, no memories in this range */
+   return 0;
+   }
+   if (!pmem)
+   return NUM_MEMS_PER_TILE;
+
+   for (i = 0; i < NUM_MEMS_PER_TILE; i++) {
+   struct aie_mem *mem = &pmem[i].mem;
+
+   memcpy(&mem->range, range, sizeof(*range));
+   if (!mem->range.start.row) {
+   mem->range.start.row = 1;
+   mem->range.size.row--;
+   }
+   }
+   /* Setup tile data memory information */
+   pmem[0].mem.offset = 0;
+   pmem[0].mem.size = KBYTES(32);
+   /* Setup program memory information */
+   pmem[1].mem.offset = 0x2;
+   pmem[1].mem.size = KBYTES(16);
+
+   return NUM_MEMS_PER_TILE;
+}
+
 /**
  * aie_set_shim_reset() - Set AI engine SHIM reset
  * @adev: AI engine device
@@ -170,6 +205,7 @@ static int aie_reset_shim(struct aie_device *adev, struct 
aie_range *range)
 
 static const struct aie_tile_operations aie_ops = {
.get_tile_type = aie_get_tile_type,
+   .get_mem_info = aie_get_mem_info,
.reset_shim = aie_reset_shim,
 };
 
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h 
b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
index 2acd34f..e84610b 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
@@ -12,6 +12,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -67,8 +69,30 @@ struct aie_device;
 struct aie_partition;
 
 /**
+ * struct aie_part_mem - AI engine partition memory information structure
+ * @apart: AI engine partition
+ * @dbuf: dmabuf pointer associated with the memory
+ * @mem: memory information of a type of memory
+ * @size: size of the total memories in the partition
+ *
+ * This structure is to keep the information of a type of memory in a
+ * partition. The memory information will be stored in @mem property.
+ * The following information will be keep:
+ *  * memory start address offset within a tile
+ *  * memory size
+ *  * what tiles contain this type of memory
+ */
+struct aie_part_mem {
+   struct aie_partition *apart;
+   struct dma_buf *dbuf;
+   struct aie_m

[PATCH v2] drm: Pass the full state to connectors atomic functions

The current atomic helpers have either their object state being passed as
an argument or the full atomic state.

The former is the pattern that was done at first, before switching to the
latter for new hooks or when it was needed.

Now that the CRTCs have been converted, let's move forward with the
connectors to provide a consistent interface.

The conversion was done using the coccinelle script below, and built tested
on all the drivers.

@@
identifier connector, connector_state;
@@

 struct drm_connector_helper_funcs {
...
struct drm_encoder* (*atomic_best_encoder)(struct drm_connector 
*connector,
-  struct drm_connector_state 
*connector_state);
+  struct drm_atomic_state 
*state);
...
}

@@
identifier connector, connector_state;
@@

 struct drm_connector_helper_funcs {
...
void (*atomic_commit)(struct drm_connector *connector,
- struct drm_connector_state *connector_state);
+ struct drm_atomic_state *state);
...
}

@@
struct drm_connector_helper_funcs *FUNCS;
identifier state;
identifier connector, connector_state;
identifier f;
@@

 f(..., struct drm_atomic_state *state, ...)
 {
<+...
-   FUNCS->atomic_commit(connector, connector_state);
+   FUNCS->atomic_commit(connector, state);
...+>
 }

@@
struct drm_connector_helper_funcs *FUNCS;
identifier state;
identifier connector, connector_state;
identifier var, f;
@@

 f(struct drm_atomic_state *state, ...)
 {
<+...
-   var = FUNCS->atomic_best_encoder(connector, connector_state);
+   var = FUNCS->atomic_best_encoder(connector, state);
...+>
 }

@ connector_atomic_func @
identifier helpers;
identifier func;
@@

(
static struct drm_connector_helper_funcs helpers = {
...,
.atomic_best_encoder = func,
...,
};
|
static struct drm_connector_helper_funcs helpers = {
...,
.atomic_commit = func,
...,
};
)

@@
identifier connector_atomic_func.func;
identifier connector;
symbol state;
@@

 func(struct drm_connector *connector,
-  struct drm_connector_state *state
+  struct drm_connector_state *connector_state
  )
 {
...
-   state
+   connector_state
...
 }

@ ignores_state @
identifier connector_atomic_func.func;
identifier connector, connector_state;
@@

 func(struct drm_connector *connector,
  struct drm_connector_state *connector_state)
{
... when != connector_state
}

@ adds_state depends on connector_atomic_func && !ignores_state @
identifier connector_atomic_func.func;
identifier connector, connector_state;
@@

 func(struct drm_connector *connector, struct drm_connector_state 
*connector_state)
 {
+   struct drm_connector_state *connector_state = 
drm_atomic_get_new_connector_state(state, connector);
...
 }

@ depends on connector_atomic_func @
identifier connector_atomic_func.func;
identifier connector_state;
identifier connector;
@@

 func(struct drm_connector *connector,
- struct drm_connector_state *connector_state
+ struct drm_atomic_state *state
   )
 { ... }

@ include depends on adds_state @
@@

 #include 

@ no_include depends on !include && adds_state @
@@

+ #include 
  #include 

Cc: Leo Li 
Cc: Alex Deucher 
Cc: "Christian König" 
Cc: Jani Nikula 
Cc: Joonas Lahtinen 
Cc: Rodrigo Vivi 
Cc: Ben Skeggs 
Cc: Rodrigo Siqueira 
Cc: Melissa Wen 
Cc: Haneen Mohammed 
Acked-by: Thomas Zimmermann 
Acked-by: Harry Wentland 
Reviewed-by: Rodrigo Siqueira 
Signed-off-by: Maxime Ripard 

---

Changes from v1:
  - Added missing coccinelle script
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c |  5 -
 drivers/gpu/drm/drm_atomic_helper.c |  8 
 drivers/gpu/drm/i915/display/intel_dp_mst.c |  7 +--
 drivers/gpu/drm/nouveau/dispnv50/disp.c |  5 -
 drivers/gpu/drm/vc4/vc4_txp.c   |  4 +++-
 drivers/gpu/drm/vkms/vkms_writeback.c   |  7 +--
 include/drm/drm_modeset_helper_vtables.h| 13 ++---
 7 files changed, 31 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 6f975c16779d..8ab0b9060d2b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -24,6 +24,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -252,8 +253,10 @@ static int dm_dp_mst_get_modes(struct drm_connector 
*connector)
 
 static struct drm_encoder *
 dm_mst_atomic_best_encoder(struct drm_connector *connector,
-  struct drm_connector_state *connector_state)
+  struct drm_atomic_state *state)
 {
+   struct drm_connector_state *connector_state =

[PATCH v2 4/5] thermal: devfreq_cooling: remove old power model and use EM

Remove old power model and use new Energy Model to calculate the power
budget. It drops static + dynamic power calculations and power table
in order to use Energy Model performance domain data. This model
should be easy to use and could find more users. It is also less
complicated to setup the needed structures.

Signed-off-by: Lukasz Luba 
---
 drivers/thermal/devfreq_cooling.c | 302 ++
 include/linux/devfreq_cooling.h   |  17 --
 2 files changed, 96 insertions(+), 223 deletions(-)

diff --git a/drivers/thermal/devfreq_cooling.c 
b/drivers/thermal/devfreq_cooling.c
index b354271742c5..28754ad46b96 100644
--- a/drivers/thermal/devfreq_cooling.c
+++ b/drivers/thermal/devfreq_cooling.c
@@ -33,20 +33,17 @@ static DEFINE_IDA(devfreq_ida);
  * @cdev:  Pointer to associated thermal cooling device.
  * @devfreq:   Pointer to associated devfreq device.
  * @cooling_state: Current cooling state.
- * @power_table:   Pointer to table with maximum power draw for each
- * cooling state. State is the index into the table, and
- * the power is in mW.
  * @freq_table:Pointer to a table with the frequencies sorted in 
descending
  * order.  You can index the table by cooling device state
- * @freq_table_size:   Size of the @freq_table and @power_table
- * @power_ops: Pointer to devfreq_cooling_power, used to generate the
- * @power_table.
+ * @max_state: It is the last index, that is, one less than the number of the
+ * OPPs
+ * @power_ops: Pointer to devfreq_cooling_power, a more precised model.
  * @res_util:  Resource utilization scaling factor for the power.
  * It is multiplied by 100 to minimize the error. It is used
  * for estimation of the power budget instead of using
- * 'utilization' (which is 'busy_time / 'total_time').
- * The 'res_util' range is from 100 to (power_table[state] * 100)
- * for the corresponding 'state'.
+ * 'utilization' (which is 'busy_time' / 'total_time').
+ * The 'res_util' range is from 100 to power * 100 for the
+ * corresponding 'state'.
  * @capped_state:  index to cooling state with in dynamic power budget
  * @req_max_freq:  PM QoS request for limiting the maximum frequency
  * of the devfreq device.
@@ -58,9 +55,8 @@ struct devfreq_cooling_device {
struct thermal_cooling_device *cdev;
struct devfreq *devfreq;
unsigned long cooling_state;
-   u32 *power_table;
u32 *freq_table;
-   size_t freq_table_size;
+   size_t max_state;
struct devfreq_cooling_power *power_ops;
u32 res_util;
int capped_state;
@@ -74,7 +70,7 @@ static int devfreq_cooling_get_max_state(struct 
thermal_cooling_device *cdev,
 {
struct devfreq_cooling_device *dfc = cdev->devdata;
 
-   *state = dfc->freq_table_size - 1;
+   *state = dfc->max_state;
 
return 0;
 }
@@ -96,16 +92,22 @@ static int devfreq_cooling_set_cur_state(struct 
thermal_cooling_device *cdev,
struct devfreq *df = dfc->devfreq;
struct device *dev = df->dev.parent;
unsigned long freq;
+   int perf_idx;
 
if (state == dfc->cooling_state)
return 0;
 
dev_dbg(dev, "Setting cooling state %lu\n", state);
 
-   if (state >= dfc->freq_table_size)
+   if (state > dfc->max_state)
return -EINVAL;
 
-   freq = dfc->freq_table[state];
+   if (dfc->em) {
+   perf_idx = dfc->max_state - state;
+   freq = dfc->em->table[perf_idx].frequency * 1000;
+   } else {
+   freq = dfc->freq_table[state];
+   }
 
dev_pm_qos_update_request(&dfc->req_max_freq,
  DIV_ROUND_UP(freq, HZ_PER_KHZ));
@@ -116,24 +118,24 @@ static int devfreq_cooling_set_cur_state(struct 
thermal_cooling_device *cdev,
 }
 
 /**
- * freq_get_state() - get the cooling state corresponding to a frequency
+ * get_perf_idx() - get the performance index corresponding to a frequency
  * @dfc:   Pointer to devfreq cooling device
- * @freq:  frequency in Hz
+ * @freq:  frequency in kHz
  *
- * Return: the cooling state associated with the @freq, or
- * THERMAL_CSTATE_INVALID if it wasn't found.
+ * Return: the performance index associated with the @freq, or
+ * -EINVAL if it wasn't found.
  */
-static unsigned long
-freq_get_state(struct devfreq_cooling_device *dfc, unsigned long freq)
+static int get_perf_idx(struct devfreq_cooling_device *dfc, unsigned long freq)
 {
+   struct em_perf_domain *em = dfc->em;
int i;
 
-   for (i = 0; i < dfc->freq_table_size; i++) {
-   if (dfc->freq_table[i] == freq)
+   for (i = 0; i < em->nr_perf_states; i++) {
+   if (em->table[i].frequency == freq)
return i;
}
 
-   return THERMA

Re: [PATCH RESEND v3 1/6] drm/of: Change the prototype of drm_of_lvds_get_dual_link_pixel_order

Hi Laurent,

On Mon, Oct 12, 2020 at 02:00:30AM +0300, Laurent Pinchart wrote:
> > -static int drm_of_lvds_get_remote_pixels_type(
> > -   const struct device_node *port_node)
> > +static int drm_of_lvds_get_remote_pixels_type(const struct device_node 
> > *endpoint)
> >  {
> > -   struct device_node *endpoint = NULL;
> > -   int pixels_type = -EPIPE;
> > +   struct device_node *remote_port;
> > +   int pixels_type;
> >  
> > -   for_each_child_of_node(port_node, endpoint) {
> > -   struct device_node *remote_port;
> > -   int current_pt;
> > -
> > -   if (!of_node_name_eq(endpoint, "endpoint"))
> > -   continue;
> > -
> > -   remote_port = of_graph_get_remote_port(endpoint);
> > -   if (!remote_port) {
> > -   of_node_put(remote_port);
> > -   return -EPIPE;
> > -   }
> > -
> > -   current_pt = drm_of_lvds_get_port_pixels_type(remote_port);
> > +   remote_port = of_graph_get_remote_port(endpoint);
> > +   if (!remote_port) {
> > of_node_put(remote_port);
> 
> You can drop this line.
> 
> > -   if (pixels_type < 0)
> > -   pixels_type = current_pt;
> > -
> > -   /*
> > -* Sanity check, ensure that all remote endpoints have the same
> > -* pixel type. We may lift this restriction later if we need to
> > -* support multiple sinks with different dual-link
> > -* configurations by passing the endpoints explicitly to
> > -* drm_of_lvds_get_dual_link_pixel_order().
> > -*/
> 
> Shouldn't we keep this check when endpoint_id is -1 in
> drm_of_lvds_get_dual_link_pixel_order() ?

I tried to do that, and I'm not quite really sure how to go around it.

This scans all the endpoints in a given port.

However, now that we have the device, port id and endpoint id, we need
to use of_graph_get_port_by_id to get the port matching the device and
port id, and iterate over all its endpoint as done here.

The trouble is that of_graph_get_port_by_id expects a !const
device_node, yet drm_of_lvds_get_dual_link_pixel_order (and seems to be
doing so rightfully), so that creates a warning because we drop the
const there.

Changing the prototype to passing only the port device_node doesn't
really work either, since it would be const, and we would need to call
of_graph_get_endpoint_by_regs (so having the parent device_node, through
of_graph_get_port_parent) and of_graph_get_port_parent takes a !const
port device_node.

I guess we could drop const entirely from our function, but that doesn't
look right either..

Maxime

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[PATCH v2 9/9] misc: xilinx-ai-engine: Add support for servicing error interrupts

From: Nishad Saraf 

AI engine errors events can be routed to generate interrupt. The
errors events routing will be done during AI engine configuration.
At runtime, Linux kernel AI engine driver monitors the interrupt and
backtracks errors events.
As error events from 400 AIE tiles and 50 shim tiles are channeled on
a single interrupt line, backtracking the source the interrupt to an
AIE module is required. To keep the top-half interrupt short,
backtracking is deferred to bottom half by scheduling a task in shared
workqueue.

Signed-off-by: Nishad Saraf 
Signed-off-by: Wendy Liang 
---
 drivers/misc/xilinx-ai-engine/Makefile |   1 +
 drivers/misc/xilinx-ai-engine/ai-engine-aie.c  | 121 
 drivers/misc/xilinx-ai-engine/ai-engine-dev.c  |  14 +
 drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 144 +
 .../misc/xilinx-ai-engine/ai-engine-interrupt.c| 659 +
 drivers/misc/xilinx-ai-engine/ai-engine-part.c |  44 ++
 drivers/misc/xilinx-ai-engine/ai-engine-res.c  |  54 ++
 7 files changed, 1037 insertions(+)
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-interrupt.c

diff --git a/drivers/misc/xilinx-ai-engine/Makefile 
b/drivers/misc/xilinx-ai-engine/Makefile
index 2e67b25..9607ecb 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -9,6 +9,7 @@ xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
   ai-engine-clock.o \
   ai-engine-dev.o \
   ai-engine-dma.o \
+  ai-engine-interrupt.o \
   ai-engine-mem.o \
   ai-engine-part.o \
   ai-engine-res.o \
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c 
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index ff721b3..af0f997 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -33,7 +33,10 @@
 #define AIE_SHIMPL_CLKCNTR_REGOFF  0x00036040U
 #define AIE_SHIMPL_COLRESET_REGOFF 0x00036048U
 #define AIE_SHIMPL_RESET_REGOFF0x0003604cU
+#define AIE_SHIMPL_GROUP_ERROR_REGOFF  0x0003450cU
 #define AIE_TILE_CORE_CLKCNTR_REGOFF   0x00036040U
+#define AIE_TILE_CORE_GROUP_ERROR_REGOFF   0x00034510U
+#define AIE_TILE_MEM_GROUP_ERROR_REGOFF0x00014514U
 
 /*
  * Register masks
@@ -93,11 +96,27 @@ static const struct aie_tile_regs aie_kernel_regs[] = {
 .soff = AIE_SHIMPL_CLKCNTR_REGOFF,
 .eoff = AIE_SHIMPL_CLKCNTR_REGOFF,
},
+   /* SHIM group error enable */
+   {.attribute = (AIE_TILE_TYPE_SHIMPL | AIE_TILE_TYPE_SHIMNOC) <<
+ AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_SHIMPL_GROUP_ERROR_REGOFF,
+.eoff = AIE_SHIMPL_GROUP_ERROR_REGOFF,
+   },
/* Tile clock control */
{.attribute = AIE_TILE_TYPE_TILE << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
 .soff = AIE_TILE_CORE_CLKCNTR_REGOFF,
 .eoff = AIE_TILE_CORE_CLKCNTR_REGOFF,
},
+   /* Tile group error for core module */
+   {.attribute = AIE_TILE_TYPE_TILE << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_TILE_CORE_GROUP_ERROR_REGOFF,
+.eoff = AIE_TILE_CORE_GROUP_ERROR_REGOFF,
+   },
+   /* Tile group error for memory module */
+   {.attribute = AIE_TILE_TYPE_TILE << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_TILE_MEM_GROUP_ERROR_REGOFF,
+.eoff = AIE_TILE_MEM_GROUP_ERROR_REGOFF,
+   },
 };
 
 static const struct aie_single_reg_field aie_col_rst = {
@@ -128,6 +147,103 @@ static const struct aie_dma_attr aie_shimdma = {
.bd_len = 0x14U,
 };
 
+static const struct aie_event_attr aie_pl_event = {
+   .bc_event = {
+   .mask = GENMASK(6, 0),
+   .regoff = 0x0U,
+   },
+   .group_error = {
+   .mask = GENMASK(10, 0),
+   .regoff = 0xcU,
+   },
+   .bc_regoff = 0x34010U,
+   .status_regoff = 0x34200U,
+   .group_regoff = 0x34500U,
+   .base_error_event = 62U,
+   .num_broadcasts = 16U,
+   .base_bc_event = 107U,
+   .num_events = 128U,
+};
+
+static const struct aie_event_attr aie_mem_event = {
+   .bc_event = {
+   .mask = GENMASK(6, 0),
+   .regoff = 0x0U,
+   },
+   .group_error = {
+   .mask = GENMASK(13, 0),
+   .regoff = 0x14U,
+   },
+   .bc_regoff = 0x14010U,
+   .status_regoff = 0x14200U,
+   .group_regoff = 0x14500U,
+   .base_error_event = 87U,
+   .num_broadcasts = 16U,
+   .base_bc_event = 107U,
+   .num_events = 128U,
+};
+
+static const struct aie_event_attr aie_core_event = {
+   .bc_event = {
+   .mask = GENMASK(6, 0),
+   .regoff = 0x0U,
+   },
+   .group_erro

[PATCH v2 8/9] firmware: xilinx: Add IOCTL support for AIE ISR Clear

From: Izhar Ameer Shaikh 

Latching of AIE NPI Interrupts is present in Versal ES1 Silicon Rev,
however it has been removed from ES2 rev.
As a result on ES1, in order to use the interrupt, a client needs to
request PMC to clear/ack the interrupt.

Provide an EEMI IOCTL to serve the same purpose. Note that, this will
only be applicable for ES1 rev. For ES2 and other non-silicon platforms,
this call will essentially be a NOP in the firmware.

Signed-off-by: Izhar Ameer Shaikh 
Signed-off-by: Wendy Liang 
---
 drivers/firmware/xilinx/zynqmp.c | 14 ++
 include/linux/firmware/xlnx-zynqmp.h |  8 
 2 files changed, 22 insertions(+)

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index efb8a66..7a0c6a3 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -702,6 +702,20 @@ int zynqmp_pm_set_boot_health_status(u32 value)
 }
 
 /**
+ * zynqmp_pm_clear_aie_npi_isr - Clear AI engine NPI interrupt status register
+ * @node:  AI engine node id
+ * @irq_mask:  Mask of AI engine NPI interrupt bit to clear
+ *
+ * Return: Returns status, either success or error+reason
+ */
+int zynqmp_pm_clear_aie_npi_isr(u32 node, u32 irq_mask)
+{
+   return zynqmp_pm_invoke_fn(PM_IOCTL, node, IOCTL_AIE_ISR_CLEAR,
+  irq_mask, 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_clear_aie_npi_isr);
+
+/**
  * zynqmp_pm_reset_assert - Request setting of reset (1 - assert, 0 - release)
  * @reset: Reset to be configured
  * @assert_flag:   Flag stating should reset be asserted (1) or
diff --git a/include/linux/firmware/xlnx-zynqmp.h 
b/include/linux/firmware/xlnx-zynqmp.h
index 7b6f9fc..cdc0867 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -120,6 +120,8 @@ enum pm_ioctl_id {
IOCTL_READ_PGGS = 15,
/* Set healthy bit value */
IOCTL_SET_BOOT_HEALTH_STATUS = 17,
+   /* AI engine NPI ISR clear */
+   IOCTL_AIE_ISR_CLEAR = 24,
 };
 
 enum pm_query_id {
@@ -361,6 +363,7 @@ int zynqmp_pm_write_pggs(u32 index, u32 value);
 int zynqmp_pm_read_pggs(u32 index, u32 *value);
 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
 int zynqmp_pm_set_boot_health_status(u32 value);
+int zynqmp_pm_clear_aie_npi_isr(u32 node, u32 irq_mask);
 #else
 static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
 {
@@ -511,6 +514,11 @@ static inline int zynqmp_pm_set_boot_health_status(u32 
value)
 {
return -ENODEV;
 }
+
+static inline int zynqmp_pm_clear_aie_npi_isr(u32 node, u32 irq_mask)
+{
+   return -ENODEV;
+}
 #endif
 
 #endif /* __FIRMWARE_ZYNQMP_H__ */
-- 
2.7.4

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[PATCH v2] drm/vmwgfx: use min_t to replace min

Use min_t to replace min, min_t is a bit fast because min use
twice typeof.
This patch also fix check_patch.pl warning:
WARNING: min() should probably be min_t(unsigned long, num_pages,
VMW_PPN_PER_REMAP)
+unsigned long nr = min(num_pages, (unsigned long)
VMW_PPN_PER_REMAP);

Signed-off-by: Bernard Zhao 
Reported-by: kernel test robot 
---
Changes since V1:
*fix compile error reported by kernel test robot

Link for V1:
*https://lore.kernel.org/patchwork/patch/1340996/
---
 drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c
index 83c0d5a3e4fd..525d5e1227e8 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c
@@ -72,7 +72,7 @@ static int vmw_gmr2_bind(struct vmw_private *dev_priv,
SVGA_REMAP_GMR2_PPN64 : SVGA_REMAP_GMR2_PPN32;
 
while (num_pages > 0) {
-   unsigned long nr = min(num_pages, (unsigned 
long)VMW_PPN_PER_REMAP);
+   unsigned long nr = min_t(unsigned long, num_pages, 
VMW_PPN_PER_REMAP);
 
remap_cmd.offsetPages = remap_pos;
remap_cmd.numPages = nr;
-- 
2.29.0

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[PATCH v2 7/9] misc: xilinx-ai-engine: Add support to request device management services

From: Nishad Saraf 

Platform management services like device control, resets, power
management, etc. are provided by Platform, Loader and Manager(PLM)
through firmware driver APIs. For requesting some of these services,
this change reads AI Engine platform management node ID from DT node.
Some other features like clearing interrupts in the NoC interconnect
might only be valid for particular silicon revisions. For supporting
such silicon specific features, AI Engine driver will query and store
this information in device instance. While at it, this change makes
EEMI operations accessible to all the other source files in the
driver.

Signed-off-by: Nishad Saraf 
Signed-off-by: Wendy Liang 
---
 drivers/misc/xilinx-ai-engine/ai-engine-dev.c  | 25 +-
 drivers/misc/xilinx-ai-engine/ai-engine-internal.h |  6 ++
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-dev.c 
b/drivers/misc/xilinx-ai-engine/ai-engine-dev.c
index 7e69ff4..78eae90 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-dev.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-dev.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -25,7 +26,8 @@
 
 #include "ai-engine-internal.h"
 
-#define AIE_DEV_MAX(MINORMASK + 1)
+#define AIE_DEV_MAX(MINORMASK + 1)
+#define VERSAL_SILICON_REV_MASKGENMASK(31, 28)
 
 static dev_t aie_major;
 struct class *aie_class;
@@ -318,6 +320,7 @@ static int xilinx_ai_engine_probe(struct platform_device 
*pdev)
 {
struct aie_device *adev;
struct device *dev;
+   u32 idcode, version, pm_reg[2];
int ret;
 
adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL);
@@ -345,6 +348,26 @@ static int xilinx_ai_engine_probe(struct platform_device 
*pdev)
return ret;
}
 
+   /*
+* AI Engine platform management node ID is required for requesting
+* services from firmware driver.
+*/
+   ret = of_property_read_u32_array(pdev->dev.of_node, "power-domains",
+pm_reg, ARRAY_SIZE(pm_reg));
+   if (ret < 0) {
+   dev_err(&pdev->dev,
+   "Failed to read power management information\n");
+   return ret;
+   }
+   adev->pm_node_id = pm_reg[1];
+
+   ret = zynqmp_pm_get_chipid(&idcode, &version);
+   if (ret < 0) {
+   dev_err(&pdev->dev, "Failed to get chip ID\n");
+   return ret;
+   }
+   adev->version = FIELD_GET(VERSAL_SILICON_REV_MASK, idcode);
+
dev = &adev->dev;
device_initialize(dev);
dev->class = aie_class;
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h 
b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
index 131d22a..b21b7025 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
@@ -41,6 +41,10 @@
 #define AIE_REGS_ATTR_PERM_MASKGENMASK(15, \
AIE_REGS_ATTR_PERM_SHIFT)
 
+/* Silicon Engineering Sample(ES) revision ID */
+#define VERSAL_ES1_REV_ID  0x0
+#define VERSAL_ES2_REV_ID  0x1
+
 /**
  * struct aie_tile_regs - contiguous range of AI engine register
  *   within an AI engine tile
@@ -173,6 +177,7 @@ struct aie_resource {
  *   while columns are occupied by partitions.
  * @num_kernel_regs: number of kernel only registers range
  * @version: AI engine device version
+ * @pm_node_id: AI Engine platform management node ID
  */
 struct aie_device {
struct list_head partitions;
@@ -193,6 +198,7 @@ struct aie_device {
u32 row_shift;
u32 num_kernel_regs;
int version;
+   u32 pm_node_id;
 };
 
 /**
-- 
2.7.4

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Re: [PATCH RESEND 1/2] dma-fence: allow signaling drivers to set fence timestamp

2020-11-19 Thread veeras


On 2020-11-12 10:27, Veera Sundaram Sankaran wrote:

Some drivers have hardware capability to get the precise timestamp of
certain events based on which the fences are triggered. This allows it
to set accurate timestamp factoring out any software and IRQ latencies.
Move the timestamp parameter out of union in dma_fence struct to allow
signaling drivers to set it. If the parameter is not set, ktime_get is
used to set the current time to fence timestamp during 
dma_fence_signal.




@Sumit Semwal / @Gustavo Padovan,
Can you please help in reviewing this change as it falls in dma-fence 
files.

Thanks,
Veera


Signed-off-by: Veera Sundaram Sankaran 
---
 drivers/dma-buf/dma-fence.c | 18 ++
 include/linux/dma-fence.h   | 15 +++
 2 files changed, 13 insertions(+), 20 deletions(-)

diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
index 43624b4..7cef49a 100644
--- a/drivers/dma-buf/dma-fence.c
+++ b/drivers/dma-buf/dma-fence.c
@@ -4,6 +4,7 @@
  *
  * Copyright (C) 2012 Canonical Ltd
  * Copyright (C) 2012 Texas Instruments
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
  *
  * Authors:
  * Rob Clark 
@@ -329,7 +330,6 @@ void __dma_fence_might_wait(void)
 int dma_fence_signal_locked(struct dma_fence *fence)
 {
struct dma_fence_cb *cur, *tmp;
-   struct list_head cb_list;

lockdep_assert_held(fence->lock);

@@ -337,16 +337,18 @@ int dma_fence_signal_locked(struct dma_fence 
*fence)

  &fence->flags)))
return -EINVAL;

-   /* Stash the cb_list before replacing it with the timestamp */
-   list_replace(&fence->cb_list, &cb_list);
-
-   fence->timestamp = ktime_get();
+   /* set current time, if not set by signaling driver */
+   if (!fence->timestamp)
+   fence->timestamp = ktime_get();
set_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags);
trace_dma_fence_signaled(fence);

-   list_for_each_entry_safe(cur, tmp, &cb_list, node) {
-   INIT_LIST_HEAD(&cur->node);
-   cur->func(fence, cur);
+   if (!list_empty(&fence->cb_list)) {
+   list_for_each_entry_safe(cur, tmp, &fence->cb_list, node) {
+   INIT_LIST_HEAD(&cur->node);
+   cur->func(fence, cur);
+   }
+   INIT_LIST_HEAD(&fence->cb_list);
}

return 0;
diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h
index 09e23ad..a9eebaf 100644
--- a/include/linux/dma-fence.h
+++ b/include/linux/dma-fence.h
@@ -4,6 +4,7 @@
  *
  * Copyright (C) 2012 Canonical Ltd
  * Copyright (C) 2012 Texas Instruments
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
  *
  * Authors:
  * Rob Clark 
@@ -70,26 +71,16 @@ struct dma_fence {
 * release the fence it is unused. No one should be adding to the
 * cb_list that they don't themselves hold a reference for.
 *
-* The lifetime of the timestamp is similarly tied to both the
-* rcu freelist and the cb_list. The timestamp is only set upon
-* signaling while simultaneously notifying the cb_list. Ergo, we
-* only use either the cb_list of timestamp. Upon destruction,
-* neither are accessible, and so we can use the rcu. This means
-* that the cb_list is *only* valid until the signal bit is set,
-* and to read either you *must* hold a reference to the fence,
-* and not just the rcu_read_lock.
-*
 * Listed in chronological order.
 */
union {
struct list_head cb_list;
-   /* @cb_list replaced by @timestamp on dma_fence_signal() */
-   ktime_t timestamp;
-   /* @timestamp replaced by @rcu on dma_fence_release() */
+   /* @cb_list replaced by @rcu on dma_fence_release() */
struct rcu_head rcu;
};
u64 context;
u64 seqno;
+   ktime_t timestamp;
unsigned long flags;
struct kref refcount;
int error;

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[PATCH 1/9] dt-binding: soc: xilinx: ai-engine: Add AI engine binding

Xilinx AI engine array can be partitioned statically for different
applications. In the device tree, there will be device node for the AI
engine device, and device nodes for the statically configured AI engine
partitions. Each of the statically configured partition has a partition
ID in the system.

Signed-off-by: Wendy Liang 
---
 .../bindings/soc/xilinx/xlnx,ai-engine.yaml| 119 +
 1 file changed, 119 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml

diff --git a/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml 
b/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
new file mode 100644
index 000..67e64f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/xilinx/xlnx,ai-engine.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx AI Engine
+
+maintainers:
+ - Wendy Liang 
+
+description: |+
+  The Xilinx AI Engine is a tile processor with many cores (up to 400) that
+  can run in parallel. The data routing between cores is configured through
+  internal switches, and shim tiles interface with external interconnect, such
+  as memory or PL.
+
+properties:
+  compatible:
+const: xlnx,ai-engine-v1.0
+
+  reg:
+description: |
+  Physical base address and length of the device registers.
+  The AI engine address space assigned to Linux is defined by Xilinx
+  platform design tool.
+
+  '#address-cells':
+enum: [2]
+description: |
+  size of cell to describe AI engine range of tiles address.
+  It is the location of the starting tile of the range.
+  As the AI engine tiles are 2D array, the location of a tile
+  is presented as (column, row), the address cell is 2.
+
+  '#size-cells':
+enum: [2]
+description: |
+  size of cell to describe AI engine range of tiles size.
+  As the AI engine tiles are 2D array, the size cell is 2.
+
+  interrupts:
+maxItems: 3
+
+  interrupt-names:
+description: |
+  Should be "interrupt1", "interrupt2" or "interrupt3".
+
+required:
+  - compatible
+  - reg
+  - '#address-cells'
+  - '#size-cells'
+  - power-domains
+  - interrupt-parent
+  - interrupts
+  - interrupt-names
+
+patternProperties:
+  "^partition[0-9]@[0-9]+$":
+type: object
+description: |
+  AI engine partition which is a group of column based tiles of the AI
+  engine device. Each AI engine partition is isolated from the other
+  AI engine partitions. An AI engine partition is defined by Xilinx
+  platform design tools. Each partition has a SHIM row and core tiles rows.
+  A SHIM row contains SHIM tiles which are the interface to external
+  components. AXI master can access AI engine registers, push data to and
+  fetch data from AI engine through the SHIM tiles. Core tiles are the
+  compute tiles.
+
+properties:
+  reg:
+description: |
+  It describes the group of tiles of the AI engine partition. It needs
+  to include the SHIM row. The format is defined by the parent AI 
engine
+  device node's '#address-cells' and '#size-cells' properties. e.g. a 
v1
+  AI engine device has 2D tiles array, the first row is SHIM row. A
+  partition which has 50 columns and 8 rows of core tiles and 1 row of
+  SHIM tiles will be presented as <0 0 50 9>.
+
+  label:
+maxItems: 1
+
+  xlnx,partition-id:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: |
+  AI engine partition ID, which is defined by Xilinx platform design
+  tool to identify the AI engine partition in the system.
+
+required:
+  - reg
+  - xlnx,partition-id
+
+examples:
+  - |
+bus {
+  #address-cells = <2>;
+  #size-cells = <2>;
+
+  ai_engine: ai-engine@200 {
+compatible = "xlnx,ai-engine-v1.0";
+reg = <0x200 0x0 0x1 0x0>;
+#address-cells = <2>;
+#size-cells = <2>;
+power-domains = <&versal_firmware 0x18224072>;
+interrupt-parent = <&gic>;
+interrupts = <0x0 0x94 0x4>,
+ <0x0 0x95 0x4>,
+ <0x0 0x96 0x4>;
+interrupt-names = "interrupt1", "interrupt2", "interrupt3";
+
+aie_partition0: aie-partition@0 {
+/* 50 columns and 8 core tile rows + 1 SHIM row */
+reg = <0 0 50 9>;
+xlnx,partition-id = <1>;
+};
+  };
+};
-- 
2.7.4

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[PATCH v3 11/11] MAINTAINERS: update MediaTek PHY/USB entry

Due to the phy/usb bindings are converted into YAML schema and
also renamed, update entries.
Meanwhile add drivers/usb/host/mtk-xhci* files.

Signed-off-by: Chunfeng Yun 
---
v3: no changes

v2: new patch
---
 MAINTAINERS | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index e73636b75f29..360c6131b866 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2084,7 +2084,7 @@ M:Chunfeng Yun 
 L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
 L: linux-media...@lists.infradead.org (moderated for non-subscribers)
 S: Maintained
-F: Documentation/devicetree/bindings/phy/phy-mtk-*
+F: Documentation/devicetree/bindings/phy/mediatek,*
 F: drivers/phy/mediatek/
 
 ARM/Microchip (AT91) SoC support
@@ -11139,6 +11139,8 @@ L:  linux-...@vger.kernel.org
 L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
 L: linux-media...@lists.infradead.org (moderated for non-subscribers)
 S: Maintained
+F: Documentation/devicetree/bindings/usb/mediatek,*
+F: drivers/usb/host/xhci-mtk*
 F: drivers/usb/mtu3/
 
 MEGACHIPS STDP-GE-B850V3-FW LVDS/DP++ BRIDGES
-- 
2.18.0

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[PATCH v2 0/5] Thermal devfreq cooling improvements with Energy Model

Hi all,

This patch set is a continuation of my previous work, which aimed
to add Energy Model to all devices. This series is a follow up
for the patches which got merged to v5.9-rc1. It aims to change
the thermal devfreq cooling and use the Energy Model instead of
private power table and structures. The new registration interface
in the patch 3/5 helps to register devfreq cooling and the EM in one
call. There is also another improvement, patch 2/5 is changing the
way how thermal gets the device status. Now it's taken on demand
and stored as a copy. The last patch wouldn't go through thermal tree,
but it's here for consistency.

The patch set is based on current next-20201118, which has new EM API
in the pm/linux-next tree.

changes:
v2:
- renamed freq_get_state() and related to perf_idx pattern as
  suggested by Ionela
v1 [2]

Regards,
Lukasz Luba

[1] https://lkml.org/lkml/2020/5/11/326
[2] https://lore.kernel.org/linux-pm/20200921122007.29610-1-lukasz.l...@arm.com/

Lukasz Luba (5):
  thermal: devfreq_cooling: change tracing function and arguments
  thermal: devfreq_cooling: get a copy of device status
  thermal: devfreq_cooling: add new registration functions with Energy
Model
  thermal: devfreq_cooling: remove old power model and use EM
  drm/panfrost: Register devfreq cooling and attempt to add Energy Model

 drivers/gpu/drm/panfrost/panfrost_devfreq.c |   2 +-
 drivers/thermal/devfreq_cooling.c   | 434 ++--
 include/linux/devfreq_cooling.h |  39 +-
 include/trace/events/thermal.h  |  19 +-
 4 files changed, 259 insertions(+), 235 deletions(-)

-- 
2.17.1

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[PATCH 8/9] firmware: xilinx: Add IOCTL support for AIE ISR Clear

From: Izhar Ameer Shaikh 

Latching of AIE NPI Interrupts is present in Versal ES1 Silicon Rev,
however it has been removed from ES2 rev.
As a result on ES1, in order to use the interrupt, a client needs to
request PMC to clear/ack the interrupt.

Provide an EEMI IOCTL to serve the same purpose. Note that, this will
only be applicable for ES1 rev. For ES2 and other non-silicon platforms,
this call will essentially be a NOP in the firmware.

Signed-off-by: Izhar Ameer Shaikh 
Signed-off-by: Wendy Liang 
---
 drivers/firmware/xilinx/zynqmp.c | 14 ++
 include/linux/firmware/xlnx-zynqmp.h |  8 
 2 files changed, 22 insertions(+)

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index efb8a66..7a0c6a3 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -702,6 +702,20 @@ int zynqmp_pm_set_boot_health_status(u32 value)
 }
 
 /**
+ * zynqmp_pm_clear_aie_npi_isr - Clear AI engine NPI interrupt status register
+ * @node:  AI engine node id
+ * @irq_mask:  Mask of AI engine NPI interrupt bit to clear
+ *
+ * Return: Returns status, either success or error+reason
+ */
+int zynqmp_pm_clear_aie_npi_isr(u32 node, u32 irq_mask)
+{
+   return zynqmp_pm_invoke_fn(PM_IOCTL, node, IOCTL_AIE_ISR_CLEAR,
+  irq_mask, 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_clear_aie_npi_isr);
+
+/**
  * zynqmp_pm_reset_assert - Request setting of reset (1 - assert, 0 - release)
  * @reset: Reset to be configured
  * @assert_flag:   Flag stating should reset be asserted (1) or
diff --git a/include/linux/firmware/xlnx-zynqmp.h 
b/include/linux/firmware/xlnx-zynqmp.h
index 5968df8..b929d57 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -116,6 +116,8 @@ enum pm_ioctl_id {
IOCTL_READ_PGGS = 15,
/* Set healthy bit value */
IOCTL_SET_BOOT_HEALTH_STATUS = 17,
+   /* AI engine NPI ISR clear */
+   IOCTL_AIE_ISR_CLEAR = 24,
 };
 
 enum pm_query_id {
@@ -357,6 +359,7 @@ int zynqmp_pm_write_pggs(u32 index, u32 value);
 int zynqmp_pm_read_pggs(u32 index, u32 *value);
 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
 int zynqmp_pm_set_boot_health_status(u32 value);
+int zynqmp_pm_clear_aie_npi_isr(u32 node, u32 irq_mask);
 #else
 static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
 {
@@ -507,6 +510,11 @@ static inline int zynqmp_pm_set_boot_health_status(u32 
value)
 {
return -ENODEV;
 }
+
+static int zynqmp_pm_clear_aie_npi_isr(u32 node, u32 irq_mask)
+{
+   return -ENODEV;
+}
 #endif
 
 #endif /* __FIRMWARE_ZYNQMP_H__ */
-- 
2.7.4

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Re: [PATCH] drm/vram: fix incorrect flag variable usage.

2020-11-19 Thread Wen Pu

On 2020/11/19 9:14, Dave Airlie wrote:
> From: Dave Airlie 
> 
> In 7053e0eab473119503f6565b4e398f9a73122481
> drm/vram-helper: stop using TTM placement flags
> 
> it appears the flags got mixed up.
> 
> This should fix a regression on ast
> [   64.782340] WARNING: CPU: 51 PID: 1964 at 
> drivers/gpu/drm/drm_gem_vram_helper.c:284 drm_gem_vram_offset+0x35/0x40 
> [drm_vram_helper]
..
> 

It may need this line:
Fixes: 7053e0eab473 ("drm/vram-helper: stop using TTM placement flags")

If possible, kindly add following tags as appropriate:
Reported-by: Pu Wen 
Tested-by: Pu Wen 

> Signed-off-by: Dave Airlie > Cc: Wen Pu 
> Cc: David Laight 
> Cc: Christian König 
> ---
>  drivers/gpu/drm/drm_gem_vram_helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c 
> b/drivers/gpu/drm/drm_gem_vram_helper.c
> index 50cad0e4a92e..2896a057b771 100644
> --- a/drivers/gpu/drm/drm_gem_vram_helper.c
> +++ b/drivers/gpu/drm/drm_gem_vram_helper.c
> @@ -140,7 +140,7 @@ static void drm_gem_vram_placement(struct 
> drm_gem_vram_object *gbo,
>   unsigned int c = 0;
>  
>   if (pl_flag & DRM_GEM_VRAM_PL_FLAG_TOPDOWN)
> - pl_flag = TTM_PL_FLAG_TOPDOWN;
> + invariant_flag = TTM_PL_FLAG_TOPDOWN;

invariant_flag should be invariant_flags :)

This change fix the regression on ast driver.

Thx.

>  
>   gbo->placement.placement = gbo->placements;
>   gbo->placement.busy_placement = gbo->placements;
> 

-- 
Regards,
Pu Wen
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[PATCH v5 3/7] dt-bindings: display: add #sound-dai-cells property to rockchip rk3066 hdmi

'#sound-dai-cells' is required to properly interpret
the list of DAI specified in the 'sound-dai' property.
Add it to rockchip,rk3066-hdmi.yaml to document that the
rk3066 HDMI TX also can be used to transmit some audio.

Signed-off-by: Johan Jonker 
---
 .../devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.yaml| 4 
 1 file changed, 4 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.yaml 
b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.yaml
index 4110d003c..585a8d3b9 100644
--- 
a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.yaml
+++ 
b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.yaml
@@ -42,6 +42,9 @@ properties:
 description:
   This soc uses GRF regs to switch the HDMI TX input between vop0 and vop1.
 
+  "#sound-dai-cells":
+const: 0
+
   ports:
 type: object
 
@@ -101,6 +104,7 @@ examples:
   pinctrl-names = "default";
   power-domains = <&power RK3066_PD_VIO>;
   rockchip,grf = <&grf>;
+  #sound-dai-cells = <0>;
 
   ports {
 #address-cells = <1>;
-- 
2.11.0

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[PATCH v2 3/9] misc: xilinx-ai-engine: Implement AI engine cleanup sequence

When AI engine partition is released, that is if no one is using the AI
engine partition, by default, it will cleanup the partition by doing the
following:
* reset the columns
* reset the SHIMs
* clear data and program memory
* gate all the tiles

If user doesn't want the partition is reset when the partition is
released, user can set the control flag to indicate not to reset the
partition when the user requests the partition.

If partition the not to reset partition control flag is set, it will
not execute the above cleanup sequence when the partition is released.

Signed-off-by: Wendy Liang 
Reviewed-by: Hyun Kwon 
---
 drivers/misc/xilinx-ai-engine/Makefile |   3 +-
 drivers/misc/xilinx-ai-engine/ai-engine-aie.c  |  92 
 drivers/misc/xilinx-ai-engine/ai-engine-dev.c  |   2 +
 drivers/misc/xilinx-ai-engine/ai-engine-internal.h |  34 ++
 drivers/misc/xilinx-ai-engine/ai-engine-part.c |   7 +-
 drivers/misc/xilinx-ai-engine/ai-engine-reset.c| 121 +
 include/uapi/linux/xlnx-ai-engine.h|   6 +
 7 files changed, 259 insertions(+), 6 deletions(-)
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-reset.c

diff --git a/drivers/misc/xilinx-ai-engine/Makefile 
b/drivers/misc/xilinx-ai-engine/Makefile
index 7827a0a..39bec61 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -8,4 +8,5 @@ obj-$(CONFIG_XILINX_AIE)+= xilinx-aie.o
 xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
   ai-engine-dev.o \
   ai-engine-part.o \
-  ai-engine-res.o
+  ai-engine-res.o \
+  ai-engine-reset.o
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c 
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index 319260f..36127f0 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -5,6 +5,9 @@
  * Copyright (C) 2020 Xilinx, Inc.
  */
 
+#include 
+#include 
+#include 
 #include 
 
 #include "ai-engine-internal.h"
@@ -24,9 +27,25 @@
 #define AIE_SHIMPL_L1INTR_MASK_A_REGOFF0x00035000U
 #define AIE_SHIMPL_L1INTR_BLOCK_NORTH_B_REGOFF 0x00035050U
 #define AIE_SHIMPL_CLKCNTR_REGOFF  0x00036040U
+#define AIE_SHIMPL_COLRESET_REGOFF 0x00036048U
 #define AIE_SHIMPL_RESET_REGOFF0x0003604cU
 #define AIE_TILE_CORE_CLKCNTR_REGOFF   0x00036040U
 
+/*
+ * Register masks
+ */
+#define AIE_SHIMPL_SHIMRST_MASK0x1U
+#define AIE_SHIMPL_COLRST_MASK 0x1U
+#define AIE_SHIMPL_CLKCNTR_COLBUF_MASK 0x1U
+
+/*
+ * AI engine SHIM reset ID.
+ * TODO: it should follow the Linux reset framework. The ID should be in the
+ * device tree. However, as versal resets is not ready, we hardcode it in the
+ * driver.
+ */
+#define VERSAL_PM_RST_AIE_SHIM_ID  0xc10405fU
+
 static const struct aie_tile_regs aie_kernel_regs[] = {
/* SHIM AXI MM Config */
{.attribute = AIE_TILE_TYPE_SHIMNOC << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
@@ -49,6 +68,12 @@ static const struct aie_tile_regs aie_kernel_regs[] = {
 .soff = AIE_SHIMPL_L1INTR_MASK_A_REGOFF,
 .eoff = AIE_SHIMPL_L1INTR_BLOCK_NORTH_B_REGOFF,
},
+   /* SHIM column reset */
+   {.attribute = (AIE_TILE_TYPE_SHIMPL | AIE_TILE_TYPE_SHIMNOC) <<
+ AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_SHIMPL_COLRESET_REGOFF,
+.eoff = AIE_SHIMPL_COLRESET_REGOFF,
+   },
/* SHIM reset Enable */
{.attribute = (AIE_TILE_TYPE_SHIMPL | AIE_TILE_TYPE_SHIMNOC) <<
  AIE_REGS_ATTR_TILE_TYPE_SHIFT,
@@ -68,6 +93,16 @@ static const struct aie_tile_regs aie_kernel_regs[] = {
},
 };
 
+static const struct aie_single_reg_field aie_col_rst = {
+   .mask = AIE_SHIMPL_COLRST_MASK,
+   .regoff = AIE_SHIMPL_COLRESET_REGOFF,
+};
+
+static const struct aie_single_reg_field aie_col_clkbuf = {
+   .mask = AIE_SHIMPL_CLKCNTR_COLBUF_MASK,
+   .regoff = AIE_SHIMPL_CLKCNTR_REGOFF,
+};
+
 static u32 aie_get_tile_type(struct aie_location *loc)
 {
if (loc->row)
@@ -79,8 +114,63 @@ static u32 aie_get_tile_type(struct aie_location *loc)
return AIE_TILE_TYPE_SHIMNOC;
 }
 
+/**
+ * aie_set_shim_reset() - Set AI engine SHIM reset
+ * @adev: AI engine device
+ * @range: range of AI engine tiles
+ * @assert: true to set reset, false to unset reset
+ */
+static void aie_set_shim_reset(struct aie_device *adev,
+  struct aie_range *range, bool assert)
+{
+   u32 c;
+   u32 val;
+   struct aie_location loc;
+
+   val = FIELD_PREP(AIE_SHIMPL_SHIMRST_MASK, (assert ? 1 : 0));
+   loc.row = 0;
+   for (c = range->start.col; c < range->start.col + range->size.col;
+c++) {
+

[PATCH v5 4/7] drm: rockchip: add sound support to rk3066 hdmi driver

From: Zheng Yang 

Add sound support to the rk3066 HDMI driver.

The I2S input of the HDMI TX allows transmission of
DVD-Audio and decoded Dolby Digital
to A/V Receivers and high-end displays.
The interface supports 2 to 8 channels audio up to 192 kHz.
The HDMI TX supports variable word length of
16bits to 32bits for I2S audio inputs.(This driver 24bit max)
There are three I2S input modes supported.(This driver HDMI_I2S only)
On RK3066/PX2 the HDMI TX audio source is connected to I2S_8CH.

Signed-off-by: Zheng Yang 
Signed-off-by: Johan Jonker 
---
 drivers/gpu/drm/rockchip/Kconfig   |   2 +
 drivers/gpu/drm/rockchip/rk3066_hdmi.c | 275 -
 2 files changed, 276 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 310aa1546..4c20445dc 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -11,6 +11,8 @@ config DRM_ROCKCHIP
select DRM_DW_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
select DRM_RGB if ROCKCHIP_RGB
select SND_SOC_HDMI_CODEC if ROCKCHIP_CDN_DP && SND_SOC
+   select SND_SOC_HDMI_CODEC if ROCKCHIP_RK3066_HDMI && SND_SOC
+   select SND_SOC_ROCKCHIP_I2S if ROCKCHIP_RK3066_HDMI && SND_SOC
help
  Choose this option if you have a Rockchip soc chipset.
  This driver provides kernel mode setting and buffer
diff --git a/drivers/gpu/drm/rockchip/rk3066_hdmi.c 
b/drivers/gpu/drm/rockchip/rk3066_hdmi.c
index 1c546c3a8..243e4077f 100644
--- a/drivers/gpu/drm/rockchip/rk3066_hdmi.c
+++ b/drivers/gpu/drm/rockchip/rk3066_hdmi.c
@@ -13,6 +13,8 @@
 #include 
 #include 
 
+#include 
+
 #include "rk3066_hdmi.h"
 
 #include "rockchip_drm_drv.h"
@@ -20,9 +22,16 @@
 
 #define DEFAULT_PLLA_RATE 3000
 
+struct audio_info {
+   int sample_rate;
+   int channels;
+   int sample_width;
+};
+
 struct hdmi_data_info {
int vic; /* The CEA Video ID (VIC) of the current drm display mode. */
bool sink_is_hdmi;
+   bool sink_has_audio;
unsigned int enc_out_format;
unsigned int colorimetry;
 };
@@ -54,12 +63,19 @@ struct rk3066_hdmi {
 
unsigned int tmdsclk;
 
+   struct platform_device *audio_pdev;
+   bool audio_enable;
+
struct hdmi_data_info hdmi_data;
+   struct audio_info audio;
struct drm_display_mode previous_mode;
 };
 
 #define to_rk3066_hdmi(x) container_of(x, struct rk3066_hdmi, x)
 
+static int
+rk3066_hdmi_config_audio(struct rk3066_hdmi *hdmi, struct audio_info *audio);
+
 static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset)
 {
return readl_relaxed(hdmi->regs + offset);
@@ -205,6 +221,23 @@ static int rk3066_hdmi_config_avi(struct rk3066_hdmi *hdmi,
HDMI_INFOFRAME_AVI, 0, 0, 0);
 }
 
+static int rk3066_hdmi_config_aai(struct rk3066_hdmi *hdmi,
+ struct audio_info *audio)
+{
+   union hdmi_infoframe frame;
+   int rc;
+
+   rc = hdmi_audio_infoframe_init(&frame.audio);
+
+   frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
+   frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
+   frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
+   frame.audio.channels = hdmi->audio.channels;
+
+   return rk3066_hdmi_upload_frame(hdmi, rc, &frame,
+   HDMI_INFOFRAME_AAI, 0, 0, 0);
+}
+
 static int rk3066_hdmi_config_video_timing(struct rk3066_hdmi *hdmi,
   struct drm_display_mode *mode)
 {
@@ -353,6 +386,7 @@ static int rk3066_hdmi_setup(struct rk3066_hdmi *hdmi,
hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK,
  HDMI_VIDEO_MODE_HDMI);
rk3066_hdmi_config_avi(hdmi, mode);
+   rk3066_hdmi_config_audio(hdmi, &hdmi->audio);
} else {
hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 0);
}
@@ -369,9 +403,20 @@ static int rk3066_hdmi_setup(struct rk3066_hdmi *hdmi,
 */
rk3066_hdmi_i2c_init(hdmi);
 
-   /* Unmute video output. */
+   /* Unmute video and audio output. */
hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
  HDMI_VIDEO_AUDIO_DISABLE_MASK, HDMI_AUDIO_DISABLE);
+   if (hdmi->audio_enable) {
+   hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, HDMI_AUDIO_DISABLE, 0);
+   /* Reset audio capture logic. */
+   hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
+ HDMI_AUDIO_CP_LOGIC_RESET_MASK,
+ HDMI_AUDIO_CP_LOGIC_RESET);
+   usleep_range(900, 1000);
+   hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
+ HDMI_AUDIO_CP_LOGIC_RESET_MASK, 0);
+   }
+
return 0;
 }
 
@@ -473,9 +518,13 @@ static int rk3066_hdmi_connector_get_modes(struct 
drm_connector *connector)
edid = drm_get_edid(connector, hdmi->ddc);

[PATCH v3] drm/msm/dp: fix connect/disconnect handled at irq_hpd

2020-11-19 Thread Kuogee Hsieh

Some usb type-c dongle use irq_hpd request to perform device connection
and disconnection. This patch add handling of both connection and
disconnection are based on the state of hpd_state and sink_count.

Changes in V2:
-- add dp_display_handle_port_ststus_changed()
-- fix kernel test robot complaint

Changes in V3:
-- add encoder_mode_set into struct dp_display_private

Reported-by: kernel test robot 
Fixes: 26b8d66a399e ("drm/msm/dp: promote irq_hpd handle to handle link 
training correctly")
Tested-by: Stephen Boyd 
Signed-off-by: Kuogee Hsieh 
---
 drivers/gpu/drm/msm/dp/dp_display.c | 92 ++---
 1 file changed, 55 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c 
b/drivers/gpu/drm/msm/dp/dp_display.c
index e9cb878..6e971d5 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -102,6 +102,8 @@ struct dp_display_private {
struct dp_display_mode dp_mode;
struct msm_dp dp_display;
 
+   bool encoder_mode_set;
+
/* wait for audio signaling */
struct completion audio_comp;
 
@@ -279,13 +281,24 @@ static void dp_display_send_hpd_event(struct msm_dp 
*dp_display)
drm_helper_hpd_irq_event(connector->dev);
 }
 
-static int dp_display_send_hpd_notification(struct dp_display_private *dp,
-   bool hpd)
+
+static void dp_display_set_encoder_mode(struct dp_display_private *dp)
 {
-   static bool encoder_mode_set;
struct msm_drm_private *priv = dp->dp_display.drm_dev->dev_private;
struct msm_kms *kms = priv->kms;
 
+   if (!dp->encoder_mode_set && dp->dp_display.encoder &&
+   kms->funcs->set_encoder_mode) {
+   kms->funcs->set_encoder_mode(kms,
+   dp->dp_display.encoder, false);
+
+   dp->encoder_mode_set = true;
+   }
+}
+
+static int dp_display_send_hpd_notification(struct dp_display_private *dp,
+   bool hpd)
+{
if ((hpd && dp->dp_display.is_connected) ||
(!hpd && !dp->dp_display.is_connected)) {
DRM_DEBUG_DP("HPD already %s\n", (hpd ? "on" : "off"));
@@ -298,15 +311,6 @@ static int dp_display_send_hpd_notification(struct 
dp_display_private *dp,
 
dp->dp_display.is_connected = hpd;
 
-   if (dp->dp_display.is_connected && dp->dp_display.encoder
-   && !encoder_mode_set
-   && kms->funcs->set_encoder_mode) {
-   kms->funcs->set_encoder_mode(kms,
-   dp->dp_display.encoder, false);
-   DRM_DEBUG_DP("set_encoder_mode() Completed\n");
-   encoder_mode_set = true;
-   }
-
dp_display_send_hpd_event(&dp->dp_display);
 
return 0;
@@ -342,7 +346,6 @@ static int dp_display_process_hpd_high(struct 
dp_display_private *dp)
 
dp_add_event(dp, EV_USER_NOTIFICATION, true, 0);
 
-
 end:
return rc;
 }
@@ -359,6 +362,8 @@ static void dp_display_host_init(struct dp_display_private 
*dp)
if (dp->usbpd->orientation == ORIENTATION_CC2)
flip = true;
 
+   dp_display_set_encoder_mode(dp);
+
dp_power_init(dp->power, flip);
dp_ctrl_host_init(dp->ctrl, flip);
dp_aux_init(dp->aux);
@@ -442,24 +447,42 @@ static void dp_display_handle_video_request(struct 
dp_display_private *dp)
}
 }
 
-static int dp_display_handle_irq_hpd(struct dp_display_private *dp)
+static int dp_display_handle_port_ststus_changed(struct dp_display_private *dp)
 {
-   u32 sink_request;
-
-   sink_request = dp->link->sink_request;
+   int rc = 0;
 
-   if (sink_request & DS_PORT_STATUS_CHANGED) {
-   if (dp_display_is_sink_count_zero(dp)) {
-   DRM_DEBUG_DP("sink count is zero, nothing to do\n");
-   return -ENOTCONN;
+   if (dp_display_is_sink_count_zero(dp)) {
+   DRM_DEBUG_DP("sink count is zero, nothing to do\n");
+   if (dp->hpd_state != ST_DISCONNECTED) {
+   dp->hpd_state = ST_DISCONNECT_PENDING;
+   dp_add_event(dp, EV_USER_NOTIFICATION, false, 0);
+   }
+   } else {
+   if (dp->hpd_state == ST_DISCONNECTED) {
+   dp->hpd_state = ST_CONNECT_PENDING;
+   rc = dp_display_process_hpd_high(dp);
+   if (rc)
+   dp->hpd_state = ST_DISCONNECTED;
}
+   }
+
+   return rc;
+}
+
+static int dp_display_handle_irq_hpd(struct dp_display_private *dp)
+{
+   u32 sink_request = dp->link->sink_request;
 
-   return dp_display_process_hpd_high(dp);
+   if (dp->hpd_state == ST_DISCONNECTED) {
+   if (sink_request & DP_LINK_STATUS_UPDATED) {
+   DRM_ERROR("Disc

[PATCH v2 6/9] misc: xilinx-ai-engine: add request and release tiles

Add request/release and related clock gating functions to AI engine
driver:
* scanning when the partition is being requested to know which tiles
  are in use.
* check if a tile is gated or not
* tiles requesting and releasing ioctl so that user application can
  enable/disable tiles at runtime.

Signed-off-by: Wendy Liang 
Reviewed-by: Hyun Kwon 
---
 drivers/misc/xilinx-ai-engine/Makefile |   1 +
 drivers/misc/xilinx-ai-engine/ai-engine-aie.c  | 227 ++-
 drivers/misc/xilinx-ai-engine/ai-engine-clock.c| 244 +
 drivers/misc/xilinx-ai-engine/ai-engine-dev.c  |  19 +-
 drivers/misc/xilinx-ai-engine/ai-engine-internal.h |  34 +++
 drivers/misc/xilinx-ai-engine/ai-engine-part.c |  32 +++
 drivers/misc/xilinx-ai-engine/ai-engine-res.c  |  51 +
 include/uapi/linux/xlnx-ai-engine.h|  31 +++
 8 files changed, 631 insertions(+), 8 deletions(-)
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-clock.c

diff --git a/drivers/misc/xilinx-ai-engine/Makefile 
b/drivers/misc/xilinx-ai-engine/Makefile
index 1b743fa..2e67b25 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -6,6 +6,7 @@
 obj-$(CONFIG_XILINX_AIE)   += xilinx-aie.o
 
 xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
+  ai-engine-clock.o \
   ai-engine-dev.o \
   ai-engine-dma.o \
   ai-engine-mem.o \
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c 
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index 19c262d..ff721b3 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -41,6 +41,9 @@
 #define AIE_SHIMPL_SHIMRST_MASK0x1U
 #define AIE_SHIMPL_COLRST_MASK 0x1U
 #define AIE_SHIMPL_CLKCNTR_COLBUF_MASK 0x1U
+#define AIE_SHIMPL_CLKCNTR_NEXTCLK_MASKBIT(1)
+#define AIE_TILE_CLKCNTR_COLBUF_MASK   BIT(0)
+#define AIE_TILE_CLKCNTR_NEXTCLK_MASK  BIT(1)
 
 /*
  * AI engine SHIM reset ID.
@@ -221,10 +224,232 @@ static int aie_reset_shim(struct aie_device *adev, 
struct aie_range *range)
return 0;
 }
 
+static int aie_init_part_clk_state(struct aie_partition *apart)
+{
+   int ret, num_tiles;
+
+   num_tiles = apart->range.size.col * (apart->range.size.row - 1);
+
+   ret = aie_resource_initialize(&apart->cores_clk_state, num_tiles);
+   if (ret) {
+   dev_err(&apart->dev,
+   "failed to initialize cores clock state resource.\n");
+   return ret;
+   }
+
+   ret = aie_resource_initialize(&apart->tiles_inuse, num_tiles);
+   if (ret) {
+   dev_err(&apart->dev,
+   "failed to initialize tiles in use resource.\n");
+   return ret;
+   }
+
+   return 0;
+}
+
+static int aie_scan_part_clocks(struct aie_partition *apart)
+{
+   struct aie_device *adev = apart->adev;
+   struct aie_range *range = &apart->range;
+   struct aie_location loc;
+
+   /* Clear the bitmap of cores and memories clock state */
+   aie_resource_put_region(&apart->cores_clk_state, 0,
+   apart->cores_clk_state.total);
+
+   for (loc.col = range->start.col;
+loc.col < range->start.col + range->size.col;
+loc.col++) {
+   for (loc.row = range->start.row;
+loc.row < range->start.row + range->size.row - 1;
+loc.row++) {
+   void __iomem *va;
+   u32 val, nbitpos;
+
+   /*
+* Reading registers of the current tile to see the next
+* tile is clock gated.
+*/
+   nbitpos = loc.col * (range->size.row - 1) + loc.row;
+
+   if (aie_get_tile_type(&loc) != AIE_TILE_TYPE_TILE) {
+   /* Checks shim tile for next core tile */
+   va = adev->base +
+aie_cal_regoff(adev, loc,
+   AIE_SHIMPL_CLKCNTR_REGOFF);
+   val = ioread32(va);
+
+   /*
+* check if the clock buffer and the next clock
+* tile is set, if one of them is not set, the
+* tiles of the column are clock gated.
+*/
+   if (!(val & AIE_SHIMPL_CLKCNTR_COLBUF_MASK) ||
+   !(val & AIE_SHIMPL_CLKCNTR_NEXTCLK_MASK))
+   break;
+
+   /* Set next tile in the row clock state on */
+

[PATCH v3 06/11] dt-bindings: phy: convert HDMI PHY binding to YAML schema

Convert HDMI PHY binding to YAML schema mediatek,hdmi-phy.yaml

Cc: Chun-Kuang Hu 
Signed-off-by: Chunfeng Yun 
Reviewed-by: Rob Herring 
---
v3: add Reviewed-by Rob
v2: fix binding check warning of reg in example
---
 .../display/mediatek/mediatek,hdmi.txt| 18 +---
 .../bindings/phy/mediatek,hdmi-phy.yaml   | 91 +++
 2 files changed, 92 insertions(+), 17 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
index 6b1c586403e4..b284ca51b913 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
@@ -53,23 +53,7 @@ Required properties:
 
 HDMI PHY
 
-
-The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
-output and drives the HDMI pads.
-
-Required properties:
-- compatible: "mediatek,-hdmi-phy"
-- the supported chips are mt2701, mt7623 and mt8173
-- reg: Physical base address and length of the module's registers
-- clocks: PLL reference clock
-- clock-names: must contain "pll_ref"
-- clock-output-names: must be "hdmitx_dig_cts" on mt8173
-- #phy-cells: must be <0>
-- #clock-cells: must be <0>
-
-Optional properties:
-- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
-- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
+See phy/mediatek,hdmi-phy.yaml
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml 
b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
new file mode 100644
index ..96700bb8bc00
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding
+
+maintainers:
+  - Chun-Kuang Hu 
+  - Chunfeng Yun 
+
+description: |
+  The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
+  output and drives the HDMI pads.
+
+properties:
+  $nodename:
+pattern: "^hdmi-phy@[0-9a-f]+$"
+
+  compatible:
+enum:
+  - mediatek,mt2701-hdmi-phy
+  - mediatek,mt7623-hdmi-phy
+  - mediatek,mt8173-hdmi-phy
+
+  reg:
+maxItems: 1
+
+  clocks:
+items:
+  - description: PLL reference clock
+
+  clock-names:
+items:
+  - const: pll_ref
+
+  clock-output-names:
+items:
+  - const: hdmitx_dig_cts
+
+  "#phy-cells":
+const: 0
+
+  "#clock-cells":
+const: 0
+
+  mediatek,ibias:
+description:
+  TX DRV bias current for < 1.65Gbps
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 0
+maximum: 63
+default: 0xa
+
+  mediatek,ibias_up:
+description:
+  TX DRV bias current for >= 1.65Gbps
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 0
+maximum: 63
+default: 0x1c
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - clock-output-names
+  - "#phy-cells"
+  - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+hdmi_phy: hdmi-phy@10209100 {
+compatible = "mediatek,mt8173-hdmi-phy";
+reg = <0x10209100 0x24>;
+clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+clock-names = "pll_ref";
+clock-output-names = "hdmitx_dig_cts";
+mediatek,ibias = <0xa>;
+mediatek,ibias_up = <0x1c>;
+#clock-cells = <0>;
+#phy-cells = <0>;
+};
+
+...
-- 
2.18.0

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Re: [PATCH RESEND 2/2] drm/drm_vblank: set the dma-fence timestamp during send_vblank_event

2020-11-19 Thread veeras


On 2020-11-13 12:45, Daniel Vetter wrote:
On Thu, Nov 12, 2020 at 10:27:23AM -0800, Veera Sundaram Sankaran 
wrote:

The explicit out-fences in crtc are signaled as part of vblank event,
indicating all framebuffers present on the Atomic Commit request are
scanned out on the screen. Though the fence signal and the vblank 
event

notification happens at the same time, triggered by the same hardware
vsync event, the timestamp set in both are different. With drivers
supporting precise vblank timestamp the difference between the two
timestamps would be even higher. This might have an impact on use-mode
frameworks using these fence timestamps for purposes other than simple
buffer usage. For instance, the Android framework uses the 
retire-fences

as an alternative to vblank when frame-updates are in progress Set the
fence timestamp during send vblank event to avoid discrepancies.


I think a reference to the exact source code in android that does this
would be really useful. Something in drm_hwcomposer or whatever is 
doing

this.



Thanks for the review. Sorry for not getting back earlier, was waiting
for the review on [patch 1/2], so that both comments can be addressed 
together.

Here is the reference for Android expecting retire-fence timestamp to
match exactly with hardware vsync as it is used for the dispsync model.

Usage: https://source.android.com/devices/graphics/implement-vsync
Code: 
https://android.googlesource.com/platform/frameworks/native/+/master/services/surfaceflinger/Scheduler/Scheduler.cpp#397

Will update the commit-text with the links as part of V2 patch.

Thanks,
Veera


Aside from documenting why we want to do this I think this all looks
reasonable.
-Daniel



Signed-off-by: Veera Sundaram Sankaran 
---
 drivers/gpu/drm/drm_vblank.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/drm_vblank.c 
b/drivers/gpu/drm/drm_vblank.c

index b18e1ef..b38e50c 100644
--- a/drivers/gpu/drm/drm_vblank.c
+++ b/drivers/gpu/drm/drm_vblank.c
@@ -24,6 +24,7 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  */

+#include 
 #include 
 #include 
 #include 
@@ -999,6 +1000,14 @@ static void send_vblank_event(struct drm_device 
*dev,

e->event.seq.time_ns = ktime_to_ns(now);
break;
}
+
+   /*
+* update fence timestamp with the same vblank timestamp as both
+* are signaled by the same event
+*/
+   if (e->base.fence)
+   e->base.fence->timestamp = now;
+
trace_drm_vblank_event_delivered(e->base.file_priv, e->pipe, seq);
drm_send_event_locked(dev, &e->base);
 }
--
2.7.4


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Re: [PATCH v6 1/2] dt-bindings: display: himax,hx8837: Add Himax HX8837 bindings

2020-11-19 Thread Lubomir Rintel

On Sun, Nov 01, 2020 at 06:39:22PM +0200, Laurent Pinchart wrote:
> Hi Lubomir,
> 
> Thank you for the patch.

Thanks for the message. Some responses inline below.

> On Fri, Oct 30, 2020 at 04:07:59AM +0100, Lubomir Rintel wrote:
> > Himax HX8837 is a secondary display controller used to drive the panel
> > on OLPC platforms.
> > 
> > Signed-off-by: Lubomir Rintel 
> > Reviewed-by: Rob Herring 
> > 
> > ---
> > Changes since v4:
> > - Rob's Reviewed-by
> > 
> > Changes since v3:
> > - Moved to bindings/display/
> > - Added the ports
> > - Converted to YAML
> > - Removed Pavel's Ack, because the changes are substantial
> > 
> > Changes since v2:
> > - s/betweend/between/
> > 
> > Changes since v1:
> > - s/load-gpio/load-gpios/
> > - Use interrupt bindings instead of gpio for the IRQ
> > 
> >  .../bindings/display/bridge/himax,hx8837.yaml | 96 +++
> >  1 file changed, 96 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
> > 
> > diff --git 
> > a/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml 
> > b/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
> > new file mode 100644
> > index 0..f5b0a00f5089d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/himax,hx8837.yaml
> > @@ -0,0 +1,96 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (C) 2018,2019,2020 Lubomir Rintel 
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/bridge/himax,hx8837.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: HX8837 Display Controller Device Tree Bindings
> > +
> > +maintainers:
> > +  - Lubomir Rintel 
> > +
> > +properties:
> > +  compatible:
> > +const: himax,hx8837
> > +
> > +  reg:
> > +const: 0xd
> > +
> > +  load-gpios:
> > +maxItems: 1
> > +description: GPIO specifier of DCON_LOAD pin (active high)
> > +
> > +  stat-gpios:
> > +minItems: 2
> > +description: GPIO specifier of DCON_STAT0 and DCON_STAT1 pins (active 
> > high)
> > +
> > +  interrupts:
> > +maxItems: 1
> > +description: Interrupt specifier of DCON_IRQ pin (edge falling)
> > +
> > +  ports:
> > +type: object
> > +
> > +properties:
> > +  port@0:
> > +type: object
> > +description: |
> > +  Video port for RGB input.
> > +
> > +  port@1:
> > +type: object
> > +description: |
> > +  Video port connected to the panel.
> > +
> > +required:
> > +  - port@0
> > +  - port@1
> 
> No regulators ?

There are four.

On the OLPC platform they're controlled together by the EC.

I've added the supplies to the EC driver and looked into supporting them 
properly in the driver and am finding it somehow tricky to do it properly.

I couldn't figure out what is the proper place to enable and disable the
regulators. Also drm_bridge_remove() just mercilessly tearing down the
bridge without ensuring it's not used anymore doesn't help us on driver
unbind.

I'm wondering if it's okay if I leave the driver without explicit
support for the power supplies for now, assuming that EC just takes
care of enabling the power and never disable it?

> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - load-gpios
> > +  - stat-gpios
> 
> Do stat-gpios need to be mandatory ? The driver in patch 2/2 doesn't
> seem to use them, could we have boards where those signals are not
> connected to GPIOs ?

Perhaps not, in theory.

Pretty sure the OLPC machines are the only ones that utilize this
silicon though.

> > +  - interrupts
> > +  - ports
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +#include 
> > +#include 
> > +
> > +i2c {
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +
> 
> Could you please avoid spaces or tabs at end of lines ? There are three
> other occurrences below.

Ugh, I was sure I ran checkpatch.pl, but apparently not.
Sorry for that.

> > +lcd-controller@d {
> > +compatible = "himax,hx8837";
> > +reg = <0x0d>;
> > +stat-gpios = <&gpio 100 GPIO_ACTIVE_HIGH>,
> > + <&gpio 101 GPIO_ACTIVE_HIGH>;
> > +load-gpios = <&gpio 142 GPIO_ACTIVE_HIGH>;
> > +interrupts = <&gpio 124 IRQ_TYPE_EDGE_FALLING>;
> > +
> > +ports {
> > +#address-cells = <0x01>;
> > +#size-cells = <0x00>;
> > +
> > +port@0 {
> > +reg = <0x00>;
> 
> reg = <0> should be fine. Same below.
> 
> With thse small issues addressed,
> 
> > +dcon_rgb_in: endpoint {
> > +remote-endpoint = <&lcd0_rgb_out>;
> > +};
> > +};
> > +
> > +port@1 {
> > +reg = <0x01>;
> > +dcon_gettl_out: endpoint {
> > +

[PATCH 4/9] misc: xilinx-ai-engine: expose AI engine tile memories to userspace

There is no concern to have userspace to directly access AI engine
program and data memories. It will be much faster to directly copy
data to and from these memories from userspace.

We choose to use DMA buf for the data and program memory because of the
DMA buf features. DMA buf can share the DMA memory between applications
and different devices, which can benefit on how to share data with AI
engine device in future.

There is one DMA buf per type of memory in an AI engine partition. e.g.
There is one DMA buf for all the tile core program memories in an AI
engine partition. There is another DMA buf for all the tile data
memories in an AI engine partition.

Signed-off-by: Wendy Liang 
Reviewed-by: Hyun Kwon 
---
 drivers/misc/xilinx-ai-engine/Makefile |   1 +
 drivers/misc/xilinx-ai-engine/ai-engine-aie.c  |  36 +++
 drivers/misc/xilinx-ai-engine/ai-engine-internal.h |  30 +++
 drivers/misc/xilinx-ai-engine/ai-engine-mem.c  | 274 +
 drivers/misc/xilinx-ai-engine/ai-engine-part.c |  47 
 drivers/misc/xilinx-ai-engine/ai-engine-reset.c|  38 +++
 include/uapi/linux/xlnx-ai-engine.h|  49 
 7 files changed, 475 insertions(+)
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-mem.c

diff --git a/drivers/misc/xilinx-ai-engine/Makefile 
b/drivers/misc/xilinx-ai-engine/Makefile
index 39bec61..2dbed42 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_XILINX_AIE)+= xilinx-aie.o
 
 xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
   ai-engine-dev.o \
+  ai-engine-mem.o \
   ai-engine-part.o \
   ai-engine-res.o \
   ai-engine-reset.o
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c 
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index 36127f0..7fce2f00 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -12,10 +12,14 @@
 
 #include "ai-engine-internal.h"
 
+#define KBYTES(n)  ((n) * 1024)
+
 #define AIE_ARRAY_SHIFT30U
 #define AIE_COL_SHIFT  23U
 #define AIE_ROW_SHIFT  18U
 
+#define NUM_MEMS_PER_TILE  2U
+
 /*
  * Registers offsets
  */
@@ -114,6 +118,37 @@ static u32 aie_get_tile_type(struct aie_location *loc)
return AIE_TILE_TYPE_SHIMNOC;
 }
 
+static unsigned int aie_get_mem_info(struct aie_range *range,
+struct aie_part_mem *pmem)
+{
+   unsigned int i;
+
+   if (range->start.row + range->size.row <= 1) {
+   /* SHIM row only, no memories in this range */
+   return 0;
+   }
+   if (!pmem)
+   return NUM_MEMS_PER_TILE;
+
+   for (i = 0; i < NUM_MEMS_PER_TILE; i++) {
+   struct aie_mem *mem = &pmem[i].mem;
+
+   memcpy(&mem->range, range, sizeof(*range));
+   if (!mem->range.start.row) {
+   mem->range.start.row = 1;
+   mem->range.size.row--;
+   }
+   }
+   /* Setup tile data memory information */
+   pmem[0].mem.offset = 0;
+   pmem[0].mem.size = KBYTES(32);
+   /* Setup program memory information */
+   pmem[1].mem.offset = 0x2;
+   pmem[1].mem.size = KBYTES(16);
+
+   return NUM_MEMS_PER_TILE;
+}
+
 /**
  * aie_set_shim_reset() - Set AI engine SHIM reset
  * @adev: AI engine device
@@ -170,6 +205,7 @@ static int aie_reset_shim(struct aie_device *adev, struct 
aie_range *range)
 
 static const struct aie_tile_operations aie_ops = {
.get_tile_type = aie_get_tile_type,
+   .get_mem_info = aie_get_mem_info,
.reset_shim = aie_reset_shim,
 };
 
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h 
b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
index 2acd34f..e84610b 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-internal.h
@@ -12,6 +12,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -67,8 +69,30 @@ struct aie_device;
 struct aie_partition;
 
 /**
+ * struct aie_part_mem - AI engine partition memory information structure
+ * @apart: AI engine partition
+ * @dbuf: dmabuf pointer associated with the memory
+ * @mem: memory information of a type of memory
+ * @size: size of the total memories in the partition
+ *
+ * This structure is to keep the information of a type of memory in a
+ * partition. The memory information will be stored in @mem property.
+ * The following information will be keep:
+ *  * memory start address offset within a tile
+ *  * memory size
+ *  * what tiles contain this type of memory
+ */
+struct aie_part_mem {
+   struct aie_partition *apart;
+   struct dma_buf *dbuf;
+   struct aie_m

Re: [PATCH v3 0/5] console: Miscellaneous clean-ups, do not use FNTCHARCNT() in fbcon.c

2020-11-19 Thread Peilin Ye

On Sat, Nov 14, 2020 at 01:22:22PM +0100, Greg Kroah-Hartman wrote:
> Ah, here's a hint:
>   https://wiki.archlinux.org/index.php/Linux_console#Fonts
> 
> The setfont tool should help you out here.

setfont seems to work fine, I tried Georgian-Fixed16 (256 chars) and
Uni2-VGA16 (512 chars) under /usr/share/consolefonts/ in my Ubuntu box,
including setting all consoles to the same font:

for i in {1..6}; do
sudo setfont -C /dev/tty${i} 
/usr/share/consolefonts/Georgian-Fixed16.psf.gz
done

Font rotation also seems to work fine:

for i in {1..4}; do
echo $i | sudo tee /sys/class/graphics/fbcon/rotate
sleep 1
done

One last thing I can think of is tile blitting, but I don't have the
hardware (e.g. a Matrox G400 card, see FB_TILEBLITTING in
drivers/video/fbdev/Kconfig) at hand, nor did I figure out how to
simulate it after searching for a while.  However based on the other
tests above I believe vc->vc_font.charcount is set properly.

Thanks,
Peilin Ye

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[PATCH v3 09/11] dt-bindings: usb: convert mediatek, mtk-xhci.txt to YAML schema

Convert mediatek,mtk-xhci.txt to YAML schema mediatek,mtk-xhci.yaml

Signed-off-by: Chunfeng Yun 
---
v3:
  1. fix yamllint warning
  2. remove pinctrl* properties supported by default suggested by Rob
  3. drop unused labels
  4. modify description of mediatek,syscon-wakeup
  5. remove type of imod-interval-ns

v2: new patch
---
 .../bindings/usb/mediatek,mtk-xhci.txt| 121 -
 .../bindings/usb/mediatek,mtk-xhci.yaml   | 171 ++
 2 files changed, 171 insertions(+), 121 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
 create mode 100644 Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml

diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt 
b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
deleted file mode 100644
index 42d8814f903a..
--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
+++ /dev/null
@@ -1,121 +0,0 @@
-MT8173 xHCI
-
-The device node for Mediatek SOC USB3.0 host controller
-
-There are two scenarios: the first one only supports xHCI driver;
-the second one supports dual-role mode, and the host is based on xHCI
-driver. Take account of backward compatibility, we divide bindings
-into two parts.
-
-1st: only supports xHCI driver
-
-
-Required properties:
- - compatible : should be "mediatek,-xhci", "mediatek,mtk-xhci",
-   soc-model is the name of SoC, such as mt8173, mt2712 etc, when using
-   "mediatek,mtk-xhci" compatible string, you need SoC specific ones in
-   addition, one of:
-   - "mediatek,mt8173-xhci"
- - reg : specifies physical base address and size of the registers
- - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control
- - interrupts : interrupt used by the controller
- - power-domains : a phandle to USB power domain node to control USB's
-   mtcmos
- - vusb33-supply : regulator of USB avdd3.3v
-
- - clocks : a list of phandle + clock-specifier pairs, one for each
-   entry in clock-names
- - clock-names : must contain
-   "sys_ck": controller clock used by normal mode,
-   the following ones are optional:
-   "ref_ck": reference clock used by low power mode etc,
-   "mcu_ck": mcu_bus clock for register access,
-   "dma_ck": dma_bus clock for data transfer by DMA,
-   "xhci_ck": controller clock
-
- - phys : see usb-hcd.yaml in the current directory
-
-Optional properties:
- - wakeup-source : enable USB remote wakeup;
- - mediatek,syscon-wakeup : phandle to syscon used to access the register
-   of the USB wakeup glue layer between xHCI and SPM; it depends on
-   "wakeup-source", and has two arguments:
-   - the first one : register base address of the glue layer in syscon;
-   - the second one : hardware version of the glue layer
-   - 1 : used by mt8173 etc
-   - 2 : used by mt2712 etc
- - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0,
-   bit1 for u3port1, ... etc;
- - vbus-supply : reference to the VBUS regulator;
- - usb3-lpm-capable : supports USB3.0 LPM
- - pinctrl-names : a pinctrl state named "default" must be defined
- - pinctrl-0 : pin control group
-   See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
- - imod-interval-ns: default interrupt moderation interval is 5000ns
-
-additionally the properties from usb-hcd.yaml (in the current directory) are
-supported.
-
-Example:
-usb30: usb@1127 {
-   compatible = "mediatek,mt8173-xhci";
-   reg = <0 0x1127 0 0x1000>,
- <0 0x11280700 0 0x0100>;
-   reg-names = "mac", "ippc";
-   interrupts = ;
-   power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
-   clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>,
-<&pericfg CLK_PERI_USB0>,
-<&pericfg CLK_PERI_USB1>;
-   clock-names = "sys_ck", "ref_ck";
-   phys = <&phy_port0 PHY_TYPE_USB3>,
-  <&phy_port1 PHY_TYPE_USB2>;
-   vusb33-supply = <&mt6397_vusb_reg>;
-   vbus-supply = <&usb_p1_vbus>;
-   usb3-lpm-capable;
-   mediatek,syscon-wakeup = <&pericfg 0x400 1>;
-   wakeup-source;
-   imod-interval-ns = <1>;
-};
-
-2nd: dual-role mode with xHCI driver
-
-
-In the case, xhci is added as subnode to mtu3. An example and the DT binding
-details of mtu3 can be found in:
-Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
-
-Required properties:
- - compatible : should be "mediatek,-xhci", "mediatek,mtk-xhci",
-   soc-model is the name of SoC, such as mt8173, mt2712 etc, when using
-   "mediatek,mtk-xhci" compatible string, you need SoC specific ones in
-   addition, one of:
-   - "mediatek,mt8173-xhci"
- - reg : specifies physical base address and size of the registers
- - reg-names: should be "mac" for xHCI

RE: Linux 5.10-rc4

2020-11-19 Thread David Laight

From: Thomas Zimmermann
> Sent: 18 November 2020 19:37
> 
> Hi
> 
> Am 18.11.20 um 19:10 schrieb Linus Torvalds:
> > On Wed, Nov 18, 2020 at 4:12 AM David Laight  
> > wrote:
> >>
> >> I've got the 'splat' below during boot.
> >> This is an 8-core C2758 Atom cpu using the on-board/cpu graphics.
> >> User space is Ubuntu 20.04.
> >>
> >> Additionally the X display has all the colours and alignment slightly
> >> messed up.
> >> 5.9.0 was ok.
> >> I'm just guessing the two issues are related.
> >
> > Sounds likely.  But it would be lovely if you could bisect when
> > exactly the problem(s) started to both verify that, and just to
> > pinpoint the exact change..

I don't quite understand what 'git bisect' did.
I was bisecting between v5.9 and v5.10-rc1 but it suddenly started
generating v5.9.0-rc5+ kernels.

The identified commit was 13a8f46d803 drm/ttm: move ghost object created.
(retyped - hope it is right).
But the diff to that last 'good' commit is massive.

So I don't know if that is anywhere near right.

David

> >
> > I'm adding Thomas Zimmermann to the cc, because he did that "drm/ast:
> > Program display mode in CRTC's atomic_enable" which looks relevant in
> > that it's right in that call-chain.
> >
> > Did some initialization perhaps get overlooked?
> >
> > And Dave and Daniel and the drm list cc'd as well..
> >
> > Full splat left quoted below for new people and list.
> >
> >  Linus
> >
> >> [   20.809891] WARNING: CPU: 0 PID: 973 at 
> >> drivers/gpu/drm/drm_gem_vram_helper.c:284
> drm_gem_vram_offset+0x35/0x40 [drm_vram_helper]
> 
> That line is at [1], which comes from
> 
>   46642a7d4d80 ("drm/vram-helper: don't use ttm bo->offset v4")
> 
> But the patch was merged in 5.9-rc1, so it's probably something else.
> 
> We've had a lot of TTM-related changes recently, so my best guess is
> that it's something in TTM with BO initialization.
> 
>  From some grepping, it looks like we have to call ttm_bo_mem_space() to
> fill mm_node (i.e., the pointer that causes the warning). But I cannot
> find where vram helpers do this. Maybe that's a good starting point.
> 
> I'm adding the TTM devs to cc.
> 
> Best regards
> Thomas
> 
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/drm_gem_vram_h
> elper.c?h=v5.10-rc4#n284
> 
> 
> >> [   20.821543] Modules linked in: nls_iso8859_1 dm_multipath scsi_dh_rdac 
> >> scsi_dh_emc scsi_dh_alua
> ipmi_ssif intel_powerclamp coretemp kvm_intel kvm joydev input_leds ipmi_si 
> intel_cstate ipmi_devintf
> ipmi_msghandler mac_hid sch_fq_codel parport_pc ppdev lp parport ip_tables 
> x_tables autofs4 btrfs
> blake2b_generic zstd_compress raid10 raid456 async_raid6_recov async_memcpy 
> async_pq async_xor
> async_tx libcrc32c xor raid6_pq raid1 raid0 multipath linear ast 
> drm_vram_helper drm_kms_helper
> syscopyarea sysfillrect sysimgblt fb_sys_fops cec drm_ttm_helper ttm 
> crct10dif_pclmul crc32_pclmul
> ghash_clmulni_intel gpio_ich drm aesni_intel hid_generic glue_helper 
> crypto_simd igb usbhid cryptd
> ahci i2c_i801 hid libahci i2c_smbus lpc_ich dca i2c_ismt i2c_algo_bit
> >> [   20.887477] CPU: 0 PID: 973 Comm: gnome-shell Not tainted 5.10.0-rc4+ 
> >> #78
> >> [   20.894274] Hardware name: Supermicro A1SAi/A1SRi, BIOS 1.1a 08/27/2015
> >> [   20.900896] RIP: 0010:drm_gem_vram_offset+0x35/0x40 [drm_vram_helper]
> >> [   20.907342] Code: 00 48 89 e5 85 c0 74 17 48 83 bf 78 01 00 00 00 74 18 
> >> 48 8b 87 80 01 00 00 5d
> 48 c1 e0 0c c3 0f 0b 48 c7 c0 ed ff ff ff 5d c3 <0f> 0b 31 c0 5d c3 0f 1f 44 
> 00 00 0f 1f 44 00 00 55
> 48 8b 87 18 06
> >> [   20.926100] RSP: 0018:9f59811d3a68 EFLAGS: 00010246
> >> [   20.931339] RAX: 0002 RBX: 8b46861e20c0 RCX: 
> >> c032d600
> >> [   20.938479] RDX: 8b468f47a000 RSI: 8b46861e2000 RDI: 
> >> 8b468f9acc00
> >> [   20.945622] RBP: 9f59811d3a68 R08: 0040 R09: 
> >> 8b46864ce288
> >> [   20.952769] R10:  R11: 0001 R12: 
> >> 8b468f47a000
> >> [   20.959915] R13:  R14:  R15: 
> >> 8b468ad2bf00
> >> [   20.967057] FS:  7f5b37ac5cc0() GS:8b49efc0() 
> >> knlGS:
> >> [   20.975149] CS:  0010 DS:  ES:  CR0: 80050033
> >> [   20.980904] CR2: 7f5b3d093f00 CR3: 000103438000 CR4: 
> >> 001006f0
> >> [   20.988047] Call Trace:
> >> [   20.990506]  ast_cursor_page_flip+0x22/0x100 [ast]
> >> [   20.995313]  ast_cursor_plane_helper_atomic_update+0x46/0x70 [ast]
> >> [   21.001524]  drm_atomic_helper_commit_planes+0xbd/0x220 [drm_kms_helper]
> >> [   21.008243]  drm_atomic_helper_commit_tail_rpm+0x3a/0x70 
> >> [drm_kms_helper]
> >> [   21.015062]  commit_tail+0x99/0x130 [drm_kms_helper]
> >> [   21.020050]  drm_atomic_helper_commit+0x123/0x150 [drm_kms_helper]
> >> [   21.026269]  drm_atomic_commit+0x4a/0x50 [drm]
> >> [   21.030737]  drm_atomic_helper_update_plane+0xe7/0x140 [drm_kms_he

[PATCH] drm/via: fix assignment in if condition

Fix check_patch.pl warning:
ERROR: do not use assignment in if condition
+   if ((HALCYON_HEADER2 == (cmd = *buf)) &&

ERROR: do not use assignment in if condition
+   if (HALCYON_HEADER2 == (cmd = *buf))

Signed-off-by: Bernard Zhao 
---
 drivers/gpu/drm/via/via_verifier.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/via/via_verifier.c 
b/drivers/gpu/drm/via/via_verifier.c
index 8d8135f424ef..3d6e3a70f318 100644
--- a/drivers/gpu/drm/via/via_verifier.c
+++ b/drivers/gpu/drm/via/via_verifier.c
@@ -1001,8 +1001,8 @@ via_verify_command_stream(const uint32_t * buf, unsigned 
int size,
state = via_check_vheader6(&buf, buf_end);
break;
case state_command:
-   if ((HALCYON_HEADER2 == (cmd = *buf)) &&
-   supported_3d)
+   cmd = *buf;
+   if ((cmd == HALCYON_HEADER2) && supported_3d)
state = state_header2;
else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
state = state_header1;
@@ -1064,7 +1064,8 @@ via_parse_command_stream(struct drm_device *dev, const 
uint32_t *buf,
state = via_parse_vheader6(dev_priv, &buf, buf_end);
break;
case state_command:
-   if (HALCYON_HEADER2 == (cmd = *buf))
+   cmd = *buf;
+   if (cmd == HALCYON_HEADER2)
state = state_header2;
else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
state = state_header1;
-- 
2.29.0

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Re: [PATCH v3 05/11] dt-bindings: phy: convert phy-mtk-ufs.txt to YAML schema

2020-11-19 Thread Stanley Chu

On Wed, 2020-11-18 at 16:21 +0800, Chunfeng Yun wrote:
> Convert phy-mtk-ufs.txt to YAML schema mediatek,ufs-phy.yaml
> 
> Cc: Stanley Chu 
> Signed-off-by: Chunfeng Yun 
> Reviewed-by: Rob Herring 

Reviewed-by: Stanley Chu 

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[PATCH 3/9] misc: xilinx-ai-engine: Implement AI engine cleanup sequence

When AI engine partition is released, that is if no one is using the AI
engine partition, by default, it will cleanup the partition by doing the
following:
* reset the columns
* reset the SHIMs
* clear data and program memory
* gate all the tiles

If user doesn't want the partition is reset when the partition is
released, user can set the control flag to indicate not to reset the
partition when the user requests the partition.

If partition the not to reset partition control flag is set, it will
not execute the above cleanup sequence when the partition is released.

Signed-off-by: Wendy Liang 
Reviewed-by: Hyun Kwon 
---
 drivers/misc/xilinx-ai-engine/Makefile |   3 +-
 drivers/misc/xilinx-ai-engine/ai-engine-aie.c  |  92 
 drivers/misc/xilinx-ai-engine/ai-engine-dev.c  |   2 +
 drivers/misc/xilinx-ai-engine/ai-engine-internal.h |  34 ++
 drivers/misc/xilinx-ai-engine/ai-engine-part.c |   7 +-
 drivers/misc/xilinx-ai-engine/ai-engine-reset.c| 121 +
 include/uapi/linux/xlnx-ai-engine.h|   6 +
 7 files changed, 259 insertions(+), 6 deletions(-)
 create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-reset.c

diff --git a/drivers/misc/xilinx-ai-engine/Makefile 
b/drivers/misc/xilinx-ai-engine/Makefile
index 7827a0a..39bec61 100644
--- a/drivers/misc/xilinx-ai-engine/Makefile
+++ b/drivers/misc/xilinx-ai-engine/Makefile
@@ -8,4 +8,5 @@ obj-$(CONFIG_XILINX_AIE)+= xilinx-aie.o
 xilinx-aie-$(CONFIG_XILINX_AIE) := ai-engine-aie.o \
   ai-engine-dev.o \
   ai-engine-part.o \
-  ai-engine-res.o
+  ai-engine-res.o \
+  ai-engine-reset.o
diff --git a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c 
b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
index 319260f..36127f0 100644
--- a/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
+++ b/drivers/misc/xilinx-ai-engine/ai-engine-aie.c
@@ -5,6 +5,9 @@
  * Copyright (C) 2020 Xilinx, Inc.
  */
 
+#include 
+#include 
+#include 
 #include 
 
 #include "ai-engine-internal.h"
@@ -24,9 +27,25 @@
 #define AIE_SHIMPL_L1INTR_MASK_A_REGOFF0x00035000U
 #define AIE_SHIMPL_L1INTR_BLOCK_NORTH_B_REGOFF 0x00035050U
 #define AIE_SHIMPL_CLKCNTR_REGOFF  0x00036040U
+#define AIE_SHIMPL_COLRESET_REGOFF 0x00036048U
 #define AIE_SHIMPL_RESET_REGOFF0x0003604cU
 #define AIE_TILE_CORE_CLKCNTR_REGOFF   0x00036040U
 
+/*
+ * Register masks
+ */
+#define AIE_SHIMPL_SHIMRST_MASK0x1U
+#define AIE_SHIMPL_COLRST_MASK 0x1U
+#define AIE_SHIMPL_CLKCNTR_COLBUF_MASK 0x1U
+
+/*
+ * AI engine SHIM reset ID.
+ * TODO: it should follow the Linux reset framework. The ID should be in the
+ * device tree. However, as versal resets is not ready, we hardcode it in the
+ * driver.
+ */
+#define VERSAL_PM_RST_AIE_SHIM_ID  0xc10405fU
+
 static const struct aie_tile_regs aie_kernel_regs[] = {
/* SHIM AXI MM Config */
{.attribute = AIE_TILE_TYPE_SHIMNOC << AIE_REGS_ATTR_TILE_TYPE_SHIFT,
@@ -49,6 +68,12 @@ static const struct aie_tile_regs aie_kernel_regs[] = {
 .soff = AIE_SHIMPL_L1INTR_MASK_A_REGOFF,
 .eoff = AIE_SHIMPL_L1INTR_BLOCK_NORTH_B_REGOFF,
},
+   /* SHIM column reset */
+   {.attribute = (AIE_TILE_TYPE_SHIMPL | AIE_TILE_TYPE_SHIMNOC) <<
+ AIE_REGS_ATTR_TILE_TYPE_SHIFT,
+.soff = AIE_SHIMPL_COLRESET_REGOFF,
+.eoff = AIE_SHIMPL_COLRESET_REGOFF,
+   },
/* SHIM reset Enable */
{.attribute = (AIE_TILE_TYPE_SHIMPL | AIE_TILE_TYPE_SHIMNOC) <<
  AIE_REGS_ATTR_TILE_TYPE_SHIFT,
@@ -68,6 +93,16 @@ static const struct aie_tile_regs aie_kernel_regs[] = {
},
 };
 
+static const struct aie_single_reg_field aie_col_rst = {
+   .mask = AIE_SHIMPL_COLRST_MASK,
+   .regoff = AIE_SHIMPL_COLRESET_REGOFF,
+};
+
+static const struct aie_single_reg_field aie_col_clkbuf = {
+   .mask = AIE_SHIMPL_CLKCNTR_COLBUF_MASK,
+   .regoff = AIE_SHIMPL_CLKCNTR_REGOFF,
+};
+
 static u32 aie_get_tile_type(struct aie_location *loc)
 {
if (loc->row)
@@ -79,8 +114,63 @@ static u32 aie_get_tile_type(struct aie_location *loc)
return AIE_TILE_TYPE_SHIMNOC;
 }
 
+/**
+ * aie_set_shim_reset() - Set AI engine SHIM reset
+ * @adev: AI engine device
+ * @range: range of AI engine tiles
+ * @assert: true to set reset, false to unset reset
+ */
+static void aie_set_shim_reset(struct aie_device *adev,
+  struct aie_range *range, bool assert)
+{
+   u32 c;
+   u32 val;
+   struct aie_location loc;
+
+   val = FIELD_PREP(AIE_SHIMPL_SHIMRST_MASK, (assert ? 1 : 0));
+   loc.row = 0;
+   for (c = range->start.col; c < range->start.col + range->size.col;
+c++) {
+

Re: [PATCH v2 0/6] drm/panel: mantix and st7703 fixes and additions

2020-11-19 Thread Linus Walleij

On Wed, Nov 18, 2020 at 9:29 AM Guido Günther  wrote:

> This adds new panel type to the mantix driver as found on the Librem 5 and
> fixes a glitch in the init sequence (affecting both panels). The fix is at the
> start of the series to make backporting simpler.
> It also adds a patch to make st7703 use dev_err_probe().
>
> changes from v1
> - as per review comments by Linus Walleij
>   - fix alphabetical ordering in 
> Documentation/devicetree/bindings/vendor-prefixes.yaml
> 
> https://lore.kernel.org/dri-devel/CACRpkdao_TMcpRsdK=7k5fnkjse0bqwk58iwu0xsxddndcf...@mail.gmail.com/
>   - add reviewed by to all except 5/6, thanks

The whole v2 looks fine to me, I'd give the devicetree
maintainers some slack to review the DT patches then I can
apply the whole series unless you have commit access yourself,
just tell me.

For all v2 patches:
Reviewed-by: Linus Walleij 

If you have time, please review my s6e63m0 series.
https://lore.kernel.org/dri-devel/20201117175621.870085-1-linus.wall...@linaro.org/
https://lore.kernel.org/dri-devel/20201117175621.870085-2-linus.wall...@linaro.org/
https://lore.kernel.org/dri-devel/20201117175621.870085-3-linus.wall...@linaro.org/

Yours,
Linus Walleij
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Re: next/master bisection: baseline.dmesg.emerg on meson-gxbb-p200

2020-11-19 Thread Guillaume Tucker

Please see the automated bisection report below about some kernel
errors on meson-gxbb-p200.

Reports aren't automatically sent to the public while we're
trialing new bisection features on kernelci.org, however this one
looks valid.

The bisection started with next-20201118 but the errors are still
present in next-20201119.  Details for this regression:

  https://kernelci.org/test/case/id/5fb6196bfd0127fd68d8d902/

The first error is:

  [   14.757489] Internal error: synchronous external abort: 96000210 [#1] 
PREEMPT SMP

Full log:

  
https://storage.kernelci.org/next/master/next-20201119/arm64/defconfig/gcc-8/lab-baylibre/baseline-meson-gxbb-p200.html#L410

Some other platforms are failing to boot starting with
next-20201118 but it's unclear whether that's due to the same
issue.  They might lead to a successful bisection which would
help clarify this.  All the baseline test results can be found
here:

  
https://kernelci.org/test/job/next/branch/master/kernel/next-20201119/plan/baseline/


Hope this helps.  Pleas let us know if you need some help to
reproduce the issue or try a fix.

Thanks,
Guillaume

On 19/11/2020 03:03, KernelCI bot wrote:
> * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
> * This automated bisection report was sent to you on the basis  *
> * that you may be involved with the breaking commit it has  *
> * found.  No manual investigation has been done to verify it,   *
> * and the root cause of the problem may be somewhere else.  *
> *   *
> * If you do send a fix, please include this trailer:*
> *   Reported-by: "kernelci.org bot"   *
> *   *
> * Hope this helps!  *
> * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
> 
> next/master bisection: baseline.dmesg.emerg on meson-gxbb-p200
> 
> Summary:
>   Start:  205292332779 Add linux-next specific files for 20201118
>   Plain log:  
> https://storage.kernelci.org/next/master/next-20201118/arm64/defconfig/gcc-8/lab-baylibre/baseline-meson-gxbb-p200.txt
>   HTML log:   
> https://storage.kernelci.org/next/master/next-20201118/arm64/defconfig/gcc-8/lab-baylibre/baseline-meson-gxbb-p200.html
>   Result: b33340e33acd drm/meson: dw-hdmi: Ensure that clocks are enabled 
> before touching the TOP registers
> 
> Checks:
>   revert: PASS
>   verify: PASS
> 
> Parameters:
>   Tree:   next
>   URL:
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
>   Branch: master
>   Target: meson-gxbb-p200
>   CPU arch:   arm64
>   Lab:lab-baylibre
>   Compiler:   gcc-8
>   Config: defconfig
>   Test case:  baseline.dmesg.emerg
> 
> Breaking commit found:
> 
> ---
> commit b33340e33acdfe5ca6a5aa1244709575ae1e0432
> Author: Marc Zyngier 
> Date:   Mon Nov 16 20:07:44 2020 +
> 
> drm/meson: dw-hdmi: Ensure that clocks are enabled before touching the 
> TOP registers
> 
> Removing the meson-dw-hdmi module and re-inserting it results in a hang
> as the driver writes to HDMITX_TOP_SW_RESET. Similar effects can be seen
> when booting with mainline u-boot and using the u-boot provided DT (which
> is highly desirable).
> 
> The reason for the hang seem to be that the clocks are not always
> enabled by the time we enter meson_dw_hdmi_init(). Moving this call
> *after* dw_hdmi_probe() ensures that the clocks are enabled.
> 
> Fixes: 1374b8375c2e ("drm/meson: dw_hdmi: add resume/suspend hooks")
> Signed-off-by: Marc Zyngier 
> Acked-by: Neil Armstrong 
> Signed-off-by: Neil Armstrong 
> Link: 
> https://patchwork.freedesktop.org/patch/msgid/20201116200744.495826-5-...@kernel.org
> 
> diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c 
> b/drivers/gpu/drm/meson/meson_dw_hdmi.c
> index 68826cf9993f..7f8eea494147 100644
> --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
> +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
> @@ -1073,8 +1073,6 @@ static int meson_dw_hdmi_bind(struct device *dev, 
> struct device *master,
>  
>   DRM_DEBUG_DRIVER("encoder initialized\n");
>  
> - meson_dw_hdmi_init(meson_dw_hdmi);
> -
>   /* Bridge / Connector */
>  
>   dw_plat_data->priv_data = meson_dw_hdmi;
> @@ -1097,6 +1095,8 @@ static int meson_dw_hdmi_bind(struct device *dev, 
> struct device *master,
>   if (IS_ERR(meson_dw_hdmi->hdmi))
>   return PTR_ERR(meson_dw_hdmi-

Re: [PATCH v3 6/7] drm/vc4: kms: Store the unassigned channel list in the state


Hi

Am 05.11.20 um 14:56 schrieb Maxime Ripard:

If a CRTC is enabled but not active, and that we're then doing a page
flip on another CRTC, drm_atomic_get_crtc_state will bring the first
CRTC state into the global state, and will make us wait for its vblank
as well, even though that might never occur.

Instead of creating the list of the free channels each time atomic_check
is called, and calling drm_atomic_get_crtc_state to retrieve the
allocated channels, let's create a private state object in the main
atomic state, and use it to store the available channels.

Since vc4 has a semaphore (with a value of 1, so a lock) in its commit
implementation to serialize all the commits, even the nonblocking ones, we
are free from the use-after-free race if two subsequent commits are not ran
in their submission order.

Fixes: 87ebcd42fb7b ("drm/vc4: crtc: Assign output to channel automatically")
Reviewed-by: Hoegeun Kwon 
Tested-by: Hoegeun Kwon 
Signed-off-by: Maxime Ripard 
---
  drivers/gpu/drm/vc4/vc4_drv.h |   1 +
  drivers/gpu/drm/vc4/vc4_kms.c | 124 +++---
  2 files changed, 100 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index bdbb9540d47d..014113823647 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -219,6 +219,7 @@ struct vc4_dev {
  
  	struct drm_modeset_lock ctm_state_lock;

struct drm_private_obj ctm_manager;
+   struct drm_private_obj hvs_channels;
struct drm_private_obj load_tracker;
  
  	/* List of vc4_debugfs_info_entry for adding to debugfs once

diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index 499c6914fce4..0a231ae500e5 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -37,6 +37,17 @@ static struct vc4_ctm_state *to_vc4_ctm_state(struct 
drm_private_state *priv)
return container_of(priv, struct vc4_ctm_state, base);
  }
  
+struct vc4_hvs_state {

+   struct drm_private_state base;
+   unsigned int unassigned_channels;
+};
+
+static struct vc4_hvs_state *
+to_vc4_hvs_state(struct drm_private_state *priv)
+{
+   return container_of(priv, struct vc4_hvs_state, base);
+}
+
  struct vc4_load_tracker_state {
struct drm_private_state base;
u64 hvs_load;
@@ -662,6 +673,70 @@ static int vc4_load_tracker_obj_init(struct vc4_dev *vc4)
return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, 
NULL);
  }
  
+static struct drm_private_state *

+vc4_hvs_channels_duplicate_state(struct drm_private_obj *obj)
+{
+   struct vc4_hvs_state *state;
+
+   state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
+   if (!state)
+   return NULL;
+
+   __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
+
+   return &state->base;
+}
+
+static void vc4_hvs_channels_destroy_state(struct drm_private_obj *obj,
+  struct drm_private_state *state)
+{
+   struct vc4_hvs_state *hvs_state;
+
+   hvs_state = to_vc4_hvs_state(state);
+   kfree(hvs_state);
+}
+
+static const struct drm_private_state_funcs vc4_hvs_state_funcs = {
+   .atomic_duplicate_state = vc4_hvs_channels_duplicate_state,
+   .atomic_destroy_state = vc4_hvs_channels_destroy_state,
+};
+
+static void vc4_hvs_channels_obj_fini(struct drm_device *dev, void *unused)
+{
+   struct vc4_dev *vc4 = to_vc4_dev(dev);
+
+   drm_atomic_private_obj_fini(&vc4->hvs_channels);
+}
+
+static int vc4_hvs_channels_obj_init(struct vc4_dev *vc4)
+{
+   struct vc4_hvs_state *state;
+
+   state = kzalloc(sizeof(*state), GFP_KERNEL);
+   if (!state)
+   return -ENOMEM;
+
+   state->unassigned_channels = GENMASK(HVS_NUM_CHANNELS - 1, 0);
+   drm_atomic_private_obj_init(&vc4->base, &vc4->hvs_channels,
+   &state->base,
+   &vc4_hvs_state_funcs);
+
+   return drmm_add_action_or_reset(&vc4->base, vc4_hvs_channels_obj_fini, 
NULL);
+}
+
+static struct vc4_hvs_state *
+vc4_hvs_get_global_state(struct drm_atomic_state *state)
+{
+   struct vc4_dev *vc4 = to_vc4_dev(state->dev);
+   struct drm_private_state *priv_state;
+
+   priv_state = drm_atomic_get_private_obj_state(state, 
&vc4->hvs_channels);
+   if (IS_ERR(priv_state))
+   return ERR_CAST(priv_state);
+
+   return to_vc4_hvs_state(priv_state);
+}
+
  /*
   * The BCM2711 HVS has up to 7 output connected to the pixelvalves and
   * the TXP (and therefore all the CRTCs found on that platform).
@@ -678,6 +753,14 @@ static int vc4_load_tracker_obj_init(struct vc4_dev *vc4)
   *   need to consider all the running CRTCs in the DRM device to assign
   *   a FIFO, not just the one in the state.
   *
+ * - To fix the above, we can't use drm_atomic_get_crtc_state on all
+ *   enabled CRTCs to pull their CRTC state into the global state, since

Re: [PATCH v3 7/7] drm/vc4: kms: Don't disable the muxing of an active CRTC


Hi

Am 05.11.20 um 14:56 schrieb Maxime Ripard:

The current HVS muxing code will consider the CRTCs in a given state to
setup their muxing in the HVS, and disable the other CRTCs muxes.

However, it's valid to only update a single CRTC with a state, and in this
situation we would mux out a CRTC that was enabled but left untouched by
the new state.

Fix this by setting a flag on the CRTC state when the muxing has been
changed, and only change the muxing configuration when that flag is there.

Fixes: 87ebcd42fb7b ("drm/vc4: crtc: Assign output to channel automatically")
Reviewed-by: Hoegeun Kwon 
Tested-by: Hoegeun Kwon 
Signed-off-by: Maxime Ripard 
---
  drivers/gpu/drm/vc4/vc4_drv.h |  1 +
  drivers/gpu/drm/vc4/vc4_kms.c | 82 ---
  2 files changed, 48 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 014113823647..325b53ff11b3 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -524,6 +524,7 @@ struct vc4_crtc_state {
struct drm_mm_node mm;
bool feed_txp;
bool txp_armed;
+   bool needs_muxing;


Maybe rather 'update_muxing'.

More generally, I'd separate fields that contain actual CRTC state, such 
assigned_channel, from those that only contain transitional state during 
update-commit, such as needs_muxing.



unsigned int assigned_channel;
  
  	struct {

diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index 0a231ae500e5..7ef164afa9e2 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -226,10 +226,7 @@ static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4,
  {
struct drm_crtc_state *crtc_state;
struct drm_crtc *crtc;
-   unsigned char dsp2_mux = 0;
-   unsigned char dsp3_mux = 3;
-   unsigned char dsp4_mux = 3;
-   unsigned char dsp5_mux = 3;
+   unsigned char mux;
unsigned int i;
u32 reg;
  
@@ -237,50 +234,59 @@ static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4,

struct vc4_crtc_state *vc4_state = 
to_vc4_crtc_state(crtc_state);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  
-		if (!crtc_state->active)

+   if (!vc4_state->needs_muxing)
continue;
  
  		switch (vc4_crtc->data->hvs_output) {

case 2:
-   dsp2_mux = (vc4_state->assigned_channel == 2) ? 0 : 1;
+   mux = (vc4_state->assigned_channel == 2) ? 0 : 1;
+   reg = HVS_READ(SCALER_DISPECTRL);
+   HVS_WRITE(SCALER_DISPECTRL,
+ (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) |
+ VC4_SET_FIELD(mux, 
SCALER_DISPECTRL_DSP2_MUX));
break;
  
  		case 3:

-   dsp3_mux = vc4_state->assigned_channel;
+   if (vc4_state->assigned_channel == 
VC4_HVS_CHANNEL_DISABLED)
+   mux = 3;
+   else
+   mux = vc4_state->assigned_channel;
+
+   reg = HVS_READ(SCALER_DISPCTRL);
+   HVS_WRITE(SCALER_DISPCTRL,
+ (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) |
+ VC4_SET_FIELD(mux, SCALER_DISPCTRL_DSP3_MUX));
break;
  
  		case 4:

-   dsp4_mux = vc4_state->assigned_channel;
+   if (vc4_state->assigned_channel == 
VC4_HVS_CHANNEL_DISABLED)
+   mux = 3;
+   else
+   mux = vc4_state->assigned_channel;
+
+   reg = HVS_READ(SCALER_DISPEOLN);
+   HVS_WRITE(SCALER_DISPEOLN,
+ (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) |
+ VC4_SET_FIELD(mux, SCALER_DISPEOLN_DSP4_MUX));
+
break;
  
  		case 5:

-   dsp5_mux = vc4_state->assigned_channel;
+   if (vc4_state->assigned_channel == 
VC4_HVS_CHANNEL_DISABLED)
+   mux = 3;
+   else
+   mux = vc4_state->assigned_channel;
+
+   reg = HVS_READ(SCALER_DISPDITHER);
+   HVS_WRITE(SCALER_DISPDITHER,
+ (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) |
+ VC4_SET_FIELD(mux, 
SCALER_DISPDITHER_DSP5_MUX));
break;
  
  		default:

break;
}
}
-
-   reg = HVS_READ(SCALER_DISPECTRL);
-   HVS_WRITE(SCALER_DISPECTRL,
- (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) |
- VC4_SET_FIELD(dsp2_mux, SCALER_DISPECTRL_DSP2_MUX));
-
-   reg = HVS_READ(SCALER_DISPCTR

Re: [PATCH v2 2/3] drm/vc4: hdmi: Disable Wifi Frequencies


Hi

Am 29.10.20 um 14:40 schrieb Maxime Ripard:

There's cross-talk on the RPi4 between the 2.4GHz channels used by the WiFi
chip and some resolutions, most notably 1440p at 60Hz.

In such a case, we can either reject entirely the mode, or lower slightly
the pixel frequency to remove the overlap. Let's go for the latter.

Signed-off-by: Maxime Ripard 

---

Changes from v1:
   - Change the name of the property
   - Test for a range instead of an exact frequency
---
  drivers/gpu/drm/vc4/vc4_hdmi.c | 21 +
  drivers/gpu/drm/vc4/vc4_hdmi.h |  8 
  2 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 506c12454086..0d72e519aec4 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -760,6 +760,9 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder 
*encoder)
  {
  }
  
+#define WIFI_2_4GHz_CH1_MIN_FREQ	24ULL

+#define WIFI_2_4GHz_CH1_MAX_FREQ   242200ULL
+
  static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
 struct drm_crtc_state *crtc_state,
 struct drm_connector_state *conn_state)
@@ -767,12 +770,27 @@ static int vc4_hdmi_encoder_atomic_check(struct 
drm_encoder *encoder,
struct drm_display_mode *mode = &crtc_state->adjusted_mode;
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
unsigned long long pixel_rate = mode->clock * 1000;
+   unsigned long long tmds_rate;
  
  	if (vc4_hdmi->variant->unsupported_odd_h_timings &&

((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
 (mode->hsync_end % 2) || (mode->htotal % 2)))
return -EINVAL;
  
+	/*

+* The 1440p@60 pixel rate is in the same range than the first
+* WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
+* bandwidth). Slightly lower the frequency to bring it out of
+* the WiFi range.
+*/
+   tmds_rate = pixel_rate * 10;
+   if (vc4_hdmi->disable_wifi_frequencies &&
+   (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
+tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
+   mode->clock = 238560;
+   pixel_rate = mode->clock * 1000;
+   }
+
if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
return -EINVAL;
  
@@ -1717,6 +1735,9 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)

vc4_hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
}
  
+	vc4_hdmi->disable_wifi_frequencies =

+   of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
+
pm_runtime_enable(dev);
  
  	drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index 6815e93b1a48..3843be830601 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -142,6 +142,14 @@ struct vc4_hdmi {
int hpd_gpio;
bool hpd_active_low;
  
+	/*

+* On some systems (like the RPi4), some modes are in the same
+* frequency range than the WiFi channels (1440p@60Hz for
+* example). Should we take evasive actions because that system
+* has a wifi adapter.


The final sentence sounds like a question. Maybe just write 'Take 
evasive actions if...'


Assuming that the display mode still works

Acked-by: Thomas Zimmermann 


+*/
+   bool disable_wifi_frequencies;
+
struct cec_adapter *cec_adap;
struct cec_msg cec_rx_msg;
bool cec_tx_ok;



--
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(HRB 36809, AG Nürnberg)
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Re: [PATCH] drm: document drm_mode_get_connector

2020-11-19 Thread Pekka Paalanen

On Wed, 18 Nov 2020 10:52:12 +
Simon Ser  wrote:

> Document how to perform a forced probe, and when should user-space do it.
> 
> Signed-off-by: Simon Ser 
> Cc: Daniel Vetter 
> Cc: Pekka Paalanen 
> ---
>  include/uapi/drm/drm_mode.h | 13 +
>  1 file changed, 13 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> index 5ad10ab2a577..09647b799f39 100644
> --- a/include/uapi/drm/drm_mode.h
> +++ b/include/uapi/drm/drm_mode.h
> @@ -368,6 +368,19 @@ enum drm_mode_subconnector {
>  #define DRM_MODE_CONNECTOR_WRITEBACK 18
>  #define DRM_MODE_CONNECTOR_SPI   19
>  
> +/**
> + * struct drm_mode_get_connector - get connector metadata
> + *
> + * If the @count_modes field is set to zero, the kernel will perform a forced
> + * probe on the connector to refresh the connector status, modes and EDID.
> + * A forced-probe can be slow and the ioctl will block.
> + *

Hi,

as I have no prior knowledge at all about how struct
drm_mode_get_connector works, the above paragraph only confuses me.
count_modes sounds totally unrelated to probing, and what does that
even do in this struct at all, how does one use this thing. I only know
the libdrm API for this. So I can't ack this bit.

> + * User-space shouldn't need to force-probe connectors in general: the kernel
> + * will automatically take care of probing connectors that don't support
> + * hot-plug detection when appropriate. However, user-space may force-probe
> + * connectors on user request (e.g. clicking a "Scan connectors" button, or
> + * opening a UI to manage screens).

This paragraph is good and clear to me.

> + */
>  struct drm_mode_get_connector {
>  
>   __u64 encoders_ptr;


Thanks,
pq


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Re: [PATCH] drm/ttm: fix DMA32 handling in the global page pool

2020-11-19 Thread Christian König


Ping, can I get an rb or at least Acked-by for this?

Thanks in advance,
Christian.

Am 17.11.20 um 16:53 schrieb Christian König:

When we have mixed DMA32 and non DMA32 device in one system
it could otherwise happen that the DMA32 device gets pages
it can't work with.

Signed-off-by: Christian König 
---
  drivers/gpu/drm/ttm/ttm_pool.c | 22 ++
  1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c
index 1b96780b4989..5455b2044759 100644
--- a/drivers/gpu/drm/ttm/ttm_pool.c
+++ b/drivers/gpu/drm/ttm/ttm_pool.c
@@ -63,6 +63,9 @@ static atomic_long_t allocated_pages;
  static struct ttm_pool_type global_write_combined[MAX_ORDER];
  static struct ttm_pool_type global_uncached[MAX_ORDER];
  
+static struct ttm_pool_type global_dma32_write_combined[MAX_ORDER];

+static struct ttm_pool_type global_dma32_uncached[MAX_ORDER];
+
  static spinlock_t shrinker_lock;
  static struct list_head shrinker_list;
  static struct shrinker mm_shrinker;
@@ -290,8 +293,14 @@ static struct ttm_pool_type *ttm_pool_select_type(struct 
ttm_pool *pool,
  #ifdef CONFIG_X86
switch (caching) {
case ttm_write_combined:
+   if (pool->use_dma32)
+   return &global_dma32_write_combined[order];
+
return &global_write_combined[order];
case ttm_uncached:
+   if (pool->use_dma32)
+   return &global_dma32_uncached[order];
+
return &global_uncached[order];
default:
break;
@@ -570,6 +579,11 @@ int ttm_pool_debugfs(struct ttm_pool *pool, struct 
seq_file *m)
seq_puts(m, "uc\t:");
ttm_pool_debugfs_orders(global_uncached, m);
  
+	seq_puts(m, "wc 32\t:");

+   ttm_pool_debugfs_orders(global_dma32_write_combined, m);
+   seq_puts(m, "uc 32\t:");
+   ttm_pool_debugfs_orders(global_dma32_uncached, m);
+
for (i = 0; i < TTM_NUM_CACHING_TYPES; ++i) {
seq_puts(m, "DMA ");
switch (i) {
@@ -640,6 +654,11 @@ int ttm_pool_mgr_init(unsigned long num_pages)
ttm_pool_type_init(&global_write_combined[i], NULL,
   ttm_write_combined, i);
ttm_pool_type_init(&global_uncached[i], NULL, ttm_uncached, i);
+
+   ttm_pool_type_init(&global_dma32_write_combined[i], NULL,
+  ttm_write_combined, i);
+   ttm_pool_type_init(&global_dma32_uncached[i], NULL,
+  ttm_uncached, i);
}
  
  	mm_shrinker.count_objects = ttm_pool_shrinker_count;

@@ -660,6 +679,9 @@ void ttm_pool_mgr_fini(void)
for (i = 0; i < MAX_ORDER; ++i) {
ttm_pool_type_fini(&global_write_combined[i]);
ttm_pool_type_fini(&global_uncached[i]);
+
+   ttm_pool_type_fini(&global_dma32_write_combined[i]);
+   ttm_pool_type_fini(&global_dma32_uncached[i]);
}
  
  	unregister_shrinker(&mm_shrinker);


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Re: [PATCH 3/8] drm/vc4: kms: Move HVS state helpers around


I'd merge this into the patch that introduces the function.

Am 13.11.20 um 16:29 schrieb Maxime Ripard:

We're going to use those helpers in functions higher in that file, let's
move it around.

Signed-off-by: Maxime Ripard 
---
  drivers/gpu/drm/vc4/vc4_kms.c | 26 +-
  1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index 7ef164afa9e2..d6712924681e 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -182,6 +182,19 @@ vc4_ctm_commit(struct vc4_dev *vc4, struct 
drm_atomic_state *state)
  VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO));
  }
  
+static struct vc4_hvs_state *

+vc4_hvs_get_global_state(struct drm_atomic_state *state)
+{
+   struct vc4_dev *vc4 = to_vc4_dev(state->dev);
+   struct drm_private_state *priv_state;
+
+   priv_state = drm_atomic_get_private_obj_state(state, 
&vc4->hvs_channels);
+   if (IS_ERR(priv_state))
+   return ERR_CAST(priv_state);
+
+   return to_vc4_hvs_state(priv_state);
+}
+
  static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4,
 struct drm_atomic_state *state)
  {
@@ -730,19 +743,6 @@ static int vc4_hvs_channels_obj_init(struct vc4_dev *vc4)
return drmm_add_action_or_reset(&vc4->base, vc4_hvs_channels_obj_fini, 
NULL);
  }
  
-static struct vc4_hvs_state *

-vc4_hvs_get_global_state(struct drm_atomic_state *state)
-{
-   struct vc4_dev *vc4 = to_vc4_dev(state->dev);
-   struct drm_private_state *priv_state;
-
-   priv_state = drm_atomic_get_private_obj_state(state, 
&vc4->hvs_channels);
-   if (IS_ERR(priv_state))
-   return ERR_CAST(priv_state);
-
-   return to_vc4_hvs_state(priv_state);
-}
-
  /*
   * The BCM2711 HVS has up to 7 output connected to the pixelvalves and
   * the TXP (and therefore all the CRTCs found on that platform).



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Re: [PATCH 4/8] drm/vc4: kms: Simplify a bit the private obj state hooks


Maybe merge this into the commit that introduces the functionality.

Am 13.11.20 um 16:29 schrieb Maxime Ripard:

Some fields that we're going to add cannot be just copied over to the
new state, and thus kmemdup is a bit unnecessary. Let's move to kzalloc
instead, and clean it up in the process.

Signed-off-by: Maxime Ripard 
---
  drivers/gpu/drm/vc4/vc4_kms.c | 8 +---
  1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index d6712924681e..3d0065df10f9 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -695,23 +695,25 @@ static int vc4_load_tracker_obj_init(struct vc4_dev *vc4)
  static struct drm_private_state *
  vc4_hvs_channels_duplicate_state(struct drm_private_obj *obj)
  {
+   struct vc4_hvs_state *old_state = to_vc4_hvs_state(obj->state);
struct vc4_hvs_state *state;
  
-	state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);

+   state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return NULL;
  
  	__drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
  
+	state->unassigned_channels = old_state->unassigned_channels;

+
return &state->base;
  }
  
  static void vc4_hvs_channels_destroy_state(struct drm_private_obj *obj,

   struct drm_private_state *state)
  {
-   struct vc4_hvs_state *hvs_state;
+   struct vc4_hvs_state *hvs_state = to_vc4_hvs_state(state);
  
-	hvs_state = to_vc4_hvs_state(state);

kfree(hvs_state);
  }
  



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[PATCH 0/8] drm/imx: Introduce i.MX8qxp DPU DRM

Hi,


This patch set introduces i.MX8qxp Display Processing Unit(DPU) DRM support.

DPU is comprised of a blit engine for 2D graphics, a display controller
and a command sequencer.  Outside of DPU, optional prefetch engines can
fetch data from memory prior to some DPU fetchunits of blit engine and
display controller.  The pre-fetchers support linear formats and Vivante
GPU tile formats.

Reference manual can be found at:
https://www.nxp.com/webapp/Download?colCode=IMX8DQXPRM


This patch set adds kernel modesetting support for the display controller part.
It supports two CRTCs per display controller, several planes, prefetch
engines and some properties of CRTC and plane.  Currently, the registers of
the controller is accessed without command sequencer involved, instead just by
using CPU.  DRM connectors would be created from the DPU KMS driver.


If people want to try this series, clock patches can be found at:
https://www.spinics.net/lists/arm-kernel/msg856137.html

and, power domain patches at:
https://www.spinics.net/lists/arm-kernel/msg856097.html


I will send other patch sets to add downstream bridges(embedded in i.MX8qxp)
to support LVDS displays.

A brief look at the pipe:
prefetch eng -> DPU -> pixel combiner -> pixel link -> pixel to DPI(pxl2dpi) ->
LVDS display bridge(LDB)


Patch 1 ~ 3 add dt-bindings for DPU and prefetch engines.
Patch 4 is a minor improvement of a macro to suppress warning as the KMS driver
uses it.
Patch 5 introduces the DPU DRM support.
Patch 6 updates MAINTAINERS.
Patch 7 & 8 add DPU and prefetch engines support in the device tree of
i.MX8qxp MEK platform.


Welcome comments, thanks.


Liu Ying (8):
  dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding
  dt-bindings: display: imx: Add i.MX8qxp/qm PRG binding
  dt-bindings: display: imx: Add i.MX8qxp/qm DPR channel binding
  drm/atomic: Avoid unused-but-set-variable warning on
for_each_old_plane_in_state
  drm/imx: Introduce i.MX8qxp DPU DRM
  MAINTAINERS: add maintainer for i.MX8qxp DPU DRM driver
  arm64: imx8qxp:dtsi: Introduce DC0 subsystem
  arm64: dts: imx8qxp-mek: Enable DPU and it's prefetch engines

 .../bindings/display/imx/fsl,imx8qxp-dprc.yaml |  87 ++
 .../bindings/display/imx/fsl,imx8qxp-dpu.yaml  | 358 
 .../bindings/display/imx/fsl,imx8qxp-prg.yaml  |  60 ++
 MAINTAINERS|   9 +
 arch/arm64/boot/dts/freescale/imx8qxp-mek.dts  |  64 ++
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 313 +++
 drivers/gpu/drm/imx/Kconfig|   1 +
 drivers/gpu/drm/imx/Makefile   |   1 +
 drivers/gpu/drm/imx/dpu/Kconfig|  10 +
 drivers/gpu/drm/imx/dpu/Makefile   |  10 +
 drivers/gpu/drm/imx/dpu/dpu-constframe.c   | 170 
 drivers/gpu/drm/imx/dpu/dpu-core.c | 880 
 drivers/gpu/drm/imx/dpu/dpu-crtc.c | 926 +
 drivers/gpu/drm/imx/dpu/dpu-crtc.h |  62 ++
 drivers/gpu/drm/imx/dpu/dpu-disengcfg.c| 114 +++
 drivers/gpu/drm/imx/dpu/dpu-dprc.c | 721 
 drivers/gpu/drm/imx/dpu/dpu-dprc.h |  40 +
 drivers/gpu/drm/imx/dpu/dpu-drv.c  | 296 +++
 drivers/gpu/drm/imx/dpu/dpu-drv.h  |  28 +
 drivers/gpu/drm/imx/dpu/dpu-extdst.c   | 296 +++
 drivers/gpu/drm/imx/dpu/dpu-fetchdecode.c  | 291 +++
 drivers/gpu/drm/imx/dpu/dpu-fetcheco.c | 221 +
 drivers/gpu/drm/imx/dpu/dpu-fetchlayer.c   | 151 
 drivers/gpu/drm/imx/dpu/dpu-fetchunit.c| 609 ++
 drivers/gpu/drm/imx/dpu/dpu-fetchunit.h| 191 +
 drivers/gpu/drm/imx/dpu/dpu-fetchwarp.c| 247 ++
 drivers/gpu/drm/imx/dpu/dpu-framegen.c | 392 +
 drivers/gpu/drm/imx/dpu/dpu-gammacor.c | 220 +
 drivers/gpu/drm/imx/dpu/dpu-hscaler.c  | 272 ++
 drivers/gpu/drm/imx/dpu/dpu-kms.c  | 543 
 drivers/gpu/drm/imx/dpu/dpu-kms.h  |  23 +
 drivers/gpu/drm/imx/dpu/dpu-layerblend.c   | 345 
 drivers/gpu/drm/imx/dpu/dpu-plane.c| 703 
 drivers/gpu/drm/imx/dpu/dpu-plane.h|  56 ++
 drivers/gpu/drm/imx/dpu/dpu-prg.c  | 389 +
 drivers/gpu/drm/imx/dpu/dpu-prg.h  |  45 +
 drivers/gpu/drm/imx/dpu/dpu-prv.h  | 203 +
 drivers/gpu/drm/imx/dpu/dpu-tcon.c | 249 ++
 drivers/gpu/drm/imx/dpu/dpu-vscaler.c  | 305 +++
 drivers/gpu/drm/imx/dpu/dpu.h  | 389 +
 include/drm/drm_atomic.h   |   4 +-
 41 files changed, 10293 insertions(+), 1 deletion(-)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
 create mode 100644 
Documentation/devicetree/bindings/

[PATCH 1/8] dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding

This patch adds bindings for i.MX8qxp/qm Display Processing Unit.

Signed-off-by: Liu Ying 
---
 .../bindings/display/imx/fsl,imx8qxp-dpu.yaml  | 358 +
 1 file changed, 358 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml

diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml 
b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml
new file mode 100644
index ..2c6b029
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml
@@ -0,0 +1,358 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Display Processing Unit
+
+maintainers:
+  - Liu Ying 
+
+description: |
+  The Freescale i.MX8qm/qxp Display Processing Unit(DPU) is comprised of two
+  main components that include a blit engine for 2D graphics accelerations
+  and a display controller for display output processing, as well as a command
+  sequencer.
+
+properties:
+  compatible:
+oneOf:
+  - const: fsl,imx8qxp-dpu
+  - const: fsl,imx8qm-dpu
+
+  reg:
+maxItems: 1
+
+  interrupts:
+items:
+ - description: store9 shadow load interrupt   (blit engine)
+ - description: store9 frame complete interrupt(blit engine)
+ - description: store9 sequence complete interrupt (blit engine)
+ - description: extdst0 shadow load interrupt   (display controller, 
content stream 0)
+ - description: extdst0 frame complete interrupt(display controller, 
content stream 0)
+ - description: extdst0 sequence complete interrupt (display controller, 
content stream 0)
+ - description: extdst4 shadow load interrupt   (display controller, 
safety stream 0)
+ - description: extdst4 frame complete interrupt(display controller, 
safety stream 0)
+ - description: extdst4 sequence complete interrupt (display controller, 
safety stream 0)
+ - description: extdst1 shadow load interrupt   (display controller, 
content stream 1)
+ - description: extdst1 frame complete interrupt(display controller, 
content stream 1)
+ - description: extdst1 sequence complete interrupt (display controller, 
content stream 1)
+ - description: extdst5 shadow load interrupt   (display controller, 
safety stream 1)
+ - description: extdst5 frame complete interrupt(display controller, 
safety stream 1)
+ - description: extdst5 sequence complete interrupt (display controller, 
safety stream 1)
+ - description: disengcfg0 shadow load interrupt   (display 
controller, display stream 0)
+ - description: disengcfg0 frame complete interrupt(display 
controller, display stream 0)
+ - description: disengcfg0 sequence complete interrupt (display 
controller, display stream 0)
+ - description: framegen0 programmable interrupt0 (display controller, 
display stream 0)
+ - description: framegen0 programmable interrupt1 (display controller, 
display stream 0)
+ - description: framegen0 programmable interrupt2 (display controller, 
display stream 0)
+ - description: framegen0 programmable interrupt3 (display controller, 
display stream 0)
+ - description: signature0 shadow load interrupt   (display 
controller, display stream 0)
+ - description: signature0 measurement valid interrupt (display 
controller, display stream 0)
+ - description: signature0 error condition interrupt   (display 
controller, display stream 0)
+ - description: disengcfg1 shadow load interrupt   (display 
controller, display stream 1)
+ - description: disengcfg1 frame complete interrupt(display 
controller, display stream 1)
+ - description: disengcfg1 sequence complete interrupt (display 
controller, display stream 1)
+ - description: framegen1 programmable interrupt0 (display controller, 
display stream 1)
+ - description: framegen1 programmable interrupt1 (display controller, 
display stream 1)
+ - description: framegen1 programmable interrupt2 (display controller, 
display stream 1)
+ - description: framegen1 programmable interrupt3 (display controller, 
display stream 1)
+ - description: signature1 shadow load interrupt   (display 
controller, display stream 1)
+ - description: signature1 measurement valid interrupt (display 
controller, display stream 1)
+ - description: signature1 error condition interrupt   (display 
controller, display stream 1)
+ - description: command sequencer error condition interrupt (command 
sequencer)
+ - description: common control software interrupt0 (common control)
+ - description: common control software interrupt1 (common control)
+ - description: common control software interrupt2 (common control)
+ - description: common control software interr

[PATCH 2/8] dt-bindings: display: imx: Add i.MX8qxp/qm PRG binding

This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Gasket.

Signed-off-by: Liu Ying 
---
 .../bindings/display/imx/fsl,imx8qxp-prg.yaml  | 60 ++
 1 file changed, 60 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml

diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml 
b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml
new file mode 100644
index ..d043f2e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-prg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Display Prefetch Resolve Gasket
+
+maintainers:
+  - Liu Ying 
+
+description: |
+  The i.MX8qm/qxp Prefetch Resolve Gasket (PRG) is a gasket interface between
+  RTRAM controller and Display Controller.  The main function is to convert
+  the AXI interface to the RTRAM interface, which includes re-mapping the
+  ARADDR to a RTRAM address.
+
+properties:
+  compatible:
+oneOf:
+  - const: fsl,imx8qxp-prg
+  - const: fsl,imx8qm-prg
+
+  reg:
+maxItems: 1
+
+  clocks:
+items:
+  - description: rtram clock
+  - description: apb clock
+
+  clock-names:
+items:
+  - const: rtram
+  - const: apb
+
+  power-domains:
+maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - power-domains
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+#include 
+prg@5604 {
+compatible = "fsl,imx8qxp-prg";
+reg = <0x5604 0x1>;
+clocks = <&dc0_lpcg IMX_DC0_LPCG_PRG0_RTRAM_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_PRG0_APB_CLK>;
+clock-names = "rtram", "apb";
+power-domains = <&pd IMX_SC_R_DC_0>;
+};
-- 
2.7.4

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[PATCH 3/8] dt-bindings: display: imx: Add i.MX8qxp/qm DPR channel binding

This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Channel.

Signed-off-by: Liu Ying 
---
 .../bindings/display/imx/fsl,imx8qxp-dprc.yaml | 87 ++
 1 file changed, 87 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml

diff --git 
a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml 
b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
new file mode 100644
index ..2827dbd
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dprc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Display Prefetch Resolve Channel
+
+maintainers:
+  - Liu Ying 
+
+description: |
+  The i.MX8qm/qxp Display Prefetch Resolve Channel(DPRC) is an engine which
+  fetches display data before the display pipeline needs the data to drive
+  pixels in the active display region.  This data is transformed, or resolved,
+  from a variety of tiled buffer formats into linear format, if needed.
+  The DPR works with a double bank memory structure.  This memory structure is
+  implemented in the Resolve Tile Memory(RTRAM) and the banks are referred to
+  as A and B.  Each bank is either 4 or 8 lines high depending on the source
+  frame buffer format.
+
+properties:
+  compatible:
+oneOf:
+  - const: fsl,imx8qxp-dpr-channel
+  - const: fsl,imx8qm-dpr-channel
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+items:
+  - description: apb clock
+  - description: b clock
+  - description: rtram clock
+
+  clock-names:
+items:
+  - const: apb
+  - const: b
+  - const: rtram
+
+  fsl,sc-resource:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: The SCU resource ID associated with this DPRC instance.
+
+  fsl,prgs:
+$ref: /schemas/types.yaml#/definitions/phandle-array
+description: |
+  List of phandle which points to Prefetch Resolve Gaskets(PRGs)
+  associated with this DPRC instance.
+
+  power-domains:
+maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - fsl,sc-resource
+  - fsl,prgs
+  - power-domains
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+#include 
+#include 
+dpr-channel@5610 {
+compatible = "fsl,imx8qxp-dpr-channel";
+reg = <0x5610 0x1>;
+interrupts = ;
+clocks = <&dc0_lpcg IMX_DC0_LPCG_DPR1_APB_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_DPR1_B_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_RTRAM1_CLK>;
+clock-names = "apb", "b", "rtram";
+fsl,sc-resource = ;
+fsl,prgs = <&dc0_prg4>, <&dc0_prg5>;
+power-domains = <&pd IMX_SC_R_DC_0>;
+};
-- 
2.7.4

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[PATCH 4/8] drm/atomic: Avoid unused-but-set-variable warning on for_each_old_plane_in_state

Artifically use 'plane' and 'old_plane_state' to avoid 'not used' warning.
The precedent has already been set by other macros in the same file.

Signed-off-by: Liu Ying 
---
 include/drm/drm_atomic.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
index 54e051a..9da1e35a3 100644
--- a/include/drm/drm_atomic.h
+++ b/include/drm/drm_atomic.h
@@ -888,7 +888,9 @@ void drm_state_dump(struct drm_device *dev, struct 
drm_printer *p);
 (__i)++)   \
for_each_if ((__state)->planes[__i].ptr &&  \
 ((plane) = (__state)->planes[__i].ptr, \
- (old_plane_state) = 
(__state)->planes[__i].old_state, 1))
+ (void)(plane) /* Only to avoid 
unused-but-set-variable warning */, \
+ (old_plane_state) = 
(__state)->planes[__i].old_state, \
+ (void)(old_plane_state) /* Only to avoid 
unused-but-set-variable warning */, 1))
 /**
  * for_each_new_plane_in_state - iterate over all planes in an atomic update
  * @__state: &struct drm_atomic_state pointer
-- 
2.7.4

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[PATCH 6/8] MAINTAINERS: add maintainer for i.MX8qxp DPU DRM driver

Add myself as the maintainer of the i.MX8qxp DPU DRM driver.

Signed-off-by: Liu Ying 
---
 MAINTAINERS | 9 +
 1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 970d9ce..dee4586 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5834,6 +5834,15 @@ F:   Documentation/devicetree/bindings/display/imx/
 F: drivers/gpu/drm/imx/
 F: drivers/gpu/ipu-v3/
 
+DRM DRIVERS FOR FREESCALE i.MX8QXP
+M: Liu Ying 
+L: dri-devel@lists.freedesktop.org
+S: Maintained
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml
+F: Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml
+F: drivers/gpu/drm/imx/dpu/
+
 DRM DRIVERS FOR GMA500 (Poulsbo, Moorestown and derivative chipsets)
 M: Patrik Jakobsson 
 L: dri-devel@lists.freedesktop.org
-- 
2.7.4

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[PATCH 7/8] arm64: imx8qxp:dtsi: Introduce DC0 subsystem

This patch adds basic i.MX8qxp DC0 subsystem support, which includes
the irqsteer, LPCG clock controller, Display Processing Unit(DPU) and
it's prefetch engines - Prefetch Resolve Gaskets(PRG) and Display Prefetch
Resolve Channels(DPRC).

Note that the clocks are still referenced in the legacy way instead of
the new "two cells" binding way.  So, prone to update as soon as the SoC
device tree is converted to follow the new way.

Signed-off-by: Liu Ying 
---
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 313 +
 1 file changed, 313 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi 
b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index e46faac..062c294 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -21,6 +21,7 @@
aliases {
ethernet0 = &fec1;
ethernet1 = &fec2;
+   dpu0 = &dpu1;
gpio0 = &lsio_gpio0;
gpio1 = &lsio_gpio1;
gpio2 = &lsio_gpio2;
@@ -223,6 +224,318 @@
clock-output-names = "xtal_24MHz";
};
 
+   dc0_subsys: bus@5600 {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0x5600 0x0 0x5600 0x100>;
+
+   dc0_irqsteer: irqsteer@5600 {
+   compatible = "fsl,imx-irqsteer";
+   reg = <0x5600 0x1>;
+   interrupt-controller;
+   interrupt-parent = <&gic>;
+   #interrupt-cells = <1>;
+   interrupts = ,
+,
+,
+,
+,
+,
+,
+;
+   clocks = <&dc0_lpcg IMX_DC0_LPCG_LIS_IPG_CLK>;
+   clock-names = "ipg";
+   fsl,channel = <0>;
+   fsl,num-irqs = <512>;
+   power-domains = <&pd IMX_SC_R_DC_0>;
+   };
+
+   dc0_lpcg: clock-controller@5601 {
+   compatible = "fsl,imx8qxp-lpcg-dc";
+   reg = <0x5601 0x1>;
+   #clock-cells = <1>;
+   };
+
+   dc0_prg1: prg@5604 {
+   compatible = "fsl,imx8qxp-prg";
+   reg = <0x5604 0x1>;
+   clocks = <&dc0_lpcg IMX_DC0_LPCG_PRG0_RTRAM_CLK>,
+<&dc0_lpcg IMX_DC0_LPCG_PRG0_APB_CLK>;
+   clock-names = "rtram", "apb";
+   power-domains = <&pd IMX_SC_R_DC_0>;
+   status = "disabled";
+   };
+
+   dc0_prg2: prg@5605 {
+   compatible = "fsl,imx8qxp-prg";
+   reg = <0x5605 0x1>;
+   clocks = <&dc0_lpcg IMX_DC0_LPCG_PRG1_RTRAM_CLK>,
+<&dc0_lpcg IMX_DC0_LPCG_PRG1_APB_CLK>;
+   clock-names = "rtram", "apb";
+   power-domains = <&pd IMX_SC_R_DC_0>;
+   status = "disabled";
+   };
+
+   dc0_prg3: prg@5606 {
+   compatible = "fsl,imx8qxp-prg";
+   reg = <0x5606 0x1>;
+   clocks = <&dc0_lpcg IMX_DC0_LPCG_PRG2_RTRAM_CLK>,
+<&dc0_lpcg IMX_DC0_LPCG_PRG2_APB_CLK>;
+   clock-names = "rtram", "apb";
+   power-domains = <&pd IMX_SC_R_DC_0>;
+   status = "disabled";
+   };
+
+   dc0_prg4: prg@5607 {
+   compatible = "fsl,imx8qxp-prg";
+   reg = <0x5607 0x1>;
+   clocks = <&dc0_lpcg IMX_DC0_LPCG_PRG3_RTRAM_CLK>,
+<&dc0_lpcg IMX_DC0_LPCG_PRG3_APB_CLK>;
+   clock-names = "rtram", "apb";
+   power-domains = <&pd IMX_SC_R_DC_0>;
+   status = "disabled";
+   };
+
+   dc0_prg5: prg@5608 {
+   compatible = "fsl,imx8qxp-prg";
+   reg = <0x5608 0x1>;
+   clocks = <&dc0_lpcg IMX_DC0_LPCG_PRG4_RTRAM_CLK>,
+<&dc0_lpcg IMX_DC0_LPCG_PRG4_APB_CLK>;
+   clock-names = "rtram", "apb";
+   power-domains = <&pd IMX_SC_R_DC_0>;
+   status = "disabled";
+   };
+
+   dc0_prg6: prg@5609 {
+   compatible = "fsl,imx8qxp-prg";
+   reg = <

[PATCH 8/8] arm64: dts: imx8qxp-mek: Enable DPU and it's prefetch engines

This patch enables DPU and it's prefetch engines for
the i.MX8qxp MEK platform.

Signed-off-by: Liu Ying 
---
 arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 64 +++
 1 file changed, 64 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts 
b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 46437d3..1ddfa5b 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -30,6 +30,70 @@
};
 };
 
+&dc0_prg1 {
+   status = "okay";
+};
+
+&dc0_prg2 {
+   status = "okay";
+};
+
+&dc0_prg3 {
+   status = "okay";
+};
+
+&dc0_prg4 {
+   status = "okay";
+};
+
+&dc0_prg5 {
+   status = "okay";
+};
+
+&dc0_prg6 {
+   status = "okay";
+};
+
+&dc0_prg7 {
+   status = "okay";
+};
+
+&dc0_prg8 {
+   status = "okay";
+};
+
+&dc0_prg9 {
+   status = "okay";
+};
+
+&dc0_dpr1_channel1 {
+   status = "okay";
+};
+
+&dc0_dpr1_channel2 {
+   status = "okay";
+};
+
+&dc0_dpr1_channel3 {
+   status = "okay";
+};
+
+&dc0_dpr2_channel1 {
+   status = "okay";
+};
+
+&dc0_dpr2_channel2 {
+   status = "okay";
+};
+
+&dc0_dpr2_channel3 {
+   status = "okay";
+};
+
+&dpu1 {
+   status = "okay";
+};
+
 &adma_dsp {
status = "okay";
 };
-- 
2.7.4

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Re: [PATCH 5/8] drm/vc4: Simplify a bit the global atomic_check




Am 13.11.20 um 16:29 schrieb Maxime Ripard:

When we can't allocate a new channel, we can simply return instead of
having to handle both cases, and that simplifies a bit the code.

Signed-off-by: Maxime Ripard 


Reviewed-by: Thomas Zimmermann 


---
  drivers/gpu/drm/vc4/vc4_kms.c | 13 ++---
  1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index 3d0065df10f9..3034a5a6637e 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -794,6 +794,7 @@ static int vc4_pv_muxing_atomic_check(struct drm_device 
*dev,
to_vc4_crtc_state(new_crtc_state);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
unsigned int matching_channels;
+   unsigned int channel;
  
  		/* Nothing to do here, let's skip it */

if ((old_crtc_state->enable && new_crtc_state->enable) ||
@@ -837,14 +838,12 @@ static int vc4_pv_muxing_atomic_check(struct drm_device 
*dev,
 * but it works so far.
 */
matching_channels = hvs_state->unassigned_channels & 
vc4_crtc->data->hvs_available_channels;
-   if (matching_channels) {
-   unsigned int channel = ffs(matching_channels) - 1;
-
-   new_vc4_crtc_state->assigned_channel = channel;
-   hvs_state->unassigned_channels &= ~BIT(channel);
-   } else {
+   if (!matching_channels)
return -EINVAL;
-   }
+
+   channel = ffs(matching_channels) - 1;
+   new_vc4_crtc_state->assigned_channel = channel;
+   hvs_state->unassigned_channels &= ~BIT(channel);
}
  
  	return 0;




--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Felix Imendörffer


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Re: [PATCH 1/8] drm: Introduce an atomic_commit_setup function