Re: [PATCH v5 3/3] xen: add helpers to allocate unpopulated memory
On 03.09.20 18:38, Roger Pau Monné wrote:
On Thu, Sep 03, 2020 at 05:30:07PM +0200, Jürgen Groß wrote:
On 01.09.20 10:33, Roger Pau Monne wrote:
To be used in order to create foreign mappings. This is based on the
ZONE_DEVICE facility which is used by persistent memory devices in
order to create struct pages and kernel virtual mappings for the IOMEM
areas of such devices. Note that on kernels without support for
ZONE_DEVICE Xen will fallback to use ballooned pages in order to
create foreign mappings.
The newly added helpers use the same parameters as the existing
{alloc/free}_xenballooned_pages functions, which allows for in-place
replacement of the callers. Once a memory region has been added to be
used as scratch mapping space it will no longer be released, and pages
returned are kept in a linked list. This allows to have a buffer of
pages and prevents resorting to frequent additions and removals of
regions.
If enabled (because ZONE_DEVICE is supported) the usage of the new
functionality untangles Xen balloon and RAM hotplug from the usage of
unpopulated physical memory ranges to map foreign pages, which is the
correct thing to do in order to avoid mappings of foreign pages depend
on memory hotplug.
Note the driver is currently not enabled on Arm platforms because it
would interfere with the identity mapping required on some platforms.
Signed-off-by: Roger Pau Monné
Sorry, I just got a build error for x86 32-bit build:
WARNING: unmet direct dependencies detected for ZONE_DEVICE
Depends on [n]: MEMORY_HOTPLUG [=n] && MEMORY_HOTREMOVE [=n] &&
SPARSEMEM_VMEMMAP [=n] && ARCH_HAS_PTE_DEVMAP [=n]
Selected by [y]:
- XEN_UNPOPULATED_ALLOC [=y] && XEN [=y] && X86 [=y]
GEN Makefile
CC kernel/bounds.s
CALL/home/gross/korg/src/scripts/atomic/check-atomics.sh
UPD include/generated/bounds.h
CC arch/x86/kernel/asm-offsets.s
In file included from /home/gross/korg/src/include/linux/mmzone.h:19:0,
from /home/gross/korg/src/include/linux/gfp.h:6,
from /home/gross/korg/src/include/linux/slab.h:15,
from /home/gross/korg/src/include/linux/crypto.h:19,
from /home/gross/korg/src/arch/x86/kernel/asm-offsets.c:9:
/home/gross/korg/src/include/linux/page-flags-layout.h:95:2: error: #error
"Not enough bits in page flags"
#error "Not enough bits in page flags"
^
make[2]: *** [/home/gross/korg/src/scripts/Makefile.build:114:
arch/x86/kernel/asm-offsets.s] Error 1
make[1]: *** [/home/gross/korg/src/Makefile:1175: prepare0] Error 2
make[1]: Leaving directory '/home/gross/korg/x8632'
make: *** [Makefile:185: __sub-make] Error 2
Sorry for this. I've tested a 32bit build but I think it was before
the last Kconfig changes. I'm a little unsure how to solve this, as
ZONE_DEVICE doesn't select the required options for it to run, but
rather depends on them to be available.
You can trigger something similar on x86-64 by doing:
$ make ARCH=x86_64 xen.config
Using .config as base
Merging ./kernel/configs/xen.config
Merging ./arch/x86/configs/xen.config
#
# merged configuration written to .config (needs make)
#
scripts/kconfig/conf --olddefconfig Kconfig
WARNING: unmet direct dependencies detected for ZONE_DEVICE
Depends on [n]: MEMORY_HOTPLUG [=y] && MEMORY_HOTREMOVE [=n] && SPARSEMEM_VMEMMAP
[=y] && ARCH_HAS_PTE_DEVMAP [=y]
Selected by [y]:
- XEN_UNPOPULATED_ALLOC [=y] && XEN [=y] && X86_64 [=y]
#
# configuration written to .config
#
I think the only solution is to have XEN_UNPOPULATED_ALLOC depend on
ZONE_DEVICE rather than select it?
Yes, I think so.
I've folded that in and now build is fine.
Juergen
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[PATCH v5 19/80] drm/vc4: crtc: Disable color management for HVS5
The HVS5 uses different color matrices. Disable color management support
for now.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 17 +++--
drivers/gpu/drm/vc4/vc4_hvs.c | 2 +-
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 04744223460a..41bc61d5a61f 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -874,6 +874,7 @@ int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc
*vc4_crtc,
const struct drm_crtc_funcs *crtc_funcs,
const struct drm_crtc_helper_funcs *crtc_helper_funcs)
{
+ struct vc4_dev *vc4 = to_vc4_dev(drm);
struct drm_crtc *crtc = &vc4_crtc->base;
struct drm_plane *primary_plane;
unsigned int i;
@@ -893,13 +894,17 @@ int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc
*vc4_crtc,
drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
crtc_funcs, NULL);
drm_crtc_helper_add(crtc, crtc_helper_funcs);
- drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
- drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
- /* We support CTM, but only for one CRTC at a time. It's therefore
-* implemented as private driver state in vc4_kms, not here.
-*/
- drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
+ if (!vc4->hvs->hvs5) {
+ drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
+
+ drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
+
+ /* We support CTM, but only for one CRTC at a time. It's
therefore
+* implemented as private driver state in vc4_kms, not here.
+*/
+ drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
+ }
for (i = 0; i < crtc->gamma_size; i++) {
vc4_crtc->lut_r[i] = i;
diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index 31a9bc5ef84e..fa61cad3a53d 100644
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -443,7 +443,7 @@ void vc4_hvs_mode_set_nofb(struct drm_crtc *crtc)
HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel),
SCALER_DISPBKGND_AUTOHS |
- SCALER_DISPBKGND_GAMMA |
+ ((!vc4->hvs->hvs5) ? SCALER_DISPBKGND_GAMMA : 0) |
(interlace ? SCALER_DISPBKGND_INTERLACE : 0));
/* Reload the LUT, since the SRAMs would have been disabled if
--
git-series 0.9.1
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[PATCH v5 39/80] drm/vc4: hdmi: Move structure to header
We will need to share the vc4_hdmi and related structures with multiple
files, so let's create a header for it.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 76 +---
drivers/gpu/drm/vc4/vc4_hdmi.h | 86 +++-
2 files changed, 87 insertions(+), 75 deletions(-)
create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi.h
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index ae8c4d53e239..5c4d2fee6b86 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -49,87 +49,13 @@
#include
#include "media/cec.h"
#include "vc4_drv.h"
+#include "vc4_hdmi.h"
#include "vc4_regs.h"
#define HSM_CLOCK_FREQ 163682864
#define CEC_CLOCK_FREQ 4
#define CEC_CLOCK_DIV (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ)
-/* HDMI audio information */
-struct vc4_hdmi_audio {
- struct snd_soc_card card;
- struct snd_soc_dai_link link;
- struct snd_soc_dai_link_component cpu;
- struct snd_soc_dai_link_component codec;
- struct snd_soc_dai_link_component platform;
- int samplerate;
- int channels;
- struct snd_dmaengine_dai_dma_data dma_data;
- struct snd_pcm_substream *substream;
-};
-
-/* General HDMI hardware state. */
-struct vc4_hdmi {
- struct platform_device *pdev;
-
- struct drm_encoder *encoder;
- struct drm_connector *connector;
-
- struct vc4_hdmi_audio audio;
-
- struct i2c_adapter *ddc;
- void __iomem *hdmicore_regs;
- void __iomem *hd_regs;
- int hpd_gpio;
- bool hpd_active_low;
-
- struct cec_adapter *cec_adap;
- struct cec_msg cec_rx_msg;
- bool cec_tx_ok;
- bool cec_irq_was_rx;
-
- struct clk *pixel_clock;
- struct clk *hsm_clock;
-
- struct debugfs_regset32 hdmi_regset;
- struct debugfs_regset32 hd_regset;
-};
-
-#define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
-#define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
-#define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
-#define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
-
-/* VC4 HDMI encoder KMS struct */
-struct vc4_hdmi_encoder {
- struct vc4_encoder base;
- bool hdmi_monitor;
- bool limited_rgb_range;
-};
-
-static inline struct vc4_hdmi_encoder *
-to_vc4_hdmi_encoder(struct drm_encoder *encoder)
-{
- return container_of(encoder, struct vc4_hdmi_encoder, base.base);
-}
-
-/* VC4 HDMI connector KMS struct */
-struct vc4_hdmi_connector {
- struct drm_connector base;
-
- /* Since the connector is attached to just the one encoder,
-* this is the reference to it so we can do the best_encoder()
-* hook.
-*/
- struct drm_encoder *encoder;
-};
-
-static inline struct vc4_hdmi_connector *
-to_vc4_hdmi_connector(struct drm_connector *connector)
-{
- return container_of(connector, struct vc4_hdmi_connector, base);
-}
-
static const struct debugfs_reg32 hdmi_regs[] = {
VC4_REG32(VC4_HDMI_CORE_REV),
VC4_REG32(VC4_HDMI_SW_RESET_CONTROL),
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
new file mode 100644
index ..5ec5d1f6b1e6
--- /dev/null
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -0,0 +1,86 @@
+#ifndef _VC4_HDMI_H_
+#define _VC4_HDMI_H_
+
+#include
+#include
+#include
+#include
+
+#include "vc4_drv.h"
+
+/* HDMI audio information */
+struct vc4_hdmi_audio {
+ struct snd_soc_card card;
+ struct snd_soc_dai_link link;
+ struct snd_soc_dai_link_component cpu;
+ struct snd_soc_dai_link_component codec;
+ struct snd_soc_dai_link_component platform;
+ int samplerate;
+ int channels;
+ struct snd_dmaengine_dai_dma_data dma_data;
+ struct snd_pcm_substream *substream;
+};
+
+/* General HDMI hardware state. */
+struct vc4_hdmi {
+ struct platform_device *pdev;
+
+ struct drm_encoder *encoder;
+ struct drm_connector *connector;
+
+ struct vc4_hdmi_audio audio;
+
+ struct i2c_adapter *ddc;
+ void __iomem *hdmicore_regs;
+ void __iomem *hd_regs;
+ int hpd_gpio;
+ bool hpd_active_low;
+
+ struct cec_adapter *cec_adap;
+ struct cec_msg cec_rx_msg;
+ bool cec_tx_ok;
+ bool cec_irq_was_rx;
+
+ struct clk *pixel_clock;
+ struct clk *hsm_clock;
+
+ struct debugfs_regset32 hdmi_regset;
+ struct debugfs_regset32 hd_regset;
+};
+
+#define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
+#define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
+#define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
+#define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
+
+/* VC4 HDMI encoder KMS struct */
+struct vc4_hdmi_encoder {
[PATCH v5 08/80] drm/vc4: crtc: Use a shared interrupt
Some pixelvalves in vc5 use the same interrupt line so let's register our interrupt handler as a shared one. Reviewed-by: Eric Anholt Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index e55b2208b4b7..9faae22cb0f8 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -919,7 +919,9 @@ static int vc4_crtc_bind(struct device *dev, struct device *master, void *data) CRTC_WRITE(PV_INTEN, 0); CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); ret = devm_request_irq(dev, platform_get_irq(pdev, 0), - vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc); + vc4_crtc_irq_handler, + IRQF_SHARED, + "vc4 crtc", vc4_crtc); if (ret) goto err_destroy_planes; -- git-series 0.9.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
RE: [PATCH v9 2/3] drm: bridge: Add support for Cadence MHDP8546 DPI/DP bridge
Hi Tomi, >-Original Message- >From: Tomi Valkeinen >Sent: Thursday, September 3, 2020 12:54 PM >To: Milind Parab ; Swapnil Kashinath Jakhade >; airl...@linux.ie; dan...@ffwll.ch; >laurent.pinch...@ideasonboard.com; robh...@kernel.org; >a.ha...@samsung.com; narmstr...@baylibre.com; jo...@kwiboo.se; >jernej.skra...@siol.net; dri-devel@lists.freedesktop.org; >devicet...@vger.kernel.org; linux-ker...@vger.kernel.org >Cc: Yuti Suresh Amonkar ; jsa...@ti.com; >nsek...@ti.com; prane...@ti.com; nikhil...@ti.com >Subject: Re: [PATCH v9 2/3] drm: bridge: Add support for Cadence MHDP8546 >DPI/DP bridge > >EXTERNAL MAIL > > >Hi Milind, > >On 03/09/2020 09:22, Milind Parab wrote: > >> Also, note that CDNS MHDP implements DP_FRAMER_TU_p where bits 5:0 >is tu_valid_symbols. So max programmable value is 63. >> Register document gives following explanation "Number of valid symbols >> per Transfer Unit (TU). Rounded down to lower integer value (Allowed >values are 1 to (TU_size-1)" >> >> So, it says in case vs calculates to 64 (where Avail BW and Req BW are >> same) we program tu_valid_symbols = 63 > >Hmm, so "Rounded down to lower integer value" means > >floor(x) - 1 ? > >If that's the case, we need to subtract 1 in all cases, not only when req bw == >avail bw. > Explicit subtraction by 1 is not mentioned anywhere There is a hint of sub-optimal performance when vs equals 64. However need to confirm from simulations. >> Third, is about the line_threshold calculation Unlike TU_SIZE and >> Valid_Symbols, line_threshold is implementation dependent >> >> CDNS MHDP register specs gives the definition as " Video FIFO latency >threshold" >> Bits 5:0, Name "cfg_active_line_tresh", Description "Video Fifo Latency >threshold. Defines the number of FIFO rows before reading starts. This setting >depends on the transmitted video format and link rate." >> >> This parameter is the Threshold of the FIFO. For optimal performance >(considering equal write and read clock) we normally put the threshold in the >mid of the FIFO. >> Hence the reset value is fixed as 32. >> Since symbol FIFO is accessed by Pxl clock and Symbol Link Clock the >> Threshold is set to a value which is dependent on the ratio of these >> clocks >> >> line_threshold = full_fifo - fifo_ratio_due_to_clock_diff + 2 where, >> full_fifo = (vs+1) * (8/bpp) fifo_ratio_due_to_clock_diff = ((vs+1) * >> pxlclock/mhdp->link.rate - 1) / mhdp->link.num_lanes >> >> Note that line_threshold can take a max value of 63 > >That doesn't result in anything sensible. 8/bpp is always 0. Consider above statements as pseudocode. For integer division we need scale up like it was scaled by 5 bits in the original code And here 8/bpp = 1 > > Tomi > >-- >Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. >Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 74/80] drm/vc4: hdmi: Switch to blank pixels when disabled
In order to avoid pixels getting stuck in an unflushable FIFO, we need when
we disable the HDMI controller to switch away from getting our pixels from
the pixelvalve and instead use blank pixels, and switch back to the
pixelvalve when we enable the HDMI controller.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 9 +
drivers/gpu/drm/vc4/vc4_regs.h | 3 +++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 8bf69cafdd7e..ab7abb409de2 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -325,6 +325,12 @@ static void vc4_hdmi_encoder_post_crtc_disable(struct
drm_encoder *encoder)
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
+
+ HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
+ VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC);
+
+ HDMI_WRITE(HDMI_VID_CTL,
+ HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
}
static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder)
@@ -563,6 +569,9 @@ static void vc4_hdmi_encoder_post_crtc_enable(struct
drm_encoder *encoder)
(vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
(hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
+ HDMI_WRITE(HDMI_VID_CTL,
+ HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
+
if (vc4_encoder->hdmi_monitor) {
HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
HDMI_READ(HDMI_SCHEDULER_CONTROL) |
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index d1e8961edaa0..30af52b406f1 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -723,6 +723,9 @@
# define VC4_HD_VID_CTL_FRAME_COUNTER_RESETBIT(29)
# define VC4_HD_VID_CTL_VSYNC_LOW BIT(28)
# define VC4_HD_VID_CTL_HSYNC_LOW BIT(27)
+# define VC4_HD_VID_CTL_CLRSYNCBIT(24)
+# define VC4_HD_VID_CTL_CLRRGB BIT(23)
+# define VC4_HD_VID_CTL_BLANKPIX BIT(18)
# define VC4_HD_CSC_CTL_ORDER_MASK VC4_MASK(7, 5)
# define VC4_HD_CSC_CTL_ORDER_SHIFT5
--
git-series 0.9.1
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[PATCH v5 45/80] drm/vc4: hdmi: Add container_of macros for encoders and connectors
Whenever the code needs to access the vc4_hdmi structure from a DRM
connector or encoder, it first accesses the drm_device associated to the
connector, then retrieve the drm_dev private data which gives it a
pointer to our vc4_dev, and will finally follow the vc4_hdmi pointer in
that structure.
That will also give us some trouble when having multiple controllers,
but now that we have our encoder and connector structures that are part
of vc4_hdmi, we can simply call container_of on the DRM connector or
encoder and retrieve the vc4_hdmi structure directly.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 41 ++-
drivers/gpu/drm/vc4/vc4_hdmi.h | 16 ++-
2 files changed, 28 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 93865327a8d4..a2053da4e443 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -121,9 +121,7 @@ static int vc4_hdmi_debugfs_regs(struct seq_file *m, void
*unused)
static enum drm_connector_status
vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
{
- struct drm_device *dev = connector->dev;
- struct vc4_dev *vc4 = to_vc4_dev(dev);
- struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
+ struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
if (vc4_hdmi->hpd_gpio) {
if (gpio_get_value_cansleep(vc4_hdmi->hpd_gpio) ^
@@ -150,17 +148,13 @@ static void vc4_hdmi_connector_destroy(struct
drm_connector *connector)
static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
{
- struct vc4_hdmi_connector *vc4_connector =
- to_vc4_hdmi_connector(connector);
- struct drm_encoder *encoder = vc4_connector->encoder;
- struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
- struct drm_device *dev = connector->dev;
- struct vc4_dev *vc4 = to_vc4_dev(dev);
+ struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
+ struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
int ret = 0;
struct edid *edid;
- edid = drm_get_edid(connector, vc4->hdmi->ddc);
- cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid);
+ edid = drm_get_edid(connector, vc4_hdmi->ddc);
+ cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
if (!edid)
return -ENODEV;
@@ -229,9 +223,7 @@ static int vc4_hdmi_connector_init(struct drm_device *dev,
static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
enum hdmi_infoframe_type type)
{
- struct drm_device *dev = encoder->dev;
- struct vc4_dev *vc4 = to_vc4_dev(dev);
- struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
+ struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
u32 packet_id = type - 0x80;
HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
@@ -244,9 +236,7 @@ static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
union hdmi_infoframe *frame)
{
- struct drm_device *dev = encoder->dev;
- struct vc4_dev *vc4 = to_vc4_dev(dev);
- struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
+ struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
u32 packet_id = frame->any.type - 0x80;
u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id);
uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
@@ -292,9 +282,8 @@ static void vc4_hdmi_write_infoframe(struct drm_encoder
*encoder,
static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
{
+ struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
- struct vc4_dev *vc4 = encoder->dev->dev_private;
- struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
struct drm_connector *connector = &vc4_hdmi->connector.base;
struct drm_connector_state *cstate = connector->state;
struct drm_crtc *crtc = encoder->crtc;
@@ -338,9 +327,7 @@ static void vc4_hdmi_set_spd_infoframe(struct drm_encoder
*encoder)
static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
{
- struct drm_device *drm = encoder->dev;
- struct vc4_dev *vc4 = drm->dev_private;
- struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
+ struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
union hdmi_infoframe frame;
int ret;
@@ -362,9 +349,7 @@ static void vc4_hdmi_set_infoframes(struct drm_encoder
*encoder)
static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
{
- struct drm_device *dev = encoder->dev;
- struct vc4_dev *vc4 = to_vc4_dev(dev);
- struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
+ struct vc4_hdmi *vc4_hdmi = encoder
[PULL] drm-misc-next
Hi Dave, Daniel, Here's this week PR for drm-misc-next Thanks! Maxime drm-misc-next-2020-09-03: drm-misc-next for 5.10: UAPI Changes: Cross-subsystem Changes: Core Changes: - doc: update the doc to encourage drivers to use devm_drm_dev_alloc - ttm: More reworks / cleanups Driver Changes: - sun4i: Minor fix in the LVDS encoder - panels: New panel: AM-1280800N3TZQW-T00H The following changes since commit cd6da0b113512b15a4d35f355f9ecd8858297369: drm/mgag200: fix spelling mistake "expeced" -> "expected" (2020-08-27 11:17:52 +0200) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2020-09-03 for you to fetch changes up to 4c8e84b8876dc726a7e5327b3113d75423c46728: drm/managed: Cleanup of unused functions and polishing docs (2020-09-03 16:25:06 +0200) drm-misc-next for 5.10: UAPI Changes: Cross-subsystem Changes: Core Changes: - doc: update the doc to encourage drivers to use devm_drm_dev_alloc - ttm: More reworks / cleanups Driver Changes: - sun4i: Minor fix in the LVDS encoder - panels: New panel: AM-1280800N3TZQW-T00H Christian König (3): drm/ttm: make sure that we always zero init mem.bus v2 drm/nouveau: move io_reserve_lru handling into the driver v5 drm/ttm: remove io_reserve_lru handling v3 Daniel Vetter (1): drm/managed: Cleanup of unused functions and polishing docs Dave Airlie (2): drm/amdgpu/ttm: remove unused parameter to move blit drm/radeon/ttm: don't store driver copy of device pointer. Dinghao Liu (1): drm/crc-debugfs: Fix memleak in crc_control_write Gerd Hoffmann (2): drm/virtio: fix unblank drm/virtio: drop virtio_gpu_output->enabled Jagan Teki (2): dt-bindings: display: simple: Add AM-1280800N3TZQW-T00H drm/panel: simple: Add AM-1280800N3TZQW-T00H Laurent Pinchart (1): drm: panel: Fix bpc for OrtusTech COM43H4M85ULC panel Maxime Ripard (1): drm/sun4i: lvds: Invert the LVDS polarity Melissa Wen (1): drm/vkms: add alpha-premultiplied color blending Randy Dunlap (3): drm: virtio: fix kconfig dependency warning dma-buf: fix kernel-doc warning in dma-fence.c dma-buf: fix kernel-doc warning in Rikard Falkeborn (1): drm/gma500: Constify static structs Robert Chiras (1): drm/panel: rm67191: Remove CLOCK_NON_CONTINUOUS flag Sam McNally (1): drm/dp_mst: Support remote i2c writes Sidong Yang (1): drm/vkms: avoid warning in vkms_get_vblank_timestamp Tian Tao (1): drm/hisilicon: Removed the dependency on the mmu Ville Syrjälä (2): drm: Nuke mode->private_flags drm: Replace mode->export_head with a boolean Vinod Koul (1): drm/bridge: Fix the dsi remote end-points .../bindings/display/panel/panel-simple.yaml | 2 + Documentation/driver-api/driver-model/devres.rst | 2 +- drivers/dma-buf/dma-fence.c| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 8 +- drivers/gpu/drm/bridge/lontium-lt9611.c| 4 +- drivers/gpu/drm/drm_connector.c| 45 +--- drivers/gpu/drm/drm_debugfs_crc.c | 4 +- drivers/gpu/drm/drm_dp_mst_topology.c | 106 +++--- drivers/gpu/drm/drm_drv.c | 78 - drivers/gpu/drm/drm_managed.c | 2 +- drivers/gpu/drm/gma500/framebuffer.c | 6 +- drivers/gpu/drm/hisilicon/hibmc/Kconfig| 2 +- drivers/gpu/drm/nouveau/nouveau_bo.c | 101 + drivers/gpu/drm/nouveau/nouveau_bo.h | 3 + drivers/gpu/drm/nouveau/nouveau_drv.h | 2 + drivers/gpu/drm/nouveau/nouveau_ttm.c | 44 +++- drivers/gpu/drm/panel/panel-raydium-rm67191.c | 3 +- drivers/gpu/drm/panel/panel-simple.c | 31 +- drivers/gpu/drm/radeon/radeon_ttm.c| 8 +- drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 +- drivers/gpu/drm/ttm/ttm_bo.c | 43 +++- drivers/gpu/drm/ttm/ttm_bo_util.c | 121 ++--- drivers/gpu/drm/ttm/ttm_bo_vm.c| 39 ++- drivers/gpu/drm/ttm/ttm_resource.c | 3 - drivers/gpu/drm/virtio/Kconfig | 2 +- drivers/gpu/drm/virtio/virtgpu_display.c | 15 ++- drivers/gpu/drm/virtio/virtgpu_drv.h | 2 +- drivers/gpu/drm/virtio/virtgpu_plane.c | 6 +- drivers/gpu/drm/vkms/vkms_composer.c | 55 +++--- drivers/gpu/drm/vkms/vkms_crtc.c | 5 + include/drm/drm_device.h | 2 +- include/drm/drm_drv.h | 16 +-- include/drm/drm_modes.h|
[PATCH v5 54/80] drm/vc4: hdmi: Add PHY RNG enable / disable function
Let's continue the implementation of hooks for the parts that change in the
BCM2711 SoC with the PHY RNG setup.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 15 +--
drivers/gpu/drm/vc4/vc4_hdmi.h | 8
drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 15 +++
3 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index f3cc612f6a0b..c29376c3fd8a 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -762,9 +762,9 @@ static int vc4_hdmi_audio_trigger(struct snd_pcm_substream
*substream, int cmd,
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
vc4_hdmi_set_audio_infoframe(encoder);
- HDMI_WRITE(HDMI_TX_PHY_CTL_0,
- HDMI_READ(HDMI_TX_PHY_CTL_0) &
- ~VC4_HDMI_TX_PHY_RNG_PWRDN);
+
+ if (vc4_hdmi->variant->phy_rng_enable)
+ vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
HDMI_WRITE(HDMI_MAI_CTL,
VC4_SET_FIELD(vc4_hdmi->audio.channels,
@@ -776,9 +776,10 @@ static int vc4_hdmi_audio_trigger(struct snd_pcm_substream
*substream, int cmd,
VC4_HD_MAI_CTL_DLATE |
VC4_HD_MAI_CTL_ERRORE |
VC4_HD_MAI_CTL_ERRORF);
- HDMI_WRITE(HDMI_TX_PHY_CTL_0,
- HDMI_READ(HDMI_TX_PHY_CTL_0) |
- VC4_HDMI_TX_PHY_RNG_PWRDN);
+
+ if (vc4_hdmi->variant->phy_rng_disable)
+ vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
+
break;
default:
break;
@@ -1432,6 +1433,8 @@ static const struct vc4_hdmi_variant bcm2835_variant = {
.reset = vc4_hdmi_reset,
.phy_init = vc4_hdmi_phy_init,
.phy_disable= vc4_hdmi_phy_disable,
+ .phy_rng_enable = vc4_hdmi_phy_rng_enable,
+ .phy_rng_disable= vc4_hdmi_phy_rng_disable,
};
static const struct of_device_id vc4_hdmi_dt_match[] = {
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index 32c80161c786..950accbc44e4 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -47,6 +47,12 @@ struct vc4_hdmi_variant {
/* Callback to disable the PHY */
void (*phy_disable)(struct vc4_hdmi *vc4_hdmi);
+
+ /* Callback to enable the RNG in the PHY */
+ void (*phy_rng_enable)(struct vc4_hdmi *vc4_hdmi);
+
+ /* Callback to disable the RNG in the PHY */
+ void (*phy_rng_disable)(struct vc4_hdmi *vc4_hdmi);
};
/* HDMI audio information */
@@ -107,5 +113,7 @@ encoder_to_vc4_hdmi(struct drm_encoder *encoder)
void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
struct drm_display_mode *mode);
void vc4_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi);
+void vc4_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi);
+void vc4_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi);
#endif /* _VC4_HDMI_H_ */
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
b/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
index 5a1746877bb5..93287e24d7d1 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
@@ -7,6 +7,7 @@
*/
#include "vc4_hdmi.h"
+#include "vc4_regs.h"
#include "vc4_hdmi_regs.h"
void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi, struct drm_display_mode
*mode)
@@ -23,3 +24,17 @@ void vc4_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi)
{
HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0xf << 16);
}
+
+void vc4_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi)
+{
+ HDMI_WRITE(HDMI_TX_PHY_CTL_0,
+ HDMI_READ(HDMI_TX_PHY_CTL_0) &
+ ~VC4_HDMI_TX_PHY_RNG_PWRDN);
+}
+
+void vc4_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi)
+{
+ HDMI_WRITE(HDMI_TX_PHY_CTL_0,
+ HDMI_READ(HDMI_TX_PHY_CTL_0) |
+ VC4_HDMI_TX_PHY_RNG_PWRDN);
+}
--
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[PATCH v5 03/80] drm/vc4: hvs: Boost the core clock during modeset
In order to prevent timeouts and stalls in the pipeline, the core clock
needs to be maxed at 500MHz during a modeset on the BCM2711.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_drv.h | 2 ++
drivers/gpu/drm/vc4/vc4_hvs.c | 18 ++
drivers/gpu/drm/vc4/vc4_kms.c | 9 +
3 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index e4cde1f9224b..6358f6ca8d56 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -320,6 +320,8 @@ struct vc4_hvs {
void __iomem *regs;
u32 __iomem *dlist;
+ struct clk *core_clk;
+
/* Memory manager for CRTCs to allocate space in the display
* list. Units are dwords.
*/
diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index 836d8799d79e..abdb43c4cc10 100644
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -19,6 +19,7 @@
* each CRTC.
*/
+#include
#include
#include
@@ -540,6 +541,20 @@ static int vc4_hvs_bind(struct device *dev, struct device
*master, void *data)
hvs->regset.regs = hvs_regs;
hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
+ if (hvs->hvs5) {
+ hvs->core_clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(hvs->core_clk)) {
+ dev_err(&pdev->dev, "Couldn't get core clock\n");
+ return PTR_ERR(hvs->core_clk);
+ }
+
+ ret = clk_prepare_enable(hvs->core_clk);
+ if (ret) {
+ dev_err(&pdev->dev, "Couldn't enable the core clock\n");
+ return ret;
+ }
+ }
+
if (!hvs->hvs5)
hvs->dlist = hvs->regs + SCALER_DLIST_START;
else
@@ -624,6 +639,7 @@ static void vc4_hvs_unbind(struct device *dev, struct
device *master,
{
struct drm_device *drm = dev_get_drvdata(master);
struct vc4_dev *vc4 = drm->dev_private;
+ struct vc4_hvs *hvs = vc4->hvs;
if (drm_mm_node_allocated(&vc4->hvs->mitchell_netravali_filter))
drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter);
@@ -631,6 +647,8 @@ static void vc4_hvs_unbind(struct device *dev, struct
device *master,
drm_mm_takedown(&vc4->hvs->dlist_mm);
drm_mm_takedown(&vc4->hvs->lbm_mm);
+ clk_disable_unprepare(hvs->core_clk);
+
vc4->hvs = NULL;
}
diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index 08318e69061b..210cc2408087 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -11,6 +11,8 @@
* crtc, HDMI encoder).
*/
+#include
+
#include
#include
#include
@@ -149,6 +151,7 @@ vc4_atomic_complete_commit(struct drm_atomic_state *state)
{
struct drm_device *dev = state->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
+ struct vc4_hvs *hvs = vc4->hvs;
struct vc4_crtc *vc4_crtc;
int i;
@@ -160,6 +163,9 @@ vc4_atomic_complete_commit(struct drm_atomic_state *state)
vc4_hvs_mask_underrun(dev, vc4_crtc->channel);
}
+ if (vc4->hvs->hvs5)
+ clk_set_min_rate(hvs->core_clk, 5);
+
drm_atomic_helper_wait_for_fences(dev, state, false);
drm_atomic_helper_wait_for_dependencies(state);
@@ -182,6 +188,9 @@ vc4_atomic_complete_commit(struct drm_atomic_state *state)
drm_atomic_helper_commit_cleanup_done(state);
+ if (vc4->hvs->hvs5)
+ clk_set_min_rate(hvs->core_clk, 0);
+
drm_atomic_state_put(state);
up(&vc4->async_modeset);
--
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[PATCH v5 06/80] drm/vc4: plane: Create more planes
Let's now create more planes that can be affected to all the CRTCs.
vc4 has 3 CRTCs, 1 primary and 1 cursor each, and was having 24 (8
planes per CRTC) overlays.
However, vc5 has 5 CRTCs, so keeping the same logic would put us at 50
planes which is well above the 32 planes limit imposed by DRM.
Using 16 seems like a good tradeoff between staying under 32 and yet
providing enough planes.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_plane.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 23916814b4e3..1e38e603f83b 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -1384,7 +1384,7 @@ int vc4_plane_create_additional_planes(struct drm_device
*drm)
* modest number of planes to expose, that should hopefully
* still cover any sane usecase.
*/
- for (i = 0; i < 8; i++) {
+ for (i = 0; i < 16; i++) {
struct drm_plane *plane =
vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
--
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[PATCH v5 09/80] drm/vc4: crtc: Move the cob allocation outside of bind
The COB allocation depends on the HVS channel used for a given
pixelvalve.
While the channel allocation was entirely static in vc4, vc5 changes
that and at bind time, a pixelvalve can be assigned to multiple
HVS channels.
Let's prepare that rework by allocating the COB when it's actually
needed.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 35 +--
drivers/gpu/drm/vc4/vc4_drv.h | 2 +--
2 files changed, 17 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 9faae22cb0f8..fdecaba77836 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -65,6 +65,20 @@ static const struct debugfs_reg32 crtc_regs[] = {
VC4_REG32(PV_HACT_ACT),
};
+static unsigned int
+vc4_crtc_get_cob_allocation(struct vc4_dev *vc4, unsigned int channel)
+{
+ u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel));
+ /* Top/base are supposed to be 4-pixel aligned, but the
+* Raspberry Pi firmware fills the low bits (which are
+* presumably ignored).
+*/
+ u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
+ u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
+
+ return top - base + 4;
+}
+
static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
bool in_vblank_irq,
int *vpos, int *hpos,
@@ -74,6 +88,7 @@ static bool vc4_crtc_get_scanout_position(struct drm_crtc
*crtc,
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ unsigned int cob_size;
u32 val;
int fifo_lines;
int vblank_lines;
@@ -109,8 +124,9 @@ static bool vc4_crtc_get_scanout_position(struct drm_crtc
*crtc,
*hpos += mode->crtc_htotal / 2;
}
+ cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc->channel);
/* This is the offset we need for translating hvs -> pv scanout pos. */
- fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
+ fifo_lines = cob_size / mode->crtc_hdisplay;
if (fifo_lines > 0)
ret = true;
@@ -823,22 +839,6 @@ static void vc4_set_crtc_possible_masks(struct drm_device
*drm,
}
}
-static void
-vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
-{
- struct drm_device *drm = vc4_crtc->base.dev;
- struct vc4_dev *vc4 = to_vc4_dev(drm);
- u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
- /* Top/base are supposed to be 4-pixel aligned, but the
-* Raspberry Pi firmware fills the low bits (which are
-* presumably ignored).
-*/
- u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
- u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
-
- vc4_crtc->cob_size = top - base + 4;
-}
-
int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
const struct drm_crtc_funcs *crtc_funcs,
const struct drm_crtc_helper_funcs *crtc_helper_funcs)
@@ -870,7 +870,6 @@ int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc
*vc4_crtc,
* implemented as private driver state in vc4_kms, not here.
*/
drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
- vc4_crtc_get_cob_allocation(vc4_crtc);
for (i = 0; i < crtc->gamma_size; i++) {
vc4_crtc->lut_r[i] = i;
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 0bc150daafb2..d80fc3bbb450 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -477,8 +477,6 @@ struct vc4_crtc {
u8 lut_r[256];
u8 lut_g[256];
u8 lut_b[256];
- /* Size in pixels of the COB memory allocated to this CRTC. */
- u32 cob_size;
struct drm_pending_vblank_event *event;
--
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[PATCH v5 04/80] drm/vc4: plane: Change LBM alignment constraint on LBM
From: Dave Stevenson The HVS5 needs an alignment of 64bytes for its LBM memory, so let's reflect it. Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Dave Stevenson Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_plane.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c index 20c949b57827..d0771ebd5f75 100644 --- a/drivers/gpu/drm/vc4/vc4_plane.c +++ b/drivers/gpu/drm/vc4/vc4_plane.c @@ -578,7 +578,9 @@ static int vc4_plane_allocate_lbm(struct drm_plane_state *state) spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags); ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm, &vc4_state->lbm, -lbm_size, 32, 0, 0); +lbm_size, +vc4->hvs->hvs5 ? 64 : 32, +0, 0); spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags); if (ret) -- git-series 0.9.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 11/80] drm/vc4: crtc: Use local chan variable
The vc4_crtc_handle_page_flip already has a local variable holding the value of vc4_crtc->channel, so let's use it instead. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index d3126fe04d9a..cdeaa0cd981f 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -533,7 +533,7 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc) * the CRTC and encoder already reconfigured, leading to * underruns. This can be seen when reconfiguring the CRTC. */ - vc4_hvs_unmask_underrun(dev, vc4_crtc->channel); + vc4_hvs_unmask_underrun(dev, chan); } spin_unlock_irqrestore(&dev->event_lock, flags); } -- git-series 0.9.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 12/80] drm/vc4: crtc: Enable and disable the PV in atomic_enable / disable
The VIDEN bit in the pixelvalve currently being used to enable or disable the pixelvalve seems to not be enough in some situations, which whill end up with the pixelvalve stalling. In such a case, even re-enabling VIDEN doesn't bring it back and we need to clear the FIFO. This can only be done if the pixelvalve is disabled though. In order to overcome this, we can configure the pixelvalve during mode_set_no_fb by calling vc4_crtc_config_pv, but only enable it in atomic_enable and flush the FIFO there, and in atomic_disable disable the pixelvalve again. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index cdeaa0cd981f..fe2e5675aed4 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -332,9 +332,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc) PV_CONTROL_TRIGGER_UNDERFLOW | PV_CONTROL_WAIT_HSTART | VC4_SET_FIELD(vc4_encoder->clock_select, -PV_CONTROL_CLK_SELECT) | - PV_CONTROL_FIFO_CLR | - PV_CONTROL_EN); +PV_CONTROL_CLK_SELECT)); } static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) @@ -386,6 +384,8 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); + CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN); + vc4_hvs_atomic_disable(crtc, old_state); /* @@ -410,6 +410,10 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc, require_hvs_enabled(dev); + /* Reset the PV fifo. */ + CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | + PV_CONTROL_FIFO_CLR | PV_CONTROL_EN); + /* Enable vblank irq handling before crtc is started otherwise * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist(). */ -- git-series 0.9.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 40/80] drm/vc4: hdmi: rework connectors and encoders
the vc4_hdmi driver has some custom structures to hold the data it needs to
associate with the drm_encoder and drm_connector structures.
However, it allocates them separately from the vc4_hdmi structure which
makes it more complicated than it needs to be.
Move those structures to be contained by vc4_hdmi and update the code
accordingly.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 87 ---
drivers/gpu/drm/vc4/vc4_hdmi.h | 64 +-
2 files changed, 72 insertions(+), 79 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 5c4d2fee6b86..9a0612a87fb8 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -191,20 +191,15 @@ static const struct drm_connector_helper_funcs
vc4_hdmi_connector_helper_funcs =
.get_modes = vc4_hdmi_connector_get_modes,
};
-static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
-struct drm_encoder
*encoder,
-struct i2c_adapter *ddc)
+static int vc4_hdmi_connector_init(struct drm_device *dev,
+ struct vc4_hdmi *vc4_hdmi,
+ struct i2c_adapter *ddc)
{
- struct drm_connector *connector;
- struct vc4_hdmi_connector *hdmi_connector;
+ struct vc4_hdmi_connector *hdmi_connector = &vc4_hdmi->connector;
+ struct drm_connector *connector = &hdmi_connector->base;
+ struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
int ret;
- hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
- GFP_KERNEL);
- if (!hdmi_connector)
- return ERR_PTR(-ENOMEM);
- connector = &hdmi_connector->base;
-
hdmi_connector->encoder = encoder;
drm_connector_init_with_ddc(dev, connector,
@@ -216,7 +211,7 @@ static struct drm_connector *vc4_hdmi_connector_init(struct
drm_device *dev,
/* Create and attach TV margin props to this connector. */
ret = drm_mode_create_tv_margin_properties(dev);
if (ret)
- return ERR_PTR(ret);
+ return ret;
drm_connector_attach_tv_margin_properties(connector);
@@ -228,7 +223,7 @@ static struct drm_connector *vc4_hdmi_connector_init(struct
drm_device *dev,
drm_connector_attach_encoder(connector, encoder);
- return connector;
+ return 0;
}
static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
@@ -298,21 +293,22 @@ static void vc4_hdmi_set_avi_infoframe(struct drm_encoder
*encoder)
struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
struct vc4_dev *vc4 = encoder->dev->dev_private;
struct vc4_hdmi *hdmi = vc4->hdmi;
- struct drm_connector_state *cstate = hdmi->connector->state;
+ struct drm_connector *connector = &hdmi->connector.base;
+ struct drm_connector_state *cstate = connector->state;
struct drm_crtc *crtc = encoder->crtc;
const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
union hdmi_infoframe frame;
int ret;
ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
- hdmi->connector, mode);
+ connector, mode);
if (ret < 0) {
DRM_ERROR("couldn't fill AVI infoframe\n");
return;
}
drm_hdmi_avi_infoframe_quant_range(&frame.avi,
- hdmi->connector, mode,
+ connector, mode,
vc4_encoder->limited_rgb_range ?
HDMI_QUANTIZATION_RANGE_LIMITED :
HDMI_QUANTIZATION_RANGE_FULL);
@@ -628,7 +624,8 @@ static const struct drm_encoder_helper_funcs
vc4_hdmi_encoder_helper_funcs = {
/* HDMI audio codec callbacks */
static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi)
{
- struct drm_device *drm = hdmi->encoder->dev;
+ struct drm_encoder *encoder = &hdmi->encoder.base.base;
+ struct drm_device *drm = encoder->dev;
struct vc4_dev *vc4 = to_vc4_dev(drm);
u32 hsm_clock = clk_get_rate(hdmi->hsm_clock);
unsigned long n, m;
@@ -647,7 +644,7 @@ static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi
*hdmi)
static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi)
{
- struct drm_encoder *encoder = hdmi->encoder;
+ struct drm_encoder *encoder = &hdmi->encoder.base.base;
struct drm_crtc *crtc = encoder->crtc;
struct drm_device *drm = encoder->dev;
struct vc
[PATCH v5 10/80] drm/vc4: crtc: Rename HVS channel to output
In vc5, the HVS has 6 outputs and 3 FIFOs (or channels), with
pixelvalves each being assigned to a given output, but each output can
then be muxed to feed from multiple FIFOs.
Since vc4 had that entirely static, both were probably equivalent, but
since that changes, let's rename hvs_channel to hvs_output in the
vc4_crtc_data, since a pixelvalve is really connected to an output, and
not to a FIFO.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 8
drivers/gpu/drm/vc4/vc4_drv.h | 4 ++--
drivers/gpu/drm/vc4/vc4_hvs.c | 2 +-
drivers/gpu/drm/vc4/vc4_txp.c | 2 +-
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index fdecaba77836..d3126fe04d9a 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -775,7 +775,7 @@ static const struct drm_crtc_helper_funcs
vc4_crtc_helper_funcs = {
static const struct vc4_pv_data bcm2835_pv0_data = {
.base = {
- .hvs_channel = 0,
+ .hvs_output = 0,
},
.debugfs_name = "crtc0_regs",
.pixels_per_clock = 1,
@@ -787,7 +787,7 @@ static const struct vc4_pv_data bcm2835_pv0_data = {
static const struct vc4_pv_data bcm2835_pv1_data = {
.base = {
- .hvs_channel = 2,
+ .hvs_output = 2,
},
.debugfs_name = "crtc1_regs",
.pixels_per_clock = 1,
@@ -799,7 +799,7 @@ static const struct vc4_pv_data bcm2835_pv1_data = {
static const struct vc4_pv_data bcm2835_pv2_data = {
.base = {
- .hvs_channel = 1,
+ .hvs_output = 1,
},
.debugfs_name = "crtc2_regs",
.pixels_per_clock = 1,
@@ -862,7 +862,7 @@ int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc
*vc4_crtc,
drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
crtc_funcs, NULL);
drm_crtc_helper_add(crtc, crtc_helper_funcs);
- vc4_crtc->channel = vc4_crtc->data->hvs_channel;
+ vc4_crtc->channel = vc4_crtc->data->hvs_output;
drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index d80fc3bbb450..d1cf4c038180 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -447,8 +447,8 @@ to_vc4_encoder(struct drm_encoder *encoder)
}
struct vc4_crtc_data {
- /* Which channel of the HVS this pixelvalve sources from. */
- int hvs_channel;
+ /* Which output of the HVS this pixelvalve sources from. */
+ int hvs_output;
};
struct vc4_pv_data {
diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index abdb43c4cc10..365425d67f3f 100644
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -419,7 +419,7 @@ void vc4_hvs_mode_set_nofb(struct drm_crtc *crtc)
struct drm_display_mode *mode = &crtc->state->adjusted_mode;
bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
- if (vc4_crtc->data->hvs_channel == 2) {
+ if (vc4_crtc->data->hvs_output == 2) {
u32 dispctrl;
u32 dsp3_mux;
diff --git a/drivers/gpu/drm/vc4/vc4_txp.c b/drivers/gpu/drm/vc4/vc4_txp.c
index a7c3af0005a0..f39d9900d027 100644
--- a/drivers/gpu/drm/vc4/vc4_txp.c
+++ b/drivers/gpu/drm/vc4/vc4_txp.c
@@ -452,7 +452,7 @@ static irqreturn_t vc4_txp_interrupt(int irq, void *data)
}
static const struct vc4_crtc_data vc4_txp_crtc_data = {
- .hvs_channel = 2,
+ .hvs_output = 2,
};
static int vc4_txp_bind(struct device *dev, struct device *master, void *data)
--
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[PATCH v5 55/80] drm/vc4: hdmi: Add a CSC setup callback
Similarly to the previous patches, the CSC setup is slightly different in
the BCM2711 than in the previous generations. Let's add a callback for it.
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 70 +--
drivers/gpu/drm/vc4/vc4_hdmi.h | 3 ++-
2 files changed, 45 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index c29376c3fd8a..532618e02399 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -334,6 +334,41 @@ static void vc4_hdmi_encoder_disable(struct drm_encoder
*encoder)
DRM_ERROR("Failed to release power domain: %d\n", ret);
}
+static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
+{
+ u32 csc_ctl;
+
+ csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
+ VC4_HD_CSC_CTL_ORDER);
+
+ if (enable) {
+ /* CEA VICs other than #1 requre limited range RGB
+* output unless overridden by an AVI infoframe.
+* Apply a colorspace conversion to squash 0-255 down
+* to 16-235. The matrix here is:
+*
+* [ 0 0 0.8594 16]
+* [ 0 0.8594 0 16]
+* [ 0.8594 0 0 16]
+* [ 0 0 0 1]
+*/
+ csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
+ csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
+ csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
+VC4_HD_CSC_CTL_MODE);
+
+ HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
+ HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
+ HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
+ HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
+ HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
+ HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
+ }
+
+ /* The RGB order applies even when CSC is disabled. */
+ HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
+}
+
static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
{
struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
@@ -357,7 +392,6 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
mode->crtc_vsync_end -
interlaced,
VC4_HDMI_VERTB_VBP));
- u32 csc_ctl;
int ret;
ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev);
@@ -428,41 +462,20 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
(vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
(hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
- csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
- VC4_HD_CSC_CTL_ORDER);
if (vc4_encoder->hdmi_monitor &&
- drm_default_rgb_quant_range(mode) ==
- HDMI_QUANTIZATION_RANGE_LIMITED) {
- /* CEA VICs other than #1 requre limited range RGB
-* output unless overridden by an AVI infoframe.
-* Apply a colorspace conversion to squash 0-255 down
-* to 16-235. The matrix here is:
-*
-* [ 0 0 0.8594 16]
-* [ 0 0.8594 0 16]
-* [ 0.8594 0 0 16]
-* [ 0 0 0 1]
-*/
- csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
- csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
- csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
-VC4_HD_CSC_CTL_MODE);
+ drm_default_rgb_quant_range(mode) ==
HDMI_QUANTIZATION_RANGE_LIMITED) {
+ if (vc4_hdmi->variant->csc_setup)
+ vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
- HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
- HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
- HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
- HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
- HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
- HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
vc4_encoder->limited_rgb_range = true;
} else {
+ if (vc4_hdmi->variant->csc_setup)
+ vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
+
vc4_encoder->limited_rgb_range = false;
}
- /* The RGB order applies even when CSC is disabled. */
- HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
-
HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
[PATCH v5 48/80] drm/vc4: hdmi: Remove vc4_dev hdmi pointer
Now that we don't have any users anymore, we can kill that pointer.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_drv.h | 1 -
drivers/gpu/drm/vc4/vc4_hdmi.c | 7 ---
2 files changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 1a97545b9244..501a48a714d3 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -73,7 +73,6 @@ struct vc4_perfmon {
struct vc4_dev {
struct drm_device *dev;
- struct vc4_hdmi *hdmi;
struct vc4_hvs *hvs;
struct vc4_v3d *v3d;
struct vc4_dpi *dpi;
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index e0dc823c622a..912560d58448 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1188,7 +1188,6 @@ static int vc4_hdmi_bind(struct device *dev, struct
device *master, void *data)
#endif
struct platform_device *pdev = to_platform_device(dev);
struct drm_device *drm = dev_get_drvdata(master);
- struct vc4_dev *vc4 = drm->dev_private;
struct vc4_hdmi *vc4_hdmi;
struct drm_encoder *encoder;
struct device_node *ddc_node;
@@ -1279,8 +1278,6 @@ static int vc4_hdmi_bind(struct device *dev, struct
device *master, void *data)
vc4_hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
}
- vc4->hdmi = vc4_hdmi;
-
/* HDMI core must be enabled. */
if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
@@ -1360,8 +1357,6 @@ static int vc4_hdmi_bind(struct device *dev, struct
device *master, void *data)
static void vc4_hdmi_unbind(struct device *dev, struct device *master,
void *data)
{
- struct drm_device *drm = dev_get_drvdata(master);
- struct vc4_dev *vc4 = drm->dev_private;
struct vc4_hdmi *vc4_hdmi;
/*
@@ -1393,8 +1388,6 @@ static void vc4_hdmi_unbind(struct device *dev, struct
device *master,
pm_runtime_disable(dev);
put_device(&vc4_hdmi->ddc->dev);
-
- vc4->hdmi = NULL;
}
static const struct component_ops vc4_hdmi_ops = {
--
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[PATCH v5 22/80] drm/vc4: crtc: Move HVS init and close to a function
In order to make further refactoring easier, let's move the HVS channel
setup / teardown to their own function.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hvs.c | 104 +++
1 file changed, 58 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index fa61cad3a53d..dde931233d4a 100644
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -196,6 +196,62 @@ static void vc4_hvs_update_gamma_lut(struct drm_crtc *crtc)
vc4_hvs_lut_load(crtc);
}
+static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct drm_crtc *crtc,
+ struct drm_display_mode *mode, bool oneshot)
+{
+ struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
+ unsigned int chan = vc4_crtc_state->assigned_channel;
+ u32 dispctrl;
+
+ /* Turn on the scaler, which will wait for vstart to start
+* compositing.
+* When feeding the transposer, we should operate in oneshot
+* mode.
+*/
+ dispctrl = SCALER_DISPCTRLX_ENABLE;
+
+ if (!vc4->hvs->hvs5)
+ dispctrl |= VC4_SET_FIELD(mode->hdisplay,
+ SCALER_DISPCTRLX_WIDTH) |
+ VC4_SET_FIELD(mode->vdisplay,
+ SCALER_DISPCTRLX_HEIGHT) |
+ (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0);
+ else
+ dispctrl |= VC4_SET_FIELD(mode->hdisplay,
+ SCALER5_DISPCTRLX_WIDTH) |
+ VC4_SET_FIELD(mode->vdisplay,
+ SCALER5_DISPCTRLX_HEIGHT) |
+ (oneshot ? SCALER5_DISPCTRLX_ONESHOT : 0);
+
+ HVS_WRITE(SCALER_DISPCTRLX(chan), dispctrl);
+
+ return 0;
+}
+
+static void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int chan)
+{
+ struct vc4_dev *vc4 = to_vc4_dev(dev);
+
+ if (HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_ENABLE)
+ return;
+
+ HVS_WRITE(SCALER_DISPCTRLX(chan),
+ HVS_READ(SCALER_DISPCTRLX(chan)) | SCALER_DISPCTRLX_RESET);
+ HVS_WRITE(SCALER_DISPCTRLX(chan),
+ HVS_READ(SCALER_DISPCTRLX(chan)) & ~SCALER_DISPCTRLX_ENABLE);
+
+ /* Once we leave, the scaler should be disabled and its fifo empty. */
+ WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
+
+ WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
+ SCALER_DISPSTATX_MODE) !=
+SCALER_DISPSTATX_MODE_DISABLED);
+
+ WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
+ (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
+SCALER_DISPSTATX_EMPTY);
+}
+
int vc4_hvs_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
@@ -268,63 +324,19 @@ void vc4_hvs_atomic_enable(struct drm_crtc *crtc,
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
struct drm_display_mode *mode = &crtc->state->adjusted_mode;
bool oneshot = vc4_state->feed_txp;
- u32 dispctrl;
vc4_hvs_update_dlist(crtc);
-
- /* Turn on the scaler, which will wait for vstart to start
-* compositing.
-* When feeding the transposer, we should operate in oneshot
-* mode.
-*/
- dispctrl = SCALER_DISPCTRLX_ENABLE;
-
- if (!vc4->hvs->hvs5)
- dispctrl |= VC4_SET_FIELD(mode->hdisplay,
- SCALER_DISPCTRLX_WIDTH) |
- VC4_SET_FIELD(mode->vdisplay,
- SCALER_DISPCTRLX_HEIGHT) |
- (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0);
- else
- dispctrl |= VC4_SET_FIELD(mode->hdisplay,
- SCALER5_DISPCTRLX_WIDTH) |
- VC4_SET_FIELD(mode->vdisplay,
- SCALER5_DISPCTRLX_HEIGHT) |
- (oneshot ? SCALER5_DISPCTRLX_ONESHOT : 0);
-
- HVS_WRITE(SCALER_DISPCTRLX(vc4_state->assigned_channel), dispctrl);
+ vc4_hvs_init_channel(vc4, crtc, mode, oneshot);
}
void vc4_hvs_atomic_disable(struct drm_crtc *crtc,
struct drm_crtc_state *old_state)
{
struct drm_device *dev = crtc->dev;
- struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(old_state);
unsigned int chan = vc4_state->assigned_channel;
- if (HVS_READ(SCALER_DISPCTRLX(chan)) &
- SCALER_DISPCTRLX_ENABLE) {
- HVS_WRITE(SCALER_DISPCTRLX(chan),
-
[PATCH v5 02/80] drm/vc4: Add support for the BCM2711 HVS5
From: Dave Stevenson
The HVS found in the BCM2711 is slightly different from the previous
generations.
Most notably, the display list layout changes a bit, the LBM doesn't have
the same size and the formats ordering for some formats is swapped.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_drv.h | 4 +-
drivers/gpu/drm/vc4/vc4_hvs.c | 34 --
drivers/gpu/drm/vc4/vc4_plane.c | 194 -
drivers/gpu/drm/vc4/vc4_regs.h | 67 +++-
4 files changed, 240 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index fa19160c801f..e4cde1f9224b 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -329,7 +329,11 @@ struct vc4_hvs {
spinlock_t mm_lock;
struct drm_mm_node mitchell_netravali_filter;
+
struct debugfs_regset32 regset;
+
+ /* HVS version 5 flag, therefore requires updated dlist structures */
+ bool hvs5;
};
struct vc4_plane {
diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index 2d2bf59c0503..836d8799d79e 100644
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -277,11 +277,19 @@ void vc4_hvs_atomic_enable(struct drm_crtc *crtc,
* mode.
*/
dispctrl = SCALER_DISPCTRLX_ENABLE;
- dispctrl |= VC4_SET_FIELD(mode->hdisplay,
- SCALER_DISPCTRLX_WIDTH) |
- VC4_SET_FIELD(mode->vdisplay,
- SCALER_DISPCTRLX_HEIGHT) |
- (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0);
+
+ if (!vc4->hvs->hvs5)
+ dispctrl |= VC4_SET_FIELD(mode->hdisplay,
+ SCALER_DISPCTRLX_WIDTH) |
+ VC4_SET_FIELD(mode->vdisplay,
+ SCALER_DISPCTRLX_HEIGHT) |
+ (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0);
+ else
+ dispctrl |= VC4_SET_FIELD(mode->hdisplay,
+ SCALER5_DISPCTRLX_WIDTH) |
+ VC4_SET_FIELD(mode->vdisplay,
+ SCALER5_DISPCTRLX_HEIGHT) |
+ (oneshot ? SCALER5_DISPCTRLX_ONESHOT : 0);
HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel), dispctrl);
}
@@ -521,6 +529,9 @@ static int vc4_hvs_bind(struct device *dev, struct device
*master, void *data)
hvs->pdev = pdev;
+ if (of_device_is_compatible(pdev->dev.of_node, "brcm,bcm2711-hvs"))
+ hvs->hvs5 = true;
+
hvs->regs = vc4_ioremap_regs(pdev, 0);
if (IS_ERR(hvs->regs))
return PTR_ERR(hvs->regs);
@@ -529,7 +540,10 @@ static int vc4_hvs_bind(struct device *dev, struct device
*master, void *data)
hvs->regset.regs = hvs_regs;
hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
- hvs->dlist = hvs->regs + SCALER_DLIST_START;
+ if (!hvs->hvs5)
+ hvs->dlist = hvs->regs + SCALER_DLIST_START;
+ else
+ hvs->dlist = hvs->regs + SCALER5_DLIST_START;
spin_lock_init(&hvs->mm_lock);
@@ -547,7 +561,12 @@ static int vc4_hvs_bind(struct device *dev, struct device
*master, void *data)
* between planes when they don't overlap on the screen, but
* for now we just allocate globally.
*/
- drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
+ if (!hvs->hvs5)
+ /* 96kB */
+ drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
+ else
+ /* 70k words */
+ drm_mm_init(&hvs->lbm_mm, 0, 70 * 2 * 1024);
/* Upload filter kernels. We only have the one for now, so we
* keep it around for the lifetime of the driver.
@@ -632,6 +651,7 @@ static int vc4_hvs_dev_remove(struct platform_device *pdev)
}
static const struct of_device_id vc4_hvs_dt_match[] = {
+ { .compatible = "brcm,bcm2711-hvs" },
{ .compatible = "brcm,bcm2835-hvs" },
{}
};
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index d040d9f12c6d..20c949b57827 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -32,45 +32,60 @@ static const struct hvs_format {
u32 drm; /* DRM_FORMAT_* */
u32 hvs; /* HVS_FORMAT_* */
u32 pixel_order;
+ u32 pixel_order_hvs5;
} hvs_formats[] = {
{
- .drm = DRM_FORMAT_XRGB, .hvs = HVS_PIXEL_FORMAT_RGBA,
+ .drm = DRM_FORMAT_XRGB,
+ .hvs = HVS_PIXEL_FORMAT_RGBA,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
},
{
- .drm = DRM_FORMAT_ARGB, .hvs = HVS_PIXEL_FORMAT_RGB
[PATCH v5 53/80] drm/vc4: hdmi: Add PHY init and disable function
The HDMI PHY in the BCM2711 HDMI controller is significantly more
complicated to setup than in the older BCM283x SoCs.
Let's add hooks to enable and disable the PHY.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/Makefile | 1 +
drivers/gpu/drm/vc4/vc4_hdmi.c | 14 +++---
drivers/gpu/drm/vc4/vc4_hdmi.h | 13 +
drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 25 +
4 files changed, 46 insertions(+), 7 deletions(-)
create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi_phy.c
diff --git a/drivers/gpu/drm/vc4/Makefile b/drivers/gpu/drm/vc4/Makefile
index b303703bc7f3..d0163e18e9ca 100644
--- a/drivers/gpu/drm/vc4/Makefile
+++ b/drivers/gpu/drm/vc4/Makefile
@@ -12,6 +12,7 @@ vc4-y := \
vc4_kms.o \
vc4_gem.o \
vc4_hdmi.o \
+ vc4_hdmi_phy.o \
vc4_vec.o \
vc4_hvs.o \
vc4_irq.o \
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 77971be075ec..f3cc612f6a0b 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -321,7 +321,9 @@ static void vc4_hdmi_encoder_disable(struct drm_encoder
*encoder)
HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
- HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0xf << 16);
+ if (vc4_hdmi->variant->phy_disable)
+ vc4_hdmi->variant->phy_disable(vc4_hdmi);
+
HDMI_WRITE(HDMI_VID_CTL,
HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
@@ -381,12 +383,8 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
if (vc4_hdmi->variant->reset)
vc4_hdmi->variant->reset(vc4_hdmi);
- /* PHY should be in reset, like
-* vc4_hdmi_encoder_disable() does.
-*/
- HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0xf << 16);
-
- HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0);
+ if (vc4_hdmi->variant->phy_init)
+ vc4_hdmi->variant->phy_init(vc4_hdmi, mode);
if (debug_dump_regs) {
struct drm_printer p = drm_info_printer(&vc4_hdmi->pdev->dev);
@@ -1432,6 +1430,8 @@ static const struct vc4_hdmi_variant bcm2835_variant = {
.init_resources = vc4_hdmi_init_resources,
.reset = vc4_hdmi_reset,
+ .phy_init = vc4_hdmi_phy_init,
+ .phy_disable= vc4_hdmi_phy_disable,
};
static const struct of_device_id vc4_hdmi_dt_match[] = {
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index 17a30589f39c..32c80161c786 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -21,6 +21,8 @@ to_vc4_hdmi_encoder(struct drm_encoder *encoder)
return container_of(encoder, struct vc4_hdmi_encoder, base.base);
}
+struct drm_display_mode;
+
struct vc4_hdmi;
struct vc4_hdmi_register;
@@ -38,6 +40,13 @@ struct vc4_hdmi_variant {
/* Callback to reset the HDMI block */
void (*reset)(struct vc4_hdmi *vc4_hdmi);
+
+ /* Callback to initialize the PHY according to the mode */
+ void (*phy_init)(struct vc4_hdmi *vc4_hdmi,
+struct drm_display_mode *mode);
+
+ /* Callback to disable the PHY */
+ void (*phy_disable)(struct vc4_hdmi *vc4_hdmi);
};
/* HDMI audio information */
@@ -95,4 +104,8 @@ encoder_to_vc4_hdmi(struct drm_encoder *encoder)
return container_of(_encoder, struct vc4_hdmi, encoder);
}
+void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
+ struct drm_display_mode *mode);
+void vc4_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi);
+
#endif /* _VC4_HDMI_H_ */
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
b/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
new file mode 100644
index ..5a1746877bb5
--- /dev/null
+++ b/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 Broadcom
+ * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark
+ */
+
+#include "vc4_hdmi.h"
+#include "vc4_hdmi_regs.h"
+
+void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi, struct drm_display_mode
*mode)
+{
+ /* PHY should be in reset, like
+* vc4_hdmi_encoder_disable() does.
+*/
+
+ HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0xf << 16);
+ HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0);
+}
+
+void vc4_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi)
+{
+ HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0xf << 16);
+}
--
git-series 0.9.1
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 29/80] drm/vc4: crtc: Add a delay after disabling the PixelValve output
In order to avoid pixels getting stuck in the (unflushable) FIFO between the HVS and the PV, we need to add some delay after disabling the PV output and before disabling the HDMI controller. 20ms seems to be good enough so let's use that. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index d0b326e1df0a..4c23cf8aefb9 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -403,6 +403,24 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); + /* +* This delay is needed to avoid to get a pixel stuck in an +* unflushable FIFO between the pixelvalve and the HDMI +* controllers on the BCM2711. +* +* Timing is fairly sensitive here, so mdelay is the safest +* approach. +* +* If it was to be reworked, the stuck pixel happens on a +* BCM2711 when changing mode with a good probability, so a +* script that changes mode on a regular basis should trigger +* the bug after less than 10 attempts. It manifests itself with +* every pixels being shifted by one to the right, and thus the +* last pixel of a line actually being displayed as the first +* pixel on the next line. +*/ + mdelay(20); + if (vc4_encoder->post_crtc_disable) vc4_encoder->post_crtc_disable(encoder); -- git-series 0.9.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 50/80] drm/vc4: hdmi: Introduce resource init and variant
The HDMI controllers found in the BCM2711 has a pretty different clock and
registers areas than found in the older BCM283x SoCs.
Let's create a variant structure to store the various adjustments we'll
need later on, and a function to get the resources needed for one
particular version.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 61 +++
drivers/gpu/drm/vc4/vc4_hdmi.h | 10 ++-
2 files changed, 51 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 5c5684f91b69..c40050b908b5 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1178,28 +1178,12 @@ static const struct cec_adap_ops vc4_hdmi_cec_adap_ops
= {
};
#endif
-static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
+static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
{
-#ifdef CONFIG_DRM_VC4_HDMI_CEC
- struct cec_connector_info conn_info;
-#endif
- struct platform_device *pdev = to_platform_device(dev);
- struct drm_device *drm = dev_get_drvdata(master);
- struct vc4_hdmi *vc4_hdmi;
- struct drm_encoder *encoder;
- struct device_node *ddc_node;
- u32 value;
+ struct platform_device *pdev = vc4_hdmi->pdev;
+ struct device *dev = &pdev->dev;
int ret;
- vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
- if (!vc4_hdmi)
- return -ENOMEM;
-
- dev_set_drvdata(dev, vc4_hdmi);
- encoder = &vc4_hdmi->encoder.base.base;
- vc4_hdmi->encoder.base.type = VC4_ENCODER_TYPE_HDMI0;
- vc4_hdmi->pdev = pdev;
-
vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
if (IS_ERR(vc4_hdmi->hdmicore_regs))
return PTR_ERR(vc4_hdmi->hdmicore_regs);
@@ -1211,6 +1195,7 @@ static int vc4_hdmi_bind(struct device *dev, struct
device *master, void *data)
vc4_hdmi->hdmi_regset.base = vc4_hdmi->hdmicore_regs;
vc4_hdmi->hdmi_regset.regs = hdmi_regs;
vc4_hdmi->hdmi_regset.nregs = ARRAY_SIZE(hdmi_regs);
+
vc4_hdmi->hd_regset.base = vc4_hdmi->hd_regs;
vc4_hdmi->hd_regset.regs = hd_regs;
vc4_hdmi->hd_regset.nregs = ARRAY_SIZE(hd_regs);
@@ -1222,12 +1207,44 @@ static int vc4_hdmi_bind(struct device *dev, struct
device *master, void *data)
DRM_ERROR("Failed to get pixel clock\n");
return ret;
}
+
vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
if (IS_ERR(vc4_hdmi->hsm_clock)) {
DRM_ERROR("Failed to get HDMI state machine clock\n");
return PTR_ERR(vc4_hdmi->hsm_clock);
}
+ return 0;
+}
+
+static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
+{
+#ifdef CONFIG_DRM_VC4_HDMI_CEC
+ struct cec_connector_info conn_info;
+#endif
+ const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
+ struct platform_device *pdev = to_platform_device(dev);
+ struct drm_device *drm = dev_get_drvdata(master);
+ struct vc4_hdmi *vc4_hdmi;
+ struct drm_encoder *encoder;
+ struct device_node *ddc_node;
+ u32 value;
+ int ret;
+
+ vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
+ if (!vc4_hdmi)
+ return -ENOMEM;
+
+ dev_set_drvdata(dev, vc4_hdmi);
+ encoder = &vc4_hdmi->encoder.base.base;
+ vc4_hdmi->encoder.base.type = VC4_ENCODER_TYPE_HDMI0;
+ vc4_hdmi->pdev = pdev;
+ vc4_hdmi->variant = variant;
+
+ ret = variant->init_resources(vc4_hdmi);
+ if (ret)
+ return ret;
+
ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
if (!ddc_node) {
DRM_ERROR("Failed to find ddc node in device tree\n");
@@ -1403,8 +1420,12 @@ static int vc4_hdmi_dev_remove(struct platform_device
*pdev)
return 0;
}
+static const struct vc4_hdmi_variant bcm2835_variant = {
+ .init_resources = vc4_hdmi_init_resources,
+};
+
static const struct of_device_id vc4_hdmi_dt_match[] = {
- { .compatible = "brcm,bcm2835-hdmi" },
+ { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
{}
};
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index 674541493909..0eaf979fe811 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -21,6 +21,15 @@ to_vc4_hdmi_encoder(struct drm_encoder *encoder)
return container_of(encoder, struct vc4_hdmi_encoder, base.base);
}
+struct vc4_hdmi;
+
+struct vc4_hdmi_variant {
+ /* Callback to get the resources (memory region, interrupts,
+* clocks, etc) for that variant.
+*/
+ int (*init_resources)(struct vc4_hdmi *vc4_hdmi);
+};
+
/* HDMI audio informati
[PATCH 1/3] drm/v3d: Don't resubmit guilty CSD jobs
From: Yukimasa Sugizaki
The previous code misses a check for the timeout error set by
drm_sched_resubmit_jobs(), which results in an infinite GPU reset loop
if once a timeout occurs:
[ 178.799106] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* Resetting GPU
for hang.
[ 178.807836] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* V3D_ERR_STAT:
0x1000
[ 179.839132] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* Resetting GPU
for hang.
[ 179.847865] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* V3D_ERR_STAT:
0x1000
[ 180.879146] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* Resetting GPU
for hang.
[ 180.887925] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* V3D_ERR_STAT:
0x1000
[ 181.919188] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* Resetting GPU
for hang.
[ 181.928002] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* V3D_ERR_STAT:
0x1000
...
This commit adds the check for timeout as in v3d_{bin,render}_job_run():
[ 66.408962] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* Resetting GPU
for hang.
[ 66.417734] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* V3D_ERR_STAT:
0x1000
[ 66.428296] [drm] Skipping CSD job resubmission due to previous error (-125)
, where -125 is -ECANCELED, though users currently have no way other
than inspecting the dmesg to check if the timeout has occurred.
Signed-off-by: Yukimasa Sugizaki
---
drivers/gpu/drm/v3d/v3d_sched.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/v3d/v3d_sched.c b/drivers/gpu/drm/v3d/v3d_sched.c
index 0747614a78f0..001216f22017 100644
--- a/drivers/gpu/drm/v3d/v3d_sched.c
+++ b/drivers/gpu/drm/v3d/v3d_sched.c
@@ -226,6 +226,17 @@ v3d_csd_job_run(struct drm_sched_job *sched_job)
struct dma_fence *fence;
int i;
+ /* This error is set to -ECANCELED by drm_sched_resubmit_jobs() if this
+* job timed out more than sched_job->sched->hang_limit times.
+*/
+ int error = sched_job->s_fence->finished.error;
+
+ if (unlikely(error < 0)) {
+ DRM_WARN("Skipping CSD job resubmission due to previous error
(%d)\n",
+error);
+ return ERR_PTR(error);
+ }
+
v3d->csd_job = job;
v3d_invalidate_caches(v3d);
--
2.7.4
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[PATCH v5 26/80] drm/vc4: crtc: Remove redundant pixelvalve reset
Since we moved the pixelvalve configuration to atomic_enable, we're now first calling the function that resets the pixelvalve and then the one that configures it. However, the first thing the latter is doing is calling the reset function, meaning that we reset twice our pixelvalve. Let's remove the first call. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 2eda2e6429ec..2c5ff45dc315 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -427,7 +427,6 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc, require_hvs_enabled(dev); - vc4_crtc_pixelvalve_reset(crtc); vc4_crtc_config_pv(crtc); CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN); -- git-series 0.9.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 51/80] drm/vc4: hdmi: Implement a register layout abstraction
The HDMI controllers found in the BCM2711 have most of the registers
reorganized in multiple registers areas and at different offsets than
previously found.
The logic however remains pretty much the same, so it doesn't really make
sense to create a whole new driver and we should share the code as much as
possible.
Let's implement some indirection to wrap around a register and depending on
the variant will lookup the associated register on that particular variant.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 427 ++---
drivers/gpu/drm/vc4/vc4_hdmi.h | 12 +-
drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 241 -
drivers/gpu/drm/vc4/vc4_regs.h | 92 +--
4 files changed, 464 insertions(+), 308 deletions(-)
create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi_regs.h
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index c40050b908b5..adc7c0693650 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -50,62 +50,13 @@
#include "media/cec.h"
#include "vc4_drv.h"
#include "vc4_hdmi.h"
+#include "vc4_hdmi_regs.h"
#include "vc4_regs.h"
#define HSM_CLOCK_FREQ 163682864
#define CEC_CLOCK_FREQ 4
#define CEC_CLOCK_DIV (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ)
-static const struct debugfs_reg32 hdmi_regs[] = {
- VC4_REG32(VC4_HDMI_CORE_REV),
- VC4_REG32(VC4_HDMI_SW_RESET_CONTROL),
- VC4_REG32(VC4_HDMI_HOTPLUG_INT),
- VC4_REG32(VC4_HDMI_HOTPLUG),
- VC4_REG32(VC4_HDMI_MAI_CHANNEL_MAP),
- VC4_REG32(VC4_HDMI_MAI_CONFIG),
- VC4_REG32(VC4_HDMI_MAI_FORMAT),
- VC4_REG32(VC4_HDMI_AUDIO_PACKET_CONFIG),
- VC4_REG32(VC4_HDMI_RAM_PACKET_CONFIG),
- VC4_REG32(VC4_HDMI_HORZA),
- VC4_REG32(VC4_HDMI_HORZB),
- VC4_REG32(VC4_HDMI_FIFO_CTL),
- VC4_REG32(VC4_HDMI_SCHEDULER_CONTROL),
- VC4_REG32(VC4_HDMI_VERTA0),
- VC4_REG32(VC4_HDMI_VERTA1),
- VC4_REG32(VC4_HDMI_VERTB0),
- VC4_REG32(VC4_HDMI_VERTB1),
- VC4_REG32(VC4_HDMI_TX_PHY_RESET_CTL),
- VC4_REG32(VC4_HDMI_TX_PHY_CTL0),
-
- VC4_REG32(VC4_HDMI_CEC_CNTRL_1),
- VC4_REG32(VC4_HDMI_CEC_CNTRL_2),
- VC4_REG32(VC4_HDMI_CEC_CNTRL_3),
- VC4_REG32(VC4_HDMI_CEC_CNTRL_4),
- VC4_REG32(VC4_HDMI_CEC_CNTRL_5),
- VC4_REG32(VC4_HDMI_CPU_STATUS),
- VC4_REG32(VC4_HDMI_CPU_MASK_STATUS),
-
- VC4_REG32(VC4_HDMI_CEC_RX_DATA_1),
- VC4_REG32(VC4_HDMI_CEC_RX_DATA_2),
- VC4_REG32(VC4_HDMI_CEC_RX_DATA_3),
- VC4_REG32(VC4_HDMI_CEC_RX_DATA_4),
- VC4_REG32(VC4_HDMI_CEC_TX_DATA_1),
- VC4_REG32(VC4_HDMI_CEC_TX_DATA_2),
- VC4_REG32(VC4_HDMI_CEC_TX_DATA_3),
- VC4_REG32(VC4_HDMI_CEC_TX_DATA_4),
-};
-
-static const struct debugfs_reg32 hd_regs[] = {
- VC4_REG32(VC4_HD_M_CTL),
- VC4_REG32(VC4_HD_MAI_CTL),
- VC4_REG32(VC4_HD_MAI_THR),
- VC4_REG32(VC4_HD_MAI_FMT),
- VC4_REG32(VC4_HD_MAI_SMP),
- VC4_REG32(VC4_HD_VID_CTL),
- VC4_REG32(VC4_HD_CSC_CTL),
- VC4_REG32(VC4_HD_FRAME_COUNT),
-};
-
static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
{
struct drm_info_node *node = (struct drm_info_node *)m->private;
@@ -134,7 +85,7 @@ vc4_hdmi_connector_detect(struct drm_connector *connector,
bool force)
if (drm_probe_ddc(vc4_hdmi->ddc))
return connector_status_connected;
- if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
+ if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
return connector_status_connected;
cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
return connector_status_disconnected;
@@ -223,10 +174,10 @@ static int vc4_hdmi_stop_packet(struct drm_encoder
*encoder,
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
u32 packet_id = type - 0x80;
- HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
- HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
+ HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
+ HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
- return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
+ return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
BIT(packet_id)), 100);
}
@@ -235,12 +186,16 @@ static void vc4_hdmi_write_infoframe(struct drm_encoder
*encoder,
{
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
u32 packet_id = frame->any.type - 0x80;
- u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id);
+ const struct vc4_hdmi_register *ram_packet_start =
+ &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
+ u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE *
packet_id;
+ void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
+
[PATCH v5 47/80] drm/vc4: hdmi: Retrieve the vc4_hdmi at unbind using our device
The unbind function needs to retrieve a vc4_hdmi structure pointer through
the struct device that we're given since we want to support multiple HDMI
controllers.
However, our optional ASoC support doesn't make that trivial since it will
overwrite the device drvdata if we use it, but obviously won't if we don't
use it.
Let's make sure the fields are at the proper offset to be able to cast
between the snd_soc_card structure and the vc4_hdmi structure
transparently so we can support both cases.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 24 +++-
drivers/gpu/drm/vc4/vc4_hdmi.h | 4 ++--
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 44126ae55a19..e0dc823c622a 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1199,6 +1199,7 @@ static int vc4_hdmi_bind(struct device *dev, struct
device *master, void *data)
if (!vc4_hdmi)
return -ENOMEM;
+ dev_set_drvdata(dev, vc4_hdmi);
encoder = &vc4_hdmi->encoder.base.base;
vc4_hdmi->encoder.base.type = VC4_ENCODER_TYPE_HDMI0;
vc4_hdmi->pdev = pdev;
@@ -1361,7 +1362,28 @@ static void vc4_hdmi_unbind(struct device *dev, struct
device *master,
{
struct drm_device *drm = dev_get_drvdata(master);
struct vc4_dev *vc4 = drm->dev_private;
- struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
+ struct vc4_hdmi *vc4_hdmi;
+
+ /*
+* ASoC makes it a bit hard to retrieve a pointer to the
+* vc4_hdmi structure. Registering the card will overwrite our
+* device drvdata with a pointer to the snd_soc_card structure,
+* which can then be used to retrieve whatever drvdata we want
+* to associate.
+*
+* However, that doesn't fly in the case where we wouldn't
+* register an ASoC card (because of an old DT that is missing
+* the dmas properties for example), then the card isn't
+* registered and the device drvdata wouldn't be set.
+*
+* We can deal with both cases by making sure a snd_soc_card
+* pointer and a vc4_hdmi structure are pointing to the same
+* memory address, so we can treat them indistinctly without any
+* issue.
+*/
+ BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
+ BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
+ vc4_hdmi = dev_get_drvdata(dev);
cec_unregister_adapter(vc4_hdmi->cec_adap);
vc4_hdmi_connector_destroy(&vc4_hdmi->connector.base);
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index 749a807cd1f3..d43462789450 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -53,13 +53,13 @@ struct vc4_hdmi_audio {
/* General HDMI hardware state. */
struct vc4_hdmi {
+ struct vc4_hdmi_audio audio;
+
struct platform_device *pdev;
struct vc4_hdmi_encoder encoder;
struct vc4_hdmi_connector connector;
- struct vc4_hdmi_audio audio;
-
struct i2c_adapter *ddc;
void __iomem *hdmicore_regs;
void __iomem *hd_regs;
--
git-series 0.9.1
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[PATCH v5 75/80] drm/vc4: hdmi: Add pixel BVB clock control
From: Hoegeun Kwon
The BCM2711 has another clock that needs to be ramped up depending on the
pixel rate: the pixel BVB clock. Add the code to adjust that clock when
changing the mode.
Signed-off-by: Hoegeun Kwon
[Maxime: Changed the commit log, used clk_set_min_rate]
Signed-off-by: Maxime Ripard
Link: https://lore.kernel.org/r/20200901040759.29992-3-hoegeun.k...@samsung.com
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 23 +++
drivers/gpu/drm/vc4/vc4_hdmi.h | 1 +
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index ab7abb409de2..39508107dafd 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -54,6 +54,7 @@
#include "vc4_regs.h"
#define CEC_CLOCK_FREQ 4
+#define VC4_HSM_MID_CLOCK 149985000
static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
{
@@ -344,6 +345,7 @@ static void vc4_hdmi_encoder_post_crtc_powerdown(struct
drm_encoder *encoder)
HDMI_WRITE(HDMI_VID_CTL,
HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
+ clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
clk_disable_unprepare(vc4_hdmi->hsm_clock);
clk_disable_unprepare(vc4_hdmi->pixel_clock);
@@ -516,6 +518,27 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct
drm_encoder *encoder)
return;
}
+ /*
+* FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup
+* at 150MHz.
+*/
+ ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock,
+ (hsm_rate > VC4_HSM_MID_CLOCK ? 15000 :
7500));
+ if (ret) {
+ DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
+ clk_disable_unprepare(vc4_hdmi->hsm_clock);
+ clk_disable_unprepare(vc4_hdmi->pixel_clock);
+ return;
+ }
+
+ ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
+ if (ret) {
+ DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
+ clk_disable_unprepare(vc4_hdmi->hsm_clock);
+ clk_disable_unprepare(vc4_hdmi->pixel_clock);
+ return;
+ }
+
if (vc4_hdmi->variant->reset)
vc4_hdmi->variant->reset(vc4_hdmi);
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index 34138e0dd4a6..59639b405b7f 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -119,6 +119,7 @@ struct vc4_hdmi {
struct clk *pixel_clock;
struct clk *hsm_clock;
struct clk *audio_clock;
+ struct clk *pixel_bvb_clock;
struct debugfs_regset32 hdmi_regset;
struct debugfs_regset32 hd_regset;
--
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[PATCH v5 61/80] drm/vc4: hdmi: Remove unused CEC_CLOCK_DIV define
The CEC_CLOCK_DIV define is not used anywhere in the driver, let's remove
it.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index a26b6bd61f74..e39c6fcf4c12 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -55,7 +55,6 @@
#define HSM_CLOCK_FREQ 163682864
#define CEC_CLOCK_FREQ 4
-#define CEC_CLOCK_DIV (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ)
static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
{
--
git-series 0.9.1
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Re: [PATCH v5 0/7] make hdmi work on bananapi-r2
Hi Any opinion about DTS Patches? Which maintainer will include it in tree? Is any ack/review needed? regards Frank ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 37/80] drm/vc4: crtc: Add BCM2711 pixelvalves
The BCM2711 has 5 pixelvalves, so now that our driver is ready, let's add
support for them.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 95 ++-
drivers/gpu/drm/vc4/vc4_regs.h | 7 +++-
2 files changed, 100 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index dfac304fe2b0..a393f93390a2 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -208,6 +208,7 @@ void vc4_crtc_destroy(struct drm_crtc *crtc)
static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
{
+ const struct vc4_crtc_data *crtc_data =
vc4_crtc_to_vc4_crtc_data(vc4_crtc);
const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
u32 fifo_len_bytes = pv_data->fifo_depth;
@@ -230,6 +231,13 @@ static u32 vc4_get_fifo_full_level(struct vc4_crtc
*vc4_crtc, u32 format)
case PV_CONTROL_FORMAT_24:
case PV_CONTROL_FORMAT_DSIV_24:
default:
+ /*
+* For some reason, the pixelvalve4 doesn't work with
+* the usual formula and will only work with 32.
+*/
+ if (crtc_data->hvs_output == 5)
+ return 32;
+
return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
}
}
@@ -238,9 +246,13 @@ static u32 vc4_crtc_get_fifo_full_level_bits(struct
vc4_crtc *vc4_crtc,
u32 format)
{
u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
+ u32 ret = 0;
+
+ ret |= VC4_SET_FIELD((level >> 6),
+PV5_CONTROL_FIFO_LEVEL_HIGH);
- return VC4_SET_FIELD(level & 0x3f,
-PV_CONTROL_FIFO_LEVEL);
+ return ret | VC4_SET_FIELD(level & 0x3f,
+ PV_CONTROL_FIFO_LEVEL);
}
/*
@@ -278,6 +290,8 @@ static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc)
static void vc4_crtc_config_pv(struct drm_crtc *crtc)
{
+ struct drm_device *dev = crtc->dev;
+ struct vc4_dev *vc4 = to_vc4_dev(dev);
struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
@@ -358,6 +372,11 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
if (is_dsi)
CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
+ if (vc4->hvs->hvs5)
+ CRTC_WRITE(PV_MUX_CFG,
+ VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP,
+PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
+
CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR |
vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
@@ -907,10 +926,82 @@ static const struct vc4_pv_data bcm2835_pv2_data = {
},
};
+static const struct vc4_pv_data bcm2711_pv0_data = {
+ .base = {
+ .hvs_available_channels = BIT(0),
+ .hvs_output = 0,
+ },
+ .debugfs_name = "crtc0_regs",
+ .fifo_depth = 64,
+ .pixels_per_clock = 1,
+ .encoder_types = {
+ [0] = VC4_ENCODER_TYPE_DSI0,
+ [1] = VC4_ENCODER_TYPE_DPI,
+ },
+};
+
+static const struct vc4_pv_data bcm2711_pv1_data = {
+ .base = {
+ .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
+ .hvs_output = 3,
+ },
+ .debugfs_name = "crtc1_regs",
+ .fifo_depth = 64,
+ .pixels_per_clock = 1,
+ .encoder_types = {
+ [0] = VC4_ENCODER_TYPE_DSI1,
+ [1] = VC4_ENCODER_TYPE_SMI,
+ },
+};
+
+static const struct vc4_pv_data bcm2711_pv2_data = {
+ .base = {
+ .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
+ .hvs_output = 4,
+ },
+ .debugfs_name = "crtc2_regs",
+ .fifo_depth = 256,
+ .pixels_per_clock = 2,
+ .encoder_types = {
+ [0] = VC4_ENCODER_TYPE_HDMI0,
+ },
+};
+
+static const struct vc4_pv_data bcm2711_pv3_data = {
+ .base = {
+ .hvs_available_channels = BIT(1),
+ .hvs_output = 1,
+ },
+ .debugfs_name = "crtc3_regs",
+ .fifo_depth = 64,
+ .pixels_per_clock = 1,
+ .encoder_types = {
+ [0] = VC4_ENCODER_TYPE_VEC,
+ },
+};
+
+static const struct vc4_pv_data bcm2711_pv4_data = {
+ .base = {
+ .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
+ .hvs_output = 5,
+ },
+ .debugfs_name = "crtc4_regs",
+ .fifo_depth = 64,
+ .pixels_per_clock = 2,
+ .encoder_types = {
+ [0] = VC4_ENCODER_TYPE_HDMI1,
[PATCH v5 77/80] dt-bindings: display: vc4: hdmi: Add BCM2711 HDMI controllers bindings
The HDMI controllers found in the BCM2711 SoC need some adjustments to the
bindings, especially since the registers have been shuffled around in more
register ranges.
Reviewed-by: Rob Herring
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml | 117
-
1 file changed, 117 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml
diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml
b/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml
new file mode 100644
index ..03a76729d26c
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/brcm,bcm2711-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM2711 HDMI Controller Device Tree Bindings
+
+maintainers:
+ - Eric Anholt
+
+properties:
+ compatible:
+enum:
+ - brcm,bcm2711-hdmi0
+ - brcm,bcm2711-hdmi1
+
+ reg:
+items:
+ - description: HDMI controller register range
+ - description: DVP register range
+ - description: HDMI PHY register range
+ - description: Rate Manager register range
+ - description: Packet RAM register range
+ - description: Metadata RAM register range
+ - description: CSC register range
+ - description: CEC register range
+ - description: HD register range
+
+ reg-names:
+items:
+ - const: hdmi
+ - const: dvp
+ - const: phy
+ - const: rm
+ - const: packet
+ - const: metadata
+ - const: csc
+ - const: cec
+ - const: hd
+
+ clocks:
+items:
+ - description: The HDMI state machine clock
+ - description: The Pixel BVB clock
+ - description: The HDMI Audio parent clock
+ - description: The HDMI CEC parent clock
+
+ clock-names:
+items:
+ - const: hdmi
+ - const: bvb
+ - const: audio
+ - const: cec
+
+ ddc:
+allOf:
+ - $ref: /schemas/types.yaml#/definitions/phandle
+description: >
+ Phandle of the I2C controller used for DDC EDID probing
+
+ hpd-gpios:
+description: >
+ The GPIO pin for the HDMI hotplug detect (if it doesn't appear
+ as an interrupt/status bit in the HDMI controller itself)
+
+ dmas:
+maxItems: 1
+description: >
+ Should contain one entry pointing to the DMA channel used to
+ transfer audio data.
+
+ dma-names:
+const: audio-rx
+
+ resets:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - resets
+ - ddc
+
+additionalProperties: false
+
+examples:
+ - |
+hdmi0: hdmi@7ef00700 {
+compatible = "brcm,bcm2711-hdmi0";
+reg = <0x7ef00700 0x300>,
+ <0x7ef00300 0x200>,
+ <0x7ef00f00 0x80>,
+ <0x7ef00f80 0x80>,
+ <0x7ef01b00 0x200>,
+ <0x7ef01f00 0x400>,
+ <0x7ef00200 0x80>,
+ <0x7ef04300 0x100>,
+ <0x7ef2 0x100>;
+reg-names = "hdmi",
+"dvp",
+"phy",
+"rm",
+"packet",
+"metadata",
+"csc",
+"cec",
+"hd";
+clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>,
<&clk_27MHz>;
+clock-names = "hdmi", "bvb", "audio", "cec";
+resets = <&dvp 0>;
+ddc = <&ddc0>;
+};
+
+...
--
git-series 0.9.1
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[PATCH v5 13/80] drm/vc4: kms: Convert to for_each_new_crtc_state
The vc4 atomic commit loop has an handrolled loop that is basically
identical to for_each_new_crtc_state, let's convert it to that helper.
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_kms.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index 210cc2408087..a41d105d4e3c 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -152,14 +152,16 @@ vc4_atomic_complete_commit(struct drm_atomic_state *state)
struct drm_device *dev = state->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_hvs *hvs = vc4->hvs;
- struct vc4_crtc *vc4_crtc;
+ struct drm_crtc_state *new_crtc_state;
+ struct drm_crtc *crtc;
int i;
- for (i = 0; i < dev->mode_config.num_crtc; i++) {
- if (!state->crtcs[i].ptr || !state->crtcs[i].commit)
+ for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
+ struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+
+ if (!new_crtc_state->commit)
continue;
- vc4_crtc = to_vc4_crtc(state->crtcs[i].ptr);
vc4_hvs_mask_underrun(dev, vc4_crtc->channel);
}
--
git-series 0.9.1
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[PATCH v5 38/80] drm/vc4: hdmi: Use debugfs private field
We're calling vc4_debugfs_add_file with our struct vc4_hdmi pointer set
in the private field, but we don't use that field and go through the
main struct vc4_dev to get it.
Let's use the private field directly, that will save us some trouble
later on.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index ec34c08b16df..ae8c4d53e239 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -183,9 +183,7 @@ static const struct debugfs_reg32 hd_regs[] = {
static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
{
struct drm_info_node *node = (struct drm_info_node *)m->private;
- struct drm_device *dev = node->minor->dev;
- struct vc4_dev *vc4 = to_vc4_dev(dev);
- struct vc4_hdmi *hdmi = vc4->hdmi;
+ struct vc4_hdmi *hdmi = node->info_ent->data;
struct drm_printer p = drm_seq_file_printer(m);
drm_print_regset32(&p, &hdmi->hdmi_regset);
--
git-series 0.9.1
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[PATCH v5 21/80] drm/vc4: crtc: Move PV dump to config_pv
Now that we only configure the PixelValve in vc4_crtc_config_pv, it doesn't
really make much sense to dump its register content in its caller.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 26 --
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index c2ab907611e3..181d3fd57bc7 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -290,6 +290,14 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
u8 ppc = pv_data->pixels_per_clock;
+ bool debug_dump_regs = false;
+
+ if (debug_dump_regs) {
+ struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
+ dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
+drm_crtc_index(crtc));
+ drm_print_regset32(&p, &vc4_crtc->regset);
+ }
vc4_crtc_pixelvalve_reset(crtc);
@@ -359,30 +367,20 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
PV_CONTROL_WAIT_HSTART |
VC4_SET_FIELD(vc4_encoder->clock_select,
PV_CONTROL_CLK_SELECT));
-}
-
-static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
-{
- struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
- bool debug_dump_regs = false;
if (debug_dump_regs) {
struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
- dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
+ dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
drm_crtc_index(crtc));
drm_print_regset32(&p, &vc4_crtc->regset);
}
+}
+static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
+{
vc4_crtc_config_pv(crtc);
vc4_hvs_mode_set_nofb(crtc);
-
- if (debug_dump_regs) {
- struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
- dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
-drm_crtc_index(crtc));
- drm_print_regset32(&p, &vc4_crtc->regset);
- }
}
static void require_hvs_enabled(struct drm_device *dev)
--
git-series 0.9.1
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[PATCH v5 25/80] drm/vc4: crtc: Remove mode_set_nofb
On BCM2711 to avoid stale pixels getting stuck in intermediate FIFOs, the
pixelvalve needs to be setup each time there's a mode change or enable /
disable sequence.
Therefore, we can't really use mode_set_nofb anymore to configure it, but
we need to move it to atomic_enable.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 284a85b9d7d4..2eda2e6429ec 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -376,11 +376,6 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
}
}
-static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
-{
- vc4_crtc_config_pv(crtc);
-}
-
static void require_hvs_enabled(struct drm_device *dev)
{
struct vc4_dev *vc4 = to_vc4_dev(dev);
@@ -433,6 +428,7 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
require_hvs_enabled(dev);
vc4_crtc_pixelvalve_reset(crtc);
+ vc4_crtc_config_pv(crtc);
CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);
@@ -791,7 +787,6 @@ static const struct drm_crtc_funcs vc4_crtc_funcs = {
};
static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
- .mode_set_nofb = vc4_crtc_mode_set_nofb,
.mode_valid = vc4_crtc_mode_valid,
.atomic_check = vc4_crtc_atomic_check,
.atomic_flush = vc4_hvs_atomic_flush,
--
git-series 0.9.1
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[PATCH v5 71/80] drm/vc4: hdmi: Always recenter the HDMI FIFO
In order to avoid a pixel getting stuck in an unflushable FIFO, we need to
recenter the FIFO every time we're doing a modeset and not only if we're
connected to an HDMI monitor.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 46 +++
1 file changed, 26 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 3c7862a1dda8..c9eae5352b9a 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -425,6 +425,30 @@ static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
(hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
}
+static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
+{
+ u32 drift;
+ int ret;
+
+ drift = HDMI_READ(HDMI_FIFO_CTL);
+ drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
+
+ HDMI_WRITE(HDMI_FIFO_CTL,
+ drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
+ HDMI_WRITE(HDMI_FIFO_CTL,
+ drift | VC4_HDMI_FIFO_CTL_RECENTER);
+ usleep_range(1000, 1100);
+ HDMI_WRITE(HDMI_FIFO_CTL,
+ drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
+ HDMI_WRITE(HDMI_FIFO_CTL,
+ drift | VC4_HDMI_FIFO_CTL_RECENTER);
+
+ ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
+ VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
+ WARN_ONCE(ret, "Timeout waiting for "
+ "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
+}
+
static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
{
struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
@@ -543,8 +567,6 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
}
if (vc4_encoder->hdmi_monitor) {
- u32 drift;
-
WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
@@ -555,25 +577,9 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
VC4_HDMI_RAM_PACKET_ENABLE);
vc4_hdmi_set_infoframes(encoder);
-
- drift = HDMI_READ(HDMI_FIFO_CTL);
- drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
-
- HDMI_WRITE(HDMI_FIFO_CTL,
- drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
- HDMI_WRITE(HDMI_FIFO_CTL,
- drift | VC4_HDMI_FIFO_CTL_RECENTER);
- usleep_range(1000, 1100);
- HDMI_WRITE(HDMI_FIFO_CTL,
- drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
- HDMI_WRITE(HDMI_FIFO_CTL,
- drift | VC4_HDMI_FIFO_CTL_RECENTER);
-
- ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
- VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
- WARN_ONCE(ret, "Timeout waiting for "
- "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
}
+
+ vc4_hdmi_recenter_fifo(vc4_hdmi);
}
static enum drm_mode_status
--
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[PATCH v5 59/80] drm/vc4: hdmi: Move CEC init to its own function
The CEC init code was put directly into the bind function, which was quite
inconsistent with how the audio support was done, and would prevent us from
further changes to skip that initialisation entirely.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 108 +-
1 file changed, 67 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 4d0b44a2ac61..bf537c6d413f 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1170,6 +1170,67 @@ static const struct cec_adap_ops vc4_hdmi_cec_adap_ops =
{
.adap_log_addr = vc4_hdmi_cec_adap_log_addr,
.adap_transmit = vc4_hdmi_cec_adap_transmit,
};
+
+static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
+{
+ struct cec_connector_info conn_info;
+ struct platform_device *pdev = vc4_hdmi->pdev;
+ u32 value;
+ int ret;
+
+ vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
+ vc4_hdmi, "vc4",
+ CEC_CAP_DEFAULTS |
+ CEC_CAP_CONNECTOR_INFO, 1);
+ ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
+ if (ret < 0)
+ return ret;
+
+ cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
+ cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
+
+ HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0x);
+ value = HDMI_READ(HDMI_CEC_CNTRL_1);
+ value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
+ /*
+* Set the logical address to Unregistered and set the clock
+* divider: the hsm_clock rate and this divider setting will
+* give a 40 kHz CEC clock.
+*/
+ value |= VC4_HDMI_CEC_ADDR_MASK |
+(4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
+ HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
+ ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
+ vc4_cec_irq_handler,
+ vc4_cec_irq_handler_thread, 0,
+ "vc4 hdmi cec", vc4_hdmi);
+ if (ret)
+ goto err_delete_cec_adap;
+
+ ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
+ if (ret < 0)
+ goto err_delete_cec_adap;
+
+ return 0;
+
+err_delete_cec_adap:
+ cec_delete_adapter(vc4_hdmi->cec_adap);
+
+ return ret;
+}
+
+static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
+{
+ cec_unregister_adapter(vc4_hdmi->cec_adap);
+}
+#else
+static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
+{
+ return 0;
+}
+
+static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
+
#endif
static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
@@ -1249,9 +1310,6 @@ static int vc4_hdmi_init_resources(struct vc4_hdmi
*vc4_hdmi)
static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
{
-#ifdef CONFIG_DRM_VC4_HDMI_CEC
- struct cec_connector_info conn_info;
-#endif
const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
struct platform_device *pdev = to_platform_device(dev);
struct drm_device *drm = dev_get_drvdata(master);
@@ -1331,43 +1389,13 @@ static int vc4_hdmi_bind(struct device *dev, struct
device *master, void *data)
if (ret)
goto err_destroy_encoder;
-#ifdef CONFIG_DRM_VC4_HDMI_CEC
- vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
- vc4_hdmi, "vc4",
- CEC_CAP_DEFAULTS |
- CEC_CAP_CONNECTOR_INFO, 1);
- ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
- if (ret < 0)
- goto err_destroy_conn;
-
- cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
- cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
-
- HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0x);
- value = HDMI_READ(HDMI_CEC_CNTRL_1);
- value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
- /*
-* Set the logical address to Unregistered and set the clock
-* divider: the hsm_clock rate and this divider setting will
-* give a 40 kHz CEC clock.
-*/
- value |= VC4_HDMI_CEC_ADDR_MASK |
-(4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
- HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
- ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
- vc4_cec_irq_handler,
- vc4_cec_irq_handler_thread, 0,
- "vc4 hdmi cec", vc4_hdmi);
+ ret = vc4_hdmi_cec_init(vc4_hdmi);
if
Re: [PATCH v10 07/17] pwm: lpss: Remove suspend/resume handlers
On Thu, Sep 03, 2020 at 03:48:16PM +0300, Andy Shevchenko wrote:
> On Thu, Sep 03, 2020 at 01:23:27PM +0200, Hans de Goede wrote:
> the question is do we need to have similar in acpi_lpss.c?
> For example,
> static const struct lpss_device_desc byt_pwm_dev_desc = {
> .flags = LPSS_SAVE_CTX,
> ^^
> .prv_offset = 0x800,
> .setup = byt_pwm_setup,
> };
>
> static const struct lpss_device_desc bsw_pwm_dev_desc = {
> .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
> ^^
> .prv_offset = 0x800,
> .setup = bsw_pwm_setup,
> };
Okay, it's a private space which has clock and reset gating, so means we still
need to handle it.
--
With Best Regards,
Andy Shevchenko
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[PATCH v5 20/80] drm/vc4: crtc: Turn pixelvalve reset into a function
The driver resets the pixelvalve FIFO in a number of occurences without
always using the same sequence.
Since this will be critical for BCM2711, let's move that sequence to a
function so that we are consistent.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 41bc61d5a61f..c2ab907611e3 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -267,6 +267,15 @@ static struct drm_encoder *vc4_get_crtc_encoder(struct
drm_crtc *crtc)
return NULL;
}
+static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc)
+{
+ struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+
+ /* The PV needs to be disabled before it can be flushed */
+ CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);
+ CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR);
+}
+
static void vc4_crtc_config_pv(struct drm_crtc *crtc)
{
struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
@@ -282,10 +291,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
u8 ppc = pv_data->pixels_per_clock;
- /* Reset the PV fifo. */
- CRTC_WRITE(PV_CONTROL, 0);
- CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
- CRTC_WRITE(PV_CONTROL, 0);
+ vc4_crtc_pixelvalve_reset(crtc);
CRTC_WRITE(PV_HORZA,
VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep /
ppc,
@@ -430,9 +436,9 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
require_hvs_enabled(dev);
- /* Reset the PV fifo. */
- CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) |
- PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
+ vc4_crtc_pixelvalve_reset(crtc);
+
+ CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);
/* Enable vblank irq handling before crtc is started otherwise
* drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
--
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[PATCH v5 68/80] drm/vc4: hdmi: Add audio-related callbacks
From: Dave Stevenson
The audio configuration has changed for the BCM2711, with notably a
different parent clock and a different channel configuration.
Make that modular to be able to support the BCM2711.
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 25 +
drivers/gpu/drm/vc4/vc4_hdmi.h | 4
2 files changed, 21 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index d8137b838326..20cfc85449ca 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -611,10 +611,22 @@ static const struct drm_encoder_helper_funcs
vc4_hdmi_encoder_helper_funcs = {
.enable = vc4_hdmi_encoder_enable,
};
+static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
+{
+ int i;
+ u32 channel_map = 0;
+
+ for (i = 0; i < 8; i++) {
+ if (channel_mask & BIT(i))
+ channel_map |= i << (3 * i);
+ }
+ return channel_map;
+}
+
/* HDMI audio codec callbacks */
static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi)
{
- u32 hsm_clock = clk_get_rate(vc4_hdmi->hsm_clock);
+ u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
unsigned long n, m;
rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate,
@@ -733,7 +745,7 @@ static int vc4_hdmi_audio_hw_params(struct
snd_pcm_substream *substream,
struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
struct device *dev = &vc4_hdmi->pdev->dev;
u32 audio_packet_config, channel_mask;
- u32 channel_map, i;
+ u32 channel_map;
if (substream != vc4_hdmi->audio.substream)
return -EINVAL;
@@ -785,12 +797,7 @@ static int vc4_hdmi_audio_hw_params(struct
snd_pcm_substream *substream,
VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
- channel_map = 0;
- for (i = 0; i < 8; i++) {
- if (channel_mask & BIT(i))
- channel_map |= i << (3 * i);
- }
-
+ channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
vc4_hdmi_set_n_cts(vc4_hdmi);
@@ -1342,6 +1349,7 @@ static int vc4_hdmi_init_resources(struct vc4_hdmi
*vc4_hdmi)
DRM_ERROR("Failed to get HDMI state machine clock\n");
return PTR_ERR(vc4_hdmi->hsm_clock);
}
+ vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
return 0;
}
@@ -1507,6 +1515,7 @@ static const struct vc4_hdmi_variant bcm2835_variant = {
.phy_disable= vc4_hdmi_phy_disable,
.phy_rng_enable = vc4_hdmi_phy_rng_enable,
.phy_rng_disable= vc4_hdmi_phy_rng_disable,
+ .channel_map= vc4_hdmi_channel_map,
};
static const struct of_device_id vc4_hdmi_dt_match[] = {
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index 77d47d1707ce..4aea5ee8a91d 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -72,6 +72,9 @@ struct vc4_hdmi_variant {
/* Callback to disable the RNG in the PHY */
void (*phy_rng_disable)(struct vc4_hdmi *vc4_hdmi);
+
+ /* Callback to get channel map */
+ u32 (*channel_map)(struct vc4_hdmi *vc4_hdmi, u32 channel_mask);
};
/* HDMI audio information */
@@ -112,6 +115,7 @@ struct vc4_hdmi {
struct clk *pixel_clock;
struct clk *hsm_clock;
+ struct clk *audio_clock;
struct debugfs_regset32 hdmi_regset;
struct debugfs_regset32 hd_regset;
--
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[PATCH v5 46/80] drm/vc4: hdmi: Pass vc4_hdmi to CEC code
Our CEC code also retrieves the associated vc4_hdmi by setting the
vc4_dev pointer as its private data, and then dereferences its vc4_hdmi
pointer.
In order to eventually get rid of that pointer, we can simply pass the
vc4_hdmi pointer directly.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 24 +---
1 file changed, 9 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index a2053da4e443..44126ae55a19 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1032,8 +1032,7 @@ static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
#ifdef CONFIG_DRM_VC4_HDMI_CEC
static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
{
- struct vc4_dev *vc4 = priv;
- struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
+ struct vc4_hdmi *vc4_hdmi = priv;
if (vc4_hdmi->cec_irq_was_rx) {
if (vc4_hdmi->cec_rx_msg.len)
@@ -1053,9 +1052,8 @@ static irqreturn_t vc4_cec_irq_handler_thread(int irq,
void *priv)
return IRQ_HANDLED;
}
-static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1)
+static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
{
- struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
unsigned int i;
@@ -1073,8 +1071,7 @@ static void vc4_cec_read_msg(struct vc4_dev *vc4, u32
cntrl1)
static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
{
- struct vc4_dev *vc4 = priv;
- struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
+ struct vc4_hdmi *vc4_hdmi = priv;
u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS);
u32 cntrl1, cntrl5;
@@ -1085,7 +1082,7 @@ static irqreturn_t vc4_cec_irq_handler(int irq, void
*priv)
cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
if (vc4_hdmi->cec_irq_was_rx) {
- vc4_cec_read_msg(vc4, cntrl1);
+ vc4_cec_read_msg(vc4_hdmi, cntrl1);
cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
@@ -1101,8 +1098,7 @@ static irqreturn_t vc4_cec_irq_handler(int irq, void
*priv)
static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
{
- struct vc4_dev *vc4 = cec_get_drvdata(adap);
- struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
+ struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
/* clock period in microseconds */
const u32 usecs = 100 / CEC_CLOCK_FREQ;
u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
@@ -1145,8 +1141,7 @@ static int vc4_hdmi_cec_adap_enable(struct cec_adapter
*adap, bool enable)
static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
{
- struct vc4_dev *vc4 = cec_get_drvdata(adap);
- struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
+ struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1,
(HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
@@ -1157,8 +1152,7 @@ static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter
*adap, u8 log_addr)
static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
u32 signal_free_time, struct cec_msg *msg)
{
- struct vc4_dev *vc4 = cec_get_drvdata(adap);
- struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
+ struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
u32 val;
unsigned int i;
@@ -1305,7 +1299,7 @@ static int vc4_hdmi_bind(struct device *dev, struct
device *master, void *data)
#ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
- vc4, "vc4",
+ vc4_hdmi, "vc4",
CEC_CAP_DEFAULTS |
CEC_CAP_CONNECTOR_INFO, 1);
ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
@@ -1329,7 +1323,7 @@ static int vc4_hdmi_bind(struct device *dev, struct
device *master, void *data)
ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
vc4_cec_irq_handler,
vc4_cec_irq_handler_thread, 0,
- "vc4 hdmi cec", vc4);
+ "vc4 hdmi cec", vc4_hdmi);
if (ret)
goto err_delete_cec_adap;
ret = cec_register_adapter(vc4_hdmi->cec_adap, dev);
--
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[PATCH v5 44/80] drm/vc4: hdmi: Use local vc4_hdmi directly
The function vc4_hdmi_connector_detect access its vc4_hdmi struct by
dereferencing the pointer in the structure vc4_dev. This will cause some
issues when we will have multiple HDMI controllers, so let's just use the
local variable for now instead of dereferencing that pointer all the time,
and we'll fix the local variable later.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 81c0f67cd0eb..93865327a8d4 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -125,20 +125,20 @@ vc4_hdmi_connector_detect(struct drm_connector
*connector, bool force)
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
- if (vc4->hdmi->hpd_gpio) {
- if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
- vc4->hdmi->hpd_active_low)
+ if (vc4_hdmi->hpd_gpio) {
+ if (gpio_get_value_cansleep(vc4_hdmi->hpd_gpio) ^
+ vc4_hdmi->hpd_active_low)
return connector_status_connected;
- cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
+ cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
return connector_status_disconnected;
}
- if (drm_probe_ddc(vc4->hdmi->ddc))
+ if (drm_probe_ddc(vc4_hdmi->ddc))
return connector_status_connected;
if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
return connector_status_connected;
- cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
+ cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
return connector_status_disconnected;
}
--
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[PATCH v5 31/80] drm/vc4: crtc: Clear the PixelValve FIFO during configuration
Even though it's not really clear why we need to flush the PV FIFO during the configuration even though we started by flushing it, experience shows that without it we get a stale pixel stuck in the FIFO between the HVS and the PV. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 73d918706f7e..00b2c2b011d1 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -358,7 +358,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc) if (is_dsi) CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); - CRTC_WRITE(PV_CONTROL, + CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) | VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | -- git-series 0.9.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 00/80] drm/vc4: Support BCM2711 Display Pipeline
Hi everyone, Here's a (pretty long) series to introduce support in the VC4 DRM driver for the display pipeline found in the BCM2711 (and thus the RaspberryPi 4). The main differences are that there's two HDMI controllers and that there's more pixelvalve now. Those pixelvalve come with a mux in the HVS that still have only 3 FIFOs. Both of those differences are breaking a bunch of expectations in the driver, so we first need a good bunch of cleanup and reworks to introduce support for the new controllers. Similarly, the HDMI controller has all its registers shuffled and split in multiple controllers now, so we need a bunch of changes to support this as well. Only the HDMI support is enabled for now (even though the DPI and DSI outputs have been tested too). Let me know if you have any comments Maxime Cc: bcm-kernel-feedback-l...@broadcom.com Cc: devicet...@vger.kernel.org Cc: Kamal Dasu Cc: Philipp Zabel Cc: Rob Herring Cc: Stephen Boyd Changes from v4: - Rebased on top of next-20200828 - Collected the various tags - Fixed some issues with 4k support and dual output (thanks Hoegeun!) - Fixed typos in commit logs (thanks Dave!) - Split the csc setup hook into its own patch again - Added the CEC clock to the DT binding - Fixed the DT binding example - Reduced the number of calls to of_device_is_compatible in vc4_kms_load - Added back the check for the state commit in our commit hook Changes from v3: - Rebased on top of next-20200708 - Added a name to the HDMI audio codec component - Only disable the BCM2711 HDMI pixelvalves at boot - Fixed an error in the HVS binding - Fix a framebuffer size condition that was inverted - Changed the channel allocation algorithm using Eric's suggestion - Always write the muxing values instead of updating if needed - Improved a bit the hvs_available_channels comment in the structure - Change atomic_complete_commit code to use for_each_new_crtc_in_state - Change the muxing code to take into account disparities between the BCM2711 and previous SoCs. - Only change the clock rate on BCM2711 during a modeset - Fix a crash at atomic_disable - Use clk_set_min_rate for the core clock too - Add a few defines, and simplify the FIFO level stuff - Reordered the patches according to Eric's reviews - Fixed a regression with VID_CTL setting on RPI3 Changes from v2: - Rebased on top of next-20200526 - Split the firmware clock series away - Removed the stuck pixel (with all the subsequent pixels being shifted by one - Fixed the writeback issue too. - Fix the dual output - Fixed the return value of phy_get_cp_current - Enhanced the comment on the reset delay - Increase the max width and height - Made a proper Kconfig option for the DVP clock driver - Fixed the alsa card name collision Changes from v1: - Rebased on top of 5.7-rc1 - Run checkpatch - Added audio support - Fixed some HDMI timeouts - Swiched to clk_hw_register_gate_parent_data - Reorder Kconfig symbols in drivers/i2c/busses - Make the firmware clocks a child of the firmware node - Switch DVP clock driver to clk_hw interface - constify raspberrypi_clk_data in raspberrypi_clock_property - Don't mark firmware clocks as IGNORE_UNUSED - Change from reset_ms to reset_us in reset-simple, and add a bit more comments - Remove generic clk patch to test if a NULL pointer is returned - Removed misleading message in the is_prepared renaming patch commit message - Constify HDMI controller variants - Fix a bug in the allocation size of the clk data array - Added a mention in the DT binding conversion patches about the breakage - Merged a few fixes from kbuild - Fixed a few bisection and CEC build issues - Collected Acked-by and Reviewed-by - Change Dave email address to raspberrypi.com Dave Stevenson (7): drm/vc4: Add support for the BCM2711 HVS5 drm/vc4: plane: Change LBM alignment constraint on LBM drm/vc4: plane: Optimize the LBM allocation size drm/vc4: hdmi: Use reg-names to retrieve the HDMI audio registers drm/vc4: hdmi: Reset audio infoframe on encoder_enable if previously streaming drm/vc4: hdmi: Set the b-frame marker to the match ALSA's default. drm/vc4: hdmi: Add audio-related callbacks Hoegeun Kwon (1): drm/vc4: hdmi: Add pixel BVB clock control Maxime Ripard (72): dt-bindings: display: Add support for the BCM2711 HVS drm/vc4: hvs: Boost the core clock during modeset drm/vc4: plane: Create more planes drm/vc4: crtc: Deal with different number of pixel per clock drm/vc4: crtc: Use a shared interrupt drm/vc4: crtc: Move the cob allocation outside of bind drm/vc4: crtc: Rename HVS channel to output drm/vc4: crtc: Use local chan variable drm/vc4: crtc: Enable and disable the PV in atomic_enable / disable drm/vc4: kms: Convert to for_each_new_crtc_state drm/vc4: crtc: Assign output to channel automatically drm/vc4: crtc: Add FIFO depth to vc4_crtc_data drm/vc
[PATCH v5 36/80] dt-bindings: display: vc4: pv: Add BCM2711 pixel valves
The BCM2711 comes with other pixelvalves that have different requirements and capabilities. Let's document their compatible. Reviewed-by: Rob Herring Reviewed-by: Eric Anholt Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml b/Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml index e60791db1fa1..4e1ba03f6477 100644 --- a/Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml +++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml @@ -15,6 +15,11 @@ properties: - brcm,bcm2835-pixelvalve0 - brcm,bcm2835-pixelvalve1 - brcm,bcm2835-pixelvalve2 + - brcm,bcm2711-pixelvalve0 + - brcm,bcm2711-pixelvalve1 + - brcm,bcm2711-pixelvalve2 + - brcm,bcm2711-pixelvalve3 + - brcm,bcm2711-pixelvalve4 reg: maxItems: 1 -- git-series 0.9.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 14/80] drm/vc4: crtc: Assign output to channel automatically
The HVS found in the BCM2711 has 6 outputs and 3 FIFOs, with each output
being connected to a pixelvalve, and some muxing between the FIFOs and
outputs.
Any output cannot feed from any FIFO though, and they all have a bunch of
constraints.
In order to support this, let's store the possible FIFOs each output can be
assigned to in the vc4_crtc_data, and use that information at atomic_check
time to iterate over all the CRTCs enabled and assign them FIFOs.
The channel assigned is then set in the vc4_crtc_state so that the rest of
the driver can use it.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 12 +-
drivers/gpu/drm/vc4/vc4_drv.h | 7 +-
drivers/gpu/drm/vc4/vc4_hvs.c | 28 ++
drivers/gpu/drm/vc4/vc4_kms.c | 168 +-
drivers/gpu/drm/vc4/vc4_regs.h | 10 ++-
drivers/gpu/drm/vc4/vc4_txp.c | 1 +-
6 files changed, 200 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index fe2e5675aed4..b7e47ce1476c 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -88,6 +88,7 @@ static bool vc4_crtc_get_scanout_position(struct drm_crtc
*crtc,
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
unsigned int cob_size;
u32 val;
int fifo_lines;
@@ -104,7 +105,7 @@ static bool vc4_crtc_get_scanout_position(struct drm_crtc
*crtc,
* Read vertical scanline which is currently composed for our
* pixelvalve by the HVS, and also the scaler status.
*/
- val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
+ val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel));
/* Get optional system timestamp after query. */
if (etime)
@@ -124,7 +125,7 @@ static bool vc4_crtc_get_scanout_position(struct drm_crtc
*crtc,
*hpos += mode->crtc_htotal / 2;
}
- cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc->channel);
+ cob_size = vc4_crtc_get_cob_allocation(vc4,
vc4_crtc_state->assigned_channel);
/* This is the offset we need for translating hvs -> pv scanout pos. */
fifo_lines = cob_size / mode->crtc_hdisplay;
@@ -520,7 +521,7 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc
*vc4_crtc)
struct drm_device *dev = crtc->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
- u32 chan = vc4_crtc->channel;
+ u32 chan = vc4_state->assigned_channel;
unsigned long flags;
spin_lock_irqsave(&dev->event_lock, flags);
@@ -719,6 +720,7 @@ struct drm_crtc_state *vc4_crtc_duplicate_state(struct
drm_crtc *crtc)
old_vc4_state = to_vc4_crtc_state(crtc->state);
vc4_state->feed_txp = old_vc4_state->feed_txp;
vc4_state->margins = old_vc4_state->margins;
+ vc4_state->assigned_channel = old_vc4_state->assigned_channel;
__drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
return &vc4_state->base;
@@ -779,6 +781,7 @@ static const struct drm_crtc_helper_funcs
vc4_crtc_helper_funcs = {
static const struct vc4_pv_data bcm2835_pv0_data = {
.base = {
+ .hvs_available_channels = BIT(0),
.hvs_output = 0,
},
.debugfs_name = "crtc0_regs",
@@ -791,6 +794,7 @@ static const struct vc4_pv_data bcm2835_pv0_data = {
static const struct vc4_pv_data bcm2835_pv1_data = {
.base = {
+ .hvs_available_channels = BIT(2),
.hvs_output = 2,
},
.debugfs_name = "crtc1_regs",
@@ -803,6 +807,7 @@ static const struct vc4_pv_data bcm2835_pv1_data = {
static const struct vc4_pv_data bcm2835_pv2_data = {
.base = {
+ .hvs_available_channels = BIT(1),
.hvs_output = 1,
},
.debugfs_name = "crtc2_regs",
@@ -866,7 +871,6 @@ int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc
*vc4_crtc,
drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
crtc_funcs, NULL);
drm_crtc_helper_add(crtc, crtc_helper_funcs);
- vc4_crtc->channel = vc4_crtc->data->hvs_output;
drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index d1cf4c038180..9e81ad8331f1 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -447,6 +447,9 @@ to_vc4_encoder(struct drm_encoder *encoder)
}
struct vc4_crtc_data {
+ /* Bitmask of channels (FIFOs) of t
[PATCH v5 63/80] drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate
The HSM clock needs to be setup at around 101% of the pixel rate. This
was done previously by setting the clock rate to 163.7MHz at probe time and
only check in mode_valid whether the mode pixel clock was under the pixel
clock +1% or not.
However, with 4k we need to change that frequency to a higher frequency
than 163.7MHz, and yet want to have the lowest clock as possible to have a
decent power saving.
Let's change that logic a bit by setting the clock rate of the HSM clock
to the pixel rate at encoder_enable time. This would work for the
BCM2711 that support 4k resolutions and has a clock that can provide it,
but we still have to take care of a 4k panel plugged on a BCM283x SoCs
that wouldn't be able to use those modes, so let's define the limit in
the variant.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 79 ---
drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +-
2 files changed, 41 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 1e6c0e26d186..84273fe650d6 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -53,7 +53,6 @@
#include "vc4_hdmi_regs.h"
#include "vc4_regs.h"
-#define HSM_CLOCK_FREQ 163682864
#define CEC_CLOCK_FREQ 4
static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
@@ -326,6 +325,7 @@ static void vc4_hdmi_encoder_disable(struct drm_encoder
*encoder)
HDMI_WRITE(HDMI_VID_CTL,
HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
+ clk_disable_unprepare(vc4_hdmi->hsm_clock);
clk_disable_unprepare(vc4_hdmi->pixel_clock);
ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
@@ -423,6 +423,7 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
bool debug_dump_regs = false;
+ unsigned long pixel_rate, hsm_rate;
int ret;
ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev);
@@ -431,9 +432,8 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
return;
}
- ret = clk_set_rate(vc4_hdmi->pixel_clock,
- mode->clock * 1000 *
- ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1));
+ pixel_rate = mode->clock * 1000 * ((mode->flags & DRM_MODE_FLAG_DBLCLK)
? 2 : 1);
+ ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
if (ret) {
DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
return;
@@ -445,6 +445,36 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
return;
}
+ /*
+* As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
+* be faster than pixel clock, infinitesimally faster, tested in
+* simulation. Otherwise, exact value is unimportant for HDMI
+* operation." This conflicts with bcm2835's vc4 documentation, which
+* states HSM's clock has to be at least 108% of the pixel clock.
+*
+* Real life tests reveal that vc4's firmware statement holds up, and
+* users are able to use pixel clocks closer to HSM's, namely for
+* 1920x1200@60Hz. So it was decided to have leave a 1% margin between
+* both clocks. Which, for RPi0-3 implies a maximum pixel clock of
+* 162MHz.
+*
+* Additionally, the AXI clock needs to be at least 25% of
+* pixel clock, but HSM ends up being the limiting factor.
+*/
+ hsm_rate = max_t(unsigned long, 12000, (pixel_rate / 100) * 101);
+ ret = clk_set_rate(vc4_hdmi->hsm_clock, hsm_rate);
+ if (ret) {
+ DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
+ return;
+ }
+
+ ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
+ if (ret) {
+ DRM_ERROR("Failed to turn on HSM clock: %d\n", ret);
+ clk_disable_unprepare(vc4_hdmi->pixel_clock);
+ return;
+ }
+
if (vc4_hdmi->variant->reset)
vc4_hdmi->variant->reset(vc4_hdmi);
@@ -559,23 +589,9 @@ static enum drm_mode_status
vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
const struct drm_display_mode *mode)
{
- /*
-* As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
-* be faster than pixel clock, infinitesimally faster, tested in
-* simulation. Otherwise, exact value is unimportant for HDMI
-* operation." This conflicts with bcm2835's vc4 documentation, which
-* states HSM's clock has to be at least 108% of the pixel clock.
-*
-* Real life tests reveal that vc4's fir
[PATCH v5 05/80] drm/vc4: plane: Optimize the LBM allocation size
From: Dave Stevenson
The current code is using the maximum of the source line size and the
destination line size to compute the size of the LBM to allocate.
While this is simpler, it starts to be an issue with modes such as 4k with
a quite long that will consume all the available memory, so we no longer
have that luxury.
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_plane.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index d0771ebd5f75..23916814b4e3 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -437,10 +437,7 @@ static void vc4_write_ppf(struct vc4_plane_state
*vc4_state, u32 src, u32 dst)
static u32 vc4_lbm_size(struct drm_plane_state *state)
{
struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
- /* This is the worst case number. One of the two sizes will
-* be used depending on the scaling configuration.
-*/
- u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w);
+ u32 pix_per_line;
u32 lbm;
/* LBM is not needed when there's no vertical scaling. */
@@ -448,6 +445,18 @@ static u32 vc4_lbm_size(struct drm_plane_state *state)
vc4_state->y_scaling[1] == VC4_SCALING_NONE)
return 0;
+ /*
+* This can be further optimized in the RGB/YUV444 case if the PPF
+* decimation factor is between 0.5 and 1.0 by using crtc_w.
+*
+* It's not an issue though, since in that case since src_w[0] is going
+* to be greater than or equal to crtc_w.
+*/
+ if (vc4_state->x_scaling[0] == VC4_SCALING_TPZ)
+ pix_per_line = vc4_state->crtc_w;
+ else
+ pix_per_line = vc4_state->src_w[0];
+
if (!vc4_state->is_yuv) {
if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ)
lbm = pix_per_line * 8;
--
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[PATCH v5 17/80] drm/vc4: crtc: Rename HDMI encoder type to HDMI0
The previous generations were only supporting a single HDMI controller, but
that's about to change, so put an index as well to differentiate between
the two controllers.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 2 +-
drivers/gpu/drm/vc4/vc4_drv.h | 2 +-
drivers/gpu/drm/vc4/vc4_hdmi.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 1d9e3658ae59..04744223460a 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -835,7 +835,7 @@ static const struct vc4_pv_data bcm2835_pv2_data = {
.fifo_depth = 64,
.pixels_per_clock = 1,
.encoder_types = {
- [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
+ [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0,
[PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
},
};
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 179010b9a010..5781773aec4b 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -426,7 +426,7 @@ to_vc4_plane_state(struct drm_plane_state *state)
enum vc4_encoder_type {
VC4_ENCODER_TYPE_NONE,
- VC4_ENCODER_TYPE_HDMI,
+ VC4_ENCODER_TYPE_HDMI0,
VC4_ENCODER_TYPE_VEC,
VC4_ENCODER_TYPE_DSI0,
VC4_ENCODER_TYPE_DSI1,
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 15a11cd4de25..ec34c08b16df 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1309,7 +1309,7 @@ static int vc4_hdmi_bind(struct device *dev, struct
device *master, void *data)
GFP_KERNEL);
if (!vc4_hdmi_encoder)
return -ENOMEM;
- vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI;
+ vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI0;
hdmi->encoder = &vc4_hdmi_encoder->base.base;
hdmi->pdev = pdev;
--
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[PATCH v5 76/80] drm/vc4: hdmi: Support the BCM2711 HDMI controllers
Now that the driver is ready for it, let's bring in the HDMI controllers
variants for the BCM2711.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 284 +-
drivers/gpu/drm/vc4/vc4_hdmi.h | 36 ++-
drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 480 +-
drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 201 -
drivers/gpu/drm/vc4/vc4_regs.h | 2 +-
5 files changed, 1003 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 39508107dafd..c994ebf84c64 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -43,6 +43,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -53,6 +54,31 @@
#include "vc4_hdmi_regs.h"
#include "vc4_regs.h"
+#define VC5_HDMI_HORZA_HFP_SHIFT 16
+#define VC5_HDMI_HORZA_HFP_MASKVC4_MASK(28, 16)
+#define VC5_HDMI_HORZA_VPOSBIT(15)
+#define VC5_HDMI_HORZA_HPOSBIT(14)
+#define VC5_HDMI_HORZA_HAP_SHIFT 0
+#define VC5_HDMI_HORZA_HAP_MASKVC4_MASK(13, 0)
+
+#define VC5_HDMI_HORZB_HBP_SHIFT 16
+#define VC5_HDMI_HORZB_HBP_MASKVC4_MASK(26, 16)
+#define VC5_HDMI_HORZB_HSP_SHIFT 0
+#define VC5_HDMI_HORZB_HSP_MASKVC4_MASK(10, 0)
+
+#define VC5_HDMI_VERTA_VSP_SHIFT 24
+#define VC5_HDMI_VERTA_VSP_MASKVC4_MASK(28, 24)
+#define VC5_HDMI_VERTA_VFP_SHIFT 16
+#define VC5_HDMI_VERTA_VFP_MASKVC4_MASK(22, 16)
+#define VC5_HDMI_VERTA_VAL_SHIFT 0
+#define VC5_HDMI_VERTA_VAL_MASKVC4_MASK(12, 0)
+
+#define VC5_HDMI_VERTB_VSPO_SHIFT 16
+#define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
+
+# define VC4_HD_M_SW_RST BIT(2)
+# define VC4_HD_M_ENABLE BIT(0)
+
#define CEC_CLOCK_FREQ 4
#define VC4_HSM_MID_CLOCK 149985000
@@ -83,6 +109,16 @@ static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
}
+static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
+{
+ reset_control_reset(vc4_hdmi->reset);
+
+ HDMI_WRITE(HDMI_DVP_CTL, 0);
+
+ HDMI_WRITE(HDMI_CLOCK_STOP,
+ HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
+}
+
static enum drm_connector_status
vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
{
@@ -393,6 +429,45 @@ static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
bool enable)
HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
}
+static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
+{
+ u32 csc_ctl;
+
+ csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, ||
USE_RGB_TO_YCBCR */
+
+ if (enable) {
+ /* CEA VICs other than #1 requre limited range RGB
+* output unless overridden by an AVI infoframe.
+* Apply a colorspace conversion to squash 0-255 down
+* to 16-235. The matrix here is:
+*
+* [ 0.8594 0 0 16]
+* [ 0 0.8594 0 16]
+* [ 0 0 0.8594 16]
+* [ 0 0 0 1]
+* Matrix is signed 2p13 fixed point, with signed 9p6 offsets
+*/
+ HDMI_WRITE(HDMI_CSC_12_11, (0x << 16) | 0x1b80);
+ HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x);
+ HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x);
+ HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x);
+ HDMI_WRITE(HDMI_CSC_32_31, (0x << 16) | 0x);
+ HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
+ } else {
+ /* Still use the matrix for full range, but make it unity.
+* Matrix is signed 2p13 fixed point, with signed 9p6 offsets
+*/
+ HDMI_WRITE(HDMI_CSC_12_11, (0x << 16) | 0x2000);
+ HDMI_WRITE(HDMI_CSC_14_13, (0x << 16) | 0x);
+ HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x);
+ HDMI_WRITE(HDMI_CSC_24_23, (0x << 16) | 0x);
+ HDMI_WRITE(HDMI_CSC_32_31, (0x << 16) | 0x);
+ HDMI_WRITE(HDMI_CSC_34_33, (0x << 16) | 0x2000);
+ }
+
+ HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
+}
+
static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
struct drm_display_mode *mode)
{
@@ -437,6 +512,53 @@ static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
HDMI_WRITE(HDMI_VERTB0, vertb_even);
HDMI_WRITE(HDMI_VERTB1, vertb);
}
+static void vc5_hdmi_se
[PATCH v5 23/80] drm/vc4: crtc: Move the HVS gamma LUT setup to our init function
Since most of the HVS channel is setup in the init function, let's move the
gamma setup there too. As this makes the HVS mode_set function empty, let's
remove it in the process.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 2 +-
drivers/gpu/drm/vc4/vc4_drv.h | 1 +-
drivers/gpu/drm/vc4/vc4_hvs.c | 59 +--
drivers/gpu/drm/vc4/vc4_txp.c | 1 +-
4 files changed, 16 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 181d3fd57bc7..284a85b9d7d4 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -379,8 +379,6 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
vc4_crtc_config_pv(crtc);
-
- vc4_hvs_mode_set_nofb(crtc);
}
static void require_hvs_enabled(struct drm_device *dev)
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 4126506b3a69..dfcc684f5d28 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -904,7 +904,6 @@ int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct
drm_crtc_state *state);
void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state
*old_state);
void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_crtc_state
*old_state);
void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *state);
-void vc4_hvs_mode_set_nofb(struct drm_crtc *crtc);
void vc4_hvs_dump_state(struct drm_device *dev);
void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel);
void vc4_hvs_mask_underrun(struct drm_device *dev, int channel);
diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index dde931233d4a..efaae60bb323 100644
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -201,6 +201,8 @@ static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct
drm_crtc *crtc,
{
struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
unsigned int chan = vc4_crtc_state->assigned_channel;
+ bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
+ u32 dispbkgndx;
u32 dispctrl;
/* Turn on the scaler, which will wait for vstart to start
@@ -225,6 +227,20 @@ static int vc4_hvs_init_channel(struct vc4_dev *vc4,
struct drm_crtc *crtc,
HVS_WRITE(SCALER_DISPCTRLX(chan), dispctrl);
+ dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(chan));
+ dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
+ dispbkgndx &= ~SCALER_DISPBKGND_INTERLACE;
+
+ HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx |
+ SCALER_DISPBKGND_AUTOHS |
+ ((!vc4->hvs->hvs5) ? SCALER_DISPBKGND_GAMMA : 0) |
+ (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
+
+ /* Reload the LUT, since the SRAMs would have been disabled if
+* all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
+*/
+ vc4_hvs_lut_load(crtc);
+
return 0;
}
@@ -421,49 +437,6 @@ void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
}
}
-void vc4_hvs_mode_set_nofb(struct drm_crtc *crtc)
-{
- struct drm_device *dev = crtc->dev;
- struct vc4_dev *vc4 = to_vc4_dev(dev);
- struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
- struct drm_display_mode *mode = &crtc->state->adjusted_mode;
- bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
-
- if (vc4_state->assigned_channel == 2) {
- u32 dispctrl;
- u32 dsp3_mux;
-
- /*
-* SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
-* FIFO X'.
-* SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
-*
-* DSP3 is connected to FIFO2 unless the transposer is
-* enabled. In this case, FIFO 2 is directly accessed by the
-* TXP IP, and we need to disable the FIFO2 -> pixelvalve1
-* route.
-*/
- if (vc4_state->feed_txp)
- dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
- else
- dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
-
- dispctrl = HVS_READ(SCALER_DISPCTRL) &
- ~SCALER_DISPCTRL_DSP3_MUX_MASK;
- HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
- }
-
- HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel),
- SCALER_DISPBKGND_AUTOHS |
- ((!vc4->hvs->hvs5) ? SCALER_DISPBKGND_GAMMA : 0) |
- (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
-
- /* Reload the LUT, since the SRAMs would have been disabled if
-* all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
-*/
[PATCH v5 07/80] drm/vc4: crtc: Deal with different number of pixel per clock
Some of the HDMI pixelvalves in vc5 output two pixels per clock cycle.
Let's put the number of pixel output per clock cycle in the CRTC data and
update the various calculations to reflect that.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 18 +++---
drivers/gpu/drm/vc4/vc4_drv.h | 3 +++
2 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 6d8fa6118fc1..e55b2208b4b7 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -235,6 +235,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
struct drm_crtc_state *state = crtc->state;
struct drm_display_mode *mode = &state->adjusted_mode;
bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
@@ -242,6 +243,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
+ u8 ppc = pv_data->pixels_per_clock;
/* Reset the PV fifo. */
CRTC_WRITE(PV_CONTROL, 0);
@@ -249,17 +251,16 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
CRTC_WRITE(PV_CONTROL, 0);
CRTC_WRITE(PV_HORZA,
- VC4_SET_FIELD((mode->htotal -
- mode->hsync_end) * pixel_rep,
+ VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep /
ppc,
PV_HORZA_HBP) |
- VC4_SET_FIELD((mode->hsync_end -
- mode->hsync_start) * pixel_rep,
+ VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) *
pixel_rep / ppc,
PV_HORZA_HSYNC));
+
CRTC_WRITE(PV_HORZB,
- VC4_SET_FIELD((mode->hsync_start -
- mode->hdisplay) * pixel_rep,
+ VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) *
pixel_rep / ppc,
PV_HORZB_HFP) |
- VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
+ VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,
+PV_HORZB_HACTIVE));
CRTC_WRITE(PV_VERTA,
VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
@@ -761,6 +762,7 @@ static const struct vc4_pv_data bcm2835_pv0_data = {
.hvs_channel = 0,
},
.debugfs_name = "crtc0_regs",
+ .pixels_per_clock = 1,
.encoder_types = {
[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
@@ -772,6 +774,7 @@ static const struct vc4_pv_data bcm2835_pv1_data = {
.hvs_channel = 2,
},
.debugfs_name = "crtc1_regs",
+ .pixels_per_clock = 1,
.encoder_types = {
[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
@@ -783,6 +786,7 @@ static const struct vc4_pv_data bcm2835_pv2_data = {
.hvs_channel = 1,
},
.debugfs_name = "crtc2_regs",
+ .pixels_per_clock = 1,
.encoder_types = {
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
[PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 6358f6ca8d56..0bc150daafb2 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -454,6 +454,9 @@ struct vc4_crtc_data {
struct vc4_pv_data {
struct vc4_crtc_database;
+ /* Number of pixels output per clock period */
+ u8 pixels_per_clock;
+
enum vc4_encoder_type encoder_types[4];
const char *debugfs_name;
--
git-series 0.9.1
___
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 72/80] drm/vc4: hdmi: Implement finer-grained hooks
In order to prevent some pixels getting stuck in an unflushable FIFO on
bcm2711, we need to enable the HVS, the pixelvalve (the CRTC) and the HDMI
controller (the encoder) in an intertwined way, and with tight delays.
However, the atomic callbacks don't really provide a way to work with
either constraints, so we need to roll our own callbacks so that we can
provide those guarantees.
Since those callbacks have been implemented and called in the CRTC code, we
can just implement them in the HDMI driver now.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 39 +++
1 file changed, 35 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index c9eae5352b9a..128d33c8c2c3 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -320,12 +320,17 @@ static void vc4_hdmi_set_infoframes(struct drm_encoder
*encoder)
vc4_hdmi_set_audio_infoframe(encoder);
}
-static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
+static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder)
{
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
- int ret;
HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
+}
+
+static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder)
+{
+ struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
+ int ret;
if (vc4_hdmi->variant->phy_disable)
vc4_hdmi->variant->phy_disable(vc4_hdmi);
@@ -341,6 +346,10 @@ static void vc4_hdmi_encoder_disable(struct drm_encoder
*encoder)
DRM_ERROR("Failed to release power domain: %d\n", ret);
}
+static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
+{
+}
+
static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
{
u32 csc_ctl;
@@ -449,11 +458,10 @@ static void vc4_hdmi_recenter_fifo(struct vc4_hdmi
*vc4_hdmi)
"VC4_HDMI_FIFO_CTL_RECENTER_DONE");
}
-static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
+static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder)
{
struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
- struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
unsigned long pixel_rate, hsm_rate;
int ret;
@@ -521,6 +529,13 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
if (vc4_hdmi->variant->set_timings)
vc4_hdmi->variant->set_timings(vc4_hdmi, mode);
+}
+
+static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder)
+{
+ struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
+ struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
+ struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
if (vc4_encoder->hdmi_monitor &&
drm_default_rgb_quant_range(mode) ==
HDMI_QUANTIZATION_RANGE_LIMITED) {
@@ -536,6 +551,13 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
}
HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
+}
+
+static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder)
+{
+ struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
+ struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
+ int ret;
HDMI_WRITE(HDMI_VID_CTL,
HDMI_READ(HDMI_VID_CTL) |
@@ -582,6 +604,10 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
vc4_hdmi_recenter_fifo(vc4_hdmi);
}
+static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
+{
+}
+
static enum drm_mode_status
vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
const struct drm_display_mode *mode)
@@ -1361,6 +1387,11 @@ static int vc4_hdmi_bind(struct device *dev, struct
device *master, void *data)
dev_set_drvdata(dev, vc4_hdmi);
encoder = &vc4_hdmi->encoder.base.base;
vc4_hdmi->encoder.base.type = variant->encoder_type;
+ vc4_hdmi->encoder.base.pre_crtc_configure =
vc4_hdmi_encoder_pre_crtc_configure;
+ vc4_hdmi->encoder.base.pre_crtc_enable =
vc4_hdmi_encoder_pre_crtc_enable;
+ vc4_hdmi->encoder.base.post_crtc_enable =
vc4_hdmi_encoder_post_crtc_enable;
+ vc4_hdmi->encoder.base.post_crtc_disable =
vc4_hdmi_encoder_post_crtc_disable;
+ vc4_hdmi->encoder.base.post_crtc_powerdown =
vc4_hdmi_encoder_post_crtc_powerdown;
vc4_hdmi->pdev = pdev;
vc4_hdmi->variant = variant;
--
git-series 0.9.1
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[PATCH v5 49/80] drm/vc4: hdmi: Remove vc4_hdmi_connector
The vc4_hdmi_connector was only used to switch between drm_connector to
drm_encoder. However, we can now use vc4_hdmi to do the switch, so that
structure is redundant.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 19 ---
drivers/gpu/drm/vc4/vc4_hdmi.h | 23 ++-
2 files changed, 10 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 912560d58448..5c5684f91b69 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -189,13 +189,10 @@ static const struct drm_connector_helper_funcs
vc4_hdmi_connector_helper_funcs =
static int vc4_hdmi_connector_init(struct drm_device *dev,
struct vc4_hdmi *vc4_hdmi)
{
- struct vc4_hdmi_connector *hdmi_connector = &vc4_hdmi->connector;
- struct drm_connector *connector = &hdmi_connector->base;
+ struct drm_connector *connector = &vc4_hdmi->connector;
struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
int ret;
- hdmi_connector->encoder = encoder;
-
drm_connector_init_with_ddc(dev, connector,
&vc4_hdmi_connector_funcs,
DRM_MODE_CONNECTOR_HDMIA,
@@ -284,7 +281,7 @@ static void vc4_hdmi_set_avi_infoframe(struct drm_encoder
*encoder)
{
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
- struct drm_connector *connector = &vc4_hdmi->connector.base;
+ struct drm_connector *connector = &vc4_hdmi->connector;
struct drm_connector_state *cstate = connector->state;
struct drm_crtc *crtc = encoder->crtc;
const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
@@ -663,7 +660,7 @@ static int vc4_hdmi_audio_startup(struct snd_pcm_substream
*substream,
{
struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
- struct drm_connector *connector = &vc4_hdmi->connector.base;
+ struct drm_connector *connector = &vc4_hdmi->connector;
int ret;
if (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream)
@@ -837,7 +834,7 @@ static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol
*kcontrol,
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
- struct drm_connector *connector = &vc4_hdmi->connector.base;
+ struct drm_connector *connector = &vc4_hdmi->connector;
uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
uinfo->count = sizeof(connector->eld);
@@ -850,7 +847,7 @@ static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol
*kcontrol,
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
- struct drm_connector *connector = &vc4_hdmi->connector.base;
+ struct drm_connector *connector = &vc4_hdmi->connector;
memcpy(ucontrol->value.bytes.data, connector->eld,
sizeof(connector->eld));
@@ -1304,7 +1301,7 @@ static int vc4_hdmi_bind(struct device *dev, struct
device *master, void *data)
if (ret < 0)
goto err_destroy_conn;
- cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector.base);
+ cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0x);
@@ -1341,7 +1338,7 @@ static int vc4_hdmi_bind(struct device *dev, struct
device *master, void *data)
err_delete_cec_adap:
cec_delete_adapter(vc4_hdmi->cec_adap);
err_destroy_conn:
- vc4_hdmi_connector_destroy(&vc4_hdmi->connector.base);
+ vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
#endif
err_destroy_encoder:
drm_encoder_cleanup(encoder);
@@ -1381,7 +1378,7 @@ static void vc4_hdmi_unbind(struct device *dev, struct
device *master,
vc4_hdmi = dev_get_drvdata(dev);
cec_unregister_adapter(vc4_hdmi->cec_adap);
- vc4_hdmi_connector_destroy(&vc4_hdmi->connector.base);
+ vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
clk_disable_unprepare(vc4_hdmi->hsm_clock);
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index d43462789450..674541493909 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -21,23 +21,6 @@ to_vc4_hdmi_encoder(struct drm_encoder *encoder)
return container_of(encoder, struct vc4_hdmi_encoder, base.base);
}
-/* VC4 HDMI connector KMS struct */
-struct vc4_hdmi_connector {
- stru
[PATCH v5 01/80] dt-bindings: display: Add support for the BCM2711 HVS
The HVS found in the BCM2711 is slightly different from the previous
generations, let's add a compatible for it.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml | 18 ++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml
b/Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml
index 02410f8d6d49..e826ab0adb75 100644
--- a/Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml
+++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml
@@ -11,7 +11,9 @@ maintainers:
properties:
compatible:
-const: brcm,bcm2835-hvs
+enum:
+ - brcm,bcm2711-hvs
+ - brcm,bcm2835-hvs
reg:
maxItems: 1
@@ -19,6 +21,10 @@ properties:
interrupts:
maxItems: 1
+ clocks:
+maxItems: 1
+description: Core Clock
+
required:
- compatible
- reg
@@ -26,6 +32,16 @@ required:
additionalProperties: false
+if:
+ properties:
+compatible:
+ contains:
+const: brcm,bcm2711-hvs"
+
+then:
+ required:
+- clocks
+
examples:
- |
hvs@7e40 {
--
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[PATCH v5 15/80] drm/vc4: crtc: Add FIFO depth to vc4_crtc_data
Not all pixelvalve FIFOs in vc5 have the same depth, so we need to add that
to our vc4_crtc_data structure to be able to compute the fill level
properly later on.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 20 +---
drivers/gpu/drm/vc4/vc4_drv.h | 3 +++
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index b7e47ce1476c..2c64efd2d3d9 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -206,10 +206,21 @@ void vc4_crtc_destroy(struct drm_crtc *crtc)
drm_crtc_cleanup(crtc);
}
-static u32 vc4_get_fifo_full_level(u32 format)
+static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
{
- static const u32 fifo_len_bytes = 64;
+ const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
+ u32 fifo_len_bytes = pv_data->fifo_depth;
+ /*
+* Pixels are pulled from the HVS if the number of bytes is
+* lower than the FIFO full level.
+*
+* The latency of the pixel fetch mechanism is 6 pixels, so we
+* need to convert those 6 pixels in bytes, depending on the
+* format, and then subtract that from the length of the FIFO
+* to make sure we never end up in a situation where the FIFO
+* is full.
+*/
switch (format) {
case PV_CONTROL_FORMAT_DSIV_16:
case PV_CONTROL_FORMAT_DSIC_16:
@@ -326,7 +337,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
CRTC_WRITE(PV_CONTROL,
VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
- VC4_SET_FIELD(vc4_get_fifo_full_level(format),
+ VC4_SET_FIELD(vc4_get_fifo_full_level(vc4_crtc, format),
PV_CONTROL_FIFO_LEVEL) |
VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
PV_CONTROL_CLR_AT_START |
@@ -785,6 +796,7 @@ static const struct vc4_pv_data bcm2835_pv0_data = {
.hvs_output = 0,
},
.debugfs_name = "crtc0_regs",
+ .fifo_depth = 64,
.pixels_per_clock = 1,
.encoder_types = {
[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
@@ -798,6 +810,7 @@ static const struct vc4_pv_data bcm2835_pv1_data = {
.hvs_output = 2,
},
.debugfs_name = "crtc1_regs",
+ .fifo_depth = 64,
.pixels_per_clock = 1,
.encoder_types = {
[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
@@ -811,6 +824,7 @@ static const struct vc4_pv_data bcm2835_pv2_data = {
.hvs_output = 1,
},
.debugfs_name = "crtc2_regs",
+ .fifo_depth = 64,
.pixels_per_clock = 1,
.encoder_types = {
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 9e81ad8331f1..179010b9a010 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -457,6 +457,9 @@ struct vc4_crtc_data {
struct vc4_pv_data {
struct vc4_crtc_database;
+ /* Depth of the PixelValve FIFO in bytes */
+ unsigned int fifo_depth;
+
/* Number of pixels output per clock period */
u8 pixels_per_clock;
--
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[PATCH v5 62/80] drm/vc4: hdmi: Rename drm_encoder pointer in mode_valid
The mode_valid hook on the encoder uses a pointer to a drm_encoder called
crtc, which is pretty confusing. Let's rename it to encoder to make it
clear what it is.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index e39c6fcf4c12..1e6c0e26d186 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -556,7 +556,7 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
}
static enum drm_mode_status
-vc4_hdmi_encoder_mode_valid(struct drm_encoder *crtc,
+vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
const struct drm_display_mode *mode)
{
/*
--
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[PATCH v5 33/80] drm/vc4: hvs: Introduce a function to get the assigned FIFO
At boot time, if we detect that a pixelvalve has been enabled, we need to
be able to retrieve the HVS channel it has been assigned to so that we can
disable that channel too. Let's create that function that returns the FIFO
or an error from a given output.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_drv.h | 1 +-
drivers/gpu/drm/vc4/vc4_hvs.c | 54 -
2 files changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 554c2e29b23d..860be019d8e3 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -908,6 +908,7 @@ void vc4_irq_reset(struct drm_device *dev);
/* vc4_hvs.c */
extern struct platform_driver vc4_hvs_driver;
void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int output);
+int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output);
int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state
*old_state);
void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_crtc_state
*old_state);
diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index b5ee9556e821..4d0a833366ce 100644
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -19,6 +19,7 @@
* each CRTC.
*/
+#include
#include
#include
#include
@@ -196,6 +197,59 @@ static void vc4_hvs_update_gamma_lut(struct drm_crtc *crtc)
vc4_hvs_lut_load(crtc);
}
+int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output)
+{
+ struct vc4_dev *vc4 = to_vc4_dev(dev);
+ u32 reg;
+ int ret;
+
+ if (!vc4->hvs->hvs5)
+ return output;
+
+ switch (output) {
+ case 0:
+ return 0;
+
+ case 1:
+ return 1;
+
+ case 2:
+ reg = HVS_READ(SCALER_DISPECTRL);
+ ret = FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg);
+ if (ret == 0)
+ return 2;
+
+ return 0;
+
+ case 3:
+ reg = HVS_READ(SCALER_DISPCTRL);
+ ret = FIELD_GET(SCALER_DISPCTRL_DSP3_MUX_MASK, reg);
+ if (ret == 3)
+ return -EPIPE;
+
+ return ret;
+
+ case 4:
+ reg = HVS_READ(SCALER_DISPEOLN);
+ ret = FIELD_GET(SCALER_DISPEOLN_DSP4_MUX_MASK, reg);
+ if (ret == 3)
+ return -EPIPE;
+
+ return ret;
+
+ case 5:
+ reg = HVS_READ(SCALER_DISPDITHER);
+ ret = FIELD_GET(SCALER_DISPDITHER_DSP5_MUX_MASK, reg);
+ if (ret == 3)
+ return -EPIPE;
+
+ return ret;
+
+ default:
+ return -EPIPE;
+ }
+}
+
static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct drm_crtc *crtc,
struct drm_display_mode *mode, bool oneshot)
{
--
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[PATCH v5 35/80] drm/vc4: drv: Disable the CRTC at boot time
In order to prevent issues during the firmware to KMS transition, we need
to make sure the pixelvalve are disabled at boot time so that the DRM state
matches the hardware state.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 25 +
drivers/gpu/drm/vc4/vc4_drv.c | 4
drivers/gpu/drm/vc4/vc4_drv.h | 1 +
3 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 4156c5f66877..dfac304fe2b0 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -427,6 +427,31 @@ static int vc4_crtc_disable(struct drm_crtc *crtc,
unsigned int channel)
return 0;
}
+int vc4_crtc_disable_at_boot(struct drm_crtc *crtc)
+{
+ struct drm_device *drm = crtc->dev;
+ struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ int channel;
+
+ if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
+ "brcm,bcm2711-pixelvalve2") ||
+ of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
+ "brcm,bcm2711-pixelvalve4")))
+ return 0;
+
+ if (!(CRTC_READ(PV_CONTROL) & PV_CONTROL_EN))
+ return 0;
+
+ if (!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN))
+ return 0;
+
+ channel = vc4_hvs_get_fifo_from_output(drm, vc4_crtc->data->hvs_output);
+ if (channel < 0)
+ return 0;
+
+ return vc4_crtc_disable(crtc, channel);
+}
+
static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
struct drm_crtc_state *old_state)
{
diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
index 38343d2fb4fb..9567d1019212 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.c
+++ b/drivers/gpu/drm/vc4/vc4_drv.c
@@ -252,6 +252,7 @@ static int vc4_drm_bind(struct device *dev)
struct drm_device *drm;
struct vc4_dev *vc4;
struct device_node *node;
+ struct drm_crtc *crtc;
int ret = 0;
dev->coherent_dma_mask = DMA_BIT_MASK(32);
@@ -298,6 +299,9 @@ static int vc4_drm_bind(struct device *dev)
if (ret < 0)
goto unbind_all;
+ drm_for_each_crtc(crtc, drm)
+ vc4_crtc_disable_at_boot(crtc);
+
ret = drm_dev_register(drm, 0);
if (ret < 0)
goto unbind_all;
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 860be019d8e3..1a97545b9244 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -813,6 +813,7 @@ void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo);
/* vc4_crtc.c */
extern struct platform_driver vc4_crtc_driver;
+int vc4_crtc_disable_at_boot(struct drm_crtc *crtc);
int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
const struct drm_crtc_funcs *crtc_funcs,
const struct drm_crtc_helper_funcs *crtc_helper_funcs);
--
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[PATCH v5 34/80] drm/vc4: crtc: Move the CRTC disable out
We'll need to reuse the part that disables the HVS and PixelValve during
boot too, so let's create a separate function.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 34 ++
1 file changed, 22 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 00b2c2b011d1..4156c5f66877 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -384,20 +384,14 @@ static void require_hvs_enabled(struct drm_device *dev)
SCALER_DISPCTRL_ENABLE);
}
-static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
- struct drm_crtc_state *old_state)
+static int vc4_crtc_disable(struct drm_crtc *crtc, unsigned int channel)
{
- struct drm_device *dev = crtc->dev;
- struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
+ struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ struct drm_device *dev = crtc->dev;
int ret;
- require_hvs_enabled(dev);
-
- /* Disable vblank irq handling before crtc is disabled. */
- drm_crtc_vblank_off(crtc);
-
CRTC_WRITE(PV_V_CONTROL,
CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
@@ -421,15 +415,31 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
*/
mdelay(20);
- if (vc4_encoder->post_crtc_disable)
+ if (vc4_encoder && vc4_encoder->post_crtc_disable)
vc4_encoder->post_crtc_disable(encoder);
vc4_crtc_pixelvalve_reset(crtc);
- vc4_hvs_atomic_disable(crtc, old_state);
+ vc4_hvs_stop_channel(dev, channel);
- if (vc4_encoder->post_crtc_powerdown)
+ if (vc4_encoder && vc4_encoder->post_crtc_powerdown)
vc4_encoder->post_crtc_powerdown(encoder);
+ return 0;
+}
+
+static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
+ struct drm_crtc_state *old_state)
+{
+ struct vc4_crtc_state *old_vc4_state = to_vc4_crtc_state(old_state);
+ struct drm_device *dev = crtc->dev;
+
+ require_hvs_enabled(dev);
+
+ /* Disable vblank irq handling before crtc is disabled. */
+ drm_crtc_vblank_off(crtc);
+
+ vc4_crtc_disable(crtc, old_vc4_state->assigned_channel);
+
/*
* Make sure we issue a vblank event after disabling the CRTC if
* someone was waiting it.
--
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[PATCH v5 65/80] drm/vc4: hdmi: Use reg-names to retrieve the HDMI audio registers
From: Dave Stevenson
The register range used for audio setup in the previous generations of
SoC were always the second range in the device tree. However, now that
the BCM2711 has way more register ranges, it makes sense to retrieve it
by names for it, while preserving the id-based lookup as a fallback.
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 487c04de6b85..53c3b5ae1179 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -953,6 +953,7 @@ static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
struct snd_soc_card *card = &vc4_hdmi->audio.card;
struct device *dev = &vc4_hdmi->pdev->dev;
const __be32 *addr;
+ int index;
int ret;
if (!of_find_property(dev->of_node, "dmas", NULL)) {
@@ -973,7 +974,13 @@ static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
* for DMA transfers.
* This VC/MMU should probably be exposed to avoid this kind of hacks.
*/
- addr = of_get_address(dev->of_node, 1, NULL, NULL);
+ index = of_property_match_string(dev->of_node, "reg-names", "hd");
+ /* Before BCM2711, we don't have a named register range */
+ if (index < 0)
+ index = 1;
+
+ addr = of_get_address(dev->of_node, index, NULL, NULL);
+
vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
vc4_hdmi->audio.dma_data.maxburst = 2;
--
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[PATCH v5 30/80] drm/vc4: crtc: Clear the PixelValve FIFO on disable
In order to avoid a stale pixel getting stuck on mode change or a disable / enable cycle, we need to make sure to flush the PV FIFO on disable. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 4c23cf8aefb9..73d918706f7e 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -424,8 +424,7 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, if (vc4_encoder->post_crtc_disable) vc4_encoder->post_crtc_disable(encoder); - CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN); - + vc4_crtc_pixelvalve_reset(crtc); vc4_hvs_atomic_disable(crtc, old_state); if (vc4_encoder->post_crtc_powerdown) -- git-series 0.9.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 78/80] dt-bindings: display: vc4: Document BCM2711 VC5
The BCM2711 comes with a new VideoCore. Add a compatible for it. Reviewed-by: Rob Herring Reviewed-by: Eric Anholt Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml b/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml index 0dcf0c397375..49a5e041aa49 100644 --- a/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml +++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml @@ -17,6 +17,7 @@ description: > properties: compatible: enum: + - brcm,bcm2711-vc5 - brcm,bcm2835-vc4 - brcm,cygnus-vc4 -- git-series 0.9.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 24/80] drm/vc4: hvs: Make sure our channel is reset
In order to clear our intermediate FIFOs that might end up with a stale pixel, let's make sure our FIFO channel is reset every time our channel is setup. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hvs.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c index efaae60bb323..0f56a7b57916 100644 --- a/drivers/gpu/drm/vc4/vc4_hvs.c +++ b/drivers/gpu/drm/vc4/vc4_hvs.c @@ -205,6 +205,10 @@ static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct drm_crtc *crtc, u32 dispbkgndx; u32 dispctrl; + HVS_WRITE(SCALER_DISPCTRLX(chan), 0); + HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET); + HVS_WRITE(SCALER_DISPCTRLX(chan), 0); + /* Turn on the scaler, which will wait for vstart to start * compositing. * When feeding the transposer, we should operate in oneshot -- git-series 0.9.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2] drm/bridge: add it6505 driver
This adds support for the iTE IT6505. This device can convert DPI signal to DP output. From: Allen Chen Signed-off-by: Jitao Shi Signed-off-by: Pi-Hsun Shih Signed-off-by: Yilun Lin Signed-off-by: Hermes Wu Signed-off-by: Allen Chen --- drivers/gpu/drm/bridge/Kconfig |7 + drivers/gpu/drm/bridge/Makefile |1 + drivers/gpu/drm/bridge/ite-it6505.c | 3336 +++ 3 files changed, 3344 insertions(+) create mode 100644 drivers/gpu/drm/bridge/ite-it6505.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 3e11af4e9f63e..f21dce3fabeb9 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -61,6 +61,13 @@ config DRM_LONTIUM_LT9611 HDMI signals Please say Y if you have such hardware. +config DRM_ITE_IT6505 + tristate "ITE IT6505 DisplayPort bridge" + depends on OF + select DRM_KMS_HELPER + help + ITE IT6505 DisplayPort bridge chip driver. + config DRM_LVDS_CODEC tristate "Transparent LVDS encoders and decoders support" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index c589a6a7cbe1d..8a118fd901ad7 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o +obj-$(CONFIG_DRM_ITE_IT6505) += ite-it6505.o obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) += megachips-stdp-ge-b850v3-fw.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c new file mode 100644 index 0..a72e524eb20b1 --- /dev/null +++ b/drivers/gpu/drm/bridge/ite-it6505.c @@ -0,0 +1,3336 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define REG_IC_VER 0x04 + +#define REG_RESET_CTRL 0x05 +#define VIDEO_RESET BIT(0) +#define AUDIO_RESET BIT(1) +#define ALL_LOGIC_RESET BIT(2) +#define AUX_RESET BIT(3) +#define HDCP_RESET BIT(4) + +#define INT_STATUS_01 0x06 +#define INT_MASK_01 0x09 +#define INT_HPD_CHANGE BIT(0) +#define INT_RECEIVE_HPD_IRQ BIT(1) +#define INT_SCDT_CHANGE BIT(2) +#define INT_HDCP_FAIL BIT(3) +#define INT_HDCP_DONE BIT(4) + +#define INT_STATUS_02 0x07 +#define INT_MASK_02 0x0A +#define INT_AUX_CMD_FAIL BIT(0) +#define INT_HDCP_KSV_CHECK BIT(1) +#define INT_AUDIO_FIFO_ERROR BIT(2) + +#define INT_STATUS_03 0x08 +#define INT_MASK_03 0x0B +#define INT_LINK_TRAIN_FAIL BIT(4) +#define INT_VID_FIFO_ERROR BIT(5) +#define INT_IO_LATCH_FIFO_OVERFLOW BIT(7) + +#define REG_SYSTEM_STS 0x0D +#define INT_STS BIT(0) +#define HPD_STS BIT(1) +#define VIDEO_STB BIT(2) + +#define REG_LINK_TRAIN_STS 0x0E +#define LINK_STATE_CR BIT(2) +#define LINK_STATE_EQ BIT(3) +#define LINK_STATE_NORP BIT(4) + +#define REG_BANK_SEL 0x0F +#define REG_CLK_CTRL0 0x10 +#define M_PCLK_DELAY 0x03 + +#define REG_AUX_OPT 0x11 +#define AUX_AUTO_RST BIT(0) +#define AUX_FIX_FREQ BIT(3) + +#define REG_DATA_CTRL0 0x12 +#define VIDEO_LATCH_EDGE BIT(4) +#define ENABLE_PCLK_COUNTER BIT(7) + +#define REG_PCLK_COUNTER_VALUE 0x13 + +#define REG_501_FIFO_CTRL 0x15 +#define RST_501_FIFO BIT(1) + +#define REG_TRAIN_CTRL0 0x16 +#define FORCE_LBR BIT(0) +#define LANE_COUNT_MASK 0x06 +#define LANE_SWAP BIT(3) +#define SPREAD_AMP_5 BIT(4) +#define FORCE_CR_DONE BIT(5) +#define FORCE_EQ_DONE BIT(6) + +#define REG_TRAIN_CTRL1 0x17 +#define AUTO_TRAIN BIT(0) +#define MANUAL_TRAIN BIT(1) +#define FORCE_RETRAIN BIT(2) + +#define REG_AUX_CTRL 0x23 +#define CLR_EDID_FIFO BIT(0) +#define AUX_USER_MODE BIT(1) +#define AUX_NO_SEGMENT_WR BIT(6) +#define AUX_EN_FIFO_READ BIT(7) + +#define REG_AUX_ADR_0_7 0x24 +#define REG_AUX_ADR_8_15 0x25 +#define REG_AUX_ADR_16_19 0x26 +#define REG_AUX_OUT_DATA0 0x27 + +#define REG_AUX_CMD_REQ 0x2B +#define AUX_BUSY BIT(5) + +#define REG_AUX_DATA_0_7 0x2C +#define REG_AUX_DATA_8_15 0x2D +#define REG_AUX_DATA_16_23 0x2E +#define REG_AUX_DATA_24_31 0x2F + +#define REG_AUX_DATA_FIFO 0x2F + +#define REG_AUX_ERROR_STS 0x9F +#define M_AUX_REQ_FAIL 0x03 + +#define REG_HDCP_CTRL1 0x38 +#define HDCP_CP_ENABLE BIT(0) + +#define REG_HDCP_TRIGGER 0x39 +#define HDCP_TRIGGER_START BIT(0) +#define HDCP_TRIGGER_CPIRQ BIT(1) +#define HDCP_TRIGGER_KSV_DONE BIT(4) +#define HDCP_TRIGGER_KSV_FAIL BIT(5) + +#define REG_HDCP_CTRL2 0x3A +#define HDCP_AN_SEL BIT(0) +#define HDCP_AN_G
[PATCH v5 28/80] drm/vc4: encoder: Add finer-grained encoder callbacks
In the BCM2711, the setup of the HVS, pixelvalve and HDMI controller
requires very precise ordering and timing that the regular atomic callbacks
don't provide. Let's add new callbacks on top of the regular ones to be
able to split the configuration as needed.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 19 +++
drivers/gpu/drm/vc4/vc4_drv.h | 7 +++
2 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index b7b0e19e2fe1..d0b326e1df0a 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -389,6 +389,8 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
{
struct drm_device *dev = crtc->dev;
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
+ struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
int ret;
require_hvs_enabled(dev);
@@ -401,10 +403,16 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
+ if (vc4_encoder->post_crtc_disable)
+ vc4_encoder->post_crtc_disable(encoder);
+
CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);
vc4_hvs_atomic_disable(crtc, old_state);
+ if (vc4_encoder->post_crtc_powerdown)
+ vc4_encoder->post_crtc_powerdown(encoder);
+
/*
* Make sure we issue a vblank event after disabling the CRTC if
* someone was waiting it.
@@ -424,6 +432,8 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
{
struct drm_device *dev = crtc->dev;
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
+ struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
+ struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
require_hvs_enabled(dev);
@@ -434,15 +444,24 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
vc4_hvs_atomic_enable(crtc, old_state);
+ if (vc4_encoder->pre_crtc_configure)
+ vc4_encoder->pre_crtc_configure(encoder);
+
vc4_crtc_config_pv(crtc);
CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);
+ if (vc4_encoder->pre_crtc_enable)
+ vc4_encoder->pre_crtc_enable(encoder);
+
/* When feeding the transposer block the pixelvalve is unneeded and
* should not be enabled.
*/
CRTC_WRITE(PV_V_CONTROL,
CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
+
+ if (vc4_encoder->post_crtc_enable)
+ vc4_encoder->post_crtc_enable(encoder);
}
static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index dfcc684f5d28..251fcc35530c 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -439,6 +439,13 @@ struct vc4_encoder {
struct drm_encoder base;
enum vc4_encoder_type type;
u32 clock_select;
+
+ void (*pre_crtc_configure)(struct drm_encoder *encoder);
+ void (*pre_crtc_enable)(struct drm_encoder *encoder);
+ void (*post_crtc_enable)(struct drm_encoder *encoder);
+
+ void (*post_crtc_disable)(struct drm_encoder *encoder);
+ void (*post_crtc_powerdown)(struct drm_encoder *encoder);
};
static inline struct vc4_encoder *
--
git-series 0.9.1
___
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 80/80] ARM: dts: bcm2711: Enable the display pipeline
Now that all the drivers have been adjusted for it, let's bring in the
necessary device tree changes.
The VEC and PV3 are left out for now, since it will require a more specific
clock setup.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 48 +++-
arch/arm/boot/dts/bcm2711.dtsi| 122 ++-
2 files changed, 169 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
index e94244a215af..09a1182c2936 100644
--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
@@ -70,6 +70,14 @@
};
};
+&ddc0 {
+ status = "okay";
+};
+
+&ddc1 {
+ status = "okay";
+};
+
&firmware {
firmware_clocks: clocks {
compatible = "raspberrypi,firmware-clocks";
@@ -170,6 +178,38 @@
"RGMII_TXD3";
};
+&hdmi0 {
+ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>,
<&clk_27MHz>;
+ clock-names = "hdmi", "bvb", "audio", "cec";
+ status = "okay";
+};
+
+&hdmi1 {
+ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>,
<&clk_27MHz>;
+ clock-names = "hdmi", "bvb", "audio", "cec";
+ status = "okay";
+};
+
+&hvs {
+ clocks = <&firmware_clocks 4>;
+};
+
+&pixelvalve0 {
+ status = "okay";
+};
+
+&pixelvalve1 {
+ status = "okay";
+};
+
+&pixelvalve2 {
+ status = "okay";
+};
+
+&pixelvalve4 {
+ status = "okay";
+};
+
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>;
@@ -253,3 +293,11 @@
&vchiq {
interrupts = ;
};
+
+&vc4 {
+ status = "okay";
+};
+
+&vec {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
index 00bcaed1be32..4847dd305317 100644
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -12,6 +12,18 @@
interrupt-parent = <&gicv2>;
+ vc4: gpu {
+ compatible = "brcm,bcm2711-vc5";
+ status = "disabled";
+ };
+
+ clk_27MHz: clk-27M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2700>;
+ clock-output-names = "27MHz-clock";
+ };
+
clk_108MHz: clk-108M {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -238,6 +250,27 @@
status = "disabled";
};
+ pixelvalve0: pixelvalve@7e206000 {
+ compatible = "brcm,bcm2711-pixelvalve0";
+ reg = <0x7e206000 0x100>;
+ interrupts = ;
+ status = "disabled";
+ };
+
+ pixelvalve1: pixelvalve@7e207000 {
+ compatible = "brcm,bcm2711-pixelvalve1";
+ reg = <0x7e207000 0x100>;
+ interrupts = ;
+ status = "disabled";
+ };
+
+ pixelvalve2: pixelvalve@7e20a000 {
+ compatible = "brcm,bcm2711-pixelvalve2";
+ reg = <0x7e20a000 0x100>;
+ interrupts = ;
+ status = "disabled";
+ };
+
pwm1: pwm@7e20c800 {
compatible = "brcm,bcm2835-pwm";
reg = <0x7e20c800 0x28>;
@@ -248,10 +281,25 @@
status = "disabled";
};
- hvs@7e40 {
+ pixelvalve4: pixelvalve@7e216000 {
+ compatible = "brcm,bcm2711-pixelvalve4";
+ reg = <0x7e216000 0x100>;
+ interrupts = ;
+ status = "disabled";
+ };
+
+ hvs: hvs@7e40 {
+ compatible = "brcm,bcm2711-hvs";
interrupts = ;
};
+ pixelvalve3: pixelvalve@7ec12000 {
+ compatible = "brcm,bcm2711-pixelvalve3";
+ reg = <0x7ec12000 0x100>;
+ interrupts = ;
+ status = "disabled";
+ };
+
dvp: clock@7ef0 {
compatible = "brcm,brcm2711-dvp";
reg = <0x7ef0 0x10>;
@@ -259,6 +307,78 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ hdmi0: hdmi@7ef00700 {
+ compatible = "brcm,bcm2711-hdmi0";
+ reg = <0x7ef00700 0x300>,
+ <0x7ef00300 0x200>,
+ <0x7ef00f00 0x80>,
+ <0x7ef00f80 0x80>,
+
Re: [PATCH v10 07/17] pwm: lpss: Remove suspend/resume handlers
On Thu, Sep 03, 2020 at 01:23:27PM +0200, Hans de Goede wrote:
> PWM controller drivers should not restore the PWM state on resume. The
> convention is that PWM consumers do this by calling pwm_apply_state(),
> so that it can be done at the exact moment when the consumer needs
> the state to be stored, avoiding e.g. backlight flickering.
>
> The only in kernel consumers of the pwm-lpss code, the i915 driver
> and the pwm-class sysfs interface code both correctly restore the
> state on resume, so there is no need to do this in the pwm-lpss code.
>
> More-over the removed resume handler is buggy, since it blindly
> restores the ctrl-register contents without setting the update
> bit, which is necessary to get the controller to actually use/apply
> the restored base-unit and on-time-div values.
While this is okay
Reviewed-by: Andy Shevchenko
the question is do we need to have similar in acpi_lpss.c?
For example,
static const struct lpss_device_desc byt_pwm_dev_desc = {
.flags = LPSS_SAVE_CTX,
^^
.prv_offset = 0x800,
.setup = byt_pwm_setup,
};
static const struct lpss_device_desc bsw_pwm_dev_desc = {
.flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
^^
.prv_offset = 0x800,
.setup = bsw_pwm_setup,
};
> Acked-by: Thierry Reding
> Signed-off-by: Hans de Goede
> ---
> Changes in v9:
> - This is a new patch in v9 of this series
> ---
> drivers/pwm/pwm-lpss-platform.c | 1 -
> drivers/pwm/pwm-lpss.c | 24
> drivers/pwm/pwm-lpss.h | 3 ---
> 3 files changed, 28 deletions(-)
>
> diff --git a/drivers/pwm/pwm-lpss-platform.c b/drivers/pwm/pwm-lpss-platform.c
> index 48f34d20aecd..c6502cf7a7af 100644
> --- a/drivers/pwm/pwm-lpss-platform.c
> +++ b/drivers/pwm/pwm-lpss-platform.c
> @@ -89,7 +89,6 @@ static int pwm_lpss_prepare(struct device *dev)
>
> static const struct dev_pm_ops pwm_lpss_platform_pm_ops = {
> .prepare = pwm_lpss_prepare,
> - SET_SYSTEM_SLEEP_PM_OPS(pwm_lpss_suspend, pwm_lpss_resume)
> };
>
> static const struct acpi_device_id pwm_lpss_acpi_match[] = {
> diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c
> index 9c5c7217c9b6..3444c56b4bed 100644
> --- a/drivers/pwm/pwm-lpss.c
> +++ b/drivers/pwm/pwm-lpss.c
> @@ -260,30 +260,6 @@ int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
> }
> EXPORT_SYMBOL_GPL(pwm_lpss_remove);
>
> -int pwm_lpss_suspend(struct device *dev)
> -{
> - struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
> - int i;
> -
> - for (i = 0; i < lpwm->info->npwm; i++)
> - lpwm->saved_ctrl[i] = readl(lpwm->regs + i * PWM_SIZE + PWM);
> -
> - return 0;
> -}
> -EXPORT_SYMBOL_GPL(pwm_lpss_suspend);
> -
> -int pwm_lpss_resume(struct device *dev)
> -{
> - struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev);
> - int i;
> -
> - for (i = 0; i < lpwm->info->npwm; i++)
> - writel(lpwm->saved_ctrl[i], lpwm->regs + i * PWM_SIZE + PWM);
> -
> - return 0;
> -}
> -EXPORT_SYMBOL_GPL(pwm_lpss_resume);
> -
> MODULE_DESCRIPTION("PWM driver for Intel LPSS");
> MODULE_AUTHOR("Mika Westerberg ");
> MODULE_LICENSE("GPL v2");
> diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h
> index 7909fa12fca2..70db7e389d66 100644
> --- a/drivers/pwm/pwm-lpss.h
> +++ b/drivers/pwm/pwm-lpss.h
> @@ -19,7 +19,6 @@ struct pwm_lpss_chip {
> struct pwm_chip chip;
> void __iomem *regs;
> const struct pwm_lpss_boardinfo *info;
> - u32 saved_ctrl[MAX_PWMS];
> };
>
> struct pwm_lpss_boardinfo {
> @@ -37,7 +36,5 @@ struct pwm_lpss_boardinfo {
> struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
>const struct pwm_lpss_boardinfo *info);
> int pwm_lpss_remove(struct pwm_lpss_chip *lpwm);
> -int pwm_lpss_suspend(struct device *dev);
> -int pwm_lpss_resume(struct device *dev);
>
> #endif /* __PWM_LPSS_H */
> --
> 2.28.0
>
--
With Best Regards,
Andy Shevchenko
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[PATCH v5 43/80] drm/vc4: hdmi: Move accessors to vc4_hdmi
The current driver only supports a single HDMI controller, and part of
the issue is that the main vc4_dev structure holds a pointer to its
(only) HDMI controller, and the HDMI registers accessors will use it to
retrieve the mapped addresses.
Let's modify those accessors to use directly the vc4_hdmi structure so
that we can eventually get rid of that single global pointer.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 22 --
drivers/gpu/drm/vc4/vc4_hdmi.h | 8
2 files changed, 12 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 6733e4bc235b..81c0f67cd0eb 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -123,6 +123,7 @@ vc4_hdmi_connector_detect(struct drm_connector *connector,
bool force)
{
struct drm_device *dev = connector->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
+ struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
if (vc4->hdmi->hpd_gpio) {
if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
@@ -230,6 +231,7 @@ static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
{
struct drm_device *dev = encoder->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
+ struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
u32 packet_id = type - 0x80;
HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
@@ -244,6 +246,7 @@ static void vc4_hdmi_write_infoframe(struct drm_encoder
*encoder,
{
struct drm_device *dev = encoder->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
+ struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
u32 packet_id = frame->any.type - 0x80;
u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id);
uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
@@ -623,9 +626,6 @@ static const struct drm_encoder_helper_funcs
vc4_hdmi_encoder_helper_funcs = {
/* HDMI audio codec callbacks */
static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi)
{
- struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
- struct drm_device *drm = encoder->dev;
- struct vc4_dev *vc4 = to_vc4_dev(drm);
u32 hsm_clock = clk_get_rate(vc4_hdmi->hsm_clock);
unsigned long n, m;
@@ -645,8 +645,6 @@ static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi)
{
struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
struct drm_crtc *crtc = encoder->crtc;
- struct drm_device *drm = encoder->dev;
- struct vc4_dev *vc4 = to_vc4_dev(drm);
const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
u32 samplerate = vc4_hdmi->audio.samplerate;
u32 n, cts;
@@ -683,7 +681,6 @@ static int vc4_hdmi_audio_startup(struct snd_pcm_substream
*substream,
struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
struct drm_connector *connector = &vc4_hdmi->connector.base;
- struct vc4_dev *vc4 = to_vc4_dev(encoder->dev);
int ret;
if (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream)
@@ -714,9 +711,7 @@ static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
{
struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
- struct drm_device *drm = encoder->dev;
struct device *dev = &vc4_hdmi->pdev->dev;
- struct vc4_dev *vc4 = to_vc4_dev(drm);
int ret;
ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO);
@@ -747,10 +742,7 @@ static int vc4_hdmi_audio_hw_params(struct
snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
- struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
- struct drm_device *drm = encoder->dev;
struct device *dev = &vc4_hdmi->pdev->dev;
- struct vc4_dev *vc4 = to_vc4_dev(drm);
u32 audio_packet_config, channel_mask;
u32 channel_map, i;
@@ -821,8 +813,6 @@ static int vc4_hdmi_audio_trigger(struct snd_pcm_substream
*substream, int cmd,
{
struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
- struct drm_device *drm = encoder->dev;
- struct vc4_dev *vc4 = to_vc4_dev(drm);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
@@ -1082,7 +1072,8 @@ static irqreturn_t vc4_cec_irq_handler_thread(int irq,
void *priv)
static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1)
{
- struct cec_msg *msg = &vc4->hdmi->cec_rx_msg;
+ struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
+ struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
unsigned int i;
msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
@@ -112
[PATCH v5 79/80] drm/vc4: drv: Support BCM2711
The BCM2711 has a reworked display pipeline, and the load tracker needs
some adjustment to operate properly. Let's add a compatible for BCM2711
and disable the load tracker until properly supported.
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_drv.c | 1 +-
drivers/gpu/drm/vc4/vc4_drv.h | 3 ++-
drivers/gpu/drm/vc4/vc4_kms.c | 44 +++---
drivers/gpu/drm/vc4/vc4_plane.c | 5 -
4 files changed, 40 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
index 9567d1019212..f1a5fd5dab6f 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.c
+++ b/drivers/gpu/drm/vc4/vc4_drv.c
@@ -372,6 +372,7 @@ static int vc4_platform_drm_remove(struct platform_device
*pdev)
}
static const struct of_device_id vc4_of_match[] = {
+ { .compatible = "brcm,bcm2711-vc5", },
{ .compatible = "brcm,bcm2835-vc4", },
{ .compatible = "brcm,cygnus-vc4", },
{},
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 501a48a714d3..8c8d96b6289f 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -200,6 +200,9 @@ struct vc4_dev {
int power_refcount;
+ /* Set to true when the load tracker is supported. */
+ bool load_tracker_available;
+
/* Set to true when the load tracker is active. */
bool load_tracker_enabled;
diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index bfc7ddd49ac5..16e233e1406e 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -536,6 +536,9 @@ static int vc4_load_tracker_atomic_check(struct
drm_atomic_state *state)
struct drm_plane *plane;
int i;
+ if (!vc4->load_tracker_available)
+ return 0;
+
priv_state = drm_atomic_get_private_obj_state(state,
&vc4->load_tracker);
if (IS_ERR(priv_state))
@@ -683,12 +686,18 @@ int vc4_kms_load(struct drm_device *dev)
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_ctm_state *ctm_state;
struct vc4_load_tracker_state *load_state;
+ bool is_vc5 = of_device_is_compatible(dev->dev->of_node,
+ "brcm,bcm2711-vc5");
int ret;
- /* Start with the load tracker enabled. Can be disabled through the
-* debugfs load_tracker file.
-*/
- vc4->load_tracker_enabled = true;
+ if (!is_vc5) {
+ vc4->load_tracker_available = true;
+
+ /* Start with the load tracker enabled. Can be
+* disabled through the debugfs load_tracker file.
+*/
+ vc4->load_tracker_enabled = true;
+ }
sema_init(&vc4->async_modeset, 1);
@@ -702,8 +711,14 @@ int vc4_kms_load(struct drm_device *dev)
return ret;
}
- dev->mode_config.max_width = 2048;
- dev->mode_config.max_height = 2048;
+ if (is_vc5) {
+ dev->mode_config.max_width = 7680;
+ dev->mode_config.max_height = 7680;
+ } else {
+ dev->mode_config.max_width = 2048;
+ dev->mode_config.max_height = 2048;
+ }
+
dev->mode_config.funcs = &vc4_mode_funcs;
dev->mode_config.preferred_depth = 24;
dev->mode_config.async_page_flip = true;
@@ -718,14 +733,17 @@ int vc4_kms_load(struct drm_device *dev)
drm_atomic_private_obj_init(dev, &vc4->ctm_manager, &ctm_state->base,
&vc4_ctm_state_funcs);
- load_state = kzalloc(sizeof(*load_state), GFP_KERNEL);
- if (!load_state) {
- drm_atomic_private_obj_fini(&vc4->ctm_manager);
- return -ENOMEM;
- }
+ if (vc4->load_tracker_available) {
+ load_state = kzalloc(sizeof(*load_state), GFP_KERNEL);
+ if (!load_state) {
+ drm_atomic_private_obj_fini(&vc4->ctm_manager);
+ return -ENOMEM;
+ }
- drm_atomic_private_obj_init(dev, &vc4->load_tracker, &load_state->base,
- &vc4_load_tracker_state_funcs);
+ drm_atomic_private_obj_init(dev, &vc4->load_tracker,
+ &load_state->base,
+ &vc4_load_tracker_state_funcs);
+ }
drm_mode_config_reset(dev);
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 1e38e603f83b..24d7e6db6fdd 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -516,6 +516,11 @@ static void vc4_plane_calc_load(struct drm_plane_state
*state)
struct vc4_plane_state *vc4_state;
struct drm_crtc_state *crtc_state;
unsigned int vscale_facto
Re: [PATCH 0/8] Convert the intel iommu driver to the dma-iommu api
On Fri, 28 Aug 2020 at 00:34, Tom Murphy wrote:
>
> On Thu, 27 Aug 2020 at 22:36, Logan Gunthorpe wrote:
> >
> >
> >
> > On 2020-08-23 6:04 p.m., Tom Murphy wrote:
> > > I have added a check for the sg_dma_len == 0 :
> > > """
> > > } __sgt_iter(struct scatterlist *sgl, bool dma) {
> > > struct sgt_iter s = { .sgp = sgl };
> > >
> > > + if (sgl && sg_dma_len(sgl) == 0)
> > > + s.sgp = NULL;
> > >
> > > if (s.sgp) {
> > > .
> > > """
> > > at location [1].
> > > but it doens't fix the problem.
> >
> > Based on my read of the code, it looks like we also need to change usage
> > of sgl->length... Something like the rough patch below, maybe?
> >
> > Also, Tom, do you have an updated version of the patchset to convert the
> > Intel IOMMU to dma-iommu available? The last one I've found doesn't
> > apply cleanly (I'm assuming parts of it have been merged in slightly
> > modified forms).
> >
>
> I'll try and post one in the next 24hours
I have just posted this now:
The subject of the cover letter is:
"[PATCH V2 0/5] Convert the intel iommu driver to the dma-iommu api"
>
> > Thanks,
> >
> > Logan
> >
> > --
> >
> > diff --git a/drivers/gpu/drm/i915/i915_scatterlist.h
> > b/drivers/gpu/drm/i915/i915
> > index b7b59328cb76..9367ac801f0c 100644
> > --- a/drivers/gpu/drm/i915/i915_scatterlist.h
> > +++ b/drivers/gpu/drm/i915/i915_scatterlist.h
> > @@ -27,13 +27,19 @@ static __always_inline struct sgt_iter {
> > } __sgt_iter(struct scatterlist *sgl, bool dma) {
> > struct sgt_iter s = { .sgp = sgl };
> >
> > + if (sgl && !sg_dma_len(s.sgp))
> > + s.sgp = NULL;
> > +
> > if (s.sgp) {
> > s.max = s.curr = s.sgp->offset;
> > - s.max += s.sgp->length;
> > - if (dma)
> > +
> > + if (dma) {
> > + s.max += sg_dma_len(s.sgp);
> > s.dma = sg_dma_address(s.sgp);
> > - else
> > + } else {
> > + s.max += s.sgp->length;
> > s.pfn = page_to_pfn(sg_page(s.sgp));
> > + }
> > }
> >
> > return s;
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[PATCH v3] drm/bridge: add it6505 driver
This adds support for the iTE IT6505. This device can convert DPI signal to DP output. From: Allen Chen Signed-off-by: Jitao Shi Signed-off-by: Pi-Hsun Shih Signed-off-by: Yilun Lin Signed-off-by: Hermes Wu Signed-off-by: Allen Chen Reported-by: kernel test robot --- drivers/gpu/drm/bridge/Kconfig |7 + drivers/gpu/drm/bridge/Makefile |1 + drivers/gpu/drm/bridge/ite-it6505.c | 3338 +++ 3 files changed, 3346 insertions(+) create mode 100644 drivers/gpu/drm/bridge/ite-it6505.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 3e11af4e9f63e..f21dce3fabeb9 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -61,6 +61,13 @@ config DRM_LONTIUM_LT9611 HDMI signals Please say Y if you have such hardware. +config DRM_ITE_IT6505 + tristate "ITE IT6505 DisplayPort bridge" + depends on OF + select DRM_KMS_HELPER + help + ITE IT6505 DisplayPort bridge chip driver. + config DRM_LVDS_CODEC tristate "Transparent LVDS encoders and decoders support" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index c589a6a7cbe1d..8a118fd901ad7 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o +obj-$(CONFIG_DRM_ITE_IT6505) += ite-it6505.o obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) += megachips-stdp-ge-b850v3-fw.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c new file mode 100644 index 0..0ed19673431ee --- /dev/null +++ b/drivers/gpu/drm/bridge/ite-it6505.c @@ -0,0 +1,3338 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define REG_IC_VER 0x04 + +#define REG_RESET_CTRL 0x05 +#define VIDEO_RESET BIT(0) +#define AUDIO_RESET BIT(1) +#define ALL_LOGIC_RESET BIT(2) +#define AUX_RESET BIT(3) +#define HDCP_RESET BIT(4) + +#define INT_STATUS_01 0x06 +#define INT_MASK_01 0x09 +#define INT_HPD_CHANGE BIT(0) +#define INT_RECEIVE_HPD_IRQ BIT(1) +#define INT_SCDT_CHANGE BIT(2) +#define INT_HDCP_FAIL BIT(3) +#define INT_HDCP_DONE BIT(4) + +#define INT_STATUS_02 0x07 +#define INT_MASK_02 0x0A +#define INT_AUX_CMD_FAIL BIT(0) +#define INT_HDCP_KSV_CHECK BIT(1) +#define INT_AUDIO_FIFO_ERROR BIT(2) + +#define INT_STATUS_03 0x08 +#define INT_MASK_03 0x0B +#define INT_LINK_TRAIN_FAIL BIT(4) +#define INT_VID_FIFO_ERROR BIT(5) +#define INT_IO_LATCH_FIFO_OVERFLOW BIT(7) + +#define REG_SYSTEM_STS 0x0D +#define INT_STS BIT(0) +#define HPD_STS BIT(1) +#define VIDEO_STB BIT(2) + +#define REG_LINK_TRAIN_STS 0x0E +#define LINK_STATE_CR BIT(2) +#define LINK_STATE_EQ BIT(3) +#define LINK_STATE_NORP BIT(4) + +#define REG_BANK_SEL 0x0F +#define REG_CLK_CTRL0 0x10 +#define M_PCLK_DELAY 0x03 + +#define REG_AUX_OPT 0x11 +#define AUX_AUTO_RST BIT(0) +#define AUX_FIX_FREQ BIT(3) + +#define REG_DATA_CTRL0 0x12 +#define VIDEO_LATCH_EDGE BIT(4) +#define ENABLE_PCLK_COUNTER BIT(7) + +#define REG_PCLK_COUNTER_VALUE 0x13 + +#define REG_501_FIFO_CTRL 0x15 +#define RST_501_FIFO BIT(1) + +#define REG_TRAIN_CTRL0 0x16 +#define FORCE_LBR BIT(0) +#define LANE_COUNT_MASK 0x06 +#define LANE_SWAP BIT(3) +#define SPREAD_AMP_5 BIT(4) +#define FORCE_CR_DONE BIT(5) +#define FORCE_EQ_DONE BIT(6) + +#define REG_TRAIN_CTRL1 0x17 +#define AUTO_TRAIN BIT(0) +#define MANUAL_TRAIN BIT(1) +#define FORCE_RETRAIN BIT(2) + +#define REG_AUX_CTRL 0x23 +#define CLR_EDID_FIFO BIT(0) +#define AUX_USER_MODE BIT(1) +#define AUX_NO_SEGMENT_WR BIT(6) +#define AUX_EN_FIFO_READ BIT(7) + +#define REG_AUX_ADR_0_7 0x24 +#define REG_AUX_ADR_8_15 0x25 +#define REG_AUX_ADR_16_19 0x26 +#define REG_AUX_OUT_DATA0 0x27 + +#define REG_AUX_CMD_REQ 0x2B +#define AUX_BUSY BIT(5) + +#define REG_AUX_DATA_0_7 0x2C +#define REG_AUX_DATA_8_15 0x2D +#define REG_AUX_DATA_16_23 0x2E +#define REG_AUX_DATA_24_31 0x2F + +#define REG_AUX_DATA_FIFO 0x2F + +#define REG_AUX_ERROR_STS 0x9F +#define M_AUX_REQ_FAIL 0x03 + +#define REG_HDCP_CTRL1 0x38 +#define HDCP_CP_ENABLE BIT(0) + +#define REG_HDCP_TRIGGER 0x39 +#define HDCP_TRIGGER_START BIT(0) +#define HDCP_TRIGGER_CPIRQ BIT(1) +#define HDCP_TRIGGER_KSV_DONE BIT(4) +#define HDCP_TRIGGER_KSV_FAIL BIT(5) + +#define REG_HDCP_CTRL2 0x3A +#define HDCP_
[PATCH v5 69/80] drm/vc4: hdmi: Deal with multiple ALSA cards
The HDMI driver was registering a single ALSA card so far with the name
vc4-hdmi.
Obviously, this is not going to work anymore when we will have multiple
HDMI controllers since we will end up trying to register two files with the
same name.
Let's use the variant to avoid that name conflict.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 3 ++-
drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 20cfc85449ca..5e479647559f 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1043,7 +1043,7 @@ static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
card->dai_link = dai_link;
card->num_links = 1;
- card->name = "vc4-hdmi";
+ card->name = vc4_hdmi->variant->card_name;
card->dev = dev;
/*
@@ -1502,6 +1502,7 @@ static int vc4_hdmi_dev_remove(struct platform_device
*pdev)
static const struct vc4_hdmi_variant bcm2835_variant = {
.encoder_type = VC4_ENCODER_TYPE_HDMI0,
.debugfs_name = "hdmi_regs",
+ .card_name = "vc4-hdmi",
.max_pixel_clock= 16200,
.cec_available = true,
.registers = vc4_hdmi_fields,
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index 4aea5ee8a91d..34138e0dd4a6 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -30,6 +30,9 @@ struct vc4_hdmi_variant {
/* Encoder Type for that controller */
enum vc4_encoder_type encoder_type;
+ /* ALSA card name */
+ const char *card_name;
+
/* Filename to expose the registers in debugfs */
const char *debugfs_name;
--
git-series 0.9.1
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[PATCH v5 57/80] drm/vc4: hdmi: Store the encoder type in the variant structure
The vc4 CRTC will use the encoder type to control its output clock
muxing. However, this will be different from HDMI0 to HDMI1, so let's
store our type in the variant structure so that we can support multiple
controllers later on.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 3 ++-
drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 9e2bc6cb690e..f6d18bdbd1bb 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1267,7 +1267,7 @@ static int vc4_hdmi_bind(struct device *dev, struct
device *master, void *data)
dev_set_drvdata(dev, vc4_hdmi);
encoder = &vc4_hdmi->encoder.base.base;
- vc4_hdmi->encoder.base.type = VC4_ENCODER_TYPE_HDMI0;
+ vc4_hdmi->encoder.base.type = variant->encoder_type;
vc4_hdmi->pdev = pdev;
vc4_hdmi->variant = variant;
@@ -1446,6 +1446,7 @@ static int vc4_hdmi_dev_remove(struct platform_device
*pdev)
}
static const struct vc4_hdmi_variant bcm2835_variant = {
+ .encoder_type = VC4_ENCODER_TYPE_HDMI0,
.registers = vc4_hdmi_fields,
.num_registers = ARRAY_SIZE(vc4_hdmi_fields),
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index 0c32dc46d289..0d529db4b3ab 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -27,6 +27,9 @@ struct vc4_hdmi;
struct vc4_hdmi_register;
struct vc4_hdmi_variant {
+ /* Encoder Type for that controller */
+ enum vc4_encoder_type encoder_type;
+
/* List of the registers available on that variant */
const struct vc4_hdmi_register *registers;
--
git-series 0.9.1
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[PATCH 2/3] drm/v3d: Correctly restart the timer when progress is made
From: Yukimasa Sugizaki
The V3D scheduler wants a timed-out job to continue running if it made
progress. However, the current DRM scheduler removes the timed-out job
from ring_mirror_list and thus the timer is not restarted automatically,
resulting in an infinite timeout. We need stop and restart the DRM
scheduler to rearm the timer.
Fixes: 135517d3565b ("drm/scheduler: Avoid accessing freed bad job.")
Signed-off-by: Yukimasa Sugizaki
---
drivers/gpu/drm/v3d/v3d_sched.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/v3d/v3d_sched.c b/drivers/gpu/drm/v3d/v3d_sched.c
index 001216f22017..feef0c749e68 100644
--- a/drivers/gpu/drm/v3d/v3d_sched.c
+++ b/drivers/gpu/drm/v3d/v3d_sched.c
@@ -312,9 +312,24 @@ v3d_cl_job_timedout(struct drm_sched_job *sched_job, enum
v3d_queue q,
u32 ctca = V3D_CORE_READ(0, V3D_CLE_CTNCA(q));
u32 ctra = V3D_CORE_READ(0, V3D_CLE_CTNRA(q));
+ /* If we've made progress, skip reset and let the timer get
+* rearmed.
+*/
if (*timedout_ctca != ctca || *timedout_ctra != ctra) {
*timedout_ctca = ctca;
*timedout_ctra = ctra;
+
+ /* Because the timed-out job has been removed from
+* ring_mirror_list in drm_sched_job_timedout(), we need to
+* stop and restart the scheduler to rearm the timer.
+* Holding the reset_lock is necessary for concurrent
+* v3d_gpu_reset_for_timeout().
+*/
+ mutex_lock(&v3d->reset_lock);
+ drm_sched_stop(sched_job->sched, sched_job);
+ drm_sched_start(sched_job->sched, sched_job);
+ mutex_unlock(&v3d->reset_lock);
+
return;
}
@@ -359,6 +374,18 @@ v3d_csd_job_timedout(struct drm_sched_job *sched_job)
*/
if (job->timedout_batches != batches) {
job->timedout_batches = batches;
+
+ /* Because the timed-out job has been removed from
+* ring_mirror_list in drm_sched_job_timedout(), we need to
+* stop and restart the scheduler to rearm the timer.
+* Holding the reset_lock is necessary for concurrent
+* v3d_gpu_reset_for_timeout().
+*/
+ mutex_lock(&v3d->reset_lock);
+ drm_sched_stop(sched_job->sched, sched_job);
+ drm_sched_start(sched_job->sched, sched_job);
+ mutex_unlock(&v3d->reset_lock);
+
return;
}
--
2.7.4
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[PATCH v5 58/80] drm/vc4: hdmi: Deal with multiple debugfs files
The HDMI driver was registering a single debugfs file so far with the name
hdmi_regs.
Obviously, this is not going to work anymore when will have multiple HDMI
controllers since we will end up trying to register two files with the same
name.
Let's use the variant to avoid that name conflict.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 5 -
drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index f6d18bdbd1bb..4d0b44a2ac61 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1369,7 +1369,9 @@ static int vc4_hdmi_bind(struct device *dev, struct
device *master, void *data)
if (ret)
goto err_destroy_encoder;
- vc4_debugfs_add_file(drm, "hdmi_regs", vc4_hdmi_debugfs_regs, vc4_hdmi);
+ vc4_debugfs_add_file(drm, variant->debugfs_name,
+vc4_hdmi_debugfs_regs,
+vc4_hdmi);
return 0;
@@ -1447,6 +1449,7 @@ static int vc4_hdmi_dev_remove(struct platform_device
*pdev)
static const struct vc4_hdmi_variant bcm2835_variant = {
.encoder_type = VC4_ENCODER_TYPE_HDMI0,
+ .debugfs_name = "hdmi_regs",
.registers = vc4_hdmi_fields,
.num_registers = ARRAY_SIZE(vc4_hdmi_fields),
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index 0d529db4b3ab..794216f3228d 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -30,6 +30,9 @@ struct vc4_hdmi_variant {
/* Encoder Type for that controller */
enum vc4_encoder_type encoder_type;
+ /* Filename to expose the registers in debugfs */
+ const char *debugfs_name;
+
/* List of the registers available on that variant */
const struct vc4_hdmi_register *registers;
--
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[PATCH v5 73/80] drm/vc4: hdmi: Do the VID_CTL configuration at once
The VID_CTL setup is done in several places in the driver even though it's
not really required. Let's simplify it a bit to do the configuration in one
go.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 128d33c8c2c3..8bf69cafdd7e 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -428,10 +428,6 @@ static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
HDMI_WRITE(HDMI_VERTB0, vertb_even);
HDMI_WRITE(HDMI_VERTB1, vertb);
-
- HDMI_WRITE(HDMI_VID_CTL,
- (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
- (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
}
static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
@@ -520,8 +516,6 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct
drm_encoder *encoder)
if (vc4_hdmi->variant->phy_init)
vc4_hdmi->variant->phy_init(vc4_hdmi, mode);
- HDMI_WRITE(HDMI_VID_CTL, 0);
-
HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
HDMI_READ(HDMI_SCHEDULER_CONTROL) |
VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
@@ -555,15 +549,19 @@ static void vc4_hdmi_encoder_pre_crtc_enable(struct
drm_encoder *encoder)
static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder)
{
+ struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
+ bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
+ bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
int ret;
HDMI_WRITE(HDMI_VID_CTL,
- HDMI_READ(HDMI_VID_CTL) |
VC4_HD_VID_CTL_ENABLE |
VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
- VC4_HD_VID_CTL_FRAME_COUNTER_RESET);
+ VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
+ (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
+ (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
if (vc4_encoder->hdmi_monitor) {
HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
--
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[PATCH v5 18/80] drm/vc4: crtc: Add HDMI1 encoder type
The BCM2711 sports a second HDMI controller, so let's add that second HDMI
encoder type.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 5781773aec4b..4126506b3a69 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -427,6 +427,7 @@ to_vc4_plane_state(struct drm_plane_state *state)
enum vc4_encoder_type {
VC4_ENCODER_TYPE_NONE,
VC4_ENCODER_TYPE_HDMI0,
+ VC4_ENCODER_TYPE_HDMI1,
VC4_ENCODER_TYPE_VEC,
VC4_ENCODER_TYPE_DSI0,
VC4_ENCODER_TYPE_DSI1,
--
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[PATCH v5 41/80] drm/vc4: hdmi: Remove DDC argument to connector_init
Now that we are passing the vc4_hdmi structure to the connector init
function, we can simply use the pointer in that structure instead of
having the pointer as an argument.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 9a0612a87fb8..1f350b068fcd 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -192,8 +192,7 @@ static const struct drm_connector_helper_funcs
vc4_hdmi_connector_helper_funcs =
};
static int vc4_hdmi_connector_init(struct drm_device *dev,
- struct vc4_hdmi *vc4_hdmi,
- struct i2c_adapter *ddc)
+ struct vc4_hdmi *vc4_hdmi)
{
struct vc4_hdmi_connector *hdmi_connector = &vc4_hdmi->connector;
struct drm_connector *connector = &hdmi_connector->base;
@@ -205,7 +204,7 @@ static int vc4_hdmi_connector_init(struct drm_device *dev,
drm_connector_init_with_ddc(dev, connector,
&vc4_hdmi_connector_funcs,
DRM_MODE_CONNECTOR_HDMIA,
- ddc);
+ vc4_hdmi->ddc);
drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
/* Create and attach TV margin props to this connector. */
@@ -1322,7 +1321,7 @@ static int vc4_hdmi_bind(struct device *dev, struct
device *master, void *data)
drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
- ret = vc4_hdmi_connector_init(drm, hdmi, hdmi->ddc);
+ ret = vc4_hdmi_connector_init(drm, hdmi);
if (ret)
goto err_destroy_encoder;
--
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[PATCH v5 16/80] drm/vc4: crtc: Add function to compute FIFO level bits
The longer FIFOs in vc5 pixelvalves means that the FIFO full level
doesn't fit in the original register field and that we also have a
secondary field. In order to prepare for this, let's move the registers
fill part to a helper function.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_crtc.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 2c64efd2d3d9..1d9e3658ae59 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -234,6 +234,15 @@ static u32 vc4_get_fifo_full_level(struct vc4_crtc
*vc4_crtc, u32 format)
}
}
+static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc,
+u32 format)
+{
+ u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
+
+ return VC4_SET_FIELD(level & 0x3f,
+PV_CONTROL_FIFO_LEVEL);
+}
+
/*
* Returns the encoder attached to the CRTC.
*
@@ -336,9 +345,8 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
CRTC_WRITE(PV_CONTROL,
+ vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
- VC4_SET_FIELD(vc4_get_fifo_full_level(vc4_crtc, format),
-PV_CONTROL_FIFO_LEVEL) |
VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
PV_CONTROL_CLR_AT_START |
PV_CONTROL_TRIGGER_UNDERFLOW |
--
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[PATCH v5 52/80] drm/vc4: hdmi: Add reset callback
The BCM2711 and BCM283x HDMI controllers use a slightly different reset
sequence, so let's add a callback to reset the controller.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 31 ++-
drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +++
2 files changed, 21 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index adc7c0693650..77971be075ec 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -69,6 +69,21 @@ static int vc4_hdmi_debugfs_regs(struct seq_file *m, void
*unused)
return 0;
}
+static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
+{
+ HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
+ udelay(1);
+ HDMI_WRITE(HDMI_M_CTL, 0);
+
+ HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
+
+ HDMI_WRITE(HDMI_SW_RESET_CONTROL,
+ VC4_HDMI_SW_RESET_HDMI |
+ VC4_HDMI_SW_RESET_FORMAT_DETECT);
+
+ HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
+}
+
static enum drm_connector_status
vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
{
@@ -363,11 +378,8 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
return;
}
- HDMI_WRITE(HDMI_SW_RESET_CONTROL,
- VC4_HDMI_SW_RESET_HDMI |
- VC4_HDMI_SW_RESET_FORMAT_DETECT);
-
- HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
+ if (vc4_hdmi->variant->reset)
+ vc4_hdmi->variant->reset(vc4_hdmi);
/* PHY should be in reset, like
* vc4_hdmi_encoder_disable() does.
@@ -1291,14 +1303,6 @@ static int vc4_hdmi_bind(struct device *dev, struct
device *master, void *data)
vc4_hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
}
- /* HDMI core must be enabled. */
- if (!(HDMI_READ(HDMI_M_CTL) & VC4_HD_M_ENABLE)) {
- HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
- udelay(1);
- HDMI_WRITE(HDMI_M_CTL, 0);
-
- HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
- }
pm_runtime_enable(dev);
drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
@@ -1427,6 +1431,7 @@ static const struct vc4_hdmi_variant bcm2835_variant = {
.num_registers = ARRAY_SIZE(vc4_hdmi_fields),
.init_resources = vc4_hdmi_init_resources,
+ .reset = vc4_hdmi_reset,
};
static const struct of_device_id vc4_hdmi_dt_match[] = {
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index b36e0210671f..17a30589f39c 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -35,6 +35,9 @@ struct vc4_hdmi_variant {
* clocks, etc) for that variant.
*/
int (*init_resources)(struct vc4_hdmi *vc4_hdmi);
+
+ /* Callback to reset the HDMI block */
+ void (*reset)(struct vc4_hdmi *vc4_hdmi);
};
/* HDMI audio information */
--
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[PATCH 0/3] drm/v3d: CL/CSD job timeout fixes
From: Yukimasa Sugizaki Hi, The current V3D scheduler has two issues where CSD jobs are resubmitted regardless of the previous timed-out flag, and where the timer is not restarted for timed-out CL/CSD jobs (which we wish to continue running). The second one is due to the DRM scheduler API change and fixed in a similar way to [1]. A kernel command-line option to set the default timeout value is also added. I tested this patchset with Piglit and our CSD programs in [2]. Because it is hard to get the current upstream kernel to work on BCM2711, I used the kernel from rpi-5.8.y tree [3]. There still are problems where some Piglit tests get longer time to finish running (3610 minutes to 3650 minutes in total), and some ones result in the invalid memory read errors with unknown reasons: [17086.230959] v3d fec0.v3d: MMU error from client CLE (4) at 0xac1000, pte invalid [17086.238722] v3d fec0.v3d: MMU error from client CLE (4) at 0x1b61000, pte invalid [18643.303188] v3d fec0.v3d: MMU error from client L2T (0) at 0x15bff00, pte invalid [18655.933748] v3d fec0.v3d: MMU error from client L2T (0) at 0x15bff00, pte invalid However, most of the CL/CSD programs are now working happily without kernel warnings and errors. Regards, Sugizaki [1] https://patchwork.kernel.org/patch/11732895/ [2] https://github.com/Idein/py-videocore6 [3] https://github.com/raspberrypi/linux/tree/rpi-5.8.y Yukimasa Sugizaki (3): drm/v3d: Don't resubmit guilty CSD jobs drm/v3d: Correctly restart the timer when progress is made drm/v3d: Add job timeout module param drivers/gpu/drm/v3d/v3d_sched.c | 62 + 1 file changed, 51 insertions(+), 11 deletions(-) -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 56/80] drm/vc4: hdmi: Add a set_timings callback
Similarly to the previous patches, the timings setup in the HDMI controller
of the BCM2711 is slightly different, mostly because it supports higher
resolutions and thus needed more spaces for the various timings, resulting
in the register layout changing.
Let's add a callback for that as well.
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 72 +++
drivers/gpu/drm/vc4/vc4_hdmi.h | 4 ++-
2 files changed, 44 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 532618e02399..9e2bc6cb690e 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -369,12 +369,9 @@ static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
bool enable)
HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
}
-static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
+static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
+struct drm_display_mode *mode)
{
- struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
- struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
- struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
- bool debug_dump_regs = false;
bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
@@ -392,6 +389,41 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
mode->crtc_vsync_end -
interlaced,
VC4_HDMI_VERTB_VBP));
+
+ HDMI_WRITE(HDMI_HORZA,
+ (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
+ (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
+ VC4_SET_FIELD(mode->hdisplay * pixel_rep,
+VC4_HDMI_HORZA_HAP));
+
+ HDMI_WRITE(HDMI_HORZB,
+ VC4_SET_FIELD((mode->htotal -
+ mode->hsync_end) * pixel_rep,
+VC4_HDMI_HORZB_HBP) |
+ VC4_SET_FIELD((mode->hsync_end -
+ mode->hsync_start) * pixel_rep,
+VC4_HDMI_HORZB_HSP) |
+ VC4_SET_FIELD((mode->hsync_start -
+ mode->hdisplay) * pixel_rep,
+VC4_HDMI_HORZB_HFP));
+
+ HDMI_WRITE(HDMI_VERTA0, verta);
+ HDMI_WRITE(HDMI_VERTA1, verta);
+
+ HDMI_WRITE(HDMI_VERTB0, vertb_even);
+ HDMI_WRITE(HDMI_VERTB1, vertb);
+
+ HDMI_WRITE(HDMI_VID_CTL,
+ (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
+ (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
+}
+
+static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
+{
+ struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
+ struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
+ struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
+ bool debug_dump_regs = false;
int ret;
ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev);
@@ -435,33 +467,8 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
- HDMI_WRITE(HDMI_HORZA,
- (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
- (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
- VC4_SET_FIELD(mode->hdisplay * pixel_rep,
-VC4_HDMI_HORZA_HAP));
-
- HDMI_WRITE(HDMI_HORZB,
- VC4_SET_FIELD((mode->htotal -
- mode->hsync_end) * pixel_rep,
-VC4_HDMI_HORZB_HBP) |
- VC4_SET_FIELD((mode->hsync_end -
- mode->hsync_start) * pixel_rep,
-VC4_HDMI_HORZB_HSP) |
- VC4_SET_FIELD((mode->hsync_start -
- mode->hdisplay) * pixel_rep,
-VC4_HDMI_HORZB_HFP));
-
- HDMI_WRITE(HDMI_VERTA0, verta);
- HDMI_WRITE(HDMI_VERTA1, verta);
-
- HDMI_WRITE(HDMI_VERTB0, vertb_even);
- HDMI_WRITE(HDMI_VERTB1, vertb);
-
- HDMI_WRITE(HDMI_VID_CTL,
- (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
- (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
-
+ if (vc4_hdmi->variant->set_timings)
+ vc4_hdmi->variant->set_timings(vc4_hdmi, mode);
if (vc4_encoder->hdmi_monitor &&
drm_default_rgb_quant_range(mode) ==
HDMI_QUANTIZATION_RANGE_LIMITED) {
@@ -1445,6 +1452,7 @@ static const struct v
[PATCH v5 70/80] drm/vc4: hdmi: Remove register dumps in enable
The current code has some logic, disabled by default, to dump the register
setup in the HDMI controller.
However, since we're going to split those functions in multiple, shorter,
functions that only make sense where they are called in sequence, keeping
the register dump makes little sense.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 17 -
1 file changed, 17 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 5e479647559f..3c7862a1dda8 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -430,7 +430,6 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
- bool debug_dump_regs = false;
unsigned long pixel_rate, hsm_rate;
int ret;
@@ -489,14 +488,6 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
if (vc4_hdmi->variant->phy_init)
vc4_hdmi->variant->phy_init(vc4_hdmi, mode);
- if (debug_dump_regs) {
- struct drm_printer p = drm_info_printer(&vc4_hdmi->pdev->dev);
-
- dev_info(&vc4_hdmi->pdev->dev, "HDMI regs before:\n");
- drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
- drm_print_regset32(&p, &vc4_hdmi->hd_regset);
- }
-
HDMI_WRITE(HDMI_VID_CTL, 0);
HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
@@ -522,14 +513,6 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
- if (debug_dump_regs) {
- struct drm_printer p = drm_info_printer(&vc4_hdmi->pdev->dev);
-
- dev_info(&vc4_hdmi->pdev->dev, "HDMI regs after:\n");
- drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
- drm_print_regset32(&p, &vc4_hdmi->hd_regset);
- }
-
HDMI_WRITE(HDMI_VID_CTL,
HDMI_READ(HDMI_VID_CTL) |
VC4_HD_VID_CTL_ENABLE |
--
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[PATCH v5 27/80] drm/vc4: crtc: Move HVS channel init before the PV initialisation
In order to avoid stale pixels getting stuck in an intermediate FIFO between the HVS and the pixelvalve on BCM2711, we need to configure the HVS channel before the pixelvalve is reset and configured. Reviewed-by: Dave Stevenson Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 2c5ff45dc315..b7b0e19e2fe1 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -427,10 +427,6 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc, require_hvs_enabled(dev); - vc4_crtc_config_pv(crtc); - - CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN); - /* Enable vblank irq handling before crtc is started otherwise * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist(). */ @@ -438,6 +434,10 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc, vc4_hvs_atomic_enable(crtc, old_state); + vc4_crtc_config_pv(crtc); + + CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN); + /* When feeding the transposer block the pixelvalve is unneeded and * should not be enabled. */ -- git-series 0.9.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 60/80] drm/vc4: hdmi: Add CEC support flag
Similarly to the audio support, CEC support is not there yet for the
BCM2711, so let's skip entirely the CEC initialization through a variant
flag.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 4
drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index bf537c6d413f..a26b6bd61f74 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1178,6 +1178,9 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
u32 value;
int ret;
+ if (!vc4_hdmi->variant->cec_available)
+ return 0;
+
vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
vc4_hdmi, "vc4",
CEC_CAP_DEFAULTS |
@@ -1476,6 +1479,7 @@ static int vc4_hdmi_dev_remove(struct platform_device
*pdev)
static const struct vc4_hdmi_variant bcm2835_variant = {
.encoder_type = VC4_ENCODER_TYPE_HDMI0,
.debugfs_name = "hdmi_regs",
+ .cec_available = true,
.registers = vc4_hdmi_fields,
.num_registers = ARRAY_SIZE(vc4_hdmi_fields),
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index 794216f3228d..3f07aebe89f1 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -33,6 +33,9 @@ struct vc4_hdmi_variant {
/* Filename to expose the registers in debugfs */
const char *debugfs_name;
+ /* Set to true when the CEC support is available */
+ bool cec_available;
+
/* List of the registers available on that variant */
const struct vc4_hdmi_register *registers;
--
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[PATCH v5 32/80] drm/vc4: hvs: Make the stop_channel function public
During the transition from the firmware to the KMS driver, we need to pay
particular attention to how we deal with the pixelvalves that have already
been enabled, otherwise either timeouts or stuck pixels can occur. We'll
thus need to call the function to stop an HVS channel at boot.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_drv.h | 1 +
drivers/gpu/drm/vc4/vc4_hvs.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 251fcc35530c..554c2e29b23d 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -907,6 +907,7 @@ void vc4_irq_reset(struct drm_device *dev);
/* vc4_hvs.c */
extern struct platform_driver vc4_hvs_driver;
+void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int output);
int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state
*old_state);
void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_crtc_state
*old_state);
diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index 0f56a7b57916..b5ee9556e821 100644
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -248,7 +248,7 @@ static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct
drm_crtc *crtc,
return 0;
}
-static void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int chan)
+void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int chan)
{
struct vc4_dev *vc4 = to_vc4_dev(dev);
--
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[PATCH v5 64/80] drm/vc4: hdmi: Use clk_set_min_rate instead
The HSM clock needs to be running at 101% the pixel clock of the HDMI
controller, however it's shared between the two HDMI controllers, which
means that if the resolutions are different between the two HDMI
controllers, and the lowest resolution is on the second (in enable order)
controller, the first HDMI controller will end up with a smaller than
expected clock rate.
Since we don't really need an exact frequency there, we can simply change
the minimum rate we expect instead.
Reviewed-by: Dave Stevenson
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 84273fe650d6..487c04de6b85 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -462,7 +462,7 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
* pixel clock, but HSM ends up being the limiting factor.
*/
hsm_rate = max_t(unsigned long, 12000, (pixel_rate / 100) * 101);
- ret = clk_set_rate(vc4_hdmi->hsm_clock, hsm_rate);
+ ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
if (ret) {
DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
return;
--
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Re: [PATCH v10 06/17] pwm: lpss: Make pwm_lpss_apply() not rely on existing hardware state
On Thu, Sep 03, 2020 at 01:23:26PM +0200, Hans de Goede wrote:
> Before this commit pwm_lpss_apply() was assuming 2 pre-conditions
> were met by the existing hardware state:
>
> 1. That the base-unit and on-time-div read back from the
> control register are those actually in use, so that it
> can skip setting the update bit if the read-back value
> matches the desired values.
>
> 2. That the controller is enabled when the cached
> pwm_state.enabled says that the controller is enabled.
>
> As the long history of fixes for subtle (often suspend/resume)
> lpss-pwm issues shows, these assumptions are not necessary
> always true.
>
> 1. Specifically is not true on some (*) Cherry Trail devices
> with a nasty GFX0._PS3 method which: a. saves the ctrl reg value.
> b. sets the base-unit to 0 and writes the update bit to apply/commit
> c. restores the original ctrl value without setting the update bit,
> so that the 0 base-unit value is still in use.
>
> 2. Assumption 2. currently is true, but only because of the code which
> saves/restores the state on suspend/resume. By convention restoring the
> PWM state should be done by the PWM consumer and the presence of this
> code in the pmw-lpss driver is a bug. Therefor the save/restore code will
> be dropped in the next patch in this series, after which this assumption
> also is no longer true.
>
> This commit changes the pwm_lpss_apply() to not make any assumptions about
> the state the hardware is in. Instead it makes pwm_lpss_apply() always
> fully program the PWM controller, making it much less fragile.
>
> *) Seen on the Acer One 10 S1003, Lenovo Ideapad Miix 310 and 320 models
> and various Medion models.
Good one!
Reviewed-by: Andy Shevchenko
> Acked-by: Thierry Reding
> Signed-off-by: Hans de Goede
> ---
> Changes in v10:
> - Fixup some wording / mistakes in the commit message
>
> Changes in v9:
> - This is a new patch in v9 of this series
> ---
> drivers/pwm/pwm-lpss.c | 21 +
> 1 file changed, 9 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c
> index 8a136ba2a583..9c5c7217c9b6 100644
> --- a/drivers/pwm/pwm-lpss.c
> +++ b/drivers/pwm/pwm-lpss.c
> @@ -85,7 +85,7 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm,
> struct pwm_device *pwm,
> unsigned long long on_time_div;
> unsigned long c = lpwm->info->clk_rate, base_unit_range;
> unsigned long long base_unit, freq = NSEC_PER_SEC;
> - u32 orig_ctrl, ctrl;
> + u32 ctrl;
>
> do_div(freq, period_ns);
>
> @@ -104,16 +104,14 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip
> *lpwm, struct pwm_device *pwm,
> do_div(on_time_div, period_ns);
> on_time_div = 255ULL - on_time_div;
>
> - orig_ctrl = ctrl = pwm_lpss_read(pwm);
> + ctrl = pwm_lpss_read(pwm);
> ctrl &= ~PWM_ON_TIME_DIV_MASK;
> ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);
> ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
> ctrl |= on_time_div;
>
> - if (orig_ctrl != ctrl) {
> - pwm_lpss_write(pwm, ctrl);
> - pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE);
> - }
> + pwm_lpss_write(pwm, ctrl);
> + pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE);
> }
>
> static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
> @@ -124,8 +122,7 @@ static inline void pwm_lpss_cond_enable(struct pwm_device
> *pwm, bool cond)
>
> static int pwm_lpss_prepare_enable(struct pwm_lpss_chip *lpwm,
> struct pwm_device *pwm,
> -const struct pwm_state *state,
> -bool enable)
> +const struct pwm_state *state)
> {
> int ret;
>
> @@ -134,12 +131,12 @@ static int pwm_lpss_prepare_enable(struct pwm_lpss_chip
> *lpwm,
> return ret;
>
> pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
> - pwm_lpss_cond_enable(pwm, enable && lpwm->info->bypass == false);
> + pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
> ret = pwm_lpss_wait_for_update(pwm);
> if (ret)
> return ret;
>
> - pwm_lpss_cond_enable(pwm, enable && lpwm->info->bypass == true);
> + pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
> return 0;
> }
>
> @@ -152,11 +149,11 @@ static int pwm_lpss_apply(struct pwm_chip *chip, struct
> pwm_device *pwm,
> if (state->enabled) {
> if (!pwm_is_enabled(pwm)) {
> pm_runtime_get_sync(chip->dev);
> - ret = pwm_lpss_prepare_enable(lpwm, pwm, state, true);
> + ret = pwm_lpss_prepare_enable(lpwm, pwm, state);
> if (ret)
> pm_runtime_put(chip->dev);
> } else {
> - ret = pwm_lpss_prepare_enable(lpwm, pwm, state, false);
> + ret = pwm_lpss_p
[PATCH v5 67/80] drm/vc4: hdmi: Set the b-frame marker to the match ALSA's default.
From: Dave Stevenson ALSA's iec958 plugin by default sets the block start preamble to 8, whilst this driver was programming the hardware to expect 0xF. Amend the hardware config to match ALSA. Tested-by: Chanwoo Choi Tested-by: Hoegeun Kwon Tested-by: Stefan Wahren Signed-off-by: Dave Stevenson Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index 43e59466b1d8..d8137b838326 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -754,10 +754,11 @@ static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream, vc4_hdmi_audio_set_mai_clock(vc4_hdmi); + /* The B frame identifier should match the value used by alsa-lib (8) */ audio_packet_config = VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | - VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); + VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0); audio_packet_config |= VC4_SET_FIELD(channel_mask, -- git-series 0.9.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 66/80] drm/vc4: hdmi: Reset audio infoframe on encoder_enable if previously streaming
From: Dave Stevenson
If the encoder is disabled and re-enabled (eg mode change) all infoframes
are reset, whilst the audio subsystem know nothing about this change.
The driver therefore needs to reinstate the audio infoframe for
itself.
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 12
drivers/gpu/drm/vc4/vc4_hdmi.h | 2 ++
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 53c3b5ae1179..43e59466b1d8 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -308,8 +308,16 @@ static void vc4_hdmi_set_audio_infoframe(struct
drm_encoder *encoder)
static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
{
+ struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
+
vc4_hdmi_set_avi_infoframe(encoder);
vc4_hdmi_set_spd_infoframe(encoder);
+ /*
+* If audio was streaming, then we need to reenabled the audio
+* infoframe here during encoder_enable.
+*/
+ if (vc4_hdmi->audio.streaming)
+ vc4_hdmi_set_audio_infoframe(encoder);
}
static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
@@ -694,6 +702,7 @@ static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
struct device *dev = &vc4_hdmi->pdev->dev;
int ret;
+ vc4_hdmi->audio.streaming = false;
ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO);
if (ret)
dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
@@ -797,6 +806,7 @@ static int vc4_hdmi_audio_trigger(struct snd_pcm_substream
*substream, int cmd,
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
vc4_hdmi_set_audio_infoframe(encoder);
+ vc4_hdmi->audio.streaming = true;
if (vc4_hdmi->variant->phy_rng_enable)
vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
@@ -815,6 +825,8 @@ static int vc4_hdmi_audio_trigger(struct snd_pcm_substream
*substream, int cmd,
if (vc4_hdmi->variant->phy_rng_disable)
vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
+ vc4_hdmi->audio.streaming = false;
+
break;
default:
break;
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index 342f6e0227a2..77d47d1707ce 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -85,6 +85,8 @@ struct vc4_hdmi_audio {
int channels;
struct snd_dmaengine_dai_dma_data dma_data;
struct snd_pcm_substream *substream;
+
+ bool streaming;
};
/* General HDMI hardware state. */
--
git-series 0.9.1
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[PATCH] drm/bridge: add it6505 driver
This adds support for the iTE IT6505. This device can convert DPI signal to DP output. From: Allen Chen Signed-off-by: Jitao Shi Signed-off-by: Pi-Hsun Shih Signed-off-by: Yilun Lin Signed-off-by: Hermes Wu Signed-off-by: Allen Chen --- drivers/gpu/drm/bridge/Kconfig |7 + drivers/gpu/drm/bridge/Makefile |1 + drivers/gpu/drm/bridge/ite-it6505.c | 3336 +++ 3 files changed, 3344 insertions(+) create mode 100644 drivers/gpu/drm/bridge/ite-it6505.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 3e11af4e9f63e..f21dce3fabeb9 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -61,6 +61,13 @@ config DRM_LONTIUM_LT9611 HDMI signals Please say Y if you have such hardware. +config DRM_ITE_IT6505 + tristate "ITE IT6505 DisplayPort bridge" + depends on OF + select DRM_KMS_HELPER + help + ITE IT6505 DisplayPort bridge chip driver. + config DRM_LVDS_CODEC tristate "Transparent LVDS encoders and decoders support" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index c589a6a7cbe1d..8a118fd901ad7 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o +obj-$(CONFIG_DRM_ITE_IT6505) += ite-it6505.o obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) += megachips-stdp-ge-b850v3-fw.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c new file mode 100644 index 0..a72e524eb20b1 --- /dev/null +++ b/drivers/gpu/drm/bridge/ite-it6505.c @@ -0,0 +1,3336 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define REG_IC_VER 0x04 + +#define REG_RESET_CTRL 0x05 +#define VIDEO_RESET BIT(0) +#define AUDIO_RESET BIT(1) +#define ALL_LOGIC_RESET BIT(2) +#define AUX_RESET BIT(3) +#define HDCP_RESET BIT(4) + +#define INT_STATUS_01 0x06 +#define INT_MASK_01 0x09 +#define INT_HPD_CHANGE BIT(0) +#define INT_RECEIVE_HPD_IRQ BIT(1) +#define INT_SCDT_CHANGE BIT(2) +#define INT_HDCP_FAIL BIT(3) +#define INT_HDCP_DONE BIT(4) + +#define INT_STATUS_02 0x07 +#define INT_MASK_02 0x0A +#define INT_AUX_CMD_FAIL BIT(0) +#define INT_HDCP_KSV_CHECK BIT(1) +#define INT_AUDIO_FIFO_ERROR BIT(2) + +#define INT_STATUS_03 0x08 +#define INT_MASK_03 0x0B +#define INT_LINK_TRAIN_FAIL BIT(4) +#define INT_VID_FIFO_ERROR BIT(5) +#define INT_IO_LATCH_FIFO_OVERFLOW BIT(7) + +#define REG_SYSTEM_STS 0x0D +#define INT_STS BIT(0) +#define HPD_STS BIT(1) +#define VIDEO_STB BIT(2) + +#define REG_LINK_TRAIN_STS 0x0E +#define LINK_STATE_CR BIT(2) +#define LINK_STATE_EQ BIT(3) +#define LINK_STATE_NORP BIT(4) + +#define REG_BANK_SEL 0x0F +#define REG_CLK_CTRL0 0x10 +#define M_PCLK_DELAY 0x03 + +#define REG_AUX_OPT 0x11 +#define AUX_AUTO_RST BIT(0) +#define AUX_FIX_FREQ BIT(3) + +#define REG_DATA_CTRL0 0x12 +#define VIDEO_LATCH_EDGE BIT(4) +#define ENABLE_PCLK_COUNTER BIT(7) + +#define REG_PCLK_COUNTER_VALUE 0x13 + +#define REG_501_FIFO_CTRL 0x15 +#define RST_501_FIFO BIT(1) + +#define REG_TRAIN_CTRL0 0x16 +#define FORCE_LBR BIT(0) +#define LANE_COUNT_MASK 0x06 +#define LANE_SWAP BIT(3) +#define SPREAD_AMP_5 BIT(4) +#define FORCE_CR_DONE BIT(5) +#define FORCE_EQ_DONE BIT(6) + +#define REG_TRAIN_CTRL1 0x17 +#define AUTO_TRAIN BIT(0) +#define MANUAL_TRAIN BIT(1) +#define FORCE_RETRAIN BIT(2) + +#define REG_AUX_CTRL 0x23 +#define CLR_EDID_FIFO BIT(0) +#define AUX_USER_MODE BIT(1) +#define AUX_NO_SEGMENT_WR BIT(6) +#define AUX_EN_FIFO_READ BIT(7) + +#define REG_AUX_ADR_0_7 0x24 +#define REG_AUX_ADR_8_15 0x25 +#define REG_AUX_ADR_16_19 0x26 +#define REG_AUX_OUT_DATA0 0x27 + +#define REG_AUX_CMD_REQ 0x2B +#define AUX_BUSY BIT(5) + +#define REG_AUX_DATA_0_7 0x2C +#define REG_AUX_DATA_8_15 0x2D +#define REG_AUX_DATA_16_23 0x2E +#define REG_AUX_DATA_24_31 0x2F + +#define REG_AUX_DATA_FIFO 0x2F + +#define REG_AUX_ERROR_STS 0x9F +#define M_AUX_REQ_FAIL 0x03 + +#define REG_HDCP_CTRL1 0x38 +#define HDCP_CP_ENABLE BIT(0) + +#define REG_HDCP_TRIGGER 0x39 +#define HDCP_TRIGGER_START BIT(0) +#define HDCP_TRIGGER_CPIRQ BIT(1) +#define HDCP_TRIGGER_KSV_DONE BIT(4) +#define HDCP_TRIGGER_KSV_FAIL BIT(5) + +#define REG_HDCP_CTRL2 0x3A +#define HDCP_AN_SEL BIT(0) +#define HDCP_AN_
[PATCH 3/3] drm/v3d: Add job timeout module param
From: Yukimasa Sugizaki
The default timeout is 500 ms which is too short for some workloads
including Piglit. Adding this parameter will help users to run heavier
tasks.
Signed-off-by: Yukimasa Sugizaki
---
drivers/gpu/drm/v3d/v3d_sched.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/v3d/v3d_sched.c b/drivers/gpu/drm/v3d/v3d_sched.c
index feef0c749e68..983efb018560 100644
--- a/drivers/gpu/drm/v3d/v3d_sched.c
+++ b/drivers/gpu/drm/v3d/v3d_sched.c
@@ -19,11 +19,17 @@
*/
#include
+#include
#include "v3d_drv.h"
#include "v3d_regs.h"
#include "v3d_trace.h"
+static uint timeout = 500;
+module_param(timeout, uint, 0444);
+MODULE_PARM_DESC(timeout,
+ "Timeout for a job in ms (0 means infinity and default is 500 ms)");
+
static struct v3d_job *
to_v3d_job(struct drm_sched_job *sched_job)
{
@@ -432,13 +438,13 @@ v3d_sched_init(struct v3d_dev *v3d)
{
int hw_jobs_limit = 1;
int job_hang_limit = 0;
- int hang_limit_ms = 500;
+ long timeout_jiffies = timeout ?
+ msecs_to_jiffies(timeout) : MAX_SCHEDULE_TIMEOUT;
int ret;
ret = drm_sched_init(&v3d->queue[V3D_BIN].sched,
&v3d_bin_sched_ops,
-hw_jobs_limit, job_hang_limit,
-msecs_to_jiffies(hang_limit_ms),
+hw_jobs_limit, job_hang_limit, timeout_jiffies,
"v3d_bin");
if (ret) {
dev_err(v3d->drm.dev, "Failed to create bin scheduler: %d.",
ret);
@@ -447,8 +453,7 @@ v3d_sched_init(struct v3d_dev *v3d)
ret = drm_sched_init(&v3d->queue[V3D_RENDER].sched,
&v3d_render_sched_ops,
-hw_jobs_limit, job_hang_limit,
-msecs_to_jiffies(hang_limit_ms),
+hw_jobs_limit, job_hang_limit, timeout_jiffies,
"v3d_render");
if (ret) {
dev_err(v3d->drm.dev, "Failed to create render scheduler: %d.",
@@ -459,8 +464,7 @@ v3d_sched_init(struct v3d_dev *v3d)
ret = drm_sched_init(&v3d->queue[V3D_TFU].sched,
&v3d_tfu_sched_ops,
-hw_jobs_limit, job_hang_limit,
-msecs_to_jiffies(hang_limit_ms),
+hw_jobs_limit, job_hang_limit, timeout_jiffies,
"v3d_tfu");
if (ret) {
dev_err(v3d->drm.dev, "Failed to create TFU scheduler: %d.",
@@ -472,8 +476,7 @@ v3d_sched_init(struct v3d_dev *v3d)
if (v3d_has_csd(v3d)) {
ret = drm_sched_init(&v3d->queue[V3D_CSD].sched,
&v3d_csd_sched_ops,
-hw_jobs_limit, job_hang_limit,
-msecs_to_jiffies(hang_limit_ms),
+hw_jobs_limit, job_hang_limit,
timeout_jiffies,
"v3d_csd");
if (ret) {
dev_err(v3d->drm.dev, "Failed to create CSD scheduler:
%d.",
@@ -484,8 +487,7 @@ v3d_sched_init(struct v3d_dev *v3d)
ret = drm_sched_init(&v3d->queue[V3D_CACHE_CLEAN].sched,
&v3d_cache_clean_sched_ops,
-hw_jobs_limit, job_hang_limit,
-msecs_to_jiffies(hang_limit_ms),
+hw_jobs_limit, job_hang_limit,
timeout_jiffies,
"v3d_cache_clean");
if (ret) {
dev_err(v3d->drm.dev, "Failed to create CACHE_CLEAN
scheduler: %d.",
--
2.7.4
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[PATCH v5 42/80] drm/vc4: hdmi: Rename hdmi to vc4_hdmi
The driver isn't consistent with the name given to the vc4_hdmi
structure pointer in its functions. Make sure to use a consistent name.
Reviewed-by: Eric Anholt
Tested-by: Chanwoo Choi
Tested-by: Hoegeun Kwon
Tested-by: Stefan Wahren
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 283 +-
1 file changed, 142 insertions(+), 141 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 1f350b068fcd..6733e4bc235b 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -109,11 +109,11 @@ static const struct debugfs_reg32 hd_regs[] = {
static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
{
struct drm_info_node *node = (struct drm_info_node *)m->private;
- struct vc4_hdmi *hdmi = node->info_ent->data;
+ struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
struct drm_printer p = drm_seq_file_printer(m);
- drm_print_regset32(&p, &hdmi->hdmi_regset);
- drm_print_regset32(&p, &hdmi->hd_regset);
+ drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
+ drm_print_regset32(&p, &vc4_hdmi->hd_regset);
return 0;
}
@@ -291,8 +291,8 @@ static void vc4_hdmi_set_avi_infoframe(struct drm_encoder
*encoder)
{
struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
struct vc4_dev *vc4 = encoder->dev->dev_private;
- struct vc4_hdmi *hdmi = vc4->hdmi;
- struct drm_connector *connector = &hdmi->connector.base;
+ struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
+ struct drm_connector *connector = &vc4_hdmi->connector.base;
struct drm_connector_state *cstate = connector->state;
struct drm_crtc *crtc = encoder->crtc;
const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
@@ -337,7 +337,7 @@ static void vc4_hdmi_set_audio_infoframe(struct drm_encoder
*encoder)
{
struct drm_device *drm = encoder->dev;
struct vc4_dev *vc4 = drm->dev_private;
- struct vc4_hdmi *hdmi = vc4->hdmi;
+ struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
union hdmi_infoframe frame;
int ret;
@@ -346,7 +346,7 @@ static void vc4_hdmi_set_audio_infoframe(struct drm_encoder
*encoder)
frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
- frame.audio.channels = hdmi->audio.channels;
+ frame.audio.channels = vc4_hdmi->audio.channels;
vc4_hdmi_write_infoframe(encoder, &frame);
}
@@ -361,7 +361,7 @@ static void vc4_hdmi_encoder_disable(struct drm_encoder
*encoder)
{
struct drm_device *dev = encoder->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
- struct vc4_hdmi *hdmi = vc4->hdmi;
+ struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
int ret;
HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0);
@@ -370,9 +370,9 @@ static void vc4_hdmi_encoder_disable(struct drm_encoder
*encoder)
HD_WRITE(VC4_HD_VID_CTL,
HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
- clk_disable_unprepare(hdmi->pixel_clock);
+ clk_disable_unprepare(vc4_hdmi->pixel_clock);
- ret = pm_runtime_put(&hdmi->pdev->dev);
+ ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
if (ret < 0)
DRM_ERROR("Failed to release power domain: %d\n", ret);
}
@@ -383,7 +383,7 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
struct drm_device *dev = encoder->dev;
struct vc4_dev *vc4 = to_vc4_dev(dev);
- struct vc4_hdmi *hdmi = vc4->hdmi;
+ struct vc4_hdmi *vc4_hdmi = vc4->hdmi;
bool debug_dump_regs = false;
bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
@@ -405,13 +405,13 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
u32 csc_ctl;
int ret;
- ret = pm_runtime_get_sync(&hdmi->pdev->dev);
+ ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev);
if (ret < 0) {
DRM_ERROR("Failed to retain power domain: %d\n", ret);
return;
}
- ret = clk_set_rate(hdmi->pixel_clock,
+ ret = clk_set_rate(vc4_hdmi->pixel_clock,
mode->clock * 1000 *
((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1));
if (ret) {
@@ -419,7 +419,7 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
return;
}
- ret = clk_prepare_enable(hdmi->pixel_clock);
+ ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
if (ret) {
DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
return;
@@ -439,11 +439,11 @@ static void vc4_hdmi_encoder_enable(stru
[PATCH] drm: xlnx: fix build warning & errors when DMADEVICES is not set
From: Randy Dunlap Fix kconfig warnings & build errors caused by DRM_ZYNQMP_DPSUB. Any driver that selects DMA_ENGINE should make sure that DMADEVICES is already enabled. As is, this causes build errors in many other drivers. See https://lore.kernel.org/lkml/202009020239.ouph82xc%25...@intel.com/ for the numerous build errors. WARNING: unmet direct dependencies detected for DMA_ENGINE Depends on [n]: DMADEVICES [=n] Selected by [y]: - DRM_ZYNQMP_DPSUB [=y] && HAS_IOMEM [=y] && (ARCH_ZYNQMP || COMPILE_TEST [=y]) && COMMON_CLK [=y] && DRM [=y] && OF [=y] Reported-by: kernel test robot Signed-off-by: Randy Dunlap Cc: Hyun Kwon Cc: Laurent Pinchart Cc: dri-devel@lists.freedesktop.org --- drivers/gpu/drm/xlnx/Kconfig |1 + 1 file changed, 1 insertion(+) --- linux-next-20200903.orig/drivers/gpu/drm/xlnx/Kconfig +++ linux-next-20200903/drivers/gpu/drm/xlnx/Kconfig @@ -2,6 +2,7 @@ config DRM_ZYNQMP_DPSUB tristate "ZynqMP DisplayPort Controller Driver" depends on ARCH_ZYNQMP || COMPILE_TEST depends on COMMON_CLK && DRM && OF + depends on DMADEVICES select DMA_ENGINE select DRM_GEM_CMA_HELPER select DRM_KMS_CMA_HELPER ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/exynos: Drop local dma_parms
Hi Robin,
On 03.09.2020 22:51, Robin Murphy wrote:
> Since commit 9495b7e92f71 ("driver core: platform: Initialize dma_parms
> for platform devices"), struct platform_device already provides a
> dma_parms structure, so we can save allocating another one.
>
> Also the DMA segment size is simply a size, not a bitmask.
>
> Signed-off-by: Robin Murphy
I've sent a similar patch over 2 months ago, but it looks it got lost:
https://lore.kernel.org/dri-devel/20200707110827.3760-1-m.szyprow...@samsung.com/
Inki, could You queue it for merge?
> ---
> drivers/gpu/drm/exynos/exynos_drm_dma.c | 26 +
> 1 file changed, 1 insertion(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_dma.c
> b/drivers/gpu/drm/exynos/exynos_drm_dma.c
> index 58b89ec11b0e..9f25a5ebbf7d 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_dma.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_dma.c
> @@ -31,23 +31,6 @@
> #define EXYNOS_DEV_ADDR_START 0x2000
> #define EXYNOS_DEV_ADDR_SIZE0x4000
>
> -static inline int configure_dma_max_seg_size(struct device *dev)
> -{
> - if (!dev->dma_parms)
> - dev->dma_parms = kzalloc(sizeof(*dev->dma_parms), GFP_KERNEL);
> - if (!dev->dma_parms)
> - return -ENOMEM;
> -
> - dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
> - return 0;
> -}
> -
> -static inline void clear_dma_max_seg_size(struct device *dev)
> -{
> - kfree(dev->dma_parms);
> - dev->dma_parms = NULL;
> -}
> -
> /*
>* drm_iommu_attach_device- attach device to iommu mapping
>*
> @@ -69,9 +52,7 @@ static int drm_iommu_attach_device(struct drm_device
> *drm_dev,
> return -EINVAL;
> }
>
> - ret = configure_dma_max_seg_size(subdrv_dev);
> - if (ret)
> - return ret;
> + dma_set_max_seg_size(subdrv_dev, UINT_MAX);
>
> if (IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)) {
> /*
> @@ -89,9 +70,6 @@ static int drm_iommu_attach_device(struct drm_device
> *drm_dev,
> ret = iommu_attach_device(priv->mapping, subdrv_dev);
> }
>
> - if (ret)
> - clear_dma_max_seg_size(subdrv_dev);
> -
> return ret;
> }
>
> @@ -114,8 +92,6 @@ static void drm_iommu_detach_device(struct drm_device
> *drm_dev,
> arm_iommu_attach_device(subdrv_dev, *dma_priv);
> } else if (IS_ENABLED(CONFIG_IOMMU_DMA))
> iommu_detach_device(priv->mapping, subdrv_dev);
> -
> - clear_dma_max_seg_size(subdrv_dev);
> }
>
> int exynos_drm_register_dma(struct drm_device *drm, struct device *dev,
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
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Re: [bug report] drm/panel: Add panel driver for the Mantix MLAF057WE51-X DSI panel
Hi,
On Mon, Aug 31, 2020 at 02:29:24PM +0300, Dan Carpenter wrote:
> Hello Guido Günther,
>
> The patch 72967d5616d3: "drm/panel: Add panel driver for the Mantix
> MLAF057WE51-X DSI panel" from Aug 17, 2020, leads to the following
> static checker warning:
>
> drivers/gpu/drm/panel/panel-mantix-mlaf057we51.c:205 mantix_get_modes()
> error: we previously assumed 'mode' could be null (see line 204)
>
> drivers/gpu/drm/panel/panel-mantix-mlaf057we51.c
>197 static int mantix_get_modes(struct drm_panel *panel,
>198 struct drm_connector *connector)
>199 {
>200 struct mantix *ctx = panel_to_mantix(panel);
>201 struct drm_display_mode *mode;
>202
>203 mode = drm_mode_duplicate(connector->dev, &default_mode);
>204 if (!mode) {
>205 dev_err(ctx->dev, "Failed to add mode %ux%u@%u\n",
>206 default_mode.hdisplay, default_mode.vdisplay,
>207 drm_mode_vrefresh(mode));
>
> This will lead to a NULL dereference.
Thanks, i'll fold a fix for this into some other upcoming changes to
this driver.
Cheers,
-- Guido
>
>208 return -ENOMEM;
>209 }
>210
>211 drm_mode_set_name(mode);
>212
>213 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
>214 connector->display_info.width_mm = mode->width_mm;
>215 connector->display_info.height_mm = mode->height_mm;
>216 drm_mode_probed_add(connector, mode);
>217
>218 return 1;
>219 }
>
> regards,
> dan carpenter
>
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[PATCH 1/3] drm/v3d: Don't resubmit guilty CSD jobs
The previous code misses a check for the timeout error set by
drm_sched_resubmit_jobs(), which results in an infinite GPU reset loop
if once a timeout occurs:
[ 178.799106] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* Resetting GPU
for hang.
[ 178.807836] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* V3D_ERR_STAT:
0x1000
[ 179.839132] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* Resetting GPU
for hang.
[ 179.847865] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* V3D_ERR_STAT:
0x1000
[ 180.879146] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* Resetting GPU
for hang.
[ 180.887925] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* V3D_ERR_STAT:
0x1000
[ 181.919188] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* Resetting GPU
for hang.
[ 181.928002] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* V3D_ERR_STAT:
0x1000
...
This commit adds the check for timeout as in v3d_{bin,render}_job_run():
[ 66.408962] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* Resetting GPU
for hang.
[ 66.417734] v3d fec0.v3d: [drm:v3d_reset [v3d]] *ERROR* V3D_ERR_STAT:
0x1000
[ 66.428296] [drm] Skipping CSD job resubmission due to previous error (-125)
, where -125 is -ECANCELED, though users currently have no way other
than inspecting the dmesg to check if the timeout has occurred.
Signed-off-by: Yukimasa Sugizaki
---
drivers/gpu/drm/v3d/v3d_sched.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/v3d/v3d_sched.c b/drivers/gpu/drm/v3d/v3d_sched.c
index 0747614a78f0..001216f22017 100644
--- a/drivers/gpu/drm/v3d/v3d_sched.c
+++ b/drivers/gpu/drm/v3d/v3d_sched.c
@@ -226,6 +226,17 @@ v3d_csd_job_run(struct drm_sched_job *sched_job)
struct dma_fence *fence;
int i;
+ /* This error is set to -ECANCELED by drm_sched_resubmit_jobs() if this
+* job timed out more than sched_job->sched->hang_limit times.
+*/
+ int error = sched_job->s_fence->finished.error;
+
+ if (unlikely(error < 0)) {
+ DRM_WARN("Skipping CSD job resubmission due to previous error
(%d)\n",
+error);
+ return ERR_PTR(error);
+ }
+
v3d->csd_job = job;
v3d_invalidate_caches(v3d);
--
2.7.4
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