[PATCH] drm/virtio: fix error check
The >= compare op must happen in cpu byte order, doing it in
little endian fails on big endian machines like s390.
Reported-by: Sebastian Mitterle
Signed-off-by: Gerd Hoffmann
---
drivers/gpu/drm/virtio/virtgpu_vq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/virtio/virtgpu_vq.c
b/drivers/gpu/drm/virtio/virtgpu_vq.c
index cfe9c54f87a3..67caecde623e 100644
--- a/drivers/gpu/drm/virtio/virtgpu_vq.c
+++ b/drivers/gpu/drm/virtio/virtgpu_vq.c
@@ -222,7 +222,7 @@ void virtio_gpu_dequeue_ctrl_func(struct work_struct *work)
trace_virtio_gpu_cmd_response(vgdev->ctrlq.vq, resp);
if (resp->type != cpu_to_le32(VIRTIO_GPU_RESP_OK_NODATA)) {
- if (resp->type >=
cpu_to_le32(VIRTIO_GPU_RESP_ERR_UNSPEC)) {
+ if (le32_to_cpu(resp->type) >=
VIRTIO_GPU_RESP_ERR_UNSPEC) {
struct virtio_gpu_ctrl_hdr *cmd;
cmd = virtio_gpu_vbuf_ctrl_hdr(entry);
DRM_ERROR_RATELIMITED("response 0x%x (command
0x%x)\n",
--
2.18.2
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[RFC PATCH 2/6] drm/radeon: don't use ttm bo->offset
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/radeon/radeon.h| 1 +
drivers/gpu/drm/radeon/radeon_object.h | 16 +++-
drivers/gpu/drm/radeon/radeon_ttm.c| 4 +---
3 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index d59b004f6695..97cfcc2870af 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -2823,6 +2823,7 @@ extern void radeon_ttm_set_active_vram_size(struct
radeon_device *rdev, u64 size
extern void radeon_program_register_sequence(struct radeon_device *rdev,
const u32 *registers,
const u32 array_size);
+struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev);
/*
* vm
diff --git a/drivers/gpu/drm/radeon/radeon_object.h
b/drivers/gpu/drm/radeon/radeon_object.h
index d23f2ed4126e..4d37571c7ff5 100644
--- a/drivers/gpu/drm/radeon/radeon_object.h
+++ b/drivers/gpu/drm/radeon/radeon_object.h
@@ -90,7 +90,21 @@ static inline void radeon_bo_unreserve(struct radeon_bo *bo)
*/
static inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo)
{
- return bo->tbo.offset;
+ struct radeon_device *rdev;
+ u64 start = 0;
+
+ rdev = radeon_get_rdev(bo->tbo.bdev);
+
+ switch(bo->tbo.mem.mem_type) {
+ case TTM_PL_TT:
+ start = rdev->mc.gtt_start;
+ break;
+ case TTM_PL_VRAM:
+ start = rdev->mc.vram_start;
+ break;
+ }
+
+ return (bo->tbo.mem.start << PAGE_SHIFT) + start;
}
static inline unsigned long radeon_bo_size(struct radeon_bo *bo)
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c
b/drivers/gpu/drm/radeon/radeon_ttm.c
index 098bc9f40b98..b10654494262 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -56,7 +56,7 @@
static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
-static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
+struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
{
struct radeon_mman *mman;
struct radeon_device *rdev;
@@ -87,7 +87,6 @@ static int radeon_init_mem_type(struct ttm_bo_device *bdev,
uint32_t type,
break;
case TTM_PL_TT:
man->func = &ttm_bo_manager_func;
- man->gpu_offset = rdev->mc.gtt_start;
man->available_caching = TTM_PL_MASK_CACHING;
man->default_caching = TTM_PL_FLAG_CACHED;
man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
@@ -109,7 +108,6 @@ static int radeon_init_mem_type(struct ttm_bo_device *bdev,
uint32_t type,
case TTM_PL_VRAM:
/* "On-card" video ram */
man->func = &ttm_bo_manager_func;
- man->gpu_offset = rdev->mc.vram_start;
man->flags = TTM_MEMTYPE_FLAG_FIXED |
TTM_MEMTYPE_FLAG_MAPPABLE;
man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
--
2.25.0
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Re: [PATCH 1/1] Support LVDS output on Allwinner A20
On Thu, Feb 13, 2020 at 12:46:53AM +0200, Andrey Lebedev wrote: > On Wed, Feb 12, 2020 at 01:53:45PM +0100, Maxime Ripard wrote: > > > > Side question, this will need some DT changes too, right? > > > > > > Hm, I agree. I think it would be reasonable to include LVDS0/1 pins > > > > That, but most importantly, the reset and clocks for the LVDS > > block. Also from looking at it, I'm not entirely sure that the TCON1 > > has a LVDS output > > I also have impression that LVDS is only supported on TCON0, but that's > mostly from this comment in sun4i_lvds.c: > > /* The LVDS encoder can only work with the TCON channel 0 */ No, that's a separate thing. Internally the TCON has two channels, one connected to panels type of display (LVDS, Parallel, etc), the second one connected to TV outputs (HDMI, composite). But then, on some SoCs like the A20, you have two TCON's too. As far as I could see, only the first TCON can use LVDS, but I'm not definitive. Allwinner seems to allow panels to only be tied to TCON0 in the BSP, so I guess we can assume that. > > do you have a board when you have been able to test it? > > Yes, I have the hardware (Cubieboard 2) at hand, but I cannot change the > any physical connections on it. FWIW, it is https://openvario.org, the > device we are (painfully) trying to upgrade from old kernel-3.4 with > proprietary mali drivers to contemporary software. What painpoints do you have? > > > and sample (but disabled) lvds panel, > > > > That's good for the sake of the example, but it shouldn't be in the > > same patch, it won't be merged. > > I jave just submitted version 2 of the patches - set of 2 patches this > time. Addressed your comments, please take a look. I will, thanks! Maxime signature.asc Description: PGP signature ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 2/2] ARM: sun7i: dts: Add LVDS panel support on A20
On Thu, Feb 13, 2020 at 10:43:04AM +0100, Maxime Ripard wrote:
> On Thu, Feb 13, 2020 at 12:23:57AM +0200, andrey.lebe...@gmail.com wrote:
> > From: Andrey Lebedev
> >
> > Define pins for LVDS channels 0 and 1, configure reset line for tcon0 and
> > provide sample LVDS panel, connected to tcon0.
> >
> > Signed-off-by: Andrey Lebedev
>
> And this prefix should be ARM: dts: sun7i ;)
Ah, thanks, I think I've got the pattern now!
> > + /omit-if-no-ref/
> > + lcd_lvds0_pins: lcd_lvds0_pins {
>
> underscores in the node names will create a dtc warning at
> compilation, you should use lcd-lvds0-pins instead.
You're right, I wasn't following the naming convention here. dtc doesn't
produce any warning on this though. Fixed that anyway.
> This will create a spurious warning message for TCON1, since we
> adjusted the driver to tell it supports LVDS, but there's no LVDS
> reset line, so we need to make it finer grained.
Yes, I can attribute two of the messages in my dmesg log [1] to this
("Missing LVDS properties" and "LVDS output disabled". "sun4i-tcon
1c0d000.lcd-controller" is indeed tcon1). And yes, I can see how they
can be confusing to someone.
I'd need some pointers on how to deal with that though (if we want to do
it in this scope).
[1] excerpt from kernel boot log:
[4.890975] sun4i-drm display-engine: bound 1e0.display-frontend (ops
sun4i_frontend_driver_exit [sun4i_frontend])
[4.902032] sun4i-drm display-engine: bound 1e2.display-frontend (ops
sun4i_frontend_driver_exit [sun4i_frontend])
[4.913467] sun4i-drm display-engine: bound 1e6.display-backend (ops
sun4i_backend_ops [sun4i_backend])
[4.923806] sun4i-drm display-engine: bound 1e4.display-backend (ops
sun4i_backend_ops [sun4i_backend])
[4.934451] sun4i-drm display-engine: bound 1c0c000.lcd-controller (ops
sun4i_tcon_platform_driver_exit [sun4i_tcon])
[4.945254] sun4i-tcon 1c0d000.lcd-controller: Missing LVDS properties,
Please upgrade your DT
[4.953935] sun4i-tcon 1c0d000.lcd-controller: LVDS output disabled
[4.960857] sun4i-drm display-engine: No panel or bridge found... RGB output
disabled
[4.968845] sun4i-drm display-engine: bound 1c0d000.lcd-controller (ops
sun4i_tcon_platform_driver_exit [sun4i_tcon])
[5.080874] sun4i-drm display-engine: bound 1c16000.hdmi (ops
sun4i_hdmi_driver_exit [sun4i_drm_hdmi])
[5.110087] [drm] Initialized sun4i-drm 1.0.0 20150629 for display-engine on
minor 0
[5.763064] sun4i-drm display-engine: fb0: sun4i-drmdrmfb frame buffer device
--
Andrey Lebedev aka -.- . -.. -.. . .-.
Software engineer
Homepage: http://lebedev.lt/
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Re: [PATCH -next] crypto: ccree - remove set but not used variable 'du_size'
On Mon, Feb 03, 2020 at 03:39:21PM +, YueHaibing wrote:
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> drivers/crypto/ccree/cc_cipher.c: In function 'cc_setup_state_desc':
> drivers/crypto/ccree/cc_cipher.c:536:15: warning:
> variable 'du_size' set but not used [-Wunused-but-set-variable]
>
> commit 5c83e8ec4d51 ("crypto: ccree - fix FDE descriptor sequence")
> involved this unused variable, so remove it.
>
> Reported-by: Hulk Robot
> Signed-off-by: YueHaibing
> ---
> drivers/crypto/ccree/cc_cipher.c | 8
> 1 file changed, 8 deletions(-)
Patch applied. Thanks.
--
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PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
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[PATCH v3 2/3] drm/sun4i: tcon: Support LVDS output on Allwinner A20
From: Andrey Lebedev
A20 SoC (found in Cubieboard 2 among others) requires different LVDS set
up procedure than A33. Timing controller (tcon) driver only implements
sun6i-style procedure, that doesn't work on A20 (sun7i).
Signed-off-by: Andrey Lebedev
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 26 ++
drivers/gpu/drm/sun4i/sun4i_tcon.h | 11 +++
2 files changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index cc6b05ca2c69..800a9bd86112 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -114,6 +114,30 @@ static void sun4i_tcon_channel_set_status(struct
sun4i_tcon *tcon, int channel,
}
}
+static void sun4i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
+ const struct drm_encoder *encoder)
+{
+ regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
+SUN4I_TCON0_LVDS_ANA0_CK_EN |
+SUN4I_TCON0_LVDS_ANA0_REG_V |
+SUN4I_TCON0_LVDS_ANA0_REG_C |
+SUN4I_TCON0_LVDS_ANA0_EN_MB |
+SUN4I_TCON0_LVDS_ANA0_PD |
+SUN4I_TCON0_LVDS_ANA0_DCHS);
+
+ udelay(2); /* delay at least 1200 ns */
+ regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG,
+ SUN4I_TCON0_LVDS_ANA1_INIT,
+ SUN4I_TCON0_LVDS_ANA1_INIT);
+ udelay(1); /* delay at least 120 ns */
+ regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG,
+ SUN4I_TCON0_LVDS_ANA1_UPDATE,
+ SUN4I_TCON0_LVDS_ANA1_UPDATE);
+ regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
+ SUN4I_TCON0_LVDS_ANA0_EN_MB,
+ SUN4I_TCON0_LVDS_ANA0_EN_MB);
+}
+
static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
const struct drm_encoder *encoder)
{
@@ -1456,11 +1480,13 @@ static const struct sun4i_tcon_quirks sun6i_a31s_quirks
= {
};
static const struct sun4i_tcon_quirks sun7i_a20_quirks = {
+ .supports_lvds = true,
.has_channel_0 = true,
.has_channel_1 = true,
.dclk_min_div = 4,
/* Same display pipeline structure as A10 */
.set_mux= sun4i_a10_tcon_set_mux,
+ .setup_lvds_phy = sun4i_tcon_setup_lvds_phy,
};
static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h
b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index 2974e59ef9f2..cfbf4e6c1679 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -193,6 +193,13 @@
#define SUN4I_TCON_MUX_CTRL_REG0x200
#define SUN4I_TCON0_LVDS_ANA0_REG 0x220
+#define SUN4I_TCON0_LVDS_ANA0_DCHS BIT(16)
+#define SUN4I_TCON0_LVDS_ANA0_PD (BIT(20) | BIT(21))
+#define SUN4I_TCON0_LVDS_ANA0_EN_MBBIT(22)
+#define SUN4I_TCON0_LVDS_ANA0_REG_C(BIT(24) | BIT(25))
+#define SUN4I_TCON0_LVDS_ANA0_REG_V(BIT(26) | BIT(27))
+#define SUN4I_TCON0_LVDS_ANA0_CK_EN(BIT(29) | BIT(28))
+
#define SUN6I_TCON0_LVDS_ANA0_EN_MBBIT(31)
#define SUN6I_TCON0_LVDS_ANA0_EN_LDO BIT(30)
#define SUN6I_TCON0_LVDS_ANA0_EN_DRVC BIT(24)
@@ -201,6 +208,10 @@
#define SUN6I_TCON0_LVDS_ANA0_V(x) (((x) & 3) << 8)
#define SUN6I_TCON0_LVDS_ANA0_PD(x)(((x) & 3) << 4)
+#define SUN4I_TCON0_LVDS_ANA1_REG 0x224
+#define SUN4I_TCON0_LVDS_ANA1_INIT (0x1f << 26 | 0x1f <<
10)
+#define SUN4I_TCON0_LVDS_ANA1_UPDATE (0x1f << 16 | 0x1f <<
00)
+
#define SUN4I_TCON1_FILL_CTL_REG 0x300
#define SUN4I_TCON1_FILL_BEG0_REG 0x304
#define SUN4I_TCON1_FILL_END0_REG 0x308
--
2.20.1
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Re: [PATCH v2 1/4] PM / EM: add devices to Energy Model
On 06/02/2020 14:46, lukasz.l...@arm.com wrote:
> From: Lukasz Luba
[..]
> @@ -26,7 +28,7 @@ framework, and interested clients reading the data from it::
s/::/: ?
> | Thermal (IPA) | | Scheduler (EAS) | | Other |
> +---+ +-+ +---+
> | | em_pd_energy()|
> - | | em_cpu_get() |
> + | em_get_pd() | em_cpu_get() |
> +-+ | +-+
em_get_pd() and em_cpu_get()? Why not em_pd_get()? em_cpu_get() is a
specific em_get_pd(). right?
[...]
> @@ -85,13 +89,20 @@ API.
> 2.3 Accessing performance domains
> ^
>
> +There is two API functions which provide the access to the energy model:
> +em_cpu_get() which takes CPU id as an argument and em_get_pd() with device
> +pointer as an argument. It depends on the subsystem which interface it is
> +going to use, but in case of CPU devices both functions return the same
> +performance domain.
There is probably a reason why we need this specific function for CPU
devices? The reason should be described. People might ask why
em_get_pd() is not sufficient.
[...]
> - * A "performance domain" represents a group of CPUs whose performance is
> - * scaled together. All CPUs of a performance domain must have the same
> - * micro-architecture. Performance domains often have a 1-to-1 mapping with
> - * CPUFreq policies.
> + * In case of CPU device, a "performance domain" represents a group of CPUs
> + * whose performance is scaled together. All CPUs of a performance domain
> + * must have the same micro-architecture. Performance domains often have
> + * a 1-to-1 mapping with CPUFreq policies.
> + * In case of other devices the 'priv' field is unused.
> */
> struct em_perf_domain {
> - struct em_cap_state *table;
> - int nr_cap_states;
> - unsigned long cpus[0];
> + struct em_perf_state *table;
> + int nr_perf_states;
> + void *priv;
In case you go back to the variable length field plus type field to
distingush EM devices, keep cpus[0] as the name.
[..]
> /**
> - * em_pd_energy() - Estimates the energy consumed by the CPUs of a perf.
> domain
> + * em_pd_energy() - Estimates the energy consumed by the CPUs of a perf.
> + domain
Why this change?
[...]
> @@ -141,12 +210,12 @@ static struct em_perf_domain *em_create_pd(cpumask_t
> *span, int nr_states,
>*/
> opp_eff = freq / power;
> if (opp_eff >= prev_opp_eff)
> - pr_warn("pd%d: hertz/watts ratio non-monotonically
> decreasing: em_cap_state %d >= em_cap_state%d\n",
> - cpu, i, i - 1);
> + dev_warn(dev, "energy_model: hertz/watts ratio
> non-monotonically decreasing: em_perf_state %d >= em_perf_state%d\n",
s/energy_model/EM ?
[...]
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[PATCH] drm/amd/display: Don't take the address of skip_scdc_overwrite in dc_link_detect_helper
Clang warns:
../drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:980:36:
warning: address of 'sink->edid_caps.panel_patch.skip_scdc_overwrite'
will always evaluate to 'true' [-Wpointer-bool-conversion]
if (&sink->edid_caps.panel_patch.skip_scdc_overwrite)
~~ ^~~
1 warning generated.
This is probably not what was intended so remove the address of
operator, which matches how skip_scdc_overwrite is handled in the rest
of the driver.
While we're here, drop an extra newline after this if block.
Fixes: a760fc1bff03 ("drm/amd/display: add monitor patch to disable SCDC
read/write")
Link: https://github.com/ClangBuiltLinux/linux/issues/879
Signed-off-by: Nathan Chancellor
---
As an aside, I don't see skip_scdc_overwrite assigned a value anywhere,
is this working as intended?
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 24d99849be5e..a3bfa05c545e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -977,10 +977,9 @@ static bool dc_link_detect_helper(struct dc_link *link,
if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME) ||
(edid_status == EDID_OK)))
same_edid = is_same_edid(&prev_sink->dc_edid,
&sink->dc_edid);
- if (&sink->edid_caps.panel_patch.skip_scdc_overwrite)
+ if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
link->ctx->dc->debug.hdmi20_disable = true;
-
if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
sink_caps.transaction_type ==
DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
/*
--
2.25.0
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Re: [PATCH v2] drm/i915: Disable -Wtautological-constant-out-of-range-compare
On Thu, Feb 13, 2020 at 02:43:21PM -0800, Nick Desaulniers wrote: > On Wed, Feb 12, 2020 at 9:17 AM Michel Dänzer wrote: > > > > On 2020-02-12 6:07 p.m., Nathan Chancellor wrote: > > > On Wed, Feb 12, 2020 at 09:52:52AM +0100, Michel Dänzer wrote: > > >> On 2020-02-11 9:39 p.m., Nathan Chancellor wrote: > > >>> On Tue, Feb 11, 2020 at 10:41:48AM +0100, Michel Dänzer wrote: > > On 2020-02-11 7:13 a.m., Nathan Chancellor wrote: > > > A recent commit in clang added -Wtautological-compare to -Wall, which > > > is > > > enabled for i915 so we see the following warning: > > > > > > ../drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1485:22: warning: > > > result of comparison of constant 576460752303423487 with expression of > > > type 'unsigned int' is always false > > > [-Wtautological-constant-out-of-range-compare] > > > if (unlikely(remain > N_RELOC(ULONG_MAX))) > > > ^ > > > > > > This warning only happens on x86_64 but that check is relevant for > > > 32-bit x86 so we cannot remove it. > > > > That's suprising. AFAICT N_RELOC(ULONG_MAX) works out to the same value > > in both cases, and remain is a 32-bit value in both cases. How can it > > be > > larger than N_RELOC(ULONG_MAX) on 32-bit (but not on 64-bit)? > > > > >>> > > >>> Hi Michel, > > >>> > > >>> Can't this condition be true when UINT_MAX == ULONG_MAX? > > >> > > >> Oh, right, I think I was wrongly thinking long had 64 bits even on > > >> 32-bit. > > >> > > >> > > >> Anyway, this suggests a possible better solution: > > >> > > >> #if UINT_MAX == ULONG_MAX > > >> if (unlikely(remain > N_RELOC(ULONG_MAX))) > > >> return -EINVAL; > > >> #endif > > >> > > >> > > >> Or if that can't be used for some reason, something like > > >> > > >> if (unlikely((unsigned long)remain > N_RELOC(ULONG_MAX))) > > >> return -EINVAL; > > >> > > >> should silence the warning. > > > > > > I do like this one better than the former. > > > > FWIW, one downside of this one compared to all alternatives (presumably) > > is that it might end up generating actual code even on 64-bit, which > > always ends up skipping the return. > > The warning is pointing out that the conditional is always false, > which is correct on 64b. The check is only active for 32b. > https://godbolt.org/z/oQrgT_ > The cast silences the warning for 64b. (Note that GCC and Clang also > generate precisely the same instruction sequences in my example, just > GCC doesn't warn on such tautologies). Thanks for confirming! I'll send a patch to add the cast later tonight. Cheers, Nathan ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 1/2] ARM: sun7i: Support LVDS output on Allwinner A20
Hi,
The prefix of your title should be "drm/sun4i: tcon:" instead of "ARM:
sun7i:"
The latter would be if you were modifying files under arch/arm, but
you're modifying files in (drivers/gpu/)drm/sun4i :)
On Thu, Feb 13, 2020 at 12:23:55AM +0200, andrey.lebe...@gmail.com wrote:
> From: Andrey Lebedev
>
> A20 SoC (found in Cubieboard 2 among others) requires different LVDS set
> up procedure than A33. Timing controller (tcon) driver only implements
> sun6i-style procedure, that doesn't work on A20 (sun7i).
>
> Signed-off-by: Andrey Lebedev
> ---
> drivers/gpu/drm/sun4i/sun4i_tcon.c | 95 --
> drivers/gpu/drm/sun4i/sun4i_tcon.h | 14 +
> 2 files changed, 77 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> index c81cdce6ed55..e4c605ca685e 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> @@ -114,46 +114,73 @@ static void sun4i_tcon_channel_set_status(struct
> sun4i_tcon *tcon, int channel,
> }
> }
>
> +static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
> + const struct drm_encoder *encoder)
> +{
> + u8 val;
> +
> + regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
> + SUN6I_TCON0_LVDS_ANA0_C(2) |
> + SUN6I_TCON0_LVDS_ANA0_V(3) |
> + SUN6I_TCON0_LVDS_ANA0_PD(2) |
> + SUN6I_TCON0_LVDS_ANA0_EN_LDO);
> + udelay(2);
> +
> + regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
> +SUN6I_TCON0_LVDS_ANA0_EN_MB,
> +SUN6I_TCON0_LVDS_ANA0_EN_MB);
> + udelay(2);
> +
> + regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
> +SUN6I_TCON0_LVDS_ANA0_EN_DRVC,
> +SUN6I_TCON0_LVDS_ANA0_EN_DRVC);
> +
> + if (sun4i_tcon_get_pixel_depth(encoder) == 18)
> + val = 7;
> + else
> + val = 0xf;
> +
> + regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
> + SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf),
> + SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val));
> +
> +}
> +
> +static void sun4i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
> + const struct drm_encoder *encoder)
> +{
> + regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
> + SUN4I_TCON0_LVDS_ANA0_CK_EN |
> + SUN4I_TCON0_LVDS_ANA0_REG_V |
> + SUN4I_TCON0_LVDS_ANA0_REG_C |
> + SUN4I_TCON0_LVDS_ANA0_EN_MB |
> + SUN4I_TCON0_LVDS_ANA0_PD |
> + SUN4I_TCON0_LVDS_ANA0_DCHS);
> +
> + udelay(2); /* delay at least 1200 ns */
> + regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG,
> +SUN4I_TCON0_LVDS_ANA1_INIT,
> +SUN4I_TCON0_LVDS_ANA1_INIT);
> + udelay(1); /* delay at least 120 ns */
> + regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG,
> +SUN4I_TCON0_LVDS_ANA1_UPDATE,
> +SUN4I_TCON0_LVDS_ANA1_UPDATE);
> + regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
> +SUN4I_TCON0_LVDS_ANA0_EN_MB,
> +SUN4I_TCON0_LVDS_ANA0_EN_MB);
> +}
> +
> +
Patches should contain only one logical change, so ideally this should
be two patches: one to create the function pointer and fill it for the
A31 style setup, the other one to add support for the A20.
Also, you should have only a single line between the two functions and
the second should come before the first (alphabetical ordering).
Maxime
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Re: [PATCH v2 2/2] ARM: sun7i: dts: Add LVDS panel support on A20
Hi,
On Thu, Feb 13, 2020 at 10:08:23PM +0200, Andrey Lebedev wrote:
> On Thu, Feb 13, 2020 at 10:43:04AM +0100, Maxime Ripard wrote:
> > On Thu, Feb 13, 2020 at 12:23:57AM +0200, andrey.lebe...@gmail.com wrote:
> > > From: Andrey Lebedev
> > >
> > > Define pins for LVDS channels 0 and 1, configure reset line for tcon0 and
> > > provide sample LVDS panel, connected to tcon0.
> > >
> > > Signed-off-by: Andrey Lebedev
> >
> > And this prefix should be ARM: dts: sun7i ;)
>
> Ah, thanks, I think I've got the pattern now!
>
> > > + /omit-if-no-ref/
> > > + lcd_lvds0_pins: lcd_lvds0_pins {
> >
> > underscores in the node names will create a dtc warning at
> > compilation, you should use lcd-lvds0-pins instead.
It's silenced by default, but you'll get them with W=1
> You're right, I wasn't following the naming convention here. dtc doesn't
> produce any warning on this though. Fixed that anyway.
>
> > This will create a spurious warning message for TCON1, since we
> > adjusted the driver to tell it supports LVDS, but there's no LVDS
> > reset line, so we need to make it finer grained.
>
> Yes, I can attribute two of the messages in my dmesg log [1] to this
> ("Missing LVDS properties" and "LVDS output disabled". "sun4i-tcon
> 1c0d000.lcd-controller" is indeed tcon1). And yes, I can see how they
> can be confusing to someone.
>
> I'd need some pointers on how to deal with that though (if we want to do
> it in this scope).
Like I was mentionning, you could introduce a new compatible for each
TCON (tcon0 and tcon1) and only set the support_lvds flag for tcon0
Maxime
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[PATCH v3 3/3] ARM: dts: sun7i: Add LVDS panel support on A20
From: Andrey Lebedev
Define pins for LVDS channels 0 and 1, configure reset line for tcon0 and
provide sample LVDS panel, connected to tcon0.
Signed-off-by: Andrey Lebedev
---
arch/arm/boot/dts/sun7i-a20.dtsi | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 92b5be97085d..3b3c366a2bee 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -47,6 +47,7 @@
#include
#include
#include
+#include
/ {
interrupt-parent = <&gic>;
@@ -407,8 +408,8 @@
compatible = "allwinner,sun7i-a20-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = ;
- resets = <&ccu RST_TCON0>;
- reset-names = "lcd";
+ resets = <&ccu RST_TCON0>, <&ccu RST_LVDS>;
+ reset-names = "lcd", "lvds";
clocks = <&ccu CLK_AHB_LCD0>,
<&ccu CLK_TCON0_CH0>,
<&ccu CLK_TCON0_CH1>;
@@ -444,6 +445,11 @@
#size-cells = <0>;
reg = <1>;
+ tcon0_out_lvds: endpoint@0 {
+ reg = <0>;
+ allwinner,tcon-channel = <0>;
+ };
+
tcon0_out_hdmi: endpoint@1 {
reg = <1>;
remote-endpoint =
<&hdmi_in_tcon0>;
@@ -1162,6 +1168,24 @@
pins = "PI20", "PI21";
function = "uart7";
};
+
+ /omit-if-no-ref/
+ lcd_lvds0_pins: lcd-lvds0-pins {
+ pins =
+ "PD0", "PD1", "PD2", "PD3", "PD4",
+ "PD5", "PD6", "PD7", "PD8", "PD9";
+ function = "lvds0";
+ allwinner,drive = ;
+ };
+
+ /omit-if-no-ref/
+ lcd_lvds1_pins: lcd-lvds1-pins {
+ pins =
+ "PD10", "PD11", "PD12", "PD13", "PD14",
+ "PD15", "PD16", "PD17", "PD18", "PD19";
+ function = "lvds1";
+ allwinner,drive = ;
+ };
};
timer@1c20c00 {
--
2.20.1
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[PATCH] drm/i915: Cast remain to unsigned long in eb_relocate_vma
A recent commit in clang added -Wtautological-compare to -Wall, which is enabled for i915 after -Wtautological-compare is disabled for the rest of the kernel so we see the following warning on x86_64: ../drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1433:22: warning: result of comparison of constant 576460752303423487 with expression of type 'unsigned int' is always false [-Wtautological-constant-out-of-range-compare] if (unlikely(remain > N_RELOC(ULONG_MAX))) ^ ../include/linux/compiler.h:78:42: note: expanded from macro 'unlikely' # define unlikely(x)__builtin_expect(!!(x), 0) ^ 1 warning generated. It is not wrong in the case where ULONG_MAX > UINT_MAX but it does not account for the case where this file is built for 32-bit x86, where ULONG_MAX == UINT_MAX and this check is still relevant. Cast remain to unsigned long, which keeps the generated code the same (verified with clang-11 on x86_64 and GCC 9.2.0 on x86 and x86_64) and the warning is silenced so we can catch more potential issues in the future. Link: https://github.com/ClangBuiltLinux/linux/issues/778 Suggested-by: Michel Dänzer Signed-off-by: Nathan Chancellor --- Round 3 :) Previous threads/patches: https://lore.kernel.org/lkml/20191123195321.41305-1-natechancel...@gmail.com/ https://lore.kernel.org/lkml/20200211050808.29463-1-natechancel...@gmail.com/ drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 60c984e10c4a..47f4d8ab281e 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1430,7 +1430,7 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct i915_vma *vma) urelocs = u64_to_user_ptr(entry->relocs_ptr); remain = entry->relocation_count; - if (unlikely(remain > N_RELOC(ULONG_MAX))) + if (unlikely((unsigned long)remain > N_RELOC(ULONG_MAX))) return -EINVAL; /* -- 2.25.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: general protection fault in fbcon_cursor
syzbot has found a reproducer for the following crash on: HEAD commit:f2850dd5 Merge tag 'kbuild-fixes-v5.6' of git://git.kernel.. git tree: upstream console output: https://syzkaller.appspot.com/x/log.txt?x=120eaae6e0 kernel config: https://syzkaller.appspot.com/x/.config?x=735296e4dd620b10 dashboard link: https://syzkaller.appspot.com/bug?extid=6acf28c23c81badd89a7 compiler: gcc (GCC) 9.0.0 20181231 (experimental) syz repro: https://syzkaller.appspot.com/x/repro.syz?x=16c8fc09e0 C reproducer: https://syzkaller.appspot.com/x/repro.c?x=1364c07ee0 IMPORTANT: if you fix the bug, please add the following tag to the commit: Reported-by: syzbot+6acf28c23c81badd8...@syzkaller.appspotmail.com general protection fault, probably for non-canonical address 0xdc002001: [#1] PREEMPT SMP KASAN KASAN: probably user-memory-access in range [0x00010008-0x0001000f] CPU: 0 PID: 2873 Comm: kworker/0:35 Not tainted 5.6.0-rc1-syzkaller #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 Workqueue: events console_callback RIP: 0010:fbcon_cursor+0x114/0x660 drivers/video/fbdev/core/fbcon.c:1387 Code: 48 89 fa 48 c1 ea 03 80 3c 02 00 0f 85 e6 04 00 00 4d 8b b4 24 a0 03 00 00 48 b8 00 00 00 00 00 fc ff df 4c 89 f2 48 c1 ea 03 <0f> b6 14 02 4c 89 f0 83 e0 07 83 c0 01 38 d0 7c 08 84 d2 0f 85 ba RSP: 0018:c90008f7faf0 EFLAGS: 00010203 RAX: dc00 RBX: 8880a386 RCX: 83f31930 RDX: 2001 RSI: 83c5b4ec RDI: 88809c3573a0 RBP: c90008f7fb30 R08: 88809ec02300 R09: ed10147ef884 R10: ed10147ef883 R11: 8880a3f7c41f R12: 88809c357000 R13: 8880a385c000 R14: 0001000c R15: 8880a385c468 FS: () GS:8880ae80() knlGS: CS: 0010 DS: ES: CR0: 80050033 CR2: 00455300 CR3: a7dad000 CR4: 001406f0 DR0: DR1: DR2: DR3: DR6: fffe0ff0 DR7: 0400 Call Trace: set_cursor drivers/tty/vt/vt.c:908 [inline] set_cursor+0x1fb/0x280 drivers/tty/vt/vt.c:899 redraw_screen+0x4e1/0x7d0 drivers/tty/vt/vt.c:1013 complete_change_console+0x105/0x3a0 drivers/tty/vt/vt_ioctl.c:1264 change_console+0x19b/0x2c0 drivers/tty/vt/vt_ioctl.c:1389 console_callback+0x3a1/0x400 drivers/tty/vt/vt.c:2824 process_one_work+0xa05/0x17a0 kernel/workqueue.c:2264 worker_thread+0x98/0xe40 kernel/workqueue.c:2410 kthread+0x361/0x430 kernel/kthread.c:255 ret_from_fork+0x24/0x30 arch/x86/entry/entry_64.S:352 Modules linked in: ---[ end trace 10588331f3234462 ]--- RIP: 0010:fbcon_cursor+0x114/0x660 drivers/video/fbdev/core/fbcon.c:1387 Code: 48 89 fa 48 c1 ea 03 80 3c 02 00 0f 85 e6 04 00 00 4d 8b b4 24 a0 03 00 00 48 b8 00 00 00 00 00 fc ff df 4c 89 f2 48 c1 ea 03 <0f> b6 14 02 4c 89 f0 83 e0 07 83 c0 01 38 d0 7c 08 84 d2 0f 85 ba RSP: 0018:c90008f7faf0 EFLAGS: 00010203 RAX: dc00 RBX: 8880a386 RCX: 83f31930 RDX: 2001 RSI: 83c5b4ec RDI: 88809c3573a0 RBP: c90008f7fb30 R08: 88809ec02300 R09: ed10147ef884 R10: ed10147ef883 R11: 8880a3f7c41f R12: 88809c357000 R13: 8880a385c000 R14: 0001000c R15: 8880a385c468 FS: () GS:8880ae80() knlGS: CS: 0010 DS: ES: CR0: 80050033 CR2: 00455300 CR3: a7dad000 CR4: 001406f0 DR0: DR1: DR2: DR3: DR6: fffe0ff0 DR7: 0400 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[RFC PATCH 0/6] do not store GPU address in TTM
With this patch series I am trying to remove GPU address dependency in TTM and moving GPU address calculation to individual drm drivers. This is required[1] to continue the work started by Brian Welty to create struct drm_mem_region which can be leverage by DRM cgroup controller to manage memory limits. I have only manage to test amdgpu driver as I only have GPU for that. I might be doing something really stupid while calculeting gpu offset for some of the drivers so please be patient and let me know how can I improve that. [1] https://www.mail-archive.com/dri-devel@lists.freedesktop.org/msg272238.html Nirmoy Das (6): drm/amdgpu: move ttm bo->offset to amdgpu_bo drm/radeon: don't use ttm bo->offset drm/vmwgfx: don't use ttm bo->offset drm/nouveau: don't use ttm bo->offset drm/qxl: don't use ttm bo->offset drm/ttm: do not keep GPU dependent addresses drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 22 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 29 - drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 4 +-- drivers/gpu/drm/nouveau/dispnv04/crtc.c | 6 ++--- drivers/gpu/drm/nouveau/dispnv04/disp.c | 2 +- drivers/gpu/drm/nouveau/dispnv04/overlay.c | 6 ++--- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/core507d.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/ovly507e.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 2 +- drivers/gpu/drm/nouveau/nouveau_abi16.c | 8 +++--- drivers/gpu/drm/nouveau/nouveau_bo.c| 1 + drivers/gpu/drm/nouveau/nouveau_bo.h| 3 +++ drivers/gpu/drm/nouveau/nouveau_chan.c | 2 +- drivers/gpu/drm/nouveau/nouveau_fbcon.c | 2 +- drivers/gpu/drm/nouveau/nouveau_gem.c | 10 +++ drivers/gpu/drm/qxl/qxl_drv.h | 6 ++--- drivers/gpu/drm/qxl/qxl_kms.c | 3 +++ drivers/gpu/drm/qxl/qxl_object.h| 5 drivers/gpu/drm/qxl/qxl_ttm.c | 9 --- drivers/gpu/drm/radeon/radeon.h | 1 + drivers/gpu/drm/radeon/radeon_object.h | 16 +++- drivers/gpu/drm/radeon/radeon_ttm.c | 4 +-- drivers/gpu/drm/ttm/ttm_bo.c| 7 - drivers/gpu/drm/vmwgfx/vmwgfx_bo.c | 4 +-- drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 2 +- drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c| 2 +- drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 2 -- include/drm/ttm/ttm_bo_api.h| 2 -- include/drm/ttm/ttm_bo_driver.h | 1 - 33 files changed, 99 insertions(+), 72 deletions(-) -- 2.25.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
RE: [PATCH v4 7/7] RFC: drm/panfrost: devfreq: Add support for 2 regulators
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[PATCH] drm/mediatek: Update the fb property mtk_plane_atomic_async_update
Commit 920fffcc8912 ("drm/mediatek: update cursors by using async atomic
update") added support to async updates of cursors by using the new atomic
interface for that. Unfortunately, introduced two issues. The first one is
that since then, the drm_atomic_helper_async_commit triggers a WARNING due
current fb is not the new fb. The second one, is that we get a black screen
connecting the external display on Elm device and another WARNING due vblank
wait timed out.
Swap the fb in mtk_plane_atomic_async_update to fix both issues.
Fixes: 920fffcc8912 ("drm/mediatek: update cursors by using async atomic
update")
Signed-off-by: Enric Balletbo i Serra
---
drivers/gpu/drm/mediatek/mtk_drm_plane.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c
b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
index 914cc7619cd7..7eb10115e72a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
@@ -116,6 +116,7 @@ static void mtk_plane_atomic_async_update(struct drm_plane
*plane,
plane->state->src_h = new_state->src_h;
plane->state->src_w = new_state->src_w;
state->pending.async_dirty = true;
+ swap(plane->state->fb, new_state->fb);
mtk_drm_crtc_async_update(new_state->crtc, plane, new_state);
}
--
2.25.0
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[RFC PATCH 1/6] drm/amdgpu: move ttm bo->offset to amdgpu_bo
GPU address should belong to driver not in memory management.
This patch moves ttm bo.offset and gpu_offset calculation to amdgpu driver.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 22 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 29 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 4 +--
5 files changed, 46 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 6f60a581e3ba..1b1c393587a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -917,7 +917,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32
domain,
bo->pin_count++;
if (max_offset != 0) {
- u64 domain_start =
bo->tbo.bdev->man[mem_type].gpu_offset;
+ u64 domain_start = amdgpu_ttm_domain_start(adev,
mem_type);
WARN_ON_ONCE(max_offset <
(amdgpu_bo_gpu_offset(bo) - domain_start));
}
@@ -1467,7 +1467,25 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
!(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
- return amdgpu_gmc_sign_extend(bo->tbo.offset);
+ return amdgpu_bo_gpu_offset_no_check(bo);
+}
+
+/**
+ * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo
+ * @bo:amdgpu object for which we query the offset
+ *
+ * Returns:
+ * current GPU offset of the object without raising warnings.
+ */
+u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
+{
+ struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+ uint64_t offset;
+
+offset = (bo->tbo.mem.start << PAGE_SHIFT) +
+amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type);
+
+ return amdgpu_gmc_sign_extend(offset);
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 96d805889e8d..9075ef20ce02 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -288,6 +288,7 @@ int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev,
struct dma_resv *resv,
bool intr);
int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr);
u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
+u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo);
int amdgpu_bo_validate(struct amdgpu_bo *bo);
int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow,
struct dma_fence **fence);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 2c1d1eb1a7e1..4bb02d787945 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -103,7 +103,6 @@ static int amdgpu_init_mem_type(struct ttm_bo_device *bdev,
uint32_t type,
case TTM_PL_TT:
/* GTT memory */
man->func = &amdgpu_gtt_mgr_func;
- man->gpu_offset = adev->gmc.gart_start;
man->available_caching = TTM_PL_MASK_CACHING;
man->default_caching = TTM_PL_FLAG_CACHED;
man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
@@ -111,7 +110,6 @@ static int amdgpu_init_mem_type(struct ttm_bo_device *bdev,
uint32_t type,
case TTM_PL_VRAM:
/* "On-card" video ram */
man->func = &amdgpu_vram_mgr_func;
- man->gpu_offset = adev->gmc.vram_start;
man->flags = TTM_MEMTYPE_FLAG_FIXED |
TTM_MEMTYPE_FLAG_MAPPABLE;
man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
@@ -122,7 +120,6 @@ static int amdgpu_init_mem_type(struct ttm_bo_device *bdev,
uint32_t type,
case AMDGPU_PL_OA:
/* On-chip GDS memory*/
man->func = &ttm_bo_manager_func;
- man->gpu_offset = 0;
man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
man->available_caching = TTM_PL_FLAG_UNCACHED;
man->default_caching = TTM_PL_FLAG_UNCACHED;
@@ -270,7 +267,7 @@ static uint64_t amdgpu_mm_node_addr(struct
ttm_buffer_object *bo,
if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
addr = mm_node->start << PAGE_SHIFT;
- addr += bo->bdev->man[mem->mem_type].gpu_offset;
+ addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
mem->mem_type);
}
return addr;
}
@@ -757,6 +754,27 @@ static unsigned long amdgpu_ttm_io_mem_pfn(struct
ttm_buffer_object *bo,
(offset >> PAGE_SHIFT);
}
+/**
+ * amdgpu_ttm_domain_start - Returns GPU star
[RFC PATCH 5/6] drm/qxl: don't use ttm bo->offset
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/qxl/qxl_drv.h| 6 ++
drivers/gpu/drm/qxl/qxl_kms.c| 3 +++
drivers/gpu/drm/qxl/qxl_object.h | 5 -
drivers/gpu/drm/qxl/qxl_ttm.c| 9 -
4 files changed, 5 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/qxl/qxl_drv.h b/drivers/gpu/drm/qxl/qxl_drv.h
index 27e45a2d6b52..9a76a2a0283d 100644
--- a/drivers/gpu/drm/qxl/qxl_drv.h
+++ b/drivers/gpu/drm/qxl/qxl_drv.h
@@ -311,10 +311,8 @@ qxl_bo_physical_address(struct qxl_device *qdev, struct
qxl_bo *bo,
(bo->tbo.mem.mem_type == TTM_PL_VRAM)
? &qdev->main_slot : &qdev->surfaces_slot;
- WARN_ON_ONCE((bo->tbo.offset & slot->gpu_offset) != slot->gpu_offset);
-
- /* TODO - need to hold one of the locks to read tbo.offset */
- return slot->high_bits | (bo->tbo.offset - slot->gpu_offset + offset);
+ return slot->high_bits | ((bo->tbo.mem.start << PAGE_SHIFT) +
+ slot->gpu_offset + offset);
}
/* qxl_display.c */
diff --git a/drivers/gpu/drm/qxl/qxl_kms.c b/drivers/gpu/drm/qxl/qxl_kms.c
index 611cbe7aee69..937cac9ba384 100644
--- a/drivers/gpu/drm/qxl/qxl_kms.c
+++ b/drivers/gpu/drm/qxl/qxl_kms.c
@@ -71,11 +71,14 @@ static void setup_slot(struct qxl_device *qdev,
unsigned long size)
{
uint64_t high_bits;
+ unsigned int gpu_offset_shift =
+ 64 - (qdev->rom->slot_gen_bits + qdev->rom->slot_id_bits + 8);
slot->index = slot_index;
slot->name = slot_name;
slot->start_phys_addr = start_phys_addr;
slot->size = size;
+ slot->gpu_offset = (uint64_t)slot_index << gpu_offset_shift;
setup_hw_slot(qdev, slot);
diff --git a/drivers/gpu/drm/qxl/qxl_object.h b/drivers/gpu/drm/qxl/qxl_object.h
index 8ae54ba7857c..21fa81048f4f 100644
--- a/drivers/gpu/drm/qxl/qxl_object.h
+++ b/drivers/gpu/drm/qxl/qxl_object.h
@@ -48,11 +48,6 @@ static inline void qxl_bo_unreserve(struct qxl_bo *bo)
ttm_bo_unreserve(&bo->tbo);
}
-static inline u64 qxl_bo_gpu_offset(struct qxl_bo *bo)
-{
- return bo->tbo.offset;
-}
-
static inline unsigned long qxl_bo_size(struct qxl_bo *bo)
{
return bo->tbo.num_pages << PAGE_SHIFT;
diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c
index 16a5e903533d..2a43d0ef9ba1 100644
--- a/drivers/gpu/drm/qxl/qxl_ttm.c
+++ b/drivers/gpu/drm/qxl/qxl_ttm.c
@@ -56,11 +56,6 @@ static int qxl_invalidate_caches(struct ttm_bo_device *bdev,
uint32_t flags)
static int qxl_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
struct ttm_mem_type_manager *man)
{
- struct qxl_device *qdev = qxl_get_qdev(bdev);
- unsigned int gpu_offset_shift =
- 64 - (qdev->rom->slot_gen_bits + qdev->rom->slot_id_bits + 8);
- struct qxl_memslot *slot;
-
switch (type) {
case TTM_PL_SYSTEM:
/* System memory */
@@ -71,11 +66,7 @@ static int qxl_init_mem_type(struct ttm_bo_device *bdev,
uint32_t type,
case TTM_PL_VRAM:
case TTM_PL_PRIV:
/* "On-card" video ram */
- slot = (type == TTM_PL_VRAM) ?
- &qdev->main_slot : &qdev->surfaces_slot;
- slot->gpu_offset = (uint64_t)type << gpu_offset_shift;
man->func = &ttm_bo_manager_func;
- man->gpu_offset = slot->gpu_offset;
man->flags = TTM_MEMTYPE_FLAG_FIXED |
TTM_MEMTYPE_FLAG_MAPPABLE;
man->available_caching = TTM_PL_MASK_CACHING;
--
2.25.0
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Re: [Intel-gfx] [PATCH v2] drm/i915: Disable -Wtautological-constant-out-of-range-compare
On Thu, Feb 13, 2020 at 04:37:15PM +0200, Jani Nikula wrote: > On Wed, 12 Feb 2020, Michel Dänzer wrote: > > On 2020-02-12 6:07 p.m., Nathan Chancellor wrote: > >> On Wed, Feb 12, 2020 at 09:52:52AM +0100, Michel Dänzer wrote: > >>> On 2020-02-11 9:39 p.m., Nathan Chancellor wrote: > On Tue, Feb 11, 2020 at 10:41:48AM +0100, Michel Dänzer wrote: > > On 2020-02-11 7:13 a.m., Nathan Chancellor wrote: > >> A recent commit in clang added -Wtautological-compare to -Wall, which > >> is > >> enabled for i915 so we see the following warning: > >> > >> ../drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1485:22: warning: > >> result of comparison of constant 576460752303423487 with expression of > >> type 'unsigned int' is always false > >> [-Wtautological-constant-out-of-range-compare] > >> if (unlikely(remain > N_RELOC(ULONG_MAX))) > >> ^ > >> > >> This warning only happens on x86_64 but that check is relevant for > >> 32-bit x86 so we cannot remove it. > > > > That's suprising. AFAICT N_RELOC(ULONG_MAX) works out to the same value > > in both cases, and remain is a 32-bit value in both cases. How can it be > > larger than N_RELOC(ULONG_MAX) on 32-bit (but not on 64-bit)? > > > > Hi Michel, > > Can't this condition be true when UINT_MAX == ULONG_MAX? > >>> > >>> Oh, right, I think I was wrongly thinking long had 64 bits even on 32-bit. > >>> > >>> > >>> Anyway, this suggests a possible better solution: > >>> > >>> #if UINT_MAX == ULONG_MAX > >>> if (unlikely(remain > N_RELOC(ULONG_MAX))) > >>> return -EINVAL; > >>> #endif > >>> > >>> > >>> Or if that can't be used for some reason, something like > >>> > >>> if (unlikely((unsigned long)remain > N_RELOC(ULONG_MAX))) > >>> return -EINVAL; > >>> > >>> should silence the warning. > >> > >> I do like this one better than the former. > > > > FWIW, one downside of this one compared to all alternatives (presumably) > > is that it might end up generating actual code even on 64-bit, which > > always ends up skipping the return. > > I like this better than the UINT_MAX == ULONG_MAX comparison because > that creates a dependency on the type of remain. > > Then again, a sufficiently clever compiler could see through the cast, > and flag the warning anyway... Would you prefer a patch that adds that cast rather than silencing the warning outright? It does appear to work for clang. Cheers, Nathan ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 1/2] Documentation: bindings: Add ANX7688 HDMI to DP bridge binding
From: Nicolas Boichat
Add documentation for DT properties supported by anx7688 HDMI-DP
converter.
Signed-off-by: Nicolas Boichat
Signed-off-by: Hsin-Yi Wang
Signed-off-by: Enric Balletbo i Serra
---
Changes in v2:
- Improve a bit the descriptions using the info from the datasheet.
- Convert binding to yaml.
- Use dual licensing.
.../bindings/display/bridge/anx7688.yaml | 79 +++
1 file changed, 79 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/anx7688.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/anx7688.yaml
b/Documentation/devicetree/bindings/display/bridge/anx7688.yaml
new file mode 100644
index ..c1b4b5191d44
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/anx7688.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/anx7688.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analogix ANX7688 HDMI to USB Type-C Bridge (Port Controller with MUX)
+
+maintainers:
+ - Nicolas Boichat
+ - Enric Balletbo i Serra
+
+description: |
+ The ANX7688 is a single-chip mobile transmitter to support 4K 60 frames per
+ second (4096x2160p60) or FHD 120 frames per second (1920x1080p120) video
+ resolution from a smartphone or tablet with full function USB-C.
+
+ This binding only describes the HDMI to DP display bridge.
+
+properties:
+ compatible:
+const: analogix,anx7688
+
+ reg:
+maxItems: 1
+description: I2C address of the device
+
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: |
+ Video port for HDMI input
+
+ port@1:
+type: object
+description: |
+ Video port for DP output
+
+required:
+ - port@0
+
+required:
+ - compatible
+ - reg
+ - ports
+
+examples:
+ - |
+i2c0 {
+#address-cells = <1>;
+#size-cells = <0>;
+
+anx7688: dp-bridge@2c {
+compatible = "analogix,anx7688";
+reg = <0x2c>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+anx7866_in: endpoint {
+remote-endpoint = <&hdmi0_out>;
+};
+};
+
+port@1 {
+reg = <1>;
+anx7866_out: endpoint {
+remote-endpoint = <&panel_in>;
+ };
+};
+};
+};
+};
--
2.25.0
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Re: [PATCH v2 2/2] ARM: sun7i: dts: Add LVDS panel support on A20
On Thu, Feb 13, 2020 at 12:23:57AM +0200, andrey.lebe...@gmail.com wrote:
> From: Andrey Lebedev
>
> Define pins for LVDS channels 0 and 1, configure reset line for tcon0 and
> provide sample LVDS panel, connected to tcon0.
>
> Signed-off-by: Andrey Lebedev
And this prefix should be ARM: dts: sun7i ;)
> ---
> arch/arm/boot/dts/sun7i-a20.dtsi | 45 +---
> 1 file changed, 42 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi
> b/arch/arm/boot/dts/sun7i-a20.dtsi
> index 92b5be97085d..b05fdf8df32e 100644
> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> @@ -47,6 +47,7 @@
> #include
> #include
> #include
> +#include
>
> / {
> interrupt-parent = <&gic>;
> @@ -407,8 +408,8 @@
> compatible = "allwinner,sun7i-a20-tcon";
> reg = <0x01c0c000 0x1000>;
> interrupts = ;
> - resets = <&ccu RST_TCON0>;
> - reset-names = "lcd";
> + resets = <&ccu RST_TCON0>, <&ccu RST_LVDS>;
> + reset-names = "lcd", "lvds";
> clocks = <&ccu CLK_AHB_LCD0>,
><&ccu CLK_TCON0_CH0>,
><&ccu CLK_TCON0_CH1>;
> @@ -444,6 +445,11 @@
> #size-cells = <0>;
> reg = <1>;
>
> + tcon0_out_lvds: endpoint@0 {
> + reg = <0>;
> + remote-endpoint =
> <&lvds_in_tcon0>;
> + allwinner,tcon-channel = <0>;
> + };
A new line here would be nice
> tcon0_out_hdmi: endpoint@1 {
> reg = <1>;
> remote-endpoint =
> <&hdmi_in_tcon0>;
> @@ -686,6 +692,19 @@
> };
> };
>
> + lvds_panel: panel@1c16500 {
> + compatible = "panel-lvds";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + port {
> + lvds_in_tcon0: endpoint {
> + remote-endpoint = <&tcon0_out_lvds>;
> + };
> + };
> + };
> +
There's no point in creating that panel.
> spi2: spi@1c17000 {
> compatible = "allwinner,sun4i-a10-spi";
> reg = <0x01c17000 0x1000>;
> @@ -872,7 +891,7 @@
> gmac_rgmii_pins: gmac-rgmii-pins {
> pins = "PA0", "PA1", "PA2",
> "PA3", "PA4", "PA5", "PA6",
> - "PA7", "PA8", "PA10",
> + "PA7", "PA8", "PA10",
> "PA11", "PA12", "PA13",
> "PA15", "PA16";
> function = "gmac";
> @@ -1162,6 +1181,26 @@
> pins = "PI20", "PI21";
> function = "uart7";
> };
> +
> + /omit-if-no-ref/
> + lcd_lvds0_pins: lcd_lvds0_pins {
underscores in the node names will create a dtc warning at
compilation, you should use lcd-lvds0-pins instead.
> + allwinner,pins =
> + "PD0", "PD1", "PD2", "PD3", "PD4",
> + "PD5", "PD6", "PD7", "PD8", "PD9";
> + allwinner,function = "lvds0";
> + allwinner,drive = ;
> + allwinner,pull = ;
Those properties are deprecated and should be replaced by pins and
functions. allwinner,drive and allwinner,pull are at their default
values and can be dropped.
This will create a spurious warning message for TCON1, since we
adjusted the driver to tell it supports LVDS, but there's no LVDS
reset line, so we need to make it finer grained.
Maybe adding a tcon0 / tcon1 compatible? Chen-Yu, any thought?
Maxime
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[PATCH v3 1/3] drm/sun4i: tcon: Introduce LVDS setup routine setting
From: Andrey Lebedev
Different sunxi flavors require slightly different sequence for enabling
LVDS output. This allows to differentiate between them.
Signed-off-by: Andrey Lebedev
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 68 --
drivers/gpu/drm/sun4i/sun4i_tcon.h | 3 ++
2 files changed, 39 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index c81cdce6ed55..cc6b05ca2c69 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -114,46 +114,48 @@ static void sun4i_tcon_channel_set_status(struct
sun4i_tcon *tcon, int channel,
}
}
+static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
+ const struct drm_encoder *encoder)
+{
+ u8 val;
+
+ regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
+SUN6I_TCON0_LVDS_ANA0_C(2) |
+SUN6I_TCON0_LVDS_ANA0_V(3) |
+SUN6I_TCON0_LVDS_ANA0_PD(2) |
+SUN6I_TCON0_LVDS_ANA0_EN_LDO);
+ udelay(2);
+
+ regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
+ SUN6I_TCON0_LVDS_ANA0_EN_MB,
+ SUN6I_TCON0_LVDS_ANA0_EN_MB);
+ udelay(2);
+
+ regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
+ SUN6I_TCON0_LVDS_ANA0_EN_DRVC,
+ SUN6I_TCON0_LVDS_ANA0_EN_DRVC);
+
+ if (sun4i_tcon_get_pixel_depth(encoder) == 18)
+ val = 7;
+ else
+ val = 0xf;
+
+ regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
+ SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf),
+ SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val));
+
+}
+
static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon,
const struct drm_encoder *encoder,
bool enabled)
{
if (enabled) {
- u8 val;
-
regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
SUN4I_TCON0_LVDS_IF_EN,
SUN4I_TCON0_LVDS_IF_EN);
-
- /*
-* As their name suggest, these values only apply to the A31
-* and later SoCs. We'll have to rework this when merging
-* support for the older SoCs.
-*/
- regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
-SUN6I_TCON0_LVDS_ANA0_C(2) |
-SUN6I_TCON0_LVDS_ANA0_V(3) |
-SUN6I_TCON0_LVDS_ANA0_PD(2) |
-SUN6I_TCON0_LVDS_ANA0_EN_LDO);
- udelay(2);
-
- regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
- SUN6I_TCON0_LVDS_ANA0_EN_MB,
- SUN6I_TCON0_LVDS_ANA0_EN_MB);
- udelay(2);
-
- regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
- SUN6I_TCON0_LVDS_ANA0_EN_DRVC,
- SUN6I_TCON0_LVDS_ANA0_EN_DRVC);
-
- if (sun4i_tcon_get_pixel_depth(encoder) == 18)
- val = 7;
- else
- val = 0xf;
-
- regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
- SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf),
- SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val));
+ if (tcon->quirks->setup_lvds_phy)
+ tcon->quirks->setup_lvds_phy(tcon, encoder);
} else {
regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
SUN4I_TCON0_LVDS_IF_EN, 0);
@@ -1465,12 +1467,14 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks
= {
.has_channel_0 = true,
.has_lvds_alt = true,
.dclk_min_div = 1,
+ .setup_lvds_phy = sun6i_tcon_setup_lvds_phy,
};
static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
.supports_lvds = true,
.has_channel_0 = true,
.dclk_min_div = 1,
+ .setup_lvds_phy = sun6i_tcon_setup_lvds_phy,
};
static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = {
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h
b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index a62ec826ae71..2974e59ef9f2 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -228,6 +228,9 @@ struct sun4i_tcon_quirks {
/* callback to handle tcon muxing options */
int (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *);
+ /* handler for LVDS setup routine */
+ void(*setup_lvds_phy)(struct sun4i_tcon *tcon,
+
Re: [PATCH] drm/mediatek: Update the fb property mtk_plane_atomic_async_update
Hi,
On 13/2/20 13:01, Enric Balletbo i Serra wrote:
> Commit 920fffcc8912 ("drm/mediatek: update cursors by using async atomic
> update") added support to async updates of cursors by using the new atomic
> interface for that. Unfortunately, introduced two issues. The first one is
> that since then, the drm_atomic_helper_async_commit triggers a WARNING due
> current fb is not the new fb. The second one, is that we get a black screen
> connecting the external display on Elm device and another WARNING due vblank
> wait timed out.
>
> Swap the fb in mtk_plane_atomic_async_update to fix both issues.
>
> Fixes: 920fffcc8912 ("drm/mediatek: update cursors by using async atomic
> update")
> Signed-off-by: Enric Balletbo i Serra
> ---
I just noticed this, which should fix the problem too, so you can ignore this
patch.
https://patchwork.kernel.org/patch/11379571/
>
> drivers/gpu/drm/mediatek/mtk_drm_plane.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c
> b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
> index 914cc7619cd7..7eb10115e72a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
> @@ -116,6 +116,7 @@ static void mtk_plane_atomic_async_update(struct
> drm_plane *plane,
> plane->state->src_h = new_state->src_h;
> plane->state->src_w = new_state->src_w;
> state->pending.async_dirty = true;
> + swap(plane->state->fb, new_state->fb);
>
> mtk_drm_crtc_async_update(new_state->crtc, plane, new_state);
> }
>
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Re: [PATCH v2 1/4] PM / EM: add devices to Energy Model
On 2/13/20 10:59 AM, Dietmar Eggemann wrote:
On 06/02/2020 14:46, lukasz.l...@arm.com wrote:
From: Lukasz Luba
[..]
@@ -26,7 +28,7 @@ framework, and interested clients reading the data from it::
s/::/: ?
| Thermal (IPA) | | Scheduler (EAS) | | Other |
+---+ +-+ +---+
| | em_pd_energy()|
- | | em_cpu_get() |
+ | em_get_pd() | em_cpu_get() |
+-+ | +-+
em_get_pd() and em_cpu_get()? Why not em_pd_get()? em_cpu_get() is a
specific em_get_pd(). right?
Yes. I will rename 'em_get_pd' to 'em_pd_get'
[...]
@@ -85,13 +89,20 @@ API.
2.3 Accessing performance domains
^
+There is two API functions which provide the access to the energy model:
+em_cpu_get() which takes CPU id as an argument and em_get_pd() with device
+pointer as an argument. It depends on the subsystem which interface it is
+going to use, but in case of CPU devices both functions return the same
+performance domain.
There is probably a reason why we need this specific function for CPU
devices? The reason should be described. People might ask why
em_get_pd() is not sufficient.
True, good point. I will extend the comment in em_cpu_get().
[...]
- * A "performance domain" represents a group of CPUs whose performance is
- * scaled together. All CPUs of a performance domain must have the same
- * micro-architecture. Performance domains often have a 1-to-1 mapping with
- * CPUFreq policies.
+ * In case of CPU device, a "performance domain" represents a group of CPUs
+ * whose performance is scaled together. All CPUs of a performance domain
+ * must have the same micro-architecture. Performance domains often have
+ * a 1-to-1 mapping with CPUFreq policies.
+ * In case of other devices the 'priv' field is unused.
*/
struct em_perf_domain {
- struct em_cap_state *table;
- int nr_cap_states;
- unsigned long cpus[0];
+ struct em_perf_state *table;
+ int nr_perf_states;
+ void *priv;
In case you go back to the variable length field plus type field to
distingush EM devices, keep cpus[0] as the name.
OK, I will.
[..]
/**
- * em_pd_energy() - Estimates the energy consumed by the CPUs of a perf. domain
+ * em_pd_energy() - Estimates the energy consumed by the CPUs of a perf.
+ domain
Why this change?
hmmm, that's odd, maybe there was 'device' then I changed it back to
'CPUs' but forgot to move the 'domain' to the old place.
[...]
@@ -141,12 +210,12 @@ static struct em_perf_domain *em_create_pd(cpumask_t
*span, int nr_states,
*/
opp_eff = freq / power;
if (opp_eff >= prev_opp_eff)
- pr_warn("pd%d: hertz/watts ratio non-monotonically decreasing:
em_cap_state %d >= em_cap_state%d\n",
- cpu, i, i - 1);
+ dev_warn(dev, "energy_model: hertz/watts ratio
non-monotonically decreasing: em_perf_state %d >= em_perf_state%d\n",
s/energy_model/EM ?
OK, I will rename them in all places.
Thank you for the review.
Regards,
Lukasz
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[PATCH v2 2/2] drm/bridge: anx7688: Add anx7688 bridge driver support
From: Nicolas Boichat
ANX7688 is a HDMI to DP converter (as well as USB-C port controller),
that has an internal microcontroller.
The only reason a Linux kernel driver is necessary is to reject
resolutions that require more bandwidth than what is available on
the DP side. DP bandwidth and lane count are reported by the bridge
via 2 registers on I2C.
Signed-off-by: Nicolas Boichat
Signed-off-by: Hsin-Yi Wang
Signed-off-by: Enric Balletbo i Serra
---
Changes in v2:
- Move driver to drivers/gpu/drm/bridge/analogix.
- Make the driver OF only so we can reduce the ifdefs.
- Update the Copyright to 2020.
- Use probe_new so we can get rid of the i2c_device_id table.
drivers/gpu/drm/bridge/analogix/Kconfig | 12 ++
drivers/gpu/drm/bridge/analogix/Makefile | 1 +
.../drm/bridge/analogix/analogix-anx7688.c| 188 ++
3 files changed, 201 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/analogix/analogix-anx7688.c
diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig
b/drivers/gpu/drm/bridge/analogix/Kconfig
index e1fa7d820373..af7c2939403c 100644
--- a/drivers/gpu/drm/bridge/analogix/Kconfig
+++ b/drivers/gpu/drm/bridge/analogix/Kconfig
@@ -11,6 +11,18 @@ config DRM_ANALOGIX_ANX6345
ANX6345 transforms the LVTTL RGB output of an
application processor to eDP or DisplayPort.
+config DRM_ANALOGIX_ANX7688
+ tristate "Analogix ANX7688 bridge"
+ depends on OF
+ select DRM_KMS_HELPER
+ select REGMAP_I2C
+ help
+ ANX7688 is an ultra-low power 4k Ultra-HD (4096x2160p60)
+ mobile HD transmitter designed for portable devices. The
+ ANX7688 converts HDMI 2.0 to DisplayPort 1.3 Ultra-HD
+ including an intelligent crosspoint switch to support
+ USB Type-C.
+
config DRM_ANALOGIX_ANX78XX
tristate "Analogix ANX78XX bridge"
select DRM_ANALOGIX_DP
diff --git a/drivers/gpu/drm/bridge/analogix/Makefile
b/drivers/gpu/drm/bridge/analogix/Makefile
index 97669b374098..27cd73635c8c 100644
--- a/drivers/gpu/drm/bridge/analogix/Makefile
+++ b/drivers/gpu/drm/bridge/analogix/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
analogix_dp-objs := analogix_dp_core.o analogix_dp_reg.o analogix-i2c-dptx.o
obj-$(CONFIG_DRM_ANALOGIX_ANX6345) += analogix-anx6345.o
+obj-$(CONFIG_DRM_ANALOGIX_ANX7688) += analogix-anx7688.o
obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o
obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp.o
diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx7688.c
b/drivers/gpu/drm/bridge/analogix/analogix-anx7688.c
new file mode 100644
index ..10a7cd0f9126
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix-anx7688.c
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * ANX7688 HDMI->DP bridge driver
+ *
+ * Copyright 2020 Google LLC
+ */
+
+#include
+#include
+#include
+#include
+
+/* Register addresses */
+#define VENDOR_ID_REG 0x00
+#define DEVICE_ID_REG 0x02
+
+#define FW_VERSION_REG 0x80
+
+#define DP_BANDWIDTH_REG 0x85
+#define DP_LANE_COUNT_REG 0x86
+
+#define VENDOR_ID 0x1f29
+#define DEVICE_ID 0x7688
+
+/* First supported firmware version (0.85) */
+#define MINIMUM_FW_VERSION 0x0085
+
+struct anx7688 {
+ struct drm_bridge bridge;
+ struct i2c_client *client;
+ struct regmap *regmap;
+
+ bool filter;
+};
+
+static inline struct anx7688 *bridge_to_anx7688(struct drm_bridge *bridge)
+{
+ return container_of(bridge, struct anx7688, bridge);
+}
+
+static bool anx7688_bridge_mode_fixup(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ struct anx7688 *anx7688 = bridge_to_anx7688(bridge);
+ int totalbw, requiredbw;
+ u8 dpbw, lanecount;
+ u8 regs[2];
+ int ret;
+
+ if (!anx7688->filter)
+ return true;
+
+ /* Read both regs 0x85 (bandwidth) and 0x86 (lane count). */
+ ret = regmap_bulk_read(anx7688->regmap, DP_BANDWIDTH_REG, regs, 2);
+ if (ret < 0) {
+ dev_err(&anx7688->client->dev,
+ "Failed to read bandwidth/lane count\n");
+ return false;
+ }
+ dpbw = regs[0];
+ lanecount = regs[1];
+
+ /* Maximum 0x19 bandwidth (6.75 Gbps Turbo mode), 2 lanes */
+ if (dpbw > 0x19 || lanecount > 2) {
+ dev_err(&anx7688->client->dev,
+ "Invalid bandwidth/lane count (%02x/%d)\n",
+ dpbw, lanecount);
+ return false;
+ }
+
+ /* Compute available bandwidth (kHz) */
+ totalbw = dpbw * lanecount * 27 * 8 / 10;
+
+ /* Required bandwidth (8 bpc, kHz) */
+ requiredbw = mode->clock * 8 * 3;
+
+ dev_dbg(&anx7688->client->dev,
+ "DP bandwidth: %d kHz (%02x/%d); mode requires %d Khz\n",
+ totalbw,
[RFC PATCH 3/6] drm/vmwgfx: don't use ttm bo->offset
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c | 4 ++--
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c| 2 +-
drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c | 2 +-
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 2 --
4 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
b/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
index 74016a08d118..dd9fd609d37c 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
@@ -258,7 +258,7 @@ int vmw_bo_pin_in_start_of_vram(struct vmw_private
*dev_priv,
ret = ttm_bo_validate(bo, &placement, &ctx);
/* For some reason we didn't end up at the start of vram */
- WARN_ON(ret == 0 && bo->offset != 0);
+ WARN_ON(ret == 0 && (bo->mem.start << PAGE_SHIFT) != 0);
if (!ret)
vmw_bo_pin_reserved(buf, true);
@@ -317,7 +317,7 @@ void vmw_bo_get_guest_ptr(const struct ttm_buffer_object
*bo,
{
if (bo->mem.mem_type == TTM_PL_VRAM) {
ptr->gmrId = SVGA_GMR_FRAMEBUFFER;
- ptr->offset = bo->offset;
+ ptr->offset = bo->mem.start << PAGE_SHIFT;
} else {
ptr->gmrId = bo->mem.start;
ptr->offset = 0;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index ff86d49dc5e8..e8a3351f35cf 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -3305,7 +3305,7 @@ static void vmw_apply_relocations(struct vmw_sw_context
*sw_context)
bo = &reloc->vbo->base;
switch (bo->mem.mem_type) {
case TTM_PL_VRAM:
- reloc->location->offset += bo->offset;
+ reloc->location->offset += bo->mem.start << PAGE_SHIFT;
reloc->location->gmrId = SVGA_GMR_FRAMEBUFFER;
break;
case VMW_PL_GMR:
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
index e5252ef3812f..1cdc445b24c3 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
@@ -612,7 +612,7 @@ static int vmw_fifo_emit_dummy_legacy_query(struct
vmw_private *dev_priv,
if (bo->mem.mem_type == TTM_PL_VRAM) {
cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
- cmd->body.guestResult.offset = bo->offset;
+ cmd->body.guestResult.offset = bo->mem.start << PAGE_SHIFT;
} else {
cmd->body.guestResult.gmrId = bo->mem.start;
cmd->body.guestResult.offset = 0;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
index d8ea3dd10af0..1e69c013b47f 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
@@ -755,7 +755,6 @@ static int vmw_init_mem_type(struct ttm_bo_device *bdev,
uint32_t type,
case TTM_PL_VRAM:
/* "On-card" video ram */
man->func = &ttm_bo_manager_func;
- man->gpu_offset = 0;
man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_MAPPABLE;
man->available_caching = TTM_PL_FLAG_CACHED;
man->default_caching = TTM_PL_FLAG_CACHED;
@@ -768,7 +767,6 @@ static int vmw_init_mem_type(struct ttm_bo_device *bdev,
uint32_t type,
* slots as well as the bo size.
*/
man->func = &vmw_gmrid_manager_func;
- man->gpu_offset = 0;
man->flags = TTM_MEMTYPE_FLAG_CMA | TTM_MEMTYPE_FLAG_MAPPABLE;
man->available_caching = TTM_PL_FLAG_CACHED;
man->default_caching = TTM_PL_FLAG_CACHED;
--
2.25.0
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[RFC PATCH 4/6] drm/nouveau: don't use ttm bo->offset
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/nouveau/dispnv04/crtc.c | 6 +++---
drivers/gpu/drm/nouveau/dispnv04/disp.c | 2 +-
drivers/gpu/drm/nouveau/dispnv04/overlay.c | 6 +++---
drivers/gpu/drm/nouveau/dispnv50/base507c.c | 2 +-
drivers/gpu/drm/nouveau/dispnv50/core507d.c | 2 +-
drivers/gpu/drm/nouveau/dispnv50/ovly507e.c | 2 +-
drivers/gpu/drm/nouveau/dispnv50/wndw.c | 2 +-
drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_abi16.c | 8
drivers/gpu/drm/nouveau/nouveau_bo.c| 1 +
drivers/gpu/drm/nouveau/nouveau_bo.h| 3 +++
drivers/gpu/drm/nouveau/nouveau_chan.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_fbcon.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_gem.c | 10 +-
14 files changed, 27 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c
b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
index 37c50ea8f847..18a06cf03fa1 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
@@ -845,7 +845,7 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
fb = nouveau_framebuffer(crtc->primary->fb);
}
- nv_crtc->fb.offset = fb->nvbo->bo.offset;
+ nv_crtc->fb.offset = fb->nvbo->offset;
if (nv_crtc->lut.depth != drm_fb->format->depth) {
nv_crtc->lut.depth = drm_fb->format->depth;
@@ -1013,7 +1013,7 @@ nv04_crtc_cursor_set(struct drm_crtc *crtc, struct
drm_file *file_priv,
nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
nouveau_bo_unmap(cursor);
- nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset;
+ nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->offset;
nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
nv_crtc->cursor.show(nv_crtc, true);
out:
@@ -1191,7 +1191,7 @@ nv04_crtc_page_flip(struct drm_crtc *crtc, struct
drm_framebuffer *fb,
/* Initialize a page flip struct */
*s = (struct nv04_page_flip_state)
{ { }, event, crtc, fb->format->cpp[0] * 8, fb->pitches[0],
- new_bo->bo.offset };
+ new_bo->offset };
/* Keep vblanks on during flip, for the target crtc of this flip */
drm_crtc_vblank_get(crtc);
diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.c
b/drivers/gpu/drm/nouveau/dispnv04/disp.c
index 44ee82d0c9b6..89a4ddfcc55f 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/disp.c
@@ -151,7 +151,7 @@ nv04_display_init(struct drm_device *dev, bool resume, bool
runtime)
continue;
if (nv_crtc->cursor.set_offset)
- nv_crtc->cursor.set_offset(nv_crtc,
nv_crtc->cursor.nvbo->bo.offset);
+ nv_crtc->cursor.set_offset(nv_crtc,
nv_crtc->cursor.nvbo->offset);
nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
nv_crtc->cursor_saved_y);
}
diff --git a/drivers/gpu/drm/nouveau/dispnv04/overlay.c
b/drivers/gpu/drm/nouveau/dispnv04/overlay.c
index a3a0a73ae8ab..9529bd9053e7 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/overlay.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/overlay.c
@@ -150,7 +150,7 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc
*crtc,
nvif_mask(dev, NV_PCRTC_ENGINE_CTRL + soff2, NV_CRTC_FSEL_OVERLAY, 0);
nvif_wr32(dev, NV_PVIDEO_BASE(flip), 0);
- nvif_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nv_fb->nvbo->bo.offset);
+ nvif_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nv_fb->nvbo->offset);
nvif_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 | src_w);
nvif_wr32(dev, NV_PVIDEO_POINT_IN(flip), src_y << 16 | src_x);
nvif_wr32(dev, NV_PVIDEO_DS_DX(flip), (src_w << 20) / crtc_w);
@@ -172,7 +172,7 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc
*crtc,
if (format & NV_PVIDEO_FORMAT_PLANAR) {
nvif_wr32(dev, NV_PVIDEO_UVPLANE_BASE(flip), 0);
nvif_wr32(dev, NV_PVIDEO_UVPLANE_OFFSET_BUFF(flip),
- nv_fb->nvbo->bo.offset + fb->offsets[1]);
+ nv_fb->nvbo->offset + fb->offsets[1]);
}
nvif_wr32(dev, NV_PVIDEO_FORMAT(flip), format | fb->pitches[0]);
nvif_wr32(dev, NV_PVIDEO_STOP, 0);
@@ -396,7 +396,7 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc
*crtc,
for (i = 0; i < 2; i++) {
nvif_wr32(dev, NV_PVIDEO_BUFF0_START_ADDRESS + 4 * i,
- nv_fb->nvbo->bo.offset);
+ nv_fb->nvbo->offset);
nvif_wr32(dev, NV_PVIDEO_BUFF0_PITCH_LENGTH + 4 * i,
fb->pitches[0]);
nvif_wr32(dev, NV_PVIDEO_BUFF0_OFFSET + 4 * i, 0);
diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c
b/drivers/gpu/drm/nouveau/dispnv50/base507c.c
[RFC PATCH 6/6] drm/ttm: do not keep GPU dependent addresses
GPU address handling is device specific and should be handle by its device
driver.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/ttm/ttm_bo.c| 7 ---
include/drm/ttm/ttm_bo_api.h| 2 --
include/drm/ttm/ttm_bo_driver.h | 1 -
3 files changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 229205e499db..2ccfebc3c9a2 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -85,7 +85,6 @@ static void ttm_mem_type_debug(struct ttm_bo_device *bdev,
struct drm_printer *p
drm_printf(p, "has_type: %d\n", man->has_type);
drm_printf(p, "use_type: %d\n", man->use_type);
drm_printf(p, "flags: 0x%08X\n", man->flags);
- drm_printf(p, "gpu_offset: 0x%08llX\n", man->gpu_offset);
drm_printf(p, "size: %llu\n", man->size);
drm_printf(p, "available_caching: 0x%08X\n",
man->available_caching);
drm_printf(p, "default_caching: 0x%08X\n", man->default_caching);
@@ -382,12 +381,6 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object
*bo,
bo->evicted = false;
}
- if (bo->mem.mm_node)
- bo->offset = (bo->mem.start << PAGE_SHIFT) +
- bdev->man[bo->mem.mem_type].gpu_offset;
- else
- bo->offset = 0;
-
ctx->bytes_moved += bo->num_pages << PAGE_SHIFT;
return 0;
diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h
index 65e399d280f7..3cf8bb82c899 100644
--- a/include/drm/ttm/ttm_bo_api.h
+++ b/include/drm/ttm/ttm_bo_api.h
@@ -219,8 +219,6 @@ struct ttm_buffer_object {
* either of these locks held.
*/
- uint64_t offset; /* GPU address space is independent of CPU word size */
-
struct sg_table *sg;
struct mutex wu_mutex;
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index cac7a8a0825a..302b0aaf8d13 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -177,7 +177,6 @@ struct ttm_mem_type_manager {
bool has_type;
bool use_type;
uint32_t flags;
- uint64_t gpu_offset; /* GPU address space is independent of CPU word
size */
uint64_t size;
uint32_t available_caching;
uint32_t default_caching;
--
2.25.0
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Re: [PATCH 1/1] Support LVDS output on Allwinner A20
On Thu, Feb 13, 2020 at 10:24:33AM +0100, Maxime Ripard wrote: > > > do you have a board when you have been able to test it? > > > > Yes, I have the hardware (Cubieboard 2) at hand, but I cannot change the > > any physical connections on it. FWIW, it is https://openvario.org, the > > device we are (painfully) trying to upgrade from old kernel-3.4 with > > proprietary mali drivers to contemporary software. > > What painpoints do you have? So, even though proprietary mali drivers worked well for us, they seem to hold us back to old kernel-3.4, and it started to get harder to avoid various compatibility issues with newer software. Since there seemed to be a good progress with OSS lima driver lately, we decided to try to replace mali with lima. And that naturally pulled to switch to DRM/KMS. The first painpoint is this LVDS support problem: after a week of trial and error, I discovered that support was simply not there. But it seemed that not that much was actually missing and after couple of evenings deep into debugging, here we are. Another one is the screen rotation: the device is installed into the glider' instrument panel, and some pilots prefer it in portrait orientation. Under old mali setup, all that (seemingly) was required was setting "fbcon=rotate:n" boot arg, and both linux console and graphical app (https://xcsoar.org/) rotated "automagically". With new DRM/KMS setup, only console is rotated, all graphical apps seem to see the screen in its "natural" landscape orientation. Do you know if there is any way to leverage DMS/KMS infrastructure to make screen appear rotated for userspace apps (writing to /sys/class/graphics/fb0/rotate didn't work)? There's of course a plan B to teach the app to rotate its output, but that leads to problem number 3. And the 3rd outstanding problem is that app doesn't really work under lima module and lima mesa driver. It starts, but renders a black window. I haven't dug deeply into this yet, but it is possible that some opengl API isn't supported in OSS drivers yet (even though app only renders 2d graphics). Hopefully that wasn't too much complaining for you :) If you have any insight on possible causes or attack vectors on any of these, that would help a lot. Also, please feel free to correct any of false assumptions I make above, I'm happy to learn more about this. -- Andrey Lebedev aka -.- . -.. -.. . .-. Software engineer Homepage: http://lebedev.lt/ ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm/atomic-helper: fix kerneldoc
Just a tiny copypasta mistake.
Fixes: 751465913f04 ("drm/bridge: Add a drm_bridge_state object")
Cc: Boris Brezillon
Cc: Neil Armstrong
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_atomic_state_helper.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
b/drivers/gpu/drm/drm_atomic_state_helper.c
index 33141d2cdad4..8fce6a115dfe 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -635,7 +635,6 @@ EXPORT_SYMBOL(__drm_atomic_helper_bridge_reset);
* drm_atomic_helper_bridge_reset() - Allocate and initialize a bridge state
* to its default
* @bridge: the bridge this state refers to
- * @state: bridge state to initialize
*
* Allocates the bridge state and initializes it to default values. This helper
* is meant to be used as a bridge &drm_bridge_funcs.atomic_reset hook for
--
2.24.1
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Re: [PATCH] drm/pl111: Support Integrator IM-PD1 module
On Thu, Feb 13, 2020 at 3:49 PM Daniel Vetter wrote: > Looking around in the arm/mach-integrator code this seems to match > roughly :-) I noticed there's also two more outputs for two panels, > but not here. Do we not care about these anymore? I actually have that hardware too (Integrator/PP2) and it is trivial to support using the existing code, one can just define the panel in the device tree. It might need some new define in panel-simple.c as well. Yours, Linus Walleij ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2] drm/i915: Disable -Wtautological-constant-out-of-range-compare
On Wed, Feb 12, 2020 at 9:17 AM Michel Dänzer wrote: > > On 2020-02-12 6:07 p.m., Nathan Chancellor wrote: > > On Wed, Feb 12, 2020 at 09:52:52AM +0100, Michel Dänzer wrote: > >> On 2020-02-11 9:39 p.m., Nathan Chancellor wrote: > >>> On Tue, Feb 11, 2020 at 10:41:48AM +0100, Michel Dänzer wrote: > On 2020-02-11 7:13 a.m., Nathan Chancellor wrote: > > A recent commit in clang added -Wtautological-compare to -Wall, which is > > enabled for i915 so we see the following warning: > > > > ../drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1485:22: warning: > > result of comparison of constant 576460752303423487 with expression of > > type 'unsigned int' is always false > > [-Wtautological-constant-out-of-range-compare] > > if (unlikely(remain > N_RELOC(ULONG_MAX))) > > ^ > > > > This warning only happens on x86_64 but that check is relevant for > > 32-bit x86 so we cannot remove it. > > That's suprising. AFAICT N_RELOC(ULONG_MAX) works out to the same value > in both cases, and remain is a 32-bit value in both cases. How can it be > larger than N_RELOC(ULONG_MAX) on 32-bit (but not on 64-bit)? > > >>> > >>> Hi Michel, > >>> > >>> Can't this condition be true when UINT_MAX == ULONG_MAX? > >> > >> Oh, right, I think I was wrongly thinking long had 64 bits even on 32-bit. > >> > >> > >> Anyway, this suggests a possible better solution: > >> > >> #if UINT_MAX == ULONG_MAX > >> if (unlikely(remain > N_RELOC(ULONG_MAX))) > >> return -EINVAL; > >> #endif > >> > >> > >> Or if that can't be used for some reason, something like > >> > >> if (unlikely((unsigned long)remain > N_RELOC(ULONG_MAX))) > >> return -EINVAL; > >> > >> should silence the warning. > > > > I do like this one better than the former. > > FWIW, one downside of this one compared to all alternatives (presumably) > is that it might end up generating actual code even on 64-bit, which > always ends up skipping the return. The warning is pointing out that the conditional is always false, which is correct on 64b. The check is only active for 32b. https://godbolt.org/z/oQrgT_ The cast silences the warning for 64b. (Note that GCC and Clang also generate precisely the same instruction sequences in my example, just GCC doesn't warn on such tautologies). -- Thanks, ~Nick Desaulniers ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5] dt-bindings: display: renesas: du: Document optional reset properties
Document the optional properties for describing module resets, to support resetting display channels on R-Car Gen2 and Gen3. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Acked-by: Rob Herring --- Who's taking this kind of patches? V1 was submmitted in March 2017. v5: - Rebase on top of renesas,cmms and renesas,vsps patches, v4: - Use "All but R8A7779" instead of "R8A779[0123456]", to reduce future churn, v3: - Add Acked-by, - Drop LVDS resets, as LVDS is now covered by a separate binding, - Update the example. v2: - s/phandles/phandle/. --- .../devicetree/bindings/display/renesas,du.txt | 10 ++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt index eb4ae41fe41f83c7..51cd4d1627703a15 100644 --- a/Documentation/devicetree/bindings/display/renesas,du.txt +++ b/Documentation/devicetree/bindings/display/renesas,du.txt @@ -50,6 +50,14 @@ Required Properties: VSP instance that serves the DU channel, and the channel index identifies the LIF instance in that VSP. +Optional properties: + - resets: A list of phandle + reset-specifier pairs, one for each entry in +the reset-names property. + - reset-names: Names of the resets. This property is model-dependent. +- All but R8A7779 use one reset for a group of one or more successive + channels. The resets must be named "du.x" with "x" being the numerical + index of the lowest channel in the group. + Required nodes: The connections to the DU output video ports are modeled using the OF graph @@ -96,6 +104,8 @@ Example: R8A7795 (R-Car H3) ES2.0 DU <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>; clock-names = "du.0", "du.1", "du.2", "du.3"; + resets = <&cpg 724>, <&cpg 722>; + reset-names = "du.0", "du.2"; renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/i915: Cast remain to unsigned long in eb_relocate_vma
Quoting Jani Nikula (2020-02-14 06:36:15) > On Thu, 13 Feb 2020, Nathan Chancellor wrote: > > A recent commit in clang added -Wtautological-compare to -Wall, which is > > enabled for i915 after -Wtautological-compare is disabled for the rest > > of the kernel so we see the following warning on x86_64: > > > > ../drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1433:22: warning: > > result of comparison of constant 576460752303423487 with expression of > > type 'unsigned int' is always false > > [-Wtautological-constant-out-of-range-compare] > > if (unlikely(remain > N_RELOC(ULONG_MAX))) > > ^ > > ../include/linux/compiler.h:78:42: note: expanded from macro 'unlikely' > > # define unlikely(x)__builtin_expect(!!(x), 0) > > ^ > > 1 warning generated. > > > > It is not wrong in the case where ULONG_MAX > UINT_MAX but it does not > > account for the case where this file is built for 32-bit x86, where > > ULONG_MAX == UINT_MAX and this check is still relevant. > > > > Cast remain to unsigned long, which keeps the generated code the same > > (verified with clang-11 on x86_64 and GCC 9.2.0 on x86 and x86_64) and > > the warning is silenced so we can catch more potential issues in the > > future. > > > > Link: https://github.com/ClangBuiltLinux/linux/issues/778 > > Suggested-by: Michel Dänzer > > Signed-off-by: Nathan Chancellor > > Works for me as a workaround, But the whole point was that the compiler could see that it was impossible and not emit the code. Doesn't this break that? -Chris ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/mediatek: fix race condition for HDMI jack status reporting
Hi, Tzung-Bi: On Fri, 2020-02-14 at 15:35 +0800, Tzung-Bi Shih wrote: > On Fri, Feb 14, 2020 at 3:07 PM CK Hu wrote: > > I think sound driver could be removed for some reason, and fn should be > > set to NULL before sound driver removed. In this case, codec_dev != NULL > > and fn == NULL. > > No..if you see sound/soc/codecs/hdmi-codec.c, plugged_cb is statically > allocated. It looks like that even though sound driver is removed, hdmi driver would still callback to sound core. This is so weird. After sound driver is removed, hdmi driver would callback with codec_dev which is invalid. I think this may cause some problem. Regards, CK ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/virtio: fix error check
On Fri, 14 Feb 2020 09:01:00 +0100
Gerd Hoffmann wrote:
> The >= compare op must happen in cpu byte order, doing it in
> little endian fails on big endian machines like s390.
>
> Reported-by: Sebastian Mitterle
> Signed-off-by: Gerd Hoffmann
> ---
> drivers/gpu/drm/virtio/virtgpu_vq.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/virtio/virtgpu_vq.c
> b/drivers/gpu/drm/virtio/virtgpu_vq.c
> index cfe9c54f87a3..67caecde623e 100644
> --- a/drivers/gpu/drm/virtio/virtgpu_vq.c
> +++ b/drivers/gpu/drm/virtio/virtgpu_vq.c
> @@ -222,7 +222,7 @@ void virtio_gpu_dequeue_ctrl_func(struct work_struct
> *work)
> trace_virtio_gpu_cmd_response(vgdev->ctrlq.vq, resp);
>
> if (resp->type != cpu_to_le32(VIRTIO_GPU_RESP_OK_NODATA)) {
> - if (resp->type >=
> cpu_to_le32(VIRTIO_GPU_RESP_ERR_UNSPEC)) {
> + if (le32_to_cpu(resp->type) >=
> VIRTIO_GPU_RESP_ERR_UNSPEC) {
> struct virtio_gpu_ctrl_hdr *cmd;
> cmd = virtio_gpu_vbuf_ctrl_hdr(entry);
> DRM_ERROR_RATELIMITED("response 0x%x (command
> 0x%x)\n",
Reviewed-by: Cornelia Huck
Endianness continues to be fun.
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[PATCH] drm/print: Delete a few unused shouting macros
We want to go over to the new lowercase ones, encourage that a bit
more.
Cc: Jani Nikula
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_managed.c | 21 +
include/drm/drm_print.h | 26 --
2 files changed, 21 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/drm_managed.c b/drivers/gpu/drm/drm_managed.c
index ea49071b16ee..7d4827b79806 100644
--- a/drivers/gpu/drm/drm_managed.c
+++ b/drivers/gpu/drm/drm_managed.c
@@ -38,4 +38,25 @@ struct drmres {
u8 __aligned(ARCH_KMALLOC_MINALIGN) data[];
};
+static __always_inline struct drmres * alloc_dr(drmres_release_t release,
+ size_t size, gfp_t gfp, int nid)
+{
+ size_t tot_size;
+ struct drmres *dr;
+
+ /* We must catch any near-SIZE_MAX cases that could overflow. */
+ if (unlikely(check_add_overflow(sizeof(*dr), size, &tot_size)))
+ return NULL;
+
+ dr = kmalloc_node_track_caller(tot_size, gfp, nid);
+ if (unlikely(!dr))
+ return NULL;
+
+ memset(dr, 0, offsetof(struct drmres, data));
+
+ INIT_LIST_HEAD(&dr->node.entry);
+ dr->node.release = release;
+ return dr;
+}
+
diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
index 894a0b9437e2..fd6ba2532f50 100644
--- a/include/drm/drm_print.h
+++ b/include/drm/drm_print.h
@@ -382,14 +382,6 @@ void drm_dev_dbg(const struct device *dev, enum
drm_debug_category category,
drm_dev_dbg(dev, DRM_UT_DRIVER, fmt, ##__VA_ARGS__)
#define DRM_DEV_DEBUG_KMS(dev, fmt, ...) \
drm_dev_dbg(dev, DRM_UT_KMS, fmt, ##__VA_ARGS__)
-#define DRM_DEV_DEBUG_PRIME(dev, fmt, ...) \
- drm_dev_dbg(dev, DRM_UT_PRIME, fmt, ##__VA_ARGS__)
-#define DRM_DEV_DEBUG_ATOMIC(dev, fmt, ...)\
- drm_dev_dbg(dev, DRM_UT_ATOMIC, fmt, ##__VA_ARGS__)
-#define DRM_DEV_DEBUG_VBL(dev, fmt, ...) \
- drm_dev_dbg(dev, DRM_UT_VBL, fmt, ##__VA_ARGS__)
-#defineDRM_DEV_DEBUG_DP(dev, fmt, ...)
\
- drm_dev_dbg(dev, DRM_UT_DP, fmt, ## __VA_ARGS__)
#define _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, category, fmt, ...) \
({ \
@@ -406,18 +398,9 @@ void drm_dev_dbg(const struct device *dev, enum
drm_debug_category category,
* @dev: device pointer
* @fmt: printf() like format string.
*/
-#define DRM_DEV_DEBUG_RATELIMITED(dev, fmt, ...) \
- _DEV_DRM_DEFINE_DEBUG_RATELIMITED(dev, DRM_UT_CORE, \
- fmt, ##__VA_ARGS__)
-#define DRM_DEV_DEBUG_DRIVER_RATELIMITED(dev, fmt, ...)
\
- _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, DRM_UT_DRIVER, \
- fmt, ##__VA_ARGS__)
#define DRM_DEV_DEBUG_KMS_RATELIMITED(dev, fmt, ...) \
_DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, DRM_UT_KMS, \
fmt, ##__VA_ARGS__)
-#define DRM_DEV_DEBUG_PRIME_RATELIMITED(dev, fmt, ...) \
- _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, DRM_UT_PRIME,\
- fmt, ##__VA_ARGS__)
/*
* struct drm_device based logging
@@ -541,18 +524,9 @@ void __drm_err(const char *format, ...);
__drm_dbg(DRM_UT_DP, fmt, ## __VA_ARGS__)
-#define DRM_DEBUG_RATELIMITED(fmt, ...)
\
- DRM_DEV_DEBUG_RATELIMITED(NULL, fmt, ##__VA_ARGS__)
-
-#define DRM_DEBUG_DRIVER_RATELIMITED(fmt, ...) \
- DRM_DEV_DEBUG_DRIVER_RATELIMITED(NULL, fmt, ##__VA_ARGS__)
-
#define DRM_DEBUG_KMS_RATELIMITED(fmt, ...)\
DRM_DEV_DEBUG_KMS_RATELIMITED(NULL, fmt, ##__VA_ARGS__)
-#define DRM_DEBUG_PRIME_RATELIMITED(fmt, ...) \
- DRM_DEV_DEBUG_PRIME_RATELIMITED(NULL, fmt, ##__VA_ARGS__)
-
/*
* struct drm_device based WARNs
*
--
2.24.1
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Re: [RFC PATCH 5/6] drm/qxl: don't use ttm bo->offset
> - if (bo->mem.mm_node) > - bo->offset = (bo->mem.start << PAGE_SHIFT) + > - bdev->man[bo->mem.mem_type].gpu_offset; > - else > - bo->offset = 0; > - > > > My assumption is > > (bo->tbo.offset - slot->gpu_offset + offset) == (bo->tbo.mem.start << > PAGE_SHIFT) + bdev->man[bo->mem.mem_type].gpu_offset - slot->gpu_offset + > offset) > > -> == (bo->tbo.mem.start << PAGE_SHIFT) + offset That looks better. > and we loose slot->gpu_offset so I thought it should be > > ((bo->tbo.mem.start << PAGE_SHIFT) + slot->gpu_offset + offset); No. The addressing scheme used by qxl is the slot in the high bits and the offset within the slot in the low bits. The qxl device has two pci memory bars, the driver creates a slot for each of them, for ttm they are VRAM and PRIV. So maybe we don't need gpu_offset at all. Not fully sure how driver and ttm interact here. cheers, Gerd ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/print: Delete a few unused shouting macros
On Fri, 14 Feb 2020, Daniel Vetter wrote:
> We want to go over to the new lowercase ones, encourage that a bit
> more.
>
> Cc: Jani Nikula
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/drm_managed.c | 21 +
Oops?
> include/drm/drm_print.h | 26 --
Acked-by: Jani Nikula
for this file.
> 2 files changed, 21 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_managed.c b/drivers/gpu/drm/drm_managed.c
> index ea49071b16ee..7d4827b79806 100644
> --- a/drivers/gpu/drm/drm_managed.c
> +++ b/drivers/gpu/drm/drm_managed.c
> @@ -38,4 +38,25 @@ struct drmres {
> u8 __aligned(ARCH_KMALLOC_MINALIGN) data[];
> };
>
> +static __always_inline struct drmres * alloc_dr(drmres_release_t release,
> + size_t size, gfp_t gfp, int nid)
> +{
> + size_t tot_size;
> + struct drmres *dr;
> +
> + /* We must catch any near-SIZE_MAX cases that could overflow. */
> + if (unlikely(check_add_overflow(sizeof(*dr), size, &tot_size)))
> + return NULL;
> +
> + dr = kmalloc_node_track_caller(tot_size, gfp, nid);
> + if (unlikely(!dr))
> + return NULL;
> +
> + memset(dr, 0, offsetof(struct drmres, data));
> +
> + INIT_LIST_HEAD(&dr->node.entry);
> + dr->node.release = release;
> + return dr;
> +}
> +
>
> diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
> index 894a0b9437e2..fd6ba2532f50 100644
> --- a/include/drm/drm_print.h
> +++ b/include/drm/drm_print.h
> @@ -382,14 +382,6 @@ void drm_dev_dbg(const struct device *dev, enum
> drm_debug_category category,
> drm_dev_dbg(dev, DRM_UT_DRIVER, fmt, ##__VA_ARGS__)
> #define DRM_DEV_DEBUG_KMS(dev, fmt, ...) \
> drm_dev_dbg(dev, DRM_UT_KMS, fmt, ##__VA_ARGS__)
> -#define DRM_DEV_DEBUG_PRIME(dev, fmt, ...) \
> - drm_dev_dbg(dev, DRM_UT_PRIME, fmt, ##__VA_ARGS__)
> -#define DRM_DEV_DEBUG_ATOMIC(dev, fmt, ...) \
> - drm_dev_dbg(dev, DRM_UT_ATOMIC, fmt, ##__VA_ARGS__)
> -#define DRM_DEV_DEBUG_VBL(dev, fmt, ...) \
> - drm_dev_dbg(dev, DRM_UT_VBL, fmt, ##__VA_ARGS__)
> -#define DRM_DEV_DEBUG_DP(dev, fmt, ...)
> \
> - drm_dev_dbg(dev, DRM_UT_DP, fmt, ## __VA_ARGS__)
>
> #define _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, category, fmt, ...) \
> ({ \
> @@ -406,18 +398,9 @@ void drm_dev_dbg(const struct device *dev, enum
> drm_debug_category category,
> * @dev: device pointer
> * @fmt: printf() like format string.
> */
> -#define DRM_DEV_DEBUG_RATELIMITED(dev, fmt, ...) \
> - _DEV_DRM_DEFINE_DEBUG_RATELIMITED(dev, DRM_UT_CORE, \
> - fmt, ##__VA_ARGS__)
> -#define DRM_DEV_DEBUG_DRIVER_RATELIMITED(dev, fmt, ...)
> \
> - _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, DRM_UT_DRIVER, \
> - fmt, ##__VA_ARGS__)
> #define DRM_DEV_DEBUG_KMS_RATELIMITED(dev, fmt, ...) \
> _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, DRM_UT_KMS, \
> fmt, ##__VA_ARGS__)
> -#define DRM_DEV_DEBUG_PRIME_RATELIMITED(dev, fmt, ...)
> \
> - _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, DRM_UT_PRIME,\
> - fmt, ##__VA_ARGS__)
>
> /*
> * struct drm_device based logging
> @@ -541,18 +524,9 @@ void __drm_err(const char *format, ...);
> __drm_dbg(DRM_UT_DP, fmt, ## __VA_ARGS__)
>
>
> -#define DRM_DEBUG_RATELIMITED(fmt, ...)
> \
> - DRM_DEV_DEBUG_RATELIMITED(NULL, fmt, ##__VA_ARGS__)
> -
> -#define DRM_DEBUG_DRIVER_RATELIMITED(fmt, ...)
> \
> - DRM_DEV_DEBUG_DRIVER_RATELIMITED(NULL, fmt, ##__VA_ARGS__)
> -
> #define DRM_DEBUG_KMS_RATELIMITED(fmt, ...) \
> DRM_DEV_DEBUG_KMS_RATELIMITED(NULL, fmt, ##__VA_ARGS__)
>
> -#define DRM_DEBUG_PRIME_RATELIMITED(fmt, ...)
> \
> - DRM_DEV_DEBUG_PRIME_RATELIMITED(NULL, fmt, ##__VA_ARGS__)
> -
> /*
> * struct drm_device based WARNs
> *
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [RFC PATCH 0/6] do not store GPU address in TTM
Hi Am 13.02.20 um 13:01 schrieb Nirmoy Das: > With this patch series I am trying to remove GPU address dependency in > TTM and moving GPU address calculation to individual drm drivers. > This is required[1] to continue the work started by Brian Welty to create > struct drm_mem_region which can be leverage by DRM cgroup controller to > manage memory > limits. > > > I have only manage to test amdgpu driver as I only have GPU for that. > I might be doing something really stupid while calculeting gpu offset for > some of the drivers so please be patient and let me know how can I improve > that. > > [1] > https://www.mail-archive.com/dri-devel@lists.freedesktop.org/msg272238.html > > Nirmoy Das (6): > drm/amdgpu: move ttm bo->offset to amdgpu_bo > drm/radeon: don't use ttm bo->offset > drm/vmwgfx: don't use ttm bo->offset > drm/nouveau: don't use ttm bo->offset > drm/qxl: don't use ttm bo->offset > drm/ttm: do not keep GPU dependent addresses I think VRAM helpers are missing from this patchset. [1] You can use bochs in qemu to test them. Best regards Thomas [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/drm_gem_vram_helper.c?h=v5.6-rc1#n217 > > drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 22 ++-- > drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 + > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 29 - > drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 + > drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 4 +-- > drivers/gpu/drm/nouveau/dispnv04/crtc.c | 6 ++--- > drivers/gpu/drm/nouveau/dispnv04/disp.c | 2 +- > drivers/gpu/drm/nouveau/dispnv04/overlay.c | 6 ++--- > drivers/gpu/drm/nouveau/dispnv50/base507c.c | 2 +- > drivers/gpu/drm/nouveau/dispnv50/core507d.c | 2 +- > drivers/gpu/drm/nouveau/dispnv50/ovly507e.c | 2 +- > drivers/gpu/drm/nouveau/dispnv50/wndw.c | 2 +- > drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 2 +- > drivers/gpu/drm/nouveau/nouveau_abi16.c | 8 +++--- > drivers/gpu/drm/nouveau/nouveau_bo.c| 1 + > drivers/gpu/drm/nouveau/nouveau_bo.h| 3 +++ > drivers/gpu/drm/nouveau/nouveau_chan.c | 2 +- > drivers/gpu/drm/nouveau/nouveau_fbcon.c | 2 +- > drivers/gpu/drm/nouveau/nouveau_gem.c | 10 +++ > drivers/gpu/drm/qxl/qxl_drv.h | 6 ++--- > drivers/gpu/drm/qxl/qxl_kms.c | 3 +++ > drivers/gpu/drm/qxl/qxl_object.h| 5 > drivers/gpu/drm/qxl/qxl_ttm.c | 9 --- > drivers/gpu/drm/radeon/radeon.h | 1 + > drivers/gpu/drm/radeon/radeon_object.h | 16 +++- > drivers/gpu/drm/radeon/radeon_ttm.c | 4 +-- > drivers/gpu/drm/ttm/ttm_bo.c| 7 - > drivers/gpu/drm/vmwgfx/vmwgfx_bo.c | 4 +-- > drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 2 +- > drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c| 2 +- > drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 2 -- > include/drm/ttm/ttm_bo_api.h| 2 -- > include/drm/ttm/ttm_bo_driver.h | 1 - > 33 files changed, 99 insertions(+), 72 deletions(-) > > -- > 2.25.0 > > ___ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel > -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Felix Imendörffer signature.asc Description: OpenPGP digital signature ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v5] dt-bindings: display: renesas: du: Document optional reset properties
Hi Geert, On 14/02/2020 08:26, Geert Uytterhoeven wrote: > Document the optional properties for describing module resets, to > support resetting display channels on R-Car Gen2 and Gen3. > > Signed-off-by: Geert Uytterhoeven > Acked-by: Laurent Pinchart > Acked-by: Rob Herring Reviewed-by: Kieran Bingham > --- > Who's taking this kind of patches? > V1 was submmitted in March 2017. Hrm ... presumably through the DRM subsystem trees? Or just for Laurent to pick up ... -- KB > > v5: > - Rebase on top of renesas,cmms and renesas,vsps patches, > > v4: > - Use "All but R8A7779" instead of "R8A779[0123456]", to reduce future > churn, > > v3: > - Add Acked-by, > - Drop LVDS resets, as LVDS is now covered by a separate binding, > - Update the example. > > v2: > - s/phandles/phandle/. > --- > .../devicetree/bindings/display/renesas,du.txt | 10 ++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt > b/Documentation/devicetree/bindings/display/renesas,du.txt > index eb4ae41fe41f83c7..51cd4d1627703a15 100644 > --- a/Documentation/devicetree/bindings/display/renesas,du.txt > +++ b/Documentation/devicetree/bindings/display/renesas,du.txt > @@ -50,6 +50,14 @@ Required Properties: > VSP instance that serves the DU channel, and the channel index identifies > the LIF instance in that VSP. > > +Optional properties: > + - resets: A list of phandle + reset-specifier pairs, one for each entry in > +the reset-names property. > + - reset-names: Names of the resets. This property is model-dependent. > +- All but R8A7779 use one reset for a group of one or more successive > + channels. The resets must be named "du.x" with "x" being the numerical > + index of the lowest channel in the group. > + > Required nodes: > > The connections to the DU output video ports are modeled using the OF graph > @@ -96,6 +104,8 @@ Example: R8A7795 (R-Car H3) ES2.0 DU ><&cpg CPG_MOD 722>, ><&cpg CPG_MOD 721>; > clock-names = "du.0", "du.1", "du.2", "du.3"; > + resets = <&cpg 724>, <&cpg 722>; > + reset-names = "du.0", "du.2"; > renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; > renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; > > ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [RFC PATCH 1/3] KVM: vmx: rewrite the comment in vmx_get_mt_mask
On 13/02/20 22:30, Chia-I Wu wrote:
> Better reflect the structure of the code and metion why we could not
> always honor the guest.
>
> Signed-off-by: Chia-I Wu
> Cc: Gurchetan Singh
> Cc: Gerd Hoffmann
> ---
> arch/x86/kvm/vmx/vmx.c | 27 +--
> 1 file changed, 17 insertions(+), 10 deletions(-)
>
> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> index 3be25ecae145..266ef87042da 100644
> --- a/arch/x86/kvm/vmx/vmx.c
> +++ b/arch/x86/kvm/vmx/vmx.c
> @@ -6854,17 +6854,24 @@ static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu,
> gfn_t gfn, bool is_mmio)
> u8 cache;
> u64 ipat = 0;
>
> - /* For VT-d and EPT combination
> - * 1. MMIO: always map as UC
> - * 2. EPT with VT-d:
> - * a. VT-d without snooping control feature: can't guarantee the
> - * result, try to trust guest.
> - * b. VT-d with snooping control feature: snooping control feature of
> - * VT-d engine can guarantee the cache correctness. Just set it
> - * to WB to keep consistent with host. So the same as item 3.
> - * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
> - *consistent with host MTRR
> + /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
> + * memory aliases with conflicting memory types and sometimes MCEs.
> + * We have to be careful as to what are honored and when.
> + *
> + * For MMIO, guest CD/MTRR are ignored. The EPT memory type is set to
> + * UC. The effective memory type is UC or WC depending on guest PAT.
> + * This was historically the source of MCEs and we want to be
> + * conservative.
> + *
> + * When there is no need to deal with noncoherent DMA (e.g., no VT-d
> + * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored. The
> + * EPT memory type is set to WB. The effective memory type is forced
> + * WB.
> + *
> + * Otherwise, we trust guest. Guest CD/MTRR/PAT are all honored. The
> + * EPT memory type is used to emulate guest CD/MTRR.
>*/
> +
> if (is_mmio) {
> cache = MTRR_TYPE_UNCACHABLE;
> goto exit;
>
This is certainly an improvement, especially the part that points out
how guest PAT still allows MMIO to be handled as WC.
Thanks,
Paolo
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[PATCH resend 0/2] dts: keystone-k2g-evm: Display support
Resend because the earlier recipient list was wrong. Now that drm/tidss is queued for mainline, lets add display support for k2g-evm. There is no hurry since tidss is out only in v5.7, but it should not harm to have the dts changes in place before that. Jyri Sarha (2): ARM: dts: keystone-k2g: Add DSS node ARM: dts: keystone-k2g-evm: add HDMI video support arch/arm/boot/dts/keystone-k2g-evm.dts | 101 + arch/arm/boot/dts/keystone-k2g.dtsi| 22 ++ 2 files changed, 123 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH resend 2/2] ARM: dts: keystone-k2g-evm: add HDMI video support
Add DT nodes for HDMI video support for K2G EVM. The HDMI uses SiI9022
DPI as HDMI encoder. The DSS DPI is connected to SiI9022 HDMI
encoder's video input and encoder's output goes to HDMI connector.
Signed-off-by: Jyri Sarha
---
arch/arm/boot/dts/keystone-k2g-evm.dts | 101 +
1 file changed, 101 insertions(+)
diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts
b/arch/arm/boot/dts/keystone-k2g-evm.dts
index b7f10bf94576..db640bab8c1d 100644
--- a/arch/arm/boot/dts/keystone-k2g-evm.dts
+++ b/arch/arm/boot/dts/keystone-k2g-evm.dts
@@ -45,6 +45,19 @@
regulator-max-microvolt = <180>;
regulator-always-on;
};
+
+ hdmi: connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&sii9022_out>;
+ };
+ };
+ };
};
&k2g_pinctrl {
@@ -89,6 +102,13 @@
>;
};
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP |
MUX_MODE0)/* i2c1_scl.i2c1_scl */
+ K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP |
MUX_MODE0)/* i2c1_sda.i2c1_sda */
+ >;
+ };
+
ecap0_pins: ecap0_pins {
pinctrl-single,pins = <
K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4)
/* pr1_mdio_data.ecap0_in_apwm0_out */
@@ -160,6 +180,40 @@
K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* MDIO_DATA.MDIO_DATA */
>;
};
+
+ vout_pins: pinmux_vout_pins {
+ pinctrl-single,pins = <
+ K2G_CORE_IOPAD(0x1078) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata23.dssdata23 */
+ K2G_CORE_IOPAD(0x107c) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata22.dssdata22 */
+ K2G_CORE_IOPAD(0x1080) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata21.dssdata21 */
+ K2G_CORE_IOPAD(0x1084) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata20.dssdata20 */
+ K2G_CORE_IOPAD(0x1088) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata19.dssdata19 */
+ K2G_CORE_IOPAD(0x108c) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata18.dssdata18 */
+ K2G_CORE_IOPAD(0x1090) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata17.dssdata17 */
+ K2G_CORE_IOPAD(0x1094) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata16.dssdata16 */
+ K2G_CORE_IOPAD(0x1098) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata15.dssdata15 */
+ K2G_CORE_IOPAD(0x109c) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata14.dssdata14 */
+ K2G_CORE_IOPAD(0x10a0) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata13.dssdata13 */
+ K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata12.dssdata12 */
+ K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata11.dssdata11 */
+ K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata10.dssdata10 */
+ K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata9.dssdata9 */
+ K2G_CORE_IOPAD(0x10b4) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata8.dssdata8 */
+ K2G_CORE_IOPAD(0x10b8) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata7.dssdata7 */
+ K2G_CORE_IOPAD(0x10bc) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata6.dssdata6 */
+ K2G_CORE_IOPAD(0x10c0) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata5.dssdata5 */
+ K2G_CORE_IOPAD(0x10c4) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata4.dssdata4 */
+ K2G_CORE_IOPAD(0x10c8) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata3.dssdata3 */
+ K2G_CORE_IOPAD(0x10cc) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata2.dssdata2 */
+ K2G_CORE_IOPAD(0x10d0) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata1.dssdata1 */
+ K2G_CORE_IOPAD(0x10d4) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssdata0.dssdata0 */
+ K2G_CORE_IOPAD(0x10d8) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dssvsync.dssvsync */
+ K2G_CORE_IOPAD(0x10dc) (BUFFER_CLASS_B | PULL_DISABLE |
MUX_MODE0) /* dsshsync.dsshsync */
+ K2G_CORE_IOPAD(0x10e0) (BUFFER_CLAS
[PATCH resend 1/2] ARM: dts: keystone-k2g: Add DSS node
Add DT node for DSS. K2G has DSS version 6. Keystone family DSS are
somewhat different compered to the old OMAP family DSSes and the
binding looks different too.
Signed-off-by: Jyri Sarha
Signed-off-by: Tomi Valkeinen
Signed-off-by: Jyri Sarha
---
arch/arm/boot/dts/keystone-k2g.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi
b/arch/arm/boot/dts/keystone-k2g.dtsi
index 1c833105d6c5..08ba31780baa 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -324,6 +324,28 @@
clock-names = "gpio";
};
+ dss: dss@0254 {
+ compatible = "ti,k2g-dss";
+ reg = <0x0254 0x400>,
+ <0x0255 0x1000>,
+ <0x02557000 0x1000>,
+ <0x0255a800 0x100>,
+ <0x0255ac00 0x100>;
+ reg-names = "cfg", "common", "vid1", "ovr1", "vp1";
+ clocks =<&k2g_clks 0x2 0>,
+ <&k2g_clks 0x2 1>;
+ clock-names = "fck", "vp1";
+ interrupts = ;
+
+ power-domains = <&k2g_pds 0x2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ max-memory-bandwidth = <23000>;
+ };
+
edma0: edma@270 {
compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
reg = <0x0270 0x8000>;
--
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Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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Re: [PATCH v7 01/13] dt-bindings: arm: move mmsys description to display
On 14/02/2020 07:42, CK Hu wrote:
> Hi, Matthias:
>
> On Thu, 2020-02-13 at 21:19 +0100, matthias@kernel.org wrote:
>> From: Matthias Brugger
>>
>> The mmsys block provides registers and clocks for the display
>> subsystem. The binding description should therefore live together with
>> the rest of the display descriptions. Move it to display/mediatek.
>>
>
> Yes, for the upstreamed driver, only display (DRM) use mmsys clock. For
> some MDP patches [1] in progress, MDP also use mmsys clock. So we just
> consider what's upstreamed now?
I'm not sure if I understand you correctly. Are you proposing to keep the
binding description in arm/mediatek?
Regards,
Matthias
>
> [1] https://patchwork.kernel.org/patch/11140747/
>
> Regards,
> CK
>
>> Signed-off-by: Matthias Brugger
>>
>> ---
>>
>> Changes in v7:
>> - move the binding description
>>
>> Changes in v6: None
>> Changes in v5: None
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2: None
>>
>> .../bindings/{arm => display}/mediatek/mediatek,mmsys.txt | 0
>> 1 file changed, 0 insertions(+), 0 deletions(-)
>> rename Documentation/devicetree/bindings/{arm =>
>> display}/mediatek/mediatek,mmsys.txt (100%)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
>> b/Documentation/devicetree/bindings/display/mediatek/mediatek,mmsys.txt
>> similarity index 100%
>> rename from Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
>> rename to
>> Documentation/devicetree/bindings/display/mediatek/mediatek,mmsys.txt
>
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>
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Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
On 14/02/2020 05:49, Bibby Hsieh wrote:
> In order to use GCE function, we need add some information
> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
>
> Signed-off-by: Bibby Hsieh
> Signed-off-by: Yongqiang Niu
> ---
For the next time please provide some context on which patches this are based
on. Bet below the '---' with a link.
For this time, on which patch/series is this based? :)
Thanks,
Matthias
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index be4428c92f35..8b522b039a37 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -9,6 +9,7 @@
> #include
> #include
> #include
> +#include
> #include "mt8183-pinfunc.h"
>
> / {
> @@ -664,6 +665,9 @@
> reg = <0 0x1400 0 0x1000>;
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> #clock-cells = <1>;
> + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> + <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400 0
> 0x1000>;
> };
>
> ovl0: ovl@14008000 {
> @@ -672,6 +676,7 @@
> interrupts = ;
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_OVL0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400 0x8000
> 0x1000>;
> };
>
> ovl_2l0: ovl@14009000 {
> @@ -680,6 +685,7 @@
> interrupts = ;
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400 0x9000
> 0x1000>;
> };
>
> ovl_2l1: ovl@1400a000 {
> @@ -688,6 +694,7 @@
> interrupts = ;
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400 0xa000
> 0x1000>;
> };
>
> rdma0: rdma@1400b000 {
> @@ -697,6 +704,7 @@
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> mediatek,rdma_fifo_size = <5120>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400 0xb000
> 0x1000>;
> };
>
> rdma1: rdma@1400c000 {
> @@ -706,6 +714,7 @@
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> mediatek,rdma_fifo_size = <2048>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400 0xc000
> 0x1000>;
> };
>
> color0: color@1400e000 {
> @@ -715,6 +724,7 @@
> interrupts = ;
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400 0xe000
> 0x1000>;
> };
>
> ccorr0: ccorr@1400f000 {
> @@ -723,6 +733,7 @@
> interrupts = ;
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400 0xf000
> 0x1000>;
> };
>
> aal0: aal@1401 {
> @@ -732,6 +743,7 @@
> interrupts = ;
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401 0
> 0x1000>;
> };
>
> gamma0: gamma@14011000 {
> @@ -741,6 +753,7 @@
> interrupts = ;
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401 0x1000
> 0x1000>;
> };
>
> dither0: dither@14012000 {
> @@ -749,6 +762,7 @@
> interrupts = ;
> power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401 0x2000
> 0x1000>;
> };
>
> mutex: mutex@14016000 {
> @@ -756,6 +770,8 @@
> reg = <0 0x1401600
Re: [RFC PATCH 0/3] KVM: x86: honor guest memory type
On 13/02/20 23:18, Chia-I Wu wrote:
>
> The bug you mentioned was probably this one
>
> https://bugzilla.kernel.org/show_bug.cgi?id=104091
Yes, indeed.
> From what I can tell, the commit allowed the guests to create cached
> mappings to MMIO regions and caused MCEs. That is different than what
> I need, which is to allow guests to create uncached mappings to system
> ram (i.e., !kvm_is_mmio_pfn) when the host userspace also has uncached
> mappings. But it is true that this still allows the userspace & guest
> kernel to create conflicting memory types.
Right, the question is whether the MCEs were tied to MMIO regions
specifically and if so why.
An interesting remark is in the footnote of table 11-7 in the SDM.
There, for the MTRR (EPT for us) memory type UC you can read:
The UC attribute comes from the MTRRs and the processors are not
required to snoop their caches since the data could never have
been cached. This attribute is preferred for performance reasons.
There are two possibilities:
1) the footnote doesn't apply to UC mode coming from EPT page tables.
That would make your change safe.
2) the footnote also applies when the UC attribute comes from the EPT
page tables rather than the MTRRs. In that case, the host should use
UC as the EPT page attribute if and only if it's consistent with the host
MTRRs; it would be more or less impossible to honor UC in the guest MTRRs.
In that case, something like the patch below would be needed.
It is not clear from the manual why the footnote would not apply to WC; that
is, the manual doesn't say explicitly that the processor does not do snooping
for accesses to WC memory. But I guess that must be the case, which is why I
used MTRR_TYPE_WRCOMB in the patch below.
Either way, we would have an explanation of why creating cached mapping to
MMIO regions would, and why in practice we're not seeing MCEs for guest RAM
(the guest would have set WB for that memory in its MTRRs, not UC).
One thing you didn't say: how would userspace use KVM_MEM_DMA? On which
regions would it be set?
Thanks,
Paolo
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index dc331fb06495..2be6f7effa1d 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -6920,8 +6920,16 @@ static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t
gfn, bool is_mmio)
}
cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
-
exit:
+ if (cache == MTRR_TYPE_UNCACHABLE && !is_mmio) {
+ /*
+* We cannot set UC in the EPT page tables as it can cause
+* machine check exceptions (??). Hopefully the guest is
+* using PAT.
+*/
+ cache = MTRR_TYPE_WRCOMB;
+ }
+
return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
}
___
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Re: [RFC PATCH 0/6] do not store GPU address in TTM
On 2/14/20 10:19 AM, Thomas Zimmermann wrote: Hi Am 13.02.20 um 13:01 schrieb Nirmoy Das: With this patch series I am trying to remove GPU address dependency in TTM and moving GPU address calculation to individual drm drivers. This is required[1] to continue the work started by Brian Welty to create struct drm_mem_region which can be leverage by DRM cgroup controller to manage memory limits. I have only manage to test amdgpu driver as I only have GPU for that. I might be doing something really stupid while calculeting gpu offset for some of the drivers so please be patient and let me know how can I improve that. [1] https://www.mail-archive.com/dri-devel@lists.freedesktop.org/msg272238.html Nirmoy Das (6): drm/amdgpu: move ttm bo->offset to amdgpu_bo drm/radeon: don't use ttm bo->offset drm/vmwgfx: don't use ttm bo->offset drm/nouveau: don't use ttm bo->offset drm/qxl: don't use ttm bo->offset drm/ttm: do not keep GPU dependent addresses I think VRAM helpers are missing from this patchset. [1] You can use bochs in qemu to test them. Thanks Thomas. I missed that, I will add that into next revision. Best regards Thomas [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/drm_gem_vram_helper.c?h=v5.6-rc1#n217 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 22 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 29 - drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 4 +-- drivers/gpu/drm/nouveau/dispnv04/crtc.c | 6 ++--- drivers/gpu/drm/nouveau/dispnv04/disp.c | 2 +- drivers/gpu/drm/nouveau/dispnv04/overlay.c | 6 ++--- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/core507d.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/ovly507e.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 2 +- drivers/gpu/drm/nouveau/nouveau_abi16.c | 8 +++--- drivers/gpu/drm/nouveau/nouveau_bo.c| 1 + drivers/gpu/drm/nouveau/nouveau_bo.h| 3 +++ drivers/gpu/drm/nouveau/nouveau_chan.c | 2 +- drivers/gpu/drm/nouveau/nouveau_fbcon.c | 2 +- drivers/gpu/drm/nouveau/nouveau_gem.c | 10 +++ drivers/gpu/drm/qxl/qxl_drv.h | 6 ++--- drivers/gpu/drm/qxl/qxl_kms.c | 3 +++ drivers/gpu/drm/qxl/qxl_object.h| 5 drivers/gpu/drm/qxl/qxl_ttm.c | 9 --- drivers/gpu/drm/radeon/radeon.h | 1 + drivers/gpu/drm/radeon/radeon_object.h | 16 +++- drivers/gpu/drm/radeon/radeon_ttm.c | 4 +-- drivers/gpu/drm/ttm/ttm_bo.c| 7 - drivers/gpu/drm/vmwgfx/vmwgfx_bo.c | 4 +-- drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 2 +- drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c| 2 +- drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 2 -- include/drm/ttm/ttm_bo_api.h| 2 -- include/drm/ttm/ttm_bo_driver.h | 1 - 33 files changed, 99 insertions(+), 72 deletions(-) -- 2.25.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v4] drm/tidss: dispc: Rewrite naive plane positioning code
On 13/02/2020 21:37, Jyri Sarha wrote:
The old implementation of placing planes on the CRTC while configuring
the planes was naive and relied on the order in which the planes were
configured, enabled, and disabled. The situation where a plane's zpos
was changed on the fly was completely broken. The usual symptoms of
this problem was scrambled display and a flood of sync lost errors,
when a plane was active in two layers at the same time, or a missing
plane, in case when a layer was accidentally disabled.
The rewrite takes a more straight forward approach when HW is
concerned. The plane positioning registers are in the CRTC (or
actually OVR) register space and it is more natural to configure them
in a one go when configuring the CRTC. To do this we need make sure we
have all the planes on the updated CRTCs in the new atomic state. The
untouched planes on CRTCs that need plane position update are added to
the atomic state in tidss_atomic_check().
The subject needs updating. This is a fix for a bug, and subject needs to
reflect that.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tidss/tidss_crtc.c | 55 +
drivers/gpu/drm/tidss/tidss_crtc.h | 2 ++
drivers/gpu/drm/tidss/tidss_dispc.c | 55 +++--
drivers/gpu/drm/tidss/tidss_dispc.h | 5 +++
drivers/gpu/drm/tidss/tidss_kms.c | 49 -
5 files changed, 130 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c
b/drivers/gpu/drm/tidss/tidss_crtc.c
index 032c31ee2820..631ec61b086a 100644
--- a/drivers/gpu/drm/tidss/tidss_crtc.c
+++ b/drivers/gpu/drm/tidss/tidss_crtc.c
@@ -17,6 +17,7 @@
#include "tidss_dispc.h"
#include "tidss_drv.h"
#include "tidss_irq.h"
+#include "tidss_plane.h"
/* Page flip and frame done IRQs */
@@ -111,6 +112,54 @@ static int tidss_crtc_atomic_check(struct drm_crtc *crtc,
return dispc_vp_bus_check(dispc, hw_videoport, state);
}
+/*
+ * This needs all affected planes to be present in the atomic
+ * state. The untouched planes are added to the state in
+ * tidss_atomic_check().
+ */
+static void tidss_crtc_position_planes(struct tidss_device *tidss,
+ struct drm_crtc *crtc,
+ struct drm_crtc_state *old_state,
+ bool newmodeset)
+{
+ struct drm_atomic_state *ostate = old_state->state;
+ struct tidss_crtc *tcrtc = to_tidss_crtc(crtc);
+ struct drm_crtc_state *cstate = crtc->state;
+ int zpos;
+
+ if (!newmodeset && !cstate->zpos_changed &&
+ !to_tidss_crtc_state(cstate)->plane_pos_changed)
+ return;
+
+ for (zpos = 0; zpos < tidss->feat->num_planes; zpos++) {
+ struct drm_plane_state *pstate;
+ struct drm_plane *plane;
+ bool zpos_taken = false;
+ int i;
+
+ for_each_new_plane_in_state(ostate, plane, pstate, i) {
+ if (pstate->crtc != crtc || !pstate->visible)
+ continue;
+
+ if (pstate->normalized_zpos == zpos) {
+ zpos_taken = true;
+ break;
+ }
+ }
+
+ if (zpos_taken) {
+ struct tidss_plane *tplane = to_tidss_plane(plane);
+
+ dispc_ovr_set_plane(tidss->dispc, tplane->hw_plane_id,
+ tcrtc->hw_videoport,
+ pstate->crtc_x, pstate->crtc_y,
+ zpos);
+ }
+ dispc_ovr_enable_layer(tidss->dispc, tcrtc->hw_videoport, zpos,
+ zpos_taken);
+ }
+}
Nitpicking, but... I think the "zpos" above is really "layer". Even the params, to which you pass
"zpos", in the ovr functions are named "layer".
"zpos_taken" sounds like it's reserved and not available for us, or something like that. Maybe
"layer_active" conveys better that we're just collecting which layers are active and which are not.
+
static void tidss_crtc_atomic_flush(struct drm_crtc *crtc,
struct drm_crtc_state *old_crtc_state)
{
@@ -146,6 +195,9 @@ static void tidss_crtc_atomic_flush(struct drm_crtc *crtc,
/* Write vp properties to HW if needed. */
dispc_vp_setup(tidss->dispc, tcrtc->hw_videoport, crtc->state, false);
+ /* Update plane positions if needed. */
+ tidss_crtc_position_planes(tidss, crtc, old_crtc_state, false);
+
WARN_ON(drm_crtc_vblank_get(crtc) != 0);
spin_lock_irqsave(&ddev->event_lock, flags);
@@ -183,6 +235,7 @@ static void tidss_crtc_atomic_enable(struct drm_crtc *crtc,
return;
dispc_vp_setup(tidss->dispc, tcrtc->hw_videoport, crtc->state, true);
+ tidss_crtc_positio
Re: [PATCH] drm/i915: Cast remain to unsigned long in eb_relocate_vma
On Fri, 14 Feb 2020, Chris Wilson wrote: > Quoting Jani Nikula (2020-02-14 06:36:15) >> On Thu, 13 Feb 2020, Nathan Chancellor wrote: >> > A recent commit in clang added -Wtautological-compare to -Wall, which is >> > enabled for i915 after -Wtautological-compare is disabled for the rest >> > of the kernel so we see the following warning on x86_64: >> > >> > ../drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1433:22: warning: >> > result of comparison of constant 576460752303423487 with expression of >> > type 'unsigned int' is always false >> > [-Wtautological-constant-out-of-range-compare] >> > if (unlikely(remain > N_RELOC(ULONG_MAX))) >> > ^ >> > ../include/linux/compiler.h:78:42: note: expanded from macro 'unlikely' >> > # define unlikely(x)__builtin_expect(!!(x), 0) >> > ^ >> > 1 warning generated. >> > >> > It is not wrong in the case where ULONG_MAX > UINT_MAX but it does not >> > account for the case where this file is built for 32-bit x86, where >> > ULONG_MAX == UINT_MAX and this check is still relevant. >> > >> > Cast remain to unsigned long, which keeps the generated code the same >> > (verified with clang-11 on x86_64 and GCC 9.2.0 on x86 and x86_64) and >> > the warning is silenced so we can catch more potential issues in the >> > future. >> > >> > Link: https://github.com/ClangBuiltLinux/linux/issues/778 >> > Suggested-by: Michel Dänzer >> > Signed-off-by: Nathan Chancellor >> >> Works for me as a workaround, > > But the whole point was that the compiler could see that it was > impossible and not emit the code. Doesn't this break that? It seems that goal and the warning are fundamentally incompatible. Back to the original patch? BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [RFC PATCH 5/6] drm/qxl: don't use ttm bo->offset
On 2/14/20 10:08 AM, Gerd Hoffmann wrote: - if (bo->mem.mm_node) - bo->offset = (bo->mem.start << PAGE_SHIFT) + - bdev->man[bo->mem.mem_type].gpu_offset; - else - bo->offset = 0; - My assumption is (bo->tbo.offset - slot->gpu_offset + offset) == (bo->tbo.mem.start << PAGE_SHIFT) + bdev->man[bo->mem.mem_type].gpu_offset - slot->gpu_offset + offset) -> == (bo->tbo.mem.start << PAGE_SHIFT) + offset That looks better. Thanks, I will use that. and we loose slot->gpu_offset so I thought it should be ((bo->tbo.mem.start << PAGE_SHIFT) + slot->gpu_offset + offset); No. Yes this doesn't work, qemu throws bunch of warnings. (tested without GUI, modprobe qxl) [ 10.691506] [drm] Device Version 0.0 [ 10.691618] [drm] Compression level 0 log level 0 [ 10.691759] [drm] 12286 io pages at offset 0x100 [ 10.691897] [drm] 16777216 byte draw area at offset 0x0 [ 10.692043] [drm] RAM header offset: 0x3ffe000 [ 10.694823] [TTM] Zone kernel: Available graphics memory: 240756 KiB [ 10.695055] [TTM] Initializing pool allocator [ 10.695294] [TTM] Initializing DMA pool allocator [ 10.695807] [drm] qxl: 16M of VRAM memory size [ 10.695933] [drm] qxl: 63M of IO pages memory ready (VRAM domain) [ 10.696093] [drm] qxl: 64M of Surface memory size [ 10.699969] [drm] slot 0 (main): base 0xf400, size 0x03ffe000, gpu_offset 0x0 [ 10.700319] [drm] slot 1 (surfaces): base 0xf800, size 0x0400, gpu_offset 0x100 [ 10.707842] [drm] Initialized qxl 0.1.0 20120117 for :00:02.0 on minor 0 id 0, group 0, virt start 0, virt end , generation 0, delta 0 id 1, group 1, virt start 7f329f40, virt end 7f32a33fe000, generation 0, delta 7f329f40 id 2, group 1, virt start 7f329b00, virt end 7f329f00, generation 0, delta 7f329b00 qemu-system-x86_64: warning: Spice: memslot.c:64:memslot_validate_virt: virtual address out of range virt=0x80329b30+0x4000 slot_id=2 group_id=1 slot=0x7f329b00-0x7f329f00 delta=0x7f329b00 qemu-system-x86_64: warning: Spice: display-channel.c:2437:display_channel_validate_surface: canvas address is 0x7f32d989eb18 for 0 (and is NULL) qemu-system-x86_64: warning: Spice: display-channel.c:2439:display_channel_validate_surface: failed on 0 qemu-system-x86_64: warning: Spice: display-channel.c:2437:display_channel_validate_surface: canvas address is 0x7f32d989eb18 for 0 (and is NULL) qemu-system-x86_64: warning: Spice: display-channel.c:2439:display_channel_validate_surface: failed on 0 qemu-system-x86_64: warning: Spice: display-channel.c:2437:display_channel_validate_surface: canvas address is 0x7f32d989eb18 for 0 (and is NULL) qemu-system-x86_64: warning: Spice: display-channel.c:2439:display_channel_validate_surface: failed on 0 qemu-system-x86_64: warning: Spice: red-worker.c:468:destroy_primary_surface: double destroy of primary surface id 0, group 0, virt start 0, virt end , generation 0, delta 0 id 1, group 1, virt start 7f329f40, virt end 7f32a33fe000, generation 0, delta 7f329f40 id 2, group 1, virt start 7f329b00, virt end 7f329f00, generation 0, delta 7f329b00 qemu-system-x86_64: warning: Spice: memslot.c:64:memslot_validate_virt: virtual address out of range virt=0x80329b304000+0x30 slot_id=2 group_id=1 slot=0x7f329b00-0x7f329f00 delta=0x7f329b00 qemu-system-x86_64: warning: Spice: display-channel.c:2437:display_channel_validate_surface: canvas address is 0x7f32d989eb18 for 0 (and is NULL) qemu-system-x86_64: warning: Spice: display-channel.c:2439:display_channel_validate_surface: failed on 0 [ 10.723939] fbcon: qxldrmfb (fb0) is primary device [ 10.749245] Console: switching to colour frame buffer device 128x48 [ 10.775038] qxl :00:02.0: fb0: qxldrmfb frame buffer device qemu-system-x86_64: warning: Spice: display-channel.c:2437:display_channel_validate_surface: canvas address is 0x7f32d989eb18 for 0 (and is NULL) qemu-system-x86_64: warning: Spice: display-channel.c:2439:display_channel_validate_surface: failed on 0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 206519] [amdgpu] kernel NULL pointer dereference on shutdown
https://bugzilla.kernel.org/show_bug.cgi?id=206519 --- Comment #3 from Shlomo (shl...@fastmail.com) --- The bug first occurs in Arch Linux 5.5.arch1-1, which set CONFIG_DRM_AMD_DC_HDCP=y [1]. Arch Linux 5.4.15.arch1-1 is good. Arch Linux 5.4.15.arch1-1 with CONFIG_DRM_AMD_DC_HDCP=y set (and no other changes) is bad. Arch Linux 5.5.arch1-1 (and later) is bad. (CONFIG_DRM_AMD_DC_HDCP=y is set) Testing the most recent Arch Linux kernel shows the same: Arch Linux 5.5.3.arch1 is bad. Arch Linux 5.5.3.arch1 with CONFIG_DRM_AMD_DC_HDCP unset is good. This means that this bug was triggered by changes to the config, not kernel changes, so I don't know if this is a regression or not. [1] https://git.archlinux.org/svntogit/packages.git/commit/trunk?h=packages/linux&id=019514c4cdff26addfd49db8a78a857cb03994d9 -- You are receiving this mail because: You are watching the assignee of the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 2/2] drm/bridge: anx7688: Add anx7688 bridge driver support
On 13.02.2020 15:54, Enric Balletbo i Serra wrote:
> From: Nicolas Boichat
>
> ANX7688 is a HDMI to DP converter (as well as USB-C port controller),
> that has an internal microcontroller.
>
> The only reason a Linux kernel driver is necessary is to reject
> resolutions that require more bandwidth than what is available on
> the DP side. DP bandwidth and lane count are reported by the bridge
> via 2 registers on I2C.
>
> Signed-off-by: Nicolas Boichat
> Signed-off-by: Hsin-Yi Wang
> Signed-off-by: Enric Balletbo i Serra
> ---
>
> Changes in v2:
> - Move driver to drivers/gpu/drm/bridge/analogix.
> - Make the driver OF only so we can reduce the ifdefs.
> - Update the Copyright to 2020.
> - Use probe_new so we can get rid of the i2c_device_id table.
>
> drivers/gpu/drm/bridge/analogix/Kconfig | 12 ++
> drivers/gpu/drm/bridge/analogix/Makefile | 1 +
> .../drm/bridge/analogix/analogix-anx7688.c| 188 ++
> 3 files changed, 201 insertions(+)
> create mode 100644 drivers/gpu/drm/bridge/analogix/analogix-anx7688.c
>
> diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig
> b/drivers/gpu/drm/bridge/analogix/Kconfig
> index e1fa7d820373..af7c2939403c 100644
> --- a/drivers/gpu/drm/bridge/analogix/Kconfig
> +++ b/drivers/gpu/drm/bridge/analogix/Kconfig
> @@ -11,6 +11,18 @@ config DRM_ANALOGIX_ANX6345
> ANX6345 transforms the LVTTL RGB output of an
> application processor to eDP or DisplayPort.
>
> +config DRM_ANALOGIX_ANX7688
> + tristate "Analogix ANX7688 bridge"
> + depends on OF
> + select DRM_KMS_HELPER
> + select REGMAP_I2C
> + help
> + ANX7688 is an ultra-low power 4k Ultra-HD (4096x2160p60)
> + mobile HD transmitter designed for portable devices. The
> + ANX7688 converts HDMI 2.0 to DisplayPort 1.3 Ultra-HD
> + including an intelligent crosspoint switch to support
> + USB Type-C.
> +
> config DRM_ANALOGIX_ANX78XX
> tristate "Analogix ANX78XX bridge"
> select DRM_ANALOGIX_DP
> diff --git a/drivers/gpu/drm/bridge/analogix/Makefile
> b/drivers/gpu/drm/bridge/analogix/Makefile
> index 97669b374098..27cd73635c8c 100644
> --- a/drivers/gpu/drm/bridge/analogix/Makefile
> +++ b/drivers/gpu/drm/bridge/analogix/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0-only
> analogix_dp-objs := analogix_dp_core.o analogix_dp_reg.o analogix-i2c-dptx.o
> obj-$(CONFIG_DRM_ANALOGIX_ANX6345) += analogix-anx6345.o
> +obj-$(CONFIG_DRM_ANALOGIX_ANX7688) += analogix-anx7688.o
> obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o
> obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp.o
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx7688.c
> b/drivers/gpu/drm/bridge/analogix/analogix-anx7688.c
> new file mode 100644
> index ..10a7cd0f9126
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx7688.c
> @@ -0,0 +1,188 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * ANX7688 HDMI->DP bridge driver
> + *
> + * Copyright 2020 Google LLC
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +/* Register addresses */
> +#define VENDOR_ID_REG 0x00
> +#define DEVICE_ID_REG 0x02
> +
> +#define FW_VERSION_REG 0x80
> +
> +#define DP_BANDWIDTH_REG 0x85
> +#define DP_LANE_COUNT_REG 0x86
> +
> +#define VENDOR_ID 0x1f29
> +#define DEVICE_ID 0x7688
> +
> +/* First supported firmware version (0.85) */
> +#define MINIMUM_FW_VERSION 0x0085
> +
> +struct anx7688 {
> + struct drm_bridge bridge;
> + struct i2c_client *client;
> + struct regmap *regmap;
> +
> + bool filter;
> +};
> +
> +static inline struct anx7688 *bridge_to_anx7688(struct drm_bridge *bridge)
> +{
> + return container_of(bridge, struct anx7688, bridge);
> +}
> +
> +static bool anx7688_bridge_mode_fixup(struct drm_bridge *bridge,
> + const struct drm_display_mode *mode,
> + struct drm_display_mode *adjusted_mode)
> +{
> + struct anx7688 *anx7688 = bridge_to_anx7688(bridge);
> + int totalbw, requiredbw;
> + u8 dpbw, lanecount;
> + u8 regs[2];
> + int ret;
> +
> + if (!anx7688->filter)
> + return true;
> +
> + /* Read both regs 0x85 (bandwidth) and 0x86 (lane count). */
> + ret = regmap_bulk_read(anx7688->regmap, DP_BANDWIDTH_REG, regs, 2);
> + if (ret < 0) {
> + dev_err(&anx7688->client->dev,
> + "Failed to read bandwidth/lane count\n");
> + return false;
> + }
> + dpbw = regs[0];
> + lanecount = regs[1];
Are these values hw invariant? Or they are result of cable probe/training?
In 1st case this code should go rather to mode_valid.
> +
> + /* Maximum 0x19 bandwidth (6.75 Gbps Turbo mode), 2 lanes */
> + if (dpbw > 0x19 || lanecount > 2) {
> + dev_err(&anx7688->client->dev,
> + "Invalid bandwidth/lane count (%02x/%d)\n",
> + dpbw, lanecount);
> +
[PATCH v4 0/6] drm/virtio: rework batching
v4: - add patches #2 + #6. v3: - split into multiple patches. Gerd Hoffmann (6): drm/virtio: rework notification for better batching drm/virtio: notify before waiting drm/virtio: batch plane updates (pageflip) drm/virtio: batch resource creation drm/virtio: batch display query drm/virtio: move remaining virtio_gpu_notify calls drivers/gpu/drm/virtio/virtgpu_drv.h | 6 ++--- drivers/gpu/drm/virtio/virtgpu_display.c | 2 ++ drivers/gpu/drm/virtio/virtgpu_gem.c | 2 ++ drivers/gpu/drm/virtio/virtgpu_ioctl.c | 4 +++ drivers/gpu/drm/virtio/virtgpu_kms.c | 5 drivers/gpu/drm/virtio/virtgpu_object.c | 2 ++ drivers/gpu/drm/virtio/virtgpu_plane.c | 7 +++-- drivers/gpu/drm/virtio/virtgpu_vq.c | 33 ++-- 8 files changed, 34 insertions(+), 27 deletions(-) -- 2.18.2 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v4 6/6] drm/virtio: move remaining virtio_gpu_notify calls
Move all remaining virtio_gpu_notify() calls from virtio_gpu_cmd_*
to the callers, for consistency reasons.
Signed-off-by: Gerd Hoffmann
---
drivers/gpu/drm/virtio/virtgpu_gem.c| 2 ++
drivers/gpu/drm/virtio/virtgpu_ioctl.c | 3 +++
drivers/gpu/drm/virtio/virtgpu_kms.c| 3 +++
drivers/gpu/drm/virtio/virtgpu_object.c | 1 +
drivers/gpu/drm/virtio/virtgpu_vq.c | 9 -
5 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/virtio/virtgpu_gem.c
b/drivers/gpu/drm/virtio/virtgpu_gem.c
index 0a2b62279647..0d6152c99a27 100644
--- a/drivers/gpu/drm/virtio/virtgpu_gem.c
+++ b/drivers/gpu/drm/virtio/virtgpu_gem.c
@@ -123,6 +123,7 @@ int virtio_gpu_gem_object_open(struct drm_gem_object *obj,
virtio_gpu_cmd_context_attach_resource(vgdev, vfpriv->ctx_id,
objs);
+ virtio_gpu_notify(vgdev);
return 0;
}
@@ -143,6 +144,7 @@ void virtio_gpu_gem_object_close(struct drm_gem_object *obj,
virtio_gpu_cmd_context_detach_resource(vgdev, vfpriv->ctx_id,
objs);
+ virtio_gpu_notify(vgdev);
}
struct virtio_gpu_object_array *virtio_gpu_array_alloc(u32 nents)
diff --git a/drivers/gpu/drm/virtio/virtgpu_ioctl.c
b/drivers/gpu/drm/virtio/virtgpu_ioctl.c
index 467649733d24..bbc31aef51f1 100644
--- a/drivers/gpu/drm/virtio/virtgpu_ioctl.c
+++ b/drivers/gpu/drm/virtio/virtgpu_ioctl.c
@@ -158,6 +158,7 @@ static int virtio_gpu_execbuffer_ioctl(struct drm_device
*dev, void *data,
virtio_gpu_cmd_submit(vgdev, buf, exbuf->size,
vfpriv->ctx_id, buflist, out_fence);
+ virtio_gpu_notify(vgdev);
return 0;
out_unresv:
@@ -314,6 +315,7 @@ static int virtio_gpu_transfer_from_host_ioctl(struct
drm_device *dev,
(vgdev, vfpriv->ctx_id, offset, args->level,
&args->box, objs, fence);
dma_fence_put(&fence->f);
+ virtio_gpu_notify(vgdev);
return 0;
err_unlock:
@@ -446,6 +448,7 @@ static int virtio_gpu_get_caps_ioctl(struct drm_device *dev,
/* not in cache - need to talk to hw */
virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver,
&cache_ent);
+ virtio_gpu_notify(vgdev);
copy_exit:
ret = wait_event_timeout(vgdev->resp_wq,
diff --git a/drivers/gpu/drm/virtio/virtgpu_kms.c
b/drivers/gpu/drm/virtio/virtgpu_kms.c
index 8fd7acef960f..ad3b673f5796 100644
--- a/drivers/gpu/drm/virtio/virtgpu_kms.c
+++ b/drivers/gpu/drm/virtio/virtgpu_kms.c
@@ -61,6 +61,7 @@ static int virtio_gpu_context_create(struct virtio_gpu_device
*vgdev,
return handle;
handle += 1;
virtio_gpu_cmd_context_create(vgdev, handle, nlen, name);
+ virtio_gpu_notify(vgdev);
return handle;
}
@@ -68,6 +69,7 @@ static void virtio_gpu_context_destroy(struct
virtio_gpu_device *vgdev,
uint32_t ctx_id)
{
virtio_gpu_cmd_context_destroy(vgdev, ctx_id);
+ virtio_gpu_notify(vgdev);
ida_free(&vgdev->ctx_id_ida, ctx_id - 1);
}
@@ -93,6 +95,7 @@ static void virtio_gpu_get_capsets(struct virtio_gpu_device
*vgdev,
}
for (i = 0; i < num_capsets; i++) {
virtio_gpu_cmd_get_capset_info(vgdev, i);
+ virtio_gpu_notify(vgdev);
ret = wait_event_timeout(vgdev->resp_wq,
vgdev->capsets[i].id > 0, 5 * HZ);
if (ret == 0) {
diff --git a/drivers/gpu/drm/virtio/virtgpu_object.c
b/drivers/gpu/drm/virtio/virtgpu_object.c
index 65d6834d3c74..3d2a6d489bfc 100644
--- a/drivers/gpu/drm/virtio/virtgpu_object.c
+++ b/drivers/gpu/drm/virtio/virtgpu_object.c
@@ -88,6 +88,7 @@ static void virtio_gpu_free_object(struct drm_gem_object *obj)
if (bo->created) {
virtio_gpu_cmd_unref_resource(vgdev, bo);
+ virtio_gpu_notify(vgdev);
/* completion handler calls virtio_gpu_cleanup_object() */
return;
}
diff --git a/drivers/gpu/drm/virtio/virtgpu_vq.c
b/drivers/gpu/drm/virtio/virtgpu_vq.c
index 2e108b426244..5e2375e0f7bb 100644
--- a/drivers/gpu/drm/virtio/virtgpu_vq.c
+++ b/drivers/gpu/drm/virtio/virtgpu_vq.c
@@ -544,7 +544,6 @@ void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device
*vgdev,
vbuf->resp_cb_data = bo;
virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
- virtio_gpu_notify(vgdev);
}
void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev,
@@ -798,7 +797,6 @@ int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device
*vgdev, int idx)
cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_CAPSET_INFO);
cmd_p->capset_index = cpu_to_le32(idx);
virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
- virtio_gpu_notify(vgdev);
return 0;
}
@@ -874,7 +872,6 @@ int virtio_gpu_cmd_get_capset(struct virtio_
[PATCH v4 5/6] drm/virtio: batch display query
Move virtio_gpu_notify() to higher-level functions for virtio_gpu_cmd_get_display_info() and virtio_gpu_cmd_get_edids(). virtio_gpu_config_changed_work_func() and virtio_gpu_init() will batch commands and notify only once per update Signed-off-by: Gerd Hoffmann Reviewed-by: Chia-I Wu --- drivers/gpu/drm/virtio/virtgpu_kms.c | 2 ++ drivers/gpu/drm/virtio/virtgpu_vq.c | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/virtio/virtgpu_kms.c b/drivers/gpu/drm/virtio/virtgpu_kms.c index 4009c2f97d08..8fd7acef960f 100644 --- a/drivers/gpu/drm/virtio/virtgpu_kms.c +++ b/drivers/gpu/drm/virtio/virtgpu_kms.c @@ -44,6 +44,7 @@ static void virtio_gpu_config_changed_work_func(struct work_struct *work) if (vgdev->has_edid) virtio_gpu_cmd_get_edids(vgdev); virtio_gpu_cmd_get_display_info(vgdev); + virtio_gpu_notify(vgdev); drm_helper_hpd_irq_event(vgdev->ddev); events_clear |= VIRTIO_GPU_EVENT_DISPLAY; } @@ -205,6 +206,7 @@ int virtio_gpu_init(struct drm_device *dev) if (vgdev->has_edid) virtio_gpu_cmd_get_edids(vgdev); virtio_gpu_cmd_get_display_info(vgdev); + virtio_gpu_notify(vgdev); wait_event_timeout(vgdev->resp_wq, !vgdev->display_info_pending, 5 * HZ); return 0; diff --git a/drivers/gpu/drm/virtio/virtgpu_vq.c b/drivers/gpu/drm/virtio/virtgpu_vq.c index 4e9b2f2e71bd..2e108b426244 100644 --- a/drivers/gpu/drm/virtio/virtgpu_vq.c +++ b/drivers/gpu/drm/virtio/virtgpu_vq.c @@ -775,7 +775,6 @@ int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev) vgdev->display_info_pending = true; cmd_p->type = cpu_to_le32(VIRTIO_GPU_CMD_GET_DISPLAY_INFO); virtio_gpu_queue_ctrl_buffer(vgdev, vbuf); - virtio_gpu_notify(vgdev); return 0; } @@ -903,7 +902,6 @@ int virtio_gpu_cmd_get_edids(struct virtio_gpu_device *vgdev) cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_EDID); cmd_p->scanout = cpu_to_le32(scanout); virtio_gpu_queue_ctrl_buffer(vgdev, vbuf); - virtio_gpu_notify(vgdev); } return 0; -- 2.18.2 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v4 1/6] drm/virtio: rework notification for better batching
Drop the virtio_gpu_{disable,enable}_notify(). Add a new
virtio_gpu_notify() call instead, which must be called whenever
the driver wants make sure the host is notified needed.
Drop automatic notification from command submission. Add
virtio_gpu_notify() calls after each command query instead.
This allows more fine-grained control over host notification
and can move around the notify calls in subsequent patches to
batch command submissions. With this in place it is also
possible to make notification optional for userspace ioctls.
Page flip batching goes away (temporarely).
v3:
- move batching to separate patches.
v2:
- rebase to latest drm-misc-next.
- use "if (!atomic_read())".
- add review & test tags.
Signed-off-by: Gerd Hoffmann
Reviewed-by: Gurchetan Singh
Tested-by: Gurchetan Singh
Reviewed-by: Chia-I Wu
---
drivers/gpu/drm/virtio/virtgpu_drv.h | 6 ++--
drivers/gpu/drm/virtio/virtgpu_plane.c | 4 ---
drivers/gpu/drm/virtio/virtgpu_vq.c| 50 --
3 files changed, 33 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.h
b/drivers/gpu/drm/virtio/virtgpu_drv.h
index af9403e1cf78..2f6c4ccbfd14 100644
--- a/drivers/gpu/drm/virtio/virtgpu_drv.h
+++ b/drivers/gpu/drm/virtio/virtgpu_drv.h
@@ -179,8 +179,7 @@ struct virtio_gpu_device {
struct virtio_gpu_queue cursorq;
struct kmem_cache *vbufs;
- bool disable_notify;
- bool pending_notify;
+ atomic_t pending_commands;
struct ida resource_ida;
@@ -335,8 +334,7 @@ void virtio_gpu_dequeue_ctrl_func(struct work_struct *work);
void virtio_gpu_dequeue_cursor_func(struct work_struct *work);
void virtio_gpu_dequeue_fence_func(struct work_struct *work);
-void virtio_gpu_disable_notify(struct virtio_gpu_device *vgdev);
-void virtio_gpu_enable_notify(struct virtio_gpu_device *vgdev);
+void virtio_gpu_notify(struct virtio_gpu_device *vgdev);
/* virtio_gpu_display.c */
void virtio_gpu_modeset_init(struct virtio_gpu_device *vgdev);
diff --git a/drivers/gpu/drm/virtio/virtgpu_plane.c
b/drivers/gpu/drm/virtio/virtgpu_plane.c
index d1c3f5fbfee4..08b2e4127eb3 100644
--- a/drivers/gpu/drm/virtio/virtgpu_plane.c
+++ b/drivers/gpu/drm/virtio/virtgpu_plane.c
@@ -154,8 +154,6 @@ static void virtio_gpu_primary_plane_update(struct
drm_plane *plane,
if (!drm_atomic_helper_damage_merged(old_state, plane->state, &rect))
return;
- virtio_gpu_disable_notify(vgdev);
-
bo = gem_to_virtio_gpu_obj(plane->state->fb->obj[0]);
if (bo->dumb)
virtio_gpu_update_dumb_bo(vgdev, plane->state, &rect);
@@ -186,8 +184,6 @@ static void virtio_gpu_primary_plane_update(struct
drm_plane *plane,
rect.y1,
rect.x2 - rect.x1,
rect.y2 - rect.y1);
-
- virtio_gpu_enable_notify(vgdev);
}
static int virtio_gpu_cursor_prepare_fb(struct drm_plane *plane,
diff --git a/drivers/gpu/drm/virtio/virtgpu_vq.c
b/drivers/gpu/drm/virtio/virtgpu_vq.c
index 67caecde623e..6cc259cfa517 100644
--- a/drivers/gpu/drm/virtio/virtgpu_vq.c
+++ b/drivers/gpu/drm/virtio/virtgpu_vq.c
@@ -329,7 +329,6 @@ static void virtio_gpu_queue_ctrl_sgs(struct
virtio_gpu_device *vgdev,
int incnt)
{
struct virtqueue *vq = vgdev->ctrlq.vq;
- bool notify = false;
int ret, idx;
if (!drm_dev_enter(vgdev->ddev, &idx)) {
@@ -368,16 +367,10 @@ static void virtio_gpu_queue_ctrl_sgs(struct
virtio_gpu_device *vgdev,
trace_virtio_gpu_cmd_queue(vq, virtio_gpu_vbuf_ctrl_hdr(vbuf));
- notify = virtqueue_kick_prepare(vq);
+ atomic_inc(&vgdev->pending_commands);
spin_unlock(&vgdev->ctrlq.qlock);
- if (notify) {
- if (vgdev->disable_notify)
- vgdev->pending_notify = true;
- else
- virtqueue_notify(vq);
- }
drm_dev_exit(idx);
}
@@ -434,19 +427,20 @@ static void virtio_gpu_queue_fenced_ctrl_buffer(struct
virtio_gpu_device *vgdev,
}
}
-void virtio_gpu_disable_notify(struct virtio_gpu_device *vgdev)
+void virtio_gpu_notify(struct virtio_gpu_device *vgdev)
{
- vgdev->disable_notify = true;
-}
+ bool notify;
-void virtio_gpu_enable_notify(struct virtio_gpu_device *vgdev)
-{
- vgdev->disable_notify = false;
-
- if (!vgdev->pending_notify)
+ if (!atomic_read(&vgdev->pending_commands))
return;
- vgdev->pending_notify = false;
- virtqueue_notify(vgdev->ctrlq.vq);
+
+ spin_lock(&vgdev->ctrlq.qlock);
+ atomic_set(&vgdev->pending_commands, 0);
+ notify = virtqueue_kick_prepare(vgdev->ctrlq.vq);
+ spin_unlock(&vgdev->ctrlq.qlock);
+
+ if (notify)
+ virtqueue_notify(vgdev->ctrlq.vq);
}
static void virtio_gpu_queue_ctrl_buffer(struct virtio_gpu_devic
[PATCH v4 3/6] drm/virtio: batch plane updates (pageflip)
Move virtio_gpu_notify() to higher-level functions for
virtio_gpu_cmd_resource_flush(), virtio_gpu_cmd_set_scanout() and
virtio_gpu_cmd_transfer_to_host_{2d,3d}().
virtio_gpu_primary_plane_update() will notify only once for a series
of commands (restores plane update command batching).
Signed-off-by: Gerd Hoffmann
Reviewed-by: Chia-I Wu
---
drivers/gpu/drm/virtio/virtgpu_display.c | 2 ++
drivers/gpu/drm/virtio/virtgpu_ioctl.c | 1 +
drivers/gpu/drm/virtio/virtgpu_plane.c | 3 +++
drivers/gpu/drm/virtio/virtgpu_vq.c | 4
4 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/virtio/virtgpu_display.c
b/drivers/gpu/drm/virtio/virtgpu_display.c
index af953db4a0c9..2b7e6ae65546 100644
--- a/drivers/gpu/drm/virtio/virtgpu_display.c
+++ b/drivers/gpu/drm/virtio/virtgpu_display.c
@@ -90,6 +90,7 @@ static void virtio_gpu_crtc_mode_set_nofb(struct drm_crtc
*crtc)
virtio_gpu_cmd_set_scanout(vgdev, output->index, 0,
crtc->mode.hdisplay,
crtc->mode.vdisplay, 0, 0);
+ virtio_gpu_notify(vgdev);
}
static void virtio_gpu_crtc_atomic_enable(struct drm_crtc *crtc,
@@ -108,6 +109,7 @@ static void virtio_gpu_crtc_atomic_disable(struct drm_crtc
*crtc,
struct virtio_gpu_output *output = drm_crtc_to_virtio_gpu_output(crtc);
virtio_gpu_cmd_set_scanout(vgdev, output->index, 0, 0, 0, 0, 0);
+ virtio_gpu_notify(vgdev);
output->enabled = false;
}
diff --git a/drivers/gpu/drm/virtio/virtgpu_ioctl.c
b/drivers/gpu/drm/virtio/virtgpu_ioctl.c
index 0477d1250f2d..467649733d24 100644
--- a/drivers/gpu/drm/virtio/virtgpu_ioctl.c
+++ b/drivers/gpu/drm/virtio/virtgpu_ioctl.c
@@ -359,6 +359,7 @@ static int virtio_gpu_transfer_to_host_ioctl(struct
drm_device *dev, void *data,
args->level, &args->box, objs, fence);
dma_fence_put(&fence->f);
}
+ virtio_gpu_notify(vgdev);
return 0;
err_unlock:
diff --git a/drivers/gpu/drm/virtio/virtgpu_plane.c
b/drivers/gpu/drm/virtio/virtgpu_plane.c
index 08b2e4127eb3..52d24179bcec 100644
--- a/drivers/gpu/drm/virtio/virtgpu_plane.c
+++ b/drivers/gpu/drm/virtio/virtgpu_plane.c
@@ -148,6 +148,7 @@ static void virtio_gpu_primary_plane_update(struct
drm_plane *plane,
plane->state->src_w >> 16,
plane->state->src_h >> 16,
0, 0);
+ virtio_gpu_notify(vgdev);
return;
}
@@ -184,6 +185,7 @@ static void virtio_gpu_primary_plane_update(struct
drm_plane *plane,
rect.y1,
rect.x2 - rect.x1,
rect.y2 - rect.y1);
+ virtio_gpu_notify(vgdev);
}
static int virtio_gpu_cursor_prepare_fb(struct drm_plane *plane,
@@ -262,6 +264,7 @@ static void virtio_gpu_cursor_plane_update(struct drm_plane
*plane,
plane->state->crtc_w,
plane->state->crtc_h,
0, 0, objs, vgfb->fence);
+ virtio_gpu_notify(vgdev);
dma_fence_wait(&vgfb->fence->f, true);
dma_fence_put(&vgfb->fence->f);
vgfb->fence = NULL;
diff --git a/drivers/gpu/drm/virtio/virtgpu_vq.c
b/drivers/gpu/drm/virtio/virtgpu_vq.c
index 653efb26bcd9..0bd1c51bbabd 100644
--- a/drivers/gpu/drm/virtio/virtgpu_vq.c
+++ b/drivers/gpu/drm/virtio/virtgpu_vq.c
@@ -568,7 +568,6 @@ void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device
*vgdev,
cmd_p->r.y = cpu_to_le32(y);
virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
- virtio_gpu_notify(vgdev);
}
void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,
@@ -590,7 +589,6 @@ void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device
*vgdev,
cmd_p->r.y = cpu_to_le32(y);
virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
- virtio_gpu_notify(vgdev);
}
void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
@@ -623,7 +621,6 @@ void virtio_gpu_cmd_transfer_to_host_2d(struct
virtio_gpu_device *vgdev,
cmd_p->r.y = cpu_to_le32(y);
virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
- virtio_gpu_notify(vgdev);
}
static void
@@ -1049,7 +1046,6 @@ void virtio_gpu_cmd_transfer_to_host_3d(struct
virtio_gpu_device *vgdev,
cmd_p->level = cpu_to_le32(level);
virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
- virtio_gpu_notify(vgdev);
}
void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
--
2.18.2
___
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v4 2/6] drm/virtio: notify before waiting
Before we are going to wait for virtqueue entries becoming available
call virtio_gpu_notify() to make sure the host has seen everything
we've submitted.
Signed-off-by: Gerd Hoffmann
---
drivers/gpu/drm/virtio/virtgpu_vq.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/virtio/virtgpu_vq.c
b/drivers/gpu/drm/virtio/virtgpu_vq.c
index 6cc259cfa517..653efb26bcd9 100644
--- a/drivers/gpu/drm/virtio/virtgpu_vq.c
+++ b/drivers/gpu/drm/virtio/virtgpu_vq.c
@@ -346,6 +346,7 @@ static void virtio_gpu_queue_ctrl_sgs(struct
virtio_gpu_device *vgdev,
if (vq->num_free < elemcnt) {
spin_unlock(&vgdev->ctrlq.qlock);
+ virtio_gpu_notify(vgdev);
wait_event(vgdev->ctrlq.ack_queue, vq->num_free >= elemcnt);
goto again;
}
--
2.18.2
___
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[PATCH v4 4/6] drm/virtio: batch resource creation
Move virtio_gpu_notify() to higher-level functions for virtio_gpu_cmd_create_resource(), virtio_gpu_cmd_resource_create_3d() and virtio_gpu_cmd_resource_attach_backing(). virtio_gpu_object_create() will batch commands and notify only once when creating a resource. Signed-off-by: Gerd Hoffmann Reviewed-by: Chia-I Wu --- drivers/gpu/drm/virtio/virtgpu_object.c | 1 + drivers/gpu/drm/virtio/virtgpu_vq.c | 3 --- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/virtio/virtgpu_object.c b/drivers/gpu/drm/virtio/virtgpu_object.c index 8870ee23ff2b..65d6834d3c74 100644 --- a/drivers/gpu/drm/virtio/virtgpu_object.c +++ b/drivers/gpu/drm/virtio/virtgpu_object.c @@ -224,6 +224,7 @@ int virtio_gpu_object_create(struct virtio_gpu_device *vgdev, return ret; } + virtio_gpu_notify(vgdev); *bo_ptr = bo; return 0; diff --git a/drivers/gpu/drm/virtio/virtgpu_vq.c b/drivers/gpu/drm/virtio/virtgpu_vq.c index 0bd1c51bbabd..4e9b2f2e71bd 100644 --- a/drivers/gpu/drm/virtio/virtgpu_vq.c +++ b/drivers/gpu/drm/virtio/virtgpu_vq.c @@ -515,7 +515,6 @@ void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev, cmd_p->height = cpu_to_le32(params->height); virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence); - virtio_gpu_notify(vgdev); bo->created = true; } @@ -644,7 +643,6 @@ virtio_gpu_cmd_resource_attach_backing(struct virtio_gpu_device *vgdev, vbuf->data_size = sizeof(*ents) * nents; virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence); - virtio_gpu_notify(vgdev); } static void virtio_gpu_cmd_get_display_info_cb(struct virtio_gpu_device *vgdev, @@ -1011,7 +1009,6 @@ virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev, cmd_p->flags = cpu_to_le32(params->flags); virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence); - virtio_gpu_notify(vgdev); bo->created = true; } -- 2.18.2 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 1/2] dt-bindings: display: sun4i-tcon: Add LVDS Dual Link property
Hi Maxime, Thank you for the patch. On Fri, Feb 14, 2020 at 01:32:43PM +0100, Maxime Ripard wrote: > SoCs that have multiple TCONs can use the two set of pins on the first TCON > to drive a dual-link display. Add a property to enable the dual link. > > Signed-off-by: Maxime Ripard > --- > .../bindings/display/allwinner,sun4i-a10-tcon.yaml | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git > a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml > b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml > index 86ad617d2327..aa6dd8409dbc 100644 > --- a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml > +++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml > @@ -105,6 +105,13 @@ properties: > - const: edp > - const: lvds > > + allwinner,lvds-dual-link: > +type: boolean > +description: | > + On a SoC with two TCON with LVDS support, the first TCON can > + operate over both pins sets to output in a dual-link setup. This > + will be triggered by setting this property. Could you maybe provide an example of how this property is supposed to be used ? I'm especially wondering what ports are used in that case and how they're connected. > + >ports: > type: object > description: | -- Regards, Laurent Pinchart ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 2/2] drm/bridge: anx7688: Add anx7688 bridge driver support
On Fri, Feb 14, 2020 at 8:18 PM Andrzej Hajda wrote:
>
> On 13.02.2020 15:54, Enric Balletbo i Serra wrote:
> > From: Nicolas Boichat
> >
> > ANX7688 is a HDMI to DP converter (as well as USB-C port controller),
> > that has an internal microcontroller.
> >
> > The only reason a Linux kernel driver is necessary is to reject
> > resolutions that require more bandwidth than what is available on
> > the DP side. DP bandwidth and lane count are reported by the bridge
> > via 2 registers on I2C.
> >
> > Signed-off-by: Nicolas Boichat
> > Signed-off-by: Hsin-Yi Wang
> > Signed-off-by: Enric Balletbo i Serra
> > ---
> >
> > Changes in v2:
> > - Move driver to drivers/gpu/drm/bridge/analogix.
> > - Make the driver OF only so we can reduce the ifdefs.
> > - Update the Copyright to 2020.
> > - Use probe_new so we can get rid of the i2c_device_id table.
> >
> > drivers/gpu/drm/bridge/analogix/Kconfig | 12 ++
> > drivers/gpu/drm/bridge/analogix/Makefile | 1 +
> > .../drm/bridge/analogix/analogix-anx7688.c| 188 ++
> > 3 files changed, 201 insertions(+)
> > create mode 100644 drivers/gpu/drm/bridge/analogix/analogix-anx7688.c
> >
> > diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig
> > b/drivers/gpu/drm/bridge/analogix/Kconfig
> > index e1fa7d820373..af7c2939403c 100644
> > --- a/drivers/gpu/drm/bridge/analogix/Kconfig
> > +++ b/drivers/gpu/drm/bridge/analogix/Kconfig
> > @@ -11,6 +11,18 @@ config DRM_ANALOGIX_ANX6345
> > ANX6345 transforms the LVTTL RGB output of an
> > application processor to eDP or DisplayPort.
> >
> > +config DRM_ANALOGIX_ANX7688
> > + tristate "Analogix ANX7688 bridge"
> > + depends on OF
> > + select DRM_KMS_HELPER
> > + select REGMAP_I2C
> > + help
> > + ANX7688 is an ultra-low power 4k Ultra-HD (4096x2160p60)
> > + mobile HD transmitter designed for portable devices. The
> > + ANX7688 converts HDMI 2.0 to DisplayPort 1.3 Ultra-HD
> > + including an intelligent crosspoint switch to support
> > + USB Type-C.
> > +
> > config DRM_ANALOGIX_ANX78XX
> > tristate "Analogix ANX78XX bridge"
> > select DRM_ANALOGIX_DP
> > diff --git a/drivers/gpu/drm/bridge/analogix/Makefile
> > b/drivers/gpu/drm/bridge/analogix/Makefile
> > index 97669b374098..27cd73635c8c 100644
> > --- a/drivers/gpu/drm/bridge/analogix/Makefile
> > +++ b/drivers/gpu/drm/bridge/analogix/Makefile
> > @@ -1,5 +1,6 @@
> > # SPDX-License-Identifier: GPL-2.0-only
> > analogix_dp-objs := analogix_dp_core.o analogix_dp_reg.o
> > analogix-i2c-dptx.o
> > obj-$(CONFIG_DRM_ANALOGIX_ANX6345) += analogix-anx6345.o
> > +obj-$(CONFIG_DRM_ANALOGIX_ANX7688) += analogix-anx7688.o
> > obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o
> > obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp.o
> > diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx7688.c
> > b/drivers/gpu/drm/bridge/analogix/analogix-anx7688.c
> > new file mode 100644
> > index ..10a7cd0f9126
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx7688.c
> > @@ -0,0 +1,188 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * ANX7688 HDMI->DP bridge driver
> > + *
> > + * Copyright 2020 Google LLC
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +/* Register addresses */
> > +#define VENDOR_ID_REG 0x00
> > +#define DEVICE_ID_REG 0x02
> > +
> > +#define FW_VERSION_REG 0x80
> > +
> > +#define DP_BANDWIDTH_REG 0x85
> > +#define DP_LANE_COUNT_REG 0x86
> > +
> > +#define VENDOR_ID 0x1f29
> > +#define DEVICE_ID 0x7688
> > +
> > +/* First supported firmware version (0.85) */
> > +#define MINIMUM_FW_VERSION 0x0085
> > +
> > +struct anx7688 {
> > + struct drm_bridge bridge;
> > + struct i2c_client *client;
> > + struct regmap *regmap;
> > +
> > + bool filter;
> > +};
> > +
> > +static inline struct anx7688 *bridge_to_anx7688(struct drm_bridge *bridge)
> > +{
> > + return container_of(bridge, struct anx7688, bridge);
> > +}
> > +
> > +static bool anx7688_bridge_mode_fixup(struct drm_bridge *bridge,
> > + const struct drm_display_mode *mode,
> > + struct drm_display_mode *adjusted_mode)
> > +{
> > + struct anx7688 *anx7688 = bridge_to_anx7688(bridge);
> > + int totalbw, requiredbw;
> > + u8 dpbw, lanecount;
> > + u8 regs[2];
> > + int ret;
> > +
> > + if (!anx7688->filter)
> > + return true;
> > +
> > + /* Read both regs 0x85 (bandwidth) and 0x86 (lane count). */
> > + ret = regmap_bulk_read(anx7688->regmap, DP_BANDWIDTH_REG, regs, 2);
> > + if (ret < 0) {
> > + dev_err(&anx7688->client->dev,
> > + "Failed to read bandwidth/lane count\n");
> > + return false;
> > + }
> > + dpbw = regs[0];
> > + lanecount = regs[1];
>
>
> Are these values hw invariant? Or they are result of cable probe/training?
>
> I
[PATCH] drm/qxl: don't take vga ports on rev5+
qemu 5.0 introduces a new qxl hardware revision 5. Unlike revision 4
(and below) the device doesn't switch back into vga compatibility mode
when someone touches the vga ports. So we don't have to reserve the
vga ports any more to avoid that happening.
Signed-off-by: Gerd Hoffmann
---
drivers/gpu/drm/qxl/qxl_drv.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/qxl/qxl_drv.c b/drivers/gpu/drm/qxl/qxl_drv.c
index 4fda3f9b29f4..afea743989dd 100644
--- a/drivers/gpu/drm/qxl/qxl_drv.c
+++ b/drivers/gpu/drm/qxl/qxl_drv.c
@@ -93,7 +93,7 @@ qxl_pci_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (ret)
goto disable_pci;
- if (is_vga(pdev)) {
+ if (is_vga(pdev) && pdev->revision < 5) {
ret = vga_get_interruptible(pdev, VGA_RSRC_LEGACY_IO);
if (ret) {
DRM_ERROR("can't get legacy vga ioports\n");
@@ -124,7 +124,7 @@ qxl_pci_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
unload:
qxl_device_fini(qdev);
put_vga:
- if (is_vga(pdev))
+ if (is_vga(pdev) && pdev->revision < 5)
vga_put(pdev, VGA_RSRC_LEGACY_IO);
disable_pci:
pci_disable_device(pdev);
@@ -155,7 +155,7 @@ qxl_pci_remove(struct pci_dev *pdev)
drm_dev_unregister(dev);
drm_atomic_helper_shutdown(dev);
- if (is_vga(pdev))
+ if (is_vga(pdev) && pdev->revision < 5)
vga_put(pdev, VGA_RSRC_LEGACY_IO);
drm_dev_put(dev);
}
--
2.18.2
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Re: [RFC PATCH 2/6] drm/radeon: don't use ttm bo->offset
Am 13.02.20 um 14:28 schrieb Nirmoy: On 2/13/20 2:00 PM, Christian König wrote: Am 13.02.20 um 13:31 schrieb Nirmoy: On 2/13/20 1:18 PM, Christian König wrote: Looks like most of the patch is missing? We should have quite a number of uses of the BO offset in radeon or do all of those go through radeon_bo_gpu_offset? Compilation worked so I think all those(bo->offset) accesses went through radeon_bo_gpu_offset. Cool, than that is a lot easier to implement than I thought it would be. I assume you don't have Radeon hardware lying around to test this? If you can you give me a branch on the AMD (or public) servers I can give it at least a quick round of testing. huh it seems I have to rebase it a bit for drm/drm-next as it is based on our internal branch :/ You can access the branch at http://gitlab1.amd.com/nirmodas/linux/tree/ttm_clean.1 I will rebase this for drm-next in next version of the patch series. Actually you should probably base it on drm-misc-next instead. And additional to the already noted VRAM helpers the bochs driver fails to compile on your branch. The good news is that my old HD5670 still works with the radeon patch applied. So this patch is Reviewed-and-tested-by: Christian König . Regards, Christian. Christian. If yes then the change is much smaller than I thought i needs to be. Christian. Regards, Nirmoy ___ amd-gfx mailing list amd-...@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7CNirmoy.Das%40amd.com%7C60aa17c05a2f474663f008d7b084b550%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637171956342728389&sdata=I2n0yMXK5CtrG5tY9Q47igxJv9Onb%2FA7PBeLwrpPb54%3D&reserved=0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/print: Delete a few unused shouting macros
Hi Daniel.
On Fri, Feb 14, 2020 at 10:04:28AM +0100, Daniel Vetter wrote:
> We want to go over to the new lowercase ones, encourage that a bit
> more.
Thanks for doing this, one item less on my TODO list now.
>
> Cc: Jani Nikula
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/drm_managed.c | 21 +
Ups...
> include/drm/drm_print.h | 26 --
This part is:
Reviewed-by: Sam Ravnborg
Could you squash in this patch too?
Is simplifies the RATELIMITED stuff and limit it to what is used.
I can send a separate patch for this if you prefer.
Sam
diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
index fd6ba2532f50..ca7cee8e728a 100644
--- a/include/drm/drm_print.h
+++ b/include/drm/drm_print.h
@@ -383,25 +383,6 @@ void drm_dev_dbg(const struct device *dev, enum
drm_debug_category category,
#define DRM_DEV_DEBUG_KMS(dev, fmt, ...) \
drm_dev_dbg(dev, DRM_UT_KMS, fmt, ##__VA_ARGS__)
-#define _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, category, fmt, ...) \
-({ \
- static DEFINE_RATELIMIT_STATE(_rs, \
- DEFAULT_RATELIMIT_INTERVAL, \
- DEFAULT_RATELIMIT_BURST); \
- if (__ratelimit(&_rs)) \
- drm_dev_dbg(dev, category, fmt, ##__VA_ARGS__); \
-})
-
-/**
- * Rate limited debug output. Like DRM_DEBUG() but won't flood the log.
- *
- * @dev: device pointer
- * @fmt: printf() like format string.
- */
-#define DRM_DEV_DEBUG_KMS_RATELIMITED(dev, fmt, ...) \
- _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, DRM_UT_KMS, \
- fmt, ##__VA_ARGS__)
-
/*
* struct drm_device based logging
*
@@ -525,7 +506,13 @@ void __drm_err(const char *format, ...);
#define DRM_DEBUG_KMS_RATELIMITED(fmt, ...)\
- DRM_DEV_DEBUG_KMS_RATELIMITED(NULL, fmt, ##__VA_ARGS__)
+({ \
+ static DEFINE_RATELIMIT_STATE(_rs, \
+ DEFAULT_RATELIMIT_INTERVAL, \
+ DEFAULT_RATELIMIT_BURST); \
+ if (__ratelimit(&_rs)) \
+ drm_dev_dbg(NULL, DRM_UT_KMS, fmt, ##__VA_ARGS__); \
+})
/*
* struct drm_device based WARNs
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Re: [PATCH] drm/i915: Cast remain to unsigned long in eb_relocate_vma
On 2020-02-14 12:49 p.m., Jani Nikula wrote: > On Fri, 14 Feb 2020, Chris Wilson wrote: >> Quoting Jani Nikula (2020-02-14 06:36:15) >>> On Thu, 13 Feb 2020, Nathan Chancellor wrote: A recent commit in clang added -Wtautological-compare to -Wall, which is enabled for i915 after -Wtautological-compare is disabled for the rest of the kernel so we see the following warning on x86_64: ../drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1433:22: warning: result of comparison of constant 576460752303423487 with expression of type 'unsigned int' is always false [-Wtautological-constant-out-of-range-compare] if (unlikely(remain > N_RELOC(ULONG_MAX))) ^ ../include/linux/compiler.h:78:42: note: expanded from macro 'unlikely' # define unlikely(x)__builtin_expect(!!(x), 0) ^ 1 warning generated. It is not wrong in the case where ULONG_MAX > UINT_MAX but it does not account for the case where this file is built for 32-bit x86, where ULONG_MAX == UINT_MAX and this check is still relevant. Cast remain to unsigned long, which keeps the generated code the same (verified with clang-11 on x86_64 and GCC 9.2.0 on x86 and x86_64) and the warning is silenced so we can catch more potential issues in the future. Link: https://github.com/ClangBuiltLinux/linux/issues/778 Suggested-by: Michel Dänzer Signed-off-by: Nathan Chancellor >>> >>> Works for me as a workaround, >> >> But the whole point was that the compiler could see that it was >> impossible and not emit the code. Doesn't this break that? > > It seems that goal and the warning are fundamentally incompatible. Not really: if (sizeof(remain) >= sizeof(unsigned long) && unlikely(remain > N_RELOC(ULONG_MAX))) return -EINVAL; In contrast to the cast, this doesn't generate any machine code on 64-bit: https://godbolt.org/z/GmUE4S but still generates the same code on 32-bit: https://godbolt.org/z/hAoz8L -- Earthling Michel Dänzer | https://redhat.com Libre software enthusiast | Mesa and X developer ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH AUTOSEL 5.5 007/542] drm/qxl: Complete exception handling in qxl_device_init()
From: Markus Elfring
[ Upstream commit dbe3ad61dcebc49fe3efca70a0f752a95b4600f2 ]
A coccicheck run provided information like the following.
drivers/gpu/drm/qxl/qxl_kms.c:295:1-7: ERROR: missing iounmap;
ioremap on line 178 and execution via conditional on line 185
Generated by: scripts/coccinelle/free/iounmap.cocci
A jump target was specified in an if branch. The corresponding function
call did not release the desired system resource then.
Thus use the label “rom_unmap” instead to fix the exception handling
for this function implementation.
Fixes: 5043348a4969ae1661c008efe929abd0d76e3792 ("drm: qxl: Fix error handling
at qxl_device_init")
Signed-off-by: Markus Elfring
Link:
http://patchwork.freedesktop.org/patch/msgid/5e5ef9c4-4d85-3c93-cf28-42cfcb5b0...@web.de
Signed-off-by: Gerd Hoffmann
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/qxl/qxl_kms.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/qxl/qxl_kms.c b/drivers/gpu/drm/qxl/qxl_kms.c
index 611cbe7aee690..bfc1631093e9b 100644
--- a/drivers/gpu/drm/qxl/qxl_kms.c
+++ b/drivers/gpu/drm/qxl/qxl_kms.c
@@ -184,7 +184,7 @@ int qxl_device_init(struct qxl_device *qdev,
if (!qxl_check_device(qdev)) {
r = -ENODEV;
- goto surface_mapping_free;
+ goto rom_unmap;
}
r = qxl_bo_init(qdev);
--
2.20.1
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[PATCH AUTOSEL 5.5 024/542] drm: rcar-du: Recognize "renesas, vsps" in addition to "vsps"
From: Geert Uytterhoeven
[ Upstream commit 7b627ce80fbd05885b27f711a5f9820f2b40749a ]
The Renesas-specific "vsps" property lacks a vendor prefix.
Add a "renesas," prefix to comply with DT best practises.
Retain backward compatibility with old DTBs by falling back to "vsps"
when needed.
Fixes: 6d62ef3ac30be756 ("drm: rcar-du: Expose the VSP1 compositor through KMS
planes")
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Laurent Pinchart
Signed-off-by: Laurent Pinchart
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/rcar-du/rcar_du_kms.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index 0d59f390de19a..662d8075f4116 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -542,6 +542,7 @@ static int rcar_du_properties_init(struct rcar_du_device
*rcdu)
static int rcar_du_vsps_init(struct rcar_du_device *rcdu)
{
const struct device_node *np = rcdu->dev->of_node;
+ const char *vsps_prop_name = "renesas,vsps";
struct of_phandle_args args;
struct {
struct device_node *np;
@@ -557,15 +558,21 @@ static int rcar_du_vsps_init(struct rcar_du_device *rcdu)
* entry contains a pointer to the VSP DT node and a bitmask of the
* connected DU CRTCs.
*/
- cells = of_property_count_u32_elems(np, "vsps") / rcdu->num_crtcs - 1;
+ ret = of_property_count_u32_elems(np, vsps_prop_name);
+ if (ret < 0) {
+ /* Backward compatibility with old DTBs. */
+ vsps_prop_name = "vsps";
+ ret = of_property_count_u32_elems(np, vsps_prop_name);
+ }
+ cells = ret / rcdu->num_crtcs - 1;
if (cells > 1)
return -EINVAL;
for (i = 0; i < rcdu->num_crtcs; ++i) {
unsigned int j;
- ret = of_parse_phandle_with_fixed_args(np, "vsps", cells, i,
- &args);
+ ret = of_parse_phandle_with_fixed_args(np, vsps_prop_name,
+ cells, i, &args);
if (ret < 0)
goto error;
@@ -587,8 +594,8 @@ static int rcar_du_vsps_init(struct rcar_du_device *rcdu)
/*
* Store the VSP pointer and pipe index in the CRTC. If the
-* second cell of the 'vsps' specifier isn't present, default
-* to 0 to remain compatible with older DT bindings.
+* second cell of the 'renesas,vsps' specifier isn't present,
+* default to 0 to remain compatible with older DT bindings.
*/
rcdu->crtcs[i].vsp = &rcdu->vsps[j];
rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0;
--
2.20.1
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[PATCH AUTOSEL 5.5 001/542] drm/amdgpu: remove set but not used variable 'mc_shared_chmap' from 'gfx_v6_0.c' and 'gfx_v7_0.c'
From: yu kuai
[ Upstream commit 747a397d394fac0001e4b3c03d7dce3a118af567 ]
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c: In function
‘gfx_v6_0_constants_init’:
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c:1579:6: warning: variable
‘mc_shared_chmap’ set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c: In function
‘gfx_v7_0_gpu_early_init’:
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:4262:6: warning: variable
‘mc_shared_chmap’ set but not used [-Wunused-but-set-variable]
Fixes: 2cd46ad22383 ("drm/amdgpu: add graphic pipeline implementation for si
v8")
Fixes: d93f3ca706b8 ("drm/amdgpu/gfx7: rework gpu_init()")
Signed-off-by: yu kuai
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 3 +--
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 3 +--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 7f0a63628c43a..31f44d05e606d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1576,7 +1576,7 @@ static void gfx_v6_0_config_init(struct amdgpu_device
*adev)
static void gfx_v6_0_constants_init(struct amdgpu_device *adev)
{
u32 gb_addr_config = 0;
- u32 mc_shared_chmap, mc_arb_ramcfg;
+ u32 mc_arb_ramcfg;
u32 sx_debug_1;
u32 hdp_host_path_cntl;
u32 tmp;
@@ -1678,7 +1678,6 @@ static void gfx_v6_0_constants_init(struct amdgpu_device
*adev)
WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK |
BIF_FB_EN__FB_WRITE_EN_MASK);
- mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index d92e92e5d50b7..8f20a5dd44fe7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4258,7 +4258,7 @@ static int gfx_v7_0_late_init(void *handle)
static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
{
u32 gb_addr_config;
- u32 mc_shared_chmap, mc_arb_ramcfg;
+ u32 mc_arb_ramcfg;
u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
u32 tmp;
@@ -4335,7 +4335,6 @@ static void gfx_v7_0_gpu_early_init(struct amdgpu_device
*adev)
break;
}
- mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
--
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[PATCH AUTOSEL 5.5 003/542] drm/dp_mst: fix multiple frees of tx->bytes
From: Colin Ian King
[ Upstream commit 2c8bc91488fc57438c43b3bb19deb7fdbc1e5119 ]
Currently tx->bytes is being freed r->num_transactions number of
times because tx is not being set correctly. Fix this by setting
tx to &r->transactions[i] so that the correct objects are being
freed on each loop iteration.
Addresses-Coverity: ("Double free")
Fixes: 2f015ec6eab6 ("drm/dp_mst: Add sideband down request tracing +
selftests")
Signed-off-by: Colin Ian King
Signed-off-by: Lyude Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20191120173509.347490-1-colin.k...@canonical.com
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/drm_dp_mst_topology.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 141ba31cf5486..cfee59e9c85e5 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -517,8 +517,10 @@ drm_dp_decode_sideband_req(const struct
drm_dp_sideband_msg_tx *raw,
}
if (failed) {
- for (i = 0; i < r->num_transactions; i++)
+ for (i = 0; i < r->num_transactions; i++) {
+ tx = &r->transactions[i];
kfree(tx->bytes);
+ }
return -ENOMEM;
}
--
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[PATCH AUTOSEL 5.5 002/542] drm/gma500: Fixup fbdev stolen size usage evaluation
From: Paul Kocialkowski
[ Upstream commit fd1a5e521c3c083bb43ea731aae0f8b95f12b9bd ]
psbfb_probe performs an evaluation of the required size from the stolen
GTT memory, but gets it wrong in two distinct ways:
- The resulting size must be page-size-aligned;
- The size to allocate is derived from the surface dimensions, not the fb
dimensions.
When two connectors are connected with different modes, the smallest will
be stored in the fb dimensions, but the size that needs to be allocated must
match the largest (surface) dimensions. This is what is used in the actual
allocation code.
Fix this by correcting the evaluation to conform to the two points above.
It allows correctly switching to 16bpp when one connector is e.g. 1920x1080
and the other is 1024x768.
Signed-off-by: Paul Kocialkowski
Signed-off-by: Patrik Jakobsson
Link:
https://patchwork.freedesktop.org/patch/msgid/20191107153048.843881-1-paul.kocialkow...@bootlin.com
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/gma500/framebuffer.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/gma500/framebuffer.c
b/drivers/gpu/drm/gma500/framebuffer.c
index 218f3bb15276e..90237abee0885 100644
--- a/drivers/gpu/drm/gma500/framebuffer.c
+++ b/drivers/gpu/drm/gma500/framebuffer.c
@@ -462,6 +462,7 @@ static int psbfb_probe(struct drm_fb_helper *helper,
container_of(helper, struct psb_fbdev, psb_fb_helper);
struct drm_device *dev = psb_fbdev->psb_fb_helper.dev;
struct drm_psb_private *dev_priv = dev->dev_private;
+ unsigned int fb_size;
int bytespp;
bytespp = sizes->surface_bpp / 8;
@@ -471,8 +472,11 @@ static int psbfb_probe(struct drm_fb_helper *helper,
/* If the mode will not fit in 32bit then switch to 16bit to get
a console on full resolution. The X mode setting server will
allocate its own 32bit GEM framebuffer */
- if (ALIGN(sizes->fb_width * bytespp, 64) * sizes->fb_height >
- dev_priv->vram_stolen_size) {
+ fb_size = ALIGN(sizes->surface_width * bytespp, 64) *
+ sizes->surface_height;
+ fb_size = ALIGN(fb_size, PAGE_SIZE);
+
+ if (fb_size > dev_priv->vram_stolen_size) {
sizes->surface_bpp = 16;
sizes->surface_depth = 16;
}
--
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[PATCH AUTOSEL 5.5 037/542] drm/mipi_dbi: Fix off-by-one bugs in mipi_dbi_blank()
From: Geert Uytterhoeven
[ Upstream commit 2ce18249af5a28031b3f909cfafccc88ea966c9d ]
When configuring the frame memory window, the last column and row
numbers are written to the column resp. page address registers. These
numbers are thus one less than the actual window width resp. height.
While this is handled correctly in mipi_dbi_fb_dirty() since commit
03ceb1c8dfd1e293 ("drm/tinydrm: Fix setting of the column/page end
addresses."), it is not in mipi_dbi_blank(). The latter still forgets
to subtract one when calculating the most significant bytes of the
column and row numbers, thus programming wrong values when the display
width or height is a multiple of 256.
Fixes: 02dd95fe31693626 ("drm/tinydrm: Add MIPI DBI support")
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Noralf Trønnes
Link:
https://patchwork.freedesktop.org/patch/msgid/20191230130604.31006-1-geert+rene...@glider.be
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/drm_mipi_dbi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_mipi_dbi.c b/drivers/gpu/drm/drm_mipi_dbi.c
index e34058c721bec..16bff1be4b8ac 100644
--- a/drivers/gpu/drm/drm_mipi_dbi.c
+++ b/drivers/gpu/drm/drm_mipi_dbi.c
@@ -367,9 +367,9 @@ static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev)
memset(dbidev->tx_buf, 0, len);
mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, 0, 0,
-(width >> 8) & 0xFF, (width - 1) & 0xFF);
+((width - 1) >> 8) & 0xFF, (width - 1) & 0xFF);
mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, 0, 0,
-(height >> 8) & 0xFF, (height - 1) & 0xFF);
+((height - 1) >> 8) & 0xFF, (height - 1) & 0xFF);
mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START,
(u8 *)dbidev->tx_buf, len);
--
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[PATCH AUTOSEL 5.5 006/542] drm/virtio: fix byteorder handling in virtio_gpu_cmd_transfer_{from, to}_host_3d functions
From: Gerd Hoffmann
[ Upstream commit 1dc3485247170d3b88a21cadee7f7da1f0433495 ]
Be consistent with the rest of the code base.
No functional change.
v2:
- fix sparse warnings for virtio_gpu_cmd_transfer_to_host_2d call.
- move convert_to_hw_box helper function.
Signed-off-by: Gerd Hoffmann
Reviewed-by: Gurchetan Singh
Link:
http://patchwork.freedesktop.org/patch/msgid/20191023062539.11728-2-kra...@redhat.com
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/virtio/virtgpu_drv.h | 5 +++--
drivers/gpu/drm/virtio/virtgpu_ioctl.c | 22 +++---
drivers/gpu/drm/virtio/virtgpu_vq.c| 19 +++
3 files changed, 21 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.h
b/drivers/gpu/drm/virtio/virtgpu_drv.h
index 0b56ba005e253..eedae2a7b532d 100644
--- a/drivers/gpu/drm/virtio/virtgpu_drv.h
+++ b/drivers/gpu/drm/virtio/virtgpu_drv.h
@@ -38,6 +38,7 @@
#include
#include
#include
+#include
#define DRIVER_NAME "virtio_gpu"
#define DRIVER_DESC "virtio GPU"
@@ -312,13 +313,13 @@ void virtio_gpu_cmd_submit(struct virtio_gpu_device
*vgdev,
void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
uint32_t ctx_id,
uint64_t offset, uint32_t level,
- struct virtio_gpu_box *box,
+ struct drm_virtgpu_3d_box *box,
struct virtio_gpu_object_array *objs,
struct virtio_gpu_fence *fence);
void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
uint32_t ctx_id,
uint64_t offset, uint32_t level,
- struct virtio_gpu_box *box,
+ struct drm_virtgpu_3d_box *box,
struct virtio_gpu_object_array *objs,
struct virtio_gpu_fence *fence);
void
diff --git a/drivers/gpu/drm/virtio/virtgpu_ioctl.c
b/drivers/gpu/drm/virtio/virtgpu_ioctl.c
index 9af1ec62434f2..205ec4abae2b9 100644
--- a/drivers/gpu/drm/virtio/virtgpu_ioctl.c
+++ b/drivers/gpu/drm/virtio/virtgpu_ioctl.c
@@ -33,17 +33,6 @@
#include "virtgpu_drv.h"
-static void convert_to_hw_box(struct virtio_gpu_box *dst,
- const struct drm_virtgpu_3d_box *src)
-{
- dst->x = cpu_to_le32(src->x);
- dst->y = cpu_to_le32(src->y);
- dst->z = cpu_to_le32(src->z);
- dst->w = cpu_to_le32(src->w);
- dst->h = cpu_to_le32(src->h);
- dst->d = cpu_to_le32(src->d);
-}
-
static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
@@ -304,7 +293,6 @@ static int virtio_gpu_transfer_from_host_ioctl(struct
drm_device *dev,
struct virtio_gpu_fence *fence;
int ret;
u32 offset = args->offset;
- struct virtio_gpu_box box;
if (vgdev->has_virgl_3d == false)
return -ENOSYS;
@@ -317,8 +305,6 @@ static int virtio_gpu_transfer_from_host_ioctl(struct
drm_device *dev,
if (ret != 0)
goto err_put_free;
- convert_to_hw_box(&box, &args->box);
-
fence = virtio_gpu_fence_alloc(vgdev);
if (!fence) {
ret = -ENOMEM;
@@ -326,7 +312,7 @@ static int virtio_gpu_transfer_from_host_ioctl(struct
drm_device *dev,
}
virtio_gpu_cmd_transfer_from_host_3d
(vgdev, vfpriv->ctx_id, offset, args->level,
-&box, objs, fence);
+&args->box, objs, fence);
dma_fence_put(&fence->f);
return 0;
@@ -345,7 +331,6 @@ static int virtio_gpu_transfer_to_host_ioctl(struct
drm_device *dev, void *data,
struct drm_virtgpu_3d_transfer_to_host *args = data;
struct virtio_gpu_object_array *objs;
struct virtio_gpu_fence *fence;
- struct virtio_gpu_box box;
int ret;
u32 offset = args->offset;
@@ -353,11 +338,10 @@ static int virtio_gpu_transfer_to_host_ioctl(struct
drm_device *dev, void *data,
if (objs == NULL)
return -ENOENT;
- convert_to_hw_box(&box, &args->box);
if (!vgdev->has_virgl_3d) {
virtio_gpu_cmd_transfer_to_host_2d
(vgdev, offset,
-box.w, box.h, box.x, box.y,
+args->box.w, args->box.h, args->box.x, args->box.y,
objs, NULL);
} else {
ret = virtio_gpu_array_lock_resv(objs);
@@ -372,7 +356,7 @@ static int virtio_gpu_transfer_to_host_ioctl(struct
drm_device *dev, void *data,
virtio_gpu_cmd_transfer_to_host_3d
(vgdev,
vfpriv ? vfpriv->ctx_id : 0, offset
[PATCH AUTOSEL 5.5 029/542] drm/amd/display: Map ODM memory correctly when doing ODM combine
From: Nikola Cornij
[ Upstream commit ec5b356c58941bb8930858155d9ce14ceb3d30a0 ]
[why]
Up to 4 ODM memory pieces are required per ODM combine and cannot
overlap, i.e. each ODM "session" has to use its own memory pieces.
The ODM-memory mapping is currently broken for generic case.
The maximum number of memory pieces is ASIC-dependent, but it's always
big enough to satisfy maximum number of ODM combines. Memory pieces
are mapped as a bit-map, i.e. one memory piece corresponds to one bit.
The OPTC doing ODM needs to select memory pieces by setting the
corresponding bits, making sure there's no overlap with other OPTC
instances that might be doing ODM.
The current mapping works only for OPTC instance indexes smaller than
3. For instance indexes 3 and up it practically maps no ODM memory,
causing black, gray or white screen in display configs that include
ODM on OPTC instance 3 or up.
[how]
Statically map two unique ODM memory pieces for each OPTC instance
and piece them together when programming ODM combine mode.
Signed-off-by: Nikola Cornij
Reviewed-by: Jun Lei
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c| 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index 3b613fb93ef80..0162d3ffe268f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -233,12 +233,13 @@ void optc2_set_odm_combine(struct timing_generator *optc,
int *opp_id, int opp_c
struct dc_crtc_timing *timing)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
- /* 2 pieces of memory required for up to 5120 displays, 4 for up to
8192 */
int mpcc_hactive = (timing->h_addressable + timing->h_border_left +
timing->h_border_right)
/ opp_cnt;
- int memory_mask = mpcc_hactive <= 2560 ? 0x3 : 0xf;
+ uint32_t memory_mask;
uint32_t data_fmt = 0;
+ ASSERT(opp_cnt == 2);
+
/* TODO: In pseudocode but does not affect maximus, delete comment if
we dont need on asic
* REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
* Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position
before DP frame start
@@ -246,9 +247,17 @@ void optc2_set_odm_combine(struct timing_generator *optc,
int *opp_id, int opp_c
* MASTER_UPDATE_LOCK_DB_X, 160,
* MASTER_UPDATE_LOCK_DB_Y, 240);
*/
+
+ /* 2 pieces of memory required for up to 5120 displays, 4 for up to
8192,
+* however, for ODM combine we can simplify by always using 4.
+* To make sure there's no overlap, each instance "reserves" 2 memories
and
+* they are uniquely combined here.
+*/
+ memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
+
if (REG(OPTC_MEMORY_CONFIG))
REG_SET(OPTC_MEMORY_CONFIG, 0,
- OPTC_MEM_SEL, memory_mask << (optc->inst * 4));
+ OPTC_MEM_SEL, memory_mask);
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
data_fmt = 1;
@@ -257,7 +266,6 @@ void optc2_set_odm_combine(struct timing_generator *optc,
int *opp_id, int opp_c
REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
- ASSERT(opp_cnt == 2);
REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
OPTC_NUM_OF_INPUT_SEGMENT, 1,
OPTC_SEG0_SRC_SEL, opp_id[0],
--
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[PATCH AUTOSEL 5.5 038/542] drm/msm/adreno: fix zap vs no-zap handling
From: Rob Clark
[ Upstream commit 15ab987c423df561e0949d77fb5043921ae59956 ]
We can have two cases, when it comes to "zap" fw. Either the fw
requires zap fw to take the GPU out of secure mode at boot, or it does
not and we can write RBBM_SECVID_TRUST_CNTL directly. Previously we
decided based on whether zap fw load succeeded, but this is not a great
plan because:
1) we could have zap fw in the filesystem on a device where it is not
required
2) we could have the inverse case
Instead, shift to deciding based on whether we have a 'zap-shader' node
in dt. In practice, there is only one device (currently) with upstream
dt that does not use zap (cheza), and it already has a /delete-node/ for
the zap-shader node.
Fixes: abccb9fe3267 ("drm/msm/a6xx: Add zap shader load")
Signed-off-by: Rob Clark
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 11 +--
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 +--
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index b02e2042547f6..7d9e63e20dedd 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -753,11 +753,18 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
gpu->funcs->flush(gpu, gpu->rb[0]);
if (!a5xx_idle(gpu, gpu->rb[0]))
return -EINVAL;
- } else {
- /* Print a warning so if we die, we know why */
+ } else if (ret == -ENODEV) {
+ /*
+* This device does not use zap shader (but print a warning
+* just in case someone got their dt wrong.. hopefully they
+* have a debug UART to realize the error of their ways...
+* if you mess this up you are about to crash horribly)
+*/
dev_warn_once(gpu->dev->dev,
"Zap shader not enabled - using SECVID_TRUST_CNTL
instead\n");
gpu_write(gpu, REG_A5XX_RBBM_SECVID_TRUST_CNTL, 0x0);
+ } else {
+ return ret;
}
/* Last step - yield the ringbuffer */
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index dc8ec2c94301b..686c34d706b0d 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -537,12 +537,19 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
a6xx_flush(gpu, gpu->rb[0]);
if (!a6xx_idle(gpu, gpu->rb[0]))
return -EINVAL;
- } else {
- /* Print a warning so if we die, we know why */
+ } else if (ret == -ENODEV) {
+ /*
+* This device does not use zap shader (but print a warning
+* just in case someone got their dt wrong.. hopefully they
+* have a debug UART to realize the error of their ways...
+* if you mess this up you are about to crash horribly)
+*/
dev_warn_once(gpu->dev->dev,
"Zap shader not enabled - using SECVID_TRUST_CNTL
instead\n");
gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0);
ret = 0;
+ } else {
+ return ret;
}
out:
--
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[PATCH AUTOSEL 5.5 039/542] pxa168fb: Fix the function used to release some memory in an error handling path
From: Christophe JAILLET
[ Upstream commit 3c911fe799d1c338d94b78e7182ad452c37af897 ]
In the probe function, some resources are allocated using 'dma_alloc_wc()',
they should be released with 'dma_free_wc()', not 'dma_free_coherent()'.
We already use 'dma_free_wc()' in the remove function, but not in the
error handling path of the probe function.
Also, remove a useless 'PAGE_ALIGN()'. 'info->fix.smem_len' is already
PAGE_ALIGNed.
Fixes: 638772c7553f ("fb: add support of LCD display controller on pxa168/910
(base layer)")
Signed-off-by: Christophe JAILLET
Reviewed-by: Lubomir Rintel
CC: YueHaibing
Signed-off-by: Bartlomiej Zolnierkiewicz
Link:
https://patchwork.freedesktop.org/patch/msgid/20190831100024.3248-1-christophe.jail...@wanadoo.fr
Signed-off-by: Sasha Levin
---
drivers/video/fbdev/pxa168fb.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/video/fbdev/pxa168fb.c b/drivers/video/fbdev/pxa168fb.c
index 1410f476e135d..1fc50fc0694bc 100644
--- a/drivers/video/fbdev/pxa168fb.c
+++ b/drivers/video/fbdev/pxa168fb.c
@@ -766,8 +766,8 @@ static int pxa168fb_probe(struct platform_device *pdev)
failed_free_clk:
clk_disable_unprepare(fbi->clk);
failed_free_fbmem:
- dma_free_coherent(fbi->dev, info->fix.smem_len,
- info->screen_base, fbi->fb_start_dma);
+ dma_free_wc(fbi->dev, info->fix.smem_len,
+ info->screen_base, fbi->fb_start_dma);
failed_free_info:
kfree(info);
@@ -801,7 +801,7 @@ static int pxa168fb_remove(struct platform_device *pdev)
irq = platform_get_irq(pdev, 0);
- dma_free_wc(fbi->dev, PAGE_ALIGN(info->fix.smem_len),
+ dma_free_wc(fbi->dev, info->fix.smem_len,
info->screen_base, info->fix.smem_start);
clk_disable_unprepare(fbi->clk);
--
2.20.1
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Re: [PATCH 1/2] dt-bindings: display: sun4i-tcon: Add LVDS Dual Link property
Hi Maxime, On Fri, Feb 14, 2020 at 04:44:05PM +0100, Maxime Ripard wrote: > On Fri, Feb 14, 2020 at 03:10:25PM +0200, Laurent Pinchart wrote: > > On Fri, Feb 14, 2020 at 01:32:43PM +0100, Maxime Ripard wrote: > > > SoCs that have multiple TCONs can use the two set of pins on the first > > > TCON > > > to drive a dual-link display. Add a property to enable the dual link. > > > > > > Signed-off-by: Maxime Ripard > > > --- > > > .../bindings/display/allwinner,sun4i-a10-tcon.yaml | 7 +++ > > > 1 file changed, 7 insertions(+) > > > > > > diff --git > > > a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml > > > b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml > > > index 86ad617d2327..aa6dd8409dbc 100644 > > > --- > > > a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml > > > +++ > > > b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml > > > @@ -105,6 +105,13 @@ properties: > > > - const: edp > > > - const: lvds > > > > > > + allwinner,lvds-dual-link: > > > +type: boolean > > > +description: | > > > + On a SoC with two TCON with LVDS support, the first TCON can > > > + operate over both pins sets to output in a dual-link setup. This > > > + will be triggered by setting this property. > > > > Could you maybe provide an example of how this property is supposed to > > be used ? I'm especially wondering what ports are used in that case and > > how they're connected. > > It's pretty trivial to support, it's only a property to set on the > encoder node itself. > > I'm not really sure what you meant by your question with the ports > though :/ I assume that, in the single-link case, you have two TCON instances that operate independently, each of them with one port that models an LVDS connection to a panel. In the dual-link mode, how does that look like ? Does the TCON instance that operate in dual-link mode have two ports in DT ? There are two physical ports, so I think it makes sense to always have two ports in DT. That's what we're doing for the LVDS encoders on R-Car Gen3, in order to specify in DT which LVDS input of the dual-link panel is connected to which LVDS output of the SoC. That allows configuring the LVDS encoder to send the even and odd pixels on the right port. -- Regards, Laurent Pinchart ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH AUTOSEL 5.5 080/542] drm/amd/display: Clear state after exiting fixed active VRR state
From: Amanda Liu
[ Upstream commit 6f8f76444baf405bacb0591d97549a71a9aaa1ac ]
[why]
Upon exiting a fixed active VRR state, the state isn't cleared. This
leads to the variable VRR range to be calculated incorrectly.
[how]
Set fixed active state to false when updating vrr params
Signed-off-by: Amanda Liu
Reviewed-by: Anthony Koo
Acked-by: Harry Wentland
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 5437b50e9f90d..d9ea4ae690af6 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -807,6 +807,7 @@ void mod_freesync_build_vrr_params(struct mod_freesync
*mod_freesync,
2 * in_out_vrr->min_refresh_in_uhz)
in_out_vrr->btr.btr_enabled = false;
+ in_out_vrr->fixed.fixed_active = false;
in_out_vrr->btr.btr_active = false;
in_out_vrr->btr.inserted_duration_in_us = 0;
in_out_vrr->btr.frames_to_insert = 0;
@@ -826,6 +827,7 @@ void mod_freesync_build_vrr_params(struct mod_freesync
*mod_freesync,
in_out_vrr->adjust.v_total_max = stream->timing.v_total;
} else if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
refresh_range >= MIN_REFRESH_RANGE_IN_US) {
+
in_out_vrr->adjust.v_total_min =
calc_v_total_from_refresh(stream,
in_out_vrr->max_refresh_in_uhz);
--
2.20.1
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[PATCH AUTOSEL 5.5 074/542] drm/nouveau/nouveau: fix incorrect sizeof on args.src an args.dst
From: Colin Ian King
[ Upstream commit f42e4b337b327b1336c978c4b5174990a25f68a0 ]
The sizeof is currently on args.src and args.dst and should be on
*args.src and *args.dst. Fortunately these sizes just so happen
to be the same size so it worked, however, this should be fixed
and it also cleans up static analysis warnings
Addresses-Coverity: ("sizeof not portable")
Fixes: f268307ec7c7 ("nouveau: simplify nouveau_dmem_migrate_vma")
Signed-off-by: Colin Ian King
Signed-off-by: Ben Skeggs
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/nouveau/nouveau_dmem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_dmem.c
b/drivers/gpu/drm/nouveau/nouveau_dmem.c
index fa14399415965..0ad5d87b5a8e5 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dmem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dmem.c
@@ -635,10 +635,10 @@ nouveau_dmem_migrate_vma(struct nouveau_drm *drm,
unsigned long c, i;
int ret = -ENOMEM;
- args.src = kcalloc(max, sizeof(args.src), GFP_KERNEL);
+ args.src = kcalloc(max, sizeof(*args.src), GFP_KERNEL);
if (!args.src)
goto out;
- args.dst = kcalloc(max, sizeof(args.dst), GFP_KERNEL);
+ args.dst = kcalloc(max, sizeof(*args.dst), GFP_KERNEL);
if (!args.dst)
goto out_free_src;
--
2.20.1
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[PATCH AUTOSEL 5.5 070/542] drm/amdgpu/sriov: workaround on rev_id for Navi12 under sriov
From: Tiecheng Zhou [ Upstream commit df5e984c8bd414561c320d6cbbb66d53abf4c7e2 ] guest vm gets 0x when reading RCC_DEV0_EPF0_STRAP0, as a consequence, the rev_id and external_rev_id are wrong. workaround it by hardcoding the rev_id to 0, which is the default value. v2. add comment in the code Signed-off-by: Tiecheng Zhou Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdgpu/nv.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 0ba66bef57468..de40bf12c4a8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -701,6 +701,12 @@ static int nv_common_early_init(void *handle) adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG | AMD_PG_SUPPORT_ATHUB; + /* guest vm gets 0x when reading RCC_DEV0_EPF0_STRAP0, +* as a consequence, the rev_id and external_rev_id are wrong. +* workaround it by hardcoding rev_id to 0 (default value). +*/ + if (amdgpu_sriov_vf(adev)) + adev->rev_id = 0; adev->external_rev_id = adev->rev_id + 0xa; break; default: -- 2.20.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH AUTOSEL 5.5 117/542] drm/amd/display: Retrain dongles when SINK_COUNT becomes non-zero
From: Harry Wentland
[ Upstream commit 3eb6d7aca53d81ce888624f09cd44dc0302161e8 ]
[WHY]
Two years ago the patch referenced by the Fixes tag stopped running
dp_verify_link_cap_with_retries during DP detection when the reason
for the detection was a short-pulse interrupt. This effectively meant
that we were no longer doing the verify_link_cap training on active
dongles when their SINK_COUNT changed from 0 to 1.
A year ago this was partly remedied with:
commit 80adaebd2d41 ("drm/amd/display: Don't skip link training for empty
dongle")
This made sure that we trained the dongle on initial hotplug (without
connected downstream devices).
This is all fine and dandy if it weren't for the fact that there are
some dongles on the market that don't like link training when SINK_COUNT
is 0 These dongles will in fact indicate a SINK_COUNT of 0 immediately
after hotplug, even when a downstream device is connected, and then
trigger a shortpulse interrupt indicating a SINK_COUNT change to 1.
In order to play nicely we will need our policy to not link train an
active DP dongle when SINK_COUNT is 0 but ensure we train it when the
SINK_COUNT changes to 1.
[HOW]
Call dp_verify_link_cap_with_retries on detection even when the detection
is triggered from a short pulse interrupt.
With this change we can also revert this commit which we'll do in a separate
follow-up change:
commit 80adaebd2d41 ("drm/amd/display: Don't skip link training for empty
dongle")
Fixes: 0301ccbaf67d ("drm/amd/display: DP Compliance 400.1.1 failure")
Suggested-by: Louis Li
Tested-by: Louis Li
Cc: Wenjing Liu
Cc: Hersen Wu
Cc: Eric Yang
Reviewed-by: Wenjing Liu
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 4619f94f0ac78..70846ae7d854d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -968,8 +968,7 @@ static bool dc_link_detect_helper(struct dc_link *link,
same_edid = is_same_edid(&prev_sink->dc_edid,
&sink->dc_edid);
if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
- sink_caps.transaction_type ==
DDC_TRANSACTION_TYPE_I2C_OVER_AUX &&
- reason != DETECT_REASON_HPDRX) {
+ sink_caps.transaction_type ==
DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
/*
* TODO debug why Dell 2413 doesn't like
* two link trainings
--
2.20.1
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[PATCH AUTOSEL 5.5 095/542] backlight: qcom-wled: Fix unsigned comparison to zero
From: Chen Zhou
[ Upstream commit 7af43a76695db71a57203793fb9dd3c81a5783b1 ]
Fixes coccicheck warning:
./drivers/video/backlight/qcom-wled.c:1104:5-15:
WARNING: Unsigned expression compared with zero: string_len > 0
The unsigned variable string_len is assigned a return value from the call
to of_property_count_elems_of_size(), which may return negative error code.
Fixes: 775d2ffb4af6 ("backlight: qcom-wled: Restructure the driver for WLED3")
Signed-off-by: Chen Zhou
Reviewed-by: Bjorn Andersson
Reviewed-by: Daniel Thompson
Reviewed-by: Kiran Gunda
Signed-off-by: Lee Jones
Signed-off-by: Sasha Levin
---
drivers/video/backlight/qcom-wled.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/backlight/qcom-wled.c
b/drivers/video/backlight/qcom-wled.c
index d46052d8ff415..3d276b30a78c9 100644
--- a/drivers/video/backlight/qcom-wled.c
+++ b/drivers/video/backlight/qcom-wled.c
@@ -956,8 +956,8 @@ static int wled_configure(struct wled *wled, int version)
struct wled_config *cfg = &wled->cfg;
struct device *dev = wled->dev;
const __be32 *prop_addr;
- u32 size, val, c, string_len;
- int rc, i, j;
+ u32 size, val, c;
+ int rc, i, j, string_len;
const struct wled_u32_opts *u32_opts = NULL;
const struct wled_u32_opts wled3_opts[] = {
--
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[PATCH AUTOSEL 5.5 131/542] drm/amdkfd: Fix a bug in SDMA RLC queue counting under HWS mode
From: Yong Zhao
[ Upstream commit f38abc15d157b7b31fa7f651dc8bf92858c963f8 ]
The sdma_queue_count increment should be done before
execute_queues_cpsch(), which calls pm_calc_rlib_size() where
sdma_queue_count is used to calculate whether over_subscription is
triggered.
With the previous code, when a SDMA queue is created,
compute_queue_count in pm_calc_rlib_size() is one more than the
actual compute queue number, because the queue_count has been
incremented while sdma_queue_count has not. This patch fixes that.
Signed-off-by: Yong Zhao
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 984c2f2b24b60..d128a8bbe19d0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1225,16 +1225,18 @@ static int create_queue_cpsch(struct
device_queue_manager *dqm, struct queue *q,
list_add(&q->list, &qpd->queues_list);
qpd->queue_count++;
+
+ if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
+ dqm->sdma_queue_count++;
+ else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
+ dqm->xgmi_sdma_queue_count++;
+
if (q->properties.is_active) {
dqm->queue_count++;
retval = execute_queues_cpsch(dqm,
KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
}
- if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
- dqm->sdma_queue_count++;
- else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
- dqm->xgmi_sdma_queue_count++;
/*
* Unconditionally increment this counter, regardless of the queue's
* type or whether the queue is active.
--
2.20.1
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[PATCH AUTOSEL 5.5 144/542] drm/amd/powerplay: remove set but not used variable 'vbios_version', 'data'
From: zhengbin
[ Upstream commit cb7709223b39287a020e92ff880d11d377dc53a1 ]
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c: In function
smu7_check_mc_firmware:
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c:4215:11: warning: variable
vbios_version set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c: In function
smu7_get_performance_level:
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c:5054:21: warning: variable
data set but not used [-Wunused-but-set-variable]
'vbios_version' is introduced by commit 599a7e9fe1b6 ("drm/amd/powerplay:
implement smu7 hwmgr to manager asics with smu ip version 7."),
but never used, so remove it.
'data' is introduced by commit f688b614b643 ("drm/amd/pp:
Implement get_performance_level for legacy dgpu"), but never used,
so remove it.
Reviewed-by: Evan Quan
Reported-by: Hulk Robot
Signed-off-by: zhengbin
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index f73dff68e7999..f754fbd70f687 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4238,7 +4238,6 @@ static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr)
{
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- uint32_t vbios_version;
uint32_t tmp;
/* Read MC indirect register offset 0x9F bits [3:0] to see
@@ -4247,7 +4246,6 @@ static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr)
*/
smu7_get_mc_microcode_version(hwmgr);
- vbios_version = hwmgr->microcode_version_info.MC & 0xf;
data->need_long_memory_training = false;
@@ -5077,13 +5075,11 @@ static int smu7_get_performance_level(struct pp_hwmgr
*hwmgr, const struct pp_hw
PHM_PerformanceLevel *level)
{
const struct smu7_power_state *ps;
- struct smu7_hwmgr *data;
uint32_t i;
if (level == NULL || hwmgr == NULL || state == NULL)
return -EINVAL;
- data = hwmgr->backend;
ps = cast_const_phw_smu7_power_state(state);
i = index > ps->performance_level_count - 1 ?
--
2.20.1
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[PATCH AUTOSEL 5.5 138/542] drm/amd/display: Renoir chroma viewport WA
From: Eric Yang
[ Upstream commit 1cad8ff7ecc6b70a062b8e8b74a0cd08c928341d ]
[Why]
For unknown reason, immediate flip with host VM translation on NV12
surface will underflow on last row of PTE.
[How]
Hack chroma viewport height to make fetch one more row of PTE.
Note that this will cause hubp underflow on all video underlay
cases, but the underflow is not user visible since it is in
blank region.
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +
.../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 65 ++-
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 1 +
3 files changed, 67 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 0416a17b0897c..320f4eeebf84c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -417,6 +417,8 @@ struct dc_debug_options {
bool cm_in_bypass;
#endif
int force_clock_mode;/*every mode change.*/
+
+ bool nv12_iflip_vm_wa;
};
struct dc_debug_data {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
index 2f5a5867e6749..1ddd6ae221558 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
@@ -164,6 +164,69 @@ static void hubp21_setup(
}
+void hubp21_set_viewport(
+ struct hubp *hubp,
+ const struct rect *viewport,
+ const struct rect *viewport_c)
+{
+ struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
+ int patched_viewport_height = 0;
+ struct dc_debug_options *debug = &hubp->ctx->dc->debug;
+
+ REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
+ PRI_VIEWPORT_WIDTH, viewport->width,
+ PRI_VIEWPORT_HEIGHT, viewport->height);
+
+ REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
+ PRI_VIEWPORT_X_START, viewport->x,
+ PRI_VIEWPORT_Y_START, viewport->y);
+
+ /*for stereo*/
+ REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
+ SEC_VIEWPORT_WIDTH, viewport->width,
+ SEC_VIEWPORT_HEIGHT, viewport->height);
+
+ REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
+ SEC_VIEWPORT_X_START, viewport->x,
+ SEC_VIEWPORT_Y_START, viewport->y);
+
+ /*
+* Work around for underflow issue with NV12 + rIOMMU translation
+* + immediate flip. This will cause hubp underflow, but will not
+* be user visible since underflow is in blank region
+*/
+ patched_viewport_height = viewport_c->height;
+ if (viewport_c->height != 0 && debug->nv12_iflip_vm_wa) {
+ int pte_row_height = 0;
+ int pte_rows = 0;
+
+ REG_GET(DCHUBP_REQ_SIZE_CONFIG,
+ PTE_ROW_HEIGHT_LINEAR, &pte_row_height);
+
+ pte_row_height = 1 << (pte_row_height + 3);
+ pte_rows = (viewport_c->height + pte_row_height - 1) /
pte_row_height;
+ patched_viewport_height = pte_rows * pte_row_height + 3;
+ }
+
+
+ /* DC supports NV12 only at the moment */
+ REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
+ PRI_VIEWPORT_WIDTH_C, viewport_c->width,
+ PRI_VIEWPORT_HEIGHT_C, patched_viewport_height);
+
+ REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
+ PRI_VIEWPORT_X_START_C, viewport_c->x,
+ PRI_VIEWPORT_Y_START_C, viewport_c->y);
+
+ REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,
+ SEC_VIEWPORT_WIDTH_C, viewport_c->width,
+ SEC_VIEWPORT_HEIGHT_C, patched_viewport_height);
+
+ REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,
+ SEC_VIEWPORT_X_START_C, viewport_c->x,
+ SEC_VIEWPORT_Y_START_C, viewport_c->y);
+}
+
void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,
struct vm_system_aperture_param *apt)
{
@@ -211,7 +274,7 @@ static struct hubp_funcs dcn21_hubp_funcs = {
.hubp_set_vm_system_aperture_settings =
hubp21_set_vm_system_aperture_settings,
.set_blank = hubp1_set_blank,
.dcc_control = hubp1_dcc_control,
- .mem_program_viewport = min_set_viewport,
+ .mem_program_viewport = hubp21_set_viewport,
.set_cursor_attributes = hubp2_cursor_set_attributes,
.set_cursor_position= hubp1_cursor_set_position,
.hubp_clk_cntl = hubp1_clk_cntl,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index b29b2c99a564e..fe0ed4c09ad0a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -847,6 +847,7 @@ static const struct dc_debug_options debug_de
[PATCH AUTOSEL 5.5 158/542] drm/amd/display: remove set but not used variable 'bp' in bios_parser.c
From: zhengbin
[ Upstream commit 7e30402bed151fc6222baafe5aa1abe3e65c3065 ]
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c: In function
bios_get_board_layout_info:
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c:2743:22: warning: variable bp
set but not used [-Wunused-but-set-variable]
It is introduced by commit 1eeedbcc20d6 ("drm/amd/display:
get board layout for edid emulation"), but never used,
so remove it.
Reviewed-by: Harry Wentland
Reported-by: Hulk Robot
Signed-off-by: zhengbin
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index 823843cd26133..c34797cb4d2d3 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -2739,7 +2739,6 @@ static enum bp_result bios_get_board_layout_info(
struct board_layout_info *board_layout_info)
{
unsigned int i;
- struct bios_parser *bp;
enum bp_result record_result;
const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
@@ -2748,7 +2747,6 @@ static enum bp_result bios_get_board_layout_info(
0, 0
};
- bp = BP_FROM_DCB(dcb);
if (board_layout_info == NULL) {
DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
return BP_RESULT_BADINPUT;
--
2.20.1
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[PATCH AUTOSEL 5.5 155/542] drm/amdkfd: remove set but not used variable 'top_dev'
From: zhengbin
[ Upstream commit d191bd678153307573d615bb42da4fcca19fe477 ]
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/amdkfd/kfd_iommu.c: In function kfd_iommu_device_init:
drivers/gpu/drm/amd/amdkfd/kfd_iommu.c:65:30: warning: variable top_dev set but
not used [-Wunused-but-set-variable]
Reported-by: Hulk Robot
Fixes: 1ae99eab34f9 ("drm/amdkfd: Initialize HSA_CAP_ATS_PRESENT capability in
topology codes")
Signed-off-by: zhengbin
Reviewed-by: Felix Kuehling
Signed-off-by: Felix Kuehling
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdkfd/kfd_iommu.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
b/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
index 193e2835bd4d2..8d871514671eb 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_iommu.c
@@ -62,9 +62,6 @@ int kfd_iommu_device_init(struct kfd_dev *kfd)
struct amd_iommu_device_info iommu_info;
unsigned int pasid_limit;
int err;
- struct kfd_topology_device *top_dev;
-
- top_dev = kfd_topology_device_by_id(kfd->id);
if (!kfd->device_info->needs_iommu_device)
return 0;
--
2.20.1
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[PATCH AUTOSEL 5.5 151/542] drm/gma500: remove set but not used variable 'htotal'
From: zhengbin
[ Upstream commit dfa703b6f91818fa9f652c00e3589c104c518930 ]
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/gma500/oaktrail_hdmi.c: In function htotal_calculate:
drivers/gpu/drm/gma500/oaktrail_hdmi.c:160:6: warning: variable htotal set but
not used [-Wunused-but-set-variable]
It is introduced by commit 39ec748f7174 ("gma600: Enable HDMI support"),
but never used, so remove it.
Reported-by: Hulk Robot
Signed-off-by: zhengbin
Signed-off-by: Daniel Vetter
Link:
https://patchwork.freedesktop.org/patch/msgid/1573828027-122323-2-git-send-email-zhengbi...@huawei.com
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/gma500/oaktrail_hdmi.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/gma500/oaktrail_hdmi.c
b/drivers/gpu/drm/gma500/oaktrail_hdmi.c
index f4c520893ceb6..f4370232767d3 100644
--- a/drivers/gpu/drm/gma500/oaktrail_hdmi.c
+++ b/drivers/gpu/drm/gma500/oaktrail_hdmi.c
@@ -159,9 +159,7 @@ static void oaktrail_hdmi_audio_disable(struct drm_device
*dev)
static unsigned int htotal_calculate(struct drm_display_mode *mode)
{
- u32 htotal, new_crtc_htotal;
-
- htotal = (mode->crtc_hdisplay - 1) | ((mode->crtc_htotal - 1) << 16);
+ u32 new_crtc_htotal;
/*
* 1024 x 768 new_crtc_htotal = 0x1024;
--
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[PATCH AUTOSEL 5.5 139/542] drm/amdgpu: remove 4 set but not used variable in amdgpu_atombios_get_connector_info_from_object_table
From: yu kuai
[ Upstream commit bae028e3e521e8cb8caf2cc16a455ce4c55f2332 ]
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c: In function
'amdgpu_atombios_get_connector_info_from_object_table':
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:376:26: warning: variable
'grph_obj_num' set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:376:13: warning: variable
'grph_obj_id' set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:341:37: warning: variable
'con_obj_type' set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:341:24: warning: variable
'con_obj_num' set but not used [-Wunused-but-set-variable]
They are never used, so can be removed.
Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
Signed-off-by: yu kuai
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 19 ++-
1 file changed, 2 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index 72232fccf61a7..be6d0cfe41aec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -338,17 +338,9 @@ bool
amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *
path_size += le16_to_cpu(path->usSize);
if (device_support & le16_to_cpu(path->usDeviceTag)) {
- uint8_t con_obj_id, con_obj_num, con_obj_type;
-
- con_obj_id =
+ uint8_t con_obj_id =
(le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
>> OBJECT_ID_SHIFT;
- con_obj_num =
- (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
- >> ENUM_ID_SHIFT;
- con_obj_type =
- (le16_to_cpu(path->usConnObjectId) &
-OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
/* Skip TV/CV support */
if ((le16_to_cpu(path->usDeviceTag) ==
@@ -373,14 +365,7 @@ bool
amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *
router.ddc_valid = false;
router.cd_valid = false;
for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
j++) {
- uint8_t grph_obj_id, grph_obj_num,
grph_obj_type;
-
- grph_obj_id =
- (le16_to_cpu(path->usGraphicObjIds[j]) &
-OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
- grph_obj_num =
- (le16_to_cpu(path->usGraphicObjIds[j]) &
-ENUM_ID_MASK) >> ENUM_ID_SHIFT;
+ uint8_t grph_obj_type=
grph_obj_type =
(le16_to_cpu(path->usGraphicObjIds[j]) &
OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
--
2.20.1
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[PATCH AUTOSEL 5.5 149/542] drm/amdgpu: remove set but not used variable 'invalid'
From: yu kuai
[ Upstream commit 9e089a29c696d86d26e79737bafbce94738fb462 ]
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c: In function
‘amdgpu_amdkfd_evict_userptr’:
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c:1665:6: warning:
variable ‘invalid’ set but not used [-Wunused-but-set-variable]
'invalid' is never used, so can be removed. Thus 'atomic_inc_return'
can be replaced as 'atomic_inc'
Fixes: 5ae0283e831a ("drm/amdgpu: Add userptr support for KFD")
Signed-off-by: yu kuai
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 888209eb8cecd..8cf2e8f647065 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1674,10 +1674,10 @@ int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem,
struct mm_struct *mm)
{
struct amdkfd_process_info *process_info = mem->process_info;
- int invalid, evicted_bos;
+ int evicted_bos;
int r = 0;
- invalid = atomic_inc_return(&mem->invalid);
+ atomic_inc(&mem->invalid);
evicted_bos = atomic_inc_return(&process_info->evicted_bos);
if (evicted_bos == 1) {
/* First eviction, stop the queues */
--
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[PATCH AUTOSEL 5.5 152/542] drm/gma500: remove set but not used variable 'error'
From: zhengbin
[ Upstream commit a5eb29a9d2fc03d07af7d02f6c2e7ae1e6d985f9 ]
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/gma500/psb_irq.c: In function psb_sgx_interrupt:
drivers/gpu/drm/gma500/psb_irq.c:210:6: warning: variable error set but not
used [-Wunused-but-set-variable]
It is introduced by commit 64a4aff283ac ("drm/gma500:
Add support for SGX interrupts"), but never used, so remove it.
Reported-by: Hulk Robot
Signed-off-by: zhengbin
Signed-off-by: Daniel Vetter
Link:
https://patchwork.freedesktop.org/patch/msgid/1573828027-122323-3-git-send-email-zhengbi...@huawei.com
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/gma500/psb_irq.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/gma500/psb_irq.c b/drivers/gpu/drm/gma500/psb_irq.c
index e6265fb85626e..dc6a73ab9777c 100644
--- a/drivers/gpu/drm/gma500/psb_irq.c
+++ b/drivers/gpu/drm/gma500/psb_irq.c
@@ -194,7 +194,6 @@ static void psb_sgx_interrupt(struct drm_device *dev, u32
stat_1, u32 stat_2)
{
struct drm_psb_private *dev_priv = dev->dev_private;
u32 val, addr;
- int error = false;
if (stat_1 & _PSB_CE_TWOD_COMPLETE)
val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS);
@@ -229,7 +228,6 @@ static void psb_sgx_interrupt(struct drm_device *dev, u32
stat_1, u32 stat_2)
DRM_ERROR("\tMMU failing address is 0x%08x.\n",
(unsigned int)addr);
- error = true;
}
}
--
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[PATCH AUTOSEL 5.5 153/542] drm/gma500: remove set but not used variable 'is_hdmi', 'is_crt'
From: zhengbin
[ Upstream commit 834c43a97f341d319aa7b74099bbce2c4e75bc72 ]
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/gma500/cdv_intel_display.c: In function cdv_intel_crtc_mode_set:
drivers/gpu/drm/gma500/cdv_intel_display.c:594:7: warning: variable is_hdmi set
but not used [-Wunused-but-set-variable]
drivers/gpu/drm/gma500/cdv_intel_display.c: In function cdv_intel_crtc_mode_set:
drivers/gpu/drm/gma500/cdv_intel_display.c:593:7: warning: variable is_crt set
but not used [-Wunused-but-set-variable]
They are not used since commit acd7ef927e06 ("gma500:
Update the Cedarview clock handling")
Reported-by: Hulk Robot
Signed-off-by: zhengbin
Signed-off-by: Daniel Vetter
Link:
https://patchwork.freedesktop.org/patch/msgid/1573828027-122323-4-git-send-email-zhengbi...@huawei.com
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/gma500/cdv_intel_display.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/gma500/cdv_intel_display.c
b/drivers/gpu/drm/gma500/cdv_intel_display.c
index 8b784947ed3b9..334a203d62555 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
@@ -582,8 +582,8 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
struct gma_clock_t clock;
u32 dpll = 0, dspcntr, pipeconf;
bool ok;
- bool is_crt = false, is_lvds = false, is_tv = false;
- bool is_hdmi = false, is_dp = false;
+ bool is_lvds = false, is_tv = false;
+ bool is_dp = false;
struct drm_mode_config *mode_config = &dev->mode_config;
struct drm_connector *connector;
const struct gma_limit_t *limit;
@@ -607,10 +607,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
is_tv = true;
break;
case INTEL_OUTPUT_ANALOG:
- is_crt = true;
- break;
case INTEL_OUTPUT_HDMI:
- is_hdmi = true;
break;
case INTEL_OUTPUT_DISPLAYPORT:
is_dp = true;
--
2.20.1
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[PATCH AUTOSEL 5.5 156/542] drm/amd/display: remove set but not used variable 'old_plane_crtc'
From: zhengbin
[ Upstream commit d3b65841b31c0192f997e0f9bc64dccbfaa97bcc ]
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c: In function
dm_determine_update_type_for_commit:
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:6516:36: warning: variable
old_plane_crtc set but not used [-Wunused-but-set-variable]
It is introduced by commit a87fa9938749 ("drm/amd/display:
Build stream update and plane updates in dm"), but never used,
so remove it.
Reviewed-by: Harry Wentland
Reported-by: Hulk Robot
Signed-off-by: zhengbin
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 803e59d974111..ce57bfde2302b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7265,7 +7265,7 @@ dm_determine_update_type_for_commit(struct
amdgpu_display_manager *dm,
int i, j, num_plane, ret = 0;
struct drm_plane_state *old_plane_state, *new_plane_state;
struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
- struct drm_crtc *new_plane_crtc, *old_plane_crtc;
+ struct drm_crtc *new_plane_crtc;
struct drm_plane *plane;
struct drm_crtc *crtc;
@@ -7311,7 +7311,6 @@ dm_determine_update_type_for_commit(struct
amdgpu_display_manager *dm,
uint64_t tiling_flags;
new_plane_crtc = new_plane_state->crtc;
- old_plane_crtc = old_plane_state->crtc;
new_dm_plane_state = to_dm_plane_state(new_plane_state);
old_dm_plane_state = to_dm_plane_state(old_plane_state);
--
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[PATCH AUTOSEL 5.5 140/542] drm/amdgpu: remove set but not used variable 'dig_connector'
From: yu kuai
[ Upstream commit 5bea7fedb7fe4d5e6d3ba9f385dd3619fb004ce7 ]
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/amdgpu/atombios_dp.c: In function
‘amdgpu_atombios_dp_get_panel_mode’:
drivers/gpu/drm/amd/amdgpu/atombios_dp.c:364:36: warning: variable
‘dig_connector’ set but not used [-Wunused-but-set-variable]
It is never used, so can be removed.
Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
Signed-off-by: yu kuai
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
index 6858cde9fc5d3..94265306ab11f 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
@@ -361,7 +361,6 @@ int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder
*encoder,
struct drm_connector *connector)
{
struct amdgpu_connector *amdgpu_connector =
to_amdgpu_connector(connector);
- struct amdgpu_connector_atom_dig *dig_connector;
int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
u16 dp_bridge =
amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector);
u8 tmp;
@@ -369,8 +368,6 @@ int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder
*encoder,
if (!amdgpu_connector->con_priv)
return panel_mode;
- dig_connector = amdgpu_connector->con_priv;
-
if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
/* DP bridge chips */
if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
--
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[PATCH AUTOSEL 5.5 143/542] drm/amdgpu: remove set but not used variable 'mc_shared_chmap'
From: yu kuai
[ Upstream commit e98042db2cb8d0b728cd76e05b9c2e1c84b7f72b ]
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c: In function
‘gfx_v8_0_gpu_early_init’:
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:1713:6: warning: variable
‘mc_shared_chmap’ set but not used [-Wunused-but-set-variable]
Fixes: 0bde3a95eaa9 ("drm/amdgpu: split gfx8 gpu init into sw and hw parts")
Signed-off-by: yu kuai
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 52a647d7022d2..cfc1403fc855a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1677,7 +1677,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct
amdgpu_device *adev)
static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
{
u32 gb_addr_config;
- u32 mc_shared_chmap, mc_arb_ramcfg;
+ u32 mc_arb_ramcfg;
u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
u32 tmp;
int ret;
@@ -1817,7 +1817,6 @@ static int gfx_v8_0_gpu_early_init(struct amdgpu_device
*adev)
break;
}
- mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
--
2.20.1
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[PATCH AUTOSEL 5.5 147/542] drm/amdgpu: remove set but not used variable 'amdgpu_connector'
From: yu kuai
[ Upstream commit 4f2922d12d6c63d0f4aa4e859ad95aee6d0d4ea0 ]
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c: In function
‘amdgpu_display_crtc_scaling_mode_fixup’:
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:693:27: warning: variable
‘amdgpu_connector’ set but not used [-Wunused-but-set-variable]
Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
Signed-off-by: yu kuai
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 3cadb0b76f221..4e699071d1443 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -690,7 +690,6 @@ bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc
*crtc,
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
struct amdgpu_encoder *amdgpu_encoder;
struct drm_connector *connector;
- struct amdgpu_connector *amdgpu_connector;
u32 src_v = 1, dst_v = 1;
u32 src_h = 1, dst_h = 1;
@@ -702,7 +701,6 @@ bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc
*crtc,
continue;
amdgpu_encoder = to_amdgpu_encoder(encoder);
connector = amdgpu_get_connector_for_encoder(encoder);
- amdgpu_connector = to_amdgpu_connector(connector);
/* set scaling */
if (amdgpu_encoder->rmx_type == RMX_OFF)
--
2.20.1
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[PATCH AUTOSEL 5.5 142/542] drm/amdgpu: remove always false comparison in 'amdgpu_atombios_i2c_process_i2c_ch'
From: yu kuai
[ Upstream commit 220ac8d1444054ade07ce14498fcda266410f90e ]
Fixes gcc '-Wtype-limits' warning:
drivers/gpu/drm/amd/amdgpu/atombios_i2c.c: In function
‘amdgpu_atombios_i2c_process_i2c_ch’:
drivers/gpu/drm/amd/amdgpu/atombios_i2c.c:79:11: warning: comparison is
always false due to limited range of data type [-Wtype-limits]
'num' is 'u8', so it will never be greater than 'TOM_MAX_HW_I2C_READ',
which is defined as 255. Therefore, the comparison can be removed.
Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
Signed-off-by: yu kuai
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/atombios_i2c.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
index 980c363b1a0ae..b4cc7c55fa16f 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c
@@ -76,11 +76,6 @@ static int amdgpu_atombios_i2c_process_i2c_ch(struct
amdgpu_i2c_chan *chan,
}
args.lpI2CDataOut = cpu_to_le16(out);
} else {
- if (num > ATOM_MAX_HW_I2C_READ) {
- DRM_ERROR("hw i2c: tried to read too many bytes (%d vs
255)\n", num);
- r = -EINVAL;
- goto done;
- }
args.ucRegIndex = 0;
args.lpI2CDataOut = 0;
}
--
2.20.1
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[PATCH AUTOSEL 5.5 141/542] drm/amdgpu: remove set but not used variable 'dig'
From: yu kuai
[ Upstream commit d1d09dc417826f5a983e0f4f212f227beeb65e29 ]
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/amdgpu/atombios_dp.c: In function
‘amdgpu_atombios_dp_link_train’:
drivers/gpu/drm/amd/amdgpu/atombios_dp.c:716:34: warning: variable ‘dig’
set but not used [-Wunused-but-set-variable]
Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
Signed-off-by: yu kuai
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
index 94265306ab11f..ea702a64f8074 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
@@ -710,7 +710,6 @@ void amdgpu_atombios_dp_link_train(struct drm_encoder
*encoder,
struct drm_device *dev = encoder->dev;
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
- struct amdgpu_encoder_atom_dig *dig;
struct amdgpu_connector *amdgpu_connector;
struct amdgpu_connector_atom_dig *dig_connector;
struct amdgpu_atombios_dp_link_train_info dp_info;
@@ -718,7 +717,6 @@ void amdgpu_atombios_dp_link_train(struct drm_encoder
*encoder,
if (!amdgpu_encoder->enc_priv)
return;
- dig = amdgpu_encoder->enc_priv;
amdgpu_connector = to_amdgpu_connector(connector);
if (!amdgpu_connector->con_priv)
--
2.20.1
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